STM32F373xx device limitations
Contents
1. Links to silicon limitations Revision B Section 2 6 1 10 bit Slave mode wrong direction bit value after Read A header reception Section 2 6 2 10 bit combined with 7 bit Slave mode ADDCODE may N indicate wrong slave address detection Section 2 6 3 Wakeup frames may not wake up the MCU when STOP A Section 2 6 12C mode entry follows enabling 12C peripheral limitations Section 2 6 4 Wrong behaviors in Stop mode when wakeup from Stop a ae A mode is disabled in 12C Section 2 6 5 Wakeup frame may not wakeup from STOP if tHD STA is N close to startup time Section 2 6 6 Wrong data sampling when data set up time tSU DAT is A smaller than one I2CCLK period Section 2 7 GPIO Section 2 7 1 GPIOx locking mechanism not working properly for A peripheral limitation GPIOx_OTYPE register Section 2 8 Comparator Section 2 8 1 VREFINT scaler startup time from power down parameter N peripheral limitation degradation 3 8 20 DoclD022714 Rev 4 STM32F373xx STM32F373xx silicon limitations 2 1 2 1 1 Note 3 System limitations Wakeup sequence from Standby mode when using more than one wakeup source Description The various wakeup sources are logically OR ed in front of the rising edge detector which generates the wakeup flag WUF The WUF needs to be cleared prior to Standby mode entry otherwise the MCU wakes up immediately If one of the configured wakeup sources is kept high duri2. fA life augmented STM32F373xx Errata sheet STM32F373xx device limitations Silicon identification This errata sheet applies to revision B of the STMicroelectronics STM32F373xx products These families feature an ARM 32 bit Cortex M4 core for which an errata notice is also available see Section 7 for details Section 2 gives a detailed description of the product silicon limitations The full list of part numbers is shown in Table 2 The products are identifiable as shown in Table 1 e by the revision code marked below the order code on the device package e bythe last three digits of the Internal order code printed on the box label Table 1 Device identification STM32F373xx Order code Revision code marked on device B 1 The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device see the RM0313 reference manual for details on how to find the revision code 2 Refer to the device datasheet for details on how to identify the revision code on the different packages Table 2 Device summary Reference STM32F373xx Part number STM32F373C8 STM32F373R8 STM32F373V8 STM32F373CB STM32F373RB STM32F373VB STM32F373CC STM32F373RC STM32F373VC March 2015 DoclD022714 Rev 4 1 20 www st com Contents STM32F373xx Contents 1 ARM 32 bit Cortex M4 limitations ccce eee ennenen 5 1 1 Cortex M4 interrupted loads to s
3. 000000 17 2 7 1 GPIOx locking mechanism not working properly for GPIOx_OTYPE POGISION sins ka ewe hale aE Os VA A TEER 17 2 8 Comparator peripheral limitation 00000 eee 18 2 8 1 VREFINT scaler startup time from power down parameter degradation 18 3 REVISION history sass ccGcees dcekeeeee deed he sees bbeeeeee ss 19 3 DoclD022714 Rev 4 3 20 List of tables STM32F373xx List of tables Table 1 Device identification ined ada taea ea eae Gua baad dak vere ee ee 1 Table 2 Device SUMMA eeso sredin rar Erer eee eee 1 Table 3 Cortex M4 core limitations and impact on microcontroller behavior 5 Table 4 Summary of silicon limitations aaaea eee 7 Table 5 Document revision history 0 000 ec eee 19 4 20 DoclD022714 Rev 4 3 STM32F373xx ARM 32 bit Cortex M4 limitations 1 1 3 ARM 32 bit Cortex M4 limitations An errata notice of the STM32F373xx core is available from the following web address http infocenter arm com All the described limitations are minor and related to the revision r0p1 v1 of the Cortex M4 core Table 3 summarizes these limitations and their implications on the behavior of STM32F373xx devices Table 3 Cortex M4 core limitations and impact on microcontroller behavior ARM ID ARM ARM summary of errata Impact on STM32F373xx category Interrupted loads to SP can cause erroneous 752770 CatB behavior Minor VDIV or
4. STM32F373xx silicon limitations STM32F373xx 2 6 5 Note 16 20 1 BUSY flag can be wrongly set when the MCU exits Stop mode This prevents from initiating a transfer in master mode as the START condition cannot be sent when BUSY is set 2 If clock stretching is enabled NOSTRETCH 0 the I C clock SCL may be stretched low by the I C as long as the MCU is in Stop mode This limitation may occur when the Stop mode is entered during the address phase of a transfer on the IC bus while SCL 0 Therefore the transfer may be stalled as long as the MCU is in Stop mode The probability of the occurrence depends also on the timings configuration the peripheral clock frequency and the IC bus frequency These behaviors can occur in Slave mode and in Master mode in a multi master topology Workaround Disable the 1 C PE 0 before entering Stop mode and re enable it in Run mode Wakeup frame may not wakeup from STOP if typsta is close to startup time Description Under specific conditions and if the TRT condition hold time tHp sta duration is very close to the HSI startup time duration the IC is not able to detect the address match and to wake up the MCU from STOP To see the limitation one of the conditions listed below has to be met e Timeout detection is enabled TIMOUTEN 1 or TEXTEN 1 and the frame before the wakeup frame is abnormally finished due to a IC Timeout detection TIMOUT 1 e The slave arbitration is lost duri
5. after the repeated start condition to enter Slave transmission mode As a result the DIR bit is incorrect in Slave mode under specific conditions Workaround If possible do not use these four values as 10 bit addresses in Slave mode e OA1 9 0 0011110001 e OA1 9 0 0111110011 e OA1 9 0 1011110101 e OA1 9 0 1111110111 If one of these addresses is the 12C slave address the DIR bit must not be used in the FW 10 bit combined with 7 bit Slave mode ADDCODE may indicate wrong slave address detection Description Under specific conditions the ADDCODE Address match code in the I2C_ISR register indicates a wrong slave address 3 DoclD022714 Rev 4 STM32F373xx STM32F373xx silicon limitations 2 6 3 2 6 4 3 To see the limitation all the following conditions have to be fulfilled e The IC slave address OA1 is enabled and configured in 10 bit mode OA1EN 1 and OA1MODE 1 e Another 7 bit slave address is enabled and the bits 1 to 7 of the 10 bit slave address OA1 are equal to the 7 bit slave address i e one of the configurations below is set OA2EN 1 and OA2MSK 0 and OA1 7 1 OA2 7 1 OA2EN 1 and OA2MSK 1 and OA1 7 2 OA2 7 2 OA2EN 1 and OA2MSK 2 and OA1 7 3 OA2 7 3 OA2EN 1 and OA2MSK 3 and OA1 7 4 OA2 7 4 OA2EN 1 and OA2MSK 4 and OA1 7 5 OA2 7 5 OA2EN 1 and OA2MSK 5 and OA1 7 6 OA2 7 6 OAZ2EN 1 and OA2MSK 6 and OA1 7 OA2
6. e 50 ns in Fast mode Plus The I2C SDA line is not correctly sampled when tsy pat is smaller than one I2CCLK l2C clock period the previous SDA value is sampled instead of the current one This can result in a wrong slave address reception a wrong received data byte or a wrong received acknowledge bit Workaround Increase the I2CCLK frequency to get I2CCLK period smaller than the transmitter minimum data set up time Or if it is possible increase the transmitter minimum data set up time GPIO peripheral limitation GPIOx locking mechanism not working properly for GPIOx_OTYPE register Description Locking of GPIOx_OTYPER i with i 15 8 depends from setting of GPIOx_LCKR i 8 and not from GPIOx_LCKR i GPIOx_LCKRIi 8 is locking GPIOx_OTYPER i together with GPIOx_OTYPERIi 8 It is not possible to lock GPIOx_OTYPER i with i 15 8 without locking also GPIOx_OTYPERIi 8 Workaround The only way to lock GPIOxOYTYPE i with i 15 8 is to lock also GPIOxOYTYPE i 8 DoclD022714 Rev 4 17 20 STM32F373xx silicon limitations STM32F373xx 2 8 2 8 1 18 20 Comparator peripheral limitation Vrerint scaler startup time from power down parameter degradation Description The Vrerint scaler is an embedded voltage follower providing the Vpgerint Or its fractions 1 2 1 4 or 3 4 to the comparator input The maximum Vrerint scaler startup time ts sc max is not as expected for the first activation of the Verrin
7. pointers misalignment on the reception FIFO The worst case is the Slave mode if the external master is running in continuous mode without clock interruption between two data transfers In full duplex Master mode it runs correctly if the SPI is working in non continuous mode meaning that the SPI is transferring two data then stopping the data transmission until the two data received are read back before sending the next two data Conditions to see this limitation e Packing mode is used e SPI master in continuous mode or Slave worst case e Full duplex or receiver mode If the packing mode is used in reception mode the FIFO reception threshold has to be set to 16 bit Under those setting and conditions when a read operation half word to read two data in one APB access takes place while the FIFO level is equal to 3 4 new data came before the two first ones are read the 16 bit read decreases the FIFO level to 1 4 The RXNE flag is not de asserted clear condition on FIFO empty event and a new request is present to read back two data although the FIFO contains only one data Read and write pointers in the FIFO become misaligned and the data is corrupted The packing mode in reception has to be discarded when the conditions described above are met It means that the reception FIFO requests that the data is read back until the FIFO content is empty It also means that for short data frame the worst case being the 4 bit data size if
8. 7 OAZ2EN 1 and OA2MSK 7 GCEN 1 and OA1 7 1 060000000 ALERTEN 1 and OA1 7 1 0b0001100 SMBDEN 1 and OA1 7 1 061100001 SMBHEN 1 and OA1 7 1 060001000 e The master starts a transfer addressed to the 10 bit slave address OA1 As a result after the address reception the ADDCODE value is OA1 7 1 equal to the 7 bit slave address instead of 0611110 amp OA1 9 8 Workaround None If several slave address are enabled mixing 10 bit and 7 bit addresses the 10 bit slave address OA1 7 1 must not be equal to the 7 bit slave address Wakeup frames may not wake up the MCU when STOP mode entry follows enabling I2C Description If the I2C is enabled PE 1 and wakeup from STOP is enabled in 12C WUPEN 1 while a transfer occurs on the IC bus and STOP mode is entered during the same transfer while SCL 0 the I C is not able to detect the first following START condition This means that if the IC is addressed it will not wake up the MCU and this address is not acknowledged Workaround After enabling the 12C PE is set to 1 wait for a temporization before entering STOP mode to ensure that the eventual on going frame is finished Wrong behaviors in Stop mode when wakeup from Stop mode is disabled in I2C Description When wakeup from Stop mode is disabled in 1 C WUPEN 0 and the MCU enters Stop mode while a transfer is on going on the bus some wrong behaviors may happen DoclD022714 Rev 4 15 20
9. VSQRT instructions might not complete 16924 Pate correctly when very short ISRs are used Minor Cortex M4 interrupted loads to stack pointer can cause erroneous behavior Description An interrupt occurring during the data phase of a single word load to the stack pointer SP R13 can cause an erroneous behavior of the device In addition returning from the interrupt results in the load instruction being executed an additional time For all the instructions performing an update of the base register the base register is erroneously updated on each execution resulting in the stack pointer being loaded from an incorrect memory location The instructions affected by this limitation are the following e LDR SP Rn imm e LDR SP Rn imm e LDR SP Rn imm e LDR SP Rn e LDR SP Rn Rm Workaround As of today no compiler generates these particular instructions This limitation can only occur with hand written assembly code Both issues can be solved by replacing the direct load to the stack pointer by an intermediate load to a general purpose register followed by a move to the stack pointer Example Replace LDR SP RO by LDR R2 RO MOV SP R2 DoclD022714 Rev 4 5 20 ARM 32 bit Cortex M4 limitations STM32F373xx 1 2 6 20 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Description On Cortex M4 with FPU core 14 cycles are
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11. making sure that the TC flag is set nRTS is active while RE or UE 0 Description The nRTS line is driven low as soon as RTSE bit is set even if the USART is disabled UE 0 or the receiver is disabled RE 0 i e not ready to receive data Workaround Configure the I O used for nRTS as alternate function after setting the UE and RE bits DoclD022714 Rev 4 11 20 STM32F373xx silicon limitations STM32F373xx 2 4 2 4 1 2 5 2 5 1 12 20 SDADC peripheral limitation SDADC incorrect gain amplification in single ended zero reference mode for 16x and 32x gains Description When using the Single ended mode zero reference for 16x and 32x gains the device subtracts incorrectly the analog offset when performing the digital multiplication for 2x and 4x respectively while using analog gain 8x and the results obtained in Single ended mode zero reference for gains 16x and 32x will be incorrect Workaround Use Single ended offset mode instead of Single ended mode zero reference for gains 16x and 32x This mode also features better dynamic characteristics for these gains SPI I2S peripheral limitations Packing mode limitation at reception Description When the SPI is configured in the short data frame mode the packing mode on the reception side may not be usable Using this feature may generate a wrong RXNE event to an Interrupt or DMA request and so the software may read back inconsistent data with FIFO
12. required to execute a VDIV or VSQRT instruction This limitation is present when the following conditions are met e AVDIV or VSQRT is executed e The destination register for VDIV or VSQRT is one of s0 s15 e An interrupt occurs and is taken e The ISR being executed does not contain a floating point instruction e 14 cycles after the VDIV or VSQRT is executed an interrupt return is executed In this case if there are only one or two instructions inside the interrupt service routine then the VDIV or VQSRT instruction does not complete correctly and the register bank and FPSCR are not updated meaning that these registers hold incorrect out of date data Workarounds Two workarounds are applicable e Disable lazy context save of floating point state by clearing LSPEN to 0 bit 30 of the FPCCR at address 0xXE000EF34 e Ensure that every ISR contains more than 2 instructions in addition to the exception return instruction DoclD022714 Rev 4 3 STM32F373xx STM32F373xx silicon limitations 2 STM32F373xx silicon limitations Table 4 gives quick references to all documented limitations The legend for Table 4 is as follows A workaround available N no workaround available P partial workaround available and grayed fixed Table 4 Summary of silicon limitations Links to silicon limitations Revision B Section 2 1 1 Wakeup sequence from Standby mode
13. the software or the DMA is not able to manage the high data rate when the SPI is running full speed an Overrun condition may occur at regular intervals DoclD022714 Rev 4 ky STM32F373xx STM32F373xx silicon limitations 2 5 2 2 5 3 3 Workaround There is no workaround The only way to avoid this overrun condition would be to slow down the SPI communication clock frequency in order to let time to the DMA best case to read back data without any FIFO full condition SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 1 Description SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 7 In the following conditions e SPlis slave or master e Full duplex or simplex mode is used e CRC feature is enabled e SPI is configured to manage data transfers by software interrupt or polling e a peripheral mapped on the same DMA channel as the SPI is doing DMA transfers the CRC may be frozen before the CRCNEXT bit is written resulting ina CRC error Workaround If the application allows it use the DMA for SPI transfers In I2S slave mode WS level must be set by the external master when enabling the I2S Description In slave mode the WS signal level is used only to start the communication If
14. when using more A than one wakeup source Serer sete Sete Section 2 1 2 Delay after an RCC peripheral clock enabling A limitations Section 2 1 3 Full JTAG configuration without NJTRST pin cannot be A used ee SUR Section 2 2 1 CRC corrupted when even polynomial is used A limitation Section 2 3 1 Communication parameters reprogramming after ATR in A Smartcard mode when SCLK is used to clock the card Section 2 3 2 Last byte written in TDR might not be transmitted if TE is ae A cleared just after writing in TDR zeuon e a Fad Section 2 3 3 Start bit detected too soon when sampling for NACK signal peripheral limitations N from the smartcard Section 2 3 4 Break request can prevent the Transmission Complete flag A TC from being set Section 2 3 5 nRTS is active while RE or UE 0 A Section 2 4 SDADC Section 2 4 1 SDADC incorrect gain amplification in single ended zero A P A peripheral limitation reference mode for 16x and 32x gains Section 2 5 1 Packing mode limitation at reception N Section 2 5 2 SPI CRC may be corrupted when a peripheral connected to Section 2 5 SPI I2S the same DMA channel of the SPI is under DMA transaction near the end A peripheral limitations of transfer or end of transfer 1 Section 2 5 3 In 12S slave mode WS level must be set by the external A master when enabling the 12S ky DoclD022714 Rev 4 7 20 STM32F373xx silicon limitations STM32F373xx Table 4 Summary of silicon limitations continued
15. in amplification in single ended zero reference mode for 16x and 32x gainS 0 ee 12 2 5 SPI 2S peripheral limitations 000000 eee ee 12 2 5 1 Packing mode limitation at reception 0 0 00000 e eee eee 12 2 5 2 SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 17 2 auauna naana 13 2 5 3 In 12S slave mode WS level must be set by the external master when enabling the 128 seek eee dee eee ee ee ed ee eee eee eee ee 13 2 6 2c peripheral limitations 000 cece eee 14 2 6 1 10 bit Slave mode wrong direction bit value after Read header FECEPUION sire niania ia achat doe aa Rib a a boda h aia ah aoa ede 14 2 20 DoclD022714 Rev 4 ky STM32F373xx Contents 2 6 2 10 bit combined with 7 bit Slave mode ADDCODE may indicate wrong slave address detection 0 00 c eee ee eee 14 2 6 3 Wakeup frames may not wake up the MCU when STOP mode entry follows enabling PC ordra dante tadiavedhetghonnahaet aes 15 2 6 4 Wrong behaviors in Stop mode when wakeup from Stop mode is disabled in IC 2 neta tceteps as hetaw dow aaa 15 2 6 5 Wakeup frame may not wakeup from STOP if typsta is close to startup time 20 000 eee 16 2 6 6 Wrong data sampling when data set up time tsy pat is smaller than one I2CCLK period 000 cc eee ee eee 17 2 7 GPIO peripheral limitation 0
16. mmary of silicon limitations Added package UFBGA100 in Appendix A Revision code on device marking STM32F378xx previously STM32F383xx devices are now covered by a separate errata sheet Added Section 1 2 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Section 2 1 3 Full JTAG configuration without NJTRST pin cannot be used Section 2 6 6 Wrong data sampling when data set up time tSU DAT is smaller than one I2CCLK period 02 Mar 2015 4 Section 2 3 3 Start bit detected too soon when sampling for NACK signal from the smartcard Section 2 3 4 Break request can prevent the Transmission Complete flag TC from being set Section 2 3 5 nRTS is active while RE or UE 0 Section 2 1 2 Delay after an RCC peripheral clock enabling Section 2 8 Comparator peripheral limitation DoclD022714 Rev 4 19 20 STM32F373xx IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST
17. n limitations STM32F373xx 2 1 3 2 2 2 2 1 2 3 2 3 1 2 3 2 10 20 Full JTAG configuration without NJTRST pin cannot be used Description When using the JTAG debug port in debug mode the connection with the debugger is lost if the NJTRST pin PB4 is used as a GPIO Only the 4 wire JTAG port configuration is impacted Workaround Use the SWD debug port instead of the full 4 wire JTAG port CRC limitation CRC corrupted when even polynomial is used Description When selecting an even polynomial the CRC is corrupted Workaround Use an odd polynomial USART peripheral limitations Communication parameters reprogramming after ATR in Smartcard mode when SCLK is used to clock the card Description If the USART is used in Smartcard mode and the card cannot use the default communication parameters after Answer To Reset and doesn t support clock stop it is not possible to use SCLK to clock the card This is due to the fact that the USART and its clock output must be disabled while reprogramming some of the parameters Workaround Use another clock source to clock the card e g a timer output programmed to the desired clock frequency Last byte written in TDR might not be transmitted if TE is cleared just after writing in TDR Description If the USART clock source is slow for example LSE and TE bit is cleared immediately after the last write to TDR the last byte will probably not be transmitted Wo
18. ng the clearing of the WUF by setting the CWUF bit it may mask further wakeup events on the input of the edge detector As a consequence the MCU might not be able to wake up from Standby mode Workaround To avoid this problem the following sequence should be applied before entering Standby mode e Disable all used wakeup sources e Clear all related wakeup flags e Re enable all used wakeup sources e Enter Standby mode Be aware that when applying this workaround if one of the wakeup sources is still kept high the MCU will enter Standby mode but then it wakes up immediately generating a power reset Delay after an RCC peripheral clock enabling Description A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read write from to registers This delay depends on the peripheral mapping If peripheral is mapped on AHB the delay is 2 AHB clock cycles after the clock enable bit is set on the hardware register If peripheral is mapped on APB the delay is 2 APB clock cycles after the clock enable bit is set on the hardware register Workarounds 1 Enable the peripheral clock sometimes before the peripheral read write register is required 2 For AHB peripheral insert two dummy read to the peripheral register 3 For APB peripheral insert a dummy read to the peripheral register DoclD022714 Rev 4 9 20 STM32F373xx silico
19. ng the frame before the wakeup frame ARLO 1 e The MCU enters STOP mode while another slave is addressed after the address phase and before the STOP condition BUSY 1 e The MCU is in STOP mode and another slave is addressed before the I7C is addressed The last three conditions can occur only in a multi slave network In STOP mode the HSI is switched on by the IC when a START condition is detected SDA falling edge while SCL is high The HSI is used to receive the address HSI is switched off after the address reception if received address is not the IC slave address If one of the conditions above is met and if the SCL falling edge following the START condition occurs on the first cycle of the I2CCLK clock HSI the address reception is not correctly done and the address match wakeup interrupt is not generated Workaround e None at MCU level If the wakeup frame is not acknowledged by the I2C and if the master can program the duration of the START hold time the master should decrease or increase the START condition hold time for more than one HSI period and resend the wakeup frame 3 DoclD022714 Rev 4 STM32F373xx STM32F373xx silicon limitations 2 6 6 2 7 2 7 1 3 Wrong data sampling when data set up time tsy pat is smaller than one I2CCLK period Description The 12C bus specification and user manual specifies a minimum data set up time tsy pat at e 250ns in Standard mode e 100 ns in Fast mode
20. rkarounds 1 Wait until TXE flag is set before clearing TE bit DoclD022714 Rev 4 3 STM32F373xx STM32F373xx silicon limitations 2 3 3 2 3 4 2 3 5 3 2 Wait until TC flag is set before clearing TE bit Start bit detected too soon when sampling for NACK signal from the smartcard Description In the S07816 when a character parity error is incorrect the smartcard receiver shall transmit a NACK error signal at 10 5 0 2 etu after the character START bit falling edge In this case the USART transmitter should be able to detect correctly the NACK signal by sampling at 11 0 0 2 etu after the character START bit falling edge The USART peripheral used in smartcard mode doesn t respect the 11 0 2 etu timing and when the NACK falling edge arrives at 10 68 etu or later the USART might misinterpret this transition as a START bit even if the NACK is correctly detected Workaround None Break request can prevent the Transmission Complete flag TC from being set Description After the end of transmission of a data D1 the Transmission Complete TC flag will not be set in the following conditions e CTS hardware flow control is enabled e D1 is being transmitted e A break transfer is requested before the end of D1 transfer e nCTS is de asserted before the end of transfer of D1 Workaround If the application needs to detect the end of transfer of the data the break request should be done after
21. t scaler after powering on the device and it can be up to 1s instead of 0 2ms in worse case conditions This maximum value depends mainly on the voltage and temperature see the device datasheet for more details Workaround None 3 DoclD022714 Rev 4 STM32F373xx Revision history 3 3 Revision history Table 5 Document revision history Date Revision Changes 06 Sep 2012 1 Initial release Added Section 2 1 1 Wakeup sequence from Standby mode when using more than one wakeup source Section 2 2 1 CRC corrupted when even polynomial is used Section 2 3 2 Last byte written in TDR might not be transmitted if TE is cleared just after writing in TDR Section 2 5 2 SPI CRC may be corrupted when a peripheral 03 Oct 2013 2 connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 1 Section 2 6 5 Wakeup frame may not wakeup from STOP if tHD STA is close to startup time Modified Section 2 6 3 Wakeup frames may not wake up the MCU when STOP mode entry follows enabling 12C and Section 2 6 4 Wrong behaviors in Stop mode when wakeup from Stop mode is disabled in 12C Updated document disclaimer Added Section 2 5 3 In 12S slave mode WS level must be set by the external master when enabling the 12S Section 2 7 1 GPIOx locking mechanism not working properly for 17 Feb 2014 3 GPIOx_OTYPE register N o Updated Table 4 Su
22. tack pointer can cause erroneous behavior 0 ccc ccc ttt eee 5 1 2 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used aaununnana eee eee 6 2 STM32F373xx silicon limitations 0 00 ee eee eee eee 7 2 1 System limitations cesta elt ge ose Stim pean Roe age paca mC pace we ae Sem war acter do ecm 9 2 1 1 Wakeup sequence from Standby mode when using more than one wakeup SOUICE 2 2 2 2 ee 9 2 1 2 Delay after an RCC peripheral clock enabling 45 9 2 1 3 Full JTAG configuration without NJTRST pin cannot be used 10 2 2 CRC IIMHAION spiced e e r a a a a a H a E aa eee ea 10 2 2 1 CRC corrupted when even polynomial is used 10 2 3 USART peripheral limitations 2 00 00002 e eee eee 10 2 3 1 Communication parameters reprogramming after ATR in Smartcard mode when SCLK is used to clock the card 000 10 2 3 2 Last byte written in TDR might not be transmitted if TE is cleared just after writingin TDR 00 c eect eae 10 2 3 3 Start bit detected too soon when sampling for NACK signal from the smartcard 0 000 c eee eee 11 2 3 4 Break request can prevent the Transmission Complete flag TC from DGING SOU ited oases wwe EEES a ee ea aR A eee 11 2 3 5 nRTS is active while RE or UE 0 02 00 0000 11 2 4 SDADC peripheral limitation 000000 12 2 4 1 SDADC incorrect ga
23. the 12S in slave mode is enabled while the master is already sending the clock and the WS signal level is low for 12S protocol or high for the LSB or MSB justified mode the slave starts communicating data immediately In this case the master and slave will be desynchronized throughout the whole communication Workaround The 12S peripheral must be enabled when the external master sets the WS line at e High level when the I2S protocol is selected e Low level when the LSB or MSB justified mode is selected DoclD022714 Rev 4 13 20 STM32F373xx silicon limitations STM32F373xx 2 6 2 6 1 2 6 2 14 20 I2C peripheral limitations 10 bit Slave mode wrong direction bit value after Read header reception Description Under specific conditions the transfer direction bit DIR bit 16 of status register I2C_ISR is low instead of high after reception of the 10 bit addressing Read header Nevertheless the I C operates correctly in Slave transmission mode and data can be sent using the TXIS flag To see the limitation all the following conditions have to be fulfilled e Chas to be configured in 10 bit addressing mode OA1MODBE is set in the l2C_OAR1 register e The high LSBs of the I7C slave address are equal to the 10 bit addressing Read header value i e OA1 7 3 11110 OA1 2 OA1 9 OA1 1 OA1 8 and OA1 0 1 in the I2C_OAR1 register e The I C receives the 10 bit addressing Read header 0x 1111 0XX1
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