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1. oi ic A tib lo tg t4 t5 lob lec ted ADS M IO Valid Delay gt ADS ADSC AP A3 A31 PWT PCD BEO 7 M IO D C W R CACHE SCYC LOCK Float Delay APCHK IERR FERR Valid Delay PCHK Valid Delay BREQ HLDA Valid Delay et 1 Ojo SMIACT Valid Delay 10 HIT Valid Delay t t b a N N a 9a 9b 42 14 5 40 m intel PENTIUM PROCESSOR 75 90 100 120 Table 16 Pentium Processor 8151100 AC Specifications for 66 MHz Bus Operation Contd 3 135 lt Vcc lt 3 465V Oto 70 C C 0 pF tn ts ot re _ Me Co JEA EADS Setup Time EADS INV AP Hold Time KEN Setup Time NA WB WT Setup Time KEN WB WT Hold Time BRDY BRDYC Setup Time BRDY BRDYC Hold Time AHOLD BOFF Setup Time AHOLD BOFF Hold Time t24 EWBE HOLD PEN Setup 5 Time BUSCHK EWBE Hold Time HOLD Hold Time A20M INTR STPCLK Setup Time A20M INTR STPCLK Hold Time INIT FLUSH NMI SMI IGNNE Setup Time 5 42 8b 2 2 ajaja n n nS 2 2 3 3 2 Q 5 zy pr p 2 0 0 0 B 16 17 INIT FLUSH NMI SMI IGNNE Hold Time 130 INIT
2. 09 _ 09 ressos os _ 19596065 os 09 09 09 09 peo minout Heat Sink Heat Sink in Inches jc dcl E 11 4 10 5 87 76 84 77 78 58 49 M MEN ms 14 4 EUM Tes EUM 08 9 08 08 84 08 8 08 77 L9 o 08 0s _ 08 54 39 Without Heat Sink NOTES Heat sinks are omni directional pin aluminum alloy Features were based on standard extrusion practices for a given height Pin size ranged from 50 to 129 mils Pin spacing ranged from 93 to 175 mils Based thickness ranged from 79 to 200 mils Heat sink attach was 0 005 of thermal grease Attach thickness of 0 002 will improve performance approximately 0 3 C Watt 55 PENTIUM PROCESSOR 75 90 100 120 Ital 0 6 Heat Sink Height in 241997 14 Figure 15 Thermal Resistance vs Heatsink Height Spreader Package 0 LFM fti 100 LFM 4 200 LFM 400 LEM 600 LFM Theta ca 0 55 0 65 0 8 Heat Sink Helght in 241997 21 Figure 16 Thermal Resistance vs Heatsink Height Non Spreader Package 56 intel 6 0 FUTURE PENTIUM OverDrive PROCESSOR SOCKET SPECIFICATION 6 1 Introduction The Future Pentium OverDrive processor is an end user single chip CPU upgrade product for Pentium processo
3. FLUSH INC INC INC 155 vss VSS vs vs VSS VSS 8 VSS VSS W R EADS ADSC 4 6 8 0 NC SCYC 8 6 BEO BUSCHK HITM PWT 7 10 RESET A20M a R AP 4 ADSS BREQ ves o o PCD SMIACT O VSS APCHK PBREQ PBGNT VSS PRDY HOLD WB WT amp PHIT BOFF VSS BRDYC VCC BRDYe VSS EWBE VCC AHOLD VSS TOP SIDE VIEW B CACHES MUOR VSS 2 PM1BP1 VSS CPUTYP TABTA FERR PMOBPO TMS TCK vcc PICD DO vcc 02 VSS D42 DP1 019 023 025 028 DP3 033 03 037 09 00 044 9 014 017 021 024 0 2 025 027 029 031 032 034 036 038 0 4 045 O D13 016 020 vss VSS VSS VSS VSS VSS vss vss vss vss vss vss o 015 022 vec vece vec vec vce vec vec vec vece vec vee vcc 97 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
4. 64 Bit 64 Data Bus Data Control AQGress Generate U Pipeline Code Cache 8 KBytes Control ROM ddress Floating aude Point V Pipeline Unit Register File ple Data Cache 8 KBytes 241997 18 Figure 1 Pentium Processor Block Diagram The block diagram shows the two instruction pipe lines the pipe and the v pipe The u pipe can execute all integer and floating point instructions The v pipe can execute simple integer instructions and the FXCH floating point instructions The separate caches are shown the code cache and data cache The data cache has two ports one for each of the two pipes the tags are triple ported to allow simultaneous inquire cycles The data cache has a dedicated Translation Lookaside Buffer TLB to translate linear addresses to the physical addresses used by the data cache The code cache branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the Pentium processor Instructions are fetched from the code cache or from the external bus Branch addresses are re membered by the branch target buffer The code cache TLB translates linear addresses to physical addresses used by the code cache The decode unit decodes the prefetched instruc tions so the Pentium processors can execute the instruction The control ROM contains the micro code which controls the sequence of operations that _ PENTIUM
5. Pentium Processor 60 66 Electrical Characteristic 5V Power Supply 3 3V Power Supply 5V TTL Inputs Outputs 3 3V Inputs Outputs Pentium Processor 75 90 100 120 Buffer Models Pentium Processor 60 66 Buffer Models The upgrade socket specifies two 5V inputs section 6 0 The sections that follow will briefly point out some ways to design with these electrical differences 3 1 1 3 3V POWER SUPPLY The Pentium processor 75 90 100 120 has all Vcc 3 3V inputs By connecting all Pentium processor 60 66 Vcc inputs to a common and dedicated pow er plane that plane can be converted to 3 3V for the Pentium processor 75 90 100 120 The CLK and PICCLK inputs can tolerate a 5V input signal This allows the Pentium processor 75 90 100 120 to use 5V or 3 3V clock drivers 3 1 2 3 3V INPUTS AND OUTPUTS The inputs and outputs of the Pentium processor 75 90 100 120 are 3 3V JEDEC standard levels Both inputs and outputs are also TTL compatible although the inputs cannot tolerate voltage swings above the 3 3V Vin max For Pentium processor 75 90 100 120 outputs if the Pentium processor 60 66 system support com ponents use TTL compatible inputs they will inter face to the Pentium processor 75 90 100 120 with out extra logic This is because the Pentium proces sor 75 90 100 120 drives according to the 5V TTL specification but not beyond 3 3V PENTIUM PROCESSOR 75 90 100 120 For Pentium processor 75 90 100 120
6. 232 13 1515 133 2 t54 TDO Float Delay All Non Test Outputs Valid Delay All Non Test Outputs Float Delay All Non Test Inputs Setup Time 25 0 20 0 n 451 TDI TMS Setup Time 452 TDI TMS Hold Time 13 0 3 0 2 9 8 10 1 3 8 10 3 7 10 3 7 10 S S S o 2 57 158 All Non Test Inputs Hold Time APIC AC Specifications PICCLK Frequency 2 0 16 66 MHz PICCLK Period PICCLK High Time _ Low Time PICCLK Rise Time PICCLK Fall Time PICDO 1 Setup Time PICDO 1 Hold Time e e 2 2 ToPICCLK To PICCLK mE olio 3 3 2 3 2 2 2 PICDO 1 Valid Delay LtoH 4 0 38 0 5 From PICCLK 8 29 PICDO 1 Valid Delay HtoL 4 0 220 5 From PICCLK 28 29 38 intel PENTIUM PROCESSOR 75 90 100 120 Table 15 Pentium Processor 735 90 Dual Processor Mode AC Specifications for 60 MHz Bus Operation 3 135 lt Vcc lt 3 465V Tcase Oto 70 C CL O pF symbol Parameter Win ws Fight Time 0 eta PEREGE PEGNT Setup Tine 60 no eo we PBREQ PBONTA HoldTime wa er Setup Time ws ADS amp WiO amp SeupTme 50 HIT HITM eo nS ws 65 ADS D C W R M IO CACHE 1 0 LOCK A5 A31 HLDA HIT HITM SCYC Hold Time 84 85 DPEN Valid Time 86 i 87 88
7. 89 nS 3 3 3 3 IX 2 NIO OININININ o pes 25 1 APIC ID BEO BE3 4 Setup Time t ID BEO BE3 Hold Time 2 0 From RESET falling edge 23 t D P Valid Delay 1 0 Primary Processor Only 3 4 5 3 AC Timing Tables for 66 MHz Bus All timings are referenced to 1 5V for both 0 and 1 logic levels unless otherwise specified Within The AC specifications given in Tables 16 and 17 the sampling window a synchronous input must be consist of output delays input setup requirements stable for correct Pentium processor 75 90 100 and input hold requirements for a 66 MHz external 120 operation bus All AC specifications with the exception of those for the TAP signals and AP IC signals are relative to the rising edge of the CLK input To RESET falling edge 23 C 2 39 PENTIUM PROCESSOR 75 90 100 120 intel Table 16 Pentium Processor 8151100 AC Specifications for 66 MHz Bus Operation 3 135 lt lt 3 465V Tcase Oto 70 C Cj 0 pF ic 3 3 2 2 3J 13 13 213 442 Adjacent Clocks 1 25 4 2 1 zi 2 0V 0 8V 1 0 8V 2 0V 1 CLK Low Time CLK Fall Time CLK Rise Time ADSC PWT PCD BEO 7 D C W R CACHE SCYC Valid Delay a gt O AP Valid Delay 1 LOCK Valid Delay
8. 9 039 ves 10 11 12 1 vss 2 BEIS 037 036 Ves vcc vss BESS BE6 vss seyc o vee NC v s RESET A20 o D35 034 vss vcc 032 033 SS o DP3 029 1 0 vec 030 027 o yee vec 14 15 16 1 18 19 20 21 ves 028 88 A18 025 vec o vss vec o D23 DP2 vee vec 019 024 158 vec vee 021 DP1 020 o D17 022 35 36 37 27 24 21 23 INTR NMI ves o DPI RS4 ves vec SMIf 88 INIT IGNNE PENS vss Vim vec NC NC ves STPCLKS 33 vcc NC ves NC TRSTA CPUTYP VCC o TCK TDI vee vce o ves vec vss vss vss vec vec 1 ver 00 vss 02 vcc PICCLK vss gt goo mno x gt DO DO lt lt 22 23 24 25 26 27 28 29 30 31 32 33 34 35
9. Processor 735 90 AC Specifications for 60 MHz Bus Operation Contd 3 135 lt lt 3 465V TcAsE Oto 70 C CL 0 pF DO D63 DPO 7 Read Data Setup Time DO D63 0 7 Read Data Hold Time Symbol W e poc Symbol Hold Time Max HM LE NM E NN Reset Configuration Signals INIT FLUSH 5 0 42 Reset Configuration Signals INIT FLUSH 2 0 Setup Time Async Reset Configuration Signals INIT FLUSH FRCMC BRDYC BUSCHK Hold Time Async t42c Reset Configuration Signals BRDYC 3 0 BUSCHK Setup Time Async To RESET falling edge 16 To RESET falling edge 27 To RESET falling edge 27 To RESET falling edge 1 27 To RESET falling edge 22 To RESET falling edge 22 To RESET falling edge To RESET falling edge 4 nS 0 8V 1 142 t42d Reset Configuration Signal BRDYC Hold 1 0 Time RESET driven synchronously t43a BF CPUTYP Setup Time Tm BF CPUTYP Hold Time e APICEN Setup Time bus APICEN Hold Time 144 145 146 147 nji o 37 PENTIUM PROCESSOR 75 90 100 120 intel Table 14 Pentium Processor 735 90 AC Specifications for 60 MHz Bus Operation Contd 3 135 lt lt 3 465V 0 to 70 C 0 pF Parameter Notes TCK Fall Time 4 Rise Time 4 TRST Pulse Width O
10. T12 T2P fma rae io Synchronous Nw He wa Asynchronous TD a w la wma Smewonws TCK EADS First BRDY NA Bus State T2 TD T2P BRDY Synchronous TCK L L n n L n n TCK TDI TMS Undefined when the CPU is configured as a Dual processor First BRDY NA 22 intel PENTIUM PROCESSOR 75 90 100 120 Table 5 Input Output Pins Internal Sat Mente wa Address Be Ho Borre _ Adress Hold Bus Hold BOFF wa _ wa sustoa Borre save dw NOTES All output and input output pins are floated during tristate test mode except TDO and checker mode except IERR and TDO BE3 BE0 have Pulldowns during RESET only Table 6 Inter Processor I O Pins sternal Resistor mme tw mmus tw Phe _ Mo mp areas Phe NOTE For proper inter processor operation the system cannot load these signals 23 a PENTIUM PROCESSOR 75 90 100 120 intel 2 5 Pin Grouping According to Function Table 7 organizes the pins with respect to their function Tab
11. 19 18 17 16 15 14 13 12 11 10 9 8 7 gt x r E gt 00390 C x KN gt m m I x v lt x lt 241997 19 Figure 2 Pentium Processor 75 90 100 120 Pinout Top Side View PENTIUM PROCESSOR 75 90 100 120 7 Y X W U T 8 R Q P N M L K J H 0 B A 12 3 4 5 6 7 9 9 10 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INC ADSC EADS WIRI INC INC e PWT INC FLUSH vece Q 153 HiTM BUSCHKs BEOS vss HIT A20ME BREQ ADSS VSS vce PCD VSS VCC PBREQ VSS PBGNT o PHITH PADY VSS HOLD VCC PHIT WB WTE 5 BOFF BROYC NAF VSS BRDY EWBE VSS AHOLD VCC CACHE INV o VSS MVO vec BP2 VSS PMIBP1 PMOBPO FERRE vsS o vcc DP7 062 061 060 vec VSS vec 057 vas vec D55 0 6 054 050 047 052 059 058 056 053 051 049 o 048 045 0 5 044 046 DP4 040 042 038 o vec
12. 3 Valid Delay PRDY Valid Delay 00 063 DPO 7 Write Data Valid Delay 5 5 5 O 1 4 7 4 gt 1 5 35 PENTIUM PROCESSOR 75 90 100 120 ntel Table 14 Pentium Processor 735 90 AC Specifications for 60 MHz Bus Operation Contd 3 135 lt Vcc lt 3 465V Oto 70 C CL 0 pF Symbol t Parameter DO D63 DPO 3 Write Data Float Delay A5 A31 Setup Time A5 A31 Hold Time INV AP Setup Time EADS Setup Time EADS INV Hold Time KEN Setup Time WB WT Setup Time WB WT Hold Time 20 BRDY BRDYC Setup Time toy BRDY BRDYC Hold Time too AHOLD BOFF Setup Time AHOLD BOFF Hold Time to4 BUSCHK EWBE HOLD PEN Setup Time BUSCHK EWBE PEN Hold Time HOLD Hold Time 126 A20M INTR STPCLK Setup Time to7 A20M INTR STPCLK Hold Time 3 14 15 ti6a t16b 7 148a 19 et KOT OF A ao ol oio 125 N gt Q3 tog INIT FLUSH NMI IGNNE Setup 5 0 ns 12 16 17 Time tog INIT FLUSH NMI SMI IGNNE Hold 1 0 7 13 Time 130 INIT FLUSH NMI SMI IGNNE Pulse 2 0 15 17 Width Async 134 R S Setup Time 7 12 16 17 50 15 R S Hold Time 133 R S Pulse Width Async 36 PENTIUM PROCESSOR 75 90 100 120 Table 14 Pentium
13. 5 6 7 2 SOCKET 5 VENDORS 5 should contact Intel for the most current list of Intel qualified socket vendors For a complete list of Qualified Sockets and Vendor Order Numbers call the Intel Faxback number for your geographical area and have document 7209 automatically faxed to you Figure 19 shows preliminary dimensions for AMP and Yamaichi sockets OEMs should directly contact the socket vendors for the most current socket information Figure 20 shows the upgrade processor s orientation in Socket 5 To order Socket 5 from AMP and Yamaichi the phone numbers and part numbers are as follows 1 800 522 6752 part 916513 1 Yamaichi 1 800 769 0797 part NP210 320K13625 63 PENTIUM PROCESSOR 75 90 100 120 1 N N 9 N o Ni LO 2 L 9 c T 2 S N Al 10 Li LW se BOO 6 a e a B ZE iu Ze m o Et g 5 gt o 5 o i 5 5 2 i 4o gt n iL E Q i F 2 z lt a g L gt 2 p 5 c j 2 gt 5 62 S 2 lt lt a intel 6 8 Testability 6 8 1 BOUNDARY SCAN The Future Pentium OverDrive processor supports the IEEE Standard 1149 1 boundary scan using the Test Access Port TAP and TAP Controller The boundary scan register for the Future Pentium OverDriv
14. 50 Package Total Pentium Processor 75 90 100 120 SPGA 37 x 37 1 95 x 1 95 4 95 cm x 4 95 cm PENTIUM PROCESSOR 75 90 100 120 Table 19 Package Dimensions with Spreader Family Ceramic Staggered Pin Grid Array Package 0 E m Wm 7 qu 1 52 Table 20 Package Dimensions without Spreader 0 120 0 130 Family 296 Pin Ceramic Pin Grid Array Package Millimeters UT Min Notes O 3 27 3 83 0 129 0 151 Ceramic Lid 327 0 66 0 86 0 026 Ceramic Lid 0 017 NE NUN ES 79 NN Mu WO Includes Fillet 279 0090 NM 0 127 0 005 Flatness of the top of the Flatness of the top of the package measured diagonally package measured diagonally st is 608 51 PENTIUM PROCESSOR 75 90 100 120 SEATING PLANE vo a 45 CHAMFER 2 29 REF INDEX CORNER 1 52 55 CU W Heat Spreader Braze Metalization 241997 12 Figure 12 Pentium Processor 75 90 100 120 Package Dimensions with Spreader 52 PENTIUM PROCESSOR 75 90 100 120 Seating 4 03 gt L D a D O O O O O O ex GOO co 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 pop OOOO
15. 7 Referenced to TCK rising edge 8 Referenced to TCK falling edge 9 1 ns be added to the maximum rise and fall times for every 10 MHz of frequency below 33 MHz 10 During probe mode operation do not use the boundary scan timings t55 58 11 FRCMC should be tied to high to ensure proper operation of the Pentium processor 75 90 100 120 as primary processor 12 Setup time is required to guarantee recognition on a specific clock Pentium processor 75 90 100 120 must meet this specification for dual processor operation for the FLUSH and RESET signals 44 13 14 15 16 17 24 25 26 27 28 29 30 PENTIUM PROCESSOR 75 90 100 120 Hold time is required to guarantee recognition on a specific clock Pentium processor 75 90 100 120 must meet this specification for dual processor operation for the FLUSH and RESET signals All TTL timings are referenced from 1 5V To guarantee proper asynchronous recognition the signal must have been de asserted inactive for a minimum of 2 clocks before being returned active and must meet the minimum pulse width This input may be driven asynchronously However when operating two processors in dual processing mode FLUSH and RESET must be asserted synchronously to both processors When driven asynchronously RESET NMI FLUSH R S INIT and SMI must be de asserted inactive for a minimum of 2 clocks before being returned ac
16. 75 90 100 120 are derived from the Pentium processor 60 66 specifications the system should see little difference between the AC behavior of the Pentium processor 75 90 100 120 and the Pentium processor 60 66 To meet specifications simulate the AC timings with Pentium processor 75 90 100 120 buffer models Pay special attention to the new signal quality re strictions imposed by 3 3V buffers 25 PENTIUM PROCESSOR 75 90 100 120 3 2 Absolute Maximum Ratings The values listed below are stress ratings only Functional operation at the maximums is not implied or guaranteed Functional operating conditions are given in the AC and DC specification tables Extended exposure to the maximum ratings may af fect device reliability Furthermore although the Pentium processor 75 90 100 120 contains protec tive circuitry to resist damage from static electric dis charge always take precautions to avoid high static voltages or electric fields Case temperature under bias 65 C to 110 C Storage temperature 65 C to 150 C 3V Supply voltage with respect to 0 5V to 4 6V 3V Only Buffer DC Input Voltage 0 5V to 0 5 not to exceed max 2 5V Safe Buffer DC Input Voltage 0 5V to 6 5V 1 3 NOTES 1 Applies to CLK and PICCLK 2 Applies to all Pentium processor 75 90 100 120 inputs except CLK and PICCLK 3 See overshoot undershoot tran
17. PROCESSOR 75 90 100 120 must be performed to implement the Pentium proc essor architecture The control ROM unit has direct control over both pipelines The Pentium processors contain a pipelined floating point unit that provides a significant floating point performance advantage Over previous Generis of processors The architectural features introduced in this UR are more fully described in the Pentium Family User s Manual 1 2 Pentium Processor 75 90 100 120 In addition to the architecture described above for the Pentium processor family the Pentium proces sor 75 90 100 120 has additional features which are described in this section The Pentium processor 75 90 100 120 offers high er performance and higher operating frequencies than the Pentium processor 60 66 The 120 MHz version of the Pentium processor 75 90 100 120 offers core operation at 120 MHz external bus inter face at 60 MHz and achieves an iCOMP index of 1000 while the 100 MHz version of the Pentium processor 75 90 100 120 offers core operation at 400 MHz external bus interface at 50 or 66 MHz and achieves an iCOMP index of 815 while the 90 MHz version offers core operation at 90 MHz ex ternal bus interface at 60 MHz and achieves an iCOMP index of 735 and the Pentium processor 75 90 100 120 core operates at 75 MHz and the exter nal bus operates at 50 MHz Symmetric dual processing in a system is supported with two Pentium pro
18. Vcc 3 3V and also takes into account the thermal time constants of the package 3 Stop Grant Auto Halt Powerdown Power Dissipation is determined by asserting the STPCLK pin or executing the HALT instruction 4 Stop Clock Power Dissipation is determined by asserting the STPCLK pin and then removing the external CLK input 3 4 AC Specifications The AC specifications of the Pentium processor 75 90 100 120 consist of setup times hold times and valid delays at 0 pF 3 4 1 PRIVATE BUS When two Pentium processors 75 90 100 120 are operating in dual processor mode a private bus exists to arbitrate for the CPU bus and maintain local cache coherency The private bus consists of two pinout changes 1 Five pins are added PBREQ PBGNT PHIT PHITM D P 2 Ten output pins become pins ADS D C M IO CACHE LOCK HIT HITM HLDA SCYC The new pins are given AC specifications of valid delays at 0 pF setup times and hold times Simulate with these parameters and their respective I O buff er models to guarantee that proper timings are met The AC specification gives input setup and hold times for the ten signals that become 1 pins These setup and hold times must only be met when a dual processor is present in the system 28 3 4 2 POWER AND GROUND For clean on chip power distribution the Pentium processor 75 90 100 120 has 53 power and 53 Vss ground inputs Power and g
19. exposure beyond the Fan ating Conditions may affect device reliability Storage Temperature 30 C to 75 C Case Temperature Under Bias 30 C to 75 C 6 4 1 DC SPECIFICATIONS The Future Pentium OverDrive processor will have compatible DC specifications to the Pentium processor 75 90 100 120 except that Power Supply Current Fan Heatsink Current and Vcc are the following Table 24 Future Pentium OverDrive Processor lcc Specification Voc5 5V 5 Tcase Oto 70 C __ Symb Parameter Power Supply Current Fan Heatsink NOTE 1 Vcc 3 1354 to 3 61 6 5 Mechanical Specifications The Future Pentium OverDrive processor will be packaged in a 320 pin ceramic staggered pin grid array SPGA The pins will be arranged in a 37 x 37 matrix and the package dimensions will be 1 95 x 1 95 4 95 cm x 4 95 cm Table 25 Processor Package Information Summary Package Type Total Pins Package Size Future Pentium OverDrive Processor SPGA 320 37 X37 1 95 x 1 95 4 95 cm x 4 95 cm 61 PENTIUM PROCESSOR 75 90 100 120 intel Table 26 Future Pentium OverDrive Processor Package Dimensions 33 88 Solid Lid 1384 Solid Lid Solid Lid 0 013 0 017 Solid Lid ouo ArSpaco _ oom 45 47 45 97 1 790 1 810 NOTES Assumes t
20. inputs the voltage must not exceed the 3 3V maximum specification System support components can con sist of 3 3V devices or open collector devices 3 3V support components may interface to the Pentium processor 60 66 since they typically meet 5V TTL specifications In open collector configuration the external resistor may be biased with the CPU Vcc as the CPU s Vcc changes from 5V to 3 3V so does this signal s maximum drive The CLK and PICCLK inputs of the Pentium proces sor 75 90 100 120 are 5V tolerant so they are electrically identical to the Pentium processor 60 66 clock input This allows a Pentium processor 60 66 clock driver to drive the Pentium processor 75 90 100 120 All pins other than the CLK and PICCLK inputs are 3 3V only If an 8259A interrupt controller is used for example the system must provide level convert ers between the 8259A and the Pentium processor 75 90 100 120 3 1 3 3 3V PENTIUM PROCESSOR 75 90 100 120 BUFFER MODELS The structure of the buffer models of the Pentium processor 75 90 100 120 are the same as those of the Pentium processor 60 66 but the values of the components change since the Pentium processor 75 90 100 120 buffers are 3 3V buffers on a differ ent process Despite this difference the simulation results of Pentium processor 75 90 100 120 buffers and Pen tium processor 60 66 buffers look nearly identical Since the OpF AC specifications of the Pentium processor
21. o vec D57 058 PICDO D2 vec 059 vss o 060 PICD vee VSS 062 TCK v83 o vee D63 DP7 TDI VSS TMS V88 o PMOBPO FERRI TAST cPUTYP VCC 88 PMIBPI NC 88 BP2 o vss CACHES INY 88 AHOLD vec vss STPCLK V88 EWBE NC NC vec v88 BRDY NC ves VSS PENI 88 WBITE WIT IGNNE 58 HOLD vss o VCC PROY NMI 84 vec VSS PBGNT INTR vss o o VCC PBREQ APCHK A23 NC vcc VSS PCHK A21 V 8 SMIACT PCD A27 A24 vec vss LOCK PLUG PLUG 26 A22 E BREQ ADS 85 198 vee vss NC 88 vec 88 NC V 9 vss vet vss A31 A25 vss 20 CLK RESET 18 A17 15 A13 A9 A5 A29 A28 VSS PWT HITM BEOS BE2t BEEF 20 A18 A16 A14 A12 A11 88 o ADSC EADS 1
22. pow er dissipation is virtually eliminated The combination of these improvements makes the Pentium proces sor 75 90 100 120 a good choice for energy effi cient desktop designs Supporting an upgrade socket Socket 5 in the sys tem will provide end user upgradability by the addi tion of a Future Pentium OverDrive processor Typi cal applications will realize a 4096 7096 perform ance increase by addition of a Future Pentium OverDrive processor The Pentium processor 75 90 100 120 supports fractional bus operation This allows the internal processor core to operate at high frequencies while communicating with the external bus at lower fre quencies The external bus frequency operates at a selectable one half or two thirds fraction of the inter nal core frequency The Pentium processor 75 90 100 120 contains an on chip Advanced Programmable Interrupt Control ler APIC This APIC implementation supports multi processor interrupt management with symmetric in terrupt distribution across all processors multiple subsystem support 8259A compatibility and in ter processor interrupt support mn intel PENTIUM PROCESSOR 75 90 100 120 2 0 PINOUT 2 1 Pinout and Pin Descriptions 2 1 1 PENTIUM PROCESSOR 75 90 100 120 PINOUT 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 10 9 8 7 6 5 4 3 2 vec vec vcc vec vee vec vec vcc
23. processor 75 90 100 120 indicating completion of the write back and invalidation If FLUSH is sampled low when RESET transitions from high to low tristate test mode is entered If two Pentium processors 75 90 100 120 are operating in dual processing mode in a system and FLUSH is asserted the Dual processor will perform a flush first without a flush acknowledge cycle then the Primary processor will perform a flush followed by a flush acknowledge cycle The functional redundancy checking master checker mode input is used to determine whether the Pentium processor 75 90 100 120 is configured in master mode or checker mode When configured as a master the Pentium processor 75 90 100 120 drives its output pins as required by the bus protocol When configured as a checker the Pentium processor 75 90 100 120 tristates all outputs except IERR and TDO and samples the output pins The configuration as a master checker is set after RESET and may not be changed other than by a subsequent RESET The hit indication is driven to reflect the outcome of an inquire cycle If an inquire cycle hits a valid line in either the Pentium processor 75 90 100 120 data or instruction cache this is asserted two clocks after EADS 15 sampled asserted If the inquire cycle misses the Pentium processor 75 90 100 120 cache this pin is negated two clocks after EADS This pin changes its value only as a result of an inquire cycle
24. rela tive to the rising edge of the CLK input All timings are referenced to 1 5V for both 0 and 1 logic levels unless otherwise specified Within the sampling window a synchronous input must be stable for correct Pentium processor 75 90 100 120 operation Table 12 Pentium Processor 610175 8151100 AC Specifications for 50 MHz Bus Operation 3 135 lt lt 3 465V TcAsE Oto 70 C 0 pF o w uw gt uw okote ADS ADSC PWT PCD BEO 7 M IO D C CACHE SCYC W R Valid Delay D gt o CLK Period 20 0 gt Alo B o CLK Fall Time 0 CLK Rise Time 0 e 100 MHz 91 2 MM gt D 2 29 PENTIUM PROCESSOR 75 90 100 120 intel Table 12 Pentium Processor 610 75 815 100 AC Specifications for 50 MHz Bus Operation Contd 3 135 lt lt 3 465V TcAsE Oto 70 C 0 pF AP Valid Delay A3 A31 LOCK Valid Delay O t6b t6c 3 13 13 13 13 13 13 53 13 15 13 15 3 15 13 13 13 15 3 3 S 5 3 o ADS ADSC AP A3 A31 PWT PCD BEO 7 M IO D C W R CACHE SCYC LOCK Float Delay APCHK IERR FERR PCHK V
25. 0 120 intel RESET Config 241997 8 440 Tu 141 Tv 137 T w t42 t43a 143 187 Tx 143 1434 188 138 139 Tz 136 Figure 8 Reset and Configuration Timings AN NW AAAAARAAAK po l sigas OO input Signal Tr t57 Ts t58 Tu t54 Tv 451 Tw t52 Tx t53 Ty t55 Tz t56 241997 9 Figure 9 Test Timings 48 ntel a PENTIUM PROCESSOR 75 90 100 120 241997 10 Figure 10 Test Reset Timings Signal Level Driver Pin 65 59 Delay Flight Time 50 35 B At Receiver Pin 241997 11 Figure 11 50 Vcc Measurement of Flight Time 49 PENTIUM PROCESSOR 75 90 100 120 4 0 MECHANICAL SPECIFICATIONS The Pentium processor 75 90 100 120 is packaged in a 296 pin staggered pin grid array package The pins are arranged in a 37 x 37 matrix and the pack age dimensions are 1 95 x 1 95 Table 18 A 1 25 x 1 25 copper tungsten heat spreader may be attached to the top of the ceramic This package intel design with spreader is being phased out in favor of a package which has no attached spreader In this section both spreader and non spreader packages are shown The mechanical specifications for the Pentium proc essor 75 90 100 120 are provided in Table 19 Fig ure 12 shows the package dimensions Table 18 Package Information Summary
26. 36 37 Figure 3 Pentium Processor 75 90 100 120 Pin Side View 241997 3 intel PENTIUM PROCESSOR 75 90 100 120 2 1 2 PIN CROSS REFERENCE TABLE FOR PENTIUM PROCESSOR 75 90 100 120 Table 1 Pin Cross Reference by Pin Name PENTIUM PROCESSOR 75 90 100 120 intel Table 1 Pin Cross Reference by Pin Name Contd A20M BRDYC FLUSH ANO7 PEN ADS BREQ FRCMC Y35 ADSC BUSCHK HIT 6 1 1 AHOLD CACHE HITM 105 PRDY AP CPUTYP HLDA PWT APCHK D C HOLD 04 R S BEO D P P04 RESET DPO IGNNE AA35 SCYC 2 DP1 INIT AA33 SMI DP2 INTR LINTO 034 SMIACT BE4 DP3 INV 005 TCK 5 DP4 KEN TDI BEG DP5 LOCK AHO4 TDO 7 DP6 M IO T04 TMS BOFF DP7 NA YO5 TRST BP2 EADS NMI LINT1 AC33 W R BP3 EWBE PCD AGOS WB WT BRDY FERR PCHK AF04 M APIC Clock Control Dual Processor Private Interface PICCLK CLK AK18 PBGNT PICDO BF Y33 PBREQ DPEN STPCLK V34 PHIT PICD1 PHITM APICEN S 10 PENTIUM PROCESSOR 75 90 100 120 Table 1 Pin Cross Reference by Pin Name Contd C01 A37 H34 B02 S33 2 2 Design Notes For reliable operation always connect unused in puts to an appropriate signal level Unused active low inputs should be connected to Vcc Unused ac tive HIGH inputs should be connected to GND No Connect NC pins must
27. 53 vss vss v vss vss ves vss 188 vss vss 8 4 0 5 5 188 FLUSH vec vec vee vec vec vec vec vcc vec A10 AG NC vss 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 3015 401 LNONId S 194205 B 0 G H J K L M N P Q 5 T U W X Y 2 gt amp lt gt 241997 15 Figure 17 Socket 5 Pinout Top Side View NOTE The Socket 5 PINOUT TOP SIDE VIEW text orientation on the top side view drawing in this section repre sents the orientation of the ink mark on the actual packages Note that the text shown in this section is not the actual text which will be marked on the packages 59 PENTIUM PROCESSOR 75 90 100 120 Table 23 Pentium Processor 75 90 100 120 vs Socket 5 Pins Pentium Processor 75 90 100 120 Socket 5 ZIZ Z 2 lt lt lt N o Vss lt m All INCs are internal connects These signals guar anteed to remain internally not connected in the Pentium processor 75 90 100 120 60 _ 6 3 Electrical Specifications The Future Pentium OverDrive processor will have the same AC specifications power and grou
28. 86 family of CPUs The Pentium processors implement several en hancements to increase performance The two in struction pipelines and floating point unit on Pentium processors are capable of independent operation Each pipeline issues frequently used instructions in a single clock Together the dual pipes can issue two integer instructions in one clock or one floating point instruction under certain circumstances two floating point instructions in one clock Branch prediction is implemented in the Pentium processors To support this Pentium processors im plement two prefetch buffers one to prefetch code in a linear fashion and one that prefetches code according to the BTB so the needed code is almost always prefetched before it is needed for execution The floating point unit has been completely rede signed over the Intel486 CPU Faster algorithms pro vide up to 10X speed up for common operations in cluding add multiply and load PENTIUM PROCESSOR 75 90 100 120 Pentium processors include separate code and data caches integrated on chip to meet performance goals Each cache is 8 Kbytes in size with a 32 byte line size and is 2 way set associative Each cache has a dedicated Translation Lookaside Buffer TLB to translate linear addresses to physical addresses The data cache is configurable to be write back or write through on a line by line basis and follows the MESI protocol The data cache tags are triple ported to
29. CMC Setup Time RESET Pulse Width Vcc amp CLK Stable Reset Configuration Signals INIT FLUSH 1 0 nS FRCMC Hold Time 31 m PENTIUM PROCESSOR 75 90 100 120 intel Table 12 Pentium Processor 610175 815 100 AC Specifications for 50 MHz Bus Operation Contd 3 135 lt Voc lt 3 465V Tcase Oto 70 C CL 0 pF Reset Configuration Signals INIT FLUSH 2 0 FRCMC Setup Time Async Reset Configuration Signals INIT FLUSH l42b FRCMC BRDYC BUSCHK Hold Time Async Reset Configuration Signals BRDYC BUSCHK Setup Time Async t42d Reset Configuration Signal BRDYC Hold 1 0 To RESET falling Time RESET driven synchronously 1 27 taga BF CPUTYP Setup Time RESET falling edge 22 t43b BF CPUTYP Hold Time 2 0 To RESET falling edge2 20 APICEN Setup Time To RESET falling edge APICEN Hold Time 2 0 m o gt 010 Cc 32 a intel PENTIUM PROCESSOR 75 90 100 120 Table 12 Pentium Processor 610 75 815 100 AC Specifications for 50 MHz Bus Operation Contd 3 135 lt lt 3 465V Tcase Oto 70 C 0 pF Parameter All Non Test Outputs Float Delay All Non Test Inputs Setup Time All Non Test Inputs Hold Time 13 APIC AC Specifications 1 3 8 10 3 7 10 3 7 10 5 e o no 125 3 57 O S teoa PICCLK Frequ
30. ENTIUM PROCESSOR at iCOMP INDEX 815 100 MHz PENTIUM PROCESSOR at iCOMP INDEX 1000 120 MHz CONTENTS PAGE 1 0 MICROPROCESSOR ARCHITECTURE OVERVIEW 3 1 1 Pentium Processor Family Architecture eai RES 3 1 2 Pentium Processor 75 90 100 120 6 2 0 PINOUT EN 2 1 Pinout and Pin Descriptions 7 2 2 Design Notes ve 2 3 Quick Pin Reference 11 2 4 Pin Reference Tables 21 2 5 Pin Grouping According to FUNCION 24 3 0 ELECTRICAL SPECIFICATIONS 25 3 1 Electrical Differences Between Pentium Processor 75 90 100 120 and Pentium Processor 60 66 25 3 2 Absolute Maximum Ratings 26 3 3 DC Specifications 26 ee a 28 3 4 AC Specifications CONTENTS PAGE 4 0 MECHANICAL SPECIFICATIONS 50 5 0 THERMAL SPECIFICATIONS 54 5 1 Measuring Thermal Values 54 6 0 FUTURE PENTIUM OverDrive PROCESSOR SOCKET SPECIFICATION nm 57 6 1 Introduction 57 6 2 Future Pentium OverDrive Processor Socket 5 Pinout 58 6 3 Electrical Specifications 60 6 4 Absolute Maximum Ratings of Upgrade S 60 6 5 Mechanical Specifications 61 6 6 Thermal Specifications 63 6 7 Upgradability with Socket 5 63 6 8 Testabi
31. FLUSH NMI SMI IGNNE Pulse 2 15 17 Width Async 12 16 17 15 17 11 12 16 R S Setup Time R S Hold Time R S Pulse Width Async 00 063 DPO 7 Read Data Setup Time 00 063 DPO 7 Read Data Hold Time RESET Setup Time c of o olol o 41 m PENTIUM PROCESSOR 75 90 100 120 intel a Table 16 Pentium Processor 815 100 AC Specifications for 66 MHz Bus Operation Contd 3 135 lt Vcc lt 3 465V Tcase Oto 70 C 0 pF c 11 13 RESET Hold Time RESET Pulse Width amp CL K Stable 15 11 17 RESET Active After amp CLK Stable ns 12 16 17 13 Reset Configuration Signals INIT FLUSH FRCMC Setup Time Reset Configuration Signals INIT FLUSH FRCMC Hold Time Reset Configuration Signals INIT FLUSH 2 0 To RESET falling FRCMC Setup Time Async edge 19 To RESET falling edge 7 ET eo eo 187 139 r 3r OA o o o LKs t42b Reset Configuration Signals INIT FLUSH FRCMC BRDYC BUSCHK Hold Time Async Reset Configuration Signals BRDYC BUSCHK Setup Time Async To RESET falling edge 27 To RESET falling edge 1 27 To RESET falling edge 22 To RESET falling edge 22 To RESET falling edge To RESET falling edge t42d Reset Configuration
32. OOOO OOO 9 0 9 9 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 A1 e 28 Wo 45 Index Chamfer Bottom View Pin Side Up Index Corner Side View Top View 241997 20 Figure 13 Pentium Processor 75 90 100 120 Package Dimensions without Spreader 53 PENTIUM PROCESSOR 75 90 100 120 5 0 THERMAL SPECIFICATIONS Due to the advanced 3 3V BiCMOS process that it is produced on the Pentium processor 75 90 100 120 dissipates less power than the Pentium proces sor 60 66 The Pentium processor 75 90 100 120 is specified for proper operation when case temperature TCASE Tc is within the specified range of 0 C to 70 C 5 1 Measuring Thermal Values The Pentium processor 75 90 100 120 package will include a heat spreader To verify that the proper Tc case temperature is maintained it should be measured at the center of the package top surface opposite of the pins The measurement is made in the same way with or without a heat sink attached When a heat sink is attached a hole smaller than 0 150 diameter should be drilled through the heat sink to allow probing the center of the package See Figure 13 for an illustration of how to measure Tc To minimize the measurement errors it is recom mended to use the following approach Use 36 gauge or finer diameter K T or J type thermocouples The laboratory testing was done using a thermocouple made by Om
33. Signal BRDYC Hold Time RESET driven synchronously l43a BF CPUTYP Setup Time 2 Ma t43b BF CPUTYP Hold Time t43c APICEN Setup Time Hold Time r o N 16 0 TDI TMS Setup Time Asynchronous no t t t t t t t 44 45 46 47 48 49 50 151 2 3 42 intel PENTIUM PROCESSOR 75 90 100 120 Table 16 Pentium Processor 815 100 AC Specifications for 66 MHz Bus Operation Contd 3 135 lt Vcc lt 3 465 Oto 70 C Cj 0 pF Parameter Max TDI TMS Hold Time 53 TDO Valid Delay 54 Float Delay 55 All Non Test Outputs Valid Delay All Non Test Outputs Float Delay All Non Test Inputs Setup Time All Non Test Inputs Hold Time gt API 52 et 2 nS 57 W e 2 23 23 Ma On 130 n AC Specifications 20 0 PICCLK Frequency teoa tp PICCLK Period PICCLK High Time PICCLK Low Time teoe PICCLK Rise Time PICCLK Fall Time PICDO 1 Setup Time PICDO 1 Hold Time PICDO 1 Valid Delay LtoH PICDO 1 Valid Delay HtoL 40 220 nS N S H nS nS To PICCLK To PICCLK NO 5 5 2 43 PENTIUM PROCESSOR 75 90 100 120 intel Table 17 Pentium Processor 8151100 Dual Processor Mode Specifications for 66 MHz Bus Operat
34. alid Delay 5 gt Oo O 00 063 DPO 3 Write Data Float Delay A5 A31 Setup Time o A5 A31 Hold Time ti6a INV AP Setup Time BE t14 115 ti6b EADS Setup Time u7 EADS INV AP Hold Time uo t21 t22 t23 Ke NAP HodTme smvssmYceWouTme oresewTme 5 e Oo gt o O 30 intel PENTIUM PROCESSOR 75 90 100 120 Table 12 Pentium Processor 610 75 815 100 AC Specifications for 50 MHz Bus Operation Contd 3 135 lt lt 3 465V TCASE Oto 70 C O pF symbol Parameter min Max BUSCHK EWBE HOLD PEN Setup Time Figure is BUSOHKA PEN Hod Time e o o Time INIT FLUSH NMI SMI IGNNE Pulse 2 0 CLKs 7 15 17 Width Async nS tog INIT FLUSH NMI SMI IGNNE Setup 5 0 nS Time tog INIT FLUSH NMI SMI IGNNE Hold 2 42 t30 iv WSesewTme ee tea ASA Puise Width A 20 isu DoDesDPO7ReaiDaaSeupTme 36 tas DoDe DPOTReaiDamaHodTme 20 m RESET Sep tme so er RESETHodTime t38 i t39 i t41 RESET Active After Vcc amp CLK Stable 1 0 Reset Configuration Signals INIT FLUSH FR
35. and retains its value between the cycles The hit to a modified line output is driven to reflect the outcome of an inquire cycle It is asserted after inquire cycles which resulted in a hit to a modified line in the data cache It is used to inhibit another bus master from accessing the data until the line is completely written back The bus hold acknowledge pin goes active in response to a hold request driven to the processor on the HOLD pin It indicates that the Pentium processor 75 90 100 120 has floated most of the output pins and relinquished the bus to another local bus master When leaving bus hold HLDA will be driven inactive and the Pentium processor 75 90 100 120 will resume driving the bus If the Pentium processor 75 90 100 120 has a bus cycle pending it will be driven in the same clock that HLDA is de asserted 15 Li PENTIUM PROCESSOR 75 90 100 120 intel Table 2 Quick Pin Reference Contd In response to the bus hold request the Pentium processor 75 90 100 120 will float most of its output and input output pins and assert HLDA after completing all outstanding bus cycles The Pentium processor 75 90 100 120 will maintain its bus in this state until HOLD is de asserted HOLD is not recognized during LOCK cycles The Pentium processor 75 90 100 120 will recognize HOLD during reset The internal error pin is used to indicate two types of
36. and com pares those values with the values it computes inter nally and asserts an error signal if a mismatch oc curs As more and more functions are integrated on chip the complexity of board level testing is increased To address this the Pentium processors have in creased test and debug capability The Pentium processors implement IEEE Boundary Scan Stan dard 1149 1 In addition the Pentium processors have specified 4 breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match Execution tracing provides exter nal indications when an instruction has completed execution in either of the two internal Pipelines or when a branch has been taken System Management Mode SMM has been imple mented along with some extensions to the SMM ar chitecture Enhancements to the virtual 8086 mode have been made to increase performance by reduc ing the number of times it is necessary to trap toa virtual 8086 monitor Figure 1 shows a block diagram of the Pentium proc essor 75 90 100 120 For Pentium Processor 610175 designs which use the TCP package Intel document 242323 must be referenced for correct TCP pinout me chanical thermal and AC specifications PENTIUM PROCESSOR 75 90 100 120 Pentium Processor 75 90 100 120 MHz Branch Target Buffer Control pp Instruction Prefetch Buffers Pointer Instruction Decode Branch Verification amp Target Address
37. ase of applications for DOS Windows OS 2 and UNIX The Pentium processor 75 90 100 120 superscalar architecture can execute two instructions per clock cycle Branch prediction and separate caches also increase performance The pipelined floating point unit delivers worksta tion level performance Separate code and data caches reduce cache conflicts while remaining software transparent The Pentium processor 75 90 100 120 has 3 3 million transistors and is built on Intel s advanced 3 3V BiCMOS silicon technology The Pentium processor 75 90 100 120 has on chip dual processing sup port a local multiprocessor interrupt controller and SL power management features 241997 17 iOther brands and trademarks are the property of their respective owners tSince publication of documents referenced in this document registration of the Pentium OverDrive and iCOMP trade marks has been issued to Intel Corporation Information in this document is provided solely to enable use of Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for Sen products Information contained herein supersedes previously published specifications on these devices from Intel INTEL CORPORATION 1995 March 1995 Order Number 241997 004 PENTIUM PROCESSOR at iCOMP INDEX 610175 MHz PENTIUM PROCESSOR at iCOMP INDEX 735 90 MHz P
38. ause abrupt changes in the power being consumed by the Pentium processor 75 90 100 120 Note that the Auto HALT Powerdown feature is always enabled even when other power management fea tures are not implemented Bulk storage capacitors with a low ESR Effective Series Resistance in the 10 to 100 pf range are required to maintain a regulated supply voltage dur ing the interval between the time the current load changes and the point that the regulated power sup ply output can react to the change in load In order to reduce the ESH it may be necessary to place several bulk storage capacitors in parallel These capacitors should be placed near the Penti um processor 75 90 100 120 on the 3 3V plane to ensure that the supply voltage stays within specified limits during changes in the supply current during operation PENTIUM PROCESSOR 75 90 100 120 3 4 4 CONNECTION SPECIFICATIONS All NC and INC pins must remain unconnected For reliable operation always connect unused in puts to an appropriate signal level Unused active low inputs should be connected to Vcc Unused ac tive high inputs should be connected to ground 3 4 5 AC TIMING TABLES 3 4 5 1 AC Timing Table for a 50 MHz Bus The AC specifications given in Tables 12 and 13 consist of output delays input setup requirements and input hold requirements for a 50 MHz external bus All AC specifications with the exception of those for the TAP signals and APIC signals are
39. cation Program ensures that a Penti um processor 75 90 100 120 based personal com puter meets a minimum set of design criteria for reli able and straight forward CPU upgradability with a Future Pentium OverDrive processor Testing per formed at the Intel Verification Labs confirms that Future Pentium OverDrive processor specifications for mechanical thermal electrical functional and end user installation attributes have been met While system designs may exceed these minimum design criteria the intent is to provide end users with confi dence that computer systems based on verified de signs can be upgraded with Future Pentium Over Drive processors The OEM submits production ready designs to one of Intel s worldwide Verification Labs for testing The OEM benefits from advance testing of the design prior to availablitiy of the Future Pentium OverDrive processor By identifying and resolving upgradability problems before a system is introduced the OEM increases system quality and reduces future support costs associated with end user calls and complica tions when the CPU upgrade is ultimately installed 57 PENTIUM PROCESSOR 75 90 100 120 Contact your local Intel representative for more in formation on the Intel Verification Program for Penti um processor 75 90 100 120 based systems 6 2 Future Pentium OverDrive Processor Socket 5 Pinout This section contains pinouts of the Future Pentium OverDrive Socket Sock
40. cessors 75 90 100 120 The processors appear to the system as a single Pentium processor 75 90 100 120 Operating sys tems with dual processing support properly schedule computing tasks between the two processors This scheduling of tasks is transparent to software appli cations and the end user Logic built into the proces sors support a glueless interface for easy system design Through a private bus the two Pentium processors 75 90 100 120 arbitrate for the external bus and maintain cache coherency Dual process m intel ing is supported in a system only if both proces sors are operating at identical core and bus fre quencies Within these restrictions two proces sors of different steppings may operae togeth er ina system In this document in order to distinguish between two Pentium processors 75 90 100 120 in dual pro cessing mode one CPU will be designated as the Primary processor with the other being the Dual processor Note that this is a different concept than that of master and checker processors de scribed above in the discussion on functional redun dancy Due to the advanced 3 3V BiCMOS process that it is produced on the Pentium processor 75 90 100 120 dissipates less power than the Pentium proces sor 60 66 In addition to the SMM features de scribed above the Pentium processor 75 90 100 120 supports clock control When the clock to the Pentium processor 75 90 100 120 is stopped
41. che e 64 Bit Data Bus e Bus Cycle Pipelining e Address Parity e Internal Parity Checking e Functional Redundancy Checking e Execution Tracing e Performance Monitoring IEEE 1149 1 Boundary Scan e System Management Mode e Virtual Mode Extensions PENTIUM PROCESSOR 75 90 100 120 In addition to the features listed above the Pentium processor 75 90 100 120 offers the following en hancements over the Pentium processor 60 66 iCOMP performance rating of 1000 at 120 MHz in single processor configuration e iCOMP performance rating of 815 at 100 MHz in single processor configuration iCOMP performance rating of 735 at 90 MHz in single processor configuration iCOMP performance rating of 610 at 75 MHz in single processor configuration Dual processing support e SL power management features e Upgradable with a Future Pentium OverDrive processor Fractional bus operation On chip local APIC device 1 1 Pentium Processor Family Architecture The application instruction set of the Pentium proc essor family includes the complete Intel486 CPU family instruction set with extensions to accommo date some of the additional functionality of the Pentium processors All application software written for the intel386 and Intel486 family microprocessors will run on the Pentium processors without modifica tion The on chip memory management unit MMU is completely compatible with the Intel386 family and Intel4
42. ddress parity check status pin is asserted two clocks after EADS is sampled active if the Pentium processor 75 90 100 120 has detected a parity error on the address bus during inquire cycles APCHK will remain active for one clock each time a parity error is detected including during dual processing private snooping Advanced Programmable Interrupt Controller Enable is new pin that enables or disables the on chip APIC interrupt controller If sampled high at the falling edge of RESET the APIC is enabled APICEN shares a pin with the Programmable Interrupt Controller Data 1 signal PICD1 BE7 BE5 4 The byte enable pins are used to determine which bytes must be written to external memory or which bytes were requested by the CPU for the current cycle The byte enables are driven in the same clock as the address lines A31 3 Unlike the Pentium processor 60 66 the lower 4 byte enables BE3 BE0 are used on the Pentium processor 75 90 100 120 as APIC ID inputs and are sampled at RESET After RESET these behave exactly like the Pentium processor 60 66 byte enables In dual processing mode BEA is used as an input during Flush cycles 12 PENTIUM PROCESSOR 75 90 100 120 Table 2 Quick Pin Reference Contd Symbol Name and Function BF Bus Frequency determines the bus to core frequency ratio BF is sampled at RESET and cannot be changed until another non war
43. e cycle hit It is sampled together with the address for the inquire cycle in the clock EADS is sampled active LINTO INTR LINT1 NMI LOCK The cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length When the Pentium processor 75 90 100 120 generates a cycle that can be cached CACHE asserted and KEN is active the cycle will be transformed into a burst line fill cycle If the APIC is enabled this pin is local interrupt 0 If the APIC is disabled this pin is interrupt If the APIC is enabled this pin is local interrupt 1 If the APICI is disabled this pin is non maskable interrupt The bus lock pin indicates that the current bus cycle is locked The Pentium processor 75 90 100 120 will not allow a bus hold when LOCK is asserted but AHOLD and BOFF are allowed LOCK goes active in the first clock of the first locked bus cycle and goes inactive after the BRDY is returned for the last locked bus cycle LOCK is guaranteed to be de asserted for at least one clock between back to back locked cycles An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed The Pentium processor 75 90 100 120 will issue ADS for a pending cycle two clocks after NA is asserted The Pentium processor 75 90 100 120 supports up to 2 outstandin
44. e processor contains a cell for each pin The turbo upgrade component will have a different bit order than the Pentium processor 75 90 100 120 If the TAP port on your system will be used by an end user following installation of the Future Penti um OverDrive processor please contact Intel for the bit order of the upgrade processor boundary scan register PENTIUM PROCESSOR 75 90 100 120 65 intel UNITED STATES Intel Corporation 2200 Mission College Blvd P O Box 58119 Santa Clara CA 95052 8119 Tel 408 765 8080 JAPAN Intel Japan K K 5 6 Tokodai Tsukuba shi Ibaraki ken 300 26 Tel 0298 47 8511 FRANCE Intel Corporation S A R L 1 Rue Edison BP 303 78054 Saint Quentin en Yvelines Cedex Tel 33 1 30 57 70 00 UNITED KINGDOM Intel Corporation U K Ltd Pipers Way Swindon Wiltshire England SN3 1RJ Tel 44 0793 696000 GERMANY Intel GmbH Dornacher Strasse 1 8016 Feldkirchen bei Muenchen Tel 49 089 90992 0 HONG KONG intel Semiconductor Ltd 32 F Two Pacific Place 88 Queensway Central Tel 852 844 4555 CANADA Intel Semiconductor of Canada Lid 190 Attwell Drive Suite 500 Rexdale Ontario M9W 6H8 Tel 416 675 2105 Printed in USA 5K 0395 RRD MV
45. efined as write Write read is one of the primary bus cycle definition pins It is driven valid in the same clock as the ADS signal is asserted W R distinguishes between write and read cycles UN The Pentium processor 75 90 100 120 has 53 3 3V power inputs EN The Pentium processor 75 90 100 120 has 53 ground inputs n Mi WB WT back or write through on a line by line basis As a result it determines whether a cache line is initially in the 5 or E state in the data cache The pins are classified as Input or Output based on their function in Master Mode See the Functional Redundancy Checking section in the Error Detection chapter of the Pentium Family User s Manual Vol 1 for further information 20 intel PENTIUM PROCESSOR 75 90 100 120 2 4 Pin Reference Tables Table 3 Output Pins Active Level M IO D C W R High Bus Hold BOFF NNNM NOTES All output and input output pins are floated during tristate test mode and checker mode except ERR These are I O signals when two Pentium processors 75 90 100 120 are operating in dual processing mode These signals are undefined when the CPU is configured as a Dual Processor 21 PENTIUM PROCESSOR 75 90 100 120 intel l Table 4 Input Pins net Per Synchronous RESET aus Sate Ta Low BF i Bus State T2
46. ega part num ber 5TC TTK 36 36 e Attach the thermocouple bead or junction to the center of the package top surface using high thermal conductivity cements The laboratory testing was done by using number 100 intel The thermocouple should be attached at a 90 de gree angle as shown in Figure 14 e The hole size should be smaller than 0 150 in diameter 5 1 1 THERMAL EQUATIONS AND DATA For the Pentium processor 75 90 100 120 an am bient temperature TA air temperature around the processor is not specified directly The only restric tion is that Tc is met To calculate TA values the following equations may be used TA Tc P ca where TA and Tc ambient and case temperature case to ambient thermal resistance C Watt 0JA junction to ambient thermal resist ance C Watt 0Jc junction to case thermal resistance C Watt P maximum power consumption Watt Table 21 lists the for Pentium 5 sor 75 90 100 120 with passive heat sinks Figure 15 shows Table 21 in graphic format 241997 13 Figure 14 Technique for Measuring TC 54 intel PENTIUM PROCESSOR 75 90 100 120 Table 21 Thermal Resistances for Packages with Spreader OcA C Watt vs Laminar Airflow linear ft Heat Sink Inches jud ME RN o 10 09
47. ency EN teod PICCLK Low Time EI PICCLK Rise Time PICCLK Fall Time To PICCLK To PICCLK ojo o oi oio gU olo olo ojo 313 1J3 1313 2 15 teon PICDO 1 Hold Time 160 teod 160 PICDO 1 Valid Delay 4 0 38 0 From PICCLK 28 29 PICDO 1 Valid Delay HtoL 4 0 22 0 nS 5 From PICCLK 28 29 160 33 PENTIUM PROCESSOR 75 90 100 120 intel Table 13 Pentium Processor 610175 8151100 Dual Processor Mode AC Specifications for 50 MHz Bus Operation 3 135 lt Vcc lt 3 465V Tcase Oto 70 C 0 pF O 2 0 i PBREQ PBGNT HoldTime 1 ASAD Setup Time 0 SCYC Setup Time ts ADS D C W R CACHE LOCK A5 A31 HLDA HIT HITM SCYC Hold Time DPEN Valid Time DPEN Hold Time B el APIC ID BEO 4 BE3 Setup Time APIC ID 4 Hold Time ka D P Valid Delay 1 0 18 19 23 18 20 23 RESET falling edge 23 From RESET falling edge 23 Primary Processor Only mh ah o o o o m gt 5 42 e ni 34 i intel PENTIUM PROCESSOR 75 90 100 120 3 4 5 2 Timing Tables for 60 MHz Bus All timings are referenced to 1 5V for both 0 and 1 logic levels unless otherwise specified Within The AC specifications given in Tables 14 and 15 the sampling window a synchronous
48. erforming a lookup to the internal caches or driving a memory cycle on the bus The effect of A20M is undefined in protected mode A20M must be asserted only when the processor is in real mode A20M is internally masked by the Pentium processor 75 90 100 120 when A31 A3 MO the physical area of memory or 1 0 accessed The external system drives the inquire address to the processor on A31 A5 ADS The address status indicates that a new valid bus cycle is currently being driven by the Pentium processor 75 90 100 120 ADSC 05 is functionally identical to ADS AHOLD In response to the assertion of address hold the Pentium processor 75 90 100 120 will stop driving the address lines A31 A3 and AP in the next clock The rest of the bus will remain active so data can be returned or driven for previously issued configured as Dual processor bus cycles APICEN As outputs the address lines of the processor along with the byte enables define Address parity is driven by the Pentium processor 75 90 100 120 with even parity information on all Pentium processor 75 90 100 120 generated cycles in the same clock that the address is driven Even parity must be driven back to the Pentium processor 75 90 100 120 during inquire cycles on this pin in the same clock as EADS to ensure that correct parity check status is indicated by the Pentium processor 75 90 100 120 The a
49. errors internal parity errors and functional redundancy errors If a parity error occurs on a read from an internal array the Pentium processor 75 90 100 120 will assert the IERR pin for one clock and then shutdown If the Pentium processor 75 90 100 120 is configured as a checker and a mismatch occurs between the value sampled on the pins and the corresponding value computed internally the Pentium processor 75 90 100 120 will assert IERR two clocks after the mismatched value is returned IGNNE INIT INTR LINTO This is the ignore numeric error input This pin has no effect when the NE bit in CRO is set to 1 When the CRO NE bit is 0 and the IGNNE pin is asserted the Pentium processor 75 90 100 120 will ignore any pending unmasked numeric exception and continue executing floating point instructions for the entire duration that this pin is asserted When the CRO NE bit is 0 IGNNE is not asserted a pending unmasked numeric exception exists SW ES 1 and the floating point instruction is one of FINIT FCLEX FSTENV FSAVE FSTSW FSTCW FENI FDISI or FSETPM the Pentium processor 75 90 100 120 will execute the instruction in spite of the pending exception When the CRO NE bit is 0 IGNNE is not asserted a pending unmasked numeric exception exists SW ES 1 and the floating point instruction is one other than FINIT FCLEX FSTENV FSAVE FSTSW FSTOW FENI FDISI or FSETPM the Pentium processor 75 90 100 120 will stop e
50. et 5 when used as single socket turbo upgrade 58 intel 6 2 1 PIN DIAGRAMS 6 2 1 1 Socket 5 Pinout For systems with a single socket for the Pentium processor 75 90 100 120 and Future Pentium OverDrive processor the following pinout must be followed for the single socket location Note that to be Intel Verified for a Future Pentium OverDrive processor this must be a ZIF socket The socket footprint contains Vcc and Vss pins that internal no connects on the Pentium processor 75 90 100 120 These pins must be connected to the appropriate PCB power and ground layers to ensure Future Pentium OverDrive processor compatibility Iri PENTIUM PROCESSOR 75 90 100 120 5 6 7 8 9 10 1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2 30 31 32 33 34 35 36 37 PLUG VSS D41 vee vec vcc vec vec ycc ycc vec vcc ycc 022 043 vss vss vss vss vss vss vss vss vss vss vss vss 020 ves 047 045 038 036 034 032 031 029 027 025 DP2 0 4 021 017 o o 050 048 044 040 039 037 035 033 030 028 026 023 019 DP1 D12 054 052 049 046 042 933 vss vec NC 33 33 NC vec 88 vss 07 o DP6 051 DP5 PLUG D5 o vce D55 053 D3 01 vec VSS D56 PLUG PICCLK V88
51. etermined using a worst case instruction mix and 5 Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes For more information refer to section 3 4 3 26 Y intel A PENTIUM PROCESSOR 75 90 100 120 Table 9 3 3V 5V Safe DC Specifications NOTES 1 Applies to CLK and PICCLK only V TTL Level 1 TTL Level 1 Table 10 Input and Output Characteristics 0 lt Vin lt Vocat 0 lt lt Vocal NOTES 1 This parameter is for input without pullup or pulldown 2 This parameter is for input with pullup 3 This parameter is for input with pulldown 4 Guaranteed by design 27 PENTIUM PROCESSOR 75 90 100 120 intel Table 11 Preliminary Power Requirements for Thermal Solution Design Active Power Dissipation Stop Grant and Auto Halt Powerdown Power Dissipation 120 MHz 100 MHz 90 MHz 75 MHz 120 MHz 100 MHz 3 90 MHz 3 75 MHz NOTES 1 This is the typical power dissipation in a system This value was the average value measured in a system using a typical device at Vcc 3 3V running typical applications This value is highly dependent upon the specific system configuration 2 Systems must be designed to thermally dissipate the maximum active power dissipation It is determined using worst case instruction mix with
52. g bus cycles NMI LINT1 PBGNT non maskable interrupt request signal indicates that an external maskable interrupt has been generated If the local APIC is enabled this pin becomes local interrupt 1 Private bus grant is the grant line that is used when two Pentium processors 75 90 100 120 are configured in dual processing mode in order to perform private bus arbitration PBGNT should be left unconnected if only one Pentium processor 75 90 100 120 exists in a system Private bus request is the request line that is used when two Pentium processors 75 90 100 120 are configured in dual processing mode in order to perform private bus arbitration PBREQ should be left unconnected if only one Pentium processor 75 90 100 120 exists in a system The page cache disable pin reflects the state of the PCD bit in CR3 the Page Directory Entry or the Page Table Entry The purpose of PCD is to provide an external cacheability indication on a page by page basis M IO The memory input output is one o f the primary bus cycle definition pins It is driven valid in the same clock as the ADS signal is asserted M IO distinguishes between memory and I O cycles 17 PENTIUM PROCESSOR 75 90 100 120 intel PHIT MO PHITM MO PICCLK Table 2 Quick Pin Reference Contd The parity check output indicates the result of a parity check on a data read It is driven with parity status t
53. he minimum air space above the fan heatsink A 0 2 clearance around three of four sides of the package is also required to allow free airflow through the fan heatsink 62 A 0 9 070202099090 00 00000 0 0 2695 9 OX O 5959050 OU OO Q 45 CHAMFER 2 29 pgp INDEX CORNER 1 52 ET PENTIUM PROCESSOR 75 90 100 120 lt SEATING PLANE gt L lt heat sink fan alr space 0205020205050505550 gt YO 000 x 241997 16 Figure 18 Future Pentium OverDrive Processor Package Dimensions 6 6 Thermal Specifications The Future Pentium OverDrive processor will be cooled with a fan heatsink cooling solution The Fu ture Pentium OverDrive processor with a fan heat sink is specified for proper operation when Ta air temperature entering the fan heatsink is a maxi mum of 45 C When the Ta max lt 45 C specifica tion is met the fan heatsink will keep Tc case tem perature within the specified range of 0 C to 70 C provided airflow through the fan heatsink is unim peded 6 7 Upgradability with Socket 5 6 7 1 INTRODUCTION e Built in upgradability for Pentium processor 75 90 100 120 based systems Supports the Future Pentium OverDrive proc essor 320 pin socket Socket
54. ing edge of RESET to determine if Socket 5 is occupied DPEN shares a pin with PICDO DP7 DPO MO DPEN 1 PICDO This signal indicates that a valid external address has been driven onto the Pentium processor 75 90 100 120 address pins to be used for an inquire cycle i The external write buffer empty input when inactive high indicates that a write cycle is pending in the external system When the Pentium processor 75 90 100 120 generates a write and EWBE is sampled inactive the Pentium processor 75 90 100 120 will hold off all subsequent writes to all E or M state lines in the data cache until all write cycles have completed as indicated by EWBE being active 14 m intel PENTIUM PROCESSOR 75 90 100 120 Table 2 Quick Pin Reference Contd Symbol Name and Function FERR The floating point error is driven active when unmasked floating point error occurs FERR is similar to the ERROR pin on the Intel387TM math coprocessor FLUSH FERR is included for compatibility with systems using DOS type floating point error FRCMC reporting FERR is never driven active the Dual processor l When asserted the cache flush input forces the Pentium processor 75 90 100 120 to write back all modified lines in the data cache and invalidate its internal caches A Flush Acknowledge special cycle will be generated by the Pentium
55. input must be consist of output delays input setup requirements stable for correct Pentium processor 75 90 100 and input hold requirements for a 60 MHz external 120 operation bus All AC specifications with the exception of those for the TAP signals and APIC signals are rela tive to the rising edge of the CLK input Table 14 Pentium Processor 735190 AC Specifications for 60 MHz Bus Operation 3 135 lt Voc lt 3 465V Oto 70 C CL O pF Symbol Parameter Max Unit Figure Notes Frequency 800 4 5 te te Coupe e s a 212 2 2 5 5 2 2 3 13 2 CLK Fall Time 2 0V 0 8V 1 5 CLK Rise Time 0 1 0 8V 2 0V 1 5 Ts 1 ns O 2 ADS ADSC PWT PCD BEO 7 M IO D C CACHE W R Valid Delay uc Tes AP Vaid Delay ee LOCKA Vaid Delay 1a tib 2 3 4 5 l6a 165 6c t7 ADS ADSC AP A3 A31 PWT tgb tob 42 N N o 5 PCD BEO 7 D C W R CACHE SCYC LOCK Float Delay O ak APCHK IERR FERR Valid Delay PCHK Valid Delay ojo N n t t t t t SMIACT Valid Delay Valid Delay HITM Valid Delay BREQ HLDA Valid Delay ab tua PMO 1 BPO
56. ins are configured as breakpoint or performance monitoring pins The pins come out of RESET configured for performance monitoring The burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the Pentium processor 75 90 100 120 data in response to a write request This signal is sampled in the T2 T12 and T2P bus states This signal has the same functionality as BRDY The bus request output indicates to the external system that the Pentium processor 75 90 100 120 has internally generated a bus request This signal is always driven whether or not the Pentium processor 75 90 100 120 is driving its bus The bus check input allows the system to signal an unsuccessful completion of a bus cycle If this pin is sampled active the Pentium processor 75 90 100 120 will latch the address and control signals in the machine check registers If in addition the MCE bit in CR4 is set the Pentium processor 75 90 100 120 will vector to the machine check exception For Pentium processor 75 90 100 120 initiated cycles the cache pin indicates internal cacheability of the cycle if a read and indicates a burst write back cycle if a write If this pin is driven inactive during a read cycle the Pentium processor 75 90 100 120 will not cache the returned data regardless of the state of the KEN pin This pin is also used
57. intel PENTIUM PROCESSOR at iCOMP INDEX 610 75 MHz PENTIUM PROCESSOR at iCOMP INDEX 735 90 MHz PENTIUM PROCESSOR at iCOMP INDEX 815 100 MHz PENTIUM PROCESSOR at iCOMP INDEX 1000 120 MHz Compatible with Large Software Base Multi Processor Support MS DOS Windows 05 21 UNIX Multiprocessor Instructions m 32 Bit CPU with 64 Bit Data Bus Support for Second Level Cache Superscalar Architecture Two Pipelined Integer Units Are E Bong Com D e m Capable of 2 Instructions Clock ompatibie Pipelined Floating Point Unit Internal Error Detection Features Separate Code and Data Caches Upgradable with a Future Pentium 8K Code 8K Write Back Data OverDrive Processor MESI Cache Protocol m Advanced Design Features Branch Prediction Virtual Mode Extensions 3 3V BiCMOS Silicon Technology 4M Pages for Increased TLB Hit Rate IEEE 1149 1 Boundary Scan Dual Processing Configuration m Power Management Features System Management Mode Clock Control Fractional Bus Operation 120 MHz Core 60 MHz Bus 100 MHz Core 66 MHz Bus 100 MHz Core 50 MHz Bus 90 MHz Core 60 MHz Bus 75 MHz 50 2 Bus The Pentium processor 75 90 100 120 extends the Pentium processor family providing performance need ed for mainstream desktop applications as well as for workstations and servers The Pentium processor is compatible with the entire installed b
58. ion 3 135 lt Vcc lt 3 465V Oto 70 C 0 pF Symbol Parameter sop PHIT PHITM FightTime PEGNT Soup Time En 5 5 42 oe Setup Time t5 ws HIT SoupTime 80 tese HLDASetupTime 60 ADS D C W R M IO CACHE LOCK A5 A31 HLDA HIT Deene 5 ala n 2 S S S S n et A 2 oio SCYC Hold Time 18 19 23 187 APIC ID BEO BE3 Setup Time 2 0 CLKs To RESET falling edge 23 88 APIC ID BEO BE3 Hold Time 2 0 CLKs From RESET falling edge 23 55 1 0 nS D P Valid Delay NOTES Notes 2 6 and 14 are general and apply to all standard TTL signals used with the Pentium Processor family 1 Not 10095 tested Guaranteed by design characterization 2 TTL input test waveforms are assumed to be 0 to 3V transitions with 1V nS rise and fall times 3 Non test outputs and inputs are the normal output or input signals besides TCK TRST TDI TDO and TMS These timings correspond to the response of these signals due to boundary scan operations 4 APCHK FERR HLDA IERR LOCK and PCHK are glitch free outputs Glitch free signals monotonically tran sition without false transitions i e glitches 5 0 8V ns lt CLK input rise fall time lt 8V ns 6 0 3V ns lt input rise fall time x 5V ns
59. le 7 Pin Functional Grouping Clock Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error L RESET INIT A31 A3 BE7 4 BEO A20M D63 DO AP PICCLK PICDO 1 DP7 DPO PCHK PEN 4 IERR BUSCHK M IO D C W R CACHE 5 LOCK ADS ADSC BRDY 4 BRDYC PCD PWT KEN WB WT _ AHOLD EADS HIT HITM INV FLUSH EWBE BOFF BREQ HOLD HLDA A System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping Consistency Cache Flush Write Ordering Bus Arbitration Dual Processing Private Bus Control PBGNT PBREQ PHIT INTR NMI FERR IGNNE _ SMIACT FRCMC IERR TMS TDI TRST PMO BPO PM1 BP1 BP3 2 1 STPCLK Miscellaneous Dual Processing CPUTYP D P Probe Mode R S PRDY Interrupts Floating Point Error Reporting System Management Mode Functional Redundancy Checking TAP Port Breakpoint Performance Monitoring Power Management 4 intel 3 0 ELECTRICAL SPECIFICATIONS This section describes the electrical differences be tween the Pentium processor 60 66 and the Penti um processor 75 90 100 120 and the DC and AC specifications 3 1 Electrical Differences Between Pentium Processor 75 90 100 120 and Pentium Processor 60 66 Difference in Pentium Processor 75 90 100 120
60. lity TC 65 intel 1 0 MICROPROCESSOR ARCHITECTURE OVERVIEW The Pentium processor at iCOMP rating 610 75 MHz iCOMP rating 735 90 MHz and iCOMP rating 815 100 MHz extends the Intel Penti um family of microprocessors It is 100 binary compatible with the 8086 88 80286 Intel886 DX CPU Intel386 SX CPU Intel486 DX CPU Intel486 SX CPU Intel486 DX2 CPUs and Pentium proces sor at iCOMP Index 510 60 MHz and iCOMP Index 567 66 MHz The Pentium processor family consists of the Penti um processor at iCOMP rating 610 75 MHz iCOMP rating 735 90 MHz and iCOMP rating 815 100 MHz product order code 80502 described in this docu ment and the original Pentium processor 60 66 or der code 80501 The name Pentium processor 75 90 100 120 will be used in this document to refer to the Pentium processor at iCOMP rating 610 75 MHz iCOMP rating 735 90 MHz iCOMP rating 815 100 MHz and iCOMP rating 1000 120 MHz Also the name Pentium processor 60 66 will be used to refer to the original 60 and 66 MHz version product The Pentium processor family architecture contains all of the features of the Intel486 CPU family and provides significant enhancements and additions in cluding the following e Superscalar Architecture e Dynamic Branch Prediction e Pipelined Floating Point Unit e Improved Instruction Execution Time e Separate 8K Code and 8K Data Caches e Writeback MESI Protocol in the Data Ca
61. m The APIC interrupt controller serial data bus clock is driven into the programmable interrupt controller clock input of the Pentium processor 75 90 100 120 PICDO 1 Programmable interrupt controller data lines 0 1 of the Pentium processor 75 DPEN 90 100 120 comprise the data portion of the APIC 3 wire bus They are open drain APICEN outputs that require external pull up resistors These signals share pins with DPEN and APICEN These pins function as part of the performance monitoring feature The breakpoint 1 0 pins are multiplexed with the performance monitoring 1 0 pins The PB1 and PBO bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins The pins come out of RESET configured for performance monitoring The probe ready output pin indicates that the processor has stopped normal execution in response to the R S pin going active or Probe Mode being entered The page write through pin reflects the state of the PWT bit in CR3 the page directory entry or the page table entry The PWT pin is used to provide an external write back indication on a page by page basis PM BP 1 0 PRDY lt 18 intel PENTIUM PROCESSOR 75 90 100 120 Table 2 Quick Pin Reference Contd Symbol Name and Function R S The run stop input is an asynchronous edge sensitive interrupt used to stop the normal execution of the processor a
62. m 1 ms assertion of RESET BOFF Additionally BF must not change values while RESET is active For proper operation of the Pentium processor 75 90 100 120 this pin should be strapped high BP 3 2 PM BP 1 0 or low When BF is strapped to Vcc the processor will operate at a 2 3 bus core BRDY frequency ratio When BF is strapped to Vss the processor will operate at a 1 2 BRDYC bus core frequency ratio If BF is left floating the Pentium processor 75 90 100 BREQ 120 defaults to a 2 3 bus ratio Note that core operation at either 75 MHz or 90 MHz does not allow 1 2 bus core frequency while core operation at 120 MHz does not BUSCHK CACHE allow 2 3 bus core frequency The backoff input is used to abort all outstanding bus cycles that have not yet completed In response to BOFF the Pentium processor 75 90 100 120 will float all pins normally floated during bus hold in the next clock The processor remains in bus hold until BOFF is negated at which time the Pentium processor 75 90 100 120 restarts the aborted bus cycle s in their entirety The breakpoint pins BP3 0 correspond to the debug registers DR3 DRO These pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches BP1 and BPO are multiplexed with the performance monitoring pins PM1 and PMO The PB1 and PBO bits in the Debug Mode Control Register determine if the p
63. nd specifications and decoupling recommendations as the Pentium processor 75 90 100 120 6 3 1 5 PIN DEFINITION The Future Pentium OverDrive processor pinout contains two 5V Vcc pins Vccs used to provide power to the fan heatsink These pins should be connected to 5V 5 regardless of the system design Failure to connect Vccs to 5V may cause the component to shut down 6 4 Absolute Maximum Ratings of Upgrade The on chip Voltage Regulation and fan heatsink devices included with the Future Pentium OverDrive processor require different stress ratings than the Pentium processor 75 90 100 120 The voltage regulator is surface mounted on the Future Pentium OverDrive processor and is therefore an integral part of the assembly The Future Pentium OverDrive processor storage temperature ratings are tightened as a result The fan is a detachable unit and the storage temperature is stated separately in the table below Functional operation of the Future Pentium OverDrive processor remains 0 C to 70 C intel PENTIUM PROCESSOR 75 90 100 120 Future Pentium OverDrive Processor and WARNING Stressing the device beyond the Ab Voltage Regulator Assembly solute Maximum Ratings may cause permanent 3 damage These are stress ratings only Operation Storage Temperature 30 C to 100 C beyond the Operating Conditions is not recom Case Temperature Under Bias 30 C to 100 C mended and extended
64. nd place it into an idle state A high to low RESET transition on the R S pin will interrupt the processor and cause it to stop execution n M RESET forces the Pentium processor 75 90 100 120 to begin execution at a known state All the Pentium processor 75 90 100 120 internal caches will be invalidated upon the RESET Modified lines in the data cache are not written back FLUSH FRCMC and INIT are sampled when RESET transitions from high to low to determine if tristate test mode or checker mode will be entered or if BIST will be run The split cycle output is asserted during misaligned LOCKed transfers to indicate that more than two cycles will be locked together This signal is defined for locked cycles only It is undefined for cycles which are not locked The system management interrupt causes a system management interrupt request to be latched internally When the latched SMI is recognized on an instruction boundary the processor enters System Management Mode An active system management interrupt active output indicates that the processor is operating in System Management Mode Assertion of the stop clock input signifies a request to stop the internal clock of the Pentium processor 75 90 100 120 thereby causing the core to consume less power When the CPU recognizes STPCLK the processor will stop execution on the next at the next instruction boundary SMIACT STPCLK in
65. r 75 90 100 120 based systems The Fu ture Pentium OverDrive processor will speed up most software applications by 40 to 70 It is bi nary compatible with the Pentium processor 75 90 100 120 An upgrade socket Socket 5 has been defined along with the Pentium processor 75 90 100 120 as part of the processor architecture Upgradability can be supported by implementing either a single Socket or a dual socket strategy for Pentium proces sor 75 90 100 120 based systems A single socket system will include a 320 pin SPGA Socket 5 When this system configuration is upgraded the Pentium processor 75 90 100 120 is simply replaced by the Future Pentium OverDrive processor A dual socket system will include a 296 pin SPGA socket for the Pentium processor 75 90 100 120 and a 320 pin SPGA Socket 5 for the second processor In dual Socket systems Socket 5 can be filled with either the Dual processor or the Future Pentium OverDrive processor 6 1 1 UPGRADE OBJECTIVES Systems using the Pentium processor 75 90 100 120 and equipped with only one processor socket must use socket 5 to also accept the Future Pentium OverDrive processor Systems equipped with two processor sockets must use Socket 5 as the second socket to contain either the Pentium processor 75 90 100 120 Dual processor or the Future Pentium OverDrive processor Inclusion of Socket 5 in Pentium processor 75 90 100 120 systems provides the end user with an easy and cost effecti
66. remain unconnected Connection of NC pins may result in component fail ure or incompatibility with processor steppings 2 3 Quick Pin Reference This section gives a brief functional description of each of the pins For a detailed description see the Hardware Interface chapter in the PentiumTMt Family User s Manual Volume 1 Note that all input pins must meet their AC DC specifications to guarantee proper functional behavior NC INC S35 W35 ALO1 ANO1 ANOS W33 X34 AL19 ANO3 5 The symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage When symbol is not present after the signal name the signal is active or asserted at the high voltage level The following pins exist on the Pentium processor 60 66 but have been removed from the Pentium processor 75 90 100 120 IBT IU IV BTO 3 The following pins become I O pins when two Pentium processors 75 90 100 120 are operating in a dual processing environment e ADS CACHE HIT HITM HLDA LOCK M IO D C W R SCYC 11 PENTIUM PROCESSOR 75 90 100 120 Table 2 Quick Pin Reference Symbol Name and Function A20M When the address bit 20 mask pin is asserted the Pentium processor 75 90 100 120 emulates the address wraparound at 1 Mbyte which occurs on the 8086 When A20M is asserted the Pentium processor 75 90 100 120 masks physical address bit 20 A20 before p
67. round connec tions must be made to all external and Vss pins of the Pentium processor 75 90 100 120 On the circuit board all Vcc pins must be connected to a 3 3V plane All Ves pins must be connected to a Vss plane 3 4 3 DECOUPLING RECOMMENDATIONS Liberal decoupling capacitance should be placed near the Pentium processor 75 90 100 120 The Pentium processor 75 90 100 120 driving its large address and data buses at high frequencies can cause transient power surges particularly when driv ing large capacitive loads Low inductance capacitors and interconnects are recommended for best high frequency electrical per formance Inductance can be reduced by shortening circuit board traces between the Pentium processor 75 90 100 120 and decoupling capacitors as much as possible These capacitors should be evenly distributed around each component on the 3 3V plane Capaci tor values should be chosen to ensure they elimi nate both low and high frequency noise compo nents intel For the Pentium processor 75 90 100 120 the power consumption can transition from a low level of power to a much higher level or high to low power very rapidly A typical example would be entering or exiting the Stop Grant state Another example would be executing a HALT instruction causing the Penti um processor 75 90 100 120 to enter the Auto HALT Powerdown state or transitioning from HALT to the Normal state All of these examples may c
68. s D P The dual primary processor indication The Primary processor drives this pin low when it is driving the bus otherwise it drives this pin high D P is always driven D P can be sampled for the current cycle with ADS like status pin This pin is defined only on the Primary processor D63 DO These are the 64 data lines for the processor Lines D7 DO define the least significant byte of the data bus lines D63 D56 define the most significant byte of the data bus When the CPU is driving the data lines they are driven during the T2 T12 or T2P clocks for that cycle During reads the CPU samples the data bus when BRDY is returned These are the data parity pins for the processor There is one for each byte of the data bus They are driven by the Pentium processor 75 90 100 120 with even parity information on writes in the same clock as write data Even parity information must be driven back to the Pentium processor 75 90 100 120 on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the Pentium processor 75 90 100 120 DP7 applies to D63 56 DPO applies to D7 0 Dual processing enable is an output of the Dual processor and an input of the Primary processor The Dual processor drives DPEN low to the Primary processor at RESET to indicate that the Primary processor should enable dual processor mode DPEN may be sampled by the system at the fall
69. sient spec intel WARNING Stressing the device beyond the Ab solute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recom mended and extended exposure beyond the ating Conditions may affect device reliability 3 3 DC Specifications Tables 8 9 and 10 list the DC specifications which apply to the Pentium processor 75 90 100 120 The Pentium processor 75 90 100 120 is a 3 3V part internally The CLK and PICCLK inputs may be 3 3V or 5V inputs Since the 3 3V 5V safe input levels defined in Table 9 are the same as the 5V TTL levels the CLK and PICCLK inputs are compatible with existing 5V clock drivers The power dissipation specification in Table 11 is provided for design of thermal solutions during operation in a sustained maximum level This is the worst case power the device would dissipate in a system This number is used for design of a thermal solution for the device Table 8 3 3V DC Preliminary Specifications 0 to 70 C 3 3 5 Input igh vaitas Output High Voltage TTL Level 3 TTL Level 3 TTL Level 1 3 TTL Level 2 3 9120 2 4 0100 MHz 4 290 2 4 975 MHz NOTES 1 Parameter measured at 4 mA 2 Parameter measured at 3 mA 3 3 3V TTL levels apply to all signals except CLK and PICCLK 4 This value should be used for power supply design It was d
70. signals to select buffer size This assumes an external pullup resistor to Vcc and a lumped capacitive load such that the maximum RC product does not exceed H 1500 C 240 pF This assumes external pullup resistor to and a lumped capacitive load such that the minimum RC product does not fall below R 1500 C 20 pF This is a flight time specification that includes both flight time and clock skew The flight time is the time from where the unloaded driver crosses 1 5V 50 of min Vcc to where the receiver crosses the 1 5V level 50 of min See Figure 11 Each valid delay is specified for a 0 pF load The system designer should use 1 0 buffer modeling to account for signal flight time delays 45 a PENTIUM PROCESSOR 75 90 100 120 intel 241997 4 t5 149 160 Tw 14 148 1604 Tx 13 147 1604 11 145 1606 Tz 12 146 160 Figure 4 Clock Waveform Tx min lt Tx max Tx t6 t8 19 110 111 112 1601 180 189 241997 5 Figure 5 Valid Delay Timings 46 B intel PENTIUM PROCESSOR 75 90 100 120 241997 6 Tx t7 t13 Ty t6min t12min Figure 6 Float Delay Timings 241997 7 Tx t14 t16 t18 t20 t22 t24 t26 128 t31 134 t60g to PICCLK t81 183 Ty 115 117 119 121 123 125 127 129 132 135 t60h to PICCLK 182 184 Figure 7 Setup and Hold Timings 47 PENTIUM PROCESSOR 75 90 10
71. struction boundary unless superseded by a higher priority interrupt and generate a stop grant acknowledge cycle When STPCLK is asserted the Pentium processor 75 90 100 120 will still respond to interprocessor and external snoop requests The testability clock input provides the clocking function for the Pentium processor 75 90 100 120 boundary scan in accordance with the IEEE Boundary Scan interface Standard 1149 1 It is used to clock state information and data into and out of the Pentium processor 75 90 100 120 during boundary scan 19 PENTIUM PROCESSOR 75 90 100 120 intel Table 2 Quick Pin Reference Contd Symbol Name and Function TDI The test data input is a serial input for the test logic TAP instructions and data are shifted into the Pentium processor 75 90 100 120 on the TDI pin on the rising edge of TCK when the TAP controller is in an appropriate state TDO The test data output is a serial output of the test logic TAP instructions and data are shifted out of the Pentium processor 75 90 100 120 on the TDO pin on TCK s falling edge when the TAP controller is in an appropriate state TMS The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP controller state changes When asserted the test reset input allows the TAP controller to be asynchronously initialized Vcc The write back write through input allows a data cache line to be d
72. support two data transfers and an inquire cycle in the same clock The code cache is an inherently write protected cache The code cache tags are also triple ported to support snooping and split line accesses Individual pages can be configured as cacheable or non cacheable by software or hard ware The caches can be enabled or disabled by software or hardware The Pentium processors have increased the data bus to 64 bits to improve the data transfer rate Burst read and burst write back cycles are supported by the Pentium processors In addition bus cycle pipe lining has been added to allow two bus cycles to be in progress simultaneously The Pentium proces sors Memory Management Unit contains optional extensions to the architecture which allow 2 Mbyte and 4 Mbyte page sizes The Pentium processors have added significant data integrity and error detection capability Data parity checking is still supported on a byte by byte basis Address parity checking and internal parity checking features have been added along with a new excep tion the machine check exception In addition the Pentium processors have implemented function al redundancy checking to provide maximum error intel detection of the processor and the interface to the processor When functional redundancy checking is used a second processor the checker is used to execute in lock step with the master processor The checker samples the master s outputs
73. tive Timings are valid only when dual processor is present Maximum time DPEN is valid from rising edge of RESET Minimum time DPEN is valid after falling edge of RESET The D C M IO W R CACHE and A5 A31 signals are sampled only on the CLK that ADS is active BF and CPUTYP should be strapped to Vcc or Vss RESET is synchronous in dual processing mode and functional redundancy checking mode All signals which have a setup or hold time with respect to a falling or rising edge of RESET in UP mode should be measured with respect to the first processor clock edge in which RESET is sampled either active or inactive in dual processing and functional redundancy checking modes The PHIT and PHITM signals operate at the core frequency 75 90 or 100 MHz These signals are measured on the rising edge of adjacent CLKs at 1 5V To ensure a 1 1 relationship between the amplitude of the input jitter and the internal and external clocks the jitter frequency spectrum should not have any power spectrum peaking between 500 KHz and 1 3 of the CLK operating frequency The amount of jitter present must be accounted for as a component of CLK skew between devices In dual processing mode timing is replaced by Timing is required for external snooping e g address setup to CLK in which EADS is sampled active in both uniprocessor and dual processor modes BRDYC and BUSCHK are used as reset configuration
74. to determine the cycle length number of transfers in the cycle 13 PENTIUM PROCESSOR 75 90 100 120 Table 2 Quick Pin Reference Contd Name and Function The clock input provides the fundamental timing for the Pentium processor 75 90 100 120 Its frequency is the operating frequency of the Pentium processor 75 90 100 120 external bus and requires TTL levels All external timing parameters except TDI TMS TRST and PICDO 1 are specified with respect to the rising edge of CLK Symbol CLK It is recommended that CLK begin toggling within 150 ms after Vcc reaches its proper operating level This recommendation is only to ensure long term reliability of the device CPUTYP CPU type distinguishes the Primary processor from the Dual processor In a single processor environment or when the Pentium processor 75 90 100 120 is acting as the Primary processor in a dual processing system CPUTYP should be strapped to Vss The Dual processor should have CPUTYP strapped to Vcc For the Future Pentium OverDrive processor CPUTYP will be used to determine whether the bootup handshake protocol will be used in a dual socket system or not in a single socket system D C The data code output is one of the primary bus cycle definition pins It is driven valid in the same clock as the ADS signal is asserted D C distinguishes between data and code or special cycle
75. ve way to increase system per formance The paradigm of simply installing an addi tional component into an easy to use Zero Insertion Force ZIF Socket to achieve enhanced system performance is familiar to the millions of end users and dealers who have purchased Intel math coproc essor upgrades to boost system floating point per formance PENTIUM PROCESSOR 75 90 100 120 The majority of upgrade installations which take ad vantage of Socket 5 will be performed by end users and resellers Therefore it is important that the de sign be end user easy and that the amount of training and technical expertise required to install the upgrade processors be minimized Upgrade in stallation instructions should be clearly described in the system user s manual In addition by making in stallation simple and foolproof PC manufacturers can reduce the risk of system damage warranty claims and service calls Feedback from Intel s math coprocessor upgrade customers highlights three main characteristics of end user easy designs e accessible socket location clear indication of upgrade component orienta tion minimization of insertion force The Future Pentium OverDrive processor will sup port the 82430NX PClset Unlike the Pentium proc essor 75 90 100 120 the Future Pentium Over Drive processor will not support the 82497 Cache Controller and 82492 Cache SRAM chip set 6 1 2 INTEL VERIFICATION PROGRAM The Intel Verifi
76. wo clocks after BRDY is returned PCHK remains low one clock for each clock in which a parity error was detected Parity is checked only for the bytes on which valid data is returned When two Pentium processors 75 90 100 120 are operating in dual processing mode PCHK may be driven two or three clocks after BRDY is returned The parity enable input along with CR4 MCE determines whether a machine check exception will be taken as a result of a data parity error a read cycle If this pin is sampled active in the clock a data parity error is detected the Pentium processor 75 90 100 120 will latch the address and contro signals of the cycle with the parity error in the machine check registers If in addition the machine check enable bit in CR4 is set to 1 the Pentium processor 75 90 100 120 will vector to the machine check exception before the beginning of the next instruction Private hit is a hit indication used when two Pentium processors 75 90 100 120 are configured in dual processing mode in order to maintain local cache coherency PHIT should be left unconnected if only one Pentium processor 75 90 100 120 exists in a system Private modified hit is a hit indication used when two Pentium processors 75 90 100 120 are configured in dual processing mode in order to maintain local cache coherency PHITM should be left unconnected if only one Pentium processor 75 90 100 120 exists in a syste
77. xecution and wait for an external interrupt IGNNE is internally masked when the Pentium processor 75 90 100 120 is configured as a Dual processor The Pentium processor 75 90 100 120 initialization input pin forces the Pentium processor 75 90 100 120 to begin execution in a known state The processor state after INIT is the same as the state after RESET except that the internal caches write buffers and floating point registers retain the values they had prior to INIT INIT may NOT be used in lieu of RESET after power up If INIT is sampled high when RESET transitions from high to low the Pentium processor 75 90 100 120 will perform built in self test prior to the start of program execution An active maskable interrupt input indicates that an external interrupt has been generated If the IF bit in the EFLAGS register is set the Pentium processor 75 90 100 120 will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed INTR must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized If the local APIC is enabled this pin becomes local interrupt 0 16 m intel a PENTIUM PROCESSOR 75 90 100 120 Table 2 Quick Pin Reference Contd Symbol Name and Function The invalidation input determines the final cache line state 5 or l in case of an inquir

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