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SN8P1929

1. Timer ADC PWM Wakeup CHIP ROM RAM LCD vO SIO TCO TC1 Bit Buzzer Pin no SN8P1908 8K 16 512 8 8 4 24 V V V 17 16 2 T LQFP64 SN8P1909 8K 16 512 8 8 4 32 Vi V V 20 16 2 1 7 LQFP80 SN8P1919 6K 16 256 8 8 4 32 V V V 22 16 2 7 LQFP80 SN8P19294K 16256 8 8 4 2 V V V 16 16 2 6 LQFP80 Table 1 1 Selection table of SN8P1929 1 2 FEATURES Memory configuration Five interrupt sources OTP ROM size 4K 16 bits RAM size 256 8 bits bank 0 bank 1 8 levels stack buffer LCD RAM size 4 24 bits VO pin configuration Input only PO Bi directional P1 P2 P4 P5 Wakeup P1 Pull up resisters PO P1 P2 P4 P5 External interrupt PO Powerful instructions Four clocks per instruction cycle All instructions are one word length Vost of instructions are 1 cycle only Maximum instruction cycle is 2 JMP instruction jumps to all ROM area All ROM area look up table function MOVC Programmable gain instrumentation amplifier Gain option 1x 12 5x 50x 100x 200x 16 bit Delta Sigma ADC with 14 bit noise free Three ADC channel configurations Two fully differential channel One differential and Two single ended channels Four single ended channels SONiX TECHNOLOGY CO LTD Three internal interrupts TO TCO TC1 Two external interrupts INTO INT1 Single power supply 2 4V 5 5V On chip watchdog timer
2. ODFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 STKPBO Read Write R W R W R W R W After reset 0 1 1 1 Bit 7 GIE Global interrupt control bit 0 Disable global interrupt 1 Enable global interrupt Example Set global interrupt control bit GIE BOBSET FGIE Enable GIE SONiX TECHNOLOGY CO LTD Page 62 Preliminary Version 0 4 Y SS Q SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Note The GIE bit must enable during all interrupt operation SONiX TECHNOLOGY CO LTD Page 63 Preliminary Version 0 4 N 7 SN8P1929 O S E 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 5 PUSH POP ROUTINE When any interrupt occurs system will jump to ORG 8 and execute interrupt service routine It is necessary to save ACC PFLAG data The chip includes PUSH for in out interrupt service routine The two instruction only save working registers 0x80 0x87 including PFLAG data into buffers The ACC data must be saved by program 1 PUSH POP instructions only process 0x80 0x87 working registers and PFLAG register Users have to save and load ACC by program as interrupt occurrence 2 The buffer of PUSH POP instruction is only one level and is independent to RAM or Stack area gt Example Store ACC and PAFLG data by PUS
3. 0 0 0 15 625K 1 27 968 1 31 25 62 5K 0 0 1 7 8125K 13 98K 15 625K 31 25K 0 1 0 3 90625K 6 99 7 8125K 15 625K 0 1 1 1 953125K 3 49K 3 90625K 7 8125K 1 0 0 976Hz 1 748 1 953125K 3 90625 1 0 1 488 2 874Hz 976 2 1 953125 1 1 0 244Hz 437 2 488 2 976Hz 1 1 1 122Hz 218Hz 244Hz 488Hz Note In general application set PGIA Chopper working clock is 2K Hz but set clock to 250Hz when High clock is 32768 crystal or in Internal Low clock mode SONiX TECHNOLOGY CO LTD Page 120 Preliminary Version 0 4 SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 11 4 3 AMPCHS PGIA CHANNEL SELECTION 091H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AMPCHS CHS3 CHS2 CHS1 50 R W R W R W R W R W After Reset 0 0 0 0 CHS 3 0 PGIA Channel Selection CHS 3 0 Selected Channel V X X Output Input Signal Type 0000 Alt AI1 V Al1 Al1 x PGIA Gain Differential 0001 Al2 Al2 V Al2 Al2 x PGIA Gain Differential 0010 Ali ACM V Al1 ACM x PGIA Gain Single ended 0011 1 ACM V Al1 ACM x PGIA Gain Single ended 0100 Al2 ACM V Al2 ACM x PGIA Gain Single ended 0101 Al2 ACM V Al2 ACM x PGIA Gain Single ended 0110 ACM ACM V ACM ACM x PGIA Gain Input Short 0111 Reserved N A N A 1000 ViVis 08V Others R
4. ADCDL 7 0 Output low byte data of ADC conversion word ADCDH 7 0 Output high byte data of ADC conversion word gt Notet ADCDL 7 0 and ADCDH 7 0 are both read only registers gt 2 ADC conversion dala is combined with ADCDH ADCDL 2 s compliment with sign bit numerical format and Bit ADCB15 is the sign bit of ADC data ADCB15 0 means data is Positive value ADCB15 1 means data is Negative value VNN ADC output must keep inside this range Note3 The Positive Full Scale Output value of ADC conversion is 0x7A12 Note4 The Negative Full Scale Output value of ADC conversion is Ox85EE Note5 Because of the ADC design limitation the ADC Linear range is 28125 28125 decimal The MAX ADC conversion data Decimal Value 2 s compliment Hexadecimal Ox7A12 31250 0x4000 16384 0x1000 4096 0x0002 2 0x0001 1 0 0000 0 1 OxFFFE 2 OxF000 4096 0 000 16384 Ox85EE 31250 SONiX TECHNOLOGY CO LTD Page 129 Preliminary Version 0 4 SONIN 11 5 5 DFM ADC Digital Filter Mode Register SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 097H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DFM WRSO DRDY R W R W After Reset 0 0 Bito DRDY ADC Data Ready Bit 1 ADC output update new conversion
5. 3 6 3 Zener Diode Reset Circuit R1 33K ohm R3 40K ohm The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely Use zener voltage to be the active level When VDD voltage level is above Vz 0 7V the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below Vz 0 7V the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by zener specification Select the right zener voltage to conform the application SONiX TECHNOLOGY CO LTD Page 44 Preliminary Version 0 4 SN8P1929 N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 6 4 Voltage Bias Reset Circuit The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely The operating voltage is not accurate as zener diode reset circuit Use R1 R2 bias voltage to be the active level When VDD voltage level is above or equal to 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by R1 R2 resistances Select the right R1 R2 value to conform the application In the circuit diagram condition the MCU s reset p
6. 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG NTO NPD C DC Z Read Write R W R W R W R W R W After reset 0 0 0 Bit 7 6 NPD Reset status flag Condition Description Reserved Watchdog reset Watchdog timer overflow Power on reset and LVD reset Power voltage is lower than LVD detecting level External reset External reset pin detect low level status Finishing any reset sequence needs some time The system provides complete procedures to make the power on reset successful For different oscillator types the reset time is different That causes the VDD rise rate and start up time of different oscillator is not fixed RC type oscillator s start up time is very short but the crystal type is longer Under client terminal application users have to take care the power on reset time for the master terminal requirement The reset timing diagram is as following VDD LVD Detect Level Power yas VDD External Reset vss External Reset External Reset High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset watchdog stop System Normal Run System Status s stop PowerOn External Watchdog Delay Time ResetDelay Reset Delay Time Time SONiX TECHNOLOGY CO LTD Page 38 Preliminary Version 0 4
7. Figure 1 1 Simplified system block diagram SONiX TECHNOLOGY CO LTD Page 7 AVDDCP AVDDR AVE Al Al LBTIN2 1 R R Preliminary Version 0 1 SONIN 1 4 PIN ASSIGNMENT SN8P1929 LQFP80 SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC COM1 COMO VLCD V3 V2 V1 R R X X Al2 AI2 Al1 Al1 AVSS ACM AVDDR AVE AVDDCP NC NMornnontgnonnoaeenene eS 2 0000 00000000 0 0 0 0 0 0 0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 10 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 SN8 P1929 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 226898252588 2069222 gt gt 502528 gt 22850 lt S5REF2 E Nn p 0 an Page 8 SONiX TECHNOLOGY CO LTD Preliminary Version 0 1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 NC NC RESET VPP VSS P5 4 PWMO0 BZO P5 3 PWM1 BZ1 5 2 P5 1 P5 0 P4 2 LBTIN2 P4 1 LBTIN1 P4 0 NC NC SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 5 PIN DESCRIPTIONS TYPE DESCRIPTION VDD VSS AVSS P supply input pins for digital analog circuit VLCD P Power supply input Regulator power ou
8. A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 marking Definition 17 1 INTRODUCTION There are many different types in Sonix 8 bit MCU production line This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 17 2 MARKING IDENTIFICATION SYSTEM SN8 X PartNo X X X B PB Free Package Ly Material G Green Package Temperature 0 C 70 C Range D 40 C 85 C Shipping W Wafer Package H Dice F LQFP Device 1929 ROM Type P OTP Title 8 bit MCU Production SONiX TECHNOLOGY CO LTD Page 152 Preliminary Version 0 4 SONIN 17 3 MARKING EXAMPLE SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Name ROM Type Device Package Temperature Material SN8P1929FB OTP 1929 LQFP 0C 70C PB Free Package SN8P1929FG OTP 1929 LQFP 0C 70 C Green Package 17 4 DATECODE SYSTEM XX X X XXXXX Internal Use Day Month Year SONiX TECHNOLOGY CO LTD Page 153 1 January 2 February 9 September A October B November C December 03 2003 04 2004 05 2005 06 2006 Preliminary Version 0 4 N SN8P1929 D B 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX d
9. 2 1 Fopu 2 Bit6 WDRST Watchdog timer reset bit 0 Noreset 1 7 clear the watchdog timer s counter The detail information is in watchdog timer chapter Bit7 WTCKS Watchdog clock source select bit 0 Fceu 1 internal RC low clock Watchdog timer overflow table WTCKS WTRATE CLKMD Watchdog Timer Overflow Time 1 fopu 2 16 1 fcpu 2 16 1 fcpu 2 16 EG B XE 1s Fosc 16KHZ 3V 16K 512 16 0 55 93V 293 ms Fosc 3 58MHz 500 ms Fosc 32768Hz 65 55 Fosc 16KHZ 3V Note The watchdog timer be enabled or disabled by the code option SONiX TECHNOLOGY CO LTD Page 75 Preliminary Version 0 4 N SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Watchdog timer application note is as following Before clearing watchdog timer check I O status and check RAM contents can improve system error clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function gt Example An operation of watchdog timer is as following To clear the watchdog timer counter in the top of the main routine of the program Main Check jos Check RAM Err JMP or RAM error Program ju
10. After compiling program ROM address BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X0100 JMP AOPOINT ACC 0 jump to AOPOINT 0X0101 JMP A1POINT ACC 1 jump to ATPOINT 0X0102 JMP A2POINT ACC 2 jump to A2POINT 0X0103 JMP A3POINT ACC 3 jump to A3POINT 0X0104 JMP AAPOINT ACC 4 jump to A4POINT SONiX TECHNOLOGY CO LTD Page 18 Preliminary Version 0 1 SONIN 2 1 2 4 CHECKSUM CALCULATION SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC The last ROM address is reserved area User should avoid these addresses last address when calculate the Checksum value gt Example The demo program shows how to calculated Checksum from to the end of user s code MOV A SEND USER CODES L BOMOV END ADDR1 A Save low end address to end addr1 MOV USER CODE M BOMOV END ADDR2 A Save middle end address to end addr2 CLR Y Set Y to 00H CLR 2 Set Z to 00H MOVC BOBSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV ADC DATA2 A Add R to Data2 JMP END CHECK Check if the YZ address the end of code AAA INCMS 2 2 2 1 JMP B If Z calculate to next address JMP Y ADD 1 If Z increase Y END CHECK MOV A END ADDR1 CMPRS 2 Check if Z low end address JMP AAA If Not jump to checksum calculate MOV A END ADDR2 CMPRS A Y If Yes check if Y middle end address JMP
11. 73 3 3 I O PORT DATA REGISTER rociero eren i trit 74 3 4 TIMER O 77 3 4 1 OVERVIEW 2E 77 3 4 2 TOM MODE REGISTER esie ecetelesUrstepede te roh 78 3 4 3 TOC COUNTING 202000000000000 79 3 4 4 TO TIMER OPERATION SEQUENCE eicit 80 EE O i D DI d DTA N PE EE 105 4 1 LCDM1 REGISTER 105 4 2 OPTION REGISTER 105 4 3 2 106 4 4 LCD RAM 108 4 5 EOD ECCE 109 5 CHARGE PUMP PGIA AND ADC 114 SONiX TECHNOLOGY CO LTD Page 3 Preliminary Version 0 1 N SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 1 OVERVIEW 114 52 ANALOG INPUT per 114 5 3 VOLTAGE CHARGE PUMP REGULATOR 115 5 3 1 CPM Charge Pump Mode 115 2 3 2 CP
12. B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC AMENDENT HISTORY Version Date Description VER 0 1 First issue VER 0 2 July 2008 Update pin assignment LQFP package VER 0 3 Sep 2008 Cancel LQFP64 package VER 0 4 Oct 2008 1 Modified VACM driving capacity Spec 2 Modified IHRC frequency Spec 3 Annotation of WTCKS function 4 Error correction of NTO and NTP 5 Cancel EZ writer programming 6 Cancel OTP programming pin to transition board mapping 7 Modified Development tools chapter VER 0 5 Dec 2008 1 Modified AVE ACM AVDDR Spec 2 Modified Marking Identification LQFP 3 Modified LCD Drive Waveform 1 4 duty 1 3 bias and 1 2 bias 4 Modified P41 and P42 description in Low Battery Detect Register 5 Modified Low Battery Detect Register 6 Modified Reset flag NTO NPD 11 when LVD and Power On Reset occurring SONiX TECHNOLOGY LTD Page 2 Preliminary Version 0 1 N SN8P1929 aU N B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Table of Content Ev dicen 2 1 PRODUCT OVERVIEW ey Ne apse UD RR ONE EUR 6 1 1 SF FECTION TABLE 6 1 2 PRAT NSCEEEE 6 1 3 SYSTEM BLOCK DIAGR AM rette reete aa re rs ee S a aa
13. SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 2 POWER ON RESET The power on reset depend on LVD operation for most power up situations The power supplying to system is a rising curve and needs some time to achieve the normal voltage Power on reset sequence is as following X Power up System detects the power voltage up and waits for power stable External reset System checks external reset pin status If external reset is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 3 3 WATCHDOG RESET Watchdog reset is a system protection In normal condition system works well and clears watchdog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following e Watchdog timer status System checks watchdog timer overflow status If watchdog timer overflow occurs the system is reset System initialization All system registers is set as initial conditions an
14. On chip charge pump regulator with 3 8V voltage output driven current On chip regulator with 3 0V 2 4V 1 5V output voltage On chip 1 2V Band gap reference for battery monitor On chip Voltage Comparator Build in ADC reference voltage V R R 0 8V 0 64V or 0 4V Build In Temperature Sensor LCD driver 1 3 or 1 2 bias voltage 4 common 24 segment Dual clock system offers four operating modes Internal high clock RC type up to 16 MHz External high clock Crystal type up to 8 MHz Normal mode Both high and low clock active Slow mode External Low clock and Internal low RC clock Green mode Period wake up by TO and TCO Sleep mode Both high and low clock stop Package LQFP80 Dice Page 6 Preliminary Version 0 1 SN8P1929 SONIX aU D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 3 SYSTEM BLOCK DIAGRAM INTERNAL 4 PC HIGH RC OTP IR EXTERNAL ROM HIGH OSC EXTERNAL LOW OSC v TIMING GENERATOR SYSTEM REGISTERS INTERRUPT CONTROL TIMER amp COUNTER LVD Low Voltage Detector WATCHDOG TIMER m gt Charge Pump gt Regulator o PGIA gt Comparator 16 BIT ADC Internal Reference Internal ADC Channel for Battery Detect 1 2 P4
15. Stop TC1 timer counting disable TC1 interrupt function and clear TC1 interrupt request flag BOBCLR FTC1ENB TC1 timer TCTOUT and PWM stop BOBCLR FTC1IEN TC 1 interrupt function is disabled BOBCLR TC1 interrupt request flag is cleared Set TC1 timer rate Besides event counter mode MOV A 0xxx0000b TC1 rate control bits exist in bit4 bit6 of TC1M The value is from x000 oxxb x1 11xxxxb BOMOV TC1M A TC 1 interrupt function is disabled Set TC1 timer clock source Select internal external clock source BOBCLR FTC1CKS Select TC1 internal clock source or BOBSET FTC1CKS Select TC1 external clock source Select TC1 Fosc internal clock source BOBCLR FTC1X8 Select 1 internal clock source or BOBSET FTC1X8 Select TC1 Fosc internal clock source Note TC1X8 is useless TC1 external clock source mode Set TC1 timer auto load mode BOBCLR FALOAD1 Enable TC1 auto reload function or BOBSET FALOAD1 Disable 1 auto reload function Set TC1 interrupt interval time TC1OUT Buzzer frequency or PWM duty cycle Set interrupt interval time TC1OUT Buzzer frequency PWM MOV A 7FH TC1C and TC1R value is decided by TC1 mode BOMOV TC1C A Set TC1C value BOMOV TCIR A Set TC1R value under auto reload mode or PWM mode In PWM mode set PWM cycle BOBCLR FALOAD1 ALOAD1 TC1OUT 00 PWM
16. 0 256 255 256 0x00 0xFF 0x00 0xFF 7 8125K Overflow per 256 count The Output duty of PWM is with different TCOR Duty range is from 0 256 255 256 0 1 128 254 255 0 NM 128 254 255 TCO Clock LULU TCOR 00H Low i TCOR 01H i High l i TCOR 80H Low SONiX TECHNOLOGY CO LTD Page 99 Preliminary Version 0 4 Ss SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 5 2 TCOIRQ AND PWM DUTY In PWM mode the frequency of TCOIRQ is depended on PWM duty range From following diagram the TCOIRQ frequency is related with PWM duty TCO Overflow TCOIRQ 1 OxFF TCOC Value 0x00 PWMO Output Duty Range 0 255 8 5 3 PWM PROGRAM EXAMPLE gt Example Setup PWMO output from TCO to PWMOOUT P5 4 The external high speed oscillator clock is 4MHz Fcpu Fosc 4 The duty of PWM is 30 256 PWM frequency is about 1KHz PWM clock source is from external oscillator clock TCO rate is Fcpu 4 The TCORATE2 TCORATE1 110 TCOC TCOR 30 01100000 Set the rate Fcpu 4 MOV 30 Set the PWM duty to 30 256 BOMOV TCOC A BOMOV TCOR A BOBSET FPWMOOUT Enable PWMO output to P5 4 and disable P5 4 I O function BOBSET FTCOENB Enable TCO timer Note The TCOR is write only register Don t process them using INCMS DECMS instructi
17. 00H38 01H 0 miS oa j 9 02HO 02H1 02H2 02H38 03H0 03H2 03H3 4 gt Example Enable LCD function Set the LCD control bit LCDENB and program LCD RAM to display LCD panel BOBSET FLCDENB LCD driver SONiX TECHNOLOGY CO LTD Page 108 Preliminary Version 0 4 NONIN rois tent ADC 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 9 5 LCD Circuit SN8P1929 in the LCD electric circuit builds in selective resistance for Voltage division User can add resistance between VLCD V3 V2 V1 for more driving current Build in register can be selected in four resistor value 400K 200K 100K and 50K controlled by LCDREFO and LCDREF1 of the OPTION register V1 V2 V3 only available for Dice form and LQFP80 package LCD Drive Waveform 1 4 duty 1 3 bias SN8P1929 50K 50K 100K 200K Masala SR 1 0 1 100 200K SR 0 1 LCDBIAS 0 OPEN LCDREF 0 1 50K 50K 100K 200K SR 0 ex LCDREF 0 1 LCDENB VLCD 400KxR 2 Ue Note If used external resister the LCD current consumption from VLCD always existence even under power down mode LCD Currentconsumptim when LCDREF 0 1 2 00 Note V2 1 3 VLCD gt V3 2 3 VLC
18. 10 ms To disable TO interrupt service To clear TO interrupt request To enable TO timer set CPUMx 10 Note During the green mode with TO wake up function the wakeup pins reset pin and 0 wakeup the system back to the last mode TO wake up period is controlled by program and TOENB must be set SONiX TECHNOLOGY CO LTD Page 57 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 3 WAKEUP 5 3 1 OVERVIEW Under power down mode sleep mode or green mode program doesn t execute The wakeup trigger can wake the system up to normal mode or slow mode The wakeup trigger sources are external trigger PO P1 level change and internal trigger TO TCO timer overflow Power down mode is waked up to normal mode The wakeup trigger is only external trigger PO P1 level change Green mode is waked up to last mode normal mode or slow mode The wakeup triggers are external trigger PO P1 level change and internal trigger TO TCO timer overflow 5 3 2 WAKEUP TIME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 2048 external high speed oscillator clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode Note Wakeup from green mode is no wakeup
19. DATA org Oh Bank 0 data section start from RAM address 0x000 WkOOBO DS 1 Temporary buffer for main loop IwkOOBO DS 1 Temporary buffer for ISR AccBuf DS 1 Accumulater buffer PflagBuf DS 1 PFLAG buffer WKkO00BO 0 EQU WKk00BO0 0 Bit 0 of WkOOBO IwkOOBO 1 EQU IwkOOBO 1 Bit 1 of Iwk00 jmp Reset ORG 8 Jmp Isr ORG 10h mov A 07Fh STKP A bOmov PFLAG 00h RBANK 00h CIrRAM call Syslnit Code section start Reset vector Address 4 to 7 are reserved Interrupt vector Initial stack pointer and disable global interrupt pflag 2 Set initial RAM bank in bank 0 Clear RAM System initial SONiX TECHNOLOGY CO LTD Page 145 Preliminary Version 0 4 SO N SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC bObclr FGIE Enable global interrupt Main routine Main bObset FWDRST Clear watchdog timer mov a 04h XBOMOV CPM a sing XBOMOV command for CPM setting mov a 00000110B XBOMOV CPCKS a using XBOMOV command for CPCKS setting XbObset FCPRENB Enable Charge Pump Regulator Call Delay 10ms Delay 10ms for CPR stable jmp Main INCLUDE 1929Ev asm SN8P1929 Ev Kit interface code Please be aware of the position of the listed file names marked in red 14 2 10 OTP WRITE IN STEP Using SN8P 1929 EV board to program is shown in following step 1 Separate EV board and ICE 2 Plug the empty OTP IC board
20. J1 should be in SHORT 3 When connecting to the develop system the JP4 should be OPEN Or else the system will not be able to reset successfully 4 Use the same oscillator for both EV Board and ICE 5 is allowed to connect to AVE gt VDD or AVDDR gt it is suggested to be connect to VDD 6 When simulate both EV Board and developer system gt J2 needed to be in SHORT Digital GND and Analog GND both connected 7 R8 R9 R10 are for LBT function Connect the resistance for this function The connection from SN8P 1929 EV board to SN8ICE 1K is shown in following Los n si SONLX EU Board 8 BITICE 00868 E 5 x gt i 27 RU m N SN8P1929 aU N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 14 2 5 STAND ALONG EV BOARD 1 Separate EV board and ICE 2 Attached the IC board with pre write in program code to Ev Board U1 3 When using the stand along Ev Board JP4 should all be in SHORT order to prevent malfunction for relative IO ports 4 Confirm J2 s connectivity status gt J2 should be in SHORT Digital GND and Analog GND both connected 5 JP3 is used for monitoring LCD voltage gt users are allow to connect to AVE or VDD 14 2 6 SONIX ASSEMBLER SONIX provides SN8ASM Assembler program and all sort developer related SN8P1929 software and as well as complier The combination of the SONIX ICE and SN8P192
21. Sn8fae sonix com tw SONiX TECHNOLOGY CO LTD Page 154 Preliminary Version 0 4
22. s high address BOMOV Y TABLE1 M To set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table s low address BOMOV A BUF Z Z BUF BOADD ZA BOBTS1 FC Check the carry flag JMP GETDATA 0 5 Y FC 1 1 GETDATA Y is not overflow INCMS X Y is overflow X X 1 NOP GETDATA To lookup data If BUF 0 data is 0x0035 If BUF 1 data is 0x5105 If BUF 2 data is 0x2012 TABLE1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H SONiX TECHNOLOGY CO LTD Page 16 Preliminary Version 0 1 SN8P1929 N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 2 3 JUMP TABLE DESCRIPTION The jump table operation is one of multi address jumping function Add low byte program counter PCL and ACC value to get one new PCL The new program counter PC points to a series jump instructions as a listing table It is easy to make a multi jump program depends on the value of the accumulator A When carry flag occurs after executing of ADD PCL it will not affect PCH register Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software If the jump table leaps over the ROM page boundary e g from xxFFH to xx00H move the jump table to the top of next program memory page xx00H Here one page mean 256 words X Note Program counter can
23. 1 STKP 0 SONiX TECHNOLOGY LTD Page 35 Preliminary Version 0 4 SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 3 2 STACK REGISTERS The stack pointer STKP is a 4 bit register to store the address used to access the stack buffer 12 bit data memory STKnH and STKnL set aside for temporary storage of stack addresses The two stack operations are writing to the top of the stack push and reading from the top of stack pop Push operation decrements the STKP and the pop operation increments each time That makes the STKP always point to the top address of stack buffer and write the last program counter value PC into the stack buffer The program counter PC value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 ODFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB3 STKPB2 STKPB1 STKPBO Read Write R W R W R W R W R W After reset 0 1 1 1 1 Bit 3 0 STKPBn Stack pointer n 0 3 Bit 7 GIE Global interrupt control bit 0 Disable 1 Enable Please refer to the interrupt chapter gt Example Stack pointer STKP reset we strongly recommended to clear the stack point
24. 1 N SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 8 1929 USER S MANUAL Preliminary Specification Version 0 5 8 Bit Micro Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part SONiX TECHNOLOGY CO LTD Page 1 Preliminary Version 0 1 N SN8P1929 D
25. 16 bit ADC 2 1 5 3 BIT DEFINITION of SYSTEM REGISTER e aaa z s zzz a _ 2 2 ZEE Address Bit7 Bit5 Bit4 Bit3 Bit2 Bit R W 080H LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBITO R W 081H HBIT7 HBIT6 HBIT5 4 HBIT3 HBIT2 HBIT1 HBITO 082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBITO 083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBITO c J 7 PFLAG 08H RBNkS3 RBNK8 RBNKS1 RBNKSO RBANK 088H RCLK R W OPTION 089H LCDREF1 LCDREFO LCDBNK LCDENB LCDBIAS LCDM1 AMPCHS AMPCKS ADCM ACMENB AVDDRENB AVENB AVESEL1 AVESELO CPAUTO CPON CPRENB CPM CPCKS3 52 CPCKS1 50 5 WRSO DRDY DFM ADCB17 ADCB16 ADCB15 ADCB14 ADCB13 ADCB12 ADCB11 ADCB10 ADCDH 4 P4110 LBTENB LBTM CPSAVE CPMTEST ROMADR6 ROMADRS ROMADR4 ROMADR3 ROMADR2 ROMADR1 ROMADRO ROMADRL ROMDA15 ROMDA14 ROMDA13 ROMDA12 ROMDA11 ROMDA10 ROMDA9 ROMDAB ROMDAH ROMDA7 ROMDA6 ROMDA5 ROMDA4 ROMDA3 ROMDA2 ROMDAO ROMDAL 5 1 POOGO PEDGE P13W P12W 1 P13M P12M 2 42 54 P53M P52M R W P5M TCOIEN TOEN POOIEN WTCKS WDRST WDRATE 1 CLKMD STPHX
26. 16 bit ADC Lo ee ee ee sapei s4Peio 54 9 54 8_ __ 5301 53 10 53 9 53 8 Po o 52 11 52010 52 9 52 8 he ee sopen siPcio 51 9 51 8 Lo 1 7 51 sore SOPCIO SOPC9 SOPC8 Note To avoid system error make sure to put all the 0 and 1 as it indicates in the above table All of register names had been declared in SN8ASM assembler One bit name had been declared in SN8ASM assembler with F prefix code bObset bObcir bset bclr instructions are only available to the R W registers SONiX TECHNOLOGY CO LTD Page 24 Preliminary Version 0 1 N 7 SN8P1929 S H x 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 5 4 ACCUMULATOR The ACC is an 8 bit data register responsible for transferring or manipulating data between ALU and data memory If the result of operating is zero Z or there is carry C or DC occurrence then these flags will be set to PFLAG register ACC is in data memory RAM so ACC can t be access by BOMOV instruction during the instant addressing mode gt Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV 0FH Write data from BUF data memory MOV A BUF The system doesn t store ACC and PFLAG value when interrupt
27. 5 00000100 R2032 2 4 3V R2032 4 4 6V 5 5Oms 50ms 4 4 5 1 5ms 50ms 50 External 5VReg 5ms 50ms 50 1 CR2032 application Please set enough delay time or the VDD will drop when Charge pump enable Note 2 IF VDD always over 4 2V set Charge pump as Auto or Disable mode to disable charge pump Note3 AA AAA dry battery application delay time is shorter than CR2032 application SONiX TECHNOLOGY CO LTD Page 135 Preliminary Version 0 4 SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 2 APPLICATION CIRCUIT 12 1 Scale Load Cell Application Circuit Note Please refer 10 5 7 for capacitor setting VDD AVDDR 1 CO CI como VLCD AVE oL SEG 220 T 1 SEG 230 R AVE too 104 R RST Hr R 10K VDD Hr Pin31 Cow CJ Aar P54 L Al 5 0 4I Avss E dus P4 2 S TL 1 cM 5 P4 1 CAVDDR 5 lt 2 O 5 25 560509 X x 9 0 7 32768 3 58M CAVE X tal X tal VDD Cc 2 7 20pF 20pF 20pF SONiX TECHNOLOGY CO LTD Page 136 Preliminary Version 0 4 SN8P1929 A 8 Bit Micro Contro
28. 7 1 4 PP REDE 8 1 5 PIN sess etes sessi 9 1 6 PIN CIRCUIT 8 2 004040000000000 10 2 CENTRAL PROCESSOR UNIT CPU essoesesssessossoessessossosssessossoossessossoossossosscossossessosssossessssssossesss 11 2 1 IVER MIO RY 11 2 1 1 PROGRAM MEMORY ROM ab 11 2 1 1 1 CHECKSUM _ 19 2 1 2 CODE OPTION TABLE eee iet erbe b ete be EY a 20 2 1 3 IRR d aiu pita RES IUE 21 2 1 4 SYSTEM REGISTER rettet evos eet ett eee ee ea oe se Yee dote ved esos eoe netus n 22 2 1 4 1 SYSTEM REGISTER 2 0 0 000000000000000000 sese nes 22 2 1 4 2 SYSTEM REGISTER 2 2 00500000000 22 2 143 BIT DEFINITION of SYSTEM REGISTER errem 23 3 E OPC eT EE 72 3 1 eausa 72 3 2 VO PULL UPREGISTBB 4t e Cetera cete Eo eco
29. JMP COSTEP Jump to COSTEP if ACC is not zero COSTEP NOP INCMS instruction INCMS BUFO JMP COSTEP Jump to COSTEP if BUFO is not zero COSTEP NOP If the destination decreased by 1 which results underflow of 0x00 to OxFF the PC will add 2 steps to skip next instruction DECS instruction DECS BUFO JMP COSTEP Jump to COSTEP if ACC is not zero COSTEP NOP DECMS instruction DECMS BUFO JMP COSTEP Jump to COSTEP if BUFO is not zero COSTEP NOP SONiX TECHNOLOGY CO LTD Page 28 Preliminary Version 0 4 SONIN 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SN8P1929 A MULTI ADDRESS JUMPING Users can jump around the multi address by either JMP instruction or ADD M A instruction M PCL to activate multi address jumping function Program Counter supports ADD M A ADC M A and BOADD instructions for carry to PCH when PCL overflow automatically For jump table or others applications users can calculate PC value by the three instructions and don t care PCL overflow problem Note PCH only support up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value not change gt Example If PC 0323H PC 0323H PC 0328H MOV BOMOV MOV BOMOV gt Example If PC 0323H PC 0323H BOADD JMP JMP JMP JMP PCH 03H
30. PCL 23H A 28H PCL A Jump to address 0328H A 00H PCL A Jump to address 0300H PCH 03H PCL 23H PCL A PCL PCL ACC the PCH cannot be changed AOPOINT If ACC 0 jump to AOPOINT A1POINT ACC 1 jump to A1POINT A2POINT ACC 2 jump to A2POINT A3POINT ACC 3 jump to 2 1 7 H L REGISTERS The H and L registers are the 8 bit buffers There are two major functions of these registers canbe used as general working registers can be used as RAM data pointers with HL register 081H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBITO Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X 080H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBITO Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X Example If want to read a data from RAM address 20H of bank 0 it can use indirectly addressing mode to SONiX TECHNOLOGY CO LTD Preliminary Version 0 4 Page 29 O N SN8P1929 BW S O 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit access data as following BOMOV 00H To set RAM bank for register BOMOV L 20H To set location 20H for L register BOMOV HL To read a data into ACC Example Clear general purpose data memory area of bank
31. PGIA 16 bit ADC 4 5 2 SYSTEM CLOCK MEASUREMENT Under design period the users can measure system clock speed by software instruction cycle Fcpu This way is useful in RC mode gt Example instruction cycle of external oscillator BOBSET 0 Set PO 0 to be output mode for outputting Fcpu toggle signal BOBSET 0 0 Output toggle signal low speed clock mode BOBCLR 0 0 Measure the frequency by oscilloscope JMP B Note Do not measure the RC frequency directly from XIN the probe impendence will affect the RC frequency SONiX TECHNOLOGY CO LTD Page 54 Preliminary Version 0 4 SONIN SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 9 SYSTEM OPERATION MODE 5 1 OVERVIEW The chip is featured with low power consumption by switching around four different modes as following P1 Wake up Function Active PO P1 Wake up Function Active TO Timer Time Out External Reset Circuit Active Normal mode High speed mode Slow mode Low speed mode Power down mode Sleep mode Green mode Power Down Mode Sleep Mode External Reset Circuit Active CPUM1 CPUMO 01 Normal Mode CLKMD 1 CLKMD 0 CPUM1 10 Slow Mode P1 Wake up Function Active TO Timer Time Out Green Mode External Reset Cir
32. The watchdog timer is a protection to make sure the system executes well Normally the watchdog timer would be clear at one point of program Don t clear the watchdog timer in several addresses The system executes normally and the watchdog won t reset system When the system is under dead band and the execution error the watchdog timer can t be clear by program The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also can improve brown out reset condition and make sure the system to return normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal range Reduce the system executing rate If the system rate is fast and the dead band exists to reduce the system executing rate can improve the dead band The lower system rate is with lower minimum operating voltage Select the power voltage that s no dead band issue and find out the mapping system rate Adjust the system rate to the value and the system exits the dead band issue This way needs to modify whole program timing to fit the application requirement External reset circuit The external reset methods also can improve brown out reset and is the complete solution There are three external reset circuits to imp
33. 0 using HL register CLR H H 0 bank 0 BOMOV L 07FH L 7 the last address of the data memory area CLR_HL_BUF CLR HL Clear HL to be zero DECMS L L 1 if L 0 finish the routine JMP CLR_HL_BUF Not zero CLR HL END_CLR End of clear general purpose data memory area of bank 0 SONiX TECHNOLOGY CO LTD Page 30 Preliminary Version 0 4 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit n SN8P1929 2 1 7 1 X REGISTERS X register is an 8 bit buffer There are two major functions of the register canbe used as general working registers be used as ROM data pointer with the MOVC instruction for look up table 085H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X XBIT7 XBIT6 XBIT5 4 XBIT3 XBIT2 XBIT1 XBITO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Note Please refer to the LOOK UP TABLE DESCRIPTION about X register look up table application 2 1 7 2 Y Z REGISTERS The Y and Z registers are the 8 bit buffers There are three major functions of these registers can be used as general working registers can be used as RAM data pointers with YZ register X can be used as ROM data pointer with the MOVC instruction for look up table 084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Y YBIT7 YBIT6 YBIT5 YBITA YBIT3 Y
34. 5105H DW 2012H Note The X Y registers will not increase automatically when Y Z registers crosses boundary from OxFF to 0x00 Therefore user must take care such situation to avoid loop up table errors If Z register is overflow Y register must be added one If Y register is overflow X register must be added one The following INC_XYZ macro shows a simple method to process X Y and Z registers automatically gt Example INC XYZ macro INC XYZ MACRO INCMS Z 2 1 Not overflow INCMS Y gt Y 1 JMP F Not overflow INCMS X 1 Not overflow ENDM SONiX TECHNOLOGY CO LTD Page 15 Preliminary Version 0 1 N SN8P1929 aU wu D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Modify above example by INC_XYZ macro BOMOV X TABLE1 H set lookup table1 s high address BOMOV Y TABLE1 M _ To set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table1 s low address MOVC To lookup data ACC 35H INC_XYZ Increment the index address for next address MOVC To lookup data 51H ACC 05H TABLE1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H The other example of loop up table is to add X Y or Z index register by accumulator Please be careful if carry happen gt Example Increase Y and Z register by BOADD ADD instruction BOMOV X TABLE1 H _ To set lookup table1
35. AAA If Not jump to checksum calculate JMP CHECKSUM END If Yes checksum calculated is done Y ADD 1 INCMS Y Increase Y NOP JMP B Jump to checksum calculate CHECKSUM_END END USER CODE SONiX TECHNOLOGY CO LTD Label of program end Page 19 Preliminary Version 0 1 N SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 3 CODE OPTION TABLE IHRC High speed internal 16MHz RC XIN XOUT become to P2 0 P2 1 High CIk bi direction pins 4M X tal Standard crystal resonator e g 4M for external high clock oscillator Force Watch Dog Timer clock source come from INT 16K RC Always_ON Also INT 16K RC never stop both in power down and green mode that INT_16K_RC means Watch Dog Timer will always enable both in power down and green mode CPUM G Enable or Disable internal 16K RC clock by CPUM register Tem Note 1 In high noisy environment set Watch Dog as Enable and INT 16K RC as Always ON and Enable Noise Filter is strongly recommended 2 Fcpu code option is only available for High Clock Fcpu of slow mode is Flosc 4 3 In high noisy environment disable Low Power is strongly recommended 4 The side effect is to increase the lowest valid working voltage level if enable Low Power and Noise Filter code option 5 Enable Low Power option will reduce operating current except in slow mode SONi
36. Bit 3 Bit 2 Bit 1 Bit 0 TOM TOENB TOrate2 TOrate1 TOrateO TC1X8 TCOX8 TCOGN TOTB Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 0 TOTB clock source control bit 0 Disable TO clock source from 1 Enable Bit 1 TCOGN Enable TCO Green mode wake up function 0 Disable 1 Enable Bit 2 0 8 TCO internal clock source control bit 0 TCO internal clock source is Fcpu TCORATE is from Fcpu 2 Fcpu 256 1 TCO internal clock source is Fosc TCORATE is from Fosc 1 Fosc 128 Bit 3 1 8 TC1 internal clock source control bit 0 TC1 internal clock source is TC1RATE is from Fcpu 2 Fcpu 256 1 TC1 internal clock source is TC1RATE is from Fosc 1 Fosc 128 Bit 6 4 TORATE 2 0 TO internal clock select bits 000 fcpu 256 001 fcpu 128 110 fcpu 4 111 fcpu 2 Bit 7 TOENB TO counter control bit 0 Disable TO timer 1 Enable TO timer Note Under TCO event counter mode TCOCKS 1 TCOX8 bit and TCORATE are useless SONiX TECHNOLOGY CO LTD Page 83 Preliminary Version 0 4 SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 4 TCOC COUNTING REGISTER TCOC is an 8 bit counter register for TCO interval time control ODBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOC TCOC7 TCOC6 TCOC5 TCOC4 TCOC3 TCOC2 TCOC1 TCOCO Read
37. Charge pump Regulator PGIA 16 bit ADC 096H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPCKS CPCKS3 CPCKS2 CPCKS1 CPCKSO R W After Reset 0 0 0 0 CPCKS 3 0 register sets the Charge Pump working clock the suggestion Charge Pump clock is 13K 15K Hz Normal mode 2K Slow mode Charge Pump Clock Fcpu 4 2 CPCKS 3 0 Refer to the following table for CPCKS 3 0 register value setting in different Fosc frequency Fosc CPCKS3 CPCKS2 CPCKS1 CPCKSO 32768Hz 2M 3 58M AWIHRC 18M 0 0 0 0 2 048K 125 223 75 250 500K 0 0 0 1 NA 62 5K 111 88 125 250K 0 0 1 0 NA 31 25K 55 94K 62 5 125 0 0 1 1 15 625K 27 97 31 25 62 5 0 1 0 0 7 8125 13 985 15 625 31 25 0 1 0 1 3 90625K 6 99K 7 8125K 15 625 0 1 1 0 NA 1 953215K 3 495K 3 90625 7 8125 0 1 1 1 0 976 1 75 1 953215 3 90625 1 0 0 0 0 488 0 875K 0 976K 1 953215 1 0 0 1 0 244 0 438K 0 488K 0 976 1 0 1 0 0 122 0 219K 0 244K 0 488 1 0 1 1 0 61K 0 11K 0 122K 0 244K 1 1 0 0 NA 0 3K 0 055K 0 061K 0 122K 1 1 0 1 NA 0 15K 0 028K 0 03 0 61K 1 1 1 0 NA 0 075K 0 014K 0 015K 0 3K 1 1 1 1 NA 0 037K 0 007K 0 008K 0 15K When enable charge pump Set Charge pump clock as 1011 to avoid VDD dropped Note2 In general applica
38. IHRC 2 2 4 Low Power Disable Analog Parts OFF Vdds 3V4AMHz IHRC 1 2 Low Power Enable Analog Parts OFF Mdd 3V4MHz IHRC 2 Low Power Disable Analog Parts ON 3V 4AMHz IHRC 45 Normal Mode Vdd 5V 4MHz IHRC 25 5 Low Power Enable Analog Parts ON Vdd 3V AMHz IHRC 4 Vdd 5V Slow mode Ext 32768Hz 20 30 Stop High Clock LCD OFF CPR OFF 3V 8 20 Ext 32768Hz Supply Current Vdd 5V 30 50 Slow mode Ext 32768Hz Stop High Clock LCD ON 200K CPR OFF Vdd 3V Ext 32768Hz 15 30 juA Vdd 5V Slow mode Ext 32768Hz 300 600 Stop High Clock LCD ON 200K CPR ON Vdd 3V Ext 32768Hz 250 500 Vdd 5V By _ Ext32768Hz 10 20 wA Vdd 3V _ 4 4 lua Stop High Clock Ext 32768Hz LCD OFF Vdd 5V 15 30 uA CPR OFF Internal RC Ext 32768Hz always on Vdd 3V Ext 32768Hz 6 12 qus Green mode ie ae 21 40 Stop High Clock By CPUM ds 3V LCD ON 200K Ext 32768Hz 10 20 uA SONiX TECHNOLOGY CO LTD Page 148 Preliminary Version 0 4 SN8P1929 N 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit Vdd 5V Internal 32768 2 25 90 Idd11 CPR OFF alwayson Vdd 3V _ 12 25 32768 2 Vdd 5V 8 Ext 32768Hz 300 390 y CPUM Green mode Vdd 3V i 250 500 LCD ON 200K Vdd 5V 300 300 CPR ON Internal RC Ext
39. INTTOCHK Jump check to next interrupt BOBTSO FPO1IRQ Check PO1IRQ JMP INTPO1 INTTOCHK Check TO interrupt request BOBTS1 FTOIEN Check TOIEN JMP INTTCOCHK Jump check to next interrupt BOBTSO FTOIRQ Check TOIRQ JMP INTTO Jump to TO interrupt service routine INTTCOCHK Check TCO interrupt request BOBTS1 FTCOIEN Check TCOIEN JMP INTTC1CHK Jump check to next interrupt BOBTSO FTCOIRQ Check TCOIRQ JMP INTTCO Jump to TCO interrupt service routine INTTC1CHK Check T1 interrupt request BOBTS1 FTC1IEN Check TC1IEN JMP INT EXIT Jump check to next interrupt BOBTSO FTC1IRQ Check TC1IRQ JMP INTTC1 Jump to TC1 interrupt service routine INT EXIT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 71 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 7 I O PORT 7 1 l O PORT MODE The port direction is programmed by PnM register All I O ports can select input or output direction expects input mode only of portO 0C1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1M P13M P12M P11M P10M Read Write R W R W R W R W After reset 0 0 0 0 0 0 0C2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2M P21M P20M Read Write R W R W After res
40. If M 0 then skip next instruction H BTSO M b If M b 0 then skip next instruction BTS1 M b If M b 7 1 then skip next instruction 50 If M bank 0 b 0 then skip next instruction BOBTS1 M b If M bank 0 b 1 then skip next instruction JMP d 15 14 lt RomPages1 0 13 lt d CALL d Stack lt 15 0 PC15 14 lt RomPages1 0 13 lt d M PC lt Stack Stack and to enable global interrupt S To push working registers 080H 087H into buffers To working registers 080H 087H from buffers NOP No operation Note 1 Processing OSCM register needs to add extra one cycle 2 If branch condition is true then 5 1 otherwise S 0 SONiX TECHNOLOGY CO LTD Page 138 Preliminary Version 0 4 SN8P1929 D N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 4 Development Tools 14 1 Development Tool Version 14 1 1 ICE In circuit emulation e SNS8ICE 1K S8KD 2 Full function emulates SN8P1929 series SN8ICE1K ICE emulation notice Operation voltage of ICE 3 0V 5 0V Recommend maximum emulation speed at 5V 4 MIPS e g 16MHZ crystal and Fcpu Fhosc 4 Use SN8P1929 EV KIT to emulation Analog Function Note S8ICE2K doesn t support SN8P1929 serial emulation 14 1 2 OTP Writer MPIII Writer ON OFF line operation to support SN8P1929 mass production Note Writer 3 0 doesn t support
41. R W OSCM TCOR7 TCOR6 TCORS TCOR4 TCOR3 TCOR2 TCOR1 TCORO W TCOR 084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBITO 085H XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBITO CHPENB BGRENB FDS1 FDSO GS2 GS1 GSO AMPENB AMPM CHS3 CHS2 CHS1 50 5 z E AMPCKS2 AMPCKS1 AMPCKSO E 5 RVS1 RVSO ADCENB ADCKS7 ADCKS6 ADCKS5 ADCKS4 ADCKS3 52 ADCKS1 ADCKSO ADCKS ADCB9 ADCB8 ADCB7 ADCB6 ADCB5 ADCB4 ADCB3 ADCB2 ADCDL ROMADR11 ROMADR10 ROMADR9 ROMADR8 ROMADRH ROMCNT5 ROMCNT4 ROMCNT3 ROMCNT2 1 ROMCNTO ROMCNT ocsH TCilRQ TCOIRQ TORO POOIRQ R W INTRQ Pc 10 R TOC7 TCOENB TCORATEO TCOCKS ALOADO TCOOUT TCOC7 0 5 TCOC4 TCOC3 TCOC2 TCOC1 TC1ENB TCtrate2 TCtrate1 TCtrateO TC1CKS ALOAD1 TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 1 2 1 1 1 0 1 7 1 6 1 5 TC1R4 TC1R3 TC1R2 TC1R1 TC1RO ODEH ODFH oH m pos e p _ oom ee eee POR POOR POUR 1 P13R P12R P10R W P1UR 2 P21R P20R W P2UR OE4H z P42R P4iR P40R W P4UR 0 5 5 P54R P53R P52R P51R P50R W P5UR _ f srpen 57 szPc9 s7Pce S6PC3 se n 5 seon OF4H S5PC7 S5PC6 S5PC5 S5PC4 S5PC3 S5PC2 S5PC1 S5PCO STK5L OF5H SPC 55 10 S5PC9 S5PC8 STK5H SONiX TECHNOLOGY CO LTD Page 23 Preliminary Version 0 1 N SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA
42. SN8P1929 OTP programming 14 1 3 IDE Integrated Development Environment 5 8 bit MCU integrated development environment include Assembler ICE debugger and OTP writer software e For SN8ICE 1K SN8IDE 1 99204 or later e Easy Writer and MP Easy Writer doesn t support SN8P1929 e M2IDE V1 0X doesn t support SN8P1929 SONiX TECHNOLOGY CO LTD Page 139 Preliminary Version 0 4 TEN L V SN8P1929 S Q MS H x 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 14 2 SN8P1929 EV KIT 14 2 1 INTRODUCTION Sonix provides a complete EV KIT for SN8P1929 which includes an ICE with S8KD chip SN8P1929 EV Board Sonix Assembler and Complier Users are able to do the programming on the computer and to simulate the program code using the software or the ICE itself On the other hand when executing the program and monitoring the RAM status users can user various functions such as Breakpoint Single step etc This makes debug much easier for most programmers Also the system has build in 5 0V power supply 14 2 2 DESCRIPTION Sonix provides SN8P1929 EV board for all functions emulation shown in FIG 1 o0000000000000 1 E 5 20 2 e 0000000 0000000 ooooooooooooo 0000000 N8P1929 EU Kit V1 0 t 248074 S8888R
43. TCOR initial value is as following TCOR initial value N TCO interrupt interval time input clock N is TCO overflow boundary number TCO timer overflow time has six types TCO timer TCO event counter TCO Fcpu clock source TCO Fosc clock source PWM mode and no PWM mode These parameters decide TCO overflow time and valid value as follow table TCOCKS TCOX8 PWMO ALOADO TCOOUT ban Gee 0 Ox00 OxFF 00000000b 11111111b o 0 256 0 00 00000000b 11111111b 2 o 1 64 0x00 0x3F xx000000b xx111111b 256 1 o 32 0 00 0 1 000006 111116 0x00 0xOF _xxxx0000b xxxx1111b 1 0 0 256 0 00 0 00000000b 11111111b Fosc 1 o 1 64 0 00 0 3 xx000000b x111111b Fosc 128 1 0 32 10 00 0 1 xxx00000b xxx1111 1b 7 256 0 00 0 00000000b 11111111b gt Example To set 10ms interval time for TCO interrupt TCO clock source is Fcpu TCOKS 0 0 8 0 no PWM output PWMOzO High clock is external 4MHz FcpuzFosc 4 Select TCORATE 010 Fcpu 64 TCOR initial value N TCO interrupt interval time input clock 256 10ms AMHz 4 64 256 102 4 106 4 64 100 64H SONiX TECHNOLOGY CO LTD Page 86 Preliminary Version 0 4 SN8P1929 N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 6 TCO CLOCK FREQUENCY OUTPUT BUZZER B
44. W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 0 TOTB clock source control bit 0 Disable TO clock source from 1 Enable Bit 1 TCOGN Enable TCO Green mode wake up function 0 Disable 1 Enable Bit 2 0 8 TCO internal clock source control bit 0 TCO internal clock source is Fcpu TCORATE is from Fcpu 2 Fcpu 256 1 TCO internal clock source is Fosc TCORATE is from Fosc 1 Fosc 128 Bit 3 1 8 TC1 internal clock source control bit 0 TC1 internal clock source is TC1RATE is from Fcpu 2 Fcpu 256 1 TC1 internal clock source is TC1RATE is from Fosc 1 Fosc 128 Bit 6 4 TORATE 2 0 TO internal clock select bits 000 fcpu 256 001 fcpu 128 110 fcpu 4 111 fcpu 2 Bit 7 TOENB TO counter control bit 0 Disable TO timer 1 Enable TO timer Note Under TC1 event counter mode TC1CKSz1 TC1X8 bit and TC1RATE are useless SONiX TECHNOLOGY CO LTD Page 92 Preliminary Version 0 4 SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 4 TC1C COUNTING REGISTER TC1C is an 8 bit counter register for TC1 interval time control ODDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1C TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1CO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equat
45. Wait 10ms A 11110110B AMPM A A 00000100B AMPCKS A A 00h AMPCHS A FAMPENB A 00000000B ADCM A A 0236 ADCKS A A 00h DFM A FADCENB FDRDY ADC_Wait FDRDY A ADCDH Data_H_Buf A A ADCDL Data L Buf A SONiX TECHNOLOGY CO LTD SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable Band Gap Reference voltage Set CPCKS as slowest clock to void VDD dropping Set AVE 3 0V CP as Auto mode and Disable AVDDR AVE ACM voltage before enable Charge pump Enable Charge Pump Delay 200ms for Charge Pump Stabilize Set CPCKS as 15 6K for 10 current loading Delay 100ms for Voltage Stabilize Enable AVDDR Voltage 3 8V Delay 10ms for AVDDR Voltage Stabilize Enable ACM Voltage 1 2v Delay 5ms for ACM Voltage Stabilize Enable AVE Voltage 3 0V 1 5V Delay 10ms for AVE Voltage Stabilize Enable Band Gap Set FDS 11 1 PGIA Gain 200 Set AMPCKS 100 for PGIA working clock 1 9K 4M X tal Selected PGIA differential input channel Al1 Al1 Enable PGIA function V X X Output V Al1 AI1 x 200 Selection ADC Reference voltage V R R Set ADCKS 236 for ADC working clock 100K 4M X tal Set ADC as continuous mode and WRSO 0 ADC conversion rate 25 Hz Enable ADC function Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word M
46. event TC1IRQ is set to be 1 As the result the system will execute the interrupt vector If the 0 the trigger event TC1IRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the TC1IEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation Example TC1 interrupt request setup BOBCLR Disable 1 interrupt service BOBCLR Disable TC1 timer MOV A 20H BOMOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H BOMOV TC1C A Set TC1 interval 10 ms BOBSET FTC1IEN Enable TC1 interrupt service BOBCLR FTC1IRQ Clear TC1 interrupt request flag BOBSET FTC1ENB Enable TC1 timer BOBSET FGIE Enable GIE Example TC1 interrupt service routine ORG 8 Interrupt vector JMP INT SERVICE INT SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTC1IRQ Check TC1IRQ JMP EXIT_INT TC1IRQ 0 exit interrupt vector BOBCLR FTC1IRQ Reset TC1IRQ MOV A 74H BOMOV TCIC A Reset TC1C A TC1 interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 69 Preliminary Version 0 4 SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 11 MULTI INTERRUPT OPERATION Under certain condition the software designer uses more than o
47. executed ACC and PFLAG data must be saved to other data memories PUSH POP save and load 0x80 0x87 system registers data into buffers Users have to save ACC data by program Example Protect ACC and working registers DATA ACCBUF DS 1 Define ACCBUF for store ACC data CODE INT SERVICE BOXCH A ACCBUF Save ACC to buffer PUSH Save PFLAG and working registers to buffer POP Load PFLAG and working registers form buffers BOXCH A ACCBUF Load ACC form buffer RETI Exit interrupt service vector Note To save and re load ACC data users must use BOXCH instruction or else the PFLAG Register might be modified by ACC operation SONiX TECHNOLOGY CO LTD Page 25 Preliminary Version 0 1 SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 6 PROGRAM FLAG The PFLAG register contains the arithmetic status of ALU operation system reset status and LVD detecting status NTO NPD bits indicate system reset status including power on reset LVD reset reset by external pin active and watchdog reset C DC Z bits indicate the result status of ALU operation 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG NTO NPD C DC Z Read Write R W R W R W R W R W After reset 0 0 0 Bit 7 6 NPD Reset status flag NTO NPD Reset Status 0 0 Reserved 0 1 1 1 1 1 Watch d
48. internal reference voltage are generated from AVE voltage X 31250 ADCIN gt ADCIN gt ADCConversionData ADCIN 4 ADCIN ADCConversionData X31250 External and Internal Reference Circuit Table External Ref Circuit RVS1 0 AVE Ref R Ref R AVSS Internal Reference Circuit IRVSz1 AVE 3 0V IRVSz1 AVE 2 4V IRVS 1 AVE 1 5V IRVS 0 AVE 3 0V IRVS 0 AVE 2 4V AVE 3 0V AVE 2 4V AVE 1 5V AVE 3 0V AVE 2 4V REF REF 0 90V REF 0 6V REF 0 8V 0 2V 0 4V 1 2V 0 4V REF REF 0 32V REF REF SONiX TECHNOLOGY CO LTD Page 126 Preliminary Version 0 4 Ss SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ADCM xxx0x00xB V REF REF V R R ADC Reference Voltage from External R R ADCM xxx0110xB V REF REF V 1 2V 0 4V 0 8V AVE 3 0V ADC Reference Voltage from Internal 1 2V and 0 4V ADCM xxx0010xB V REF REF V 0 8V 0 4V 0 4V AVE 3 0V ADC Reference Voltage from Internal 0 8V and 0 4 ADCM xxx0111xB V REF REF V 1 2V 0 4V 0 8V AVE 3 0V ADC Reference Voltage from Internal 1 2V and 0 4V and ADC output is Voltage measurement result SONiX TECHNOLOGY CO LTD Page 127 Preliminary Version 0 4 SONIN 11 5 2 ADCKS ADC Clock Register SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 094H Bit 7 Bi
49. power down mode sleep mode both high speed oscillator and internal low speed oscillator will be stopped BOBSET FCPUMO To stop external high speed oscillator and internal low speed oscillator called power down mode sleep mode SONiX TECHNOLOGY CO LTD Page 48 Preliminary Version 0 4 C N 9 xX SN8P1929 N D H PN 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONiX TECHNOLOGY CO LTD Page 49 Preliminary Version 0 4 SO N SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 4 SYSTEM HIGH CLOCK The system high clock is from internal 16MHz oscillator RC type or external oscillator The high clock type is controlled by High_Clk code option High CIk Code Option Description IHRC 16M The high clock is internal 16MHz oscillator RC type XIN and XOUT pins are general purpose pins 4M The high clock is external oscillator The typical frequency is 4MHz 4 4 1 INTERNAL HIGH RC The chip is built in RC type internal high clock 16MHz controlled by IHRC 16M code options In IHRC 16M mode the system clock is from internal 16 2 RC type oscillator and XIN XOUT pins are general purpose pins IHRC High clock is internal 16MHz oscillator RC type XIN XOUT pins are general purpose pins 4 4 2 EXTERNAL HIGH CLOCK External high clock includes three modules Crystal Ceramic RC and external clock signal The high clock osc
50. six types TC1 timer TC1 event counter TC1 Fcpu clock source TC1 Fosc clock source PWM mode and no PWM mode These parameters decide TC1 overflow time and valid value as follow table TC1R valid TC1 R value Fee ema Doce ee T x x 256 0 00 0 00000000b 11111111b 0 E Fepu2 1 0 1 64 0 00 03 0000006 1111116 Fcpu 256 31 32 0x00 0xtF 3xx00000b xx11111b Pot 1 1 16 O0x00 0x0F xxxx0000b xxxx1111b o x x 256 O0x00 OxFF 00000000b 11111111b 1 1 0 0 256 0 00 0 00000000b 11111111b Fosci 1 0 1 64 0 00 0 3 xx000000b xx111111b 128 1 1 0 32 f O0x00 OxftF 000005 11111 Pot 256 Ox00 OxFF 00000000b 11111111b gt Example To set 10ms interval time for TC1 interrupt TC1 clock source is Fcpu TC1KS 0 1 8 0 no PWM output PWM1 0 High clock is external 4MHz FcpuzFosc 4 Select TC1RATE 010 64 initial value N TC1 interrupt interval time input clock 256 10ms 4MHz 4 64 256 102 4 106 4 64 100 64 SONiX TECHNOLOGY CO LTD Page 95 Preliminary Version 0 4 SN8P1929 D N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 6 TC1 CLOCK FREQUENCY OUTPUT BUZZER Buzzer output TC1OUT is from TC1 timer counter frequency output function By setting the 1 clock frequency the cl
51. to avoid working at unusual power condition e g brown out reset in AC power application 3 6 EXTERNAL RESET CIRCUIT 3 6 1 Simply RC Reset Circuit R1 47K ohm 100 ohm This is the basic reset circuit and only includes R1 and C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a power on signal from the timing difference Note The reset circuit is no any protection against unusual power or brown out reset SONiX TECHNOLOGY CO LTD Page 43 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 6 2 Diode amp RC Reset Circuit R1 47K ohm 100 ohm This is the better reset circuit The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal The reset circuit has a simply protection against unusual power The diode offers a power positive path to conduct higher power to VDD It is can make reset pin voltage level to synchronize with VDD voltage The structure can improve slight brown out reset condition Note The R2 100 ohm resistor of Simply reset circuit and Diode amp RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over stress EOS
52. 1 ROMADR10 ROMADR9 ROMADR8 Read Write R R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 OA1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMADRL ROMADR7 ROMADR6 ROMADRS5 ROMADR4 ROMADR3 ROMADR2 ROMADR1 ROMADRO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 VPPCHK VPP pin Programming Voltage Check 0 VPP s Voltage NOT reached 12 5V Can t program ISP ROM 1 VPP s Voltage reached 12 5V Can program ISP ROM Note 2 Using Marco BOBTS1_FVPPCHK and 2 0 50 FVPPCHK for checking VPP voltage status ROMADR 14 0 ISP ROM Programming Address ROM Address which will be Programmed 10 3 ROMDAH ROMADL REGISTERS 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMDAH ROMDA15 ROMDA14 ROMDA13 ROMDA12 ROMDA11 ROMDA10 ROMDA9 ROMDA8 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMDAL ROMDA7 ROMDA6 ROMDA5 ROMDA4 ROMDA3 ROMDA2 ROMDA1 ROMDAO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 ROMDA 15 0 ISP ROM Programming Data ROM Data which want to Programming into ROM area SONiX TECHNOLOGY CO LTD Page 111 Preliminary Version 0 4 SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10 4 ROMCNT RE
53. 2UR P21R P20R Read Write After reset 0 0 OEAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4UR P42R P41R P40R Read Write After reset 0 0 0 OE5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5UR P54R P53R P52R P51R P50R Read Write After reset 0 0 0 0 0 Note is Write Only Register gt Example I O Pull up Register MOV A Enable Port1 Pull up register BOMOV P1UR A SONiX TECHNOLOGY CO LTD Page 73 Preliminary Version 0 4 SONIN 7 3 VO PORT DATA REGISTER SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PO P01 00 Read Write R W R W After reset 0 0 0D1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1 P13 P12 P11 P10 Read Write R W R W R W R W After reset 0 0 0 0 0D2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2 P21 P20 Read Write R W R W After reset 0 0 0D4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4 P42 P41 P40 Read Write R W R W R W After reset 0 0 0 OD5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
54. 3 1 2 VLCD VSS VLCD SEGO 1010b 1 2 VLCD VSS OFF OFF OFF VLCD SEGO 0101b 1 2 VLCD VSS le ON OFF OFF LCD Drive Waveform 1 4 duty 1 2 bias SONiX TECHNOLOGY CO LTD Page 106 Preliminary Version 0 4 SONIN LCD Clock COMO COM1 COM2 COM3 SEGO 1010b SEGO 0101b SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 Frame 1 Frame OFF ON FF ON OFF ON lt ON OFF ON OFF ON OFF OFF lt lt gt lt gt lt LCD Drive Waveform 1 4 duty 1 3 bias SONiX TECHNOLOGY CO LTD Page 107 VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS VLCD 2 3 VLCD 1 3 VLCD VSS Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 9 4 LCD RAM LOCATION RAM bank 15 address vs Common Segment pin location i Cf coms 0 0 2
55. 32768Hz always Vdd 3V Ext 32768Hz 250 500 Vdd 5V 1 5 uA 19013 Sleep Mode NEN 07 5 F 25 1 9 2 0 21 V LVD Detect Level V Internal POR detect level vo 40 C 85C 18 20 22 Internal High Clock Freq Internal High RC Oscillator Frequency 14 16 18 MHz These parameters are for design reference not tested gt Note Analog Parts including Charge Pump Regulator CPR PGIA and ADC SONiX TECHNOLOGY CO LTD Page 149 Preliminary Version 0 4 N SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC All of voltages refer to Vdd 3 8V Fosc 4MHz ambient temperature is 25 C unless otherwise note PARAMETER SYM DESCRIPTION MIN TYP MAX UNIT Analog to Digital Converter Operating current Run mode 3 8V 800 1000 uA Power down current IPDN Stop mode 3 8V 0 1 1 uA Conversion rate Fsmp ADCKS 200KHz 25 sps R R Input Range External Ref 0 4 2 0 V Reference Voltage Input Voltage Vref R R Input Range Internal Ref 0 2 2 0 V Differential non linearity DNL ADC range 28125 50 5 0 5 LSB Integral non linearity INL ADC range 28125 1 4 LSB No missing code NMC ADC range 28125 16 bit Noise free code NFC ADC range 28125 14 16 bit Effective number of bits ENOB ADC range 28125 14 16 bit ADC Input
56. 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCM WTCKS WDRST WDRATE CPUM1 CPUMO CLKMD STPHX 0 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 1 STPHX External high speed oscillator control bit 0 External high speed oscillator free run 1 External high speed oscillator free run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is external low clock Bit 4 3 CPUM 1 0 CPU operating mode control bits 00 7 normal 01 sleep power down mode 10 green mode 11 reserved Bit5 WDRATE Walchdog timer rate select bit 0 Fopy 2 1 2 Bit6 WDRST Watchdog timer reset bit 0 Noreset 1 clear the watchdog timer s counter The detail information is in watchdog timer chapter Bit7 WTCKS Watchdog clock source select bit 0 1 internal RC low clock The WTCKS bit will be set as 1 when Int 16k RC Always selected in the code option WTCKS WTRATE CLKMD Timer Overflow Time 1 fcpu 2 293 ms Fosc 3 58MHz po fo o 1 fcpu 27 T 500 ms Fosc 32768Hz 1 fcpu 2 24 16 65 55 Fosc 16KHz 3V 1 fcpu 28 16 15 Fosc 16KHZ 3V 16K 16 0 55 3V gt Stop high speed oscillator BOBSET FSTPHX To stop external high speed oscillator only gt Example When entering the
57. 9 Emulation Board are used for the purpose of actual circuitry verification and testing thus to save the costs and time for development 14 2 7 SYSTEM REQUIREMENT Operationg system SONIX assembler software supports WIN95 win98 WINME WIN200 and WINXP operation system It s necessary to install device driver under WIN2000 WINXP Files Description SN8IDE Assembler software package gt xxx means version SN8ASMxxxx EXE Main execution program xxxx mean version MACRO1 H Reference macro one 2 Reference macro two Reference macro three SN8P1929 INC Define SN8P1929 all function 1929Ev H Constant and Macro definition for SN8P1929 Ev Kit emulation code 1929Ev ASM SN8P1929 EV Kit interface subroutine User must include this file to communication with Ev Kit 1929 EV Demo ASM SN8P1929 Demo code SONiX TECHNOLOGY CO LTD Page 143 Preliminary Version 0 4 N SN8P1929 aU N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 14 2 8 NOTE FOR SOFTWARE INSTALLATION 1 Check if the SN8P1929 INC has been included the designated folder for SONIX Assembler Default directory is C Sonix Sn8IDE_xxxx use_inc2 2 Check if the main program include 1929Ev H and 1929Ev ASM gt please refer to 1929 TEMPLATE ASM for detailed instruction 3 The first line of the main program are listed below ICE Mode EQU 1 CHIP SN8P1929 4 When done with the pr
58. ADC 8 2 4 TO TIMER OPERATION SEQUENCE TO timer operation sequence of setup TO timer is as following Stop TO timer counting disable TO interrupt function and clear TO interrupt request flag BOBCLR FTOENB TO timer BOBCLR FTOIEN TO interrupt function is disabled BOBCLR FTOIRQ TO interrupt request flag is cleared A Set TO timer rate MOV A 0xxx0000b TO rate control bits exist in bit4 bit6 of TOM The value is from x000xxxxb x1 11xxxxb BOMOV TOM A TO timer is disabled Set TO clock source from Fcpu or RTC BOBCLR FTOTB Select TO Fcpu clock source 2 BOBSET FTOTB Select TO RTC clock source Set TO interrupt interval time MOV A 7FH BOMOV Set TOC value Set TO timer function mode BOBSET FTOIEN Enable TO interrupt function Enable TO timer BOBSET FTOENB Enable TO timer SONiX TECHNOLOGY CO LTD Page 80 Preliminary Version 0 4 SONIX 8 3 TIMER COUNTER 0 8 3 1 OVERVIEW SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC The TCO is an 8 bit binary up counting timer TCO has two clock sources including internal clock and external clock for counting a precision time The internal clock source is from or Fosc controlled by TCOX8 flag to get faster clock source Fosc The external clock is INTO from P0 0 pin Falling edge trigger Using TCOM register selects TCOC s clock source from internal or external If TCO timer occu
59. AXIMUM RATING Supply eO CURIE 0 3V 6 0 Input in voltage Vss 0 2V 0 2V Operating ambient temperature 0 C 70 C Storage ambient temperature 40 C 125 C 15 2 ELECTRICAL CHARACTERISTIC All of voltages refer to Vss VDD 5 0V Fosc 4MHz Fcpu 1MHZ ambient temperature is 25 C unless otherwise note PARAMETER 5 DESCRIPTION UNIT Operating voltage Vdd Normal mode Vpp Vdd 50 55 V RAM Data Retention Md AS dV rise rate VDD rise rate to ensure power on reset V ms IViL1 All input pins 0 3Vdd V le 02 IViH1 All input pins 0 7Vdd Vdd V dinis 0 9vdd Vdd Reset leakage current llekg Vin Vdd 5 port pull up resistor Ru Vin Vss Vdd 3V 190 300 Ko pu Vss Vdd 5V o pm 180 I O port input leakage current Pull up resistor disable Vin Vdd 2 uA Port source current DERE Vdd 0 5V 12 mA sink current loL Vop Vss 0 5V 8 15 INTn trigger pulse width Ts INTO INT1 interrupt request pulse width 2 fcpu 1991 Normal Mode Vdd 5V 4MHz
60. BIT2 YBIT1 YBITO Read Write R W R W R W R W R W R W R W R W After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBITO Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z register as the data pointer to access data in the RAM address 025H of banko BOMOV Y 00H To set RAM bank 0 for Y register BOMOV Z 25H To set location 25H for Z register BOMOV A YZ To read a data into ACC Example Uses the Y Z register as data pointer to clear the RAM data BOMOV Y 0 Y 0 bank 0 BOMOV Z 07FH Z the last address of the data memory area CLR_YZ_BUF CLR YZ Clear YZ to be zero DECMS Z Z 1 if Z 0 finish the routine JMP CLR_YZ_BUF Not zero CLR YZ END_CLR End of clear general purpose data memory area of bank 0 SONiX TECHNOLOGY CO LTD Page 31 Preliminary Version 0 4 C N 9 xX SN8P1929 N D H PN 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONiX TECHNOLOGY CO LTD Page 32 Preliminary Version 0 4 SONIN 2 1 7 3 R REGISTERS SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC R register is an 8 bit buffer There are two major functions of the register Can be used as working register For store high byte data of look up table MOVC instruction executed the high byte data of specified ROM ad
61. Bit 2 Bit 1 Bit 0 P5 P54 P53 P52 P51 P50 Read Write R W R W R W R W R W After reset 0 0 0 0 0 gt Example Read data from input port BOMOV A PO Read data from Port 0 BOMOV A P1 Read data from Port 1 BOMOV A P4 Read data from Port 4 Example Write data to output port MOV A Write data FFH to all Port BOMOV P1 A BOMOV P2 A BOMOV P4 A BOMOV P5 A gt Example Write one bit data to output port BOBSET P1 0 Set P1 0 to be 1 BOBCLR P1 0 Set P1 0 to be 0 SONiX TECHNOLOGY CO LTD Page 74 Preliminary Version 0 4 SONIN 8 TIMERS SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 1 WATCHDOG TIMER WDT The watchdog timer WDT is a binary up counter designed for monitoring program execution If the program goes into the unknown status by noise interference WDT overflow signal raises and resets MCU The instruction that clears the watchdog timer BOBSET FWDRST should be executed within a certain period If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows reset signal is generated and system is restarted OCAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCM WTCKS WDRST WDRATE CPUM1 CPUMO CLKMD STPHX 0 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit5 WDRATE Watchdog timer rate select bit 0
62. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1M TC1ENB TCtrate2 1 1 TC1rateO TC1CKS ALOAD1 TC1OUT PWM1OUT Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 0 PWM1OUT PWM output control bit 0 Disable PWM output 1 Enable PWM output PWM duty controlled by TC1OUT ALOAD1 bits Bit 1 TC1OUT TC1 time out toggle signal output control bit Only valid when PWM10OUT 0 0 Disable P5 3 is function 1 Enable P5 3 is output TC1OUT signal Bit 2 ALOAD1 Auto reload control bit Only valid when PWM10OUT 0 0 Disable TC1 auto reload function 1 Enable TC1 auto reload function Bit 3 TC1CKS TC1 clock source select bit 0 7 Internal clock Fcpu or Fosc 1 External clock from P0 1 INT1 pin Bit 6 4 TC1RATE 2 0 TC1 internal clock select bits Bit 7 00 1 Fcpu 250 Fosc 128 TC1ENB TC1 counter control bit 0 Disable TC1 timer 1 Enable TC1 timer Note When TC1CKS 1 TC1 became external event counter and TC1RATE is useless No more 0 1 interrupt request will be raised P0 1IRQ will be always 0 SONiX TECHNOLOGY CO LTD Page 91 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 3 TC1X8 TCOX8 TCOGN FLAGS OD8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOM TOENB TOrate2 TOrate1 TOrateO TC1X8 TCOX8 TCOGN TOTB Read Write R W R W R W R W R
63. CKS Charge Pump Clock Register 117 5 4 PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER cessere enne enne enne 119 5 4 1 AMPM NI QN REUS QU E a E 119 5 4 2 AMPCKA PGIA CLOCK SELECTION xd exuta ren YA OH NO UR XS QUE PATI IA UR 120 5 4 3 AMPCHS PGIA CHANNEL SELECTION esit etant kt AM RIEN ra Pet cbe VENOUS 121 5 4 4 Temperature Sensor CES ime e Fd du aV NE 122 5 5 I6 BIT ADU 125 5 5 1 PPCM AIG Mode Register 125 222 2 ADCGKS ADC Clock Register 128 5 5 3 ADCDL ADC Low Byte Data Keglster 129 JIA ADCDH ADC High Byte Data a sedeat deeds 129 2 2 2 DFM ADC Digital Filter Mode Register 130 5 5 6 LBTM Low Battery DOCU 133 252 Analog Setting and 134 6 2554 UDR SR HIN UN REGN ISIEKR UNE OQ UE X PC INN CR NAE 136 6 1 SCALE LOAD CELL APPLICATION CIRCUIT iiis leui bras ee eet D
64. D SONiX TECHNOLOGY CO LTD Page 109 Preliminary Version 0 4 N SN8P1929 aU wu B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC LCD Drive Waveform 1 4 duty 1 2 bias 5 8 1929 VLCD 50K 50K 100K 200K R LCDREF 0 1 e V3 LCDREF1 e V2 e 50K 50K 100K 200K R yo lu 1 0 1 e VI PX VLCD 400Kx R IX2 E z when LCDREF Q 1 00 LCD Currentconsumptin Note If used external resister the LCD current consumption from VLCD always existence even under power down mode Note V2 V3 2 3 VLCD SONiX TECHNOLOGY CO LTD Page 110 Preliminary Version 0 4 SONIN 1 On SYSTEM PROGRAM ROM 10 1 OVERVIEW In System Program ROM ISP provided user an easy way to storage data into Read Only Memory Choice any ROM address and executing ROM programming instruction ROMWRT and supply 12 5V voltage on VPP RST pin after programming time which controlled by ROMCNT ROMDAH ROMDAL data will be programmed into address ROMADRH ROMADRL 10 2 ROMADRH ROMADRL REGISTER SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMADRH VPPCHK ROMADR14 ROMADR13 ROMADR12 ROMADR 1
65. ERVIEW PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin P5 3 The 8 bit counter counts modulus 256 bits The value of the 8 bit counter TC1C is compared to the contents of the reference register TC1R When the reference register value TC1R is equal to the counter value TC1C the PWM output goes low When the counter reaches zero the PWM output is forced high The ratio duty of the PWM1 output is TC1R 256 MAX PWM PWM duty range TC1C valid value TC1R valid bits value Frequency Remark Fcpu 2 0 256 255 256 0x00 0xFF 0x00 0xFF 7 8125K Overflow per 256 count The Output duty of PWM is with different TC1R Duty range is from 0 256 255 256 0 1 12800 254 255 0 1 12800 254 255 TC1 Clock TC1R 00H Low i High T i High l 80 Low i High l i Low i SONiX TECHNOLOGY CO LTD Page 102 Preliminary Version 0 4 SN8P1929 N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 6 2 TC1IRQ AND PWM DUTY In PWM mode the frequency of TC1IRQ is depended on PWM duty range From following diagram the TC1IRQ frequency is related with PWM duty TC1 Overflow TC1IRQ 1 OxFF TC1C Value 0x00 PWM1 Output Duty Range 0 255 8 6 3 PWM PROGRAM EXAMPLE gt Example Setup PWM1
66. GISTERS and ROMWRT INSTRUCTION Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 ROMCNT ROMCNT7 6 5 ROMCNT4 ROMCNT3 ROMCNT2 ROMCNT1 ROMCNTO Read Write W W W W W W W W After reset Bit 7 0 ROMCNT 7 0 ISP ROM Programming Time Counter The ISP ROM Programming Time was controlled by ROMCNT 7 0 Programming will be 256 ROMCNT 4 Fcpu The Suggestion Programming is 1ms Fcpu ROMCNT Programming Time 1MIPs 6 1ms When all setting was done execute ROMWRT instruction to program data ROMDA 15 0 into address ROMADR 14 0 Note1 Please Keep VDD 5V when accessing ISP ROM Note2 After access ROMWHT at least 3 NOP instruction delay is necessary Note3 Please executing ISP function in room temperature 25 C SONiX TECHNOLOGY CO LTD Page 112 Preliminary Version 0 4 SN8P1929 SONIX aU A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 10 5 ISP ROM ROUTINE EXAMPLE gt Example Reserved ISP ROM Area as OxFFFF ORG 0100H QCALDATA DW OxFFFF Program Data 55 into address CALDATA MOV A CALDATA L BOMOV ROMADRL A MOV A CALDATA H BOMOV ROMADRH A MOV A 0 55 BOMOV ROMDAL A MOV A BOMOV ROMDAH A VPP Voltage Check BOBTS1_ FVPPCHK JMP 1 Set programming counter and Accessing ISP ROM WRT MOV A 6 BOMOV ROMCNT A R
67. H POP instructions when interrupt service routine executed DATA ACCBUF DS 1 ACCBUF is ACC data buffer CODE ORG 0 JMP START ORG 8 JMP INT SERVICE ORG 10H START INT SERVICE BOXCH A ACCBUF Save ACC in a buffer PUSH Save 0x80 0x87 working registers and PFLAG register to buffers POP Load 0x80 0x87 working registers and PFLAG register from buffers BOXCH A ACCBUF Restore ACC from buffer RETI Exit interrupt service vector ENDP SONiX TECHNOLOGY CO LTD Page 64 Preliminary Version 0 4 5 7 SN8P1929 S S H 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 6 INTO PO 0 INTERRUPT OPERATION When the INTO trigger occurs the POOIRQ will be set to 1 no matter the POOIEN is enable or disable If the POOIEN 1 and the trigger event POOIRQ is also set to be 1 As the result the system will execute the interrupt vector ORG 8 If the POOIEN 0 and the trigger event POOIRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the POOIRQ is set to be 1 Users need to be cautious with the operation under multi interrupt situation Nolte The interrupt trigger direction of 0 0 is control by PEDGE register OBFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE PEDGEN P0061 P00GO R W R W R W Bit7 PEDGEN Interrupt and wakeup trigger edge control bit 0 Disable edge trigger f
68. If the TCOIEN 0 the trigger event is still set to be 1 Moreover the system won t execute interrupt vector even when the TCOIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation gt Example TCO interrupt request setup BOBCLR FTCOIEN Disable TCO interrupt service BOBCLR FTCOENB Disable TCO timer MOV A 20H BOMOV TCOM A Set TCO clock Fcpu 64 MOV A 74H Set TCOC initial value 74H BOMOV TCOC A Set interval 10 ms BOBSET FTCOIEN Enable TCO interrupt service BOBCLR FTCOIRQ Clear TCO interrupt request flag BOBSET FTCOENB Enable TCO timer BOBSET FGIE Enable GIE gt Example TCO interrupt service routine ORG 8 Interrupt vector JMP INT SERVICE INT SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTCOIRQ Check TCOIRQ JMP EXIT INT TCOIRQ 0 exit interrupt vector BOBCLR FTCOIRQ Reset TCOIRQ MOV A 74H BOMOV TCOC TCO interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 68 Preliminary Version 0 4 N SN8P1929 S nt S B 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit 6 10 TC1 INTERRUPT OPERATION When the TC1C counter overflows the TC1IRQ will be set to 1 no matter the TC1IEN is enable or disable If the TC1IEN and the trigger
69. It is easy to understand the rules of SONIX program from demo programs given above These points are as following 1 The address 0000H is JMP instruction to make the program starts from the beginning 2 The address 0008H is interrupt vector 3 User s program is a loop routine for main purpose application SONiX TECHNOLOGY CO LTD Page 14 Preliminary Version 0 1 N SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 2 2 LOOK UP TABLE DESCRIPTION In the ROM s data lookup function X register is pointed to high byte address bit 16 bit 23 Y register is pointed to middle byte address bit 8 bit 15 and Z register is pointed to low byte address bit O bit 7 of ROM After MOVC instruction executed the low byte data will be stored in ACC and high byte data stored in R register gt Example To look up the ROM data located TABLE1 BOMOV X TABLE1 H set lookup table1 s high address BOMOV Y TABLE1 M _ To set lookup table1 s middle address BOMOV Z TABLE1 L To set lookup table1 s low address MOVC To lookup data R ACC 35H Increment the index address for next address INCMS Z 2 1 JMP Z is not overflow 5 Y 2 15 overflow Y Y 1 JMP Y is not overflow INCMS X Y is overflow X X 1 NOP MOVC To lookup data R 51H ACC 05H TABLE DW 0035H define a word 16 bits data DW
70. O LTD Page 40 Preliminary Version 0 4 SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 4 2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level Different system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship System Mini Operating Voltage Vdd POT Normal Operating Area Dead Band Area System Reset Voltage Reset Area System Rate Fcpu Normally the system operation voltage area is higher than the system reset voltage to VDD and the reset voltage is decided by LVD detect level The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset voltage 3 4 3 BROWN OUT RESET IMPROVEMENT How to improve the brown reset condition There are some methods to improve brown out reset as following LVDreset e Watchdog reset Reduce the system executing rate External reset circuit Zener diode reset circuit Voltage bias reset circuit External reset IC Note 1 The Zener diode reset circuit Voltage bias reset circuit and External reset IC can completely im
71. OMWRT NOP NOP NOP VPP Voltage Check BOBTSO_ FVPPCHK JMP 1 Check Programmed Data BOMOV Z H CALDATA L BOMOV Y CALDATA H MOVC CMPRS A 0x55 JMP WRT_ERR BOMOV A R CMPRS A 0xAA JMP WRT_ERR SONiX TECHNOLOGY CO LTD Move Low Byte Address to ROMADRL Move Low Byte Address to ROMADRH Move Low Byte Data to ROMDAL Move Low Byte Data to ROMADRH Check VPP Voltage is 12 5V or not If VPP not reach 12 5V Keep waiting Set Programming Counter Programming ISP ROM NOP Delay NOP Delay Delay Set VPP as VDD voltage Check VPP Voltage is VDD or not If VPP still reach 12 5V Keep waiting MOVE ISP ROM Data into A and R Check ISP ROM Data Correction Page 113 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 1 Charge Pump PGIA ADC 11 1 OVERVIEW SN8P1929 has built in Voltage Charge Pump Regulator CPR to support a stable voltage 3 8V from AVDDR and 3 0V 2 4v 1 5V from pin AVE with maximum 10mA current driving capacity This CPR provides stable voltage for internal circuits PGIA ADC from AVDDR and external sensor load cell or thermistor from AVE The SN8P1929 series also integrated A gt Analog to Digital Converters ADC to achieve 16 bit performance and up to 62500 step resolution The ADC has THREE different input channel modes 1 Two fully differential inputs 2 One fully differenti
72. PO1IEN is enable or disable If the PO1IEN 1 and the trigger event PO1IRQ is also set to be 1 As the result the system will execute the interrupt vector ORG 8 If the PO1IEN 0 and the trigger event PO1IRQ is still set to be 1 Moreover the system won t execute interrupt vector even when the is set to be 1 Users need to be cautious with the operation under multi interrupt situation Note The interrupt trigger direction of P0 1 is controlled by PEDGEN bit gt Example interrupt request setup BOBSET FPO1IEN Enable INT1 interrupt service BOBCLR FPO1IRQ Clear INT1 interrupt request flag BOBSET FGIE Enable GIE gt Example interrupt service routine ORG 8 Interrupt vector JMP INT SERVICE INT SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FPO1IRQ Check PO1IRQ JMP EXIT INT 0 exit interrupt vector BOBCLR FPO1IRQ Reset PO1IRQ are INT1 interrupt service routine EXIT_INT Pop routine to load ACC and PFLAG from buffers Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 66 Preliminary Version 0 4 N wow SN8P1929 S st MS H 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit 6 8 TO INTERRUPT OPERATION When the TOC counter occurs overflow the TOIRQ will be set to 1 however the TOIEN is enable or disable If the TOIEN 1 the trigger event will make the TOIRQ to be 1 and the system ent
73. R MED eu dau 136 6 2 THERMOMETER APPLICATION CIRCUIT AD AN 137 5 5 139 7 1 DEVELOPMENT TOOL VERSION rx 139 7 1 1 ICE In circuit emulation testet teste she 139 7 1 2 OTP WEE 139 7 1 3 IDE Integrated Development Environment eese eese ee eene enne 139 152 140 7 2 1 INTRODUCTION 140 7 2 2 PCB DESCRIPTION err 140 7 2 3 EV BOARD SETTING 141 7 2 4 SN8P1929 EV BOARD CONNECT WITH ICE esee eene ener nnns 142 STANDALONG EV BOARD 143 7 2 6 eT Ie METIS ELEY RD Ue TRC eo 143 7 2 7 SYSTEM REQUIREMENT at ds am dM P hu tM re 143 7 2 8 NOTE FOR SOFTWARE INSTALLATION esses enne nennen eene nnne 144 7 2 9 EXAMPLE PROGRAM 144 OTP WRITE IN SEEP 146 7 2 11 SN8P1929 PROGRAMMING BOARD CONNECT TO WRITER sse 146 SONiX TECHNOLOGY CO LTD Page 4 Pr
74. S Port 0 structure Pin E Port1 Port4 and Port5 structure Pin Port2 structure Oscillator Code Option Pull Up PnUR Bus Pull Up Pin SONiX TECHNOLOGY CO LTD PnM PnUR NEM EE e gt Input Bus penis Output Bus Pull Up Pa PnUR 27 gt Input Bus Output Output Bus Int Osc Page 10 Preliminary Version 0 1 SONIN SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 CENTRAL PROCESSOR UNIT CPU 2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM words ROM 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000FH 0010H 0011H FFEH FFFH SONiX TECHNOLOGY CO LTD ROM Resetvector General purpose area Reserved Interrupt vector General purpose area CodeOptio Page 11 User reset vector Jump to user start address Jump to user start address Jump to user start address User interrupt vector User program End of user program Code option address Preliminary Version 0 1 N SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 2 RESET VECTOR 0000H A one word vector address area is used to execute system reset Power On Reset 0 1 NPD 1 Wa
75. SET FAVDDRENB Enable AVDDR Voltage 3 8V CALL Wait 10ms Delay 10ms for AVDDR Voltage Stabilize Q ACM Enable XBOBSET FACMENB Enable ACM Voltage 1 2v CALL Wait_5ms Delay 5ms for ACM Voltage Stabilize AVE_Enable XBOBSET FAVENB Enable AVE Voltage 3 0V 2 4V 1 5V CALL Wait_10ms Delay 10ms for AVE Voltage Stabilize PGIA_Init MOV A 11110110B XBOMOV AMPM A Enable Band Gap Set FDS 11 CHPENB 1 PGIA Gain 200 MOV A 00000100B XBOMOV AMPCKS A Set AMPCKS 100 for PGIA working clock 1 9K 4M X tal MOV A 00h XBOMOV AMPCHS A Selected PGIA differential input channel Al1 Al1 PGIA_Enable XBOBSET FAMPENB Enable PGIA function si V X X Output V Al1 AI1 x 200 gt Note 1 Enable Charge Pump Regulator before PGIA working gt Note 2 Please set PGIA relative registers first then enable PGIA function bit SONiX TECHNOLOGY CO LTD Page 123 Preliminary Version 0 4 SONIN Example PGIA channel change PGIA_Init PGIA_Enable PGIA_Sensor PGIA_TS XBOBSET MOV XBOMOV MOV XBOMOV MOV XBOMOV MOV XBOMOV A 11110110B AMPM A A 00000100B AMPCKS A A 00000000B AMPCHS A FAMPENB A 11110111B AMPM A A 00000001B AMPCHS A A 11110001B AMPM A A 00001000B AMPCHS A SONiX TECHNOLOGY CO LTD SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable Band Gap Set 05 11 1 PGIA Gai
76. Status Status AVDDR Function 0 OFF OFF OV Not Available 1 OFF ON See Note1 See Note1 1 Auto Mode ON 3 8V Available 1 Always ON ON 3 8V Available In Auto Mode Charge Pump ON OFF depended on VDD voltage Auto Mode Description Charge Pump Regulator AVDDR PGIA ADC CPRENB CPAUTO AVDDRENB VDD Status Status Output Function 24V OFF ON 3 8V Available 1 0 1 1 lt 4 1V ON ON 3 8V Available Note 1 When Charge Pump is OFF and Regulator is ON VDD voltage must be higher than 4 1V to make sure AVDDR output voltage for PGIA and ADC functions are working well Charge Pump Regulator AVDDR PGIA ADC CPRENB CPAUTO AVDDRENB VDD Status Status Output Function 24 1V OFF ON 3 8V Available 1 0 0 1 lt 4 1V OFF ON VDD Not Available Note 1 For normally application set CP as Auto mode CPAUTO 1 is strongly recommended Note 2 If VDD is higher than 5 0V don t set Charge Pump as Always ON mode Note 3 Band Gap Reference voltage must be enable first FBRGENB before following function accessing Reference AMPM register for detail information 1 Charge pump Regulator 2 PGIA function 3 16 bit ADC function 4 Low Battery Detect function SONiX TECHNOLOGY CO LTD Page 116 Preliminary Version 0 4 SONIN 11 3 2 CPCKS Charge Pump Clock Register SN8P1929 8 Bit Micro Controller with
77. TECHNOLOGY CO LTD Page 77 Preliminary Version 0 4 SN8P1929 JON IX O B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 2 2 TOM MODE REGISTER OD8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOM TOENB TOrate2 TOrate1 TOrateO TC1X8 TCOX8 TCOGN TOTB Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 0 TOTB RTC clock source control bit 0 Disable RTC TO clock source from 1 Enable RTC will be 0 5 sec RTC Low clock must be 32768 cyrstal Bit 1 TCOGN Enable TCO Green mode wake up function 0 Disable 1 Enable Bit 2 TCOX8 TCO internal clock source control bit 0 TCO internal clock source is TCORATE is from Fcpu 2 Fcpu 256 1 TCO internal clock source is Fosc TCORATE is from Fosc 1 Fosc 128 Bit 3 TC1X8 TC1 internal clock source control bit 0 TC1 internal clock source is Fcpu TC1RATE is from Fcpu 2 Fcpu 256 1 TC1 internal clock source is Fosc TC1RATE is from Fosc 1 Fosc 128 Bit 6 4 TORATE 2 0 TO internal clock select bits 000 fcpu 256 001 fcpu 128 110 fcpu 4 111 fcpu 2 Bit 7 TOENB TO counter control bit 0 Disable TO timer 1 Enable TO timer gt Note TORATE is not available RTC mode The TO interval time is fixed at 0 5 sec SONiX TECHNOLOGY CO LTD Page 78 Preliminary Version 0 4 Ss SN8P1929 D N A 8 Bit M
78. U39R8 ER RR ERE 082108 oco o dade 36 20000000 2 z 000000000000000 2 0000000000000 00 0000000000000 00 0000000000000 0 09 oooooooooooo0oooQ0 00000060000000 0000000000000 0 0 900000000000000 o 0000000000000 0000000000000 0000000000000 0000000000000 000000000000 oooooooooooQ 0000000000 0000000000 00000000000 2000000000000 000000000009090 10000000000 t ocooc0600075o5o0o00o00000000 t dua di fo RoR oe of f 9 ri gt 5 Janaka ICIC HSS AUSS DN e l i 962 8555554 P ET TEREFE FIG 1 SN8P1929 EV board SONiX TECHNOLOGY CO LTD Page 140 Preliminary Version 0 4 S 14 2 3 N o 11 12 13 14 15 16 17 NiX EV BOARD SETTING CON1 connecting with the ICE PORT SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC J1 Switch it SHORT position when using the power from ICE and switch it DPEN when using connecting the power from other source D1 Power indicator S1 RESET KEY JP1 OTP write in PORT JP2 LCD PORT JP3 select different voltage setting for VLCD JP4 When separate ICE and Ev board switch JP4 to SHORT or else the relative IO port won t work JP5 Target board connector JP6 JP7 Differential Input Channel 1 2 JP10 Selection of external refere
79. VE 3 0V V REF REF 0 4V 1 Internal Reference Voltage V REF REF is AVE 0 266 When AVE 3 0V V REF REF 0 8V Bit4 Always Set to 0 IRVS RVS1 Rvso AvEsEL 0 22 Peference Voltage Channel Input EXE ADCIN X 0 0 11 10 11 AVE 3 0V 10 Oo om 01 EAE NM External Ref Voltage VOX lt 04V X 0 04 lt 0 4 V X X lt 0 32 0 X 0 0 8V X 0 V X EIE 0 4V EIE Ref Voltage AVE AVES EEMEEE aves 30V 3 16 VDD 2 16 9 1 O64V 032V Te Lg T gr T 4v 0 96V 0 32 1 ADC conversion data is combined with ADCDH and ADCDL register 25 compliment with Note2 The Internal Reference Voltage is divided from AVE so the voltage will follow the changing with sign bit numerical format and Bit ADCB15 is the sign bit of ADC data Refer to following formula to calculate ADC conversion data value AVE 3 0V 2 4V 1 5V which selected by AVESELT 1 0 SONiX TECHNOLOGY CO LTD Page 125 Preliminary Version 0 4 SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ADCIN ADCIN REF REF ADCIN 4 ADCIN REF 4 REF Note The
80. Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TCOC initial value is as following TCOC initial value N TCO interrupt interval time input clock is TCO overflow boundary number TCO timer overflow time has six types TCO timer TCO event counter TCO Fcpu clock source TCO Fosc clock source PWM mode and no PWM mode These parameters decide TCO overflow time and valid value as follow table TCOC valid TCOC value TCOXS EEE TCOOUT x x verflow per count x 256 0 00 00000000b 11111111b Overflow per 256 x x verflow per count 256 0 00 00000000b 11111111b Overflow per 256 2 1 0 1 64 0x00 0x3F xx000000b xx111111b Overflow 64 count Fcpu 256 1 1 o 32 0 00 0 1 xxx00000b xxx11111b Overflow per 32 count 1 1 1 16 0 00 0 0 0000 11115 Overflow per 16 count 0 x x 256 0 00 0 00000000b 11111111b Overflow per 256 count 1 1 0 0 256 0 00 0 00000000b 11111111b Overflow per 256 count Fosci 1 0 1 64 0 00 0 xx000000b xx111111b Overflow per 64 count 128 1 1 0 32 0 00 000005 1111175 Overflow per 32 count LS 256 0 00 0 00000000b 11111111b Overflow per 256 count SONiX TECHNOLOGY CO LTD Page 84 Preliminary Versi
81. X TECHNOLOGY CO LTD Page 20 Preliminary Version 0 1 N 9 SN8P1929 BW D H A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 4 DATA MEMORY RAM 256 X8 bit RAM RAM location 000h General purpose area 000h 07Fh of Bank 0 To store general purpose data 128 bytes BANK 0 AR m 080h System register 080h OFFh of Bank 0 To store system registers 128 bytes OFFh End of bank 0 area 100h General purpose area 100h 17Fh of Bank 1 To store general BANK 1 f purpose data 128 bytes 17Fh FOOh LCD RAM area Bank 15 To store LCD display data BANK 15 24bytes F17h End of LCD RAM SONiX TECHNOLOGY CO LTD Page 21 Preliminary Version 0 1 Ss SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 5 SYSTEM REGISTER 2 1 5 1 SYSTEM REGISTER TABLE L H R Z Y X PFLAG RBANK OPTION LCDM1 g AMPM AMPCHS AMPCKS ADCM ADCKS CPCKS ADCDL ADCDH LBTM ROMADRH ROMADRL ROMDAH ROMDAL ROMCNT ee a ee ee ee ee Pim f Psm JINTRO INTEN OSCM PCL PCH P1 P2 PB pep TCIC TCR STKP P2UR Paur PSUR HL avz j 2 1 5 2 SYSTEM REGISTER DESCRIPTION L H Working amp HL ad
82. ach push operation to restore the program counter PC The RETI instruction uses for interrupt service routine The RET instruction is for CALL instruction When a pop operation occurs the STKP is incremented and points to the next free stack location The stack buffer restores the last program counter PC to the program counter registers The Stack Restore operation is as the following table STKP Register Stack Buffer 1 1 1 sm e 0 4 1 1 sra 0 STK4H O smt ski 4 sm Fe o 7 Low d o1 0 0 E ee NATI LIS ee o1 0 1 STGL LO o1 1 0 Ek o1 qp 1 1 EE un wx SONiX TECHNOLOGY CO LTD Page 37 Preliminary Version 0 4 O SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 RESET 3 1 OVERVIEW The system would be reset in three conditions as following Power on reset Watchdog reset Brown out reset External reset When any reset condition occurs all system registers keep initial status program stops and program counter is cleared After reset status released the system boots up and program starts to execute from ORG 0 The NTO NPD flags indicate system reset status The system can depend on NTO NPD status and go to different paths by program
83. address will be inserted to bit O bit 11 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit8 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO PC 11 10 PC9 PC6 PC5 PC4 2 PC1 PCO After reset 0 0 0 0 0 0 0 0 0 0 0 0 PCL ONE ADDRESS SKIPPING There are nine instructions CMPRS INCS INCMS DECS DECMS 50 51 BOBTSO BOBTS1 with one address skipping function If the result of these instructions is true the PC will add 2 steps to skip next instruction If the condition of bit test instruction is true the PC will add 2 steps to skip next instruction BOBTS1 FC To skip if Carry_flag 1 JMP COSTEP Else jump to COSTEP COSTEP NOP BOMOV A BUFO Move BUFO value to ACC BOBTSO FZ To skip if Zero flag 0 JMP C1STEP Else jump to C1STEP C1STEP NOP If the ACC is equal to the immediate data or memory the PC will add 2 steps to skip next instruction CMPRS 12 To skip if ACC 12H JMP COSTEP Else jump to COSTEP COSTEP NOP SONiX TECHNOLOGY CO LTD Page 27 Preliminary Version 0 4 Ss N SN8P1929 aU N B 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit If the destination increased by 1 which results overflow of OxFF to 0x00 the PC will add 2 steps to skip next instruction INCS instruction INCS BUFO
84. al input and Two single ended inputs 3 Four single ended inputs This ADC is optimized for measuring low level unipolar or bipolar signals in weight scale and medical applications A very low noise chopper stabilized programmable gain instrumentation amplifier PGIA with selectable gains of 1x 12 5x 50x 100x and 200x in the ADC to accommodate these applications 11 2 ANALOG INPUT Following diagram illustrates a block diagram of the PGIA and ADC module The front end consists of a multiplexer for input channel selection a PGIA Programmable Gain Instrumentation Amplifier and the A gt ADC modulator To obtain maximum range of ADC output the ADC maximum input signal voltage V X X should be close to but can t over the reference voltage V R R Choosing a suitable reference voltage and a suitable gain of PGIA can reach this purpose The relative control bits are RVS 1 0 bits Reference Voltage Selection in ADCM register and GS 2 0 bits Gain Selection in AMPM register Cx Temperature Sensor Block Diagram of PGIA ADC module 1 The low pass filter Cx will filler out chopper frequency of PGIA Note 2 The recommend value of Cy is 0 1 F This capacitor needs to place as close chip as possible SONiX TECHNOLOGY CO LTD Page 114 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 11 3 Voltage Charge Pump R
85. an avoid VDD drop when CR2032 battery application If VDD source came from AA or AAA dry battery the delay time can be shorten to 50ms Note2 Please refer the SN8P1929 EV Board manual for the detail XBOMOV XBOBSET command SONiX TECHNOLOGY CO LTD Page 118 Preliminary Version 0 4 SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIN 11 4 PGIA Programmable Gain Instrumentation Amplifier SN8P1929 includes a low noise chopper stabilized programmable gain instrumentation amplifier PGIA with selection gains of 1x 12 5x 50x 100x and 200x by register AMPM The PGIA also provides two types channel selection mode 1 Two fully differential input 2 One fully differential input and Two single ended inputs 3 Four single ended inputs it was defined by register AMPCHS 11 4 1 AMPM Amplifier Mode Register Bits Bit2 0908 Bit Bito AMPM CHPENB BGRENB 51 FDSO 052 4651 GSO AMPENB 0 0 0 1 1 1 0 After Reset 0 BitO AMPENB PGIA function enable control bit 0 Disable PGIA function 1 Enable PGIA function Bit 3 1 GS 2 0 PGIA Gain Selection control bit GS 2 0 PGIA Gain 000 12 5 001 50 010 100 011 200 100 101 110 Reserved 111 1 X Note When selected gain is 1x PGIA be disabled 0 for power saving Bit5 4 FDS 1 0 Chopper Low frequency setting No
86. ance and SESS Table Ca Caves CR2032 2 4 3V CR2032 4 4 6V 4 TuF 4 TuF Note 1 When MCU source from CR2032 battery the AVE loading can t over 3mA for example the Load cell resistance can t over 1K Note 2 In AA AAA battery application the can loading 10mA current so that the Load cell can be up to 330 ohm Note 3 If VDD always over 4 2V Set Charge pump as Auto or Disable mode so that charge pump will disable and current consumption will not time 2 from AVDDR and AVE Capacitors of AVDDR and C C can be removed and Connect AVDDCP to VDD Note 1 The positive note of Cayppgce connect to AVDDCP and Negative note connect to VDD 2 The positive note of Cac connect to AVDDR and Negative note connect to ACM SONiX TECHNOLOGY CO LTD Page 134 Preliminary Version 0 4 SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC VDD 2 4V 4 2V Analog Capacitor Connection 9 a CAVDDC Cc CAVDDR AVDDR VDD 4 2V 5 5V Analog Capacitor Connection z O lt a Cavor AVDDR AVSS CAVE I L AVE or avor lt CAVE AVE 4 5 20 5 5 AvoncP q L svss Delay Time Charge Pump Enable Delay Enable Enable Enable honc Step 1 Step 2 ACM AVDDR AVE CPCKS 00001011B
87. carry then C 1 else 0 ADD lt if occur carry then C 1 else C 0 SBC A M lt A M if occur borrow then C 0 else C 1 SBC M amp A M if occur borrow then C 0 else 1 SUB lt A M if occur borrow then C 0 else 1 SUB M A M if occur borrow then 0 else 1 SUB lt if occur borrow then 0 else 1 DAA To adjust ACC s data format from HEX to DEC MUL AM R A A M The LB of product stored in Acc and HB stored in register ZF affected by lt A and M M A M lt A and M AND A Aand OR lt Aor M OR M AorM OR lt 1 A M A lt A xor M lt A xor M lt 63 60 67 64 lt M b7 b4 b3 b0 R SWAP P SWAPM M b3 b0 b7 b4 M b7 b4 b3 b0 R RRC M lt RRC M RRCM M M lt RRC M RLC M A lt RLC M E RLCM M M RLC M S CLR M 0 5 M b M b 0 BSET M b M b 1 BOBCLR M b M bank 0 b lt 0 BOBSET M b M bank 0 b lt 1 CMPRS Al 2 lt 1 then skip next instruction B CMPRS ZF C A M skip next instruction R INCS M lt M 1 If A 0 then skip next instruction A INCMS M M lt M 1 If M 0 then skip next instruction N DECS M lt M 1 If A 0 then skip next instruction C DECMS M M lt 1
88. control bit 0 Set P41 as I O Port 1 Set P41 as LBT function Bit2 LBTO Low Battery Detect Output Bit 0 P4 2 LBT voltage Higher than ACM 1 2V 1 P4 2 LBT voltage Lower than ACM 1 2V There are two circuit connections for LBT application One is using P4 0 and P4 1 which can avoid power consumption in sleep mode the another is using P4 0 only The second way will leak a small current in power down mode but can use P4 1 for Input application These two circuits are following LBTENB 1 1 LBTENB 1 4110 0 P5 1 as LBT function No leakage current in sleep mode P4 1 as Input port Leak current in sleep mode Low Battery Voltage R R2 LBTO i VDD 2 4V 1 33 0 0 66 0 VDD 3 6V 1 5MQ 0 5 0 VDD 4 8V Note Get LBTO 1 more 10 times in a raw every certain period ex 20 ms to make sure the Low Battery signal is stable SONiX TECHNOLOGY CO LTD Page 133 Preliminary Version 0 4 SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 11 5 7 Analog Setting and Application The most applications of SN8P1929 were for DC measurement ex Weight scale Pressure measure In different applications had each Analog capacitor setting to avoid VDD drop when Charge pump enable or can save cost Following table indicate different applications setting which MCU power source came from CR2032 battery AA AAA dry battery or external Regulator Resist
89. cuit Active System Mode Switching Diagram Operating mode description POWER DOWN MODE NORMAL SLOW GREEN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop Ext LRC Running Running Running Stop CPU instruction Executing Executing Stop Stop TO timer Active Active Active Inactive Active if TOENB 1 TCO timer Active Active Active Inactive Active if TCOENB 1 TC1 timer Active Active Inactive Inactive Active if TC1ENB 1 Watchdog timer By Watch_Dog By Watch_Dog By Watch_Dog By Watch_Dog Refer to code option 9 Code option Code option Code option Code option description Internal interrupt All active All active TO TCO All inactive External interrupt All active All active All active All inactive PO P1 TO TCO Wakeup source Reset PO P1 Reset EHOSC External high clock Ext LRC External low clock SONiX TECHNOLOGY CO LTD Page 55 Preliminary Version 0 4 S SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 2 SYSTEM MODE SWITCHING gt Example Switch normal slow mode to power down sleep mode BOBSET Set CPUMO 1 X Note During the sleep only the wakeup pin and reset can wakeup the system back to the normal mode gt Example Switch normal mode to slow mode BOBSET FCLKMD set CLKMD 1 Change the system into slow mode BOBSET FSTPHX stop external high speed oscillator fo
90. cycle boundary is BOBCLR FTC1OUT 0 255 Or BOBCLR FALOAD1 ALOAD1 TC1OUT 01 PWM cycle boundary is BOBSET FTC1OUT 0 63 Or BOBSET FALOAD1 ALOAD1 TC10UT 10 PWM cycle boundary is BOBCLR FTC1OUT 0 31 Or BOBSET FALOAD1 ALOAD1 TC1OUT 11 PWM cycle boundary is BOBSET FTC1OUT 0715 SONiX TECHNOLOGY CO LTD Page 97 Preliminary Version 0 4 SONIN Set TCO timer function mode BOBSET FTC1IEN Or BOBSET FTC1OUT Or BOBSET FPWM1OUT A Enable TCO timer BOBSET FTCOENB SONiX TECHNOLOGY CO LTD SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable TC1 interrupt function Enable TC10UT Buzzer function Enable PWM function Enable TC1 timer Page 98 Preliminary Version 0 4 SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 5 PWMO MODE 8 5 1 OVERVIEW PWM function is generated by TCO timer counter and output the PWM signal to PWMOOUT pin P5 4 The 8 bit counter counts modulus 256 bits The value of the 8 bit counter TCOC is compared to the contents of the reference register TCOR When the reference register value TCOR is equal to the counter value TCOC the PWM output goes low When the counter reaches zero the PWM output is forced high The ratio duty of the PWMO output is TCOR 256 MAX PWM PWM duty range TCOC valid value TCOR valid bits value Frequency Remark Fcpu 2
91. d system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 Watchdog timer application note is as following Before clearing watchdog timer check I O status and check RAM contents can improve system error Don t clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information SONiX TECHNOLOGY CO LTD Page 39 Preliminary Version 0 4 N SN8P1929 i A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 4 BROWN OUT RESET 3 4 1 BROWN OUT DESCRIPTION The brown out reset is a power dropping condition The power drops from normal voltage to low voltage by external factors e g EFT interference or external loading changed The brown out reset would make the system not work well or executing program error VDD System Work Well Area System Work Error Area VSS Brown Out Reset Diagram The power dropping might through the voltage range that s the system dead band The dead band means the power range can t offer the system minimum operation power requirement The above dia
92. data to ADCDH ADCDL 0 ADCDH ADCDL conversion data are not ready Bit2 WRS 1 0 ADC output Word Rate Selection Output Word Rate ADC clock 200K ADC clock 100K ADC clock 80K 50Hz 25 Hz 20 Hz 25Hz 12 5 Hz 10 Hz Note 1 AC power 50 Hz noise will be filter out when output word rate 25Hz Note 2 AC power 60 Hz noise will be filter out when output word rate 20Hz Note 3 Both AC power 50 Hz and 60 Hz noise will be filter out when output word rate 10Hz Note 4 Clear Bit DRDY after got ADC data or this bit will keep High all the time Note 5 Adjust ADC clock ADCKS and bit 50 can get suitable ADC output word rate SONiX TECHNOLOGY LTD Page 130 Preliminary Version 0 4 SONIN Example Charge Pump PGIA setting Fosc 4M X tal CPREG Init Enable AVDDR Enable Q ACM Enable QAVE Enable PGIA_Init PGIA_Enable ADC Init ADC_Enable QADC Wait Q ADC Read XBOBSET MOV XBOMOV MOV XBOMOV XBOBSET CALL MOV XBOMOV CALL XBOBSET CALL XBOBSET CALL XBOBSET CALL MOV XBOMOV XBOMOV XBOBSET MOV XBOMOV MOV XBOMOV MOV XBOMOV XBOBSET XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV FBGRENB A 00001011b CPCKS A A 00011100B CPM A FCPRENB Wait 200ms A 0000100b CPCKS A Wait 100ms FAVDDRENB Wait 10ms FACMENB Wait 5ms FAVENB
93. des a macro for safe jump table function This macro will check the ROM boundary and move the jump table to the right position automatically The side effect of this macro maybe wastes some ROM size gt Example If jump table crosses over ROM boundary will cause errors JMP_A MACRO VAL IF 1 amp OXFFOO VAL amp OXFFO0 JMP OXFF ORG OXFF ENDIF ADD PCL A ENDM Note VAL is the number of the jump table listing number gt Example JMP_A application SONIX macro file called MACRO3 H BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five JMP AOPOINT ACC 0 jump to AOPOINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 jump to A3POINT JMP A4POINT ACC 4 jump to A4POINT If the jump table position is across ROM boundary OxOOFF 0x0100 the JMP_A macro will adjust the jump table routine begin from next RAM boundary 0x0100 gt Example A operation Before compiling program ROM address BOMOV A BUFO BUFO is from 0 to 4 JMP_A 5 The number of the jump table listing is five OXOO0FD JMP AOPOINT ACC 0 jump to AOPOINT OXOOFE JMP A1POINT ACC 1 jump to ATPOINT OXOOFF JMP A2POINT ACC 2 jump to A2POINT 0X0100 JMP A3POINT ACC 3 jump to A3POINT 0X0101 JMP AAPOINT ACC 4 jump to A4POINT
94. dress will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBITO Read Write R W R W R W R W R W R W R W After reset z z Note Please refer to the LOOK UP TABLE DESCRIPTION about register look up table application SONiX TECHNOLOGY CO LTD Page 33 Preliminary Version 0 4 SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 2 ADDRESSING MODE 2 2 1 IMMEDIATE ADDRESSING MODE The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM gt Example Move the immediate data 12H to ACC MOV A 12H To set an immediate data 12H into ACC gt Example Move the immediate data 12H to R register BOMOV R 12H To set an immediate data 12H into R register Note immediate addressing mode application the specific RAM must be 0x80 0x87 working register 2 2 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC gt Example Move 0x12 RAM location data into ACC BOMOV A 12H To get a content of RAM location 0 12 of bank 0 and save ACC gt Example Move ACC data into 0x12 RAM location BOMOV 12H A To get a content of ACC and save in RAM
95. dressing register OPTION RCLK options Y Z Working YZ and ROM addressing register RBANK RAM bank select register PFLAG ROM page and special flag register AMPCHS PGIA channel selection AMPM PGIA mode register ADCM ADC s mode register AMPCKS PGIA clock selection CPM Charge pump mode ADCKS ADC clock selection DFM Decimation filter mode CPCKS Charge pump clock selection ADCDH ADC high byte data buffer ADCDL ADC low byte data buffer P1W Port 1 wakeup register Port input output mode register Port pull up register Py N data buffer INTRQ Interrupt request register INTEN Interrupt enable register OSCM Oscillator mode register LCDM1 LCD mode register PCH PCL Program counter TOM Timer 0 mode register TCOM Timer Counter 0 mode register Timer 0 counting register TCOC Timer Counter 0 counting register 1 Timer Counter 1 mode register TCOR Timer Counter 0 auto reload data buffer TC1C Timer Counter 1 counting register LBTM Low Battery Detect Register STKP Stack pointer buffer STKO STK7 Stack 0 stack 7 buffer HL indirect addressing index pointer ROMADRH L ISP ROM Address YZ RAM YZ indirect addressing index pointer ROMDAH L ISP ROM Data Working register and ROM look up data buffer ROMCNT ISP ROM Counter SONiX TECHNOLOGY CO LTD Page 22 Preliminary Version 0 1 SN8P1929 D D E A 8 Bit Micro Controller with Charge pump Regulator PGIA
96. e for TC1 interrupt TC1 clock source is Fcpu TC1KS 0 TC1X8 0 PWM output PWM1 0 High clock is external 4MHz FcpuzFosc 4 Select TC1RATE 010 64 initial value N TC1 interrupt interval time input clock 256 10ms 4MHz 4 64 256 102 4 106 4 64 100 64H The basic timer table interval time of TC1 TC1X1 0 One step 256 One step 256 31250 15625 7812 5 us 3906 25 us 1953 125 us Fosc 128 Fosc 64 SONiX TECHNOLOGY CO LTD Page 94 Preliminary Version 0 4 Ss SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 5 TC1R AUTO LOAD REGISTER TC1 timer is with auto load function controlled by ALOAD1 bit of TC1M When TC1C overflow occurring TC1R value will load to TC1C by system It is easy to generate an accurate time and users don t reset TC1C during interrupt service routine Note Under PWM mode auto load is enabled automatically The ALOAD1 bit is selecting overflow boundary ODEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1RO Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC1R initial value is as following initial value N TC1 interrupt interval time input clock N is TC1 overflow boundary number TC1 timer overflow time has
97. egulator CPR SN8P1929 is built in a CPR which can provide a stable 3 8V pin AVDDR and 3 0V 2 4V 1 5V pin AVE with maximum 10mA current driving capacity Register CPM can enable or disable CPR and controls CPR working mode another register CPCKS sets CPR working clock to 4KHz Because the power of PGIA and ADC is come from AVDDR turn on AVDDR AVDDRENB 1 first before enabling PGIA and ADC The AVDDR voltage was regulated from AVDDCP In addition the CP will need at least 10ms for output voltage stabilization after set CPRENB to high 11 3 1 CPM Charge Pump Mode Register 095H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPM ACMENB AVDDRENB AVENB AVESEL1 AVESELO CPAUTO CPON CPRENB R W R W R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 Bito CPRENB Charge Pump Regulator function enable control bit 0 Disable charge pump and regulator 1 Enable charge pump and regular Bit1 CPON Change Pump always ON function control bit CPRENB must 1 0 Charge Pump On Off controlled by bit CPAUTO 1 Always turn ON the charge pump regulator Bit2 CPAUTO Charge Pump Auto Mode function control bit 0 Disable charge pump auto mode 1 Enable charge pump auto mode Bit3 4 AVESEL 1 0 AVE voltage selection control bit AVESEL1 AVESELO AVE Voltage 1 1 30V 3 0V 1 1 L1 0 24V 1 2 E 24 L0 0 Reseved Bit5 AVENB AVE voltage out
98. eliminary Version 0 1 O N SN8P1929 BW wu N H 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit APPENDIX A EV KIT BOARD eo cities reir ePi 147 8 ELECTRICAL CHARACTERISTIC i isessassstcassssscassansesesesvesscnsensssnaonn FER MEREDR Y EMI aov 148 8 1 ABSOLUTE MAXIMUM RATING sprite cesses 148 6 2 ELECTRICAL CHARACTERISTIC iini ed tent ti Ee bao tom ta 148 9 PACKAGE INFORMATION ose ERO UE 151 9 1 LQFP 80 PIN 151 10 MARKING 152 10 4 n 152 10 2 MARKING IDENTIFICATION 152 IUS MARKINGEXAMPLE Desi dace SUM dace uda usi 153 104 DATECODE SYSTEM embed tuus 153 SONiX TECHNOLOGY CO LTD Page 5 Preliminary Version 0 1 SONIN 1 SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC PRODUCT OVERVIEW 1 1 SELECTION TABLE
99. er interrupt vector If the TOIEN O the trigger event will make the TOIRQ to be 1 but the system will not enter interrupt vector Users need to care for the operation under multi interrupt situation Example TO interrupt request setup BOBCLR FTOIEN Disable TO interrupt service BOBCLR FTOENB Disable TO timer MOV A 20H BOMOV TOM A Set TO clock Fcpu 64 MOV A 74H Set TOC initial value 74H BOMOV TOC A Set TO interval 10 ms BOBSET FTOIEN Enable TO interrupt service BOBCLR FTOIRQ Clear TO interrupt request flag BOBSET FTOENB Enable TO timer BOBSET FGIE Enable GIE Example TO interrupt service routine ORG 8 Interrupt vector JMP INT SERVICE INT SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FTOIRQ Check TOIRQ JMP EXIT INT TOIRQ 0 exit interrupt vector BOBCLR FTOIRQ Reset TOIRQ MOV A 74H BOMOV TOC A Reset TOC 0 TO interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 67 Preliminary Version 0 4 N SN8P1929 aU N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 9 TCO INTERRUPT OPERATION When the TCOC counter overflows the TCOIRQ will be set to 1 no matter the TCOIEN is enable or disable If the TCOIEN and the trigger event TCOIRQ is set to be 1 As the result the system will execute the interrupt vector
100. errupt request indication flags Each one of the interrupt requests occurs the bit of the INTRQ register would be set 1 The INTRQ value needs to be clear by programming after detecting the flag In the interrupt vector of program users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ TC1IRQ TCOIRQ TOIRQ Read Write R W R W RAW R W R W After reset 0 0 0 0 0 Bit 0 POOIRQ External P0 0 interrupt INTO request flag 0 None INTO interrupt request 1 INTO interrupt request Bit 1 External PO 1 interrupt INT1 request flag 0 None INT1 interrupt request 1 INT1 interrupt request Bit4 TOIRQ TO timer interrupt request flag 0 None TO interrupt request 1 TO interrupt request Bit 5 TCOIRQ TCO timer interrupt request flag 0 None TCO interrupt request 1 TCO interrupt request Bit 6 TC1IRQ TC1 timer interrupt request flag 0 None TC1 interrupt request 1 TC1 interrupt request 6 4 GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit interrupts start work after the GIE 1 It is necessary for interrupt service request One of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level
101. ers in the beginning of the program MOV A 00001111B BOMOV STKP A OFOH OFFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnH SnPC11 SnPC10 SnPC9 SnPC8 Read Write R W R W R W R W After reset 0 0 0 0 OFOH OFFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKnL SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 STKn STKnH STKnL 7 0 SONiX TECHNOLOGY CO LTD Page 36 Preliminary Version 0 4 SN8P1929 D B 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit 2 3 3 STACK OPERATION EXAMPLE The two kinds of Stack Save operations refer to the stack pointer STKP and write the content of program counter PC to the stack buffer are CALL instruction and interrupt service Under each condition the STKP decreases and points to the next available stack location The stack buffer stores the program counter about the op code address The Stack Save operation is as the following table Stack Level STKP Register Stack Buffer STKPBO Hi o 1 Fee J stko smk Sra Std STK6L sf Stack Over error Description Lo 1 1 Lo sg 1201 4 02 1 1 0 tt t u There are Stack Restore operations correspond to e
102. eserved N A N A Note 1 V Al Al Al voltage Al voltage Note 2 V Al ACM Al voltage ACM voltage Note 3 The purpose of Input Short mode is only for PGIA offset testing Note 4 When CPR is Disable or system in stop mode signal on analog input pins must be Zero 0 V including Al Al X X R and R or it will cause the current consumption from these pins AMPCHSJ 3 0 0000 AMPCHSJ 3 0 001 0 Alt l l cae te pl AMPCHS 3 0 z 001 1 AMPCHS 2 0 0110 cm F aet E Alt IACM l ACM AL eee ee 1 SONiX TECHNOLOGY CO LTD Page 121 Preliminary Version 0 4 SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC N 7 SONIX 11 4 4 Temperature Sensor TS In applications sensor characteristic might change in different temperature also To get the temperature information SN8P1929 build in a temperature senor TS for temperature measurement Select the respective PGIA channel to access the Temperature Sensor ADC output AMPCHS 3 0 1000 Note1 When selected Temperature Sensor PGIA gain must set to 1x or the result will be incorrect Note2 Under this setting X will be the V TS voltage and X will be 0 8V Note3 The Temperature Sensor was just a reference dala not real air temperature For precision applica
103. et 0 0 0C4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4M P42M P41M P40M Read Write R W R W R W After reset 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P54M P53M P52M P51M P50M Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 7 0 PnM 7 0 Pn mode control bits n 0 5 0 Pnis input mode 1 Pn is output mode 1 Users can program them by bit control instructions BOBSET BOBCLR 2 Port 0 is input only port 3 Port2 is shared with XIN and XOUT gt Example I O mode selecting CLR P1M Set all ports to be input mode CLR P2M MOV A HOFFH Set all ports to be output mode BOMOV P1M A BOMOV P2M A BOBCLR P1M 0 Set P1 0 to be input mode BOBSET P1M 0 Set P1 0 to be output mode SONiX TECHNOLOGY CO LTD Page 72 Preliminary Version 0 4 SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 7 2 O PULL UP REGISTER OEOH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POUR PO1R POOR Read Write After reset 0 0 OE1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1UR P13R P12R P11R P10R Read Write After reset 0 0 0 0 OE2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P
104. f TC1 timer occurs an overflow it will continue counting and issue a time out signal to trigger TC1 interrupt to request interrupt service TC1 overflow time is OxFF to 0 00 normally Under PWM mode TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC10OUT bits The main purpose of the TC1 timer is as following 8 bit programmable up counting timer Generates interrupts at specific time intervals based on the selected clock frequency External event counter Counts system events based on falling edge detection of external clock signals at the INT1 input pin Buzzer output PWM output Fcpu 2 Fcpu 256 Fcpu TC1 Rate gt TC1X8 Fosc gt TC1 Rate Fosc 1 Fosc 128 INT1 Schmitter Trigger L Internal P5 3 I O Circuit TC1OUT ALOAD1 J Y Buzzer le Aa Reload TC1 2 A ee ALOAD1 TC1OUT Data Buffer JR PWM1OUT Compare EAM TC1CKS 1 B m s Load M TC1C X 8 Bit Binary Up gt TC1 Time Out SONiX TECHNOLOGY CO LTD Counting Counter 1 Page 90 Preliminary Version 0 4 SONIN 8 4 2 TC1M MODE REGISTER SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC ODCH Bit 7 Bit 6
105. for store ACC data CODE ORG 0 0000H JMP START Jump to user program address ORG 8 Interrupt vector BOXCH A ACCBUF Save ACC in a buffer PUSH Save 0x80 0x87 working registers and PFLAG register to buffers POP Load 0x80 0x87 working registers and PFLAG register from buffers BOXCH A ACCBUF Restore ACC from buffer RETI End of interrupt service routine START The head of user program 245 User program JMP START End of user program ENDP End of program SONiX TECHNOLOGY CO LTD Page 13 Preliminary Version 0 1 SONIN SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Defining Interrupt Vector The interrupt service routine is following user program DATA ACCBUF CODE ORG JMP ORG JMP ORG START JMP MY IRQ BOXCH PUSH POP BOXCH RETI ENDP DS 1 0 START IRQ 10H START A ACCBUF A ACCBUF Define ACCBUF for store ACC data 0000H Jump to user program address Interrupt vector 0008H Jump to interrupt service routine address 0010H The head of user program User program End of user program The head of interrupt service routine Save ACC in a buffer Save 0x80 0x87 working registers and PFLAG register to buffers Load 0x80 0x87 working registers and PFLAG register from buffers Restore ACC from buffer End of interrupt service routine End of program Note
106. gram is a typical brown out reset diagram There is a serious noise under the VDD and VDD voltage drops very deep There is a dotted line to separate the system working area The above area is the system work well area The below area is the system work error area called dead band V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC application The power source of DC application is usually using battery When low battery condition and MCU drive any loading the power drops and keeps dead band Under the situation the power won t drop deeper and not touch the system reset voltage That makes the system under dead band AC application In AC power application the DC power is regulated from AC power source This kind of power usually couples with AC noise that makes the DC power dirty Or the external loading is very heavy e g driving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the system works under unstable power situation The power on duration and power down duration are longer in AC application The system power on sequence protects the power on successful but the power down situation is like DC low battery condition When turn off the AC power the VDD drops slowly and through the dead band for a while SONiX TECHNOLOGY C
107. ias 1 LCD Bias is 1 2 Bias 9 2 OPTION REGISTER DESCRIPTION OPTION initial value xxx0 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 RCLK R W After Reset RCLK External low oscillator type control bit 0 Crystal Mode 1 RC mode gt 1 Circuit diagram when 0 External Low Clock sets as Crystal mode LXIN LXOUT VSS VSS SONiX TECHNOLOGY CO LTD Page 105 Preliminary Version 0 4 N SN8P1929 D i N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt 2 Circuit diagram when RCLK 1 will enable external Low Clock sets as RC mode LXIN VSS 20P Connect the C as near as possible to the VSS pin of micro controller The frequency of external low RC is decided by the capacitor value Adjust capacitor value to about 32KHz frequency LCD frame rate is supplied from external Low clock and frame rate is 64Hz 32768Hz 512 9 3 LCD TIMING LCD frame rate is always supplied from external Low clock and frame rate is 64Hz 32768Hz 512 LCD Clock 1 Frame gt lt 1 Frame gt VLCD COMO 1 2 VLCD vss VLCD 1 1 2 VLCD VSS VLCD COM2 1 2 VLCD VSS VLCD COM
108. icro Controller with Charge pump Regulator PGIA 16 bit ADC 8 2 3 TOC COUNTING REGISTER TOC is an 8 bit counter register for TO interval time control OD9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOC TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOCO Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TOC initial value is as following TOC initial value 256 TO interrupt interval time input clock gt Example To set 10ms interval time for TO interrupt High clock is external 4MHz Fcpu Fosc 4 Select TORATE 010 64 TOC initial value 256 TO interrupt interval time input clock 256 10ms AMHz 4 64 256 10 2 4 106 4 64 100 64 The basic timer table interval time of TO TORATE TOCLOCK High speed mode Fcpu 4MHz 4 Low speed mode Fcpu 32768Hz 4 Max overflow interval One step max 256 Max overflow interval One step max 256 Fcpu 256 65 536 ms 8000 ms 31250 us Fcpu 128 32 768 ms 4000 ms 15625 us Fcpu 64 16 384 ms 2000 ms 7812 5 us 500 ms 250 ms 125 ms 62 5 ms Fcpu 32 8 192 ms 1000 ms 3906 25 us gt Note TOC is not available RTC mode The interval time is fixed at 0 5 sec SONiX TECHNOLOGY CO LTD Page 79 Preliminary Version 0 4 N SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit
109. illator module is controlled by High code option The start up time of crystal ceramic and RC type oscillator is different RC type oscillator s start up time is very short but the crystal s is longer The oscillator start up time decides reset time length 4MHz Crystal 4MHz Ceramic SONiX TECHNOLOGY CO LTD Page 50 Preliminary Version 0 4 Ss SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 4 21 CRYSTAL CERAMIC Crystal Ceramic devices are driven by XIN XOUT pins For high normal low frequency the driving currents are different High code option supports different frequencies 12M option is for high speed ex 12MHz 4M option is for normal speed 4MHz XIN CRYSTAL MCU 20 SSA Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of micro controller 4 4 2 2 EXTERNAL CLOCK SIGNAL Selecting external clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN pin XOUT pin is general purpose I O pin External Clock Input XIN XOUT MCU VSS VDD Note The GND of external oscillator circuit must be as near as possible to VSS of micro controller SONiX TECHNOLOGY CO LTD Page 51 Prelimi
110. in level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is larger than 0 7V The external reset circuit is with a stable current through R1 and R2 For power consumption issue application e g DC power system the current must be considered to whole system power consumption Note Under unstable power condition as brown out reset Zener diode rest circuit and Voltage bias reset circuit can protects system no any error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes reset sequence That makes sure the system work well under unstable power situation SONiX TECHNOLOGY CO LTD Page 45 Preliminary Version 0 4 SN8P1929 D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 6 5 External Reset IC The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different application and system requirement to select suitable reset IC The reset circuit can improve all power variation SONiX TECHNOLOGY CO LTD Page 46 Preliminary Version 0 4 65 RN Q SN8P1929 aU A 8 Bit Micro Controller with Charge
111. interrupt event counter TCOOUT and PWM The sequence of setup TCO timer is as following Stop TCO timer counting disable TCO interrupt function and clear TCO interrupt request flag BOBCLR FTCOENB TCO timer TCOOUT and PWM stop BOBCLR FTCOIEN TCO interrupt function is disabled BOBCLR FTCOIRQ TCO interrupt request flag is cleared TCO timer rate Besides event counter mode MOV A 0xxx0000b TCO rate control bits exist bit4 bit6 of TCOM The value is from x000 oxxb x1 11xxxxb BOMOV TCOM A interrupt function is disabled TCO timer clock source Select TCO internal external clock source BOBCLR FTCOCKS Select TCO internal clock source or BOBSET FTCOCKS Select TCO external clock source Select TCO Fosc internal clock source BOBCLR FTCOX8 Select TCO internal clock source or BOBSET FTCOX8 Select TCO Fosc internal clock source Note TCOX8 is useless in TCO external clock source mode Set TCO timer auto load mode BOBCLR FALOADO Enable TCO auto reload function or BOBSET FALOADO Disable TCO auto reload function Set TCO interrupt interval time TCOOUT Buzzer frequency or PWM duty cycle Set TCO interrupt interval time TCOOUT Buzzer frequency or PWM duty MOV A 7FH TCOC and TCOR value is decided by TCO mode BOMOV TCOC A Set TCOC value BOMOV TCOR A Set TCOR value under auto reload mode or PWM m
112. ion of TC1C initial value is as following TC1C initial value N TC1 interrupt interval time input clock N is TC1 overflow boundary number TC1 timer overflow time has six types TC1 timer TC1 event counter TC1 Fcpu clock source TC1 Fosc clock source PWM mode and no PWM mode These parameters decide TC1 overflow time and valid value as follow table TC1C valid TC1C value TC1x8 E ALOADi TCioUT TEC value x x 25e oxoo oxFF 00000000b 11111111b Overflow 256 count 0 00 00000000b 11111111b Overflow per 256 count 2 1 0 1 64 0 00 0 3 xx000000b xx111111b Overflow 64 count Fcpu 256 1 1 o 32 0 00 0 1 xxx00000b xxx11111b Overflow per 32 count 1 1 1 16 0 00 0 0 0000 11115 Overflow per 16 count 0 x x 256 0 00 0 00000000b 11111111b Overflow per 256 count 1 1 0 0 256 0 00 0 00000000b 11111111b Overflow per 256 count Fosci 1 0 1 64 0 00 0 xx000000b xx111111b Overflow per 64 count 128 1 1 0 32 0 00 000005 1111175 Overflow per 32 count LS 256 0 00 0 00000000b 11111111b Overflow per 256 count SONiX TECHNOLOGY CO LTD Page 93 Preliminary Version 0 4 N SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example To set 10ms interval tim
113. ller with Charge pump Regulator PGIA 16 bit ADC 12 2 Thermometer Application Circuit Note Please refer 10 5 7 for capacitor setting VDD AVDDR N 1 5 5000 S a E jogwg 9 9 VLCD EJ cl x SEG 220 Thermopile x SEG 230I 400 104 RST R 10K VDD eJ Pin31 Al P5 4 Al I 5 0 lt j CacM 4 2 Skiet acm 5 P4 1 U CAVDDR T HADR z 8 5 ozar Nm PHO zx o Q9QE8U X X x 9 gg k amp amp amp I 32768 3 58M CAVE X tal X tal LS Ld Ur VDD 5 20pF 20pF 20pF 20pF SONiX TECHNOLOGY CO LTD Page 137 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 3 INSTRUCTION TABLE Field Mnemonic Description MOV A M A M MOV M A A M lt M bnak 0 BOMOV M A M bank 0 A MOV lt 1 BOMOV lt 1 only for Working registers R Y 27 RBANK amp PFLAG XCH BOXCH A M gt bank 0 MOVC R A lt ROM Y Z ADC A lt M C if occur carry then 1 else C 0 ADC C if occur carry then C 1 else C 0 ADD if occur carry then 1 else 0 ADD M A M M if occur carry then C 1 else C 0 BOADD M A M bank 0 lt M bank 0 A if occur
114. location 12H of bank 0 2 2 3 INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to access the memory by the data pointer registers H L Y Z Example Indirectly addressing mode with HL register BOMOV H 40 To clear H register to access RAM bank 0 BOMOV L 12H To set an immediate data 12H into L register BOMOV A HL Use data pointer HL reads a data from RAM location 012H into ACC Example Indirectly addressing mode with YZ register BOMOV Y 0 To clear Y register to access RAM bank 0 BOMOV Z 12H set an immediate data 12H into Z register BOMOV A YZ Use data pointer QYZ reads a data from RAM location 012H into ACC SONiX TECHNOLOGY CO LTD Page 34 Preliminary Version 0 4 N SN8P1929 aU A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 3 STACK OPERATION 2 3 1 OVERVIEW The stack buffer has 8 level These buffers are designed to push and pop up program counter s PC data when interrupt service routine and CALL instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program counter PC data RET CALL RETI INTERRUPT 1 PCL STACK Buffer STACK Buffer STACK Level High Byte Low Byte TKP 7 STKP 1 STKP 1 E STKP 6 STKP 5 STKP STKP 4 STKP 3 STKP 2 5
115. mp here and don t clear watchdog Wait watchdog timer overflow to reset IC Correct and RAM are correct Clear watchdog timer and execute program BOBSET FWDRST Only one clearing watchdog timer of whole program CALL SUB1 CALL SUB2 JMP MAIN SONiX TECHNOLOGY CO LTD Page 76 Preliminary Version 0 4 N SN8P1929 D i D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 2 TIMER 0 TO 8 2 1 OVERVIEW The TO is an 8 bit binary up timer and event counter If TO timer occurs an overflow from to 00H it will continue counting and issue a time out signal to trigger TO interrupt to request interrupt service The main purposes of the TO timer is as following A 8 bit programmable up counting timer Generates interrupts at specific time intervals based on the selected clock frequency timer Generates interrupts at real time intervals based on the selected clock source RTC function is only available in 1 Green mode wakeup function TO can be green mode wake up time as TOENB 1 System will be wake up by TO time out TO Rate Fcpu 2 Fcpu 256 Internal Data Bus nd TOTB gt gt TOC 8 Bit Binary Up Counting Counter 2200 CPUMO 1 m gt Time Out RTC gt gt Note In RTC mode the TO interval time is fixed at 0 5 sec isn t controlled by TOC SONiX
116. n 200 Set AMPCKS 100 for PGIA working clock 1 9K 4M X tal Selected PGIA differential input channel Al1 Al1 Enable PGIA function V X X Output V Al1 AI1 x 200 Don t Disable PGIA when change PGIA CH Enable Band Gap Set FDS 11 CHPENB 1 PGIA Gain 200 Selected PGIA as Differential channel V X X Output V AI2 AI2 x 200 Don t Disable PGIA when change PGIA CH Enable Band Gap Set 5 11 CHPENB 1 Gain 1x Selected PGIA as Temperature Sensor ch V X X Output V TS 0 4 x 1 Page 124 Preliminary Version 0 4 S SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC NiX 11 5 16 Bit ADC 11 5 1 ADCM ADC Mode Register 093H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCM IRVS RVS1 RVSO ADCENB R W R W R W R W R W After Reset 0 0 0 0 0 Bito ADCENB ADC function control bit 0 Disable 16 bit ADC 1 Enable 16 bit ADC Bit1 RVS 0 ADC Reference Voltage Selection bit 0 Selection ADC as normal operation from X X 1 Selection ADC as VDD voltage detect Bit2 RVS 1 ADC Reference Voltage Selection bit 1 0 Selection ADC Reference voltage from External reference R R 1 Selection ADC Reference voltage from Internal reference Bit3 IRVS Internal Reference Voltage Selection 0 Internal Reference Voltage V REF REF is AVE 0 133 When A
117. nary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 5 SYSTEM LOW CLOCK The system low clock source is the external low speed oscillator The low speed oscillator can use 32768 crystal or RC type oscillator circuit 4 5 1 1 CRYSTAL Crystal devices are driven by LXIN LXOUT pins The 32768 crystal and 10uF capacitor must be as near as possible to MCU LXIN 32768Hz LXOUT MCU 10 4 5 1 2 RC Type LXOUT LXIN 22pF 3v L 2 M C U 35pF SV T VDD VSS The external low clock supports watchdog clock source and system slow mode controlled by CLKMD A Flosc External low oscillator Slow mode Flosc 4 SONiX TECHNOLOGY CO LTD Page 52 Preliminary Version 0 4 SN8P1929 bU N 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC In power down mode the external low clock will be Stop gt Example Stop internal low speed oscillator by power down mode BOBSET FCPUMO To stop external high speed oscillator and internal low speed oscillator called power down mode sleep mode Note The external low speed clock can t be turned off individually It is controlled by CPUMO CPUM1 bits of OSCM register SONiX TECHNOLOGY CO LTD Page 53 Preliminary Version 0 4 N SN8P1929 aU wu N B A 8 Bit Micro Controller with Charge pump Regulator
118. nce voltage V R R power JP11 ACM ACE AVDDR AVDDCP output port JP12 This jumper short as RST VPP VDD for normal operation or short as RST VPP 12 5V for executing ISP function J2 AVSS and VSS SHORT R5 R6 R7 Resistors for ADC external reference voltage R8 R9 R10 LBT function resistance R23 R24 R25 LCD External resistors for voltage division User can add resistance between VLCD V3 2 V1 for more driving current Ev board connects ICE Ev board connects WRITER Only EV board JP1 Disconnect Write in SN8P1929 Disconnect JP2 LCD No Function Depends on actual situation JP3 VL CD Connect to VDD or AVE Connect to VDD Depends on actual situation JP4 Disconnect all Disconnect all Connect all JP5 Depends on actual situation Disconnect Depends on actual situation JP6 7 8 9 10 11 Depends on actual situation Depends on actual situation J1 Depends on actual situation Short J2 U1 Short SN8P1929 EV Link IC only Blank 5 8 1929 IC for programming Short SN8P1929 IC with system application code R8 R9 R10 LBT Depends on actual situation SONiX TECHNOLOGY CO LTD Depends on actual situation Page 141 Preliminary Version 0 4 SONIX EV Board U1 requires IC board embedded with connection program when attach to each other 2 When power source is supply from the ICE
119. ne interrupt requests Processing multi interrupt request requires setting the priority of the interrupt requests The IRQ flags of interrupts are controlled by the interrupt event Nevertheless the IRQ flag 1 doesn t mean the system will execute the interrupt vector In addition which means the IRQ flags can be set 1 by the events without enable the interrupt Once the event occurs the IRQ will be logic 1 The IRQ and its trigger event relationship is as the below table Interrupt Name Trigger Event Description POOIRQ P0 0 trigger controlled by PEDGE TOIRQ TOC overflow For multi interrupt conditions two things need to be taking care of One is to set the priority for these interrupt requests Two is using IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bit and interrupt request flag in interrupt routine SONiX TECHNOLOGY CO LTD Page 70 Preliminary Version 0 4 N SN8P1929 i D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Check the interrupt request under multi interrupt operation ORG 8 Interrupt vector JMP INT SERVICE INT SERVICE Push routine to save ACC and PFLAG to buffers INTPOOCHK Check INTO interrupt request BOBTS1 FPOOIEN Check POOIEN JMP INTPO1CHK Jump check to next interrupt BOBTSO FPOOIRQ Check POOIRQ JMP INTPOO INTPO1CHK Check INT1 interrupt request BOBTS1 FPO1IEN Check PO1IEN JMP
120. nted and program jump to ORG 8 to execute interrupt service routines The program exits the interrupt service routine when the returning interrupt service routine instruction RETI is executed 0C9H Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN TCOIEN TOIEN PO1IEN POOIEN Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 POOIEN External P0 0 interrupt INTO control bit 0 Disable INTO interrupt function 1 Enable INTO interrupt function Bit 1 PO1IEN External PO 1 interrupt 1 control bit 0 Disable INT1 interrupt function 1 Enable INT1 interrupt function Bit4 TOIEN TO timer interrupt control bit 0 Disable TO interrupt function 1 Enable TO interrupt function Bit 5 TCOIEN TCO timer interrupt control bit 0 Disable TCO interrupt function 1 Enable TCO interrupt function SONiX TECHNOLOGY CO LTD Page 60 Preliminary Version 0 4 N 9 SN8P1929 D 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Bit 6 TC1IEN TC1 timer interrupt control bit 0 Disable TC1 interrupt function 1 Enable TC1 interrupt function SONiX TECHNOLOGY CO LTD Page 61 Preliminary Version 0 4 SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 3 INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register The register includes all int
121. ock signal is output to P5 3 and the P5 3 general purpose function is auto disable The TC1OUT frequency is divided by 2 from TC1 interval time TC1OUT frequency is 1 2 TC1 frequency The TC1 clock has many combinations and easily to make difference frequency The TC1OUT frequency waveform is as following TC1 Overflow Clock TC10OUT Buzzer Output Clock gt Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC10OUT frequency is 0 5KHz Because the TC1OUT signal is divided by 2 set the TC1 clock to 1KHz TC1 clock source is from external oscillator clock TC1 rate is Fcpu 4 The TCORATE2 TCORATE1 110 TCOC TCOR 131 MOV A 01100000B BOMOV TC1M A Set the TC1 rate to Fcpu 4 MOV A 131 Set the auto reload reference value BOMOV 1 BOMOV TCIR A BOBSET FTC1OUT Enable TC1 output to P5 3 and disable P5 3 I O function BOBSET FALOAD1 Enable TC1 auto reload function BOBSET Enable TC1 timer Note Buzzer output is enable and PWM1OUT must be 0 SONiX TECHNOLOGY CO LTD Page 96 Preliminary Version 0 4 Ss SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 4 7 TC1 TIMER OPERATION SEQUENCE TC1 timer operation includes timer interrupt event counter TC1OUT and PWM The sequence of setup TC1 timer is as following
122. ode In PWM mode set PWM cycle BOBCLR FALOADO ALOADO TCOOUT 00 PWM cycle boundary is BOBCLR FTCOOUT 0 255 Or BOBCLR FALOADO ALOADO TCOOUT 01 PWM cycle boundary is BOBSET FTCOOUT 0 63 or BOBSET FALOADO ALOADO TCOOUT 10 PWM cycle boundary is BOBCLR FTCOOUT 0 31 or BOBSET FALOADO ALOADO TCOOUT 11 PWM cycle boundary is BOBSET FTCOOUT 0 15 SONiX TECHNOLOGY CO LTD Page 88 Preliminary Version 0 4 SONIN Set TCO timer function mode or or or BOBSET BOBSET BOBSET BOBSET Enable TCO timer BOBSET FTCOIEN FTCOOUT FPWMOOUT FTCOGN FTCOENB SONiX TECHNOLOGY CO LTD SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Enable TCO interrupt function Enable TCOOUT Buzzer function Enable PWM function Enable TCO green mode wake up function Enable TCO timer Page 89 Preliminary Version 0 4 SONIN 8 4 TIMER COUNTER 1 TC1 8 4 1 OVERVIEW SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC The TC1 is an 8 bit binary up counting timer TC1 has two clock sources including internal clock and external clock for counting a precision time The internal clock source is from or Fosc controlled by TC1X8 flag to get faster clock source Fosc The external clock is INT1 from 1 pin Falling edge trigger Using TC1M register selects TC1C s clock source from internal or external I
123. oes not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part Main Office Address 9F NO 8 Hsien Cheng 5th St Chupei City Hsinchu Taiwan R O C Tel 886 3 551 0520 Fax 886 3 551 0523 Taipei Office Address 15F 2 NO 171 Song Ted Road Taipei Taiwan R O C Tel 886 2 2759 1980 Fax 886 2 2759 8180 Hong Kong Office Address Flat 3 9 F Energy Plaza 92 Granville Road Tsimshatsui East Kowloon Tel 852 2723 8086 Fax 852 2723 9179 Technical Support by Email
124. og time out Reset by LVD Reset by external Reset Pin Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotation with shifting out logic 1 comparison result 20 0 Addition without carry subtraction with borrowing signal rotation with shifting out logic O comparison result lt 0 Bit 1 DC Decimal carry flag 1 Addition with carry from low nibble subtraction without borrow from high nibble 0 Addition without carry from low nibble subtraction with borrow from high nibble Bit 0 Z Zero flag 1 The result of an arithmetic logic branch operation is zero 0 The result of an arithmetic logic branch operation is not zero Note Refer to instruction set table for detailed information of DC and 2 flags SONiX TECHNOLOGY CO LTD Page 26 Preliminary Version 0 4 SN8P1929 N B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 6 1 PROGRAM COUNTER The program counter PC is a 12 bit binary counter separated into the high byte 4 and the low byte 8 bits This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit Normally the program counter is automatically incremented with each instruction during program execution Besides it can be replaced with specific address by executing CALL or JMP instruction When JMP or CALL instruction is executed the destination
125. ogramming users must set the first line in the main program to real chip mode for OTP programming example is as follows ICE Mode EQU 0 CHIP SN8P1929 Warning 1 When monitoring the special registers of XBOMOV table over the ICE we suggest users to copy the XBOMOV to USER RAM area 2 Do not use special instruction table ie XBOMOV that has not been descried in the previous chapter to avoid unexpected malfunction 14 2 9 EXAMPLE PROGRAM CODE STRUCTURE eek eee e e eee he ee e hee ee hee e e hee ehe hee e hee he ehe ehe e hee hee hee hee ehe hee he hee hee ehe hee hee hee hee hee hee hehe ee eee e FILENAME 1929 Demo ASM AUTHOR 5 PURPOSE Demo Code for SN8P1929 eee eee e e ehe e he ee e hee ee hee e ehe ee he hee ehe ehe ehe ehe REREREREREREREKEREERERERERERERERERERERERER c Copyright 2008 TECHNOLOGY CO LTD eek eee e e ehe ehe hee e hee hee hee e ehe e ehe hee e he ehe ee ehe e hee ee hee ehe eee hee ehe hee hee hee hehe hee hehehe ee eee e ICE Mode EQU 1 1 for ICE 0 for real chip Mode EQU 0 CHIP SN8P1929 Select the CHIP nolist do not list the macro file INCLUDESTD MACRO1 H INCLUDESTD 2 INCLUDESTD MACRO3 H INCLUDE 1929Ev h for ICE linking emulation board SONiX TECHNOLOGY CO LTD Page 144 Preliminary Version 0 4 SONIX SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC list Enable the listing function
126. on 0 4 N SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example To set 10ms interval time for TCO interrupt TCO clock source is Fcpu TCOKS 0 0 8 0 and PWM output PWMOzO High clock is external 4MHz FcpuzFosc 4 Select TCORATE 010 64 TCOC initial value N TCO interrupt interval time input clock 256 10ms AMHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of TCOX8 0 TCORATE One step max 256 One step max 256 31250 us 15625 us 7812 5 us 3906 25 us 1953 125 us Fosc 128 Fosc 64 SONiX TECHNOLOGY CO LTD Page 85 Preliminary Version 0 4 SN8P1929 D D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 5 TCOR AUTO LOAD REGISTER TCO timer is with auto load function controlled by ALOADO bit of TCOM When TCOC overflow occurring TCOR value will load to TCOC by system It is easy to generate an accurate time and users don t reset TCOC during interrupt service routine Note Under PWM mode auto load is enabled automatically ALOADO bit is selecting overflow boundary Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOR TCOR7 TCOR6 TCOR5 TCOR4 TCOR3 TCOR2 TCOR1 TCORO Read Write After reset 0 0 0 0 0 0 0 0 The equation of
127. ons gt Example Modify TCOR registers value MOV A 30H Input a number using BOMOV instruction BOMOV TCOR A INCMS BUFO Get the new TCOR value from the BUFO buffer defined by NOP programming BOMOV A BUFO BOMOV TCOR A Note The PWM can work with interrupt request SONiX TECHNOLOGY CO LTD Page 100 Preliminary Version 0 4 Ss SN8P1929 N B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 5 4 PWMO DUTY CHANGING NOTICE In PWM mode the system will compare TCOC and TCOR all the time When TCOC TCOR the PWM will output logic High when gt TCOR the PWM will output logic Low If TCOC is changed in certain period the PWM duty will change immediately If TCOR is fixed all the time the PWM waveform is also the same TCOC TCOR TCOC overflow and TCOIRQ set Y Y Y v v TCOC Value 0x00 PWMO Output 1 2 3 4 5 6 7 Period gt a Above diagram is shown the waveform with fixed TCOR In every TCOC overflow PWM output High when gt TCOR PWM output Low Note Setting PWM duty in program processing must be at the new cycle start SONiX TECHNOLOGY CO LTD Page 101 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 6 PWM1 MODE 8 6 1 OV
128. output from TC1 to PWM1OUT P5 3 The external high speed oscillator clock is 4MHz Fcpu Fosc 4 The duty of PWM is 30 256 The PWM frequency is about 1KHz The PWM clock source is from external oscillator clock TC1 rate is 4 The TC1RATE2 TC1RATE1 110 TC1R 30 MOV A 01100000B BOMOV TC1M A Set the TC1 rate to Fcpu 4 MOV 0 Set the PWM duty to 30 256 BOMOV TC1C A BOMOV TC1R A BOBSET FPWM1OUT Enable PWM 1 output to P5 3 and disable P5 3 I O function BOBSET FTC1ENB Enable TC1 timer Note The TC1R is write only register Don t process them using INCMS DECMS instructions gt Example Modify TC1R registers value MOV A 30H Input a number using BOMOV instruction BOMOV TC1R A INCMS BUFO Get the new TC1R value from the BUFO buffer defined by NOP programming BOMOV A BUFO BOMOV TC1R A The PWM can work with interrupt request SONiX TECHNOLOGY CO LTD Page 103 Preliminary Version 0 4 N SN8P1929 N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 6 4 PWM1 DUTY CHANGING NOTICE In PWM mode the system will compare TC1C and TC1R all the time When TC1C lt TC1R the PWM will output logic High when TC1C z TC1R the PWM will output logic Low If TC1C is changed in certain period the PWM duty will change immediately If TC1R is fixed all the time the PWM waveform is also the same TC1C TC1R TC1C
129. ove ADC conversion High byte to Data Buffer Move ADC conversion Low byte to Data Buffer Page 131 Preliminary Version 0 4 SONIX SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Note Please set ADC relative registers first than enable ADC function bit Example ADC Reference Voltage Changes ADC Init ADC Enable QADC Wait Q ADC Read RVS 1 ADC_RVS2 MOV XBMOV MOV XBOMOV MOV XBOMOV XBOBSET XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV MOV XBOMOV XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV MOV XBMOV XBOBTS1 JMP XBOBCLR XBOMOV BOMOV XBOMOV BOMOV 00000000B ADCM 0236 ADCKS A 00h DFM A FADCENB FDRDY QADC Wait FDRDY A ADCDH Data Buf A A ADCDL Data L Buf A A 00001101B ADCM A FDRDY B FDRDY A ADCDH Data_H_Buf A A ADCDL Data L Buf A A 00001111B ADCM A FDRDY B FDRDY A ADCDH Data_H_Buf A A ADCDL Data L Buf A SONiX TECHNOLOGY CO LTD Selection ADC Reference voltage V R R Set ADCKS 236 for ADC working clock 100K 4M X tal Set ADC as continuous mode and WRSO 0 25 Hz Enable ADC function Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word Move ADC conversion High byte to Data Buffer Move ADC conversion Lo
130. overflow and TC1IRQ set Y Y Y v v 1 Value 0 00 PWM1 Output 1 2 3 4 5 6 7 Period gt a Above diagram is shown the waveform with fixed TC1R In every TC1C overflow PWM output High when TC1C TC1R PWM output Low Note Setting PWM duty in program processing must be at the new cycle start SONiX TECHNOLOGY CO LTD Page 104 Preliminary Version 0 4 SONIN 9 LCD DRIVER There are 4 common pins and 24 segment pins in the SN8P1929 The LCD scan timing is 1 4 duty and 1 2 OR 1 3 bias structure to yield 96 dots LCD driver 91 LCDM1 REGISTER LCDM1 register initial value 000x 00 SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 089H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDM1 LCDREF1 LCDREFO LCDBNK LCDENB LCDBIAS R W R W R W R W R W R W After Reset 0 0 0 0 0 Bit 7 6 LCDREF 0 1 Selective range of resistance for LCD Bias Voltage division 00 400k resistance 01 200k resistance 10 100k resistance 11 50k resistance Bit5 LCDBNK LCD blank control bit 0 Normal display 1 All of the LCD dots off Bit3 LCDENB LCD driver enable control bit 0 Disable 1 Enable Bit2 LCDBIAS LCD Bias Selection Bit 0 LCD Bias is 1 3 B
131. prove the brown out reset DC low battery and AC slow power down conditions 2 For AC power application and enhance EFT performance the system clock is 4 2 4 1 mips and use external reset Zener diode reset circuit Voltage bias reset circuit External reset The structure can improve noise effective and get good EFT characteristic SONiX TECHNOLOGY CO LTD Page 41 Preliminary Version 0 4 N SN8P1929 D i D B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC LVD reset VDD Power yss Power is below LVD Detect Voltage and System Reset System Normal Run System Status system stop On Delay Time The LVD low voltage detector is built in Sonix 8 bit MCU to be brown out reset protection When the VDD drops and is below LVD detect voltage the LVD would be triggered and the system is reset The LVD detect level is different by each MCU The LVD voltage level is a point of voltage and not easy to cover all dead band range Using LVD to improve brown out reset is depend on application requirement and environment If the power variation is very deep violent and trigger the LVD the LVD can be the protection If the power variation can touch the LVD detect level and make system work error the LVD can t be the protection and need to other reset methods More detail LVD information is in the electrical characteristic section Watchdog reset
132. pump Regulator PGIA 16 bit ADC 4 SYSTEM CLOCK 4 1 OVERVIEW The micro controller is a dual clock system There are high speed clock and low speed clock The high speed clock is generated from the external oscillator circuit or on chip 16MHz high speed RC oscillator circuit IHRC 16MHz The low speed clock is generated from LXIN LXOUT by 32768 crystal or RC oscillator circuit Both the high speed clock and the low speed clock can be system clock Fosc The system clock in slow mode is divided by 4 to be the instruction cycle Fcpu Normal Mode High Clock Fcpu Fhosc 4 Fhosc 4M 8M crystal Fhosc 16 Fhosc IHRC Slow Mode Low Clock 4 4 2 CLOCK BLOCK DIAGRAM STPHX gn Fhosc Fhosc 4 Fhosc 4M crystal Fosc XOUT Fhosc 16 Fhosc IHRC Mmm Fosc CPUN 1 0 Flosc ee Flosc 4 HOSC High_Clk code option Fhosc External high speed clock Internal high speed RC clock Flosc External low speed clock Fosc System clock source Instruction cycle SONiX TECHNOLOGY CO LTD Page 47 Preliminary Version 0 4 SN8P1929 D D 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 4 3 OSCM REGISTER The OSCM register is an oscillator control register It controls oscillator status system mode OCAH Bit 7 Bit
133. put control bit 0 Disable AVE output Voltage 1 Enable AVE output Voltage Bit6 AVDDRENB Regulator AVDDR voltage Enable control bit 0 Disable Regulator and AVDDR Output voltage 3 8V 1 Enable Regulator and AVDDR Output voltage 3 8V Bit7 ACMENB Analog Common Mode ACM voltage Enable control bit 0 Disable Analog Common Mode and ACM Output voltage 1 2V 1 Enable Analog Common Mode and ACM Output voltage 1 2V Note1 30ms delay is necessary for output voltage stabilization after set CPRENB 1 Note2 All current consumptions from AVDDR AVE including PGIA ADC will time 2 when Charge Pump was Enabled Note3 Before Enable Charge pump Regulator Must enable Band Gap Reference 1 first Note4 Before Enable ACM voltage Enable AVDDR voltage first Note5 Before Enable PGIA and ADC Must enable Band Gap Reference BGRENBz 1 ACM 1 and AVDDR AVDDRENB Note6 CPR can work in slow mode but CPCKS AMPCKS register value must be reassigned SONiX TECHNOLOGY CO LTD Page 115 Preliminary Version 0 4 SONIN SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Bit CPRENB CPON and CPAUTO are Charge Pump working mode control bit By these three bits Charge Pump can be set as OFF Always ON or Auto mode Charge Pump Regulator PGIA ADC CPRENB CPON CPAUTO AVDDRENB
134. r power saving Example Switch slow mode to normal mode The external high speed oscillator is still running BOBCLR FCLKMD set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch back normal mode It is necessary to delay at least 20ms for external clock stable BOBCLR FSTPHX Turn on the external high speed oscillator BOMOV 2 54 If VDD 5V internal RC 32KHz typical will delay DECMS Z 0 125ms X 162 20 25ms for external clock stable JMP B BOBCLR FCLKMD Change the system back to the normal mode Example Switch normal slow mode to green mode BOBSET FCPUM1 Set CPUM1 1 Note If TO TCO timer wakeup function is disabled in the green mode only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode SONiX TECHNOLOGY CO LTD Page 56 Preliminary Version 0 4 SONIN SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC gt Example Switch normal slow mode to Green mode and enable TO wakeup function Set TO timer wakeup function BOBCLR BOBCLR BOBCLR BOBCLR BOBSET Go into green mode BOBCLR BOBSET FTOIEN FTOENB FTOIEN FTOIRQ FTOENB FCPUMO FCPUM1 To disable TO interrupt service To disable TO timer To set TO clock Fcpu 64 To set TOC initial value 74H To set TO interval
135. range VAIN 0 4 2 0 V Temperature Sensor inaccuracy Ets Inaccuracy range vs real Temp 8 Current consumption IDD_PGIA Run mode 3 8V 300 500 uA Power down current IPDN Stop mode 3 8V 0 1 uA Input offset voltage Vos 25 50 uV Bandwidth BW 100 Hz ao GR VDD 3 8V 180 200 250 PGIA Input Range Vopin VDD 3 8V 0 4 2 V PGIA Output Range Vopout 3 8V 0 4 2 V Band gap Reference Refer to ACM Band gap Reference Voltage VBG 1 18 1 23 1 28 V 2 7 Temperature Tacm 50 Operating current IBc Run mode 3 8V 50 100 uA Charge pump regulator Supply voltage VcPs Normal mode 24 5 5 V Regulator output voltage AVDDR 3 65 3 8 4 0 V Regulator output voltage AVE VAVE AVE set as 3 0V 2 9 3 0 3 3 V Analog common voltage VACM 1 18 1 23 1 28 V Regulator output current capacity 10 mA Quiescent current lai 700 1400 uA VacM driving capacity IsRc 10 uA VacM sinking capacity 5 1 mA In System Program ROM Function ISP operating temperature TisP 25 30 Note When Charge Pump enable current consumption will be time 2 of ADC PGIA CPR and Loading from AVE AVDDR SONiX TECHNOLOGY CO LTD Page 150 Preliminary Version 0 4 SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 6 PACKAGE INFORMATION 16 1 LOFP 80 PIN SONiX TECHNOLOGY CO LTD Page 151 Preliminary Version 0 4 SN8P1929
136. rove brown out reset including Zener diode reset circuit Voltage bias reset circuit and External reset IC These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead band The external reset information is described in the next section SONiX TECHNOLOGY CO LTD Page 42 Preliminary Version 0 4 SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 3 5 EXTERNAL RESET External reset pin is Schmitt Trigger structure and low level active The system is running when reset pin is high level voltage input The reset pin receives the low voltage and the system is reset The external reset operation actives in power on and normal running mode During system power up the external reset pin must be high level input or the system keeps in reset status External reset sequence is as following External reset System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from ORG 0 The external reset can reset the system during power on duration and good external reset circuit can protect the system
137. rs an overflow it will continue counting and issue a time out signal to trigger TCO interrupt to request interrupt service TCO overflow time is OxFF to 0 00 normally Under PWM mode TCO overflow is decided by PWM cycle controlled by ALOADO and TCOOUT bits The main purposes of the TCO timer is as following clock frequency INTO input pin out Buzzer output PWM output TCO Rate Fepu 2 Fcpu 256 TCOX8 Fcpu gt Fosc gt Internal P5 4 I O Circuit TCOOUT TCO Rate Fosc 1 Fosc 128 INTO Schmitter Trigger SONiX TECHNOLOGY CO LTD id Counting Counter ALOADO _y Buzzer le Reload gt TC0 2 A _ TOOR bs amp ALOADO TCOOUT Data Buffer X JR PWMOOUT Compare RWM TCOCKS TCOENB gt S Load TCOC 8 Bit Binary Up Time Out 1 Page 81 Preliminary Version 0 4 8 bit programmable up counting timer Generates interrupts at specific time intervals based on the selected External event counter Counts system events based on falling edge detection of external clock signals at the Green mode wake up function TCO can be green mode wake up timer System will be wake up by TCO time Ss SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bi
138. t 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCKS ADCKS7 ADCKS6 ADCKS5 ADCKS4 ADCKS3 ADCKS2 ADCKS1 ADCKSO R W 0 0 0 0 0 0 0 0 ADCKS 7 0 register sets the ADC working clock the suggestion ADC clock is 100K Hz Refer the following table for ADCKS 7 0 register value setting in different Fosc frequency ADC Clock Fosc 256 ADCKS 7 0 2 ADCKS 7 0 Fosc ADC Working Clock 246 4M 4M 10y2 200 236 4M 4M 20y2 100 243 4M 4M 13y2 154 231 4M 4 25 2 80K ADCKS 7 0 Fosc ADC Working Clock 236 8M 8M 20 2 200 216 8M 8 402 100K 231 8 8 25 2 160 206 8 8 50 2 80 gt Note In general application ADC working clock is 100K Hz SONiX TECHNOLOGY CO LTD Page 128 Preliminary Version 0 4 SONIN 11 5 3 ADCDL ADC Low Byte Data Register SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 098H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCDL ADCB7 ADCB6 ADCB5 ADCB4 ADCB3 ADCB2 ADCB1 ADCBO R W R R R R R R R R After Reset 0 0 0 0 0 0 0 0 11 5 4 ADCDH ADC High Byte Data Register 099H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCDH ADCB15 ADCB14 ADCB13 ADCB12 ADCB11 ADCB10 ADCB8 ADCB9 R W R R R R R R R R After Reset 0 0 0 0 0 0 0 0
139. t ADC 8 3 2 TCOM MODE REGISTER ODAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCOM TCOENB TCOrate2 TCOrate1 TCOrate0 TCOCKS ALOADO TCOOUT PWMOOUT Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 0 PWMOOUT PWM output control bit Bit 1 Bit 2 Bit 3 Bit 6 4 Bit 7 0 Disable PWM output 1 Enable PWM output PWM duty controlled by TCOOUT ALOADO bits TCOOUT TCO time out toggle signal output control bit Only valid when PWMOOUT 0 0 Disable P5 4 is I O function 1 Enable P5 4 is output TCOOUT signal ALOADO Auto reload control bit Only valid when PWMOOUT 0 0 Disable TCO auto reload function 1 Enable TCO auto reload function TCOCKS TCO clock source select bit 0 Internal clock Fcpu 1 External clock from PO 0 INTO pin TCORATE 2 0 TCO internal clock select bits 00 Fcpu 250 Fosc 128 TCOENB TCO counter control bit 0 Disable TCO timer 1 Enable TCO timer Note When TCOCKS 1 TCO became an external event counter and TCORATE is useless No more 0 0 interrupt request will be raised PO 0IRQ will be always 0 SONiX TECHNOLOGY CO LTD Page 82 Preliminary Version 0 4 Ss SN8P1929 D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 3 TC1X8 TCOX8 TCOGN FLAGS OD8H Bit 7 Bit 6 Bit 5 Bit 4
140. t Micro Controller with Charge pump Regulator PGIA 16 bit ADC INTERRUPT 6 1 OVERVIEW This MCU provides three interrupt sources including three internal interrupts TO TCO TC1 and two external interrupt INTO INT1 The external interrupt can wakeup the chip while the system is switched from power down mode to high speed normal mode Once interrupt service is executed the GIE bit in STKP register will clear to O for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next interrupts request All of the interrupt request signals are stored in INTRQ register INTEN Interrupt Enable Register INTO Trigger Em PO1IRQ gt Interrupt Vector Address 0008H INT1 Trigger 7 INTRQ Int t nterrup gt Global Interrupt Request Signal TO Time Out gt 5 Bit Enable TCO Time li 1 Latchs TC1IRQ Gating TCO Time Out GIE bit must enable during all interrupt operation 6 2 INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including one internal interrupts one external interrupts enable control bits One of the register to be set 1 is to enable the interrupt request function Once of the interrupt occur the stack is increme
141. t carry from PCL to PCH when PCL is overflow after executing addition instruction gt Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary BOADD PCL A PCL PCL ACC the PCH can t be changed JMP AOPOINT ACC 0 jump to AOPOINT JMP A1POINT ACC 1 jump to ATPOINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 jump to In following example the jump table starts at OX00FD When execute BOADD PCL A If ACC 0 or 1 the jump table points to the right address If the ACC is larger then 1 will cause error because PCH doesn t increase one automatically We can see the PCL 0 when ACC 2 but the PCH still keep in 0 The program counter PC will point to a wrong address 0x0000 and crash system operation It is important to check whether the jump table crosses over the boundary xxFFH to xx00H A good coding style is to put the jump table at the start of ROM boundary e g 0100 gt Example If jump table crosses over ROM boundary will cause errors ROM Address 0X00FD BOADD PCL A PCL PCL ACC the PCH can t be changed 0 00 JMP AOPOINT ACC 0 0X00FF JMP A1POINT 1 0 0100 JMP A2POINT 2 jump table cross boundary here 0X0101 JMP A3POINT ACC 3 SONiX TECHNOLOGY CO LTD Page 17 Preliminary Version 0 1 SN8P1929 B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC SONIX provi
142. tchdog Reset 0 0 NPD 1 External Reset 0 1 NPD 1 After power on reset external reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from NTO NPD flags of PFLAG register The following example shows the way to define the reset vector in the program memory gt Example Defining Reset Vector ORG 0 0000H JMP START Jump to user program address ORG 10H START 0010H The head of user program E User program ENDP End of program SONiX TECHNOLOGY CO LTD Page 12 Preliminary Version 0 1 Ss SN8P1929 D E A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 2 1 2 1 INTERRUPT VECTOR 0008H A 1 word vector address area is used to execute interrupt request If any interrupt service executes the program counter PC value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt Users have to define the interrupt vector The following example shows the way to define the interrupt vector in the program memory Note PUSH instructions only process 0x80 0x87 working registers and PFLAG register Users have to save and load ACC by program as interrupt occurrence gt Example Defining Interrupt Vector The interrupt service routine is following ORG 8 DATA ACCBUF DS 1 Define ACCBUF
143. te Set FDS 1 0 11 for all applications Bit6 BGRENB Band Gap Reference voltage enable control bit 0 Disable Band Gap Reference Voltage 1 Enable Band Gap Reference Voltage Notet Band Gap Reference voltage must be enable FBRGENB before following function accessing 1 Charge pump Regulator 2 PGIA function 3 16 bit ADC function 4 Low Battery Detect function 2 PGIA can t work in slow mode unless gain selection is 1x Bit7 CHPENB Chopper clock Enable control pin 0 Disable Chopper clock Chopper clock set to High 1 Enable Chopper clock Note Set CHPENB 1 for all applications SONiX TECHNOLOGY CO LTD Page 119 Preliminary Version 0 4 SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 11 4 2 AMPCKS PGIA CLOCK SELECTION 092H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AMPCKS AMPCKS1 AMPCKS1 AMPCKSO R W After Reset 0 0 0 Bit2 0 2 0 register sets the PGIA Chopper working clock The suggestion Chopper clock is 1 95K Hz 4MHz 1 74K 0 3 58MHz PGIA Clock 32 2 AMPCKS Refer to the following table for AMPCKS 2 0 register value setting in different Fosc frequency High Clock AMPCKS2 AMCKS1 50 2M 3 58M AWIHRC 3M
144. time because the clock doesn t stop in green mode The value of the wakeup time is as the following The Wakeup time z 1 Fosc 2048 sec gt high clock start up time Note The high clock start up time is depended on the VDD and oscillator type of high clock Example In power down mode sleep mode the system is waked up After the wakeup time the system goes into normal mode The wakeup time is as the following The wakeup time 1 Fosc 2048 0 512 ms Fosc 4MHz The total wakeup time 0 512 ms oscillator start up time SONiX TECHNOLOGY CO LTD Page 58 Preliminary Version 0 4 N SN8P1929 aU D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 5 3 3 P1W WAKEUP CONTROL REGISTER Under power down mode sleep mode and green mode the I O ports with wakeup function are able to wake the system up to normal mode The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port 1 is controlled by the P1W register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1W P13W P12W P11W P10W Read Write W W After reset 0 0 0 0 Bit 3 0 P10W P13W Port 1 wakeup function control bits 0 Disable P1n wakeup function 1 Enable P1n wakeup function SONiX TECHNOLOGY CO LTD Page 59 Preliminary Version 0 4 SN8P1929 A 8 Bi
145. tion CP working clock is about 13K 15K Hz in normal mode 2K Hz in slow mode External Low Clock mode Note3 The Faster of Charge pump clock AVE can load more current 4 In slow mode or Green mode Set CPCKS 0x00 for AVDDR AVE ACM can supply the max current SONiX TECHNOLOGY CO LTD Page 117 Preliminary Version 0 4 N SN8P1929 A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Example Charge Pump setting Fosc 4M X tal CPREG_Init XBOBSET FBGRENB Enable Band Gap Reference voltage MOV A 00001011b XBOMOV CPCKS A Set CPCKS as slowest clock to void VDD dropping MOV A 00011100B XBOMOV CPM A Set AVE 3 0V CP as Auto mode and Disable AVDDR AVE ACM voltage before enable Charge pump Enable XBOBSET FCPRENB Enable Charge Pump CALL Wait 200ms Delay 200ms for Charge Pump Stabilize MOV A 0000100b XBOMOV CPCKS A Set CPCKS as 15 6K for 10mA current loading CALL Wait 100ms Delay 100ms for Voltage Stabilize AVDDR Enable XBOBSET FAVDDRENB Enable AVDDR Voltage 3 8V CALL Wait 10ms Delay 10ms for AVDDR Voltage Stabilize ACM Enable XBOBSET FACMENB Enable ACM Voltage 1 2v CALL Wait_5ms Delay 5ms for ACM Voltage Stabilize AVE_Enable XBOBSET FAVENB Enable AVE Voltage 3 0V 2 4V 1 5V CALL Wait_10ms Delay 10ms for AVE Voltage Stabilize 1 The Charge pump delay 200ms 100ms c
146. tion please use external Thermister sensor In 25 V TS will be about 0 8V and if temperature rise 10C V TS will decrease about 15mV if temperature drop 10C V TS will increase about 15mV Example Temperature V TS V REF REF ADC output 15 0 815V 0 8V 16211 25 0 800V 0 8V 15625 35 0 785V 0 8V 15039 By ADC output of V TS can get temperature information and compensation the syste Note1 The V TS voltage and temperature curve of each chip might different Calibration in room temperature is necessary when application temperature sensor Note2 The typical temperature parameter of Temperature Sensor is 1 5mV C SONiX TECHNOLOGY CO LTD Page 122 Preliminary Version 0 4 N SN8P1929 aU wu B A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC Example PGIA setting Fosc 4M X tal CPREG_Init XBOBSET FBGRENB Enable Band Gap Reference voltage MOV A 00001011b XBOMOV CPCKS A Set CPCKS as slowest clock to void VDD dropping MOV A 00011100B XBOMOV Set AVE 3 0V CP as Auto mode and Disable AVDDR AVE ACM voltage before enable Charge pump Enable XBOBSET FCPRENB Enable Charge Pump CALL Wait 200ms Delay 200ms for Charge Pump Stabilize MOV A 0000100b XBOMOV CPCKS A Set CPCKS as 15 6K for 10mA current loading CALL Wait 100ms Delay 100ms for Voltage Stabilize AVDDR Enable XBOB
147. to 01 3 Confirm JP3 JUMPER connectivity to VDD 4 Connect JP1 to MPIII writer 5 Confirm J2 s connecting status J2 is required to be in SHORT 14 2 11 SN8P1929 PROGRAMMING BOARD CONNECT TO MPIII WRITER SONiX TECHNOLOGY CO LTD Page 146 Preliminary Version 0 4 bit 16 SN8P1929 r PGIA ith Charge pump Regulato Micro Controller w it 8 B EV KIT BOARD CIRCUIT NiX APPENDIX 17 AVE 9 20 2 RSUVPP VSS PS3 P52 p30 p Pt Pao SNSPINDD 80 Pin Board COME VLD v2 MI Re R Xe X M Mis Alle AVSS MM 10 1 12 Y M 1 ANDUR 17 AVE AVDDCPS 20 PI ICE 37 P5 por a 0 HEADER 18X2 2 For Target Board CON 5 3 5 60 vss ICE CONNECT ps4 53 n Psi 4 Pal pao SNSPIIDG LQFP80 LBT Circuit SW PR sw PB HEADER 4 s um Tr 10u s 20 Aves 59 SW PBE SW PBR Sh 5 SW PBE sw PB HEADER 3 HEADER 4 3 9 VLCD HEADER 2 VLCD Jumper HEADER 2 HEADER 4 HEADER 5X2 0 4 ton Vers iminary Prel Page 147 SONiX TECHNOLOGY CO LTD Ss SN8P1929 D D A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 5 ELECTRICAL CHARACTERISTIC 15 1 ABSOLUTE M
148. tput pin Voltage of 3 8V AVE Regulator output 3 0V 2 4V 1 5V for Sensor Maximum output current of 10mA ACM P Gap Voltage output of 1 2V AVDDCP LP gus Pump Voltage output connect a 10uF or higher capacitor to Al pPosiivereferenceinput 0 Negative reference input L3 A essenDCdfemlad Al1 Al2 Pose analog input channel OTP ROM programming pin VPP RST System reset input pin Schmitt trigger structure active low normal h XIN XOUT LO External High clock oscillator pins No RC mode P0 0 INTO PO 0 shared with INTO trigger pin Schmitt trigger Built in pull up resisters PO 1 INT1 shared with INT1 trigger pin Schmitt trigger Built in pull up resisters P1 3 0 P1 0 P1 3 bi direction pins wakeup pins Built in pull up resisters P2 0 P2 1 bi direction pins Built in pull up resisters Shared with ENS P5 2 0 l O bi direction pins Built in pull up resisters P5 4 3 bi direction pins Built in pull up resisters Shared with PWM i TCOUT LBTIN1 2 1 Low BatTery detect Input pins shared with P4 1 P4 2 3 0 LCD driver common port SEGO SEG23 LCD driver segment pins SONiX TECHNOLOGY CO LTD Page 9 Preliminary Version 0 1 SN8P1929 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 1 6 PIN CIRCUIT DIAGRAM
149. unction Port 0 Low level wakeup trigger and falling edge interrupt trigger Port 1 Low level wakeup trigger 1 Enable edge trigger function P0 0 Both Wakeup and interrupt trigger are controlled by POOG1 and 0060 bits 0 4 Wakeup trigger and interrupt trigger is Level change falling or rising edge Port 1 Wakeup trigger is Level change falling or rising edge Bit 4 3 POOG 1 0 Port 0 0 edge select bits 00 reserved 01 falling edge 10 rising edge 11 rising falling bi direction gt Example Setup INTO interrupt request and bi direction edge trigger MOV A 98H BOMOV PEDGE A Set INTO interrupt trigger as bi direction edge BOBSET FPOOIEN Enable INTO interrupt service BOBCLR FPOOIRQ Clear INTO interrupt request flag BOBSET FGIE Enable GIE gt Example INTO interrupt service routine ORG 8 Interrupt vector JMP INT SERVICE INT SERVICE Push routine to save ACC and PFLAG to buffers BOBTS1 FPOOIRQ Check POOIRQ JMP EXIT INT POOIRQ 0 exit interrupt vector BOBCLR FPOOIRQ Reset POOIRQ INTO interrupt service routine EXIT INT Pop routine to load ACC and PFLAG from buffers RETI Exit interrupt vector SONiX TECHNOLOGY CO LTD Page 65 Preliminary Version 0 4 N 7 SN8P1929 S S E 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 6 7 INT1 0 1 INTERRUPT OPERATION When the INT1 trigger occurs the PO1IRQ will be set to 1 no matter the
150. uzzer output TCOOUT is from TCO timer counter frequency output function By setting the TCO clock frequency the clock signal is output to P5 4 and the P5 4 general purpose function is auto disable The TCOOUT frequency is divided by 2 from TCO interval time TCOOUT frequency is 1 2 TCO frequency The TCO clock has many combinations and easily to make difference frequency The TCOOUT frequency waveform is as following TCO Overflow Clock TCOOUT Buzzer Output Clock gt Example Setup TCOOUT output from TCO to TCOOUT P5 4 The external high speed clock is 4MHz The TCOOUT frequency is 0 5KHz Because the TCOOUT signal is divided by 2 set the TCO clock to 1KHz The TCO clock source is from external oscillator clock TOC rate is Fcpu 4 The TCORATE2 TCORATE1 110 TCOC TCOR 131 MOV A 01100000B BOMOV TCOM A Set the TCO rate to Fcpu 4 MOV A 131 Set the auto reload reference value BOMOV TCOC A BOMOV TCOR A BOBSET FTCOOUT Enable TCO output to P5 4 and disable P5 4 I O function BOBSET FALOAD1 Enable TCO auto reload function BOBSET FTCOENB Enable TCO timer Note Buzzer output is enable and PWMOOUT must be 0 SONiX TECHNOLOGY CO LTD Page 87 Preliminary Version 0 4 SN8P1929 N A 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 8 3 7 TCO TIMER OPERATION SEQUENCE TCO timer operation includes timer
151. w byte to Data Buffer Don t disable ADC when change Reference Votlage Selection ADC Reference voltage internal V 1 2V 0 4V Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word Move ADC conversion High byte to Data Buffer Move ADC conversion Low byte to Data Buffer Don t disable ADC when change Reference Votlage Selection ADC as Voltage Measure Check ADC output new data or not Wait for Bit DRDY 1 Output ADC conversion word Move ADC conversion High byte to Data Buffer Move ADC conversion Low byte to Data Buffer Page 132 Preliminary Version 0 4 N 7 SN8P1929 O S 8 Bit Micro Controller with Charge pump Regulator PGIA 16 bit ADC 11 5 6 LBTM Low Battery Detect Register SN8P1929 provided two different way to measure Power Voltage One is from ADC reference voltage selection It will be more precise but take more time and a little bit complex The another way is using build in Voltage Comparator divide power voltage and connect to P4 1 bit LBTO will output the P4 2 voltage Higher or Lower than ACM 1 2V 09AH Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 LBTM P4110 LBTENB R W R W R W After Reset 0 0 0 Bito LBTENB Low Battery Detect mode control Bit 0 Disable Low Battery Detect function 1 Enable Low Battery Detect function Bit1 P4110 Port 4 1 Input LBT function

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