ML67Q5270
Contents
1. ks xioocsn O N EMemalOchpseect No XREN O N Extemalbusreadenable oH 19 XWEN N External bus write enabe O Nj EMemabusbyeseect 7 29 K6 16 ma XD15 H12 EA F10 B E e _ _ _ E fE Oo E wo o wo E Wo Wo Wo Wo Wo D FEDL67Q5270 02 LAPIS Semiconductor Co Ltd lw EE TT 7 182 13 BotDeiceSeet __ ora sso 1 Boot Device Selecta Ie PRI 1 Pimttpr Nm ML67Q5270 Descri WE Sam Oman 0002 function function Pin No Pin name Initial value c o PRO BuitinRomPono 2 D8 AFSEL PTAGSeet ARMFLASH H3 TESTE TetModeSeect Ai3 A FLASHTestPin 0 0 0 1 8V Power Supply for VDDCORE Power Supply for IO I DOETSASC TIIE D2 GNDPLL GroundforPLL EEE c4 VDDUSB B3VPowrSuplyforUSB F B2 GNDUSB JGomdfrPL d i PU PD column PU Pulled up with a built in resistor PD P2. I lt 1 1 External ROM External RAM write timing 1 txcss i 1 txcsH 4 4 XROMCSN XRAMCSN X 7 txas txas l I I I l n r I XWEN N Itxpon i i 16 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd External IO Timing ML67Q5270 core 1 62 to 1 98V Vpp to 3 6V Ta 40 to 85 C Parameter Symbol Unit XIOOCSN output setup time XIOOCSN output setup time 2 XIOOCSN output hold time XA XBSN output setup time XA XBSN output setup time 2 XA XBSN output hold time XREN pulse width XWEN pulse width XD input setup time XD input hold time XD output setup time XD output hold time XWAITON input setup time XWAITON input hold time tioas toRWIDTH tiowWIDTH tiopoFF tions 8 tos 6 tioAs 8 ttioas 8 tBuscik 6 tioAs 8 ttioas 8 tsuscLk 6 tioas 8 tsuscLk tioAs 8 tsuscLk 6 6 tionwiprH 10 tiogwiprH 10 tiowwiprH 10 tiowwiprH 10 O 5 tioas 13 tBuscik 15 20 tioas 13 tBuscik 15 Address setup time set by register RE pulse width set by register WE pulse width set by register Data of
3. Eternal bus address signal ae External bus address signal External bus address signal External bus address signal External bus address signal Ex o Ex External bus address 2008 FS Ex Ex Ex Ex Ex gt ej 4mA Ks temalbusadaresssigna 5 o extemal bus addresssignal m B B E E B E B B ES bus adress signal External bus address signal External bus address signal External bus address signaal ama External bus address signal External bus data signal External bus data signal External bus data signal External bus data signal External bus data signal Exemalbusdatasigna External bus data signal E13 xb08__ vo Extemal bus data signat or uo sematbus deta sal B13 10 External bus data signal A 005 10 B A10 10 External bus data B xpos wO Exemabusdatasgna A9 002 0 extemal busdatasignal PU Cos oom wo festa bus deta signer B9 uo External bus data signa PU M9 XROMCSN O N ROM chip select 0 Cw xm o N enema
4. FEDL67Q5270 02 ML67Q5270 1 62 1 98 Vpp IO 3 0 to 3 6 V Ta 40 to 85 Unit Serial clock cycle time D 2 lBuscLK Serial clock High Low time lBUSCLK Data delay time output tb ns Data setup time input tsp LPs 1 Data hold time input lup 30 pF ns SPInSSN SPInSCK lead time a 1 SPInSCK SPInSSN lag time tLac teusak 15 ns Slave data invalid time tois 25 ns SPI slave mode timing CPHA 0 SPInSSN B Input tLEap gt lt SPInSCK CPOL 0 Input K 5 SPInSCK twsck CPOL 1 Input tis 4 K SPInMISO LSB Output H lsp tup SPInMOSI Input LSB jj MSB n 0 1 SPI slave mode timing CPHA 1 SPInSSN Input dV ta li gap X lt SPInSCK ES CPOL 0 Input twsck twsck SPInSCK CPOL 1 Input 1 N lop SPInMISO Output LSB MSB 5 lsp tup SPInMOSI Input LSB n 0 1 21 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 Synchronous SIO Access Timing Switching between master mode and slave mode can be set for this synchronous SIO by the software register setting Serial clock polarity
5. 5 Z c i gt LO c o Initial value Description Oscillation Pin NS Oscillation Pin D1 RESETN FCIRE System Reset ES EN 252 71 2 4 yTaGRetum Clock f de Tek 24 e d 2 mms P ITAGTestmodestate mm s TD 313 NIRST 1 NyTAGTestReset Joj deuf to 2 10 General Purpose Port A12 SIO Receive Data 4mA M8 VO General Purpose Port At O SIO TransmitData Ama A12 10 General Purpose Port A10 VO 5910 Communication Clock Ama 1 10 General Purpose PortA9 SSlOReeieData 4mA T 1 0 08 WO General Purpose Port A8 SsiOTransmitData 4mA T F2 10 General Purpose Port A7 VO SPlClockforCHi 4 1 LU UE PEIUS SPI Data for CH1 05 5 4 Master Receive Slave Transmit SPI Data for CH1 PA04 General Port 4 4 Master Transmit Slave Eum Cim mr s Clock for CH0 ama i C s a SPI Data for CH0 PA01 General Purpose Port A1 I O 4mA Master Receive Slave Transmit SPI
6. SSIOCLK 155500 lt gt tsssis tsssiH lt SSIORX Serial clock Positive polarity 22 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 GPIO PA PB PC Access Timing 1 62 to 1 98 V Vpp 3 0 to 3 6 V Ta 40 to 85 Parameter Symbol Unit PAn PBm PCI input H duration n PAn PBm PCI input L duration teusaxx2 ns Note 1 12 to 0 m 11 to 0 1 11 to 0 PAn PBm and PCI input timing n 12 to 0 m 11 to 0 1 11 to 0 TGPIOIH TGPIOIL PAn PBm PCI 23 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 Clock Output Secondary Function of PB11 Pin Timing 1 62 to 1 98 V Vpp 3 0 to 3 6 V Ta 40 to 85 Parameter Symbol Unit 0 0 0 tcLKOUT tcLKOUT tcLKOUT 0 0 0 tcLKOUT tcLKOUT tcLKOUT tcrkour 1 the cycle time of the 6 MHz or 12 MHz clock generated by 2 clock sources and the frequency divide ratio Clock output secondary function of PB11 pin timing leikour H teikour L 1 1 1 1 24 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 8 bit Parallel IO Access Timing Vpp c io 3 0 to 3 6 V Ta 40 to 85 Parameter Symbol Typ Unit PLICLK cycle time ns PLICLK to PLISYNC setup time input Lewes ns PLICLK to PLISYN
7. ParallelIF ce Poor wo foenera Pupose Por cor L PD an B7 PCO6 10 General Purpose Port 606 Parallel IF Datas PD 4m UM D7 08 0 General Purpose Port 605 Paralleli IF Datas PD mA 1 A2 PCO4 10 General Purpose Port 04 PD ama 11 Coe Pom uo foenera Pupose Por cos r Pmamwpun Po ama Be 2002 10 General Purpose Portco2 1 ParalleliF PD Ama 1 6 29 FEDL67Q5270 02 ML67Q5270 LAPIS Semiconductor Co Ltd WE Sam Oman 0002 function function 2 t pco fuo 1 f DM A USB dev D bl s o fal use aevoe i roon o L H4 External bus address signal H2 Exemalbusaddesssgna 4m o Extemal bus address signat ooo y d ml xms Extemalbus address signal K Extemal bus address signal Ka 6 Exteral bus address signal 8 0 Enema bus f dL 4 Pin No Pin name Initial value gt gt v a c 6 gt LO c o T femal bus address signal e w om
8. This function can not be used during security function being activated SRAM bank x 4 Mbytes Supports 16 bit devices External I O e bank x 4 Mbytes Supports 8 bit 16 bit devices Enable to setting address setup RW WE pulse and data off timing in system clock cycle unit e Supports an access wait function by wait signal e Interrupt control FIQ resource External 1 20 IRQ resources External 3 Internal 17 7 priority levels for each source e DMA controller DMAC 2 channels Enable to allocate multiple DMA transfer request sources for each channel Channel priority fixed mode round robin mode DMA transfer mode cycle steal mode burst mode DMA request type software requests hardware requests Maximum transfer count 65 536 Data transfer size 8 bits 16 bits 32 bits Transfer request source CPU SPI Synchronous SIO Smartcard IF e GPIO 13 bits x 1 channel 12 bits x 2 channel Enable to setting input mode or output mode for each bit Enable to setting as interruption source for each bit Interruption mode level edge and positive logic negative logic e Timer 16 bit auto reload timer x 1 channel for system operation 16 bit auto reload timer x 1 channel for applications 16 bit flexible timer x 2 channel for applications Auto reload timer ART mode Compare out CMO mode Pulse width modulation PWM mode Capture CAP mode e Watch dog timer WDT 16 bit timer 8 389 s
9. 12 x 1 0025 MHz 83 33 x 83 33 x 0 55 clock H pulse width tsyscH 0 45 x tsvsc ns SYSC 0 55 x Main clock XI XO L pulse width tsyscL 0 45 x tsysc ns SYSC 1 Main system bus clock within the LSI and operating clocks of CPU etc tsyscH tsyscL XI XO tBUSCLK BUSCLK 14 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 External ROM External RAM Timing 1 62 1 98 Vpp IO 3 0 to 3 6 V 40 to 85 Parameter Symbol Min Max Unit XROMCSN XRAMCSN txcss tasetup 6 tasErup 6 output setup time txcsH tauscLk 6 6 output hold time output setup time output hold time XREN pulse width trworn 15 fmwom 15 XWEN pulse width twwori 15 twwor 15 XD input setup time 225 XD input hold time x O XD output setup time 6 output hold time deusuk O usck 6 tASETUP Address setup time set by register tewipTH RE pulse width set by register twwIDTH WE pulse width set by register tpoFF Data off wait time set by register 15 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 External ROM External RAM read timing txcss 1 XROMCSN XRAMCSN N txas i txas I l 0 A txREw
10. BSELO XDO6 13 A CORE PB01 XBSN1 TMS is XD15 XD14 GNDIO XD10 09 CND SIMVCT CORE CORE L0 K VDD PBO6 09 09 CORE EE AES OMS SSIORX BPIFD7 SL 05 PA08 N C XD11 u en GNDIO SSIOTX XD03 XDO4 10 XDO1 VDDIO XD00 2 9 PC07 PC08 Sa BPIFD5 BPIFD6 P LFBGA 144 1111 0 80 PCO5 PC06 PB11 Bottom View BPIFD3 BPIFD4 CLKO PC03 PC02 PES C 6 GND PUCTL 5 1 PA05 PA06 XA09 XA07 11 XA16 SPIOMIS 21 SPI1MIS SPIISSN XI VDDUSB VDDIO 4 7 VDD XA12 XA10 GNDIO 18 XA19 TESTE VDDPLL FIQ CORE DM GNDIO 3 GND PC04 XA13 14 Gore PR1 VDDIO N C 9 005 BPIFD2 GND PBos 09 10 GNDIO RESETN exINTO EXINT1 VBUS 1 A CORE L K J H G F E D C B PINLAYOUT BSEL1 GNDIO TCK PB00 XBSN0 SSIOCL 12 VDDIO N C RTCK PC10 PC11 PA12 FTM0 FTM1 SIORX ANE XROMCS XREN XWEN GNDIO 11 GND N core TI VDD CORE dpi a 2 VDDIO XA01 N XA04 GNDIO XA02 XA03 VDDIO XA05 XA08 XA06 N VDDIO 8 5 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 PIN LIST Description Primary function Secondary function A s gt
11. Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual The Products are not designed or manufactured to be used with any equipment device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury such as a medical instrument transportation equipment aerospace machinery nuclear reactor controller fuel controller or other safety device LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes If a Product is intended to be used for any such special purpose please contact a ROHM sales representative before purchasing If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law you will be required to obtain a license or permit under the Law Copyright 2011 LAPIS Semiconductor Co Ltd 29 29
12. mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contactROHM s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times 27 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 REVISION HISTORY Page Document No Date Previous Current Description Edition FEDL67Q5270 01 15 2010 29 29 Finmledtion1 FEDL67Q5270 02 Jul 1 2011 Applicable fingerprint sensor AES1711 is deleted 28 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 NOTICE No copying or reproduction of this document in part or in whole is permitted without the consent of LAPIS Semiconductor Co Ltd The content specified herein 15 subject to change for improvement without notice The content specified herein is for the purpose of introducing LAPIS Semiconductor s products hereinafter Products If you wish to use any such Product please be sure to refer to the specifications which can be obtained from LAPIS Semiconductor upon request Examples of application circuits circuit constants and any other information contained herein illustrate the standard usage and operations of the Products The peripheral conditions must be taken into account when designing circuits for mass production Great care
13. was taken in ensuring the accuracy of the information specified in this document However should you incur any damage arising from any inaccuracy or misprint of such information LAPIS Semiconductor shall bear no responsibility for such damage The technical information specified herein 15 intended only to show the typical functions of and examples of application circuits for the Products LAPIS Semiconductor does not grant you explicitly or implicitly any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information The Products specified in this document are intended to be used with general use electronic equipment or devices such as audio visual equipment office automation equipment communication devices electronic appliances and amusement devices The Products specified in this document are not designed to be radiation tolerant While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products a Product may fail or malfunction for a variety of reasons Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury fire or any other damage caused in the event of the failure of any Product such as derating redundancy fire control and fail safe designs LAPIS
14. C hold time input E CL 30pF 5 ns PLID data setup time input 10 ns PLID data hold time input 5 ns tPLicLk PLICLK 1 tPLISYNCH PLISYNC 1 ae 1 clock Positive polarity 2 PLISYNC Positive polarity 25 29 FEDL67Q5270 02 POWER OFF SEQUENCE Power ON sequence Core VDDCORE VDDPLL and IO VDDIO VDDUSB power should be on at the same time or IO VDDIO VDDUSB power should be on after Core VDDCORE VDDPLL on Power ON Sequence d VDDIO VDDUSB Power On 1 8 V VDDCORE VDDPLL Power OFF sequence Core VDDCORE VDDPLL and IO VDDIO VDDUSB power should be off at the same time Core VDDCORE VDDPLL power should be off after IO VDDIO VDDUSB off Power OFF Sequence Power OFF 3 3 V VDDIO VDDUSB 26 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 PACKAGE DIMENSIONS INDEX MARK INDEX MARK e T c I ce 0 50 0 10 20 1000 LAPIS Semiconductor Co Ltd ACKAGE MATERIAL QSL 39143 jtf BE CHL ROTRERT TITLE P LFBGA144 1111 0 80 2 ee NOTES 1 THE DIMENSIONS ON PACKAGE OUTLINE INCLUDES THE ATTACHED BALLS 9 Y Yoshida 2 THE BALL PITCH MEANS THE DISTANCES BETWEEN THE BALL CENTERS REVISION Tet ISSUE Notes for Mounting the Surface Mount Type Package The surface
15. Data for CHO 00 I O General Purpose Port AO I O 4mA A Transmit Slave Receive ra is pesa Clock Output for senson ama B PBO9 WO General Purpose Port 00 Exemalintemuptinput foriIRQ28 8 4 1 Ci 08 10 General Purpose Port B08 Exemalintemuptinput foriIRQ30 S 4mA 1 D3 PBO7 WO General Purpose Port 807 1 Exemalintemuptinput forFIQ 4m T HII PB06 General Purpose Port B06 Smartcard iF Clock 4mA 610 08 0 General Purpose Port B05 Smartcard IF Reset Ama 0 General Purpose Port 804 Smartcard IF Serial Data Few ponens Dit 02 10 General Purpose Port B02 Smartcard IF Voltage Control 1 ama 1 4mA E cker O 27 mms E B C12 PBO 10 General Purpose PortB01 Smartcard IF Voltage Controio 4mA B12 PB00__ WO General Purpose Port 800 Smartcard IF Card Detection 4mA WO General Purpose Port C1 VO Flexible Timer forchi PD ama MI RS M General Purpose Pon wm ae PD 4m 38 Bi 09 10 General Purpose Port C09 Parallel IF B B8 pcos 10 General Purpose Port 608
16. LAPIS FEDL67Q5270 02 SEMICONDUCTOR Issue Date Jul 2011 ML67Q5270 DFT Based Fingerprint Authentication LSI GENERAL DESCRIPTION The ML67Q5270 is a single chip LSI that executes fingerprint authentication without external memory by using the embedded fingerprint authentication accelerator This fingerprint authentication accelerator uses DFT Discrete Fourier Transform based algorithm licensed from Precise Biometrics and supports AuthenTec s slide sensors and certain touch sensors from several sensor manufacturers Besides the ML67Q5270 has the secure circuit to protect enrolled fingerprint data from unauthorized access Thus this LSI helps customers quickly design new products that offer convenient security as far as high performance fingerprint authentication low cost small size and high level of security FEATURES e Fingerprint authentication DFT Discrete Fourier Transform based algorithm licensed from Precise Biometrics This DFT based algorithm achieves a lower FTE False To Enrollment rate and a higher authentication accuracy especially when a slide sensor is used as compared to the minutiae algorithm Easy to use The fingerprint authentication is performed by the fingerprint authentication accelerator which does not ask customers for so complicated control No external memory Customer s application program and up to 45 fingerprint data can be stored in the embedded Flash memory on the ML67Q5270 No external memory is
17. ase supply from same power source to both aM pins and Vpp put pin 10 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 ELECTRICAL CHARACTERISTICS DC Characteristics DC characteristics Core IO 1 62 to 1 98 V Vpp 3 0 to 3 6 V Ta 40 to 85 Parameter Max Unit H input voltage Vu 20 10 40 3 L input voltage 0 3 08 4 Schmitt trigger Vr 0 01 14 20 input threshold voltage 5 V tolerant 06 _ H output voltage Cva tow ama L output voltage Va 4 High level input current 1 T FERME NN lin LTEM C d e el 46 3 Vin 5 5 V 3 pa Low level input current 1 E li E puree Low level input current 2 10 3 state output leakage current Puldown ow 30 w 14 30 Supply current during STOP 4 losio D 420 P n 2 s core _ fsusak 320MHz 5 Lm O Imo 5 1 Pins other than 5 V tolerant pins 2 5 V tolerant pins 3 Input ports VDD IO or 0 V Other ports No load excluding the current flowing in pull up pull down resistors 4 LSI supply current when going into LSI stop mode by stopping clock oscillation PLL operation and random number generator operation and setting USB power dow
18. can be switched When clock polarity is set to positive data is transmitted shifted out on the falling edge of the clock and 15 received shifted in on the rising edge of the clock At completion of 8 bit data transmission reception the clock stops at a high level and the last data is retained for data output When clock polarity 15 set to negative data 15 transmitted shifted out on the rising edge of the clock and 15 received shifted in on the falling edge of the clock At completion of 8 bit data transmission reception the clock stops at a low level and the last data 15 retained for data output The following waveforms show the cases where the clock polarity is positive Master mode 1 62 to 1 98 V Vpp_ 3 0 to 3 6 V Ta 40 to 85 C Parameter Unit Output data delay time 2 Input data setting time CL 30 pF 30 ns Input data retained time 98 Note 11 clock outputs for transferring 1s selectable from 2 synchronous SIO clock sources and the frequency divide ratios SSIOCLK SSIOTX SSIORX Serial clock Positive polarity Slave mode _ 1 62 to 1 98 V Vpp_ 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Condition Unit Serial clock cycle LOW 65 Output data delay time j 8 Input data setting time L2 Input data retained time 2
19. econds max when CPU operating frequency is 32 MHz Enables generation of interrupt or reset by setting e SIO UART Full duplex asynchronous mode Built in baud rate generator e SPI 2 channels of full duplex serial peripheral interfaces Operating mode master mode slave mode Data transfer size 8 bits byte 16 bits word Built in 16 byte 16 word FIFO on the transmission side and the reception side Supports DMA transfer master slave mode 2 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 e Synchronous SIO SSIO clock synchronous serial port x 1 channel Data transfer size 8 bits byte Selectable clock polarity Selectable LSB first or MSB first Operation mode master mode slave mode Supports DMAC transfer in master mode only e Smart Card interface Smartcard IF ISO UART x 1 channel Built in 16 byte FIFO Built in parity error counter in receive mode and transmit mode at automatic retransmission Supports asynchronous protocol of T 0 and T 1 according to ISO7816 and Built in error detection code generation and error detection functions by hardware Supports DMA transfer e USB2 0 full speed device Compliant with Universal Serial Bus USB 2 0 Full speed 12 Mbps x 1 port End points 5 or 6 Supports all data transfer types control transfer bulk transfer interrupt transfer isochronous transfer Built in SOP generation and CRC5 16 generation function
20. f wait time set by register 17 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 External IO read timing I txiocss I I txiocsH l XIO0CSN l txioas txioas 1 txoa 1 0 21 i txioREw i gt I I XREN XDn 1 bxiopis i txiopir n 0 15 XC i txywartis txwartiy I VVVVVVVV XWAITON 7 External IO write timing txiocss2 txiocsH XIO0CSN AC txoas2 txioas2 txoan 1 0 21 nin U VVV N VNV xBsn n 0 1 KAMA Kt i txiowew XWEN 4 5 i 1000 0 15 Pi gt txwartis XWAITON 18 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 USB Access Timing Full Speed 1 62 to 1 98 Vpp_usB 3 0 to 3 6 V 40 to 85 C Rise time 1 Te 4 20 Fall time 1 Tr CL 80p 4 20 n Output signal crossover Vors CL 50 pF 25 V DP DM voltage Average bit rate dict 12Mbps 0 25 1197 iih 1 TR and TF are transition time from 10 to 90 of 19 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 SPI Access Timing Characteristics of master mode timi
21. n mode 5 The current supplied to the LSI when fingerprint authentication is executed without USB operation under the conditions that the programs are stored in the built in Flash ROM and no external memory are connected 6 Clock pulse is driven to XI clock input pin 11 29 FEDL67Q5270 02 DC characteristics USB 1 62 to 1 98V Vpp UsB 3 0 to 3 6 40 to 85 Parameter Symbol Max Unit Absolute value of the Differential input sensitivity difference between the 02 and DM pins Differential common mode range Yow VDI rangs Includes VDI range 08 25 V Single end input threshold voltage 08 29 V W RL is connected Low level output voltage 1 5K W RL to 3 6 V V Driver output resistance Steady state 28 4 O 12 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 AC Characteristics Reset Timing 1 62 1 98 V Vpp 3 0 to 3 6 V Ta 40 to 85 C Parameter Symbol Unit Reset pulse width tsw 60 ms trstw RESETN When power on release the reset after the clock oscillation stabilization 13 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 Main Clock Timing E to 1 98 V Vpp 3 0 to 3 6 V Ta 40 to 85 Parameter Symbol Unit Main clock XI XO frequency 12 x 0 9975 NN
22. ng 1 62 to 1 98 V Vpp 3 0 to 3 6 V Ta 40 to 85 Parameter Unit Data delay time output too 2 ns Data setup time input 25 ns Data hold time input CL 30pF ns SPInSSN SPInSCK lead time O5 tsck 15 0 5 tscx 15 ns SPInSCK SPInSSN lag time O 5 tsck 15 O 5 tscx 15 ns Although actual values may become negative depending on the external load input the serial data so that the data hold time can be guaranteed 2 tSCK 1 the cycle time of the serial clock for SPI transferring which is obtained by dividing the frequency of the bus clock whose cycle time is tBUSCLK SPI master mode timing CPHA 0 SPInSSN Y Output 7 K lLEAD A lt gt SPInSCK CPOL 0 Output SPInSCK CPOL 1 Output K tsp tp 3 SPInMISO nou LSB 1 P MSB too top SPInMOSI Output LSB X MB xX n 0 1 SPI master mode timing CPHA 1 SPInSSN Output t eao tsck gt tac SPInSCK CPOL 0 Output d SPInSCK CPOL 1 Output d M tsp gt tHp SPInMISO Input LSB MSB 22 SPInMOSI top Output LSB MSB 4L f n 0 1 20 29 LAPIS Semiconductor Co Ltd Characteristics of slave mode timing Parameter
23. required when a slide sensor is used High speed authentication besides low power consumption The highly optimized fingerprint authentication accelerator achieves high speed authentication using a low speed clock Authentication lt 0 8 seconds 1 1 authentication lt 1 8 seconds 1 45 authentication Enrollment lt 2 seconds finger Applicable fingerprint sensor Slide sensor AuthenTec AES1751 128 x 8 pixels e CPU 32 bit RISC CPU ARM7TDMI S Little endian format Instruction system A high density 32 bit instruction and a 16 bit instruction of high object efficiency which is the subset of the 32 bit instruction can be executed in mixed mode General purpose register 32 bits x 31 registers Built in barrel shifter ALU and barrel shift operation can be executed by one instruction Built in debugging function JTAG interface The JTAG interface pin is shared with GPIO e Built in Memories 16 Kbyte working RAM for CPU 128 Kbyte Flash ROM for application program and fingerprint template data whose erase rewrite times are maximum 10 000 8 Kbyte Mask ROM for update of program in the Built in Flash ROM CONNECTED ARM is a registered trademark of ARM Limited ARM7TDMI ARM7TDMI S AMBA are a trademark of ARM Limited 1 29 FEDL67Q5270 02 LAPIS Semiconductor Co Ltd ML67Q5270 e External memory controller ROM Flash bank x 4 Mbytes Supports 16 bit devices Bootable from external ROM Flash
24. s Access size to data transfer FIFOs 8 bits 16 bits 32 bits e Random number generator RANDOM Generates 8 bit random numbers e 8bit Parallel I F 8 bit byte parallel port x 1 channel Receive clock 13 5 MHz max Enable level for clock edge and synchronous signal can be selected e Clock Input clock 12 MHz oscillator connected System clock CPU operating clock 32 MHz System clock is generated by PLL using 12MHz clock Output clock 6 12 MHz for fingerprint sensor e Power management Power saving mode ndividual module clock stop mode Clock operation stop can be set for each functional block HALT mode Only CPU clock 15 stopped STOP mode clocks are stopped and start stop of internal PLL and oscillator circuit are selectable e Package 144 pin LFBGA P LFBGA144 1111 0 80 3 29 LAPIS Semiconductor Co Ltd BLOCK DIAGRAM AHB Interrupt controller Clock Reset Power Saving control GPIO 3 ch 37 bits FEDL67Q5270 02 ML67Q5270 Built in ROM 8KB Working RAM 16KB Built in Flash ROM 128 KB External Memory DMA controller Controller 2ch Fingerprint Accelerator Built in FlashROM controller USB FS RAN Device DOM LSI controller Memory Management bit SIO SPI SSIO Parallel 2ch 1ch Figure 1 Block Diagram 4 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 PB04 VDD TDI NTRST VDDIO SIMDAT XD08 XDO7
25. ulled down with a built in resistor 2 This pin is used in the Built in ROM for an update function of the Built in FlashROM 8 29 FEDL67Q5270 02 LAPIS Serniconductor Co Ltd ML67Q5270 For details see the User s manual for USB firmware update function Termination of Pins Not Used 5 XREN XWRN XBSN1 XBSNO 9 29 LAPIS Semiconductor Co Ltd ABSOLUTE MAXIMUM RATINGS Parameter Digital power supply voltage CORE 1 8 V PLL power supply voltage 1 8 V Digital power supply voltage I O 3 3 V USB power supply voltage I O 3 3 V Input voltage normal buffer Input voltage 5 V tolerant Output voltage Input allowable current output allowable current L output allowable current Power dissipation Storage temperature GUARANTEED OPERATING RANGES FEDL67Q5270 02 ML67Q5270 Symbol VDD PLL Rating Unit 0 3 to 2 5 Jo 0 3 to 4 6 10to 10 pw fot pe t GND 0 V Parameter Digital power supply voltage CORE 1 PLL power supply voltage 1 Digital power supply voltage I O USB power supply voltage CPU operating frequency Ambient temperature Flash read Flash write Flash write count Unit E PLL 7 Von uss qu EE 3 ve 40 25 85 40 25 85 C m m 40 25 85 110 000 cycle Ple
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