Home

ISL94203EVKIT1Z User Guide

1. B E 2 sz i j A a 5 enden n x Sleep Delay TRANSLATE yo rien Watchdog Lem m I rin FIGURE 15194203 GUI PACK SETTINGS TAB MEMORY OPERATIONS Submit Document Feedback 19 intersil AN1952 2 December 4 2015 Application Note 1952 VOLTAGE LIMITS The upper left section of the Pack Settings tab contains the voltage thresholds and delay times see Figure 31 The voltages can be set from OV to 4 8V A negative number loads and value greater than 4 8V loads 4 8V The timer values for OV Delay UV Delay and Open Wire Sample Time can be between O and 1023 The timer value for Sleep Voltage Delay time can be between 0 and 512 Lockout a 350 Over Voltage 4 250 L0 uv m 7 000 FIGURE 31 VOLTAGE THRESHOLDS AND DELAY TIMES OV Delay i sec i Time UV Delay 1 sec Time Sleep Volt 15 sec Delay Time Open Wire 20 ms Smple Time lt lt lt lt lt Normally the OV Lockout threshold is greater than the Overvoltage threshold and the UV Lockout threshold is lower than the Undervoltage threshold The reason for this is based on the definition of the values Reaching the overvoltage and undervoltage thresholds causes the respective power FETs to turn off but the pack continues to operate normally However if the voltage of any cell reaches the UVLO or OVL
2. s2 se R w x Riwi s s rz Rw ss e Be ss Rw 27 lw Rw R wl s lt Rw PAE Rw Rw se r2 Pole Rw Fla Rw Read Write WS EEPROM EEPROM FIGURE 27 18L94203 GUI EEPROM ACCESS TAB Submit Document Feedback 16 intersil AN1952 2 December 4 2015 Application Note 1952 USER MEMORY memory The user can keep these values or load other data in the GUI boxes To write the data to the ISL94203 User EEPROM requires individual writes click the EEPROM Memory Access first or a write all using the Write User EE button this automatically sets the EEPROM Access bit The user memory area is different from the Configuration memory The User memory does not have a RAM component so all reads and writes are to the EEPROM only Also the device ships with the user memory cleared So an initial read from user memory reads 0 The User EE tab also includes a Load Default from File and a Save User Default to File These buttons load and save User EE Using the Load User Factory Default tells the GUI to put the data at addresses 50H to 57H only software revision number in the GUI locations for the user Config Mem User EE Pack Settings uc Control DEMO 52 Ba 7G 20 31 2E 33 40 used User Factory Defaut User EE Load User Default fr
3. is no longer checked and the part is not balancing during End of Charge After clicking on any of the option bits in the Pack Settings tab or on the main screen above the FET control indicators it is necessary to do a Write EEPROM either on the Pack Settings tab or the Config Mem tab Without this write operation the change only resides in the ISL94203 Configuration RAM space When repeatedly read the EEPROM memory in the configuration tab the communications lock up There was a problem with the old GUI code The best solution is to get the new Win7 8 code This new code does not have this problem Until then the best way to clear this without removing the battery from the board is to remove the 2 cable and use a jumper to momentarily connect and release the SCL line to VSS it is pulled up by a resistor This creates a clock pule Do this up to 9 times to clear the ISL94203 port Then reconnect the 2 cable AN1952 2 December 4 2015 Application Note 1952 FET Gate Drive Rise Fall Characteristics Verify basic digital logic analog interface level shifters and charge pump operation a I N LLL LL LL INL LL LLL j j _ NL dL ul TIME 100ps DIV TIME 1ms DIV FIGURE 56 DFET RISE FIGURE 57 DFET FALL AMPLITUDE V ANPLITUDE V T AMPLITUDE V AMPLITUDE V TIME 100us DIV TIME 100ps DIV FIGURE 5
4. SMD 0603 1pF 50V 10 XbR ROHS TDK C1608X5R1H105K 3 ea C1 C22 C23 SMD 0603 4700pF 100V 10 X7R ROHS VENKEL CO0603X7R101 472KNE 1 ea C27 CAP SMD 0603 1000pF 16V 10 X7R ROHS VENKEL CO603X7R160102KNE 1 ea C28 CAP SMD 0603 2 2yF 10V 10 X7R ROHS MURATA GRM188R71A225KE15D 2 ea C3 C4 CAP SMD 0603 1 0pF 10V 10 X7R ROHS AVX 0603ZC105KAT2A 2 ea C31 C32 CAP SMD 0603 2 2nF 100V 10 X7R ROHS VENKEL C0603X7R101 222KNE 3 ea D18 D20 DIODE ZENER SMD 2P SOD 123 18V 500mW ROHS DIODES INC MMSZ5248B 7 F T 8 ea D1 D8 LED SMART SMD 0603 YELLOW 1 8V 2mA 587nm 7 9mcd OSRAM LY L29K J1K2 26 Z ROHS 1 ea D21 DIODE RECTIFIER SMD SMPC 100V 10A ROHS VISHAY V10P10 M3 86A 3 ea D22 D23 025 LED SMART SMD 0603 2P RED 1 8V 2 630nm 4 5mcd OSRAM LSL29K G1J2 1 0 2 R18 Z ROHS 1 ea D26 LED SMART SMD 0603 GREEN 1 7V 2mA 570nm 3 9mcd ROHS OSRAM LGL29K G2J1 24 Z 3 ea D27 028 034 DIODE TVS BIDIRECTIONAL SMD 2P SMA 40V 400W ROHS DIODES INC SMAJAOCA 13 F 1 ea D29 DIODE DUAL SWT SMD SOT23 100V 2A 350mW ROHS DIODES INC MMBD7000HS 7 F 1 ea D30 DIODE ZENER SMD 2P SOD 123 3 3V 500mW ROHS DIODES INC BZT52C3V3 7 F 3 ea 031 033 032 DIODE ZENER SMD SOD 123 43V 410mW ROHS DIODES INC BZT52C43 7 F 1 ea D35 Diode Schottky SOD323 2 ea D36 D37 Diode Schottky SOD523 1 ea Q11 TRANSIST MOS N CHANNEL SMD DPAK 40V 9A ROHS FAIRCHILD FDD8451 4 ea
5. Balancing resumes when all cell voltages drop below 3 883V CB Max Delta specifies the maximum difference between the CELLMAX and CELLMIN values When this happens it implies that there is something wrong with the cells or connections When cell voltages exceed the CB Max Delta limits the CELLF flag is set This can cause the PSD pin to active optional which can shut down the pack The CELLF indication also starts the open wire detection operation The CB over and under temperature settings specify the temperature range over which the cell balance operates If the external temperature sensors show that the temperature is out of bounds then cell balance stops The CBON and CBOFF times specify how long the cell balance is on and off These timers are mainly used for thermal control to manage the heat dissipated by the cell balance resistors TEMPERATURE LIMITS On the lower right of the Pack Settings tab are the pack temperature limit settings There are temperature limits for charge and discharge as well as temperature recovery levels for each These limits refer to the ADC converted value of the temperature sensor inputs so they are affected by the TGAIN bit The GUI limits values in these locations from 0 to 1 8V voltage setting or 40 C to 125 C temperature setting Charge Over Terp 0 530 V Charge OT Recover 0 590 V Charge UT Recover 1 190 V Charge Under Temp 1 344 V Discharge Over Temp 0 530 V Discharge
6. STATUS BITS The status indicators on the lower right of the GUI screen see Figure 12 reflect the status of the bits in the device If an indicator is red it shows a fault or out of bounds condition If an indicator is green it is showing an operating condition such as current direction or power mode The status indicators are automatically updated when doing a voltage read operation However refreshing only the status bits is much quicker So clicking the Read Status bits updates only the status CHING C OvLO C DOT C DCHING C ov DUT O C EOCHG C COT C uv C LVCHG C IOT UvLO C LD PRSNT Q 2 CBOV C CBUT CBUV C IDLE ene CO CELLF C DOZE SUUS VIS OPEN SLEEP FIGURE 12 STATUS INDICATORS FET INDICATORS Above the voltage readings are the FET indicators see Figure 13 These show the status of the PCFET CFET and DFET control bits If the bit is 1 indicating that the FET should be on the indicator is green If the bit is O indicating that the FET should be off then the indicator is red Submit Document Feedback 9 intersil PCFET CFET on DFET on E Enable during OV during UV FIGURE 13 FET INDICATORS The FET indicators are more than just readouts Clicking on the indicators can also set or clear the bits to turn on or turn off the FETs However the GUI does not have control over the FETs when the device is operating in stand al
7. intersil Application Note 1952 ISL94203EVKIT1Z Evaluation Kit User Guide ISL94203EVKIT1Z is a kit that facilitates testing of the ISL94203 Li ion battery pack monitor and control ICs The ISL94203 monitors cell voltage current and temperature It converts the cell voltages pack current and temperatures to 12 bit digital values provides cell balance control and provides complete stand alone battery pack operation The ISL94203 default stand alone operation can be overridden by an external microcontroller The PC graphical user interface GUI supports the hooks needed to monitor stand alone operation and to demonstrate operation with an external microcontroller Specifications This board has been configured and optimized for the following operating conditions Configurable to 3 to 8 cells default 3 cells Standard cell voltage range 2 699V to 4 250V OV UV delay times 1 and 4 seconds respectively CB max delta voltage 0 501 e CB max min voltage 4 032V and 3 100V NOTE Consult programming options for full listing of programmable parameters and ranges z poppe iw 15 3 SI B PEREL sigs eS 3 TT m T m I E0268 196 ME NETTEN aco ner E ays s EE sit e Key Features Status LEDs monitor EOC SD and PSD conditions Jumper configuration single or split path applications Wakeup push
8. December 4 2015 Application Note 1952 MICROCONTROLLER DOES The next set of controls Figure 43 allows the GUI or microcontroller to take over several functions of the device The most general is the uC Does Scan box When checked the device stops scanning the cells which effectively stops automatic operation When this box is checked cell voltages are scanned by the external uC OV and UV voltages must be manually compared with limits and cell balance must be controlled externally The only function maintained internally during a UCSCAN operation is the overcurrent short circuit monitoring These continue to be automatically monitored uc Does Scan uc Controls FETs uC Does Charge Mon Charge Mon Enable CLR Charge error Does Load Mon Load Mon Enable CLR Load Error Pack Shut Down Open Wire PSD Pin Start FIGURE 43 uC Controls FETs operation gives the GUI or external uC control over the FETs With this box unchecked the ISL94203 has exclusive control over the FETs It is not possible to change the FETs from the outside When the box is checked the FETs are only controlled by the GUI or an external uC The uC Does Charge Mon bit overrides the internal charger monitor function When overridden the GUI or an external uC can turn on the charger monitor current and detection hardware by setting the Charge Mon Enable The GUI or external uC then needs to mo
9. voltages and the status bits Between presses of this button the device continues to scan the voltage current and temperature values at the rate of 32ms or 256ms if in IDLE mode or 512ms if in DOZE mode Rate Logagin 1 ER ss Read Voltages Single Auto Scan START FIGURE 6 Pressing the Auto Scan START button starts a repetitive update of the values The rate of update is set by the Rate sec dropdown box As shown the GUI updates the voltages and status every 1 second Autoscan is stopped by pressing the autoscan STOP button While the autoscan is operating all other memory accesses are prohibited To read the pack settings or change a register value first stop the automatic scan To log the data press Logging START prior to clicking on the Auto Scan START button The data will be stored as a text document in a file location specified by the user When all data has been captured stop the auto scan and stop logging AN1952 2 December 4 2015 Application Note 1952 TEMPERATURE READINGS To the right of the pack voltage values are the temperature readings see Figure 7 In the default state these boxes report the voltage on the temperature inputs There are two boxes for each temperature Temperature Volts 0 553 25 3 degC Vadc Input xT1 0 957 0 478 v xT2 0 947 0 474 v FIGURE 7 TEMPERATURE READINGS The internal temperature reading at the t
10. 012 013 015 TRANSISTOR DUAL NPN SMD SOT363 40V 200mA ROHS DIODES INC MMDT3904 7 F Q16 5 ea Q1 Q5 TRANSISTOR MOS N CHANNEL SMD SOT23 60V 280mA ROHS FAIRCHILD NDS7002A 3 ea Q6 Q8 TRANSISTOR P CHANNEL SMD SOT23 60V 180mA ROHS FAIRCHILD NDSO605 2 ea Q9 Q10 TRANSISTOR MOS N CHANNEL SMD D2PAK 40V 75A ROHS NXP 101 004 SEMICONDUCTOR 12 ea R18 R25 R49 RES SMD 0402 1k 1 16W 1 TF ROHS VENKEL CRO402 16W 102JT R50 R52 R53 8 ea R1 R8 RES SMD 0603 330k 1 10W 196 TF ROHS YAGEO RCO603FR 07330KL 8 ea R26 R33 RES SMD 2512 1000 1W 196 TF ROHS VISHAY DALE CRCW2512100RFKEG 10 ea R40 R48 R63 RES SMD 0603 1k 1 10W 1 TF ROHS PANASONIC ERJ 3EKF1001V 1 ea R34 R39 RES SMD 0603 1000 1 10W 196 TF ROHS VENKEL CRO603 10W 1000FT 1 ea R54 RES SMD 2512 200 1W 5 TF ROHS VENKEL CR2512 1W 201JT 5 ea R55 R57 R64 RES SMD 0603 1M 1 10W 1 TF ROHS PANASONIC ERJ SEKF1004V R65 2 ea R58 R59 RES SMD 2512 0020 1W 196 TF ROHS PANASONIC ERJ M1WTF2MOU 2 ea R61 R62 RES SMD 0402 22k 1 16W 196 TF ROHS VENKEL CRO402 16W 223JT 2 ea R66 R67 RES SMD 0603 4990 1 10W 196 TF ROHS VENKEL CRO603 10W 4990FT 2 ea R68 R69 RES SMD 0402 4 7k 1 16W 1 TF ROHS VENKEL CRO402 16W 4701FT 5 ea R70 R74 RES SMD 0402 49 9k 1 16W 1 TF ROHS PANASONIC ERJ 2RKF4992 Submit Document Feedback 27 intersil AN1952 2 December 4 2015 Application
11. 54mm ROHS BERG FCI 68000 236HLF 4 ea 1Path 2Path CONN HEADER 1x2 BRKAWY 1X36 2 54mm ROHS BERG FCI 68000 236HLF XTH1 xTH2a 3 ea ADDR J7 J9 CONN HEADER 1x3 BREAKAWY 1X36 2 54mm ROHS BERG FCI 68000 236HLF 1 ea J5 CONN HEADER 1X8 BRKAWY 1X36 2 54mm ROHS BERG FCI 68000 236HLF 1 ea J2 CONN HDR 1x9 BRKAWY 1X36 2 54mm ST ROHS BERG FCI 68000 236 1 ea CS1 CS2 CONN HEADER 1X2 BRKAWY 1X64 2 54mm 0 195x0 118 ROHS MILL MAX 800 10 064 10 001000 1 ea CHMON LDMON CONN HEADER 1X5 BRKAWY 1X64 2 54mm 0 195x0 118 ROHS MILL MAX 800 10 064 10 001000 PCFET CFET DFET 1 ea VB VCO VC8 CONN HDR 1X10 BRKAWY 1X64 2 54mm 0 195x0 118 ROHS MILL MAX 800 10 064 10 001000 DO NOT POPULATE O ea C24 CAP SMD 1206 ROHS O ea R60 RES SMD 0805 68mQ ROHS 0 ea 11 710 111 DO NOT POPULATE 0 ea TP1 TP9 10 DO NOT POPULATE O ea CB1 CB8 CONN HEADER 1X1 BRKAWY 1X64 2 54mm 0 195x0 118 ROHS MILL MAX 800 10 064 10 001000 0 ea SCL SDA CONN HEADER 1X3 BRKAWY 1X64 2 54mm 0 195x0 118 ROHS MILL MAX 800 10 064 10 001000 VREF xT1 xT2 0 ea FETSOFF PSD INT CONN HEADER 1X6 BRKAWY 1X64 2 54mm 0 195x0 118 ROHS MILL MAX 800 10 064 10 001000 SD EOC RGO Submit Document Feedback 28 intersil AN1952 2 December 4 2015 Application Note 1952 FIGURE 50 TOP LAYER FIGURE 52 MIDDLE LAYER 2 Hardware Overview The hardware design follows recommendations in the datasheet
12. Note 1952 Bi II of Materials Continued REFERENCE QTY UNIT DESIGNATOR DESCRIPTION MANUFACTURER MANUFACTURER PART 1 ea R75 RES SMD 0603 120k 1 10W 1 TF ROHS VISHAY DALE 0603120 1 ea R76 RES SMD 0603 00 1 10W TF ROHS VENKEL 0603 10 000 1 ea R77 RES SMD 0402 00 1 16W 5 TF ROHS VENKEL CRO402 16W 00T 4 ea R78 R79 R81 RES SMD 0402 2 49k 1 16W 1 TF ROHS PANASONIC ERJ 2RKF2491V R82 2 ea R83 R87 RES SMD 0603 3 3M 1 10W 1 TF ROHS PANASONIC ERJ 3EKF3304V 1 ea R84 RES SMD 0603 550k 1 10W 1 TF ROHS VENKEL CRO603 10W 5503FT 11 ea R9 R17 R85 R86 RES SMD 0402 10k 1 16W 1 TF ROHS PANASONIC ERJ 2RKF1002X 2 ea S1 S2 SWITCH TACTILE PUSH TH 8X8mm SPST 12V 50mA ROHS OMRON B3WN 6002 3 ea Th1 TH2a TH2b THERMISTOR SMD 0603 10k 1 10W 5 PANASONIC ERT J1VG103JA B VALUE 3375 3345K ROHS 1 ea U1 IC MULTI CELL LI ION MONITOR 48P QFN 6X6 ROHS INTERSIL ISL94203IRTZ 1 ea U2 IC TVS ESD PROTECTOR SMD 6P SOT 23 6L 3pF 6V ROHS ST USBLC6 2SC6 MICROELECTRONICS 1 ea PWB PCB ISL94203EVKIT1Z REVD ROHS CONNECTORS HEADERS 1 ea J13 CONN HEADER 4PIN 2 54mm RIGHT ANGLE ROHS MOLEX 22 05 2041 1 ea J3 CONN HEADER 1X9 FLAT BRK AWAY 2 54mm R A ROHS MOLEX 22 28 8091 1 ea TP11 CONN HEADER 1x1 BREAKAWAY 1X36 2
13. OT Recover 0 590 V Discharge UT Recover 1 190 V Discharge Under Temp 1 344 V Internal Over Trnp 0 719 V Internal OT Recover 682 V FIGURE 36 PACK TEMPERATURE LIMIT SETTINGS AN1952 2 December 4 2015 Application Note 1952 When the TGAIN bit changes from to 1 or 1 to 0 the GUI rewrites the values of the temperature limits in the EEPROM tab based on the temperature input amplifier gain and sends these new values to the ISL94203 The GUI also updates the Pack Settings Information The Pack Settings tab temperature limits do not change if they are shown in C but the value in the device does change This is because the calculations for the temperature settings in C includes the setting of the TGAIN bit PACK OPTIONS In the lower left of the Pack Setting tab are various option controls see Figure 37 xT2 Monitors FET Temp Enable CELLF PSD action Enable Open Wire PSD Enable UVLO Power Down Disable Open Wire Scan Cascade two 15194203 FIGURE 37 OPTION CONTROLS Setting the xT2 Monitors FET Temp to 1 tells the device to treat the xT2 input as a FET temperature not a cell temperature With this bit set an over temperature on the xT2 input does not stop cell balancing it only turns off the power FET The Enable CELLF PSD action when set to 1 causes the PSD bit to be set when the device detects a condition that sets the CELLF bit The Enab
14. activate the cell balance outputs see Figure 44 LIC Does Cell Bal CBS CB CBG CB CB4 CB3 CB2 CBI Cell Balance On M IM IM IM IM I FIGURE 44 CELL BALANCE However before the balancing outputs turn on all other conditions for balancing must be met There can be no error conditions and if balancing is selected during charge then there must be a charge current before the cell balance outputs turn on During a controlled cell balance operation the and CBOFF timers are not used Once the uC Does Cell is set the Watchdog timer starts and communications must happen within the watchdog time out period If there is an interruption in the communications then the UCCBAL bit is reset and the device waits for a valid communication When a valid communication is received the device resumes normal default operation The indicators to the left of the control boxes indicates which cells are to be balanced If proper balancing conditions are not met the indicators are off If the cells should be balancing the indicators are on If the LEDs on the board are not on at the same time as the indicators in the GUI then there could be a hardware problem When clicking the Read Control Registers button Figure 45 the status of all of the override bits are updated Read Control Registers FIGURE 45 DEMO Tab The last tab in the GUI offers some demonstration
15. and VCO VC8 inputs Trace inductance and capacitance can easily affect circuit performance Vias in the signal lines add inductance at high frequency and should be avoided Match channel to channel analog 1 0 trace lengths and layout symmetry This is especially true for the CS1 and CS2 lines since their inputs are normally very low voltage Maximize use of AC decoupled PCB layers All signal 1 0 lines should be routed over continuous ground planes i e no split planes or PCB gaps under these lines Avoid vias in the signal 1 0 lines When testing use good quality connectors and cables matching cable types and keeping cable lengths to a minimum AN1952 2 December 4 2015 Application Note 1952 IX FT 24 256 palat On TO PC USB PORT ISL94203EVKIT1Z BOARD gp A a dum 3 k E 9 3 in WAKEUP 85 Nopo CONTROL LEM i CHARGE DISCHARGE 27 7 1 PATH OR 2 PATH SETS TO 1 PATH OR c MI INT 2 PATH E MCB PS Z BOARD aE vB 5 Q E CN FETSOFF EE MANUAL k 2 E p CONTROL B m intersii afm a ISL94203EVKIT1Z u I i em El a e i f 6V 38V a p EF ee r E Bd 4 c PORT M TO USB I2C El th BOARD Pam i CELL BALANCE a LEDs mm SET xT2 THERMISTOR TO FET OR TO CELL SET
16. coded as shown in the datasheet and are grouped by function The EEPROM tab has three other buttons The first is a Load Factory Default button This fills the GUI EEPROM locations with the factory default values as defined at the time of the GUI release This lets a user recover to a known good operating point Again use of this button simply fills the GUI registers To change the operation of the device or the contents of the EEPROM requires a separate write for each memory location The other two buttons are Save User Default to File and Load User Default from File These commands allow the user Configuration Memory to be saved and recalled The values saved are locations OH through 4BH uC Control Thermistor DEMO Configuration Memory m ho o B mm Po n3 un n3 Ch 4 gt n fo ra e o 4 C JU l z 9 o gt e 9 S e e S o a e x a s 3 a m i E rl oj J Tl ca s s s s s s s s s s s s s s s s 2 m mi gt gt mimi mio Load Factory Default Read Configuration Load Default fram File RAM Save Default to File d RAM EE RAM EE Rw 20 3 1
17. jequieoeg C CS6TNV 9 1ueuinooq HiSsz Tuss ISL94203EVKIT1Z Hardware Design R60 C24 R63 TENEO VBATT Note 68 4 7uF 50V a WakeUp Maximum continuous charge current 2 5A on Maximum continuous discharge current 20A 2 R84 549k Over charge current 8A 1s Over discharge current 30A 500ms Short circuit current 75A 200us J1 VBATT CON1 12 9 Test points J3 9 Battery Connect Notes Add a 3 3M resistor or higher from LDMON to GND and CHG to DSCG to allow sleep mode in 2Path configuration Add a 2 2nF cap from SD EOC to GND Prevent spike when the pin goes high Add 1 schottky diode to VDD to get better accuracy in single power path conection Zener diodes on cell balance circuits removed They were not needed Add FETs to I2C inputs to prevent powering ISL94203 through the uC Remove cell to cell caps and increase cell to gnd caps Replace power FETs to increase max voltage Added resistors in current sense circuit for test purposes Change resistor values for R83 R84 to reduce current 200 1W 9 D31 Q 021 10 10 19 CS1 CS2 IRF1010 60V 75A a csi Split Path 43V 1 Single Path D27 52 Single Path Q10 TVS BIDIR IRF1010 60V 75A Path2 GND pon ADD for lower drop in VDD when Q9 is off 002
18. of the precharge FET When the cell voltages are below the Low V charge level the precharge FET is on When the cell voltages are greater than the Low V charge level then the charge FET is on Submit Document Feedback 20 imtersir CURRENT LIMITS To the right of the voltage settings are the current limits for discharge overcurrent charge overcurrent and discharge short circuit events see Figure 32 The delay time values can be 0 to 1023 microseconds milliseconds seconds or minutes Care should be taken when setting the range of these timers The threshold levels are set by drop down boxes and set the overcurrent level by setting the voltage expected across the sense resistor Discharge 32mV DOC Delay Charge Delay 160 ms Discharge SC 128 DSC Delay 200 lus Charge Detect Pulse width ims Load Detect Pulse width ims FIGURE 32 CURRENT LIMITS Also in this selection is the setting for the duration of the charge and load pulse widths When the power FETs turn off in response to an overcurrent event the ISL94203 starts looking for the release of the load or charger It does this by periodically sourcing or sinking a current to the load or from the charger The duration of the pulse width might need to be changed depending on the load or charger capacitance since the detection circuit is attempting to pull the voltage at the terminals
19. specified and the Sample Voltages button is pressed This brings up a dialog box asking for the file name for the data to be stored The GUI then captures the specified number of samples and stores the data to the file This is a tab delimited file that can be imported into Excel Between the Sample All Voltages and Sample Single Voltage buttons is a progress indicator showing the ongoing data capture Config Mem RAM User Pack Settings uc Control Thermistor DEMO Power Control m L Power n Idle Doze Sleep n None Sample All I Voltages or Current Gain R w Sample Single Select Monitor 14 bit HEX Monitor Voltage R w 0 sl 50 uC Does Scan uC Controls FETs uC Does Charge Mon CLR Charge error uC Does Load Mon CLR Load Error Charge Mon Enable Load Mon Enable uC Does Cell Bal CBs CB7 CB6 CB5 CB4 CB3 CB2 CB1 Cell Balance On Read Control Registers o o o oo m m m m m i FIGURE 39 15194203 GUI CONTROL TAB Cumentcan EE ARW Down Monitor Voltage w 0 o FIGURE 41 Pack Shut Down Open Wire PSD Pin Start Power C Idle C Doze C Sleep C None FIGURE 40 Submit Document Feedback 23 intersil Sample All Voltages Abort Sample Single Select Monitor Voltage Voltage at left Number of samples 50 RES FIGURE 42 14 bit HEX AN1952 2
20. values are returned from the ISL94203 registers To properly implement this operation the GUI stops the internal voltage scan of the 15194203 using the uCSCAN bit It then reads the cell voltages and CELLMAX and CELLMIN values and restarts the automatic scan of the device The values are read asynchronously so without stopping the scan there is not sufficient time to read all the values prior to the next internal scan For this reason the CELLMIN and CELLMAX values are often reported from a different scan than the rest of the cell voltages Also during the scan the cell balance operation is stopped This is so the cell balance currents do not cause false readings of the cell voltages due to external voltage drops Voltage CELLS CELL7 CELLS CELLS CELLA CELL3 5 519 3 652 3 573 3 661 3 474 3 742 CELL 3 603 736 3742 3 474 ze c c C C lt cC lt CELL1 x lt LH m li CellMin eurn 1 8 29 060 wu VRGO 2 494 w To the right of the cell voltages there is a graphic indication of the capacity of the cell This is based on the voltage of the cell In this graphic depiction the scale shows no bar when the voltage is less than or equal to the undervoltage threshold It shows 100 or maximum when the cell voltage is equal to or greater than the overvoltage threshold See the overvoltage and undervoltage thresholds in the Pack settings ta
21. 00x This addresses the device having the ADDR pin pulled low In a cascade configuration or an application that does not need current sense or FET control where the ADDR pin is tied high write the I2C Addr as 52 I2C Addr 50 FIGURE 14 2 ADDRESS AN1952 2 December 4 2015 Application Note 1952 Temperature measurement options are selected in this box Figure 15 below the tabs The pack settings and temperature outputs can be shown as either volts or C Changing the setting initiates a voltage scan and an update of the Pack Settings The calculations are made in the GUI as described in previous The device simply maintains the voltage value associated with the temperature Temp reading in degC TGain Gain now is 2x FIGURE 15 TEMPERATURE MEASUREMENT OPTIONS This box also has the selection for the TGAIN bit Clicking on the TGAIN box changes the TGAIN bit in the device updates all of the RAM settings for temperature limits and initiates an update of the Pack Settings tab It does not do a voltage scan The caption shows the current status of the temperature gain Figure 15 indicates that the temperature gain is set to 2x Access to EEPROM requires an access control bit to be set prior to a read or write operation In all of the screens where a button initiates multiple read or write operations the memory access is automatically set to the correct access code and automatically reverts to RAM acc
22. 1W Improves accuracy Split Path 5 240 R59 002 1W x x 2 a m ol 96 a 2 NDS0605 Added iue resistors to LDMON x R18 test effect LDMON mm R26 on current s lt Di 100 1W aem 5 LED s s lt 2 2 07 NDS0605 TUM D2 100 1W LED 08 50605 R28 100 1W R38 100 R29 EM o 2 m 100 1W 27 FETSOFF NDS7002A R30 100 1W 49 9k n R31 100 1W FETSOFF powering IC from I2C ADD to prevent NDS7002A 4700pF 50V R32 100 1W MBT3904DW1 MBT3904DW1 MBT3904DW1 MBT3904DW1 a j d Th2b is physically A located under TP9 10 11 1 es GND GND GND GND a Note R33 100 1W ADD to reduce switching spikes xT2 select XH103F INTERSIL LOGO NDS7002A ROHS ROHS ROHS FIGURE 49 ISL94203EVKIT1Z HARDWARE DESIGN 96 910N Application Note 1952 Bill of Materials REFERENCE QTY UNIT DESIGNATOR DESCRIPTION MANUFACTURER MANUFACTURER PART 9 ea C13 C21 CAP SMD 0603 47nF 100V 10 X7R ROHS VENKEL CO603X7R101 473KNE 3 ea C2 25 26
23. 8 CFET RISE FIGURE 59 CFET FALL Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that the document is current before proceeding For information regarding Intersil Corporation and its products see www intersil com Submit Document Feedback 33 intersil AN1952 2 December 4 2015
24. F INPUT BUFFER LEVEL SHIFTER OPEN WIRE DETECT uv CB STATE MACHINE SCAN STATE MACHINE 143 BIT TEMP b wvE 16 RG 2 FIGURE 22 AN1952 2 December 4 2015 Application Note 1952 MAIN AD FORM TOOLS About Advanced Trace Options RSVD ISL94203 Block Diagram Measurement Screen Active Measurement Source Total Reedings ADC FOF ADC input VBAT Go Stop Grephing Options 07426 V Div 27 99834 V midscale a Reset Peaks 1 0 EXE Reset Scalo ee gt Gy ee ee ee AutoRange DEO HE cuc CONES alos ae pk to pk 0 06329 me Instant 28 00889 1 3 Max V 2804405 Senstviy 14 Min V 27 98076 Cantor 1 5 ISL94203 Internal Mux Selecton 1 8 Total Loop Time mSec pr 76 Interest Temp XTemp XTernmpl Reg 0x85 AD Control vRGO VBAT Current r Current Gain 4 1 7 veo Omm 50 C 5 1 9 500 500 CELL1 CELL2 CELL 3 CELL 4 CELL 5 CELL6 CELL CELL 8 Save Measurements to File CAUsersVPubhic5L94203 HIDABattery Voltage td 1000 Measurernent sets written 08 11 2014 12 13 47 ser Comment 5194202 AD Data FIGURE 23 Actual Dual Byte Hex value of AD reading 20 Checking will append latest collection of readings to a file Calculated value based on channel selected 21 Browse to directory location where captured readings will be Active channel being measured s
25. GURE 46 15194203 GUI DEMO TAB CURRENT DIRECTION DEMO The Force Charge Indicator or Force Discharge Indicator controls force the device to indicate a charge or discharge condition see Figure 47 This is not a real condition for example the current readout shows no current flow However the device responds as if there is a current Current Direction C Force Charge Indicator C Force Discharge Indicator Un Force Current Direction Indicator FIGURE 47 While in either of these demo modes the device will not respond to real overcurrent or short circuit conditions To clear the conditions click on the Un force Current Direction Indicator button OVERCURRENT DEMO To simulate any of the overcurrent or short circuit conditions use the Over Current Fault demo options see Figure 48 The Force Charge Over Current Condition sets the COC bit and the device responds as if that condition exists In order to better view the operation the GUI sets the uUCLMON and p CCMON bits so the recovery conditions are controlled manually Without the uCCMON and pu CLMON bits set the device will do the following The test bit indicates to the device that there is an overcurrent condition The device sees that there is no current so starts the LDMON or CHMON operation Submit Document Feedback 25 gmtersil The device sees that there is no load and no charger so it clears the fault condition The device im
26. However this section provides some additional guidelines and explanations Jumpers There are three user selectable options on the ISL94203EVKIT1Z board Submit Document Feedback 29 FIGURE 51 MIDDLE LAYER 1 HIN MEM 2 P 3 T FIGURE 53 BOTTOM LAYER ADDR This jumper selects the 2 address Normally this jumper connects to the O position With the jumper set to the 1 position the GUI I C address value must be changed to 52 X12 SELECT There are three external thermistors on the board There are two near the battery connectors These can be used to monitor the battery cells connect external thermistors to connectors xTh1 or AN1952 2 December 4 2015 Application Note 1952 xTH2a and remove the on board thermistors 1 Th2a There is a third resistor located under the discharge power FET The xT2Select jumper allows the ISL94203 to monitor either the Th2a thermistor near the battery terminals CELL position or the Th2b thermistor under the power FET FET position When monitoring the FET thermistor you might want to check the xT2 Monitors FET box in the GUI see Pack Options on page 22 POWER FET CONFIGURATION The board allows for both a single charge discharge path and separate charge discharge path Configuring the options requires two jumpers For a single path connect a shunt on th
27. I2C ADDR FIGURE 2 ISL94203EVKIT1Z BOARD SETUP Submit Document Feedback 3 intersil AN1952 2 December 4 2015 Application Note 1952 Quick GUI Setup Guide Step 1 Once the board is powered up and connected to the PC through the USB cable start the GUI program Then click on the dropdown box Intersil 519 203 Evaluation Software Main Startup Menu x intersil Connect Intersil Evaluation kit as shown Q APPLY 28V to PS Z Board Then Press Wake Up Control lt Select Option when Ready EI JI ISL94203 Ready Proceed to angan Demo I2C PORT E Be semasa im ESE TO PC USB PORT dm FW SEO E TO EVAL BOARD ISL94203INTFACEKIT1Z Me epp ot 1 SETS 1 Fa DISCHARGE PATH EY WAKE UP SETS CHMON MC3 PS Z BOARD CONTROL i TO 1 PATH ie all FETSOFF 2 5 PIS sm LET MANUAL CONTROL m f gt i coo co a aL T mos Bons ia s d UAI 3 v Kas dE d LE a oN EE ee 3 2 PORT zu eV TO 38V zm B EPA mcd it ot zu TO USE i USB I2C BOARD n lt m c SET XT2 THERMIST R o FET TO CELL SET 2 ADDR FIGURE 3 MAIN GUI START UP WINDOW Submit Document Feedback 4 intersil AN1952 2 December 4 2015 Appli
28. LS 10000011 3 Cells connected C1 C2 C8 11000011 4 Cells connected C1 C2 C7 C8 11000111 5 Cells connected C1 C2 C3 C7 C8 11100111 6 Cells connected C1 C2 C3 C6 C7 C8 11101111 7 Cells connected C1 C2 C3 C4 C6 C7 C8 11111111 8 Cells connected All cells connected NOTE Only these combinations are acceptable Any other combination will prevent any FET from turning on CELL BALANCE LIMITS The next box to the right Figure 35 contains the settings for cell balancing The voltage limits that can be set in the GUI are fixed at O and 4 8V There are no limits to the temperature settings The temperature values are limited by the GUI from 0 to 1 8V voltage setting or 40 C to 125 C temperature setting Submit Document Feedback 21 imtersir CB Upper Lim 4 032 CB Lower Lim 3 100 CE Max Delta 0 501 CB Min Delta CB Over Temp 0 530 CB Recover 0 590 CB UT Recover 1 190 CB Under Temp 1 344 CB Off Time 2 sec T FIGURE 35 NUMBER OF CELLS BOX lt c c lt c lt The CB lower limit and CB upper limit define the boundaries of the cell voltage operation except in EOC balancing If ALL cell voltages exceed the limits then balancing stops Balancing starts again when ALL cell voltages drop back within the specified limits plus a hysteresis For example if the CB upper limit is set to 4 0V then balancing stops when all cell voltages exceed 4 0
29. O thresholds then something is very wrong with the pack or the charger Reaching the OVLO threshold causes the device to set a pack shutdown PSD bit This can be used to blow a fuse to disable the pack Reaching the UVLO threshold indicates that one or more cells are much below their lower limit so the device powers down to remove as much load as possible from the cells The End of Charge threshold is usually lower than the overvoltage threshold When a cell reaches the overvoltage threshold the end of charge output EOC pin can turn off the charger If the voltage continues to rise then there is something wrong with the charger so the overvoltage indication turns off the charger current from within the pack Alternatively the EOC limit can be used for cell balancing to specify a level where balancing is to begin In this case when any cell reaches the End of Charge threshold all cells that are higher than CELLMIN CB MIN Delta start to balance Balancing continues until all cells are below the EOC Threshold 117mvV The Sleep voltage along with the sleep voltage timer determine if the cells drop below a sleep threshold If so the power FETs turn off and the device enters a sleep mode The device wakes from a sleep mode by the connection of a load or a charger to the pack The Low V Charge threshold is used when the Precharge FET is enabled The low voltage charge threshold is the level where the charge FET turns on instead
30. RAM changes the voltage at which the device detects a fault condition However the value has not yet changed in the EEPROM so a power cycle returns the old OV threshold To make the value permanent requires that the value also be written to the EEPROM The EEPROM tab see Figure 27 of the GUI shows only one set of registers This could be the values read from the Configuration RAM or from the EEPROM Which values it displays is dependent on the access code The access code is set in Register 89H but the GUI automatically sets this bit when the Read EEPROM or Write EEPROM buttons are pressed The Access code is also settable by clicking the Memory Access button as described previously Config Mem RAM User EE Pack Settings To write to individual bytes of the RAM part of the Configuration Memory set the RAM Access in the Memory access box Each byte in RAM can be written separately Writing to individual bytes to the EEPROM part of the Configuration Memory is limited Each EEPROM write needs to write all four bytes on a page For this reason the GUI has a different larger button for writing to EEPROM As previously mentioned in order to write to a page of EEPROM it is necessary to set the EEPROM Access the Memory access box prior to the write As with the RAM tab hovering over an address box brings up a dialog showing a simple description of the register contents Also the various registers are color
31. Uvieckou i 500 v cB Lower um 3 100 SLEEP Mode 240 min lt 5 1 CB Min Delta 0 019 0 530 OT Recover 0 590 ee UT Recover 1 190 CB under Temp 1 344 CB On Time 2 sec vw Internal Over Tmp 0 719 V CB Off Time 2 sec Internal OT Recover 0 662 CB during charge CB during discharge wD Timer 31 sec of Cells 8 xT2 Monitors FET Temp Enable CELLF PSD action Enable Open Wire PSD Enable UVLO Power Down Disable Open Wire Scan I Cascade two 15194203 CB during Charge Detect Pulse width ims Load Detect Pulse Width ims I Charge Over Temp o s30 V charge OT Recover o ss0 V Charge Under Temp 1 344 V Discharge Over Temp o 530 v Discharge OT Recover o 590 V Discharge UT Recover 1 190 V v Discharge Under Temp 1 344 V lt lt lt lt lt lt lt Read Pack Write Write Settings Settings EEPROM FIGURE 29 ISL94203 GUI PACK SETTINGS TAB Submit Document Feedback 18 AN1952 2 December 4 2015 Application Note 1952 ISL94203 GUI ISL94203 GUI ISL94203 DEVICE ISL94203 DEVICE PACK SETTINGS TAB EEPROM TAB CONFIGURATION RAM EEPROM MEMORY EEPROM SHADOW MEMORY w E i a 3 4 m on 1 ui s mox j amp m
32. aved GO Starts and STOP ends data collection Click Stop to save 22 Perform actual write operation collected readings to file A WO N HM Enable Plot speeds up data collection by disabling real time graphing Highest reading lowest reading Display of most recent reading Peak Maximum value recorded o ON Minimum value recorded 10 Clears items 6 8 9 11 Resets graphing scale to max default 12 Recalculate Maximum and Minimum values of graphing area 13 Decreases volts per division visual only does not affect collected readings 14 Increase voltages per division visual only does not affect collected readings 15 Recenters midrange scale and moves graphing range 16 Actual time in milliseconds to capture and graph a measurement 17 Hex value of Mux control register 18 Internal Mux selection 19 PGA gain selected when making a current measurement Submit Document Feedback 12 intersil AN1952 2 December 4 2015 Application Note 1952 The Internal AD Utility form is a separated form that can be closed or minimized independent of the main screen see Figure 24 US hose Es Uy Boa ntes 8194203 Muxand AD a Aud luc pioni inte amp il 15194203 eg ur Actio Source Se uM fata neo I wm 39
33. b on the left of the screen The GUI highlights the specific cells that equal the CELLMAX and CELLMIN voltages This helps to identify which cells are high or low on quick inspection When any cell voltage is lower than the undervoltage level or higher than the overvoltage level the background color of that voltage readout changes to red When the voltage rises above the UV recovery voltage or drops below the OV recovery voltage the background color returns to white These color changes are GUI representations of the cell voltage conditions the actual Submit Document Feedback 6 intersil indication from the device is shown by the UV and OV status indicators bottom right of the screen These indicators come directly from the device status bits Below the CellMIN and CellMAX readings are three boxes that show additional voltage values The top box contains the sum of the individual cell readings The middle box shows the voltage reading of the total battery pack as derived from an internal divide by 16 voltage divider and converted by the ADC Comparing these two values allows a gross determination if there is a cell voltage failure The bottom box shows the voltage of the 2 5V regulator The regulator voltage is internally divided by 2 then converted by the ADC and multiplied by 2 prior to display Pressing the Read Voltages Single button completes one read of the values in the device see Figure 6 This includes all of the
34. be considered The 1k resistor can be reduced but this makes the part more susceptible to input currents during hot plug of the battery cells A smaller input resistor would also require higher value capacitors to ground to maintain the same filter Higher value resistors on the upper cells would be higher cost Submit Document Feedback imtersil The 1k resistor can be increased The limit relates to the accuracy of measurement In the worst case conditions there is a difference of about 2 of bias current on the inputs The ISL94203 is factory calibrated assuming an input 1k resistor An extra 1k input resistor can generate up to 2 of error Larger input resistors increase this error The capacitors from each input to ground provide a better filter than the capacitors across each input However differences in capacitors on adjacent inputs could result in some voltage errors on the input Both capacitors to ground and capacitors across inputs are provided on the board but the application may not need both Larger input capacitors can affect the open wire detection circuit If larger capacitors are used and the open wire circuit does not seem to detect the open condition increase the Open Wire Sample Time timer value in the GUI Protection Circuits The board contains several protection components that should be on any application There should be diodes on VBATT DSCG CHRG to GND to preve
35. button for Exit Sleep control FETs off push button for quick all FETs off condition Cell balance LEDs for MCB process observation e PCB layout accommodates solder braid addition for high current evaluation e Software enables real time observation and data collection of 14 analog measurements and 27 digital status indicators References ISL94203 Datasheet Ordering Information FE 1S Age PART NUMBER DESCRIPTION ISL94203EVKIT1Z Evaluation kit for the ISL94203 1k oooOOOOO Epoooon FIGURE 1 ISL94203EVKIT1Z EVALUATION BOARD December 4 2015 1 AN1952 2 1 888 INTERSIL or 1 888 468 3774 Copyright Intersil Americas LLC 2014 2015 All Rights Reserved Intersil and design is a trademark owned by Intersil Corporation or one of its subsidiaries All other trademarks mentioned are the property of their respective owners CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures Application Note 1952 What is Inside The Evaluation Kit contains ISL94203 evaluation board MCB_PS_Z multicell power supply test board 519420 17 USB to 2 interface kit includes PCB and I2C cable e USB cable connects PC to USB I2C interface board What is Needed The following instruments will be needed to perform testing 30V 1A adjustable p
36. cation Note 1952 Step 2 Click on Read Voltages Single This updates all the Step 4 Review the operation of the GUI features in the cell voltages temperature and current readings and following sections updates the status indicators Step 3 Click on Read Pack Settings This returns the configuration parameters set in the device PCSDA Control Internal AD Utility About PCFET CFET on DFET on mtersil ISL94203EVKIT1Z Enable during UV Uviskeu o IDLE DOZE CE Upper Lim Mode Timer mn Ed zs Charge Detect Pulse width ims Load Detect Pulse width dud Ixr2 0 945 0 472 y Charge Over Tem p D V Charge OT Recover av TE Rate E i Tus 29 120 V pei ipe 1 Charge UT Recover 0v i 29 131 V Charge Under Temp ov i Auto Scan VRGO 2 515 START CHING OVLO DOT Discharge Over ov Discharge OT Recover ov CB UT Recover 0 Discharge UT Recover of Calls 3 DCHING ov DUT Under Temp 0 Discharge Under Temp ov 5 5 COT coc CB Time o ms Internal Over Tmp v uv C CUT Enable CELLF PSD action CB Off Time o me Internal CT Recover ow Enable Open Wire PSD C psc LVCHG C IOT Enable UVLO Power Down d
37. controls see Figure 46 This allows the user to test some items without connecting a real charger or load to the system This is useful in simulating current flow and overcurrent errors The controls available in this tab are test modes only They set the various bits in the device but do not actually create the condition However by setting the bits in the device the device responds as if the condition occurred For example forcing the charge current direction bit forces the device back into normal operating mode and enables balancing if balancing is enabled during charge AN1952 2 December 4 2015 Application Note 1952 Config Mem Useree Pack Settings Control Thermistor Current Direction Force Charge Indicator Force Discharge Indicator Un Force Current Direction Indicator Over Current Fault Force Charge Over Current Indicator Force Discharge Over Current Indicator C Force Discharge Short Circuit Indicator Un Force Over Current Indicator Note This routine also sets the uCLMON and uCCMON bits These are test modes only They set the various bits in the device but do not actually create the condition However by setting the bits in the device the device responds as if the condition occurred For example forcing the charge current direction bit forces the device back into normal operating mode and enables balancing if balancing is enabled during charge FI
38. e 1Path aide of J4 Also connect a shunt on the 1Path side of jumper J9 In this configuration both charge and discharge connections of the pack connect to the DSCG pin For the separate charge and discharge path connect a shunt on J4 and 19 on the 2Path side of each In this configuration discharge is on the DSCG pin and charge is on the CHRG pin If the plan is to test the board with significant amounts of current then replace the shunt with some soldered braided wire to complete the circuit In this way the board should be able to handle a discharge current of 20A and charge current of 2 5A 1 Path FIGURE 54 SOLDER JUMPERS FOR HIGHER CURRENT AFE The analog front end of the ISL94203 adds external cell balancing components The cell balance output from each cell balance pin is a constant current of about 25 This generates about 8 25V across the 330k resistor between the gate and source of the balancing transistor If a balance FET with lower gate voltage requirements is desired reduce the value of the gate resistor The evaluation board uses 1000 cell balance resistors so it balances about 40mA of current The board also includes LEDs on each cell balance circuit to indicate when the cell balance is active The cell input filters consist of a 1k resistor a 4 7nF capacitor to ground and a 10nF capacitor cell to cell These can be changed to suit the application but the following guidelines should
39. e it does the same function as the button in the EEPROM Tab However in the Pack Settings tab it is necessary to do a Write Pack Settings operation prior to doing the Write EEPROM Otherwise the EEPROM would not get the latest values from the Configuration Memory RAM to write to EEPROM This is because the Write EEPROM writes values from the GUI Config Mem tab to the device and the values in the GUI Config Mem tab are not updated until execution of the Write Pack Settings operation Figure 30 on page 19 shows a graphical representation of the operation of the Pack Settings tab operation the GUI EEPROM tab and the ISL94203 internal registers The memory operations of the Pack Settings tab was described above The next section covers some additional details about the calculations and use of the values shown in the Pack Settings tab Config Mem RAM User EE Pack Settings uC Control Thermistor DEMO Lockout 4 350 OV Delay 1 sec Discharge OC 32mV Time Over Voltage 4 250 DOC Delay 160 ms uv Delay 1 Recover 4 149 Charge OC 8rnV End of Charge 4 200 Sleepvok is sec v 160 lt Discharge SC 128mV Under Voltage 2 699 Open Wire 20 ms 55 Smple Time OSC Delay 200 jus Sleep Voltage 2 000 Low V Charge 2 300 V V V V Recover 3 000 V Delay Time V V V
40. er operations are prohibited until the read or write completes and the color and caption return to normal This sequence occurs on all controls described in the following The main screen shows the real world contents of the ISL94203 registers converting hex values to volts current or temperature and indicating individual status bits The GUI performs this update when the Read Voltages Single or automatic scan executes The update operation begins with a Read All RAM operation This brings in values from the ISL94203 see Figure 26 on page 15 The GUI then converts the hex values in RAM to the proper voltage current or temperature value The GUI controls for the writable RAM registers are located in the uC Control tab These tab operations will be discussed in more detail in the following Pack Settings I Cc Read All pan Write All FIGURE 25 15194203 GUI RAM ACCESS Submit Document Feedback 14 AN1952 2 December 4 2015 ISL94203 MAIN SCREEN SN PW Scie OR KIRAY i Bi 1 E payaa aaa a E l S SENSE 3 wi al aY 4 1 i i E I l E sp _ R P P LM misi xs ma mx LAN NM NL Application Note 1952 ISL94203 GUI RAM TAB 2 d ed C Doc 1 in i i Am ca Y 1 Y 1 d x im mua
41. ess However for individual memory read or write it may be necessary to change the access code These buttons allow this access code change Simply click on the About Advanced Trace Lipson BSVD Active Measurement Sours ADC Hex ADC Cale Instant a V HATH Temp X Turi r Curreet Gan vRGO VBAT Cunent UNI UR im 50 5 C sm CELL CEU 3 CELL 4 CELLS CELL CELL CELLE PS47201 Block Mux Input E desired memory area button prior to the actual read or write operation Memory FIGURE 16 MEMORY ACCESS 15194203 Internal AD Utility screen enables the user to view and record AD readings in real time By using the I2c interface the GUI enables a user to select any of the internal Mux channels and view capture the results in real time To bring up the AD form click on the Internal AD Utility selection on the menu bar of the main form 2 SDA Control Internal AD Utility About ISL94203EVKIT1Z FIGURE 17 intersil When first loaded the new form will appear as in Figure 18 Mensurement Screen Findings Graphing Options Peaks Farad Susi Putin x Decisis Boniin Total Loo mac Fu ES FIGURE 18 Submit Document Feedback 10 intersil AN1952 2 Dece
42. ings e The source of measurement should have a low output impedance A string of resistors that sets the input voltages like the Intersil MCB_PS_Z board can have small changes in the input voltage as the ISL94203 samples each cell Later models of the MCB_PS_Z board will have 10pF capacitors across each input These capacitors should minimize sampling errors e The ADC reading should be compared with the voltage on the PCB before the input resistors at J2 If the voltages are compared with DVM readings at the battery pack where there is a long cable then there should be separate wires for GND and VCO and for VC8 and VBAT The reason for this is that the VBAT and GND leads will carry perhaps a lot of current so there may be voltage drops across the wires The VCO and VC8 terminals are Kelvin connections that do not carry much current Cell voltage measurements are based on VCO and VC8 not GND and VBAT intersil 3 4 e Soldering the board to the PCB can change the stresses on the package from what they were during device calibration This can change the value of the voltage reference which changes the ADC converted value This does not affect the relative voltage readings If there is an external uC then an offset can be added to the uC to correct for solder induced stresses changed the Pack Settings tab such that the CB during EOC button is checked But after power cycling the part the CB during
43. le Open Wire PSD bit when set to 1 causes the PSD bit to be set when the device detects an open wire condition The Enable UVLO Power Down when set to 1 causes the device to power down when it detects an undervoltage lockout condition The Disable Open Wire Scan bit when set to 1 turns off the open wire scan operation The Cascade two ISL94203 bit when set causes the device to operate in cascade mode as determined by the ADDR input When the ADDR input is tied to RGO then the part thinks that it is the lower device so it turns off the current sense circuits and does not drive the FETs When the ADDR is tied to VSS then it thinks it is the upper device so it keeps the current sense circuit on and controls the power FETs The ADDR bit also changes the 2 slave byte address Submit Document Feedback 22 imtersir CELL BALANCE ENABLE As part of the Cell balance settings are the Cell Balance controls for charge discharge or end of charge balancing see Figure 38 CB during charge CB during discharge CB during EOC FIGURE 38 CELL BALANCE CONTROLS If CB during charge is checked then the device activates cell balancing if charge current is detected and all other conditions are within limits If there is no current or there is discharge current then the device does not balance If CB during discharge is checked then the device activates cell balancing if discharge c
44. ltage result in large changes in LED brightness If the LEDs connect direct to the RGO output the 4 LEDs would pull at least 5mA from the RGO output While this is within the capability of the RGO it could lead to some internal heating of the die Since this board is for evaluation and an actual application would not normally have the LEDs an indirect approach to powering the LEDs was adopted The current mirrors use a resistor on one side to provide a current gain The LEDs are each driven with 1mA of current from VBATT but the drain from the RGO output is only 40 6 CELLS VCELL8 CB8 VCELL7 CB7 VCELL6 FIGURE 55 BATTERY CONNECTION OPTIONS USING THE ISL94203EVKIT1Z BOARD Submit Document Feedback 31 intersil AN1952 2 December 4 2015 Submit Document Feedback 32 Application Note 1952 Errata Q amp A 1 When I power the board the device does not power up correctly It looks like it is in sleep mode Before applying power to the evaluation board disconnect the 2 cable the board is powered then connect the I2C interface The reason for this is that U2 on the board has internal protection diodes from the 2 traces to RGO When SCL and SDA pull up externally to 3 3V the ISL94203 is partially powered so it does not complete its power up cycle Cell measurement accuracy does not match the specifications in the datasheet There are some other potential reasons for inaccurate read
45. m u Y V 1 1 L gt gt gt gt ISL94203 RAM MEMORY udi a Lor E rr ial al ado dg at 1 1 4 7 1 cra Wa E d A Cn it E14 Voltage I NR CELLS Voltage f LECIE i T CU ted TE eae wi ig _ a W ep li Mao UL BR NOTE Read Voltages Single or Read Status Bits Operation execution steps are numbered Write All RAM writes to the ISL94203 RAM memory then updates the Main Screen FIGURE 26 ISL94203 GUI RAM UPDATE OPERATION READ OPERATION NUMBERED Submit Document Feedback 15 intersil AN1952 2 December 4 2015 Application Note 1952 CONFIGURATION MEMORY The Configuration Memory consists of two parts the EEPROM cells and Configuration RAM On power up the contents of the EEPROM is copied to the Configuration RAM The device operates out of Configuration RAM Reading and writing the EEPROM does not automatically go through the Configuration RAM Writes made to the EEPROM locations will go into effect when the device power cycles or when the EEPROM contents are read from the EEPROM and rewritten to the Configuration RAM In the normal course of developing an application a change is made to the Configuration RAM This changes the operation of the device For example changing the overvoltage setting in the Configuration
46. mber 4 2015 Application Note 1952 An important first step is to select an internal Mux Channel that is going to be measured By making a selection clicking Mux selection button see Figure 19 data collection graphing will automatically start and after a few seconds Auto Range will take place 15134203 Internal Mux Selection Internal Temp Tempe ATempl Current Gain VRAGO VBAT Current CELL T CELL CELL CELL 4 CELLS CELL 8 FIGURE 19 Essentially clicking in the frame selection selects the value written to register Ox85 The user can consult the datasheet for specifics related to each Mux Input connection BIT Current gain set when current ls monitored by Only used when Microcontroller overrides the intemal scan Ext iC sets this 010 Galn 03210 03210 bit to 1 to start a 00 150 0000 OFF 1000 conversion 016 0001 1001 Pack current 101500 0010 V2 1010 VBAT 18 111500 0011 V3 1011 R60 2 0100 Ved 1100111 0101 V5 1101 12 0110 16 11101 0111 Wi 1111 OFF FIGURE 20 A real time display of the register contents is displayed in Figure 21 Reg 0x85 AD Control FIGURE 21 Submit Document Feedback 11 inter Therefore this selection programs the MUX blocks connected to the input of the internal AD CURRENT SENSE GAIN AMPLIFIER E x5 GAIN OVERCURRENT STATE MACHINE FET CONTROLS C
47. mediately sees the test mode fault condition so it again responds as if there is fault The device continues to oscillate between these modes because the demo condition is not real Over Current Fault Force Charge Over Current Indicator C Force Discharge Over Current Indicator C Force Discharge Short Circuit Indicator Un Force Over Current Indicator Note This routine also sets the uCLMON and uCCMON bits FIGURE 48 OVERCURRENT FAULT DEMO OPTIONS To get a better understanding of the operation connect a potentiometer to the load output Make sure that the minimum resistance on the potentiometer is about 1kQ This is not so low that it is damaged when the FETs are on but is low enough to detect a load Now force a discharge overcurrent condition Look at the SD LED on the PCB it should be on continuously Use the p C Control tab to clear the uC Load Monitor bit Now the device detects the overcurrent from the test bit It sees that there is no current so it starts the load monitor Because of the potentiometer it sees that there is a load so the fault condition remains in effect and the SD LED remains on By gradually increasing the resistance on the potentiometer the device will reach the point where the device detects that the load is removed At this point the SD LED will resume the oscillations as it detects the load clearing and sees the demo fault AN1952 2 December 4 2015 y
48. nitor the CH_PRSNT bit to detect if there is a charger present If the charger is removed following an overcurrent condition then the GUI pC needs to reset the charge error bit by clicking on CLR Charge Error The uC Does Load Mon bit overrides the internal load monitor function When overridden the GUI or an external uC can turn on the load monitor current and detection hardware by setting the Load Mon Enable The GUI or external uC then needs to monitor the LD_PRSNT bit to detect if there is a load present If the load is removed following an overcurrent condition then the GUI uC needs to reset the load error bit by clicking on CLR Load Error All of these operations start the Watchdog timer If communications with the device stop for more than the Watchdog time out period then the device resets the override bits and waits for a valid communication When a valid communication is received the device resumes normal default operation The Pack Shut Down control is a direct control of the PSD pin The Open Wire Start is a manual open wire start operation This open wire scan does not need to first wait for a CELLF condition Submit Document Feedback 24 CELL BALANCE The GUI uC can manually control the cell balance operation overriding the internal automatic balancing Set the HC Does Cell Bal bit and the Cell Balance On bit Then check any or all of the individual cell balance bits to
49. nt negative voltages on the pins of the ISL94203 The schematics show the use of 43V zener diodes so the inputs are also protected against high voltage transients The board provides transient voltage suppressors on the pack pins to help minimize problems with ESD on the board There is a protection device USBLC6 on the 2 inputs to minimize damage due to ESD on the IC connector While this component helps protect against ESD it is also a problem for the board Since this component has internal diodes between the I2C pins and the RGO power pin connecting the 2 interface to an externally powered uC before the 15194203 powers up prevents proper power up of the ISL94203 If there is a hardwired connection between the uC and the evaluation board U2 can be removed from the board and replaced with jumpers across pins 1 to 6 and 3 to 4 This will allow the uC to power up before the ISL94203 powers up Back to back diodes are connected across the current sense inputs to prevent excessive differential voltage across these pins Push Buttons The board provides two push buttons for ease of use and evaluation purposes These are not required in an application The wake up push button simulates the connection of a pack to a charger It does this by connecting the CHRG pin to VDD using a 1k series resistor The device sees this as a charger connection The ISL94203 can also be wakened by momentarily connecting a resistor from the DSCG
50. oard directly to the MCB PS Z board at connector J1 Make sure the board is connected on the ground side of J1 see Figure 2 Step 6 Turn on the power to the supply If no LEDs light press the WakeUp button Notice that there is one green LED RGO indicating the LDO regulator on the ISL94203 is operating The voltages at various points should be RGO 2 5V 3 VREF 1 80V 0 5 Step 7 Connect the USB port of the PC to the USB port of the 1519420 17 interface board Step 8 Connect the 2 cable from the 1 519420 17 board to the 1519420 17 board J13 Step 9 Open the ISL94203 GUI software Use the software to read the cell voltages Step 10 Compare the voltages at the board input use a meter to measure each input voltage because the MCB_PS_Z board may not accurately divide the voltages into equal 3 5V steps with the readings provided by the GUI These voltages should closely match Step 11 See other operations described later in this document PCB Layout Guidelines The AC performance of this circuit depends greatly on the care taken in designing the PC board The following are recommendations to achieve optimum high performance from your PC board The use of low inductance components such as chip resistors and chip capacitors is strongly recommended Minimize signal trace lengths This is especially true for the VDD charge pump decoupling CS1 CS2
51. om File Write User Save User Default to File AA A A A A FIGURE 28 15194203 GUI USER EEPROM TAB Submit Document Feedback 17 intersil AN1952 2 December 4 2015 Application Note 1952 PACK SETTINGS TAB The Pack Settings tab see Figure 29 provides access to the contents of the Configuration RAM but with real world values This provides an easier way to program the operation of the pack and to monitor the present settings Values in the Pack Settings tab are saved in the GUI When a Read Pack Settings button is pressed the value is read from the device and loaded into the Configuration RAM tab of the GUI The GUI then takes the contents of the Configuration RAM calculates the real world value and writes it to the pack settings tab When a value is changed in the Pack Settings tab nothing happens until a Write Pack Settings button is pressed The GUI then takes the value in the Pack Settings tab converts the value to hex and writes the new value to the Configuration RAM tab in the GUI These values are then written from the GUI to the RAM part of the device Configuration memory If a value is changed in the GUI but no write button is pressed then the device is not updated with the new value As soon as the Write Pack operation completes the ISL94203 begins operating with the new parameters The Pack Settings tab also includes a Write EEPROM button This is a convenience sinc
52. one mode To control the FETs through the GUI requires that the UCFET bit is set first This bit is set or reset using the uC Controls FET button the p C Control Tab Above the FET control bits are some controls to change the operation of the device These controls are PCFET enable CFET on during OV and DFET on during UV Setting the PCFET enable to active causes the PCFET to turn on instead of the CFET when the voltage is below the Low V Charge threshold voltage see the Pack settings Setting the CFET on during OV to active means that the charge FET will turn on when there is an overvoltage condition if the device detects a discharge current This reduces heat generated in the CFET during discharge This is more important when there is a single charge discharge path configuration Similarly setting the DFET on during UV to active means that the discharge FET will turn on when there is an undervoltage condition if the device detects a charge current This reduces heat generated in the DFET during charge This is more important when there is a single charge discharge path configuration OTHER MAIN SCREEN CONTROLS Communication to the device requires an 2 bus The I C bus uses a Slave byte to determine the specific device on bus that is being addressed In the GUI this is set by the IC Addr box see Figure 14 This is located in the lower left of the screen By default the Slave Byte is 50H 0101 0
53. op has two boxes The left box shows the voltage reading from the internal temperature sensor This voltage is dependent on the setting of the temperature gain bit TGAIN The temperature gain can be changed using the GUI by clicking the TGAIN button in the temperature box in the bottom left of the screen below the tabs The box on the right shows the conversion of the internal temperature to C This conversion uses Equations 1 and 2 _ 973 15 TGAIN 0 18527 ICTemp C 0 1 intTemp mV _ 092685 273 15 ICTemp C For the external temperatures the left box shows the digital reading from the ADC The right box shows the applied input voltage The value on the left is dependent on the setting of the TGAIN bit If TGAIN 0 then the temperature input voltage is multiplied by 2 prior to being read by the ADC If TGAIN 1 then the temperature input voltage is multiplied by 1 The left box of the external temperature readings simply translates the voltage readout by the ADC The right box calculates the input voltage based on the setting of the TGAIN bit TGAIN 1 EQ 2 Submit Document Feedback intersil The temperature readings can also be displayed C see Figure 8 The conversion to C depends on several items First is the gain setting so the actual input voltage is known Second is the external resistor divider components Third is the conversion of the thermisto
54. or set to power down but it can only return to a normal scan operation if it detects current flow in the pack The GUI also offers a demo mode that forces a current indication so that can be used to return to normal mode It is not necessary to override any internal operation to change the operating mode AN1952 2 December 4 2015 Application Note 1952 INDIVIDUAL VOLTAGE MONITORING The GUI or an external uC can force a read of any voltage available from the internal MUX This includes cell voltages pack current and voltage and temperatures It is not necessary to override any internal function to use this measurement To use this feature select the voltage to be measured and click the W button R button reads the status of the bits but a write operation sets the bits for the desired voltage and sets the ADCSTRT bit needed to start the internal conversion operation The resulting voltage shows in the box at the right see Figure 41 This is a 14 bit hex value This value then needs to be converted to voltage current or temperature When measuring the current the gain of the amplifier can be manually set prior to the ADC read by using the drop down box and W button on the top line The GUI allows the repetitive capture of any single voltage or all voltages For a single voltage capture the desired voltage is selected by the Monitor Voltage box see Figure 42 The number of samples is
55. ot saved AN1952 2 December 4 2015 Application Note 1952 Config RAM xT2 PIN 80 C 0 153V 50 C 0 295V 25 C 0 463V 0 C 0 624V 20 C 0 710V 40 C 0 755V MuRata NCP XH103F Type Thermistors R1 R2 Temp Resistor Ohms 22000 iJ e FIGURE 9 15194203 GUI THERMISTOR TAB lt H gt 2 2 TEMPERATURE FIGURE 10 VOLTAGE TO TEMPERATURE CONVERSION Submit Document Feedback 8 intersil AN1952 2 December 4 2015 Application Note 1952 CURRENT READINGS The current readout consists of four boxes see Figure 11 The top box shows the voltage across the sense resistor as reported by the device and converted to volts The next box shows the current reading in milliamps This value depends on the value of the current resistor This can be entered into the third current box The default value is 10 because that is the value on the ISL94203EVKIT1Z board If the resistor value changes then this value can be changed in the GUI but the default cannot be changed in this revision of the GUI The bottom box simply relates the current amplifier gain setting in the device In automatic scans there is an automatic gain control The gain setting is most useful when forcing a current read by the GUI Current ISense v 0 000 ISense A mA ISense R 1 mohm cS Gain 5 FIGURE 11 CURRENT READOUT
56. ower supply e Wires to connect power supply to MCB_PS_Z board Precision multimeter optional Oscilloscope optional Cables and wires optional Software Installation Connect the ISLUSBI2C USB to the PC The board should automatically enumerate in the device control panel under Human Interface Devices The vendor ID will OXO9AA and the product ID will be Ox2036 Since it is a HID device no special driver is needed Step 1 Step 2 Copy the islI94203evkit1z software exe program to the PC any desired location Double click to run the installation file Note you may need to use the Run as Administrator open when performing the installation file Quick Hardware Setup Guide Step 1 Check the jumpers and switches on the board The board should be configured as follows e ADDR jumper set to 0 x72 Select jumper on either CELL or FET FET jumpers set for either one path or two path Start with one path J4 jumper is set to 1 Path J9 jumper is set to 1 Path Step 2 Connect the power supply to the MCB_PS_Z board The positive terminal is J5 J11 and the negative terminal is J8 J12 There should be a jumper on JP2 8CELL Step 3 Setthe power supply voltage to 28V 3 5V per cell Optional check that the voltages at terminal J1 or J3 are 3 5V per cell Step 4 Turn off the power to the power supply Submit Document Feedback 2 intersil Step 5 Connect the ISL94203 b
57. pin to GND Use a 2k resistor to minimize current when the power FETs turn on During manufacture of the battery pack the finished pack can be connected to a charger or this wake up switch can be included on an external jig to power up the board prior to final programming The FETSOFF pin connects directly to the FETSOFF input of the ISL94203 When pressed the power FETs and cell balance AN1952 2 December 4 2015 Application Note 1952 FETs turn off Normally in a system this input would connect to a uC or an external control source If FETSOFF connects off board add a 3V zener diode to GND to prevent glitches on this input from going too high or negative LED Indicators There are 4 LED indicators on the board The LEDs are not required in a real application they are used here to provide quick monitoring of the system The LEDs are RGO Green EOC Red SD Red and PSD Red The LED indicator circuits use current mirrors to drive the LEDs There are several reasons for this The ISL94203 RGO regulator output voltage is 2 5V 2 25V to 2 5V Because of this voltage and range it is difficult to 8 CELLS VCELL8 d CB8 VCELL8 CB8 VCELL7 CB7 VCELL6 7 CELLS directly drive LEDs that have a forward voltage drop of 1 8V to 2 3V while controlling current to acceptable levels When directly driving the LEDs from the RGO output using a current limiting resistor small variations in the supply vo
58. r of cells it is not the value stored in memory The GUI translates the number of cells value to the proper code for the device as specified in Table 1 FIGURE 34 NUMBER OF CELLS BOX When the board first powers up the of Cells is set to 3 This causes some of the cells to show OV in a Voltage Scan This is because the cells are skipped in the scan If there are more cells connected change the setting write the values to the pack then write the values to EEPROM The reason for the default value of 3 in the of Cells box is that if the number in the box is greater than the number of cells connected to the pack when the ISL94203 first powers up it reads a cell input as OV The ISL94203 thinks that this is a cell failure so does not complete its power up sequence This is part of the protection mechanisms of the part If the value written to the EEPROM is higher than the number of cells connected and the device powers down then it will not power up properly It will be necessary to connect the programmed number of cells or more so the device powers up Then the EEPROM value can be reset For the proper connections of fewer than 8 cells see Table 1 When using the evaluation board with fewer than 8 cells connect the unused cell inputs at the board connection It is not necessary to remove any components on the board see Figure 55 on page 31 TABLE 1 ISL94203 CELL CONFIGURATION CELLS VALUE NUMBER OF CEL
59. r value to C Temperature V 0 570 34 5 Input xT1 0 907 26 3 degC 0 897 27 1 degt FIGURE 8 TEMPERATURE READINGS DISPLAYED IN C The gain setting is important only for determining the voltage applied at the input xTn pin Next the conversion depends on the external resistor divider and assumes that the external circuit is implemented as shown in the Thermistor tab drawing Figure 9 on page 8 There is a 10k resistor parallel to the thermistor There are two reasons for this First it makes the conversion curve more linear Second the thermistor voltage range better matches the default 2x gain on the temperature input amplifier The thermistors are from Murata XH103F If an external thermistor replaces the thermistors on the board the conversion can be changed by changing the values in the Thermistor tab of the GUI The values in the table are the voltages applied to the xTn input pins The voltage depends on the resistance of the Thermistor at each temperature and the voltage on the TEMPCO pin The TEMPCO voltage is 2 5V Based on calculations the voltage temperature curve for this circuit is shown in Figure 10 on page 8 The GUI uses the Thermistor table for this conversion and performs a linear interpolation between points For calculations of the external temperature the Thermistor tab contains a value for the external divider resistor This can be changed by the user but n
60. the GUI already described and the GUI reads and writes these registers as needed The user also has direct access to the RAM memory through the RAM tab See Figure 25 To update the values in the GUI with the values in the ISL94203 press the Read All RAM button The display now shows the hex values of the RAM registers Alternatively each individual location can be updated by clicking on the R to the right of the register location There are only six registers that can be changed by the user These are addresses 84H to 89H These locations have a W next to the register To change the register contents write a new hex value in the desired location and press the W button or the Write All RAM button Until a write occurs the contents of the ISL94203 RAM is not changed Config Mem As shown in Figure 25 hovering the mouse pointer over the address of a register returns a description of the register Also the registers are color coded to match the datasheet and to group like registers For example in Figure 25 registers 80H to 84H are cyan color These are the status registers Also registers 8EH through ABH are blue These registers hold the voltage readings for the cells current and temperature When pressing the Read All RAM or Write All RAM buttons the color of the button changes and the caption changes to Busy During this time the GUI is performing the specified operation and oth
61. to some intermediate state If the load or charger is off but there is a large capacitance still connected to the terminals a short pulse width will take longer to detect the removal The ISL94203 allows detection pulse widths from 1ms to 16ms TIMERS Below the voltage settings are some timer controls The upper box specifies the amount of time the device spends in normal mode with no measured current before entering into IDLE and the time the device spends in IDLE before entering the DOZE mode The Sleep Mode timer specifies how long the device remains in DOZE mode with no measured current before going to sleep Detection of any current returns the part to the normal operating mode IDLE DOZE 1eLEozE ismi 15 min Mode Timer SLEEP Mode 240 min Timer wD Timer 31 FIGURE 33 TIMER CONTROLS The WD Timer setting is used with uC override operations When the uC sets any condition that overrides internal operation the WD timer starts The WDT is reset by any valid reception of an I2c slave byte If there are no valid communications before the WDT times out then the ISL94203 turns off all FETs and waits for a valid command AN1952 2 December 4 2015 Application Note 1952 NUMBER OF CELLS The number of cells box Figure 34 specifies the number of cells connected to the pack The number in the box can be lower than the number of cells connected to the pack This value is a direct representation of the numbe
62. uring charge 5 C UVLO i Settings Settings EEPROM Cascade two 15194203 VH UM cO e eS EE C CH PRSNT CBOV CBUT Volts iT 0 544 20 5 degC Input xT1 0 944 0 472 V Current EN i Discharge 0C amv gt EU os E Over Voltage 0 shi f BUS o in E ISense a 79 mA End of Charge V Siecp Vor ame COC Delay 0 gt asa Uv Recover o v E EE Discharge 5 6 gt v Temperature v v V CB Lower Lim 0 SLEEP Mode 15 min Timer CB Max Delta 0 CB Min Delta 0 WD Timer 0 sec CB Over Tem p CB OT Recover X GIO a GLO o X lt I2C Disabled ERG HIE Memory agite cM IDLE a so Ey zem RAM EEPROM pe J CELLF poze NAK OPEN SLEEP t degC Gain now is 2 Ezd FIGURE 4 MAIN GUI WINDOW SHOWING PACK SETTINGS Submit Document Feedback 5 intersil AN1952 2 December 4 2015 Application Note 1952 Using the GUI Common Screen The right side of the GUI shows the status of the ISL94203 At the top are voltage current and temperature readings The bottom are the status bits At the bottom of the screen are several controls for temperature settings and memory access CELL VOLTAGE SCANS The voltage readouts Figure 5 show the values for each cell plus CELLMAX and CELLMIN values The CELLMAX and CELLMIN
63. urrent is detected and all other conditions are within limits If there is no current or there is a charge current then the device does not balance If the CB during EOC is checked then the device ignores the current detection and balances only based on the end of charge condition as long as all other conditions are with limits With this option selected cell balancing is enabled when any cell reaches the end of charge threshold Balancing continues as long as any cell is greater than the EOC threshold minus 117 While cell balancing is enabled in any mode balancing is turned on for any cell whose voltage is more than CELLMIN CB Min Delta volts uC Control Tab The uC Control tab provides a mechanism for the GUI to override the internal operation of the device An external microcontroller would use similar techniques to provide different functionality to the pack than is offered by the built in automatic operations The options available on the p C Control tab are shown in Figure 39 on page 23 POWER CONTROL The mode of operation of the device is controlled by these check boxes see Figure 40 on page 23 Clicking any box puts the device into that mode of operation Clicking on None removes any forcing condition The uC Control features does not allow the device to be placed back into normal operation For example once the device enters IDLE mode it can be placed in DOZE mode returned to IDLE mode put to sleep
64. wy n V midscalef ER nlarsil V midsca emus a s gt Jet e dmi 51 1 Ar i I il de Yo ts m 28 E a o2 Instant 3504 try tt rate WR ins nf von Min V 1489 E E harper ane oo Afra een Tocca Ta 3 190 viam 28406 EE vaca 151v _ i a Curtin t i 0 ure m rer vam Cm RN aT Went erg SD gre ML a eu Romer town 7 CA dunng charge SS emas EE Ne e 85000900 EPROM pias ois ae Data Collection Running Click Stop Graphing Options or New Mux Channel pena EJ ES C aqe nx ae To quit the program click on Quit Read Quit Status Bits Submit Document Feedback 13 intersil FIGURE 24 AN1952 2 December 4 2015 Application Note 1952 Tab Controls ISL94203 Memory Access RAM The ISL94203 has two main memory areas RAM and Configuration Memory The RAM area contains the transient values such as cell voltages status bits and microcontroller override conditions The RAM registers relate to the part of

ISL94203EVKIT1Z User Guide

Contents

Download Pdf Manuals

Related Search

Related Contents