SMT498 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. 4 22 luo Meer WAA 0 CO PEO 0 O 24 A E E Erg 26 RSL Side 1 Pinout LVDS only dete e 26 RSL Side 2 Pinout LVDS only iie ultra annee nes dite 26 3 RESTE RIT to CIE RT TOO RE 27 POWET CONMECION Rc 28 PGB KA Aa aec 28 Salely ri asado SR Liu se dps 29 EMG auis to MEL Ed 30 o em E 30 Configuring Me FPGA t 31 PCW MO aa iaa 31 JIAG Boundary SCANT naaa adds 32 SISI MAE SC ER 33 Stat s Bit EMCOGING assi NO ES 34 Creating System ACE programming file MPM esses 35 Page 5 Table of Figures Figure 1 Block diagram of the SMT498 wwwwwmwmmimiwimamami maimamu ai 8 Figure 2 Single Size PMC card from IEEE 1386 2001 8 Figure 3 QL5064 CONNeCtIO Ms ss la 10 Figure 4 Default FPGA Configuration ii 12 Figure 5 SH CORectol aseo ote da 13 Figure 6 RSL Top Connector eoe i 15 Figure 7 RSL Bottom COMnmeCton tte odere ee pag uei esee idt deu n reda duce o Ma uua 15 Figure 8 Location of JTAG IN OUT and DIP Switches ccccccconoccnoncccnncccnnanaononcnncncnnnnos 27 Figure 9 Module Side 1 MIOW neca iet e ee oca tens 29 Figure 10 Module Side 2 VINS ss eR ds 29 Figure 11 Module Side View issues 29 Figure 12 Location of the DIP Switches and the PROM 31 Table of Tables Table 1 SHB configuration Matrice nn ina tendue sien 14 Table 2 RSL Speed VS FPGA Speed Grade 16 Table2. 3 Board CIOCkS re P Reb da 16 Table 4 PMC P11 P12 Interface cta operto dias 23 Table 5 PMC P13 P14 Interface suicidas 24 Table 6 SHB UMC ACE Em 25 Table 7 RSL Side PA ui 26 Table 8 RSL Side 2 PIN UWA 26 Table 9 JTAG Header PIU uote rr eS erem id 27 Table 10 Status Bits ENCON cuisine ok ete este 34 Page 6 Introduction Overview The SMT498 is Sundance s latest FPGA PrPMC module This module uses a Xilinx Virtex II Pro XC2VP100 which is configured to provide two comport links five SHB s two RSL s and other functions Module Features The main features of the SMT498 are listed below Xilinx Virtex Il Pro XC2VP100 FF1704 package 128MB of DDR2 SDRAM Five SHB two RSL and two 8 bit Comport interfaces for easy interconnection to Sundance products In System Configuration using System ACE Soft Controller Tall single size PrPMC module 66MHz 64 bit PCI interface with over 500MB s data rate Related Documents 1 PCI Mezzanine Card PMC Spec IEEE http shop ieee org store product asp prodno SS94922 2 Sundance High speed Bus SHB specifications Sundance http sundance com docs SHB 20Technical 20Specification pdf 3 Rocket Serial Link RSL specifications Sundance http sundance com docs RSL 20 20Technical 20Specificationv20Rev01 201ss03 paf 4 Processor PMC PrPMC Spec VITA http www vita com 5 System ACE SC Solution Datasheet Xilinx http di
3. SMT498 adheres to PrPMC standards the entire active and hot parts are on the back of the module which is suitable to place a conduction plate at the back of the module to provide conduction coolong Power Supply The SMT498 shall conform to the PMC standard for single size modules The PCI connectors supply the module with 5 0V and 3 3V power supply The 3 3V will be used to supply all LVTTL digital I O voltages directly The FPGA Core Voltage Vocint 1 5V is generated from the 5 0V FPGA Auxiliary voltage Vccaux 2 5V is derived from 3 3V to minimise losses Note Due to restrictions of the Virtex Il Pro the FPGA Auxiliary voltage Vccaux must be provided before Veco 3 3V Given that Veco is generated externally and Vecaux is generated locally there will need to be a means to switch Veco built into the hardware Standalone operation A 4 pin 0 200 power connector such as the type used to power PC hard disks will be provided on Side 2 of the module This connector provides 5V 12V power and ground SMT498 will generate 3 3V on board from the 5V supply Only use this connector for standalone operation i e when not plugged into a PCI slot Reset Structure The SMT498 shall obey the reset signal provided by the PCI connector In the absence of an external reset signal the module will bring itself out of reset once all supplies are in compliance Page 21 Header Pinout PCI A 66MHz 64 bit PCI bridge will allow SMT49
4. SVF STAPL XSVF 1 want to impot e Spem ACE OF System ACE MPM SC Operating Mode c Expert eet Preference sor Preference eotPreterence sotPreterence setPreterence ATOM cetProterence ese HATCH CHD eetPreference ese BATCH CMD eetPreterence ep ATCH CHD setPrelerence ATCH CMD setPreterence ATCH CMD setPreterence ATCH CMD ATCH CHD BATCH CMD set GUI Switch to File Mode ee BATCH CHD wet For Heti press PI Pin Generation Mode Page 35 b Select size as 64Mbits as the flash can hold 64Mbits TO b d LE Cos Maj A F 6 eve 4 Jr mm sss 46 o a co ews de oe c ene c mme 2 SS i C Specify the name of the MPM file and the location to store it antis En Gunaratiwa Made MBALI NS HIE EN Arte sas ts EH Page 36 d Select In Select MAP mode Rd PACT LLLI co 5 wwa Vi sa som 4 waw d waa wwa d o LLLI o LCA or 22 ass BATCH PATCH Page 37 f Select Configuration Addr 0 Click Next If multiple bitstreams are stored under different configuration addresses The bitstream select switches must be set to the particular address before the board is powered up in order to configure the target FPGA with the respective bitstream os AE VE E mw ts a aco a 9v System ACE PROM formatter SVF STAPL XSVF Fo png
5. System ACE PROM The System ACE SC solution has a OTP PROM XC17V01 The PROM is programmed with the configuration controller before it is installed on the board Configuration Controller The XCV50E is used as the configuration controller The PROM on power up configures the Virtex E chip XCV50E After configuration the XCV50E is seen as a XCCACE64M System ACE chip in the JTAG chain The controller forms a link between the Flash and the target FPGA Four status LEDs are connected to the controller to monitor its state See the Appendix for status bit encoding table Flash A 8MB Flash ROM device is connected to the XCV50E configuration controller The target FPGA bitstream is loaded in to this Flash via JTAG to configure the FPGA on power up Page 17 Power Supplies Due to the close packing of components between PMC Side 1 and the host module power consumption is limited to 4 0W for 10 0mm standoffs this increases to 6 0W for 13 0mm standoffs The total consumption for Side 1 and Side 2 of the module shall not exceed 7 5W and represents the total power drawn from all power rails provided at the connector 5V 3 3v VI O 12V 12V 3 3Vaux For this reason it is recommended that you analyse the total FPGA device power drawn by using Xilinx XPOWER before implementing your design in the FPGA This module must have 5V and 3 3V supplied through the PMC connectors Either 5V or 3 3V may be supplied for PCI I O voltage and sh
6. not go high System Busy Decompressor error System Busy Invalid controller state System Buy Flash memory blank or invalid configuration data in Flash memory System Busy Invalid configuration option System Busy Flash Chip erase successful System Busy System ready to accept commands through JTAG port Successful Slave serial Slave Select MAP configuration CFG DONE high System ready to accept commands through JTAG port Configuration Error CFG DONE did not go high System ready to accept commands through JTAG port Decompressor error System ready to accept commands through JTAG port Invalid controller state System ready to accept commands through JTAG port Flash memory blank or invalid configuration data in Flash memory System ready to accept commands through JTAG port Invalid configuration option System ready to accept commands through JTAG port Flash Chip erase successful System ready to accept commands through JTAG port Table 10 Status Bits Encoding Page 34 Creating System ACE programming file MPM Once the BIT file is generated using the normal procedure open Xilinx IMPACT software Under mode select File mode In the blank space right click to launch wizard a Select System ACE MPM SC Click Next untitied 1 de Gesme attan Mode 21 bow Ow eim tuit d zt 2 System ACE PROM Formatter
7. 2 FPGA Block Diagrami erein 12 Eolio UIRE LiLo e 12 MMO Ya E E E TER 12 SHBS a2 uiuit ad 13 o dots beet E A oU dunes UTR 13 SHB able ASsembly is tete ads 14 SHB Inter Modules solutions ro ERR bct tele x een eR ee ER Ib d ERR VER 14 Half Word Interface 16 bit SHB Interface sssne 14 ROSES Cu PR 15 RSE COMMOCION a dia 15 RSL Gable Assembly ui ads 15 Miscellaneous POS sardi ea cam ssec d UN en EE 16 System AGE SC cion 17 uie p 17 Contigurati n Controller eo tidad 17 IECUR 17 Power Supplies yen Ee liz 18 DG DG CONVENO Sins aa a Up id SON REC 18 Linear Voltage Teguise dif de 18 Daughter Module insti itte aris cera ra ira eaa a a c EUER TU gas 19 PMC Standard enn 20 Voltage Keying ii dea reset ee es tt en ia tresse 20 CORROCIOLS ennemies nm nine tente mine VAR UA Rm a a lente 20 Td minimum aie a i eked Et 20 Board WA reu 20 Standoffs AN Ua 20 Bezel and MO capability Aa 20 Power COMSUMPLOMN recita 20 UNGA CE 21 Condicion Gera MC T cL d pr 21 A Ege 21 Standalone opSrallon eerie oder Obi tee Rh pd iunii as 21 Only use this connector for standalone operation i e when not plugged into a PCI slot 21 Reset SUCIU HA KA outenes ot Aaa eS Mauss he are ac cbepeate paeeeen 21 FUCA SPU OU occidi ei ac ccc ad ae tecen bn a 22 d EES E
8. 8 to communicate with the host system As the Local Bus has a maximum clock speed of 64MHz the maximum theoretical speed data can be transferred between the host and FPGA is 512MB s PMC PCI connectors are directly connected to the QuickLogic 5064 bridge chip PMC P14 must be 5V tolerant P11 P12 Pin Signal name Signal name Pin Pin Signal name Signal name Pin 12V djet2v TRSTN INTAN TDO INTCN GND 5V PCI RSVD N o AJN 3 5 7 GND INTBN BUSMODE1 PCI RSVD PCI RSVD BUSMODE2N 3 3V RSTN BUSMODE3 NTDN ND PCI RSVD 3 3Vaux GND eo A N N N o 1 C2 A anh w Z GNTN BUSMODE4 GND Z IN IN MINI gt N al GND AD29 AD26 3 3V AD23 AD20 GN C BE2N PMC RSVD 3 3V STOPN GND SERRN GND REQN 5V VIO AD31 D28 AD27 D25 GND GND C BE3N AD22 AD21 D19 5 IO AD17 3 FRAMEN GND 35 GND IRDYN 37 DEVSELN 5V 39 GND LOCKN 41 PCI RSVD PCI RSVD PAR GND gt NINI _ 0O 0 J al DIN 0 N O1 2 O1 N NI D o1 ao Oo 00 C2 NJ BILLA DWI WD WI W WININININI NI B IN O O D BA N O O0O O 2 N O O O gt A w oO 3 Co Olt Ula Ol i gt Tsi lo ul O Do miz Z ja Z 215 m 2 3 0 Og e O Z Z gt N D OI N AY AJN BA Page 22 a 5 saoe Jadi e sen fPucrsvo en s
9. GA device and can support data rates of 100MHz Two of the SHBs on Side 1 are wired to support LVDS Each of these connectors can support 28 pairs of LVDS data including 1 pair for clock input Due to a lack of clock inputs on the FPGA only SHBA fully supports 2x16 bit SDB mode All SHBs fully support 32 bit mode See Table 1 for details 16 bit SDB 32 bit SDB LVDS capable capable capable 2xTX RX TX RX No B 2xTX 1xRX TX RX TX RX 2XTX 1xRX TX RX No Page 13 D 2xTX 1xRX TX RX No E 2xTX 1xRX TX RX TX RX Table 1 SHB configuration Matrix The demo logic will configure SHBA SHBB SHBE as receivers while SHBC and SHBD are transmitters As SHBA is the only SHB that can support two 16 bit SDB receivers it will be configured for that implementation The rest of the SHBs either support 32 bit SDBs or 16 bit SDB transmitters See Figure 4 for details SHB Cable Assembly The cable is custom made by Precision Interconnect and a cable assembly solution builder can be found at http www precisionint com tdibrsb content howtouse asp SHB Inter Modules solutions High speed data transfer can be achieved between PMC modules thanks to the use of a 60 way flat ribbon micro coax cable or via PCB connections As a result NO DIFFERENTIAL lines are required to transfer data on long distances and at speeds in excess of 100MHz which allows the full use of the SHB connector 60 pins Half W
10. L Side 2 Pinout LVDS only mew Eme s mew s TXBN4 TXBN5 Table 8 RSL Side 2 Pinout Page 26 JTAG headers The JTAG header is used to access the XC2VP FPGA scan chain and configure the System ACE configuration solution RSL Connectors HB Connectors ATRAS 2 AAA Dt murem JTAG IN DIP Switch S2 JTAG OUT Figure 8 Location of JTAG IN OUT and DIP Switches The JTAG Multilinx header has the following pinout Name La Function Connections Power To target system VCC Supplies VCC 3 3V 10 mA typically to the cable TMS 4 Test Mode Select Connect to system This signal is decoded by the TAP controller to control test operations TMS pih Test Clock Connect to system TCK pin This clock drives the test logic for all devices on boundary scan chain TDO Read Data Connect to system TDO pin Read back data from the target system is read at this pin Test Data In Connect to system TDI pin This signal is used to transmit serial test instructons and data Ground To target system ground Supplies ground reference to the cable 14 Table 9 JTAG Header Pinout Page 27 A JTAG In port and JTAG Out port are provided for chaining multiple modules together A DIP switch is provided to activate the JTAG Out port Power connector A power connector is provided on the board for stand alone operation This connector is a 4 pin male header
11. Moe aS Dott Configuration Adad Corgan Ada Configuaatien Ada Corfg ation Ada Gur oe Switch to File Mode Fie Generate Mode System ACE mon TAM g Click Next h Add the respective BIT file with which you intend to configure the target FPGA neat tt test LE the Cra stida tings peul desktop ent498 rest files Page 38 i Click on Finish j Click on Yes to Generate file k Do not compress the file Click OK Once the file is generated it will be stored in the location specified Page 39
12. SMT498 User Manual Certificate Number FM 55022 User Manual Version 1 2 11 01 05 Sundance Digital Signal Processing Inc 2004 Page 1 Revision History WAA KA Jimi sws Fmtmeme O PIM O AA em 11 1 05 Update on System ACE and JTAG Page 2 List of Abbreviations Abbreviation Explanation ASIC Application Specific Integrated Circuit BOM Bill Of Materials CMC Common Mezzanine Card Comport Communications Port DSP Digital Signal Processor FPDP Front Panel Data Port FPGA Field Programmable Gate Array NA Not Applicable OTP One Time Programmable PC Personal Computer PCB Printed Circuit Board PCl Peripheral Component Interconnect PMC PCI Mezzanine Card PrPMC Processor PMC SDB Sundance Digital Bus SDRAM Synchronous Dynamic Random Access Memory SHB Sundance High speed Bus SMT Sundance Multiprocessor Technology TBD To Be Determined Tl Texas Instruments Page 3 Table of Contents A Rt 7 COV SIMO WE ces O 7 Module FSA RR 7 Related DOCUS etc ME CE 7 Block BISUEOITE os AA Deoa liri xe OE M E v deae Laien eoe TATA AA ENS DE ivi 8 Mechanical Standard 2 sn kiu tieu eiii ec AN ne Ni cna Lie E coe 8 SMT4SS8 SUp POM ii Iia rcc na tee Duda ed cu eee 9 SMT498 lI stalla OT memet 9 QE5060 ns 10 LOCAL UA A aaa 10 Virtex FPGA CONTINUATION RES Ed te 11 Mirtex PA desde AN 11 BU C Rl Wen UA AAA EP RET BE AA AA 1
13. TE 014 xx DP on the SMT407 Side 2 mates with QSE 014 xx DP e Samtec for details RSL Cable Assembly Cable assemblies with QTE connectors on one side and QSE on the other are like the flexible versions of the PCB adapters mentioned above RSL Interface Page 15 The RSL connectors are the fastest FPGA connections available on SMT498 As RSL are based on RocketlO transceiver blocks the speed is limited by the speed grade of FPGA installed RSL speed Gbps 3 125 3 125 Table 2 RSL Speed VS FPGA Speed Grade Based on the above the 14 bi directional links of SMT498 can provide a combined bandwidth of up to 37 5Gbps Refer to the latest SUNDANCE RSL specification for technical information on how it works Local bus http www quicklogic com images QL5064 CD UM pdf Clocks The FPGA is provided with the following clocks Description Speed QL5064 Local bus clock 64MHz SHB clock 100MHz RSL LVDS clock 125MHz Table 3 Board Clocks Miscellaneous l O s The following external interfaces will be provided for user defined functions e PMC P14 64 bits 5V tolerant e 4LEDs e 4 DIP switches Page 16 System ACE SC The SMT498 FPGA PMC module is equipped with In System FPGA configuration solution called System ACE SC As soon as the board is powered up the FPGA is configured from the flash The System ACE SC has a PROM Configuration controller and a Flash For more information on System ACE look at
14. This module obeys the PrPMC Tall module specs for component heights Heights of components on PMC Side 1 see Figure 10 are limited to 4 7mm except in the 1 0 Area where they may extend to the host module surface Components on PMC Side 2 see Figure 10 are limited to 23 5mm minus PCB thickness or about 22 0mm assuming 1 5mm PCB thickness Board Weight The SMT498 weighs approximately 85 grams Standoffs There are two standoffs as part of the module The standoffs are of standard 10mm height in order to support the broadest range of host modules Bezel and I O capability Access to the right angle FPDP port is provided through the front panel For purposes of mechanical rigidity and EMC compliance a customised bezel is provided through which the FPDP is accessed Power consumption Due to the close packing of components between PMC Side 1 and the host module power consumption is limited to 4 0W for 10 0mm standoffs this increases to 6 0W for 13 0mm standoffs For Tall PrPMC modules an additional cooling method such as a heat sink and fan should be considered if the total module power exceeds 25W Page 20 The following information shall be provided on the PMC card a 5V current drawn peak and average a 3 3V current drawn peak and average Note While it may appear that a stacking height of 13 0mm is desirable some hosts may not accept this Grounding Per section 4 14 of IEEE 1386 2001 Conduction Cooling As the
15. end fou 6d se PMCRSVD 6 Table 4 PMC P11 P12 Interface P13 P14 Pin Signal name Signal Pin Pin Signal name Signal name Pin name Page 23 ws he jo jo 4 eme me ao o Ta Jeno joe 4 so jo 45 jos poss 4 CC CC s pos fo s 4o jo s s s s sslPormsvo pormsvo ej slo Jo s 3 Table 5 PMC P13 P14 Interface SHBs The SHB signals have been named to match 2 16 bit SDB interfaces or Hw SHB interface pinout according to the SUNDANCE SHB specification Half Word configuration SMT498 will be equipped with 4 SHBs Two SHBs will be wired to the FPGA to support LVDS number number ET CS CON ET Sie seen CS EC i Hw QSH Pin QSH Pin Hw Page 24 Sa SHBxUSER1 2 4 USE SHBxUSER1 2 6 e 20 30 SHBxUSER1 7 8 SHBxUSER1 2 4 35 SHBxUSER1 3 9 0 SHBxUSER1 3 22 34 SHBxUSER1 3 1 2 4 CI ae ET e eoo seon s e ET ET e e Horto suoi a Jo seon sumo s A NETO ra q Table 6 SHB Interface Due to height constraints of components on the PMC module vertical SHB cables will not be possible Luckily there is a right angle cable available htto www precisionint com tdibrsb images drawings D043850NNNLLLDD20 pdf Page 25 RSL Header Headers are per RSL Spec RSL Side 1 Pinout LVDS only s mae mue s rant mw s s mam mue w Dr pem mam EE Table 7 RSL Side 1 Pinout RS
16. ering Information FPGA Block Diagram oi BUS QuickLogic Interface Figure 4 Default FPGA Configuration Configuration The FPGA can be configured in three different ways Loading the FPGA on power up from flash on the board using System ACE SC Using the SMT6041 498 utility to load the FPGA over the PCI bus Using the on board JTAG header and Xilinx JTAG programming tools See the Appendix for full details Memory Two banks of DDR SDRAM are attached directly to the FPGA for storage of incoming data Each bank consists of two 133 MHz DDR SDRAM components Micron MT46V32M16FN or equivalent providing a total of 128 MB of storage capacity on the module Page 12 SHBs SHB Connectors The SMT498 includes five 60 pin connectors to provide SHB communication to the outside world All 60 pins of each SHB connector are routed to the FPGA Figure 5 SHB Connector Features High speed socket strip QSH 030 01 L D A K on the SMT498 mates with QTH 030 01 L D A K QTH are used for cable assembly or PCB connecting 2 PMCs Centreline 0 5mm 0 0197 QSH Connector An adapter is available for Agilent probes for the 16760A Logic Analyser The 2 probes supported are the E5378A 100 pin Single ended Probe and the E5386A Half Channel Adapter with E5378A The SMT498 can include five Sundance High speed Bus SHB interfaces three on PMC Side 1 and two on PMC Side 2 They are connected directly to the FP
17. logic designs loaded in the Virtex FPGA CS 3 0 Virtex FPGA Config User QL5064 Defined 64 Bit 66 MHz o 2 em O a Local Bus User Defined Figure 3 QL5064 Connection More information about the Local bus interface and protocols can be obtained from QuickLogic at http www quicklogic com images QL5064 CD UM pdf Page 10 Virtex FPGA configuration Programming of the Virtex FPGA can be achieved over the PCI bus using the SelectMAP interface This interface is 8 bits wide and runs at the full speed of the Local bus By simply writing a stream of configuration bytes to the location at CS 0 the FPGA can be programmed An example of this is provided in the SMT6041 498 software package available from SUNDANCE Virtex FPGA design Once the FPGA has been programmed the user may then communicate with the design by means of CS regions 1 2 and 3 12 address lines allow for a total addressable space of 4kB per CS region Accesses to these regions may be up to 64 bits wide An example of this is provided in the SMT6041 498 software package available from SUNDANCE Page 11 Virtex II FPGA The module can be fitted with an XC2VP70 or XC2VP100 FPGA Only flip chip FF1152 package will fit on this board The choice of FPGA will be price performance driven This Xilinx Virtex II Pro is responsible for the provision of 5 SHBs 2 Comports via the SHB user lO pins a PCI Local bus interface and 14 RSLs see Ord
18. ord Interface 16 bit SHB Interface The SHB connectors provide connections to the external world You can implement your own interface to transfer data over using these connectors but if you want to communicate with other Sundance modules you can implement a Half Word Hw interface sitting on 25 pins of an SHB connector The SHBs are parallel communication links for synchronous transmission An SHB interface is derived from the SDB interface which is a 16 bit wide synchronous communication interface SUNDANCE SDB specification The differences are e The SHB interface can be made Byte 8 bits Half Word 16 bits or Word 32 bits wide e The transfer rate can be increased thanks to better quality interconnect As an example let us consider the Half Word Hw SHB interface You can implement 2 x 16 bit SHB interfaces per SHB connector and have some spare signals for User defined functions no differential lines are needed thanks to our SHB cable assembly described in SHB Cable Assembly You must refer to the latest SUNDANCE SDB specification for technical information on how it works Page 14 RSLs RSL Connector The SMT498 includes two 28 pin 7 pair RSL connectors 28 pins 7 pairs of each RSL connector 52 total are routed to the FPGA Am E E L 07 Figure 7 RSL Bottom Connector Features e High speed socket strip QSE 014 xx DP on the SMT407 Side 1 mates with QTE 014 xx DP e High speed socket strip Q
19. ould be consistent with the signaling standard of the PCI host bus 12V and 12V are optional and may be supplied to the PMC connectors as per PMC specifications Contained on the module are linear regulators for the FPGA VCCAUX and FPGA RocketlO A DC DC converter supplies the core voltage for the FPGA and DSPs DC DC converter An International Rectifier P1201 Power Block is used to supply the 1 5V core voltage to the FPGA The current limits are configured for 10A and 5A respectively The DC DC converter is powered from the 5V supply Linear Voltage regulator The FPGA VCCAUX and FPGA RocketlO voltages are supplied through linear voltage regulators drawn from 3 3V Page 18 Daughter Module SMT498 has been designed to incorporate the option for a daughter module that can interface to the FPGA and provide external I O functions SMT498 has one location for a daughter module The daughter module interfaces to SMT498 via SHBE therefore this SHB will not be available when the daughter module is installed Page 19 PMC Standard Voltage keying The QuickLogic 5064 bridge is both 3 3V and 5V compliant Both keying holes are provided Connectors According to IEEE 1386 1 2001 connectors Pn1 through Pn3 are provided for 64 bit PCI connectivity Additionally connector Pn4 is provided for 64 bits of user defined O Given that SMT498 is a single size card these connectors are referenced from P11 through P14 Component heights
20. re initialize the JTAG chain this will show two devices as shown in the figure below G Untitled Configuration Mode iMPACT File Edit View Mode Operations Output Debug Help D oc H Ol X Fr m is ERN Boundary Scan Slaye Serial SelectMAP Desktop Configuration Right click device to select operations TDI xc2vp100 xccacemb4sc led_flash bit test mpm TDO The first device will be the XC2VP100 and the second device will be XCCACEM64 SC this is the System ACE chip that allows the bitstream to be loaded into the flash via JTAG Assign the MPM file Generation of the MPM file is given at the end to the System ACE chip and program it To check the configuration of the VP100 via the Flash toggle the switch 4 of S3 this will reset the system ACE and configure the FPGA from the Flash You will see the done pin LED D5 which is not populated on the prototype of the Target FPGA go low This confirms the FPGA is configured and you will see the status LED s D12 D13 lit From now onwards as soon as the board is powered up the VP100 will be configured from Flash Note In this mode the VP100 cannot be configured directly via the JTAG Page 33 Status Bit Encoding Status bits 3 0 D14 D13 D12 D11 Status Definition 1 1 1 1 System busy Cannot process JTAG commands Successful slave serial or select map configuration CFG DONE High System Busy Configuration Error CFG DONE did
21. rect xilinx com bvdocs publications ds088 pdf Page 7 Block Diagram The following diagram shows the block diagram of the SMT498 JTAG D In JTAG D Out Figure 1 Block diagram of the SMT498 Mechanical Standard PMC is a variant of CMC that uses PCI to communicate over the backplane The IEEE CMC standard describes both single and double size mezzanine cards SMT498 will be a single size card SIGNAL VOLTAGE Y KEYHOLE 77 CONNECTOR j STANDOFF SINGLE CMC Figure 2 Single Size PMC card from IEEE 1386 2001 Page 8 Dimensions of the single size CMC are 74 0mm wide by 149 0mm deep SMT498 Support The SMT498 is supported by the SMT6041 498 software package available from SUNDANCE Please register on the SUNDANCE Support Forum if not yet registered Then enter your company s forum and you can reguest the SMT6041 498 from there SMT498 Installation Do NOT connect any external TTL 5v signals to the SMT498 I Os which connect directly to the FPGA as the FPGA is NOT 5v tolerant However the lines on connector P14 of the carrier board are made 5V tolerant for some applications You can fit the SMT498 on its own on any PMC compatible carrier board When mated with a carrier board such as Twin Industries Xtend1000 it may then be plugged into a host computer e g Windows PC Please follow these steps to install the SMT498 module on a Host system 1 Remove the carrier board f
22. rom the host system 2 Place the SMT498 module on a PMC site See your carrier board User Manual Make sure that the board is firmly seated before screwing the SMT498 to the two main mounting holes Use 10mm M3 Standoffs Digikey 4391K ND and M3 5mm bolts Digikey H742 ND to secure the module to any carrier card 3 Connect the SHB and or RSL cables to the SMT498 if required by your application 4 Install the carrier board in the host system and start the PC 5 The SMT498 can also be used as a standalone FPGA board Connect a molex power connector similar to the one used for the hard disk to provide 5V Note only 5V should be provided do not provide 12 V Page 9 QL5064 The PCI bridge chip from QuickLogic is installed on a SMT498 This device combines a 66MHz 64 bit PCI Master Target ASIC core with a one time programmable OTP FPGA fabric The configuration of the FPGA fabric in the QL5064 is performed prior to manufacturing of the module and cannot be changed by the user Local bus QL5064 provides a bridge between the PCI bus of the host system and the Local bus of the SMT498 This interface will allow software on the host PC to transfer data to and from the other interfaces in this design The interface between the FPGA and PCI bridge is clocked at a speed of 64MHz with a data bus width of 64 bits There are two primary functions of the Local bus on SMT498 1 Configuration of the Virtex FPGA 2 Communication with
23. similar to the type used to power PC hard disk drives Although the standard pinout for these connectors provides 5V and 12V power only 5V will be required to power the module PCB Layout Page 28 The following figures show a preliminary concept of the Side 1 Side 2 and side view of the module Subject to change based on final design details m mum EEE m 550 ao 5 7 4 TT zzm 2 te o E EE EE EE EE EN HE o y la z s zc Hu M B d i o gr e Es M SIS I um TT C J 8 I j as e ji e mum Wa WO a e as as po N a m Hi P ZEIT a nia i9 omm 0 0 5 a M Lees A zo 21 M m i Figure 9 Module Side 1 View Om zio m nu 33 com TT mmm eE H M A T m s EE nu oc os Ego alain E em z EEO LL cael 22 E H Mi nM pal EN 8 9 o aF B jus z d e AA il E Em EN EU See io 7 m ii ll iK T iw EE SEE BI EE SEE S 70 BB BE O em q 0 22 p ES SE Q n c z 7 RN LL HETTER Q Figure 10 Module Side 2 View I O Area ot El LI Tes B Ep Corer Figure 11 Module Side View Safety Page 29 PCI Connx PCB Plane This module presents no hazard to the user EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless i
24. t is installed within an adequate host system Appendix Page 30 Configuring the FPGA The module will be provided with the default VHDL core burned in the Flash On power up the FPGA will be configured with the default bitstream In case the user wants to use his own custom design the following method can be used to configure the FPGA It is assumed that the user is familiar with Xtend1000 PMC carrier card and is aware of the procedure for mounting the PMC on the Xtend1000 and powering it up within a PC environment PCI Mode To configure the FPGA Virtex Il Pro VP 100 using the PCI interface switch switch 4 of S3 to ON position and use the PCI driver for SMT407 498 to download the firmware to the FPGA MVA LY as VCOLECEITG L1 089270 144 m001dATIX I XALHIA sXNIIIX 2 PROM there is a S3 jumper near this PROM S2 which is not shown in this picture Figure 12 Location of the DIP Switches and the PROM Page 31 JTAG Boundary Scan The JTAG header is provided to enable device programming via suitable software See board header table for JTAG pin details Typically this will be Xilinx IMPACT Xilinx IMPACT supports Parallel Cable IV download cable for communication between the PC and FPGA s The JTAG header on the board was designed to mate directly with the 2m ribbon cable provided with the MultiLINX Cable IV BE SURE TO ATTACH THE RIBBON CABLE PROPERLY To directly configure the FPGA
25. via the JTAG remove the jumper near the PROM chip as shown on the picture below Turn switch 1 of S2 to ON position and switch 2 of S2 to OFF position The switch 4 of S3 should be in OFF position for the JTAG to work To initialize the JTAG chain connect the Xilinx Parallel cable to JTAG IN connector JA2 Using the Xilinx impact software initialize the JTAG chain this will show two devices as shown in the figure below S Untitled Configuration Mode iMPACT File Edit View Mode Operations Output Debug Help O o gt E D Ga 36 x CF is SX Boundary Scan Slave Serial SelectMAP Desktop Configuration Right click device to select operations TDI c2wp100 xcvble led flash bit sxev50e_cs144 bsd TDO The first device will be the XC2VP100 and the second device will be XCV50E Assign the intended BIT file to the XC2VP100 and program it This will configure the FPGA directly via the JTAG To test the approaches please use the LED_FLASH bit which is provided Page 32 System ACE SC To configure the FPGA from the Flash on power up install the jumper pin near the PROM chip Turn the switch 1 of S2 to ON position and switch 2 of S2 to OFF position Switch 4 of S3 should be in OFF position for the JTAG to work and switches 1 2 and 3 should be in the ON position To initialize the JTAG chain connect the Xilinx Parallel cable to JTAG IN connector JA2 Using the Xilinx impact softwa
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