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Infineon XC866-1FR, XC866-2FR, XC866-4FR, XC866L-1FR

1. Note Flash memory cell programmed 00 1111 from O to 1 but not from 1 to O Flash memory cells 32 byte write buffers Figure 4 4 D Flash Program User s Manual 4 6 V 0 2 2005 01 Flash Memory V 0 3 Cnfineon XC866 techno ogies Flash Memory 4 4 Operating Modes The Flash operating modes for each bank are shown in Figure 4 5 Sector s Erase Ready to Read Program Call of Call of DFLASH_ERASE routine DFLASH_PROG routine or by BSL or by BSL Power Down System Power Down Figure 4 5 Flash Operating Modes In general the Flash operating modes are controlled by the BSL and D Flash program erase subroutines see Section 4 7 Each Flash bank must be in ready to read mode before the program mode or sector s erase mode can be entered In the ready to read mode the 32 byte write buffers for each Flash bank can be written and the memory cell contents can be read via CPU access In the program mode data in the 32 byte write buffers is programmed into the Flash memory cells of the targeted wordline The operating modes for each Flash bank are enforced by its state machine to ensure the correct sequence of Flash mode transition This avoids inadvertent destruction of the Flash contents with a reasonably low software overhead The state machine also ensures that a Flash bank is blocked no read
2. 10 31 10 3 4 Register Description 10 32 10 3 4 1 Port Input Select Register 10 32 10 3 4 2 Configuration 5 10 33 10 3 4 3 Baud Rate Timer Reload 10 37 10 3 4 4 Transmit and Receive Buffer Register 10 38 11 TIME S okt re eat acted ac io ora 8 81 E Rol OR Pep e Pep ede e ded 11 1 11 1 Timer O and Imeri 2 52 45 3 552 lt oe ws 11 1 11 1 1 Basic Timer Operations 11 1 11 1 2 MIME MOUBS 13d 2a con bine AREER EEE ada e edd 11 2 11 1 2 1 o socere das ands yh P EEEE eH Se Sooo Rese Ses 11 3 11 1 2 2 Mode ecu uaa dues tu EE 11 4 11 1 2 3 eta Ree eee soe eects oe ewan ewan 11 5 11 1 2 4 loi M 11 6 11 1 3 mE PUPPI 11 7 11 1 4 Register Description 11 8 11 2 P cmm 11 13 11 2 1 Auto Reload Mode 11 13 11 2 1 1 Up Down Count Disabled 11 13 User s Manual 4 V 0 2 2005 01 Infineon 76866 technologies Table of Contents Page 11 2 1 2 Up Down Count Enabled 11 14 11 2 2 Capture MOde 11 16 11 2 3 Reg
3. 12 19 12 1 6 1 Sampling of the Hall Pattern 12 19 12 1 6 2 Brushless DC Control 12 20 12 1 7 Interrupt Generation 12 23 12 1 8 Port Connection eae oe ds 9o ds 12 23 12 2 Regisiter 52 d a hates 12 26 12 3 Register Description 12 29 12 3 1 System 5 12 31 12 3 1 1 Port Input Selection 12 31 12 3 2 Timer T12 Related Registers 2 12 35 12 3 3 Timer T13 Related Registers 12 41 12 3 4 Capture Compare Control Registers 12 45 12 3 5 Modulation Control Registers 12 57 12 3 5 1 Global Module 12 57 12 3 5 2 Multi Channel Control 12 65 12 3 6 Interrupt Control 12 77 13 Analog to Digital Converter 13 1 User s Manual l 5 V 0 2 2005 01 techno ogies Table of Contents Page 13 1 Structure Overview 13 2 13 2 Clocking Scheme 13 3 13 2 1 Conversion TIMING 2
4. ISRH Capture Compare Interrupt Status Reset Register High Reset Value 00 7 6 5 4 3 2 1 0 R R R R R R R 0 T13 T13 STR IDLE WHE CHE TRPF PM CM WwW Ww r Ww Field Bits Type Description RT13CM 0 Reset Timer T13 Compare Match Flag 0 No action 1 Bit T13CM in register IS will be reset RT13PM 1 Reset Timer 13 Period Match Flag 0 No action 1 Bit T13PM in register IS will be reset RTRPF 2 Reset Trap Flag 0 No action 1 Bit TRPF in register IS will be reset not taken into account while input CTRAP 0 and TRPPEN 1 RCHE 4 Reset Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be reset RWHE 5 Reset Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be reset RIDLE 6 Ww Reset IDLE Flag 0 No action 1 Bit IDLE in register IS will be reset RSTR 7 Reset STR Flag 0 No action 1 Bit STR in register IS will be reset 0 3 r Reserved Returns 0 if read should be written with 0 User s Manual 12 83 V 0 2 2005 01 6 V 0 4 Infineon technologies XC866 Capture Compare Unit 6 IENL Capture Compare Interrupt Enable Register Low Reset Value 00 7 6 5 4 3 2 1 0 EN EN EN EN EN EN EN EN T12 T12 CC CC CC CC CC CC PM OM 62F 62R 61F 61R 60F 60R rw rw rw rw rw rw rw rw Field Bits Type Description ENCC60R 0 rw Ca
5. 5 1 5 2 Maskable Interrupts 2 4 5 1 5 2 1 Internal 5 5 1 5 2 2 External Interrupts 2 22a a dor RD RR 5 2 5 2 3 Extended Interrupts 5 2 5 3 Interrupt Source and 5 8 5 4 Interrupt Register Description 5 9 5 4 1 Interrupt Enable Registers 5 9 5 4 2 Interrupt Request FIAQS 5 14 5 4 3 Interrupt Priority Registers 5 19 5 4 4 Interr pt Priority oe a a a a eE a a a a a 5 21 5 4 5 Interrupt Request Flags 5 22 5 5 interr pt 5 23 5 6 Interrupt Response Time 5 24 6 Parallel Ports 6 1 6 1 General Port Operation 6 2 6 1 1 General Register 6 5 6 1 1 1 Data Register UR n dan 6 6 6 1 1 2 Direcuon RREGISICN oo 545 ne 6 7 6 1 1 3 Open Drain Control Register 6 7 6 1 1 4 Pull Up Pull Down Device Register 6 8 6 1 1 5 Alternate Input Functions
6. 6 10 6 1 1 6 Alternate Output Functions 6 10 6 2 Register 6 11 6 3 POM Oe m 6 14 6 3 1 a n capp Gea ea 6 14 6 3 2 Register Description 6 16 User s Manual 2 V 0 2 2005 01 techno ogies Table of Contents Page 6 4 td Seiad dhe do ato od aed ore BE EUM 6 19 6 4 1 a gei 6 19 6 4 2 Register Description 6 21 6 5 6 24 6 5 1 FUNCIONS ae a dod gc 6 24 6 5 2 Register Description 6 26 6 6 POM RPM cM 6 28 6 6 1 FUNCIONS ETC ME 6 28 6 6 2 Register Description 6 31 7 Power Supply Reset and Clock Management 7 1 7 1 Power Supply System with Embedded Voltage Regulator 7 1 7 2 Reset Control x uu usd cea cames 7 3 7 2 1 Types of 7 3 7 2 1 1 Power On Reset 7 3 7 2 1 2 Hardware 7 4 7 2 1 3 Watchdog Timer Reset 7 4 7 2 1 4 Power Down Wake Up Reset 7 4 7 2 1 5 Br wnout 7
7. o5 o FV Capture Compare interrupt node 2 Capture Compare interrupt node 3 Y Bit addressable Request is cleared by hardware Figure 5 4 Interrupt Request Sources Part 3 User s Manual 5 6 V 0 2 2005 01 Interrupt System V 0 5 e Infineon technologies XC866 Interrupt System CC60 isco 6 En IENL O 4 s ICC60F o SLi ENCC60F IENL 1 INPL1 INPL O CCe1 IBL2 LENCC6IR IENL 2 gt ICC61F o ISLa LENCC6IF IENL 3 INPL3 INPL2 ICC62R o s4 LENCC62R 4 gt X H Icc62F 18 5 ENL5 5 INPL 4 T12 One match 7120 Ame T12 B 5 ACH Period match ENT12PM r ISL 7 IENL 7 INPH 3 2 T13 T13CM ENT13CM ISH 0 0 gt 1 low T13 Period match MISPM Seek ISH 1 ENR INPH 5 INPH 4 STRAP NTRPF f IENH 2 gt 1 Wrong Ha WHE Event ISH 5 ENWHE y INPH 1 0 Correct Hall ISHA TENHA gt 1 Multi Channel Transfer L ENSTR INPL7 INPL6 IENH 7 CCU6 Interrupt node CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node 3 Figure 5 5 Interrupt Request Sources Part 4 User s Manual 5 7 V 0 2 2005 01 Interrupt System V 0 5 _ Infin
8. 7 6 5 4 3 2 1 0 0 JTAGTDIs JTAGTCK 0 EXINTOIS URRIS r rw rw r rw rw The functions of the shaded bits are not described here Field Bits Description URRIS 0 rw UART Receive Input Select 0 UART Receiver Input RXD 0 is selected 1 UART Receiver Input RXD 1 is selected EXINTOIS 1 rw External Interrupt 0 Input Select 0 External Interrupt Input EXINTO 0 is selected 1 External Interrupt Input EXINTO 1 is selected 0 3 2 r Reserved 7 6 Returns 0 if read should be written with O 1 Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 0 T2 DIS CCU DIS SSC DIS ADC DIS r rw rw rw rw Field Bits Description ADC_DIS 0 rw ADC Disable Request Active high 0 ADC is in normal operation default 1 ADC is disabled SSC DIS 1 rw SSC Disable Request Active high 0 SSC is in normal operation default 1 SSC is disabled User s Manual 8 8 V 0 2 2005 01 SCU V 0 4 technologies Power Saving Modes Field Bits Description CCU DIS 2 rw CCU6 Disable Request Active High 0 CCU6 is in normal operation default 1 CCUG is disabled T2 DIS 3 rw Timer 2 Disable Request Active High 0 Timer 2 is in normal operation default 1 Timer 2 is disabled 0 7 4 r Reserved Returns 0 if read should be written with O ADC GLOBCTR Global Control Register Reset Value 00 7 6 5 4 3 2 1 0 ANON DW CTC 0
9. PISEL Port Input Select Register Reset Value 00 7 6 5 4 3 2 1 0 0 5 SIS MIS r rw rw rw Field Bits Type Description MIS 0 rw Master Mode Receiver Input Select 0 Receiver input is disabled for master mode 1 Receiver input is enabled for master mode SIS 1 rw Slave Mode Receiver Input Select 0 Receiver input is disabled for slave mode 1 Receiver input is enabled for slave mode CIS 2 rw Slave Mode Clock Input Select 0 Clock input is disabled 1 Clock input is enabled 0 7 3 r Reserved Returns 0 if read should be written with 0 User s Manual 10 32 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon technologies XC866 Serial Interfaces 10 3 4 2 Configuration Register The operating mode of the serial channel SSC is controlled by the control register CON This register contains control bits for mode and error check selection and status flags for error identification Depending on bit EN either control functions or status flags and master slave control are enabled CON EN 0 Programming Mode CONL Control Register Low Reset Value 00 7 6 5 4 3 2 1 0 LB PO PH HB BM nw nw rw rw rw Field Bits Type Description BM 3 0 rw Data Width Selection 0000 Reserved Do not use this combination 0001 0111 Transfer Data Width is 2 8 bits lt BM gt 1 Note BM 3 is fixed to 0 HB 4 rw Heading Control 0 Transmit Receive LSB First 1 Transmit
10. technologies Parallel Ports 6 6 Port 3 Port P3 is an 8 bit general purpose bidirectional port The registers of P3 are summarized in Table 6 11 Table 6 11 Port 3 Registers Register Short Name Register Full Name P3 DATA Port 3 Data Register P3 DIR Port 3 Direction Register P3 OD Port 3 Open Drain Control Register P3 PUDSEL Port 3 Pull Up Pull Down Select Register P3 PUDEN Port 3 Pull Up Pull Down Enable Register P3 ALTSELO Port 3 Alternate Select Register 0 P3 ALTSEL1 Port 3 Alternate Select Register 1 6 6 1 Functions Table 6 12 Port 3 Input Output Functions PortPin Input Output Select Connected Signal s From to Module P3 0 Input GPI P3 DATA PO ALT 1 60 0 CCU6 ALT 2 ALT 3 Output GPO P3 DATA PO ALT1 CC60 0 CCU6 ALT2 P3 1 Input GPI P3 DATA P1 ALT 1 ALT 2 ALT 3 Output GPO P3 DATA P1 ALT1 COUT60 0 CCU6 ALT2 User s Manual 6 28 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 Parallel Ports Table 6 12 Port 3 Input Output Functions cont d PortPin Input Output Select Connected Signal s From to Module P3 2 Input GPI P3 DATA P2 ALT 1 CC61 0 CCU6 ALT 2 ALT 3 Output GPO P3 DATA P3 ALT1 CC61 0 CCU6 ALT2 P3 3 Input
11. eed 13 4 13 3 Low Power Mode 13 7 13 4 Functional Description sd bd 13 8 13 4 1 Request Source Arbiter 13 9 13 4 2 Conversion Start Modes 13 10 13 4 3 Channel Conltol u2 neces emere 13 10 13 4 4 Sequential Request Source 13 11 13 4 4 1 13 11 13 4 4 2 Request Source Control 13 12 13 4 5 Parallel Request Source 13 13 13 4 5 1 Uc c ARCUP 13 13 13 4 5 2 Request Source Control 13 13 13 4 5 3 External 13 14 13 4 5 4 Software Control 22 256 13 14 13 4 5 5 bol Gp 13 15 13 4 6 Wait for Read Mode 13 15 13 4 7 Result Generation 13 16 13 4 7 1 OVGIMIOW 2443 5242542552 555656 506 e E E N 13 16 13 4 7 2 Limit CHECKING gt gt arg e ee eee EUR eE 13 17 13 4 7 3 Data Reduction Filt r 2222 e ocu Ice e sg tease bm Rog 13 18 13 4 7 4 Result FIFO Functionality 13 19 13 4 7 5 Result Register View 13 19 13 4 8 de Bede S He eee 13 21 13 4 8 1 Event Interrupts
12. Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description HSYNC 6 4 rw Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields In all modes a trigger by software by writing a 1 to bit SWHC is possible 000 Any edge at one of the inputs CCPOSx x 0 2 triggers the sampling 001 T13 compare match triggers the sampling 010 T13 period match triggers the sampling 011 The Hall sampling triggered by hardware sources is switched off 100 T12 period match while counting up triggers the sampling 101 T12 one match while counting down triggers the sampling 110 AT12 compare match of channel 0 while counting up triggers the sampling 111 AT12 compare match of channel 0 while counting down triggers the sampling DBYP Delay Bypass Bit DBYP determines if the source signal for the sampling of the Hall input pattern selected by HSYNC uses the dead time counter DTCO of timer T12 as additional delay or if the delay is bypassed 0 The delay bypass is not active The dead time counter DTCO generates a delay after the source signal becomes active 1 The delay bypass is active The dead time counter DTCO is not used by the sampling of the Hall pattern Note In the capture modes all edges at the CC6x inputs l
13. 8 a _ 0 0 2 0 a 0 c 1i a E 9 2 9 5 c ao 77 x 5 a 2 J 8 5 29 Figure 10 2 Serial Interface Modes 2 and 3 Timing Diagram User s Manual 10 6 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces 10 1 2 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with bit 9 1 and data bytes with bit 9 0 In these modes 9 data bits are received The 9th data bit goes into RB8 The communication always ends with one stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One of the ways to use this feature in multiprocessor systems is described in the following paragraph When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte that identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive
14. Infineon XC866 techno ogies Analog to Digital Converter 13 7 3 External Trigger Control Register Register ETRCR contains bits that select the external trigger input signal source and enable synchronization of the external trigger input ETRCR External Trigger Control Register Reset Value 00 7 6 5 4 3 2 1 0 SYNEN1 SYNENO ETRSEL1 ETRSELO rw rw rw rw Field Bits Type Description ETRSELx 2 0 rw External Trigger Selection for Request Source x x 0 1 5 3 This bit field defines which external trigger input signal is selected 000 The trigger input is selected 001 The trigger input ETRx1 is selected 111 The trigger input is selected SYNENx 6 7 rw Synchronization Enable x 0 1 0 Synchronizing stage is not in external trigger input REQTRx path 1 Synchronizing stage is in external trigger input REQTRx path User s Manual 13 35 V 0 2 2005 01 ADC V 0 3 Infineon XC866 techno ogies Analog to Digital Converter 13 7 4 Channel Control Registers The channel control registers contain bits that select the targeted result register and control the limit check mechanism Register CHCTRx defines the settings for the input channel x CHCTRx x 0 7 Channel Control Register x Reset Value 00 7 6 5 4 3 2 1 0 0 LCC 0 RESRSEL c Field Bits Type Description RESRSEL 1 0 rw Result Reg
15. 7 6 5 4 1 0 EVINP7 EVINP6 EVINP5 EVINP4 0 EVINP1 EVINPO rw rw rw rw r rw rw Field Bits Type Description EVINPx 1 0 rw Interrupt Node Pointer for Event 0 x 0 1 4 7 7 4 This bit defines which SR lines becomes activated if the event 0 interrupt is generated 0 The line SRO becomes activated 1 The line SR1 becomes activated 3 2 Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 55 V 0 2 2005 01 Infineon technologies XC866 Analog to Digital Converter The bit fields in register LCBR define the four MSB of the compare values boundaries used by the limit checking unit The values defined in bit fields BOUNDO and BOUND1 are concatenated with either four 8 bit conversion or six 10 bit conversion Os at the end to form the final value used for comparison with the converted result For example the reset value of BOUND 1 Bp will translate into BO for an 8 bit comparison and 2 for a 10 bit comparison LCBR Limit Check Boundary Register Reset Value B7 7 5 4 3 2 1 0 BOUND1 BOUNDO IW IW Field Bits Type Description BOUNDx 3 0 rw Boundary for Limit Checking x 0 1 7 4 This bit field defines the four MSB of the compare value used by the limit checking unit The result of the limit check is used for interrupt generation User s Manual ADC V 0 3 13 56 V 0 2 2005 01
16. 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 1 6 Dead time Generation In most cases the switching behavior of the connected power switches is not symmetrical with respect to the times needed to switch on and to switch off A general problem arises if the time taken to switch on is less than the time to switch off the power device This leads to a short circuit in the inverter bridge leg which may damage the entire system In order to solve this problem by hardware the CCU6 contains a programmable dead time counter which delays the passive to active edge of the switching signals the active to passive edge is not delayed T12 Center aligned T12 Edge aligned CC6xST CC6xST DTCx_o Pin CC6x CC6xST AND DTCx CC6xPS 0 PSL 0 Pin COUT6x COUT6xPS 1 CC6xST AND DTCx o PSL 0 Figure 12 5 PWM signals with Dead time Generation Register T12DTC controls the dead time generation for the timer T12 compare channels Each channel can be independently enabled disabled for dead time generation by bit DTEx If enabled the transition from passive state to active state is delayed by the value defined by bit field DTM 8 bit down counter clocked with T12CLK The dead time counter can only be reloaded when it is zero Each of the three channels works independently with its own dead time counter trigger and enable signals The value of bit field DTM is
17. IENO 7 Figure 5 2 Interrupt Request Sources Part 1 User s Manual 5 4 V 0 2 2005 01 Interrupt System V 0 5 e Infineon technologies XC866 Interrupt System Timer 2 Overflow TF2 T2CON 7 x 2 x 24 EXEN2 T2CON 6 T2CON 3 EDGES EL T2MOD 5 o LX EINT2 oH x Fem o P Fi IRCONO 2 EX2 o IEN1 2 l EXINT2 4 5 n o X oH x EXINT3 s IRCONO 3 e EXICONO 6 7 e n X EINT4 ot Xx r4 EXINT4 e IRCONO 4 EXICON1 0 1 5 5 IRCONO 5 HA EXINT5 EXICON1 2 3 o LX 6 oo x IRCONO 6 HA EXINT6 1 4 5 Y Bit addressable 4 Request flag is cleared by hardware Figure 5 3 Interrupt Request Sources Part 2 User s Manual 5 5 V 0 2 2005 01 Interrupt System V 0 5 e Infineon technologies XC866 Interrupt System ADC SRCO ADCSRCO IRCON1 3 ADC SRC1 IRCON1 4 IEN1 0 SSC EIR 1 0 SSC TIR Jj TIR 221 1 1 SSC RIR RIR IRCON1 2 Capture Compare interrupt node 0 Capture Compare interrupt node 1
18. g gt g 0 2 0 1 538 T E A822 A821 A820 z 5 ME ASF Eris UU 802 801 A800 22222222 OF82 0 81 0280 NIFE cies need ATE2 ATE1 ATEO ssepe 0 62 OF61 OF60 g 7 z P S g Los E 3 90 pud c ME ASF A442 A441 A440 82 S OF1F OF02 0 01 OFO0 9 422 A421 M20 OEFF OEE2 OEE1 OEEO A41F 402 401 A400 H H H H 2 A3E1 A3EO 222 0062 0061 0060 25 5 per 0042 0041 0040 ROSE A042 A041 A040 52 eee 0022 0021 0020 o errr 022 A021 A020 2 2 0002 0001 0000 A002 001 A000 WL WL Address Address Figure 4 3 Flash Wordline Addresses User s Manual 4 5 V 0 2 2005 01 Flash Memory V 0 3 Cnfineon XC866 techno ogies Flash Memory A WL address can be calculated as follow 0000 20 x n with 0 lt lt 127 for P Flash 0 4 1 1000 204 x n with 0 lt lt 127 for P Flash 1 4 2 2000 20 x n with 0 lt n lt 127 for P Flash 2 4 3 A000 20 x n with 0 lt n lt 127 for D Flash 4 4 Only one out of all the wordlines in the Flash banks can be programmed at a time The width of each WL is 32 bytes minimum maximum program width Before progr
19. 1 Capture Compare Interrupt Enable IDLE WHE CHE TRPF PM CM Register High Type rw rw rw rw r rw rw rw 9E CCU6_INPL Reset 404 Bit Field INPCHE INPCC62 INPCC61 INPCC60 Capture Compare Interrupt Node Pointer Register Low Type rw rw rw rw User s Manual 3 22 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 7 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 CCU6_INPH Reset 394 Bit Field 0 INPT13 INPT12 INPERR Capture Compare Interrupt Node Pointer Register High Type r rw rw rw A4y CCU6_ISSL Reset 00 Field ST12P 57120 5 62 5 62 5 61 SCC61 SCC60 SCC60 Capture Compare Interrupt Status Set M M F R R F R Register Low Type w w w w Ww w w w A54 CCU6_ISSH Reset 00 Bit Field SSTR SIDLE SWHE SCHE SWHC ST13 ST13 Capture Compare Interrupt Status Set PM CM Register High Type w w w w w w w w CCU6 PSLR Reset 00 BitField PSL63 0 PSL Passive State Level Register Type rwh r rwh CCU6 MCMCTR Reset 00 Bit Field 0 SWSYN 0 SWSEL Multi Channel Mode Control Register Type rw r rw CCU6 TCTR2L Reset 00 Bit Field 0 T13TED T13TEC T13 T12 Timer Cont
20. 60 CC60 MCMPO no modulation COUT60 MCMP1 no modulation 60 T12 no modulation COUTO0 T12 no modulation CC60 MCMPO modulated with T 12 COUT60 MCMP1 modulated with T12 CC60 MCMPO modulated with T12 and 13 COUT60 MCMP1 modulated with T12 and T 13 Figure 12 12 Modulation Control Example for CC60 and COUT60 User s Manual 12 15 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 4 Trap Handling The trap functionality permits the PWM outputs to react to the state of the input pin CTRAP This functionality can be used to switch off the power devices if the trap input becomes active e g as emergency stop During the trap state the selected outputs are forced into the passive state and no active modulation is possible The trap state is entered immediately by hardware if the CTRAP input signal becomes active and the trap function is enabled by bit TRPPEN It can also be entered by software by setting bit TRPF trap input flag thus leading to TRPS 1 trap state indication flag The trap state can be left when the input is inactive by software control and synchronized to the following events is automatically reset after CTRAP becomes inactive if TRPM2 0 must be reset by software after CTRAP becomes inactive if TRPM2 1 synchronized to T12 PWM after TRPF is reset T12 period match in e
21. Cnfineon XC866 techno ogies On Chip Debug Support 14 On Chip Debug Support The On Chip Debug Support OCDS provides the basic functionality required for the software development and debugging of XC800 based systems The OCDS design is based on these principles e use the built in debug functionality of the XC800 Core add a minimum of hardware overhead provide support for most of the operations by a Monitor Program use standard interfaces to communicate with the Host a Debugger Features e Set breakpoints on instruction address and within a specified address range Set breakpoints on internal RAM address e Support unlimited software breakpoints in Flash RAM code region Process external breaks Step through the program code User s Manual 14 1 V 0 2 2005 01 OCDS V 0 2 techno ogies Functional Description 14 1 Functional Description The OCDS functional blocks are shown in Figure 14 1 The Monitor Mode Control MMC block at the center of OCDS system brings together control signals and supports the overall functionality The MMC communicates with the XC800 Core primarily via the Debug Interface and also receives reset and clock signals After processing memory address and control signals from the core the MMC provides proper access to the dedicated extra memories a Monitor ROM holding the code and a Monitor RAM for work data and Monitor stack The OCDS system is accessed through th
22. Figure 12 8 T13 Overview Timer T13 counts according to the same counting and switching rules as timer T12 in edge aligned mode Figure 12 8 shows an overview of Timer T13 12 1 2 1 Timer Configuration Register T13 represents the counting value of timer T13 It can be written only while the timer T13 is stopped Write actions are not taken into account while T13 is running Register T13 can always be read by software Timer T13 supports only edge aligned mode counting up Timer T13 can be started and stopped by using bit T13R by hardware or software User s Manual 12 11 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 Bit T13R is set reset by software by setting bit T13RR or T13RS In single shot mode if bit T13SSC 1 the bit T13R is reset by hardware when T13 reaches its period value Bit fields T13TEC T13TED select the trigger event that will set bit T13R for synchronization of different T12 compare events T13 counter register can be reset to zero by setting bit TT3RES Setting of TT3RES has no impact on bit T13R 12 1 2 2 Compare Mode Register CC63R is the actual compare register for T13 The value stored in CC63R is compared to the counter value of T13 The register CC63R can only be read by software and the modification of the value is done by a shadow register transfer from register CC63SR The corresponding shadow register CC63SR can be read a
23. Table 14 5 HWBPSR 3 0 Selecting Hardware Breakpoint Registers BPSEL Register Selected BPSEL Register Selected Oxxx Reserved 1000 HWBPOL 1001 HWBPOH 1010 HWBP1L 1011 HWBP1H 1100 HWBP2L 1101 HWBP2H 1110 HWBP3L 1111 HWBP3H HWBPDR Hardware Breakpoints Data Register mapped SFR 7 Reset Value 00 7 6 5 4 3 2 1 0 HWBPxx rw User s Manual 14 8 V 0 2 2005 01 OCDS V 0 2 Infineon technologies XC866 On Chip Debug Support Field Bits Type Description HWBPxx 7 0 rw Data to be written into read from a HWBPxx register as currently selected by HWBPSR see Table 14 3 14 3 1 JTAG ID Register This is a read only register located inside the JTAG module and is used to recognize the device s connected to the JTAG interface Its content is shifted out when INSTRUCTION register contains the IDCODE command opcode 04y and the same is also true immediately after reset The JTAG ID register contents for the XC866 Flash devices are given in Table 14 4 Table 14 4 JTAG ID Summary Device Type Device Name JTAG ID Flash XC866L 4FR 1010 0083 XC866 4FR 100 5083 XC866L 2FR 1010 2083 XC866 2FR 1010 1083 User s Manual 14 9 V 0 2 2005 01 OCDS V 0 2 Infineon technologies XC866 15 Index 15 1 Keyword Index Keyword Index This section lists a number of keywords which ref
24. 3 16 3 3 5 5 3 17 3 3 5 6 limer 2 RegisIBIS iuda 0 4556 ee dere SE acd 3 20 3 3 5 7 CCUG Eae SE eR EE ES 3 20 3 3 5 8 SOC IS60IS BIS as toe vip ERR RR Orr erae sand 3 24 3 3 5 9 OCDS Registers 3 25 3 4 Boot ROM Operating Mode 3 26 3 4 1 User IMOUB s de soie oru lets whe 3 26 User s Manual 1 1 V 0 2 2005 01 techno ogies Table of Contents Page 3 4 2 BootStrap Loader 3 27 3 4 3 OCDS MOUB weed ua we om ube ea icd ud 3 27 4 Flash 4 1 4 1 Flash Memory 225225524555 andes age 4 2 4 2 Flash Bank Sectorization 4 3 4 3 Wordline Address 4 5 4 4 Operating Modes 4 7 4 5 Error Detection and Correction 4 8 4 6 In System Programming 4 9 4 7 In Application Programming 4 10 4 7 1 D Flash Programming 4 11 4 7 2 Flash EISSIHE lt 2 gt 23 455 505 255555 ERR PR ES ES 4 13 5 Interrupt System 5 1 5 1 Non maskable Interrupt
25. ALT 2 ALT 3 ANALOG 6 2 7 Input GPI P2 DATA P7 ALT 1 ALT 2 ALT 3 ANALOG AN7 ADC User s Manual 6 25 V 0 2 2005 01 Parallel Ports V 0 3 _ 866 techno ogies Parallel Ports 6 5 2 Register Description P2_DATA Port 2 Data Register Reset Value 00 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 PO r r r r r r r r Field Bits Description Pn n r Port 2 Pin n Data Value n20 7 0 Port 2 pin n data value 0 default 1 Port 2 pin n data value 1 P2 PUDSEL Port 2 Pull Up Pull Down Select Register Reset Value FF 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 nw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 2 Bit n n 0 7 0 Pull down device is selected 1 Pull up device is selected User s Manual 6 26 V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon technologies XC866 Parallel Ports P2 PUDEN Port 2 Pull Up Pull Down Enable Register Reset Value 00 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 nw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 2 Bit n n 0 7 0 Pull up or Pull down device is disabled default 1 Pull up or Pull down device is enabled User s Manual Parallel Ports V 0 3 V 0 2 2005 01
26. techno ogies Parallel Ports 6 1 1 5 Alternate Input Functions The number of alternate functions that uses a pin for input is not limited Each port control logic of an I O pin provides several input paths Digital input value via register Direct digital input value 6 1 1 6 Alternate Output Functions Alternate functions are selected via an output multiplexer This multiplexer can be controlled by the following registers Register Px ALTSELO Register Px ALTSEL1 Selection of alternate functions is defined in registers ALTSELO and ALTSEL1 Px ALTSELn n 0 1 Port x Alternate Select Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 rw rw rw rw nw nw nw rw Function of Bits Px ALTSELO Pn and Px_ALTSEL1 Pn Px ALTSELO Pn Px_ALTSEL1 Pn Function 0 0 Normal GPIO 1 0 Alternate Output 1 0 1 Alternate Output 2 1 1 Reserved Note Set Px_ALTSELO Pn and Px_ALTSEL1 Pn to select only implemented alternate output functions User s Manual 6 10 V 0 2 2005 01 Parallel Ports V 0 3 Cnfineon XC866 techno ogies Parallel Ports 6 2 Register Map The Port SFRs are located in the standard memory area RMAP 0 and are organized into 4 pages The PORT_PAGE register is located at address 2 It contains the page value and page control information PORT_PAGE Page Register for PORT Reset Val
27. 0 3 r Reserved Returns 0 if read should be written with 0 User s Manual 13 29 V 0 2 2005 01 ADC V 0 3 Infineon technologies XC866 Analog to Digital Converter All ADC register names described in the following sections will be referenced in other chapters of this document with the module name prefix e g ADC GLOBCTR The addresses of the SFRs are listed in Table 13 3 and Table 13 4 Table 13 3 SFR Address List for Pages 0 2 Address Page 0 Page 1 Page 2 CAy GLOBCTR CHCTRO RESROL CBy GLOBSTR CHCTR1 RESROH CCy PRAR CHCTR2 RESR1L CDy LCBR CHCTR3 RESR1H CHCTR4 RESR2L CFy ETRCR CHCTR5 RESR2H D24 CHCTR6 RESR3L CHCTR7 RESR3H Table 13 44 SFR Address List for Pages 3 6 Address Page 3 Page 4 Page 5 Page 6 CAy RESRAOL RCRO CHINFR CRCR1 CBy RESRAOH RCR1 CHINCR CRPR1 CC RESRA1L RCR2 CHINSR CRMR1 CDy RESRA1H RCR3 CHINPR QMRO CEy RESRA2L VFCR EVINFR QSRO CFy RESRA2H EVINCR QORO D24 RESRA3L EVINSR QBURO QINRO RESRA3H EVINPR User s Manual 13 30 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter 13 7 Register Description 13 7 1 General Function Registers Register GLOBCTR contains bits that control the analog converter and the conversion delay GLOBCTR Global Contro
28. 1 2 Configure global control functions Select conversion width GLOBCTR DW Select analog clock fapc divider ratio GLOBCTR CTC Configure arbitration control functions Select request source x priority PRAR PRIOx conversion start mode PRAR CSMx Enable arbitration slot x PRAR ASENXx Select arbitration mode PRAR ARBM Configure channel control information Select channel x limit check control CHCTRx LCC target result register CHCTRx RESRSEL Select sample time for all channels INPCRO STC Configure result control information Enable disable result register x data reduction RCRx DRCTR event interrupt RCRx IEN FIFO functionality RCRx FEN wait for read mode RCRx WFR valid flag reset by read access RCRx VFCTR Configure interrupt control functions Select channel x interrupt node pointer CHINPR CHINPx Select event x interrupt node pointer CHINPR EVINFx Configure limit check boundaries Select limit check boundaries for all channels LCBR BOUNDO LCBR BOUND1 Configure external trigger control functions Select source x external trigger input ETRCR ETRSELx Enable disable source x external trigger input synchronization ETRCR SYNENx Setup sequential source Enable conversion request QMRO ENGT Enable disable external trigger QMRO ENTR Select trigger mode QMRO TRMD User s Manual 13 26 V 0 2 2005 01 ADC V 0 3
29. User s Manual Parallel Ports V 0 3 6 17 V 0 2 2005 01 Infineon technologies XC866 Parallel Ports PO PUDEN Port 0 Pull Up Pull Down Enable Register Reset Value C4 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 1 rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 0 Bit n 0 5 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled default 0 7 6 r Reserved Returns 0 if read should be written with 0 PO ALTSELn n 0 1 Port 0 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 1 rw nw rw rw rw rw Table 6 5 Function of Bits PO ALTSELO Pn and PO ALTSEL1 Pn PO ALTSELO Pn PO ALTSEL1 Pn Function 0 0 Normal GPIO 1 0 Alternate Output 1 0 1 Alternate Output 2 1 1 Reserved User s Manual 6 18 V 0 2 2005 01 Parallel Ports V 0 3 Cnfineon XC866 techno ogies Parallel Ports 6 4 Port 1 Port P1 is a 5 bit general purpose bidirectional port The registers of P1 are summarized in Table 6 6 Table 6 6 Port 1 Registers Register Short Name Register Full Name P1 DATA Port 1 Data Register P1 DIR Port 1 Direction Register P1 OD Port 1 Open Drain Control Register P1 PUDSEL Port 1 Pull Up Pull Down Select Register P1 PUDEN Port 1 Pull Up Pull Down Enabl
30. 0 1 Wait for Start In this mode the current conversion is completed normally The pending conversion request will be treated immediately after the conversion is completed The conversion start takes place as soon as possible e Cancel Inject Repeat In this mode the current conversion is aborted immediately if a new request with a higher priority has been found The new conversion is started as soon as possible after the abort action The aborted conversion request is restored in the request source that has requested the aborted conversion As a result it takes part in the next arbitration round The priority of an active request source including pending or active conversion must not be changed by software The abort will not be accepted during the last 3 clock cycles of a running conversion Refer to Section 13 7 2 for register description relating to conversion start control 13 4 3 Channel Control Each channel has its own control information that defines the target result register for the conversion result see Section 13 7 4 The only control information that is common to all channels is the sampling time defined by the input class register see Section 13 7 5 User s Manual 13 10 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter 13 4 4 Sequential Request Source 13 4 4 1 Overview The sequential request source at arbitration slot 0 requests one conversion after another
31. 1 0 2 9 bit UART fixed baud rate 32 or fpc 64 1 1 Mode 3 9 bit UART variable baud rate 10 1 4 Baud Rate Generation There are several ways to generate the baud rate clock for the serial port depending on the mode in which it is operating Baud rate clock and baud rate must be distinguished from each other The serial interface requires a clock rate that is 16 times the baud rate for internal synchronization Therefore the baud rate generators must provide a baud rate clock to the serial interface where it is divided by 16 to obtain the actual baud rate The abbreviation fpc refers to the input clock frequency In mode 2 the baud rate is either fpc 64 or 32 depending on the setting of PCON SMOD which acts as a Double Baud Rate selector However when the serial port is being used in either mode 1 or mode 3 it has a variable baud rate principally set by the underflow rate of the dedicated baud rate generator User s Manual 10 9 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces The fixed baud rate of the serial port in mode 2 is controlled by bit SMOD in SFR PCON as shown below The variable baud rate supplied by the dedicated baud rate generator for modes 1 and 3 is unaffected by this bit PCON Power Control Register Reset Value 00 7 6 5 4 3 2 1 0 SMOD 0 GF
32. 4 Analog Input 4 2 5 22 Hi Z 5 Analog Input 5 P2 6 23 Hi Z 6 Analog Input 6 P2 7 26 Hi Z AN7 Analog Input 7 User s Manual 1 9 V 0 2 2005 01 Intro V 0 3 Infineon technologies XC866 Introduction Table 1 2 Pin Definitions and Functions cont d Symbol Pin Type Reset Function Number State P3 3 Port 3 is a bidirectional general purpose port It can be used as alternate functions for the CCU6 P3 0 32 Hi Z 60 0 Input Output of Capture Compare channel 0 P3 1 33 Hi Z COUT60 0 Output of Capture Compare channel 0 P3 2 34 Hi Z 61 0 Input Output of Capture Compare channel 1 P3 3 35 Hi Z COUT61_0 Output of Capture Compare channel 1 P3 4 36 Hi Z 62 0 Input Output of Capture Compare channel 2 P3 5 37 Hi Z COUT62 0 Output of Capture Compare channel 2 P3 6 30 PD CCU6 Trap Input RSTOUT Reset output indication for internal reset condition in microcontroller P3 7 31 Hi Z EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture Compare channel 3 User s Manual Intro 0 3 1 10 0 2 2005 01 _ Infineon technologies XC866 Introduction Table 1 2 Pin Definitions and Functions cont d Symbol Pin Type Reset Function Number State Vppp 18 Port Supply 3 0 5 5 V Vssp 19 Port Ground Vppc 8 Core Supply Output 2 5 V Vssc 7
33. 7 6 5 4 3 2 1 0 ECCERRADDR 7 0 rh FEAH Flash Error Address Register High Reset Value 00 7 6 5 4 3 2 1 0 ECCERRADDR 15 8 rh Field Bits Type Description ECCERRADDR 7 0 of rh ECC Error Address Value FEAL 7 0 of FEAH User s Manual 4 8 V 0 2 2005 01 Flash Memory V 0 3 techno ogies Flash Memory 4 6 In System Programming In System Programming ISP of the Flash memory is supported via the Boot ROM based BootStrap Loader BSL allowing a blank microcontroller device mounted onto an application board to be programmed with the user code and also previously programmed device to be erased then reprogrammed without removal from the board This feature offers ease of use and versatility for the embedded design ISP is supported through the microcontrollers serial interface UART which is connected to the personal computer host via the commonly available RS 232 serial cable The BSL mode is selected if the latched values of the MBC and TMS pins are 0 after power on or hardware reset The BSL routine will first perform an automatic synchronization with the transfer speed baud rate of the serial communication partner personal computer host Communication between the BSL routine and the host is done via a simple transfer protocol information is sent from the host to the microcontroller in blocks with specified block structure and the BSL routine acknowledges the received data by returning a singl
34. Core Supply Ground Varep 25 ADC Reference Voltage VacND 24 ADC Reference Ground XTAL1 6 Hi Z External Oscillator Input backup for on chip OSC normally NC XTAL2 5 Hi Z Oscillator Output backup for on chip OSC normally NC TMS 11 Test Mode Select RESET 38 Reset Input for PG TSSOP 38 package MBC 1 Monitor BootStrap Loader Control User s Manual Intro V 0 3 1 11 V 0 2 2005 01 _ Infineon XC866 techno ogies Introduction 1 4 Textual Convention This document uses the following textual conventions for named components of the XC866 Functional units of the XC866 are shown in upper case For example The SSC can be used to communicate with shift registers Pins using negative logic are indicated by an overbar For example A reset input pin RESET is provided for the hardware reset Bit fields and bits in registers are generally referenced as Register name Bit field or Register name Bit Most of the register names contain a module name prefix separated by an underscore character _ from the actual register name In the example of 55 SSC is the module name prefix and CON is the actual register name Variables that are used to represent sets of processing units or registers appear in mixed case type For example the register name CC6xR refers to multiple registers with the variable
35. User s Manual 10 10 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces The baud rate of the baud rate generator depends on the following bits and register values Input clock fpc Value of register BCON BRPRE e Value of the 8 bit reload register BG 8 Bit Baudrate Timer f DIV R Figure 10 3 Baud rate Generator Circuitry The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization Therefore the baud rate generators must provide a baud rate clock to the serial interface which is divided by 16 and results in the actual baud rate The following formula includes the factor and calculates the final baud rate 16 x PRE x BG 1 The value of PRE prescaler is chosen by the bit BCON BRPRE BG represents the contents of the reload register BG BR VALUE which is taken as unsigned 8 bit integer The maximum baud rate that can be achieved for a module clock of 26 7 MHz is 1 67 MBaud Table 10 2 lists various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baud rate Table 10 2 Typical Baud Rates of UART baud rate Baud rate PRE Reload Value Deviation Error 26 7 MHz 19 2 kBaud 1 BRPRE 000 87 57 0 22 96 9600 Baud 1 BRPRE 000 174 AEQ 0 22 96 4800 Baud 2 BRPRE 001 174 AEQ 0 22 96 2400 Baud
36. 2 82 2 81 2F80 ning AF82 AF81 AF80 NENNEN 2F62 2F61 2F6 Q 2222222 AF62 AF61 AF60 org 868 i 868 N 8 TS 2 8 ES 5 2 1 2 02 2 01 2200 AFIF AF02 AFO1 0 0 e 2EFF 2 2 2EE1 2EEO AEFF AEE2 AEE1 AEEQ x H 5 oro ES 275 AEGF AE82 AE81 80 EE UNIT 2062 2061 2060 8 2 AETF AE62 1 AEG0 9 2042 2041 2040 59 2a 2 27277722777 2022 2021 2020 8 8 8 e 2002 2001 2000 pucr 02 01 AE00 cT ci ADE2 ADE1 ADEO 1FE2 1 1 1FEO oc A S4 8 g9 d Ble i g N Oe T M 1 82 1F81 1F80 ADIF cette tees AD02 001 ADOO 162 1561 fF R cR TT 2 ACE1 ACEO p i i 2 292 os 382 5 5 e REA 5 1FAF 1F02 1 01 1200 28 ir 1EFF 1EE2 1 1 1EE0 02 AC01 ACOO 2 1 ao e g H d E 5525 amp US I LT Ti 321 BASF A22 AA21 20 525 ee AA02 AAO 00 Misses es A9E2 9 A9EO 1002 1001 1000
37. 7 6 5 0 1 P1 Alternate Select 0 Register Type rw rw rw r rw rw 914 P1_ALTSEL1 Reset 00 Bit Field D P6 P5 0 P1 PO P1 Alternate Select 1 Register Type rw rw rw r rw rw P3 ALTSELO Reset 004 Bit Field 7 6 5 2 1 P3 Alternate Select 0 Register Type rw rw rw rw rw rw rw rw P3 ALTSEL1 Reset 00 Bit Field 7 6 P5 P4 P3 P2 P1 PO P3 Alternate Select 1 Register Type rw rw rw rw rw rw rw rw RMAP 0 Page 3 804 PO OD Reset 00 Bit Field 0 P5 2 1 PO Open Drain Control Register Type r rw rw rw rw rw rw 90 1 Reset 00 Bit Field P7 P6 P5 0 P1 PO P1 Open Drain Control Register Type rw rw rw r rw rw P3 OD Reset 00 Bit Field P7 P6 P5 P4 P3 P2 P1 PO P3 Open Drain Control Register Type rw rw rw rw rw rw rw rw 3 3 5 5 ADC Registers The ADC SFRs be accessed in the standard memory area RMAP 0 Table 3 5 ADC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 Dih ADC_PAGE Reset 00 Bit Field OP STNR 0 PAGE Page Register for ADC Type w w r rw RMAP 0 Page 0 ADC GLOBCTR Reset 00 Bit Field DW CTC 0 Global Control Register Type rw rw rw r ADC GLOBSTR Reset 00 Bit Field 0 CHNR 0 SAM BUSY Global Status Register PLE Type r rh r rh rh CC ADC_PRAR Reset 00 Bit Field ASE
38. COUT62 CCPOS2 Inputs Outputs Outputs 60 CC61 62 COUT6 COUTE6 COUT6 050 51 052 0 1 2 Rotate left 1 0 1 inactive inactive active inactive active inactive 0 phase shift 4 0 0 inactive inactive active active inactive inactive 1 1 0 inactive active inactive active inactive inactive 0 1 0 inactive active inactive inactive inactive active 0 1 1 active inactive inactive inactive inactive active 0 0 1 active inactive inactive inactive active inactive Rotate right 1 1 0 active inactive inactive inactive active inactive 1 0 0 active inactive inactive inactive inactive active 1 0 1 inactive active inactive inactive inactive active 0 0 1 inactive active inactive active inactive inactive 0 1 1 inactive inactive active active inactive inactive 0 1 0 inactive inactive active inactive active inactive Slow down X X X inactive inactive inactive active active active Idle X X X inactive inactive inactive inactive inactive inactive 1 In case the sampled Hall inputs were neither the current nor the expected Hall pattern the bit WHE Wrong Hall Event is set which can also cause an interrupt and set the IDLE mode to clear MCMP modulation outputs are inactive User s Manual 6 V 0 4 12 21 0 2 2005 01 866 Capture Compare Unit 6 technologies Infi
39. Description 0 holds the 8 bit timer value 1 THX holds the higher 8 bit part of the 16 bit timer value 2 holds the 8 bit reload value 3 THO holds the 8 bit timer value TH1 is not used User s Manual 11 9 V 0 2 2005 01 Timers V 0 4 Infineon technologies XC866 Timers Register TCON controls the operations of Timer 0 and Timer 1 TCON Timer Control Register Reset Value 00 7 6 5 4 3 2 1 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO nw rw rw rw rw rw rw rw The functions of the shaded bits are not described here Field Bits Description TRO 4 rw Timer 0 Run Control 0 Timer is halted 1 Timer runs TFO 5 rw Timer 0 Overflow Flag Set by hardware when Timer 0 overflows Cleared by hardware when the processor calls the interrupt service routine TR1 6 rw Timer 1 Run Control 0 Timer is halted 1 Timer runs TF1 7 rw Timer 1 Overflow Flag Set by hardware when Timer 12 overflows Cleared by hardware when the processor calls the interrupt service routine 1 Also affects THO if Timer 0 operates in mode 3 2 TF1 is set by THO instead if Timer 0 operates in mode 3 User s Manual Timers V 0 4 11 10 V 0 2 2005 01 techno ogies Timers Register TMOD contains bits that select the operating modes of Timer 0 and Timer 1 TMO
40. EN EE counter EEEE 9 r1 r3 r7 result register x a 1 iconem oe valid flag for result register x E i 5 25 jue M f 5 6 6 murdsx ve Figure 13 10 Data Reduction Flow If DRC is 0 and a new conversion result comes in DRC is reloaded with its reload value defined by bit DRCTR in the result control register and the value of 0 is added to the conversion result instead of the previous result register content Then the complete result is stored in the selected result register If the reload value is 0 data reduction filter disabled accumulation is done over one conversion Hence a result event is generated and the valid bit VF for the result register becomes set If the reload value is 1 data reduction filter enabled accumulation is done over two conversions In this case neither a result event is generated nor the valid bit is set User s Manual 13 18 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter If DRC is 1 and a new conversion result comes in the data reduction filter adds the incoming result to the value already stored in the result register and decrements DRC After this addition the complete result is stored in the selected result register The result event is generated and the valid bit becomes set It is possible to have
41. Each pin can also be programmed to activate an internal weak pull up or pull down device Register Px PUDSEL selects whether a pull up or the pull down device is activated while register Px PUDEN enables or disables the pull device To achieve high speed data transfer each I O pin can be switched for direct connection to the various inputs of the peripheral units AltDataln The function of the input line from the pin to the data register Px DATA and to AltDataln is independent of whether the port pin operates as input or output This means that when the pin is in output mode the level of the pin can be read by software via Px DATA or a peripheral can use the pin level as an input This offers additional advantages in an application When the pin is configured as general purpose output the data written to the data register Px DATA by software can be used as input data to an on chip peripheral This enables for example peripheral tests via software without external circuitry Examples for this can be the triggering of a timer count input generating an external interrupt or simulating the incoming serial data stream to a serial port receive input via software User s Manual 6 2 V 0 2 2005 01 Parallel Ports V 0 3 e Infineon technologies XC866 Parallel Ports When the pin is configured for alternate output function the output data that is driven to the pin by a peripheral can be read through software via Px D
42. Processor Architecture Table 2 1 CPU Instruction Timing cont d Mnemonic Hex Code Bytes Number of fcc Cycles XC866 8051 no ws 1 ws INC dir 05 2 2 6 12 INC Ri 06 07 1 2 4 12 DECA 14 1 2 4 12 18 1 1 2 4 12 DEC dir 15 2 2 6 12 DEC Ri 16 17 1 2 4 12 INC DPTR A3 1 4 4 24 MUL AB A4 1 8 8 48 DIV AB 84 1 8 8 48 DAA D4 1 2 4 12 LOGICAL ANL A Rn 58 5F 1 2 4 12 ANL A dir 55 2 2 6 12 ANL A Ri 56 57 1 2 4 12 ANL A data 54 2 2 6 12 ANL dir A 52 2 2 6 12 ANL dir data 53 3 4 10 24 ORL A Rn 48 4F 1 2 4 12 ORL A dir 45 2 2 6 12 ORL A Ri 46 47 1 2 4 12 ORL A data 44 2 2 6 12 ORL dir A 42 2 2 6 12 ORL dir data 43 3 4 10 24 XRL A Rn 68 6F 1 2 4 12 XRL A dir 65 2 2 6 12 XRL A Ri 66 67 1 2 4 12 XRL A data 64 2 2 6 12 XRL dir A 62 2 2 6 12 User s Manual 2 11 V 0 2 2005 01 Processor Architecture V 0 3 Cnfineon XC866 techno ogies Processor Architecture Table 2 1 CPU Instruction Timing cont d Mnemonic Hex Code Bytes Number of fcc Cycles XC866 8051 no ws 1 ws XRL dir data 63 d 4 10 24 CLR A E4 1 2 4 12 CPLA 1 2 4 12 SWAP A C4 1 2 4 12 RLA 23 1 2 4 12 RLCA 33 1 2 4 12 RRA 03 1 2 4 12 13 1 2 4 12 DATA TRANSFER MOV A Rn E8 EF 1 2 4 12 MOV A dir E5 2
43. Queue Mode Register Reset Value 00 7 6 5 4 3 2 1 0 CEV TREV FLUSH CLRV TRMD ENTR 0 Ww Ww Ww Ww rw rw r rw Field Bits Type Description ENGT 0 rw Enable Gate This bit enables the gating functionality for the request source 0 The gating line is permanently 0 The source is switched off 1 The gating line is permanently 1 The source is switched on ENTR 2 rw Enable External Trigger This bit enables the external trigger possibility If enabled bit EV is set if a rising edge is detected at the external trigger REQTR when at least one V bit is set in register QORO or QBURO 0 The external trigger is disabled 1 The external trigger is enabled TRMD 3 rw Trigger Mode This bit defines which trigger mode is selected In trigger mode 0 the output lines REQPND and REQCHNRV can become active at the same time In trigger mode 1 the signal REQPND can become active before REQCHNRV 0 Trigger mode 0 is selected 1 Trigger mode 1 is selected CLRV 4 Ww Clear V Bits 0 No action 1 The bit V in register QORO or QBURO is reset If QBURO V 1 then QBURO V is reset If QBURO V 0 then QORO V is reset User s Manual 13 38 V 0 2 2005 01 ADC V 0 3 _ Infineon technologies XC866 Analog to Digital Converter Field Bits Type Description FLUSH 5 w Flush Queue 0 No action 1 All bits V in the queue registers and bit EV are reset The queue contains no more va
44. Register 1 Type rwh rwh rwh rwh r User s Manual 3 19 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 5 ADC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 CCy ADC CRMR1 Reset 00 Bit Field 0 LDEV CLR SCAN ENSI ENTR ENGT Conversion Request Mode Register 1 PND Type r w w rw rw rw rw CDy ADC QMRO Reset 00 Bit Field CEV TREV FLUSH CLRV TRMD ENTR ENGT Queue Mode Register 0 Type w w w w rw rw rw CEy ADC QSRO Reset 20 Bit Field 0 EMPTY EV 0 Queue Status Register 0 Type r rh rh r ADC_QORO Reset 00 Bit Field EXTR ENSI RF V 0 REQCHNR Queue 0 Register 0 Type rh rh rh rh rh D24 ADC QBURO Reset 00 Bit Field EXTR ENSI RF V 0 REQCHNR Queue Backup Register 0 Type rh rh rh rh rh D24 ADC QINRO Reset 00 Bit Field EXTR ENSI RF 0 REQCHNR Queue Input Register 0 Type w w w r w 3 3 5 6 Timer 2 Registers The Timer 2 SFRs can be accessed in the standard memory area RMAP 0 Table 3 6 Timer 2 Register Overview Addr Register Bit 7 6 5 4 3 2 1 0 2 2 Reset 00 Bit Field TF2 EXF2 0 2 TR2 C T2 CP Timer 2 Control Register RL2 Type rwh rwh r rw rwh rw rw C14 T2_T2MOD Reset 00 Bit Field 0 EDGE PREN T2PRE DCEN Timer 2 Mode Registe
45. STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10p the contents of PAGE are saved in STx before being overwritten with the new value If OP 11g the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STOis selected 01 STl1is selected 10 ST2is selected 11 ST3 is selected User s Manual 12 26 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description OP 7 6 Ww Operation OX 10 11 Manual page mode The value of STNR is ignored and PAGE is directly written New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR Reserved Returns 0 if read should be written with 0 User s Manual 6 V 0 4 12 27 0 2 2005 01 Infineon technologies XC866 Capture Compare Unit 6 All CCUG register names described in the following sections will be referenced in other chapters of this
46. Slow down mode 7 13 8 2 User s Manual Keyword Index Software breakpoints 14 5 Break before make 14 5 Source priority 13 9 Special Function Register area 3 1 Stack pointer 2 4 Synchronization phase 13 5 Synchronous serial interface 10 19 Data width 10 20 Error detection 10 27 Baud rate error 10 28 Phase error 10 28 Receive error 10 28 Transmit error 10 29 Interrupts 10 27 Master mode 10 19 Operating mode 10 20 Right aligned 10 20 Slave mode 10 19 T Timer 0 and Timer 1 11 1 11 12 External control 11 2 Mode 0 13 bit timer 11 3 Mode 1 16 bit timer 11 4 Mode 2 8 bit automatic reload timer 11 5 Mode 3 two 8 bit timers 11 6 Timer operations 11 1 Timer overflow 11 1 Timer 2 11 13 11 21 Auto Reload mode 11 16 Capture mode 11 16 Up Down Count Disabled 11 13 Up Down Count Enabled 11 14 Timer T12 12 3 Capture mode 12 9 Center aligned mode 12 4 Compare mode 12 6 Dead time 12 8 Duty cycle 12 7 Edge aligned mode 12 4 Hysteresis like control mode 12 10 Shadow transfer 12 3 15 4 V 0 2 2005 01 _ Infineon technologies XC866 Single shot mode 12 9 Three phase PWM 12 1 Timer T13 12 11 Compare mode 12 12 Shadow transfer 12 11 Single shot mode 12 12 Total conversion time 13 6 Trap handling 12 16 Tristate 6 8 U UART 10 2 10 13 Interrupt requests 10 5 Mode 1 8 bit UART 10 2 Mode 2 9 bit UART 10 5 Mode 3 9 bit UART 10 5 V VCO bypass 7 12 W Wait for read mode 13 15 Wait for Start 13
47. T13CVL rwh T13H Timer T13 Counter Register High Reset Value 00 7 6 5 4 3 2 1 0 T13CVH rwh Field Bits Type Description T13CV 7 0 of rwh Timer T13 Counter Value T13L This register represents the 16 bit counter value of 7 0 of timer T13 T13H Note Once timer T13 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays User s Manual 12 41 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 T13PRL Timer T13 Period Register Low Reset Value 00 7 6 5 4 3 2 1 0 T13PVL rwh T13PRH Timer 13 Period Register High Reset Value 00 7 6 5 4 3 2 1 0 T13PVH rwh Field Bits Type Description T13PV 7 0 of rwh 13 Period Value T13PRL The value T13PV defines the counter value for T13 7 0 of which leads to a period match On reaching this T13PRH value the timer T13 is set to zero User s Manual 12 42 V 0 2 2005 01 CCUG V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 CC63RL Capture Compare Register for Channel CC63 Low Reset Value 00 7 6 5 4 3 2 1 0 CC63VL r CC63RH Capture Compare Register for Channel CC63 High Reset Value 00 7 6 5 4 3 2 1 0 CC63VH rh Field Bits Type Description CC63V 7 0 of rh Channel CC63 Compare Value CC63RL The bit fiel
48. Type r rwh rwh rw rw rwh rw 5 1 Reset 00 Bit Field 0 T2 DIS CCU SSC ADC Power Mode Control Register 1 _DIS DIS DIS Type r rw rw rw rw B6y OSC_CON Reset 08 Bit Field 0 OSC XPD OSC ORD OSCR OSC Control Register PD 55 5 r rw rw rw rwh rw B7y PLL_CON Reset 20 Bit Field NDIV VCO OSC LOCK PLL Control Register BYP DISC Type rw rw rw rwh rh BAY CMCON Reset 00 Bit Field 0 CLKREL Clock Control Register Type r rw BBy PASSWD Reset 07 Bit Field PASS PROTE MODE Password Register CT_S Type wh rh rw BC FEAL Reset 00 Bit Field ECCERRADDR 7 0 Flash Error Address Register Low Type rh BDy FEAH Reset 00 Bit Field ECCERRADDR 15 8 Flash Error Address Register High Type rh User s Manual 3 15 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization 3 3 5 3 WDT Registers The WDT SFRs be accessed in the mapped memory area RMAP 1 Table 3 3 WDT Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 1 WDTCON Reset 00 Bit Field 0 WINB WDT 0 WDT WDT WDT Watchdog Timer Control Register EN PR EN RS IN Type r rw rh r rw rwh rw BCy WDTREL Reset 00 Bit Field WDTREL Watchdog Timer Reload Register Type rw BDy WDTWINB Reset 00 Bit Field WDTWINB Watchdog Window Boundary Count Register Type rw BEy WDTL Reset 00 Bit Field
49. With the first falling edge of RXD e Ifthe system is the power down mode and PMCONO WS 01 a wake up from the power down through the RXD pin will be activated e Once the system enters normal mode the following settings must be done by software Bit 1 2 DIS is set to 0 enable Timer 2 Bit BCON BRDIS is set to 0 enable baud rate detection Bit BCON T2EXIS is set to O T2EX pin is used for baud rate detection Provide the baud rate range via bit BCON BGSEL Bits T2CON CP RL2 and T2CON 2 are set to 1 T2MOD EDGESEL is set to 0 Timer 2 is set to the capture mode with falling edge trigger User s Manual 10 17 V 0 2 2005 01 Serial Interfaces V 0 3 technologies Serial Interfaces The UART is running with an estimated baud rate which is generated by the baud rate generator See Section 10 1 4 1 Step 2 With the second falling edge of Synch Byte Start Timer 2 by hardware Bit 1 of Synch Byte field Step 3 With the third falling edge of Synch Byte The capture action of Timer 2 will be triggered and lead to a capture of the time of bit 1 and bit 2 in Synch Byte field The contents of the timer register THL2 are captured into the RC2 register The captured value is 2 LIN bit times long If the capture signal is detected while the counter is being incremented the counter is first incremented before the capture operation is performed This ensures that the latest value of the t
50. for channel numbers between 0 and 7 The queue stage stores the requested channel number and some additional control information As a result the order in which the channels are to be converted is freely programmable without restrictions in the sequence The additional control information is used to enable the request source interrupt when the requested channel conversion is completed and to enable the automatic refill process A sequential source consists of a queue stage QORO a backup stage QBURO and a mode control register QMRO The backup stage stores the information about the latest conversion requested after it has been aborted If the backup register contains an aborted request V 1 itis treated before the entry in the queue stage This implies that only the bit V in the backup register is cleared when the requested conversion is started If the bit V in the backup register is not set the bit V in the queue stage is reset when the requested conversion is started The request source can take part in the source arbitration if the backup stage or queue stage contains a valid request V 1 data written by CPU queue input register Ww queue stage CHNR RF ENSI abort of conversion start of conversion Figure 13 5 Base Structure of Sequential Request Source The automatic refill feature can be activated RF 1 to allow automatic re insertion of the pending request into the queue stage after a succes
51. or changes its count direction to down counting center aligned mode User s Manual 6 V 0 4 12 36 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 CC6xRL x 0 2 Capture Compare Register for Channel CC6x Low Reset Value 00 7 6 5 4 3 2 1 0 CC6xVL x 0 2 CC6xRH 0 2 Capture Compare Register for Channel CC6x High Reset Value 00 7 6 5 4 3 2 1 0 CC6xVH x 0 2 rh Field Bits Type Description CC6xV 7 0 of rh Channel x Capture Compare Value x 0 2 CC6xRL In compare mode the bit fields CC6xV contain the 7 0 of values that are compared to the T12 counter value In CC6xRH capture mode the captured value of T12 can be read from these registers User s Manual 12 37 V 0 2 2005 01 CCUG V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 CC6xSRL x 0 2 Capture Compare Shadow Register for Channel CC6x Low Reset Value 00 7 6 5 4 3 2 1 0 CC6xSL x 0 2 rwh CC6xSRH x 0 2 Capture Compare Shadow Register for Channel CC6x High Reset Value 00 7 6 5 4 3 2 1 0 CC6xSH x 0 2 rwh Field Bits Type Description 6 5 7 0 of rwh Shadow Register for Channel x Capture Compare x 0 2 CC6xSRL Value 7 0 of In compare mode the contents of bit fields CC6xS CC6xSRH are transferred to the
52. rw rw rw r The functions of the shaded bits are not described here Field Bits Type Description ANON 7 rw Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode 0 The analog part is switched off and conversions are not possible To achieve minimal power consumption the internal analog circuitry is its power down state and the generation of fApc is stopped 1 The analog part of the ADC module is switched on and conversions are possible The automatic power down capability of the analog part is disabled 3 0 r Reserved Returns 0 if read should be written with 0 User s Manual SCU V 0 4 8 9 V 0 2 2005 01 technologies Power Saving Modes OSC CON OSC Control Register Reset Value 0000 10008 7 6 5 4 3 2 1 0 0 OSCPD XPD OSCSS ORDRES OSCR r rw rw rw rwh rh uH The functions of the shaded bits are not described here Field Bits Description XPD 3 rw XTAL Power down Control 0 XTAL is not powered down 1 XTAL is powered down OSCPD 4 nw On chip OSC Power down Control 0 The on chip oscillator is not powered down 1 The on chip oscillator is powered down 0 7 5 r Reserved Returns 0 if read should be written with 0 User s Manual SCU V 0 4 8 10 V 0 2 2005 01 techno ogies Watchdog Timer 9 Watchdog Timer The Watchdog Timer WDT provi
53. the timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the timer overflow flag TFx The overflow flag TFx can then be used to request an interrupt The counted input is enabled for the timer when TRx 1 and either GATEx 0 or EXINTx 1 setting GATEx 1 allows the timer to be controlled by external input EXINTx to facilitate pulse width measurements TRx is a control bit in the register TCON bit GATEx is in register TMOD The 13 bit register consists of all the 8 bits of THx and the lower 5 bits of TLx The upper 3 bits of TLx are indeterminate and should be ignored Setting the run flag TRx does not clear the registers eh Interrupt Mode 0 operation is the same for Timer 0 and Timer 1 THO 5 8Bits Control GATEO 0 ModeO Figure 11 1 Timer 0 Mode 0 13 bit Timer User s Manual 11 3 V 0 2 2005 01 Timers V 0 4 technologies 11 1 2 2 Mode 1 Mode 1 operation is similar to that of mode 0 except that the timer register runs with all 16 bits Mode 1 operation for Timer 0 is shown in Figure 11 2 Li gt Interrupt Control GATEO EXINTO Timer Mode1 Figure 11 2 Timer 0 Mode 1 16 bit Timer User s Manual 11 4 V 0 2 2005 01 Timers V 0 4 techno ogies Timers 11 1 2 3 Mode 2 In mode 2 operation the timer is configured as an 8 bit counter TLx w
54. 000 000 Hz Data format quantities are defined as follows byte 8 bit quantity User s Manual 1 12 V 0 2 2005 01 Intro V 0 3 Cnfineon XC866 techno ogies Introduction 1 5 Reserved Undefined and Unimplemented Terminology In tables where register bit fields are defined the following conventions are used to indicate undefined and unimplemented function Further types of bits and bit fields are defined using the abbreviations shown in Table 1 3 Table 1 3 Bit Function Terminology Function of Bits Description Unimplemented Register bit fields named 0 indicate unimplemented functions with the following behavior Reading these bit fields returns 0 Writing to these bit fields has no effect These bit fields are reserved When writing software should always set such bit fields to 0 in order to preserve compatibility with future products Setting the bit fields to 1 may lead to unpredictable results Undefined Certain bit combinations in a bit field can be labeled Reserved indicating that the behavior of the XC866 is undefined for that combination of bits Setting the register to undefined bit combinations may lead to unpredictable results Such bit combinations are reserved When writing software must always set such bit fields to legal values as provided in the bit field description tables rw The bit or bit field can be read and written r The bit or bit field can on
55. 1 rw Conversion Start Mode of Request Source 0 This bit defines the conversion start mode of the sequential request source 0 0 The wait for start mode is selected 1 The cancel inject repeat mode is selected PRIO1 2 rw Priority of Request Source 1 This bit defines the priority of the parallel request source 1 0 Low priority 1 High priority CSM1 3 rw Conversion Start Mode of Request Source 1 This bit defines the conversion start mode of the parallel request source 1 0 The wait for start mode is selected 1 The cancel inject repeat mode is selected ARBM 4 rw Arbitration Mode This bit defines which arbitration mode is selected 0 Permanent arbitration default 1 Arbitration started by pending conversion request User s Manual 13 33 V 0 2 2005 01 ADC V 0 3 _ Infineon technologies XC866 Analog to Digital Converter Field Bits Type Description ASENx x 2 0 1 7 6 rw Arbitration Slot x Enable Each bit enables an arbitration slot of the arbiter round ASENO enables arbitration slot 0 ASEN1 enables slot 1 If an arbitration slot is disabled a pending conversion request of a request source connected to this slot is not taken into account for arbitration 0 The corresponding arbitration slot is disabled 1 The corresponding arbitration slot is enabled Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 34 V 0 2 2005 01 _
56. 1 rw Timer 0 Overflow Interrupt Enable 0 Timer 0 interrupt is disabled 1 Timer 0 interrupt is enabled 3 rw Timer 1 Overflow Interrupt Enable 0 Timer 1 interrupt is disabled 1 Timer 1 interrupt is enabled 1 When Timer 0 operates in mode 3 this interrupt indicates an overflow in the Timer 0 register THO User s Manual 11 12 V 0 2 2005 01 Timers V 0 4 techno ogies Timer 11 2 Timer 2 Timer 2 is a 16 bit general purpose timer that has two modes of operation a 16 bit auto reload mode and a 16 bit one channel capture mode If the prescalar is disabled Timer 2 counts with an input clock of PCLK 12 11 2 1 Auto Reload Mode The auto reload mode is selected when the bit CP RL2 in register T2CON is zero In this mode Timer 2 counts to an overflow value and then reloads its register contents with a 16 bit start value for a fresh counting sequence The overflow condition is indicated by setting bit TF2 in the T2CON register This will then generate an interrupt request to the core The overflow flag TF2 must be cleared by software The auto reload mode is further classified into two categories depending upon the DCEN control bit in register T2MOD 11 2 1 1 Up Down Count Disabled If DCEN 0 the up down count selection is disabled The timer therefore functions as a pure up counting timer only The operational block diagram is shown in Figure 11 5 If the T2CON register bit EXEN2 0 the timer
57. 13 22 13 4 8 2 Channel Interrupts 13 23 13 4 9 External Trigger Inputs 13 25 13 5 ADC Module Initialization Sequence 13 26 13 6 ghd wha de os bk oe BS oe eee ee he 13 28 13 7 Register Description 13 31 13 7 1 General Function Registers 13 31 13 7 2 Priority and Arbitration 13 33 13 7 3 External Trigger Control Register 13 35 13 7 4 Channel Control Registers 13 36 13 7 5 Input Class Register 13 37 13 7 6 Sequential Source Registers 13 38 13 7 7 Parallel Source Registers 13 44 13 7 8 Result RegiSIGIS pact cb Gebiget ieee deewele oo 13 48 13 7 9 Interrupt Registers 13 52 14 On Chip Debug Support 14 1 14 1 Functional Description 14 2 User s Manual 6 V 0 2 2005 01 techno ogies Table of Contents Page 14 2 Debugging scu OE nra aad he ee Mobs ee ee RUP 14 3 14 2 1 Debug pnl ACH eee eee eee 14 3 14 2 1 1 Hardware Breakpoints 14 4 14 2 1 2 Soft
58. 18 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 5 ADC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 ADC RESRA2H Reset 00 Bit Field RESULT 10 3 Result Register 2 View A High Type rh D24 ADC_RESRA3L Reset 00 Bit Field RESULT 2 0 VF DRC CHNR Result Register 3 View A Low Type rh rh rh rh ADC RESRA3H Reset 00 Bit Field RESULT 10 3 Result Register 3 View A High Type rh RMAP 0 Page 4 ADC RCRO Reset 00 BitField VFCTR WFR FEN IEN 0 DRCT Result Control Register 0 R Type rw rw rw rw r rw ADC 1 Reset 00 Bit Field VFCTR WFR FEN IEN 0 DRCT Result Control Register 1 R Type rw rw rw rw r rw CC ADC RCR2 Reset 00 BitField VFCTR WFR FEN IEN 0 DRCT Result Control Register 2 R Type rw rw rw rw r rw ADC RCR3 Reset 00 Bit Field VFCTR WFR FEN IEN 0 DRCT Result Control Register 3 R Type rw rw rw rw r rw ADC VFCR Reset 00 Bit Field 0 VFC3 VFC2 VFC1 VFCO Valid Flag Clear Register Type r w w w w RMAP 0 Page 5 CHINFR Reset 00 BitField CHINF CHINF CHINF CHINF CHINF CHINF Channel Interrupt Flag Register 7 6 5 4 3 2 1 0 Type rh
59. 2 2005 01 Power Reset and Clock V 0 4 Cnfineon XC866 techno ogies Power Supply Reset and Clock Management 7 3 1 1 Functional Description When the 866 is powered up the PLL is disconnected from the oscillator and will run at its VCO base frequency After the EVR is stable provided the oscillator is running the PLL will be connected and the continuous lock detection will ensure that the PLL starts functioning Once reset has been released bit OSCR will be set to 1 if the oscillator is running and bit LOCK will be set to 1 if the PLL is locked Loss of Lock Operation If the PLL is not the system s clock source VCOBYP 1 when the loss of lock is detected only the lock flag is reset PLL_CON LOCK 0 and no further action is taken This allows the PLL parameters to be switched dynamically If PLL loses its lock to the oscillator the PLL Loss of Lock NMI flag NMISR FNMIPLL is set and an NMI request to the CPU is activated if PLL NMI is enabled NMICON NMIPLL In addition the LOCK flag in PLL CON is reset PLL VCO gradually slows down to its base frequency Emergency routines can be executed with the XC866 clocked with this base frequency The XC866 remains in this loss of lock state until the next power on reset hardware reset or after a successful lock recovery has been performed Loss of Lock Recovery If PLL has lost its lock to the oscillator the PLL can be re locked by software The following sequence
60. 3 Digital input clock 13 3 Direct drive 7 11 Direct feed through 6 4 Document Acronyms 1 14 Terminology 1 13 Textual convention 1 12 Dynamic error detection 4 8 E EEPROM emulation 4 4 Embedded voltage regulator 7 1 Features 7 2 Low power voltage regulator 7 2 Main voltage regulator 7 2 Threshold voltage levels 7 2 Error Correction Code 4 8 Extended operation 2 6 External breaks 14 6 Break now 14 6 External data memory 3 3 External oscillator 7 9 7 11 F Flash 4 1 Endurance 4 4 Erase mode 4 7 Non volatile 4 1 Operating modes 4 7 Power down mode 4 7 Program mode 4 7 Program width 4 6 Ready to read mode 4 7 Sector 4 3 Flash devices 3 1 Flash program memory 3 1 Flash Timer NMI 4 11 Full duplex operation 10 21 G Gate disturb 4 6 GPIO 6 1 6 6 User s Manual Keyword Index H Half duplex operation 10 24 Hall sensor mode Actual hall pattern 12 19 Block commutation 12 21 Brushless DC 12 19 12 20 Correct hall event 12 19 Expected Hall pattern 12 19 Hall pattern 12 19 Modulation pattern 12 19 Noise filter 12 19 Hamming code 4 8 Hardware breakpoints 14 4 Hardware reset 7 4 High impedance 6 2 Idle mode 7 13 8 2 In Application Programming 4 10 Input class 13 8 Instruction decoder 2 2 Instruction timing 2 8 2 10 CPU state 2 8 Mnemonic 2 10 Wait state 2 8 In System Programming 4 9 Internal analog clock 13 3 Maximum frequency 13 3 Internal data memory 3 3 Internal RAM 3 1 Interrupt handling 5
61. 3 Bit n n 0 7 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled P3_ALTSELn n 0 1 Port 3 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw Table 6 13 Function of Bits P3 ALTSELO Pn and P3_ALTSEL1 Pn P3 ALTSELO Pn P3 ALTSEL1 Pn Function 0 0 Normal GPIO 1 0 Alternate Output 1 0 1 Alternate Output 2 1 1 Reserved User s Manual 6 33 V 0 2 2005 01 Parallel Ports V 0 3 techno ogies Power Supply Reset and Clock Management 7 Power Supply Reset and Clock Management The XC866 provides a range of utility features for secure system performance under critical conditions e g brownout The power supply to the core memories and the peripherals is regulated by the Embedded Voltage Regulator EVR with detection circuitries to ensure that the supplied voltages are within the specified operating range The main voltage and low power voltage regulators in the EVR may be independently switched off to reduce power consumption for the different power saving modes At the center of the XC866 clock system is the Clock Generation Unit CGU which generates a master clock frequency using the Phase Locked Loop PLL and oscillator units In phase synchronized clock signals are derived from the master clock and distributed throughout the system A programmable clock divider is available for scaling the mast
62. 4 BRPRE 010 174 AEQ 0 22 96 User s Manual 10 11 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces Register BCON contains control bits for baud rate generator and the prescaler bit field BCON Baud Rate Control Register Reset Value 00 7 6 5 4 3 2 1 0 BGSEL 2 5 BRDIS BRPRE R rw rw rw rw rw Field Bits Description R 0 rw Baud rate Generator Run Control Bit 0 Baud rate generator is disabled 1 Baud rate generator is enabled Note BR_VALUE should only be written if R 0 BRPRE 3 1 rw Prescaler Bit Selects the input clock for fp which is derived from the peripheral clock 000 fpiv 001 2 010 fpcik 4 011 8 100 fpiv 1 6 101 fpiv 32 Others reserved BRDIS 4 rw Baud Rate Detection Disable 0 Baud rate detection is enabled 1 Baud rate detection is disabled T2bXIS 5 rw T2EX Function Select 0 T2EX is selected for baud rate detection 1 T2EX is selected for Timer 2 function BGSEL 7 6 rw Baud Rate Select for detection 00 10 kHz to 20 kHz 01 5 kHz to 10 kHz 10 2 5 kHz to 5 kHz 11 1 25 kHz to 2 5 kHz User s Manual 10 12 V 0 2 2005 01 Serial Interfaces V 0 3 Infineon XC866 techno ogies Serial Interfaces Register BG contains the 8 bit reload value for the baud r
63. 4 Low STD STR RES Type w w r w w w w 9 CCU6 Reset 004 Bit Field T13 T13 0 T13 T13RS T13RR Timer Control Register 4 High STD STR RES Type w r w w w CCU6 MCMOUTSL Reset 00 Bit Field STRM 0 MCMPS Multi Channel Mode Output Shadow CM Register Low Type w r rw CCU6 MCMOUTSH Reset 004 Bit Field STRHP 0 CURHS EXPHS Multi Channel Mode Output Shadow Type w r rw rw Register High A4u CCU6_ISRL Reset 00 BitField 2 120 62 62 RCC61 61 60 60 Capture Compare Interrupt Status M M R E R F R Reset Register Low Type w w w w w w w w Ady CCU6_ISRH Reset 00 Bit Field RSTR RIDLE RWHE RCHE 0 RTRPF RT13 RT13 Capture Compare Interrupt Status PM CM Reset Register High Type m w w w r w w w CCU6 CMPMODIFL Reset 00 Bit Field 0 MCC63 0 MCC62 61 60 Compare State Modification Register S S S S Low Type r w r w w w CCU6 CMPMODIFH Reset 00 Bit Field 0 MCC63 0 62 61 60 Compare State Modification Register R R R R High Type r w r w w w CCU6 CC60SRL Reset 00 Bit Field CC60SL Capture Compare Shadow Register for Channel CC60 Low Type rwh CCU6 CC60SRH Reset 00 Bit Field CC60SH Capture Compare Shadow Register for Channel CC60 High Type rwh FC CCU6 CC61SRL Reset 00 Bit Field CC61SL Capture Compare Shadow Register for Channel CC61 Low Type rwh FDy CCU6_CC61SRH Reset 00 Bit Field CC61SH Capture Comp
64. 5 7 2 2 Module Reset Behavior 7 6 7 2 3 Booting Scheme 7 6 7 2 4 Register Description __ 7 7 7 3 7 9 7 3 1 Clock Generation Unit 7 9 7 3 1 1 Functional Description 7 10 7 3 2 Clock Source Control 7 11 7 3 3 Clock Management 7 13 7 3 4 Register Description 7 14 8 Power Saving 8 1 8 1 Functional Description 8 2 8 1 1 Mode tae ee 8 2 8 1 2 Slow Down 8 2 8 1 3 Power down 8 3 8 1 4 Peripheral Clock Management 8 4 8 2 Register DescHnpllOH usse as os pe RES ROS e hos 8 6 9 Watchdog 9 1 9 1 Functional Description 9 2 9 2 Register 9 5 9 3 Register Description 9 5 10 Serial Interfaces 10 1 10 1 WA 10 2 User s Manual 3 V 0 2 2005 01 techno ogies Table of Contents Page 10 1 1 VART 251 oe Cee ae he ees 10 2 10 1 1 1
65. 6 12 V 0 2 2005 01 Infineon technologies XC866 The addresses of the Port SFRs are listed in Table 6 2 Parallel Ports Table 6 2 SFR Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 804 PO DATA PO PUDSEL PO ALTSELO PO OD 86H PO_DIR PO PUDEN PO ALTSEL1 90 P1 DATA P1 PUDSEL P1 ALTSELO P1 OD 91 P1 DIR P1 PUDEN P1 ALTSEL1 P2 DATA P2 PUDSEL Aly P2 PUDEN P3 DATA P3 PUDSEL ALTSELO P3 OD Biy P3 DIR P3 PUDEN P3 ALTSEL1 User s Manual 6 13 V 0 2 2005 01 Parallel Ports V 0 3 Cnfineon XC866 techno ogies Parallel Ports 6 3 Port 0 Port PO is a 6 bit general purpose bidirectional port The registers of PO are summarized in Table 6 3 Table 6 3 Port 0 Registers Register Short Name Register Full Name PO DATA Port 0 Data Register PO DIR Port 0 Direction Register PO OD Port 0 Open Drain Control Register PO PUDSEL Port 0 Pull Up Pull Down Select Register PO PUDEN Port 0 Pull Up Pull Down Enable Register PO ALTSELO Port 0 Alternate Select Register 0 PO ALTSEL1 Port O Alternate Select Register 1 6 3 1 Functions Table 6 4 Port 0 Input Output Functions Port Pin Input Output Select Connected Signal s From to Module P0 0 Input GPI PO DATA PO ALT1 0 ALT2 T12HR 1 CCU6 ALT3 CC61_1 CCU6 Output GPO PO DATA
66. ADC Block Diagram User s Manual 13 8 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter 13 4 1 Request Source Arbiter The arbiter can operate in two modes that are selectable by bit ARBM Permanent arbitration In this mode the arbiter will continuously poll the request sources even when there is no pending conversion request Arbitration started by pending conversion request In this mode the arbiter will start polling the request sources only if there is at least one conversion pending request Once started the arbiter polls the two request sources source x at slot x x 0 1 to find the analog channel with the highest priority that must be converted For each arbitration slot the arbiter polls the request pending signal REQPND and the channel number valid signal REQCHNRV of one request source The sum of all arbitration slots is called an arbitration round An arbitration slot must be enabled ASENx 1 before it can take part in the arbitration Each request source has a source priority that can be programmed via bit PRIOx Starting with request source 0 arbitration slot 0 the arbiter checks if a request source has a pending request REQPND 1 for a conversion If more than one request source is found with the same programmed priority level and a pending conversion request the channel specified by the request source that was found first is selected The REQCHNRYV signal is also check
67. Bit Digital VO 1 All ROM devices include 4K x 8 Flash Figure 1 1 866 Functional Units User s Manual 1 1 V 0 2 2005 01 Intro 0 3 Infineon technologies XC866 Introduction The XC866 product family features eight devices with different configurations and program memory sizes offering cost effective solution for different application requirements In general each device contains a non volatile 8K x 8 read only program memory a volatile 768 x 8 read write data memory four ports three 16 bit timers a 16 bit capture compare unit a 16 bit compare timer 14 interrupt vectors and an NMI four priority level interrupt structure two serial ports versatile fail safe mechanisms on chip debugging support logic and a 10 bit ADC The list of XC866 devices and their differences are summarized in Table 1 1 Table 1 1 Device Summary Device Type Device Name Flash Size ROM Size LIN Support Flash XC866L 4FR 16 Kbytes Yes XC866 4FR 16 Kbytes XC866L 2FR 8 Kbytes Yes XC866 2FR 8 Kbytes ROM XC866L 4RR 4 Kbytes 16 Kbytes Yes XC866 4RR 4 Kbytes 16 Kbytes No XC866L 2RR 4 Kbytes 8 Kbytes Yes XC866 2RR 4 Kbytes 8 Kbytes No The term XC866 in this document refers to all devices of the XC866 family unless otherwise stated User s Manual Intro 0 3 0 2 2005 01 Cnfineon XC866 techno ogies Intro
68. C44 Bit Field 0 P5 P4 P3 P2 P1 PO Pull Up Pull Down Enable Register Type r rw rw rw rw rw rw 90 P1 PUDSEL Reset FF Bit Field P7 P6 P5 0 1 P1 Pull Up Pull Down Select Register Type rw rw rw r rw rw User s Manual 3 16 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 4 Port Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 914 P1_PUDEN Reset Bit Field P6 P5 0 P1 PO P1 Pull Up Pull Down Enable Register Type rw rw rw r rw rw P2 PUDSEL Reset FF Bit Field P7 P6 P5 P4 P3 P2 P1 PO P2 Pull Up Pull Down Select Register Type rw rw rw rw rw rw rw rw Aly P2_PUDEN Reset 00 Bit Field 7 6 5 2 1 P2 Pull Up Pull Down Enable Register Type rw rw rw rw rw rw rw rw P3 PUDSEL Reset Bit Field P7 P6 P5 P4 P3 P2 P1 P3 Pull Up Pull Down Select Register Type rw rw rw rw rw rw rw rw Bly P3_PUDEN Reset 40 Bit Field P7 P6 P5 P4 P3 P2 1 P3 Pull Up Pull Down Enable Register Type rw rw rw rw rw rw rw rw RMAP 0 Page 2 804 PO ALTSELO Reset 004 Bit Field 0 P5 P4 P3 P2 P1 PO PO Alternate Select 0 Register Type r rw rw rw rw rw rw 864 PO ALTSEL1 Reset 00 Bit Field 0 P5 P4 P3 P2 P1 PO PO Alternate Select 1 Register Type r rw rw rw rw rw rw 904 P1 ALTSELO Reset 004 Bit Field
69. D1 It contains the page value and page control information ADC PAGE Page Register for ADC Reset Value 00 7 6 5 4 3 2 1 0 OP STNR 0 w w r w Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page When read the value indicates the currently active page STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10 the contents of PAGE are saved in STx before being overwritten with the new value If OP 11g the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STOis selected 01 ST1is selected 10 ST2is selected 11 ST3is selected User s Manual 13 28 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter Field Bits Type Description OP 7 6 w Operation OX Manual page mode The value of STNR is ignored and PAGE is directly written 10 New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR 11 A Automatic restore page action The value written to the bit positions of PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR
70. DPTR 2 4 2 2 3 2 22222522 6 2 4 2 2 4 B RSGISIBI a daa eme E domat d 2 4 2 2 5 Program Status Word 2 5 2 2 6 Extended Operation Register EO 2 6 2 2 7 Power Control Register PCON 2 7 2 3 Iris rt DOE 2252420 here ee 2 8 3 Memory Organization 3 1 3 1 Program Memory 3 3 3 2 Data Memory seses usua ee ch Gk ede dee E R ee ee ees 3 3 3 2 1 Internal Data Memory 3 3 3 2 2 External Data Memory 3 3 3 3 Special Function Registers 3 4 3 3 1 Address Extension by Mapping 3 4 3 3 2 Address Extension by Paging 3 6 3 3 3 s rsa whe Reh ke RE Mee 3 9 3 3 4 System Control Registers 3 10 3 3 4 1 Bit Protection Scheme 3 12 3 9 5 XC866 Register Overview 3 13 3 3 5 1 CPU Registers 3 13 3 3 5 2 System Control Registers 3 14 3 3 5 3 3 16 3 3 5 4
71. DPTR1 used destroyed Resources RO R7 of Register Bank IRAM address 184 1Fp reserved IRAM address 36 Machine cycles 358 taken 2 1 The data in the reserved resources must not be altered throughout the erasing period including Flash Timer NMI servicing to ensure correct erasing flow 2 User s Manual Flash Memory V 0 3 Estimated value without wait state 4 13 V 0 2 2005 01 techno ogies Flash Memory Upon completing the D Flash erasing sequence the Flash Timer NMI will be disabled NMICON NMIFLASHTIMER 0 by the erase subroutine For end of D Flash erasing indication the user can check for one of the following Bit NMICON NMIFLASHTIMER is cleared of Register Bank IRAM address 1 is 03 A manual check on the D Flash data is necessary to determine the success of the erasing via a MOVC instruction User s Manual 4 14 V 0 2 2005 01 Flash Memory V 0 3 _ Infineon XC866 techno ogies Interrupt System 5 Interrupt System The XC800 Core supports one non maskable interrupt NMI and 14 maskable interrupt requests In addition to the standard interrupt functions supported by the core 0 configurable interrupt priority and interrupt masking the XC866 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sou
72. Data Flash D Flash bank with different sectorization The program memory map for the two different Flash sizes is shown in Figure 4 1 P Flash Bank 2 4 Kbytes P Flash Bank 1 4 Kbytes 1000 P Flash Bank 0 4 Kbytes P Flash Bank 0 4 Kbytes I I 1 1 0000 H 8 Kbytes 16 Kbytes Figure 4 1 Flash Memory Map For the 8 Kbyte Flash devices P Flash bank 0 is available and occupies the lower part of the program memory address starting from 0000 where the reset and interrupt vectors are located For the 16 Kbyte Flash devices two additional P Flash banks 1 and 2 are provided for storing user code e P Flash bank 1 occupies the address range 1000 1FFFy e P Flash bank 2 occupies 2000 2FFF All devices in the XC866 product family including ROM devices offer a 4 Kbyte D Flash bank occupying the address region A000 AFFF User s Manual 4 2 V 0 2 2005 01 Flash Memory V 0 3 Cnfineon XC866 techno ogies Flash Memory 4 2 Flash Bank Sectorization The XC866 Flash devices consist of two types of 4 Kbyte banks namely Program Flash P Flash bank and Data Flash D Flash bank with different sectorization as shown in Figure 4 2 Both types can be used for code and data storage The label Data neither implies that the D Flash is mapped to the data memory region nor that it can only be used for data s
73. Device User s Manual 3 2 V 0 2 2005 01 Memory Organization V 0 2 Cnfineon XC866 techno ogies Memory Organization 3 1 Program Memory The performance of the CPU is optimized with a dedicated interface for direct interfacing with the program memory without using any port pin This means that a code fetch can occur on every rising edge of the clock Hence there is no concept of internal or external program memory as all code is fetched from a single program memory interface 3 2 Data Memory The data memory space consists of an internal and external memory space The labels internal and external for data memory are used to distinguish between the register memory and the 64 Kbyte data space accessed using MOV instructions They do not imply that the external data memory is located off chip 3 2 1 Internal Data Memory The internal data memory is divided into two physically separate and distinct blocks the 256 byte RAM and the 128 byte Special Function Register SFR area While the upper 128 bytes of RAM and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of RAM can be accessed through either direct or register indirect addressing while the upper 128 bytes of RAM can be accessed through register indirect addressing only The SFRs are accessible through direct addressing The 16 bytes of RAM that occupy addresses from 20
74. EV can be set only if a conversion request is valid with V 1 In this case the signal REQCHNRYV is derived from bit EV Bit TRMD trigger mode offers the possibility to wait with the valid bit already set for an event to be detected before taking part in the arbitration This ensures that the reaction to an event is with minimum delay If this feature is not desired TRMD 0 the event bit EV can be used to generate both REQPND and REQCHNRV User s Manual 13 12 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter 13 4 5 Parallel Request Source 13 4 5 1 Overview The parallel request source at arbitration slot 1 generates one or more conversion requests for channel numbers between 4 and 7 in parallel The requests are always treated one after the other in separate arbitration rounds in a predefined sequence higher channel numbers before lower channel numbers The parallel request source consists of a conversion request control register CRCR1 a conversion request pending register CRPR1 and a conversion request mode register CRMR1 The contents of the conversion request control register are copied overwrite to the conversion request pending register when a selected load event LDE occurs The type of the event defines the behavior and the trigger of the request source The activation of a conversion request to the arbiter may be started if the content of the conversion pendin
75. MTSR MRST First Transmit Data Last Bit T Bit Latch Data Shift Data Figure 10 10 Serial Clock Phase and Polarity Options When initializing the devices for serial communication one device must be selected for master operation while all other devices must be programmed for slave operation 10 3 1 2 Full Duplex Operation The various devices are connected through three lines The definition of these lines is always determined by the master the line connected to the master s data output line TXD is the transmit line the receive line is connected to its data input line RXD the shift clock line is either MS_CLK or SS_CLK Only the device selected for master operation generates and outputs the shift clock on line MS_CLK Since all slaves receive this clock their pin SCLK must be switched to input mode The external connections are hard wired and the function and direction of these pins are determined by the master or slave operation of the individual device User s Manual 10 21 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces Master Device 1 Device 2 Slave Shift Register Shift Register Figure 10 11 SSC Full Duplex Configuration The data output pins MRST of all slave devices are connected together onto the single receive line in the configuration shown in Figure 10 11 During a transfer each slave shifts out data from its shift register There are two ways to avoid
76. Memory Organization V 0 2 Infineon technologies 866 Memory Organization 3 3 5 XC866 Register Overview The SFRs of the XC866 are organized into groups according to their functional units The contents bits of the SFRs are summarized in Section 3 3 5 1 to Section 3 3 5 9 Note The addresses of the bitaddressable SFRs appear in bold typeface in Table 3 1 to Table 3 9 3 3 5 1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas RMAP 0 or 1 Table 3 1 CPU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 or 1 814 SP Reset 07 Bit Field SP Stack Pointer Register Type rw 824 DPL Reset 00 Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPLO Data Pointer Register Low Type rw rw rw rw rw rw rw rw 834 DPH Reset 00 Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPHO Data Pointer Register High Type rw rw rw rw rw rw rw rw 87 Reset 00 Bit Field SMOD 0 GF1 GFO 0 IDLE Power Control Register Type rw r rw rw r rw 884 TCON Reset 00 Bit Field TF1 TR1 TFO TRO IE1 IT1 IEO ITO Timer Control Register Type rwh rw rwh rw rwh rw rwh rw 89 TMOD Reset 00 BitField GATE1 0 T1M GATEO 0 TOM Timer Mode Register Ty
77. Mode 1 8 Bit UART Variable Baud Rate 10 2 10 1 1 2 Mode 2 9 Bit UART Fixed Baud Rate 10 5 10 1 1 3 Mode 3 9 Bit UART Variable Baud Rate 10 5 10 1 2 Multiprocessor Communication 10 7 10 1 3 Register Description 10 7 10 1 4 Baud Rate Generation 10 9 10 1 4 1 Baud rate Generator 10 10 10 1 5 Interfaces of UART 10 13 10 2 rrr 10 14 10 2 1 LIN seee sia mia a a a D T t TT DLL Lo 10 14 10 2 2 LIN Header Transmission 10 16 10 2 3 Baud Rate Detection 10 17 10 3 High Speed Synchronous Serial Interface 10 19 10 3 1 General Operation 10 20 10 3 1 1 Operating Mode Selection 10 20 10 3 1 2 Full Duplex Operation 10 21 10 3 1 3 Half Duplex Operation 10 24 10 3 1 4 Continuous Transfers 10 25 10 3 1 5 Port CoDIFGl X E 10 25 10 3 1 6 Baud Rate Generation 10 26 10 3 1 7 Error Detection Mechanisms 10 27 10 3 2 nine PTT 10 30 10 3 3 Register
78. On areceiver full condition On error condition receive phase baud rate transmit error User s Manual 10 1 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces 10 1 UART The UART provides a full duplex asynchronous receiver transmitter i e it can transmit and receive simultaneously It is also receive buffered i e it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still has not been read by the time reception of the second byte is complete one of the bytes will be lost 10 1 1 UART Modes The UART can be used in three asynchronous modes In mode 1 it operates as an 8 bit serial port and in modes 2 and 3 it operates as a 9 bit serial port The only difference between mode 2 and mode 3 is the baud rate which is fixed in mode 2 but variable in mode 3 The variable baud rate is derived from the dedicated baud rate generator The different modes are selected by setting bits SMO and SM1 to their corresponding values as shown in Table 10 1 The selection where the value of both SMO and SM1 is zero is reserved Table 10 1 UART Modes SMO SM1 Operating Mode Baud Rate 0 0 Reserved 0 1 Mode 1 8 bit shift UART Variable 1 0 Mode 2 9 bit shift UART 32 or foc 64 1 1 Mode 3 9 bit shift UART Variable 10 1 1 1 Mode 1 8 Bit UART Varia
79. Ports PO P1 and P3 are bidirectional and can be used as general purpose input output GPIO or to perform alternate input output functions for the on chip peripherals When configured as an output the open drain mode can be selected Port P2 is an input only port providing general purpose input functions alternate input functions for the on chip peripherals and also analog inputs for the Analog to Digital Converter ADC Bidirectional Port Features Configurable pin direction Configurable pull up pull down devices Configurable open drain mode e Transfer of data through digital inputs and outputs general purpose Alternate input output for on chip peripherals Input Port Features Configurable pull up pull down devices Receive of data through digital input general purpose input Alternate input for on chip peripherals e Analog input for ADC module User s Manual 6 1 V 0 2 2005 01 Parallel Ports V 0 3 techno ogies Parallel Ports 6 1 General Port Operation Figure 6 1 shows the block diagram of an XC866 bidirectional port pin Each port pin is equipped with a number of control and data bits thus enabling very flexible usage of the pin By defining the contents of the control register each individual pin can be configured as an input or an output The user can also configure each pin as an open drain pin with or without internal pull up pull down device Each bidirectional port pin can be
80. Receive MSB First PH 5 rw Clock Phase Control 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing edge PO 6 rw Clock Polarity Control 0 Idle clock line is low leading clock edge is low to high transition 1 Idle clock line is high leading clock edge is high to low transition LB 7 rw Loop Back Control 0 Normal output 1 Receive input is connected with transmit output half duplex mode User s Manual Serial Interfaces V 0 3 10 33 V 0 2 2005 01 Infineon technologies XC866 CONH Control Register High 7 6 Serial Interfaces Reset Value 00 4 3 2 1 0 EN MS AREN BEN PEN REN TEN rw rw Field Bits Description TEN 0 Transmit Error Enable 0 Ignore transmit errors 1 Check transmit errors REN 1 Receive Error Enable 0 Ignore receive errors 1 Check receive errors PEN 2 Phase Error Enable 0 Ignore phase errors 1 Check phase errors BEN 3 Baud Rate Error Enable 0 Ignore baud rate errors 1 Check baud rate errors AREN 4 Automatic Reset Enable 0 No additional action upon a baud rate error 1 The SSC is automatically reset upon a baud rate error MS 6 Master Select 0 Slave mode Operate on shift clock received via SCLK 1 Master mode Generate shift clock and output it via SCLK EN 7 Enable Bit 0 Transmission a
81. STNR 5 4 w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10g the contents of PAGE are saved in STx before being overwritten with the new value If OP 11g the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STO is selected 01 ST1is selected 10 ST2is selected 11 ST3is selected User s Manual 3 10 V 0 2 2005 01 Memory Organization V 0 2 Infineon technologies XC866 Memory Organization Field Bits Type Description OP 7 6 w Operation OX Manual page mode The value of STNR is ignored and PAGE is directly written 10 New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR 11 A Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR 0 3 r Reserved Returns 0 if read should be written with 0 User s Manual Memory Organization V 0 2 3 11 V 0 2 2005 01 _ nfineon XC866 techno ogies Memory Organization 3 3 4 4 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits i e protected
82. SWSYN 0 SWSEL Field Bits Type Description SWSEL 2 0 rw Switching Selection Bit field SWSEL selects one of the following trigger request sources next multi channel event for the shadow transfer from MCMPS to MCMP The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer The shadow transfer takes place synchronously with an event selected in bit field SWSYN 000 No trigger request will be generated 001 Correct hall pattern on CCPOSx detected 010 T13 period match detected while counting up 011 T12 one match while counting down 100 T12 channel 1 compare match detected phase delay function 101 T12 period match detected while counting up else reserved no trigger request will be generated User s Manual 12 70 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 Field Bits Type Description SWSYN 5 4 rw Switching Synchronization Bit field SWSYN triggers the shadow transfer between MCMPS and MCMP if it has been requested before flag R set by an event selected by SWSEL This feature permits the synchronization of the outputs to the PWM source that is used for modulation T12 or T13 00 Direct the trigger event directly causes the shadow transfer 01 113 zero match triggers the shadow transfer 10 A T12 zero
83. T12 Shadow Transfer Disable 0 No action 1 STE12 is reset without triggering the shadow transfer 0 5 4 Ir Reserved Returns 0 if read should be written with 0 User s Manual 12 55 V 0 2 2005 01 CCU6 V 0 4 _ Infineon technologies XC866 Capture Compare Unit 6 Timer Control Register 4 High Reset Value 00 7 6 5 4 3 2 1 0 T13 T13 0 T13 T13 T13 STD STR RES RS RR WwW r Ww Field Bits Type Description T13RR 0 Timer T13 Run Reset Setting this bit resets the T13R bit 0 T13R is not influenced 1 T13R is cleared T13 stops counting T13RS 1 Timer T13 Run Set Setting this bit sets the T13R bit 0 T13R is not influenced 1 T13R is set T13 counts T13RES 2 Timer T13 Reset 0 No effect on T13 1 The T13 counter register is reset to zero The switching of the output signals is according to the switching rules Setting of TT3RES has no impact on bit T13R T13STR 6 Timer T13 Shadow Transfer Request 0 No action 1 STE13 is set enabling the shadow transfer T13STD 7 Timer T13 Shadow Transfer Disable 0 No action 1 STE13 is reset without triggering the shadow transfer 0 5 3 r Reserved Returns 0 if read should be written with O Note A simultaneous write of a 1 to bits which set and reset the same bit will trigger no action for example writing 1 to bits T13RR and T13RS will not modify bit T13R
84. The corresponding bit will remain unchanged User s Manual 6 V 0 4 12 56 0 2 2005 01 _ Infineon XC866 techno ogies Capture Compare Unit 6 12 3 5 Modulation Control Registers 12 3 5 1 Global Module Control Register MODCTR contains control bits that enable the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13 Furthermore the multi channel mode can be enabled as additional modulation source for the output signals MODCTRL Modulation Control Register Low Reset Value 00 7 6 5 4 3 2 1 0 0 T12MODEN nw r rw Field Bits Type Description T12MODEN 5 0 rw 12 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T12 The bit positions correspond to the following output signals Bit 0 Modulation of CC60 Bit 1 Modulation of COUT60 Bit 2 Modulation of CC61 Bit 3 Modulation of COUT61 Bit 4 Modulation of CC62 Bit 5 Modulation of COUT62 The enable feature of the modulation is defined as follows 0 The modulation of the corresponding output signal by a T12 PWM pattern is disabled 1 The modulation of the corresponding output signal by a T12 PWM pattern is enabled User s Manual 12 57 V 0 2 2005 01 6 V 0 4 _ lnfineon XC866 techno ogies Capture Compare Unit 6 Fi
85. Up Pull Down Enable Register Page 6 8 Px ALTSELO Port x Alternate Select Register 0 Page 6 10 Px ALTSEL1 Port x Alternate Select Register 1 Page 6 10 User s Manual 6 5 V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon XC866 techno ogies Parallel Ports 6 1 1 1 Data Register If a port pin is used as general purpose output output data is written into the data register Px DATA If a port pin is used as general purpose input the latched value of the port pin can be read through register Px DATA Note A port pin that has been assigned as input will latch in the active internal pull up pull down setting if it is not driven by an external source This results in register Px DATA being updated with the active pull value Px DATA Port x Data Register 7 6 5 4 3 2 1 0 7 6 5 4 2 1 rw rw rw rw rw rw rw rw Field Bits Description Pn n rw Port x Pin n Data Value n 0 7 0 Port x pin n data value 0 1 Port x pin n data value 1 Bit Px_DATA n can only be written if the corresponding pin is set to output Px_DIR n 1 and cannot be written if the corresponding pin is set to input Px_DIR n 0 The content of Px_DATA n is output on the assigned pin if the pin is assigned as GPIO pin and the direction is switched set to output A read operation of Px_DATA returns the register value and not the state of the corresponding Px_DATA pin User
86. Vpp drops below 1 6 V User s Manual 7 2 V 0 2 2005 01 Power Reset and Clock V 0 4 techno ogies Power Supply Reset and Clock Management 7 2 Reset Control The XC866 has five types of reset power on reset hardware reset watchdog timer reset power down wake up reset and brownout reset When the XC866 is first powered up the status of certain pins see Table 7 2 must be defined to ensure proper start operation of the device At the end of a reset sequence the sampled values are latched to select the desired boot option which cannot be modified until the next power on reset or hardware reset This guarantees stable conditions during the normal operation of the device The hardware reset function can be used during normal operation or when the chip is in power down mode A reset input pin RESET is provided for the hardware reset The Watchdog Timer WDT module is also capable of resetting the device if it detects a malfunction in the system Another type of reset that needs to be detected is a reset while the device is in power down mode wake up reset While the contents of the static RAM are undefined after a power on reset they are well defined after a wake up reset from power down mode A brownout reset is triggered if the Vpp supply voltage dips below 2 1 V 7 2 1 Types of Reset 7 2 1 1 Power On Reset The supply voltage Vppp is used to power up the chip The EVR is the first module in the chip to b
87. WDT 7 0 Watchdog Timer Register Low Type rh BFy WDTH Reset 00 Bit Field WDT 15 8 Watchdog Timer Register High Type rh 3 3 5 4 Port Registers The Port SFRs can be accessed in the standard memory area RMAP 0 Table 3 4 Port Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 2 PORT PAGE Reset 00 Bit Field OP STNR 0 PAGE Page Register for PORT Type w w r rw RMAP 0 Page 0 80 PO DATA Reset 00 Bit Field 0 P5 P4 P3 P2 P1 PO PO Data Register Type r rw rw rw rw rw rw 86H PO DIR Reset 00 Bit Field 0 P5 2 1 PO Direction Register Type r rw rw rw rw rw rw 90 1 DATA Reset 00 Bit Field P7 P6 P5 0 1 P1 Data Register Type rw rw rw r rw rw 914 P1_DIR Reset 004 Bit Field P7 P6 P5 0 1 P1 Direction Register Type rw rw rw r rw rw 0 P2 DATA Reset 00 Bit Field P7 P6 P5 P4 P3 P2 P1 PO P2 Data Register Type rw rw rw rw rw rw rw rw P3 DATA Reset 00 Bit Field P6 P5 P4 P3 P2 P1 Data Register Type rw rw rw rw rw rw rw rw B1y P3_DIR Reset 00 Bit Field 6 5 2 1 P3 Direction Register Type rw rw rw rw rw rw rw rw RMAP 0 Page 1 804 PO PUDSEL Reset FF Bit Field 0 P5 P4 P3 P2 P1 PO PO Pull Up Pull Down Select Register Type r rw rw rw rw rw rw 864 PO PUDEN Reset
88. access possible while it is being programmed or erased However it is possible to program erase one Flash bank while reading from another When the user sets bit PMCONO PD 1 to enter the system power down mode the Flash banks will automatically be brought to its power down state by hardware Upon wake up from system power down the Flash banks are brought to ready to read mode to allow access by the CPU User s Manual 4 7 V 0 2 2005 01 Flash Memory V 0 3 _ Infineon XC866 techno ogies Flash Memory 4 5 Error Detection and Correction The 8 bit data from the CPU is encoded with an Error Correction Code ECC before being stored in the Flash memory During a read access data is retrieved from the Flash memory and decoded for dynamic error detection and correction The correction algorithm hamming code has the capability to Detect and correct all 1 bit errors Detect all 2 bit errors but cannot correct A corrected 1 bit error result is valid and an uncorrected 2 bit error result is invalid are not distinguished with an ECC non maskable interrupt NMI generated for both cases The 16 bit Flash address at which the ECC error occurs is stored in the system control SFRs FEAL and FEAH and can be accessed by the interrupt service routine to determine the Flash bank sector in which the error occurred FEAL Flash Error Address Register Low Reset Value 00
89. an identical cycle behavior of the path to the result register with the data reduction filter being enabled or disabled Furthermore an overflow of the result register is avoided because a maximum of 2 conversion results are added a 10 bit result added twice delivers a maximum of 11 bits 13 4 7 4 Result FIFO Functionality The four result registers can be independently configured to provide a 2 3 or 4 stage FIFO functionality This allows the storing of measurement results with relaxed CPU access timing If the FIFO mechanism is enabled FEN 1 for result register x independent from the read views the following actions take place the setting of result register x 1 has no influence on these actions If the valid flag VFx is not set result register x does not contain valid data and VFx 1 of result register x 1 is set the contents of result register x 1 are transferred to result register x Furthermore VFx becomes set and VFx 1 becomes reset The setting of VFx can generate an event interrupt A result interrupt x is generated when new data is stored in result register x if the previous register x 1 is not enabled for FIFO functionality 13 4 7 5 Result Register View In order to cover a wide range of applications the content of result register x x 0 to 3 is available as different read views at different addresses see Figure 13 11 Normal read view RESRxL H This view delivers the 8 bit or 10 bit conversion
90. be enabled or disabled individually via register NMICON After reset the enable bits of IENO IEN1 and NMICON are cleared to 0 This implies that the corresponding interrupts are disabled IENO Interrupt Enable Register 0 Reset Value 00 7 6 5 4 3 2 1 0 EA 0 ET2 ES ET1 EX1 ETO EXO nw r nw rw rw rw rw rw Field Bits Type Description EX0 0 rw Enable External Interrupt 0 0 External Interrupt 0 is disabled 1 External Interrupt 0 is enabled ETO 1 rw Enable Timer 0 Overflow Interrupt 0 Timer 0 Overflow interrupt is disabled 1 Timer 0 Overflow interrupt is enabled EX1 2 rw Enable External Interrupt 1 0 External interrupt 1 is disabled 1 External interrupt 1 is enabled ET1 3 rw Enable Timer 1 Overflow Interrupt 0 Timer 1 Overflow interrupt is disabled 1 Timer 1 Overflow interrupt is enabled ES 4 rw Enable Serial Port Interrupt 0 Serial Port interrupt is disabled 1 Serial Port interrupt is enabled ET2 5 rw Enable Timer 2 Interrupt 0 Timer 2 interrupt is disabled 1 Timer 2 interrupt is enabled User s Manual 5 9 V 0 2 2005 01 Interrupt System V 0 5 _ Infineon XC866 techno ogies Interrupt System Field Bits Type Description EA 7 rw Enable Disable All Interrupts 0 No interrupt will be acknowledged 1 Each interrupt source is individually enabled or disabled by setting or clearing its enable bit 0 6 r Reserved Returns 0 if read
91. been detected T13PM 1 rh Timer T13 Period Match Flag 0 A timer T13 period match has not been detected since this bit was reset 1 A timer T13 period match has been detected TRPF 2 rh Trap Flag The trap flag TRPF will be set by hardware if TRPPEN 1 and CTRAP 0 or by software If 2 0 bit TRPF is reset by hardware if the input CTRAP becomes inactive TRPPEN 1 If TRPM2 1 bit TRPF must be reset by software in order to leave the trap state 0 The trap condition has not been detected 1 The trap condition has been detected input CTRAP has been 0 or by software TRPS 3 rh Trap State 0 The trap state is not active 1 The trap state is active Bit TRPS is set while bit TRPF 1 It is reset according to the mode selected in register TRPCTR 4 rh Correct Hall Event 0 A transition to a correct expected hall event has not been detected since this bit was reset 1 A transition to a correct expected hall event has been detected User s Manual 12 78 V 0 2 2005 01 6 V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description WHE 5 rh Wrong Hall Event 0 A transition to a wrong hall event not the expected one has not been detected since this bit was reset 1 A transition to a wrong hall event not the expected one has been detected IDLE 6 rh IDLE State This bit is set together wi
92. bits using the PASSWD register When the bit field MODE is 11g writing 10011g to the bit field PASS opens access to writing of all protected bits and writing 10101g to the bit field PASS closes access to writing of all protected bits Note that access is opened for maximum 32 CCLKs if the close access password is not written If open access password is written again before the end of 32 CCLK cycles there will be a recount of 32 CCLK cycles The protected bits include NDIV WDTEN PD and SD PASSWD Password Register Reset Value 07 7 6 5 4 3 2 1 0 PASS PROTECT MODE wh rh rw Field Bits Type Description MODE 1 0 rw Bit Protection Scheme Control bits 00 Scheme Disabled 11 Scheme Enabled default Others Scheme Enabled These two bits cannot be written directly To change the value between 11g and 00g the bit field PASS must be written with 11000 only then will the MODE 1 0 be registered PROTECT S 2 rh Bit Protection Signal Status bit This bit shows the status of the protection 0 Software is able to write to all protected bits 1 Software is unable to write to any protected bits PASS 7 3 wh Password bits The Bit Protection Scheme only recognizes three patterns 11000 Enables writing of the bit field MODE 10011g Opens access to writing of all protected bits 10101g Closes access to writing of all protected bits User s Manual 3 12 V 0 2 2005 01
93. by check byte 10 2 2 LIN Header Transmission LIN header transmission is only applicable in master mode In the LIN communication a master task decides when and which frame is to be transferred on the bus It also identifies a slave task to provide the data transported by each frame The information needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame The header consists of a break and synch pattern followed by an identifier Among these three fields only the break pattern cannot be transmitted as a normal 8 bit UART data The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes The UART can be used to transmit a 20 bit break field by the following sequence Step 1 Set the UART to mode 1 This configures the UART as an 8 bit UART with a variable baud rate Step 2 Set the baud rate to two times of the desired baud rate Step 3 Write 00 to the transmit buffer to begin transmission By having two times of the desired baud rate the 10 bit UART frame consisting of the start stop and 8 data bits will achieve the effect of a 20 bit break field on the LIN bus For subsequent synch and identifier fields the baud rate must then be adjusted back to the initial value User s Manual 10 16 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces 10 2 3 Baud Ra
94. configured for input or output operation Switching between input and output mode is accomplished through the register Px_DIR x 0 1 or 3 which enables or disables the output and input drivers A port pin can only be configured as either input or output mode at any one time In input mode default after reset the output driver is switched off high impedance The actual voltage level present at the port pin is translated into a logic 0 or 1 via Schmitt Trigger device and can be read via the register Px_DATA In output mode the output driver is activated and drives the value supplied through the multiplexer to the port pin In the output driver each port line can be switched to open drain mode or normal mode push pull mode via the register Px_OD The output multiplexer in front of the output driver enables the port output function to be used for different purposes If the pin is used for general purpose output the multiplexer is switched by software to the data register Px_DATA Software can set or clear the bit in Px_DATA and therefore directly influence the state of the port pin If an on chip peripheral uses the pin for output signals alternate output lines AltDataOut can be switched via the multiplexer to the output driver circuitry Selection of the alternate function is defined in registers Px_ALTSELO and Px_ALTSEL1 When a port pin is used as an alternate function its direction must be set accordingly in the register Px_DIR
95. direct feed through to the ADC input channel Internal Bus P2 PUDSEL Pull up Pull down Selec Register Pull up Pull down Control Logic P2 PUDEN Pull up Pull down Enable Register y Pull Device Input In Driver P2 Data 4 Data Register Schnitt Trigger Pad AltDataln lt Analogln Figure 6 2 General Structure of Input Port User s Manual 6 4 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 6 1 1 General Register Description Parallel Ports The individual control and data bits of each parallel port are implemented in a number of 8 bit registers Bits with the same meaning and function are assembled together in the same register The registers configure and use the port as general purpose or alternate function input output For port P2 not all the registers in Table 6 1 are implemented The availability and definition of registers specific to each port is defined in Section 6 3 to Section 6 6 This section provides only an overview of the different port registers Table 6 1 Port Registers Register Short Name Register Full Name Description see Px DATA Port x Data Register Page 6 6 Px DIR Port x Direction Register Page 6 7 Px OD Port x Open Drain Control Register Page 6 7 Px PUDSEL Port x Pull Up Pull Down Select Register Page 6 8 Px PUDEN Port x Pull
96. down mode is activated by setting the bit SD in SFR PMCONO The bit field CMCON CLKREL is used to select different slow down frequency The CPU and peripherals are clocked at this lower frequency The slow down mode is terminated by clearing bit SD The slow down mode can be combined with the idle mode by performing the following sequence 1 The slow down mode is activated by setting the bit PMCONO SD 2 The idle mode is activated by setting the bit PCON IDLE There are two ways to terminate the combined idle and slow down modes The idle mode can be terminated by activation of any enabled interrupt CPU operation is resumed and the interrupt will be serviced The next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLE Nevertheless the slow down mode stays enabled and if required User s Manual 8 2 V 0 2 2005 01 SCU V 0 4 _ Infineon XC866 techno ogies Power Saving Modes termination must be done by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow down mode The other way of terminating the combined idle and slow down mode is through a hardware reset 8 1 3 Power down Mode In power down mode the oscillator and the PLL are turned off The FLASH is put into the power down mode The main voltage regulator is switched off but the low power voltag
97. illustrates the memory address spaces of the 16 Kbyte Flash devices For the 8 Kbyte Flash devices the shaded banks are not available FFFF FFFF F200 F200 XRAM XRAM 512 bytes F000 512 bytes F000 E000 Boot ROM 8 Kbytes C000 B000 D Flash Bank 4 Kbytes A000 Indirect Direct 3000 Address Address P Flash Bank 2 FF 4 Kbytes Special Function 2000 Internal RAM Registers P Flash Bank 1 80 4 Kbytes 1000 7E H P Flash Bank 0 4 Kbytes Internal RAM 0000 0000 00 Program Space External Data Space Internal Data Space Figure 3 1 Memory Map of XC866 Flash Device User s Manual 3 1 Memory Organization V 0 2 V 0 2 2005 01 866 technologies Memory Organization Figure 3 2 illustrates the memory address spaces of the 16 Kbyte ROM devices For the 8 Kbyte ROM devices the shaded address regions are not available FFFF FFFF F200 F200 XRAM XRAM 512 bytes F000 512 bytes F000 E000 Boot ROM 8 Kbytes C000 B000 D Flash Bank 4 Kbytes A000 4000 Indirect Direct Address Address FF Special Function ROM 2000 Intemal RAM Registers 16 Kbytes 80 TF Internal RAM 0000 0000 00 v A V v P v J Program Space External Data Space Internal Data Space Figure 3 2 Memory Map of XC866 ROM
98. interrupt generation is the detection of a set condition by hardware or software for the corresponding bit in register IS Note In compare mode and hall mode the timer related interrupts are only generated while the timer is running TxR 1 In capture mode the capture interrupts are also generated when the timer T12 is stopped User s Manual 6 V 0 4 12 79 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 ISSL Capture Compare Interrupt Status Set Register Low Reset Value 00 7 6 5 4 3 2 1 0 5 5 5 5 5 5 T12 T12 CC CC CC CC CC CC PM OM 62F 62R 61F 61R 60F 60R Ww Ww Ww Ww Ww Ww Ww Ww Field Bits Type Description SCC60R 0 Ww Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC60R in register IS will be set SCC60F 1 w Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC60F in register IS will be set SCC61R 2 Ww Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS will be set SCC61F 3 w Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC61F in register IS will be set SCC62R 4 Ww Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC62R in register IS will be set SCC62F 5 Ww Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC62F in register IS will be set ST120M 6 Set Timer T12 One Match Flag 0 No action 1 Bit T12OM in register IS
99. is selected for CC60 0 01 Reserved 10 Reserved 11 Reserved ISCC61 3 2 rw Input Select for CC61 This bit field defines the port pin that is used for the CC61 capture input signal 00 The input pin is selected for CC61 0 01 The input pin is selected for CC61 1 10 Reserved 11 Reserved ISCC62 5 4 rw Input Select for CC62 This bit field defines the port pin that is used for the CC62 capture input signal 00 The input pin is selected for 62 0 01 The input pin is selected for CC62 1 10 Reserved 11 Reserved ISTRP 7 6 Input Select for CTRAP This bit field defines the port pin that is used for the CTRAP input signal 00 The input pin is selected for CTRAP 0 01 input pin is selected for CTRAP 1 10 The input pin is selected for 2 11 Reserved User s Manual 12 32 V 0 2 2005 01 6 V 0 4 Infineon technologies XC866 PISELOH Port Input Select Register 0 High Capture Compare Unit 6 Reset Value 00 7 6 5 3 2 1 0 IST12HR ISPOS2 ISPOS1 ISPOSO rw rw rw rw Field Bits Type Description ISPOSO 1 0 rw Input Select for CCPOSO This bit field defines the port pin that is used for the CCPOSO input signal 00 The input pin is selected for CCPOSO 0 01 The input pin is selected for CCPOSO 1 10 Reserved 11 Reserved ISPOS1 3 2 rw Input Select for CCPOS1 This bit field defin
100. levels as shown in Table 5 2 Table 5 2 Interrupt Priority Level Selection IPH x IPH1 x IP x IP1 x Level 0 0 Level 0 lowest 0 1 Level 1 1 0 Level 2 1 1 Level 3 highest Note As the NMI has the highest priority it does not use the level selection shown in Table 5 2 A low priority interrupt can be interrupted by a high priority interrupt but not by another interrupt of the same or lower priority Further an interrupt of the highest priority cannot be interrupted by any other interrupt source If two or more requests of different priority levels are received simultaneously the request of the highest priority is serviced first If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced first Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 5 3 Table 5 3 Priority Structure within Interrupt Level Source Level Non Maskable Interrupt NMI highest External Interrupt O Timer O Interrupt External Interrupt 1 1 2 3 Timer 1 Interrupt 4 UART Interrupt 5 Timer 2 Interrupt 6 7 8 9 1 1 ADC Interrupt SSC Interrupt External Interrupt 2 External Interrupt 6 3 CCU6 Interrupt Node Pointer 0 User s Manual 5 21 V 0 2 2005 01 Interrupt System V 0 5 _ Infineon
101. match while counting up triggers the shadow transfer 11 Reserved no action 0 r Reserved 7 6 Returns 0 if read should be written with 0 Note The generation of the shadow transfer request by hardware is only enabled if bit MCMEN f User s Manual 12 71 V 0 2 2005 01 CCUG V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 Register T12MSEL contains control bits that select the capture compare functionality of the three channels of timer T12 T12MSELL 12 Capture Compare Mode Select Register Low Reset Value 00 7 6 5 4 3 2 1 0 MSEL61 MSEL60 rw rw Field Bits Type Description MSEL60 3 0 rw Capture Compare Mode Selection MSEL61 7 4 These bit fields select the operating mode of the three timer T12 capture compare channels Each channel n 0 2 can be programmed individually either for compare or capture operation according to 0000 Compare outputs disabled pins CC6n and be used for I O pins No capture action 0001 Compare output pin CC6n pin COUT6n can be used for I O pins No capture action 0010 Compare output pin COUT6n CC6n can be used for I O pins No capture action 0011 Compare output on pins COUT6n CC6n 01XX Double register capture modes see Table 12 5 1000 Hall sensor mode see Table 12 6 In order to enable the hall edge detection MSEL6x x 0 2 must be programmed to h
102. memory when the CPU is initialized and subsequently also to provide software updates The instruction copies the contents of the accumulator to the code memory at the location pointed to by the current data pointer and then increments the data pointer The instruction uses the opcode 5 which is the same as the software break instruction TRAP see Table 2 1 Register bit EO TRAP_EN is used to select the instruction executed by the opcode A54 When TRAP is 0 default the A54 opcode executes the MOVC instruction When TRAP is 1 the A54 opcode executes the software break instruction TRAP which switches the CPU to debug mode for breakpoint processing EO Extended Operation Register Reset Value 00 7 6 5 4 3 2 1 0 0 TRAP EN 0 DPSELO r rw r rw Field Bits Type Description DPSELO 0 rw Data Pointer Select 0 DPTRO is selected 1 DPTR1 is selected TRAP EN 4 rw TRAP Enable 0 Select MOVC DPTR A 1 Select software TRAP instruction 0 3 1 r Reserved 7 5 Returns 0 if read should be written with 0 User s Manual 2 6 V 0 2 2005 01 Processor Architecture V 0 3 _ Infineon XC866 techno ogies Processor Architecture 2 2 7 Power Control Register PCON The CPU has two power saving modes idle mode and power down mode The idle mode can be entered via the PCON register In idle mode the clock to the CPU is stopped while the timers serial port and inter
103. must be performed 1 Disconnect the oscillator from the PLL OSCDISC 1 2 Set the N divider of the PLL to the value 16 PLL_CON NDIV 0010p 3 Wait for 50 us until the oscillator is stable 4 Restart the Oscillator Run Detection by setting bit OSC_CON ORDRES If bit OSC_CON OSCR is set then 1 Select the VCO bypass mode VCOBYP 1 2 Reconnect oscillator to the PLL OSCDISC 0 3 Reprogram the NDIV factor to the original value 4 The RESLD bit must be set and the LOCK flag checked Only if the LOCK flag is set again can the VCO bypass mode be deselected and normal operation resumed If neither OSCR nor LOCK is set emergency measures must be executed Emergency measures such as a system shut down can be carried out by the user User s Manual 7 10 V 0 2 2005 01 Power Reset and Clock V 0 4 technologies Power Supply Reset and Clock Management Changing PLL Parameters To change the PLL parameters first check if the oscillator is running OSC CON OSCR 1 In this case 1 Select VCO bypass mode VCOBYP 1 2 Connect oscillator to PLL OSCDISC 0 3 Program desired NDIV value 4 Wait till the LOCK bit has been set 5 Disable VCO bypass mode Select the External Oscillator To select the external oscillator the following sequence must be performed 1 Select the VCO bypass mode VCOBYP 1 2 Disconnect the oscillator from the PLL OSCDISC 1 3 External OSC is power
104. occurrence of the next desired expected hall pattern or a wrong pattern If the current hall pattern at the hall input pins is equal to the bit field EXPH bit CHE correct hall event is set interrupt request is generated if enabled by bit ENCHE If the current hall pattern at the hall input pins is not equal to the bit fields CURH or EXPH bit WHE wrong hall event is set and an interrupt request is generated if enabled by bit ENWHE CURH 5 3 rh Current Hall Pattern Bit field CURH is written by a shadow transfer from bit field CURHS The contents are compared after every detected edge at the hall input pins in order to detect the occurrence of the next desired expected hall pattern or a wrong pattern If the current Hall input pattern is equal to bit field CURH the detected edge at the hall input pins was an invalid transition e g a spike 0 7 6 r Reserved Returns 0 if read should be written with 0 1 The bits in the bit fields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx x 0 2 the following order 2 EXPH 1 EXPH 0 CURH 2 CURH 1 CURH 0 CCPOS2 CCPOS1 50 User s Manual 12 69 V 0 2 2005 01 6 V 0 4 techno ogies Capture Compare Unit 6 Register MCMCTR contains control bits for the multi channel functionality MCMCTR Multi Channel Mode Control Register Reset Value 00 7 6 5 4 3 2 1 0 0
105. offers the possibility of configuring the following input characteristics e tristate high impedance with a weak pull up device high impedance with a weak pull down device and the following output characteristics push pull optional pull up pull down open drain with internal pull up open drain with external pull up The pull up pull down device can be fixed or controlled via the registers Px_PUDSEL Px PUDEN Register Px PUDSEL selects the type of pull up pull down device while register Px_PUDEN enables or disables it The pull up pull down device can be selected pinwise Px_PUDSEL Port x Pull Up Pull Down Select Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port x Bit n n 0 7 0 Pull down device is selected 1 Pull up device is selected Px_PUDEN Port x Pull Up Pull Down Enable Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 rw rw rw rw rw rw rw rw User s Manual 6 8 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 Parallel Ports Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port x Bit n n 0 7 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled User s Manual 6 9 V 0 2 2005 01 Parallel Ports V 0 3
106. passive state The PWM generated by T12 or T13 is not taken into account 1 The output can deliver the PWM generated by T12 or T13 according to register MODCTR User s Manual 12 67 V 0 2 2005 01 6 V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description rh Reminder Flag This reminder flag indicates that the shadow transfer from bit field MCMPS to MCMP has been requested by the selected trigger source This bit is cleared when the shadow transfer takes place and while MCMEN 0 0 No shadow transfer from 5 to MCMP is requested 1 A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source but has not been executed because the selected synchronization condition has not occurred Reserved Returns 0 if read should be written with 0 1 While IDLE 1 bit field MCMP is cleared User s Manual CCUG V 0 4 12 68 V 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 MCMOUTH Multi Channel Mode Output Register High Reset Value 00 7 6 5 4 3 2 1 0 0 CURH EXPH r rh rh Field Bits Type Description 2 0 rh Expected Hall Pattern Bit field EXPH is written by a shadow transfer from bit field EXPHS The contents are compared after every detected edge at the hall input pins in order to detect the
107. performed at the module level by paging With the address extension by mapping the XC866 has a 256 SFR address range However this is still less than the total number of SFRs needed by the on chip peripherals To meet this requirement some peripherals have a built in local address extension mechanism for increasing the number of addressable SFRs The extended address range is not directly controlled by the CPU instruction itself but is derived from bit field PAGE in the module page register MOD_PAGE Hence the bit field PAGE must be programmed before accessing the SFR of the target module Each module may contain a different number of pages and a different number of SFRs per page depending on the specific requirement Besides setting the correct RMAP bit value to select the SFR area the user must also ensure that a valid PAGE is selected to target the desired SFR A page inside the extended address range can be selected as shown in Figure 3 4 SFR Address from CPU i PAGE 0 MOD PAGE PAGE Ww PAGE 1 SFR Data to from CPU PAGE q Module Figure 3 4 Address Extension by Paging User s Manual 3 6 V 0 2 2005 01 Memory Organization V 0 2 Cnfineon XC866 techno ogies Memory Organization In order to access a register located in a page different from the actual one the current page must be left This is done by reprogramming the bit field PAGE in the page register Only
108. register have only a read view A write operation to this address leads to a data write to CRCR1 with an automatic load event one clock cycle later CRPR1 Conversion Request Pending Register 1 Reset Value 00 7 6 5 4 3 2 1 0 CHP7 CHP6 CHP5 4 0 rwh rwh rwh rwh Field Bits Type Description CHPx X rwh Channel Pending Bit x 4 7 Write view A write to this address targets the bits in register CRCR1 Read view Each bit corresponds to one analog channel the channel number x is defined by the bit position in the register The arbiter automatically resets at start of conversion or sets it again at abort of conversion for the corresponding analog channel 0 The analog channel x is not requested for conversion by the parallel request source 1 The analog channel x is requested for conversion by the parallel request source 0 3 0 r Reserved Returns 0 if read should be written with 0 Note The bits that can be read from this register location are generally rh They cannot be modified directly by a write operation A write operation modifies the bits in that is why they are marked rwh and leads to a load event one clock cycle later User s Manual 13 45 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter Register CRMR1 contains bits that are used to set the request source in the desir
109. required reload value for a given baud rate ER fPcLK a rate D Ll 2 x lt BR gt 1 2 x Baud rate lt gt represents the contents of the reload register taken as an unsigned 16 bit integer while baud rate is equal to fus 55 aS shown in Figure 10 14 User s Manual 10 26 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces The maximum baud rate that can be achieved when using a module clock of 26 7 MHz is 13 3 MBaud in master mode with lt BR gt 0000 or 6 7 MBaud in slave mode with lt BR gt 0001p Table 10 3 lists some possible baud rates together with the required reload values and the resulting deviation errors assuming a module clock frequency of 26 7 MHz Table 10 3 Typical Baud Rates of the SSC fn 26 7 MHz Reload Value Baud Rate fus 55 Deviation 0000 13 3 MBaud only in Master mode 0 096 00014 6 7 MBaud 0 096 0009 1 3 MBaud 0 0 000 1 2 5 0011 750 kBaud 1 296 00134 666 7 kBaud 0 0 00154 600 kBaud 1 0 001A 500 kBaud 1 296 00314 266 7 kBaud 0 0 0042 200 kBaud 0 5 0063 133 3 kBaud 0 0 00844 100 kBaud 0 25 FFFFy 203 45 Baud 0 0 10 3 1 7 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes Transmit Error and Baud Rate Error apply only to slav
110. result Accumulated read view RESRAxL H This view delivers the accumulated 9 bit or 11 bit conversion result All conversion results with or without accumulation are stored in the result registers but can be viewed at either RESRxL H or RESRAXL H which shows different data alignment and width When the data reduction filter is enabled DRCTR 1 read access should be performed RESRAxL H as it shows the full 9 bit R8 RO or 11 bit R10 RO accumulated conversion result Reading from RESRxL H gives the appended MSB unavailable accumulated result When the data reduction filter is disabled DRCTR 0 the user can read the 8 bit or 10 bit conversion result from either RESRxL H or RESRAxL H In particular for 8 bit User s Manual 13 19 V 0 2 2005 01 ADC V 0 3 e Infineon technologies XC866 Analog to Digital Converter conversion without accumulation the result can be read from RESRxH with a single instruction Hence depending on the application requirement the user can choose to read from the different views Result Register x High Result Register x Low 76543210 76543210 R10 R9 Ra R7 R6 R5 R4 R2 R1 RO VF DRC CHNR RESRxH RESRxL RESRAxH RESRAxL 76543210 76543210 76543210 76543210 R7 R6 R5 R4 R R2 R1 RO 0
111. result is above both boundaries After a conversion has been completed a channel interrupt can be triggered according to the following conditions selected by the limit check control bit field LCC LCC 000 No trigger the channel interrupt is disabled LCC 001 A channel interrupt is generated if the conversion result is not in area e LCC 010 A channel interrupt is generated if the conversion result is not in area e LCC 011 A channel interrupt is generated if the conversion result is not in area III e LCC 100 A channel interrupt is always generated regardless of the boundaries LCC 101 A channel interrupt is generated if the conversion result is in area e LCC 110 A channel interrupt is generated if the conversion result is in area e LCC 111 A channel interrupt is generated if the conversion result is in area User s Manual 13 23 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter The channel specific interrupt node pointer CHINPx x 0 to 7 selects the service request output SR 1 0 that will be activated upon a channel interrupt trigger See Figure 13 15 to SRO to SR1 channel number Figure 13 15 Channel Interrupt Routing User s Manual 13 24 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter 13 4 9 External Trigger Inputs The sequential and parallel request sources ha
112. rh rh rh rh rh rh rh ADC CHINCR Reset 00 BitField CHINC CHINC CHINC CHINC CHINC CHINC CHINC Channel Interrupt Clear Register 7 6 5 4 3 2 1 0 w w w w w CCy ADC_CHINSR Reset 00 Bit Field CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS Channel Interrupt Set Register 7 6 5 4 3 2 1 0 w w w w w w CDy ADC_CHINPR Reset 00 Bit Field CHINP CHINP CHINP CHINP CHINP Channel Interrupt Node Pointer 7 6 5 4 3 2 1 0 Register Type rw rw rw rw rw rw rw rw ADC EVINFR Reset 00 BitField EVINF EVINF EVINF EVINF 0 EVINF EVINF Event Interrupt Flag Register 7 6 5 4 1 0 Type rh rh rh rh r rh rh ADC EVINCR Reset 00 BitField EVINC EVINC EVINC 0 EVINC EVINC Event Interrupt Clear Flag Register 7 6 5 4 1 0 w w w r w w D2u ADC EVINSR Reset 00 BitField EVINS EVINS EVINS EVINS 0 EVINS EVINS Event Interrupt Set Flag Register 7 6 5 4 1 0 w w r ADC EVINPR Reset 00 BitField EVINP EVINP EVINP 0 EVINP EVINP Event Interrupt Node Pointer Register 7 6 5 4 1 0 rw rw rw rw r rw rw RMAP 0 Page 6 ADC CRCR1 Reset 00 Bit Field CH7 CH6 CH5 CH4 0 Conversion Request Control Register 1 Type rwh rwh rwh rwh r ADC CRPR1 Reset 00 Bit Field CHP7 CHP6 CHP5 4 0 Conversion Request Pending
113. rw rw E8y IEN1 Reset 00 Bit Field ECCIP ECCIP ECCIP ECCIP EXM EX2 ESSC EADC Interrupt Enable Register 1 3 2 1 0 Type rw rw rw rw rw rw rw rw Reset 00 Bit Field B7 B6 B5 4 B3 B2 B1 BO B Register Type rw rw rw rw rw rw rw rw F84 IP1 Reset 00 Bit Field PCCIP PCCIP PCCIP PCCIP PXM PX2 PSSC PADC Interrupt Priority Register 1 3 2 1 0 Type rw rw rw rw rw rw rw rw F94 IPH1 Reset 00 Bit Field PCCIP PCCIP PCCIP PXMH 2 PSSCH PADC Interrupt Priority Register 1 High 3H 2H 1H OH H Type rw rw rw rw rw rw rw rw 3 3 5 2 System Control Registers The system control SFRs can be accessed in the standard memory area RMAP 0 Table 3 2 System Control Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 or 1 8 SYSCONO Reset 00 Bit Field 0 RMAP System Control Register 0 Type r rw RMAP 0 BFy SCU_PAGE Reset 00 Bit Field OP STNR 0 PAGE Page Register for System Control Type w w r rw RMAP 0 Page 0 MODPISEL Reset 00 Bit Field 0 JTAG JTAG 0 EXINT URRIS Peripheral Input Select Register TDIS TCKS 015 r rw rw r rw rw B44 IRCONO Reset 00 Bit Field 0 EXINT EXINT EXINT EXINT EXINT Interrupt Request Register 0 6 5 4 3 2 1 0 Type r rwh rwh rwh rwh rw
114. rwh Serial Interface Buffer Register SCON Serial Channel Control Register Reset Value 00 7 6 5 4 3 2 1 0 SMO SM1 SM2 REN TB8 RB8 Tl RI rw rw rw rw rw rwh rwh rwh Field Bits Description RI 0 Receive Interrupt Flag This is set by hardware at the half point of the stop bit in modes 1 2 and 3 Must be cleared by software Tl 1 rwh Transmit Interrupt Flag This is set by hardware at the beginning of the stop bit in modes 1 2 and 3 Must be cleared by software RB8 2 rwh Serial Port Receiver Bit 9 In modes 2 and 3 this is the 9th data bit received In mode 1 this is the stop bit received TB8 3 rw Serial Port Transmitter Bit 9 In modes 2 and 3 this is the 9th data bit sent REN 4 rw Enable Receiver of Serial Port 0 Serial reception is disabled 1 Serial reception is enabled SM2 5 rw Enable Serial Port Multiprocessor Communication in Modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 RI will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 is set to 1 RI will not be activated if a valid stop bit RB8 was not received User s Manual 10 8 V 0 2 2005 01 Serial Interfaces V 0 3 _ lnfineon XC866 techno ogies Serial Interfaces Field Bits Description SM1 6 rw Serial Port Operating Mode Selection SMO 7 SMO SM1 Selected operating mode 0 0 Mode 0 Reserved 0 1 Mode 1 8 bit UART variable baud rate
115. slave In the master and all slaves the contents of the shift register are copied into the receive buffer RB and the RIR is activated If no further transfer is to take place TB is empty CON BSY will be cleared at the same time Software should not modify CON BSY as this flag is hardware controlled When configured as a slave device the SSC will immediately output the selected first bit MSB or LSB of the transfer data at the output pin once the contents of the transmit buffer are copied into the slave s shift register Bit CON BSY is not set until the first clock edge at SS_CLK appears Note On the SSC a transmission and a reception take place at the same time regardless of whether valid data has been transmitted or received Note The initialization of the CLK pin on the master requires some attention in order to avoid undesired clock transitions which may disturb the other devices Before the clock pin is switched to output via the related direction control register the clock output level will be selected in the control register CON and the alternate output be prepared via the related ALTSEL register or the output latch must be loaded with the clock idle level User s Manual 10 23 V 0 2 2005 01 Serial Interfaces V 0 3 Cnfineon XC866 techno ogies Serial Interfaces 10 3 1 3 Half Duplex Operation In a half duplex mode only one data line is necessary for both receiving and transmitting of data The data excha
116. software When read this bit always delivers O 0 The bit fields CURH and EXPH are updated according to the defined hardware action The write access to bit fields CURHS and EXPHS does not modify the bit fields CURH and EXPH 1 The bit fields CURH and EXPH are updated by the value written to the bit fields CURHS and EXPHS 0 6 r Reserved Returns 0 if read should be written with 0 User s Manual 12 66 V 0 2 2005 01 6 V 0 4 Infineon XC866 techno ogies Capture Compare Unit 6 Register MCMOUT specifies the multi channel control bits that are currently used MCMOUTL Multi Channel Mode Output Register Low Reset Value 00 7 6 5 4 3 2 1 0 0 R MCMP r rh rh Field Bits Type Description 1 5 0 rh Multi Channel PWM Pattern Bit field MCMP is written by a shadow transfer from bit field MCMPS It contains the output pattern for the multi channel mode If this mode is enabled by bit MCMEN in register MODCTR the output state of the following output signal can be modified Bit O Multi channel state for output CC60 Bit 1 Multi channel state for output COUT60 Bit 2 Multi channel state for output CC61 Bit 3 Multi channel state for output COUT61 Bit 4 Multi channel state for output CC62 Bit 5 Multi channel state for output COUT62 The multi channel patterns can set the related output to the passive state 0 The output is set to the
117. support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered 866 8 Bit Single Chip Microcontroller Infineon chnologies te thinking 866 Revision History 2005 01 0 2 Previous Version We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com gt lt techno ogies Table of Contents Page 1 Introduction uuu LES RESERxRaR db ERS 1 1 1 1 Feature Summary sb Rescue eee Sew ew ase 1 3 1 2 Pin COMIOUIAUON mia edet Race 1 5 1 3 Pin Definitions and Functions 1 6 1 4 Text al Convention scc bd idit ex eadem i ee d 1 12 1 5 Reserved Undefined and Unimplemented Terminology 1 13 1 6 ee ade 1 14 2 Processor Architecture 2 1 2 1 Functional Description 2 2 2 2 CPU Register Description 2 4 2 2 1 Stack Pointer 5 2 4 2 2 2 Data Pointer
118. techno ogies Analog to Digital Converter Setup parallel source Enable conversion request CRMR1 ENGT Enable disable external trigger CRMR1 ENTR Enable disable source interrupt CRMR1 ENSI Enable disable autoscan CRMR1 SCAN 10 Turn on analog part Set GLOBCTR ANON wait for 100 ns 11 Start sequential request Write to QINRO with information such as REQCHNR RF ENSI and EXTR Generate a pending conversion request using any method described Section 13 4 4 2 12 Start parallel request Write to CRCR1 no load event or CRPR1 automatic load event the channels to be converted Generate a load event if not already available to trigger a pending conversion request using any method described in Section 13 4 5 2 13 Wait for ADC conversion to be completed The source interrupt indicates that the conversion requested by the source is completed The channel interrupt indicates that the corresponding channel conversion is completed with limit check performed The result interrupt indicates that the result with without accumulation or FIFO in the corresponding result register is ready and can be read 14 Read ADC result User s Manual 13 27 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter 13 6 Register Map The ADC SFRs are located in the standard memory area RMAP 0 and are organized into 7 pages The ADC PAGE register is located at address
119. techno ogies Timers 11 1 3 Register Map Seven SFRs control the operations of Timer 0 and Timer 1 They can be accessed from both the standard non mapped and mapped SFR area Table 11 2 lists the addresses of these SFRs Table 11 2 SFR Address List Address Register 88 89 TMOD 8A TLO 8By TL1 8Cy THO 8 1 User s Manual 11 7 V 0 2 2005 01 Timers V 0 4 Infineon technologies XC866 11 1 4 Register Description Timers The low and high bytes of both Timer 0 and Timer 1 can be combined to a one timer configuration depending on the mode used TLx x 0 1 Timer x Register Low Reset Value 00 7 6 5 4 3 2 1 0 VAL rwh THx x 2 0 1 Timer x Register High Reset Value 00 7 6 5 4 3 2 1 0 VAL rwh Field Bits Description TLx VAL 7 0 rwh Timer 0 1 Low Register x20 1 Operating Description Mode 0 TLx holds the 5 bit prescaler value 1 holds the lower 8 bit part of the 16 bit timer value holds the 8 bit timer value TLO holds the 8 bit timer value TL 1 is not used User s Manual Timers V 0 4 11 8 V 0 2 2005 01 Infineon XC866 technologies Timers Field Bits Description THx VAL 7 0 rwh Timer 0 1 High Register 0 1 Operating
120. technologies XC866 Interrupt System Table 5 3 Priority Structure within Interrupt Level cont d Source Level CCU6 Interrupt Node Pointer 1 12 CCU6 Interrupt Node Pointer 2 13 CCU6 Interrupt Node Pointer 3 14 5 4 5 Interrupt Request Flags The interrupt request flags are located in different SFRs Table 5 4 shows the bit locations of the interrupt request flags Detailed information about the interrupt request flags is provided in the respective peripheral chapters Table 5 4 Locations of the Interrupt Request Flags Interrupt Source Request Flags SFR Timer 0 Interrupt TFO TCON Timer 1 Interrupt TF1 TCON Timer 2 Interrupt TF2 T2CON EXF2 T2CON UART RI SCON TI SCON External Interrupt O IEO TCON External Interrupt 1 IE1 TCON External Interrupt 2 EXINT2 IRCONO External Interrupt 3 External Interrupt 4 EXINT4 IRCONO External Interrupt 5 5 External Interrupt 6 EXINT6 IRCONO ADC Interrupt ADCSRCO IRCON1 ADCSRC1 IRCON1 SSC Interrupt EIR IRCON1 TIR IRCON1 RIR IRCON1 CCU6 Node 0 Interrupt See note CCU6 Node 1 Interrupt See note CCU6 Node 2 Interrupt See note User s Manual Interrupt System V 0 5 5 22 V 0 2 2005 01 Cnfineon XC866 techno ogies Interrupt System Table 5 4 Locations of the Interrupt Request Flags c
121. that a backup copy of the data set is available in the event that the actual data set is corrupted or erased Alternatively the user can implement an algorithm for EEPROM emulation which uses the D Flash bank like a circular stack memory the latest data updates are always programmed on top of the actual region When the top of the sector is reached all actual data representing the EEPROM data is copied to the bottom area of the next sector and the last sector is then erased This round robin procedure using multifold replications of the emulated EEPROM size significantly increases the endurance To speed up data search the RAM can be used to contain the pointer to the valid data set User s Manual 4 4 V 0 2 2005 01 Flash Memory V 0 3 4 3 e Infineon technologies XC866 Wordline Address The wordline WL addresses of the P Flash and D Flash banks are given in Figure 4 3 Flash Memory Byte 31 2 1 0 31 2 1 0 2 2 2FE1 2FEO X AFFF sss 2 AFE1 AFEO X d ZEE i 538 E Se i i 8 S
122. to 2F are bitaddressable RAM occupying direct addresses from to 7Fy can be used as scratch pad registers or used for the stack 3 2 2 External Data Memory The 512 byte XRAM is mapped to both the external data memory area and the program memory area It can be accessed using both MOV and MOVC instructions User s Manual 3 3 V 0 2 2005 01 Memory Organization V 0 2 techno ogies Memory Organization 3 3 Special Function Registers The Special Function Registers SFRs occupy direct internal data memory space in the range 80 to FF All registers except the program counter reside in the SFR area SFRs include pointers and registers that provide an interface between the CPU and the on chip peripherals As the 128 SFR range is less than the total number of registers required address extension mechanisms are required to increase the number of addressable SFRs The address extension mechanisms include Mapping Paging 3 3 1 Address Extension by Mapping Address extension is performed at the system level by mapping The SFR area is extended into two portions the standard non mapped SFR area and the mapped SFR area Each portion supports the same address range 80 to bringing the number of addressable SFRs to 256 The extended address range is not directly controlled by the CPU instruction itself but is derived from bit RMAP in the system control register SYSCONO at address 8F
123. valid for all three channels User s Manual 12 8 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 1 7 Capture Mode In capture mode the bits CC6xST indicate the occurrence of the selected capture event according to the bit fields MSEL6x MSEL6x 01XXg double register capture mode see Table 12 5 MSEL6x 101Xg or 11XXg multi input capture modes see Table 12 7 A rising and or a falling edge on the pins CC6x or CCPOSx can be selected as the capture event that is used to transfer the contents of timer T12 to the CC6xR and CC6xSR registers In order to work in capture mode the capture pins must be configured as inputs There are several ways to store the captured values in the registers For example in double register capture mode the timer value is stored in the channel shadow register CC6xSR The value previously stored in this register is simultaneously copied to the channel register CC6xR The software can then check the newly captured value while still preserving the possibility of reading the value captured earlier Note In capture mode a shadow transfer can be requested according to the shadow transfer rules except for the capture compare registers that are left unchanged 12 1 1 8 Single Shot Mode The single shot mode of timer T12 is selected when bit T12SSC is set to 1 In single shot mode the timer T12 stops automatically at the end of its counting period Fig
124. value Compare value Period value Compare value 0 Pin CC6x CC6xPS 0 PSL 0 __ Pin COUT6x COUT6xPS 1 1 PSL 0 T Pin CCPOSx Figure 12 7 Hysteresis Like Control Mode User s Manual 12 10 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 2 Timer T13 The timer T13 is similar to timer T12 except that it has only one channel in compare mode The counter can only count up similar to the edge aligned mode of T12 input clock for timer T13 can be from fcc ug to a maximum of 128 and is configured by bit field TT3CLK In order to support higher clock frequencies an additional prescaler factor of 1 256 be enabled for the prescaler of T13 if bit T13PRE 1 The T13 shadow transfer in case of a period match is enabled by bit STE13 During the T13 shadow transfer the contents of register CC63SR are transferred to register CC63R Both registers can be read by software while only the shadow register can be written by software The bits CC63PS 1 and PSL63 have shadow bits The contents of these shadow bits are transferred to the actually used bits during the T13 shadow transfer Write actions target the shadow bits while read actions deliver the value of the actually used bits zero match period match counter register T13 Maak 6 113 overv
125. voltage regulator continues to function and provide power supply to the system with low power consumption The EVR has the Vpp and Vppp detectors There are two threshold voltage levels for Vpp detection prewarning 2 3 V and brownout 2 1 V When Vpp is below 2 3 V the Vpp NMI flag NMISR FNMIVDD is set and an NMI request to the CPU is activated if Vpp NMI is enabled NMICON NMIVDD If Vpp is below 2 1 V the brownout reset will be activated putting the microcontroller into a reset state For Vppp there is only one prewarning threshold of 4 0 V if the external power supply is 5 0 V When Vppp is below 4 0 V the NMI flag NMISR FNMIVDDP is set and an NMI request to the CPU is activated if Vppp NMI is enabled NMICON NMIVDDP If an external power supply of 3 3 V is used the user must disable Vppp detector by clearing bit NMICON NMIVDDP In power down mode the detector is switched off and Vppp detector will continue to function The EVR also has a power on reset POR detector for Vpp to ensure correct power up The voltage level detection of POR is 1 6 V The monitoring function is used in both active mode and power down mode During power up after Vpp exceeds 1 6 V the reset of EVR is extended by a delay that is typically 300 us In active mode Vpp is monitored mainly by the Vpp detector and a reset is generated when Vpp drops below 2 1 V In power down mode the Vpp is monitored by the POR and a reset is generated when
126. will cause the chip to enter slow down mode It is reset by the user The SD bit is a protected bit When the Protection Scheme is activated this bit cannot be written directly WKSEL 4 rw Wake up Reset Select Bit 0 Wake up without reset 1 Wake up with reset WKRS 5 rwh_ Wake up Indication Bit 0 No wake up occurred 1 Wake up has occurred This bit can only be set by hardware and reset by software User s Manual 8 6 V 0 2 2005 01 SCU V 0 4 _ lnfineon XC866 techno ogies Power Saving Modes Field Bits Type Description 0 7 r Reserved Returns 0 if read should be written with 0 Table 8 1 Reset Values of Register PMCONO Reset Source Reset Values Power on Res et Hardware Reset Brownout Reset 0000 00008 Watchdog Timer Reset 0100 0000g Power down Wake up Reset 0010 0000g PCON Power Control Register Reset Value 00 7 6 5 4 3 2 1 0 SMOD 0 GF1 GFO 0 IDLE rw r rw rw r rw The functions of the shaded bits are not described here Field Bits Description IDLE 0 rw Idle Mode Enable 0 Do not enter idle mode 1 Enter idle mode User s Manual 8 7 V 0 2 2005 01 SCU V 0 4 Infineon technologies XC866 MODPISEL Peripheral Input Select Register Power Saving Modes Reset Value 00
127. x x 0 1 2 The bounds of the variables are always specified where the register expression is first used e g x 0 27 and is repeated as needed The default radix is decimal Hexadecimal constants have a suffix with the subscript letter H e g Binary constants have a suffix with the subscript letter e g 11g When the extents of register fields groups of signals or groups of pins are collectively named in the body of the document they are represented as which defines a range from B to A for the named group Individual bits signals or pins are represented as NAME C with the range of the variable C provided in the text e g CFG 2 0 and TOS 0 Units are abbreviated as follows MHz Megahertz us Microseconds kBaud kbit 1000 characters bits per second MBaud Mbit 1 000 000 characters bits per second Kbyte 1024 bytes of memory Mbyte 1 048 576 bytes of memory In general the k prefix scales a unit 1000 whereas the prefix scales a unit by 1024 Hence the Kbyte unit scales the expression preceding it by 1024 The kBaud unit scales the expression preceding it by 1000 The M prefix scales by 1 000 000 or 1 048 576 and scales by 0 000001 For example 1 Kbyte is 1024 bytes 1 Mbyte is 1024 x 1024 bytes 1 kBaud kbit are 1000 characters bits per second 1 MBaud Mbit are 1 000 000 characters bits per second and 1 MHz is 1
128. 0 User s Manual Interrupt System V 0 5 5 19 V 0 2 2005 01 Infineon technologies XC866 Interrupt System The second pair of interrupt priority registers is SFRs IP1 and IPH1 IP1 Interrupt Priority Register 1 Reset Value 00 7 6 5 4 3 2 1 0 2 PCCIP1 PCCIPO PXM PX2 PSSC PADC nw rw rw rw rw rw rw rw IPH1 Interrupt Priority Register 1 High Reset Value 00 7 6 5 4 3 2 1 0 PCCIP2H PCCIPOH PXMH PX2H PSSCH PADCH nw rw rw rw rw rw rw rw Field Bits Type Description PADC 0 rw Priority Level for ADC Interrupt PADCH PSSC 1 rw Priority Level for SSC Interrupt PSSCH PX2 2 rw Priority Level for External Interrupt 2 PX2H PXM 3 rw Priority Level for External Interrupt 3 to 6 PXMH PCCIPO 4 rw Priority Level for CCU6 Interrupt Node Pointer 0 PCCIPOH PCCIP1 5 rw Priority Level for CCU6 Interrupt Node Pointer 1 PCCIP1H PCCIP2 6 rw Priority Level for CCU6 Interrupt Node Pointer 2 PCCIP2H PCCIP3 7 rw Priority Level for CCU6 Interrupt Node Pointer 3 PCCIP3H User s Manual Interrupt System V 0 5 5 20 V 0 2 2005 01 Cnfineon XC866 techno ogies Interrupt System 5 4 4 Interrupt Priority The respective bit fields of the interrupt priority registers together select one of the four priority
129. 0 0 VF DRC CHNR 0 R7 R6 Rb R4 R3 R2 R1 RO 0 0 VF CHNR rh rh rh rh 8 bit conversion with without accumulation 8 bit conversion without accumulation 76543210 76543210 76543210 76543210 R9 R8 R7 R6 R5 R4 R3 R2 0 VF CHNR R8 R7 R6 R5 R4 R3 R2 R4 RO 0 0 VF CHNR rh rh rh rh 10 bit conversion with without accumulation 8 bit conversion accumulated 9 bit 76543210 76543210 0 R8 R7 5 4 R8 2 R1 RO VF DRO CHNR rh rh 10 bit conversion without accumulation 76543210 76543210 10 R9 R8 R7 R6 R5 R4 R2 R1 RO VF DRO CHNR rh rh 10 bit conversion accumulated 11 bit Figure 13 11 Result Register View User s Manual 13 20 V 0 2 2005 01 ADC V 0 3 _ Infineon technologies XC866 13 4 8 Interrupts Analog to Digital Converter The ADC module provides 2 service request outputs SR 1 0 that can be activated by different interrupt sources The interrupt structure of the ADC supports two different types of interrupt sources Event Interrupts Activated by events of the request sources source interrupts or result registers result interrupts Channel Int
130. 0 3 rh User s Manual 13 49 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter Writing a 1 to a bit position in register VFCR clears the corresponding valid flag in registers RESRx RESRAx If a hardware event triggers the setting of a bit VFx and VFCx 1 the bit VFx is cleared software overrules hardware VFCR Valid Flag Clear Register Reset Value 00 7 6 5 4 3 2 1 0 0 VFC3 VFC2 VFC1 VFCO r WwW WwW Ww Field Bits Type Description VFCx X Clear Valid Flag for Result Register x x 0 3 0 No action 1 Bit VFR x is reset 0 7 4 r Reserved Returns 0 if read should be written with 0 The result control registers RCRx contain bits that control the behavior of the result registers and monitor their status RCRx x 0 3 Result Control Register x Reset Value 00 7 6 5 4 3 2 1 0 VFCTR WFR FEN IEN 0 DRCTR nw rw rw rw r rw User s Manual 13 50 V 0 2 2005 01 ADC V 0 3 _ Infineon technologies XC866 Analog to Digital Converter Field Bits Type Description DRCTR Data Reduction Control This bit defines how many conversion results are accumulated for data reduction It defines the reload value for bit DRC 0 The data reduction filter is disabled The reload value for DRC is 0 so the accumulation is done over 1 conversion 1 The
131. 0 Register 0 Reset Value 00 7 6 5 4 3 2 1 0 EXTR ENSI RF V 0 REQCHNR rh rh rh rh r rh User s Manual 13 40 V 0 2 2005 01 ADC V 0 3 Infineon technologies XC866 Analog to Digital Converter Field Bits Type Description REQCHNR 2 0 rh Request Channel Number This bit field indicates the channel number that will be or is currently requested rh Request Channel Number Valid This bit indicates if the data in REQCHNR RF ENSI and EXTR is valid Bit V is set when a valid entry is written to the queue input register QINRO or by an update by intermediate queue registers 0 The data is not valid 1 The data is valid RF 5 rh Refill This bit indicates if the pending request is discarded after being executed conversion start or if it is automatically refilled in the top position of the request queue 0 The request is discarded after conversion start 1 The request is refilled in the queue after conversion start ENSI 6 rh Enable Source Interrupt This bit indicates if a source interrupt will be generated when the conversion is completed The interrupt trigger becomes activated if the conversion requested by the source has been completed and ENSI 1 0 The source interrupt generation is disabled 1 The source interrupt generation is enabled EXTR 7 rh External Trigger This bit defines if the conversion request is sensitive to an external trigg
132. 01 Power Reset and Clock V 0 4 _ lnfineon XC866 techno ogies Power Supply Reset and Clock Management 7 2 4 Register Description PMCONO Power Mode Control Register 0 Reset Value See Table 7 3 7 6 5 4 3 2 1 0 0 WDTRST WKRS WKSEL SD PD WS r rwh rwh rw rw rwh rw The functions of the shaded bits are not described here Field Bits Description WS 1 0 rw Wake Up Source Select 00 No wake up is selected 01 Wake up source RXD is selected 10 Wake up source EXINTO is selected 11 Wake up source RXD or EXINTO is selected WKSEL 4 rw Wake Up Reset Select Bit 0 Wake up without reset 1 Wake up with reset WKRS 5 rwh Wake Up Indication Bit 0 No wake up occurred 1 Wake up has occurred This bit can only be set by hardware and reset by software WDTRST 6 Watchdog Timer Reset Indication Bit 0 No watchdog timer reset occurred 1 Watchdog timer reset has occurred This bit can only be set by hardware and reset by software 0 7 r Reserved Returns 0 if read should be written with 0 User s Manual 7 7 V 0 2 2005 01 Power Reset and Clock V 0 4 Infineon technologies XC866 Power Supply Reset and Clock Management Table 7 3 Reset Values of Register PMCONO Reset Source Reset Value Power on Reset Hardware Reset Brownout Reset 0000 0000 Watchdog Timer Reset 0100 0000g Power dow
133. 010 The timer value of T12 is stored in CC6nR after a rising edge at the input pin The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx 1011 The timer value of T12 is stored in CC6nR after a falling edge at the input pin The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx 1100 The timer value of T12 is stored in CC6nR after a rising edge at the input pin The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx 1101 The timer value of T12 is stored in CC6nR after a falling edge at the input pin The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx 1110 The timer value of T12 is stored in CC6nR after any edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after any edge at the input pin CCPOSx 1111 Reserved no capture or compare action User s Manual 12 76 V 0 2 2005 01 6 V 0 4 Infineon technologies XC866 Capture Compare Unit 6 12 3 6 Interrupt Control Registers ISL Capture Compare Interrupt Status Register Low Reset Value 00 7 6 5 4 3 2 1 0 T12 T12 ICC ICC ICC ICC ICC ICC PM OM 62F 62R 61F 61R 60F 60R rh rh rh rh rh rh rh rh Field Bits Type Description ICC60R 0 rh Capture Compare Match Rising Edge Flag ICC61R 2 In compare mode a compare match has been I
134. 01016 5 32 01106 fsys 64 01116 fsys 128 10006 fsys 256 10016 fsys 512 10106 fsys 1024 10116 fsys 2048 1100 Reserved 1101g Reserved 1110g Reserved 1111g Reserved 7 4 Reserved Returns 0 if read should be written with 0 Note Registers OSC CON PLL CON and CMCON are not reset during the watchdog timer reset User s Manual Power Reset and Clock V 0 4 7 17 V 0 2 2005 01 technologies Power Saving Modes 8 Power Saving Modes The power saving modes in the XC866 provide flexible power consumption through a combination of techniques including Stopping the CPU clock Stopping the clocks of individual system components Reducing clock speed of some peripheral components Power down of the entire system with fast restart capability After a reset the active mode normal operating mode is selected by default see Figure 8 1 and the system runs in the main system clock frequency From active mode different power saving modes can be selected by software They are Idle mode Slow down mode Power down mode ACTIVE any interrupt amp 0 0 EXINTO RXD pin clear SD bit POWER DOWN set IDLE bit any interrupt amp SD 1 SLOW DOWN amp SD 1 Figure 8 1 Transition between Power Saving Modes User s Manual 8 1 V 0 2 2005 01 SCU V 0 4 Cnfineon XC866 techno ogies Power Saving Modes 8 1 Functi
135. 1 GFO 0 IDLE rw r rw rw r rw The functions of the shaded bits are not described here Field Bits Type Description SMOD 7 rw Double Baud Rate Enable 0 Do not double the baud rate of serial interface in mode 2 1 Double baud rate of serial interface in mode 2 Note Depending on the programmed operating mode different paths are selected for the baud rate clock 10 1 4 1 Baud rate Generator The XC866 provides a dedicated baud rate generator to generate the baud rate for the UART module It has programmable 8 bit reload value and 3 bit prescaler The baud rate generator is clocked with a clock derived via prescaler from the input clock fpc The baud rate timer counts downwards and can be started or stopped through the baud rate control run bit BCON R Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 8 bit reload register each time it underflows The prescaler is selected by the bit field BCON BRPRE Register BG is the dual function Baud rate Generator Reload register Reading BG returns the contents of the timer while writing to BG always updates the reload register An auto reload of the timer with the contents of the reload register is performed each time BG is written to However if BCON R is cleared at the time a write operation to BG is performed the timer will not be reloaded until the first instruction cycle after BCON R is set
136. 10 Watchdog timer 9 1 9 8 Input frequency 9 3 Servicing 9 2 Time period 9 3 Watchdog timer reset 7 4 Window boundary 9 2 Wordline address 4 5 Write buffers 4 6 Write result phase 13 5 X XC866 register overview 3 13 XRAM 3 1 User s Manual 15 5 Keyword Index V 0 2 2005 01 _ Infineon technologies XC866 15 2 Register Index Register Index This section lists the references to the Special Function Registers of the XC866 A A 2 4 ADC PAGE 13 28 B B 2 4 BCON 10 12 BG 10 13 BRH 10 37 BRL 10 37 C CC63RH 12 43 CC63RL 12 43 CC63SRH 12 44 CC63SRL 12 44 CC6xRH x 0 2 12 37 CC6xRL x 0 2 12 37 CC6xSRH x 0 2 12 38 CC6xSRL x 0 2 12 38 CCU6 PAGE 12 26 CHCTRx x 0 7 13 36 CHINCR 13 52 CHINFR 13 52 CHINPR 13 53 CHINSR 13 53 CMCON 7 17 CMPMODIFH 12 47 CMPMODIFL 12 47 CMPSTATH 12 46 CMPSTATL 12 45 CONH 10 34 10 35 CONL 10 33 10 35 CRCR1 13 44 CRMR1 13 46 CRPR1 13 45 User s Manual D DPH 2 4 DPL 2 4 E EO 2 6 ETRCR 13 35 EVINCR 13 54 EVINFR 13 54 EVINPR 13 55 EVINSR 13 55 EXICONO 5 12 EXICON1 5 13 F FEAH 4 8 FEAL 4 8 G GLOBCTR 8 9 13 31 GLOBSTR 13 32 H HWBPDR 14 8 HWBPSR 14 8 ID 3 15 IENO 5 9 11 12 IEN1 5 10 IENH 12 85 IENL 12 84 INPCRO 13 37 INPH 12 89 INPL 12 88 IP 5 19 IP1 5 20 15 6 V 0 2 2005 01 _ Infineon technologies XC866 IPH 5 19 IPH1 5 20 IRCONO 5 14 IRCON1 5 15 ISH 12
137. 12MSELH 12 73 T12MSELL 12 72 T12PRH 12 36 T12PRL 12 36 T13H 12 41 T13L 12 41 T13PRH 12 42 T13PRL 12 42 T2CON 11 19 T2H 11 21 T2L 11 21 T2MOD 11 17 TBL 10 38 TCON 5 16 11 10 TCTROH 12 49 TCTROL 12 48 TCTR2H 12 54 TCTR2L 12 52 User s Manual Register Index TCTR4H 12 56 TCTR4L 12 55 THx x 2 0 1 11 8 TLx x 0 1 11 8 TMOD 11 11 TRPCTRH 12 61 TRPCTRL 12 60 V VFCR 13 50 W WDTCON 9 6 WDTH 9 7 WDTL 9 7 WDTREL 9 5 WDTWINB 9 7 15 8 V 0 2 2005 01
138. 2 6 12 MOV A Ri E6 E7 1 2 4 12 MOV A data 74 2 2 6 12 MOV Rn A F8 FF 1 2 4 12 MOV Rn dir A8 AF 2 4 8 24 MOV Rn data 78 7F 2 2 6 12 MOV dir A F5 2 2 6 12 MOV dir Rn 88 8F 2 4 8 24 MOV dir dir 85 3 4 10 24 MOV dir QRi 86 87 2 4 8 24 MOV dir Zdata 75 3 4 10 24 MOV Ri A F6 F7 1 2 4 12 MOV A6 A7 2 4 8 24 MOV Ri data 76 77 2 2 6 12 MOV DPTR data 90 3 4 10 24 MOVC A A DPTR 93 1 4 6 24 A A PC 83 1 4 6 24 MOVX A Ri E2 E3 1 4 6 24 User s Manual 2 12 V 0 2 2005 01 Processor Architecture V 0 3 Infineon technologies XC866 Processor Architecture Table 2 1 CPU Instruction Timing cont d Mnemonic Hex Code Bytes Number of fcc Cycles XC866 8051 no ws 1 ws MOVX A DPTR EO 1 4 6 24 MOVX Ri A F2 F3 1 4 6 24 MOVX DPTR A FO 1 4 6 24 PUSH dir CO 2 4 8 24 POP dir DO 2 4 8 24 C8 CF 1 2 4 12 C5 2 2 6 12 A Ri C6 C7 1 2 4 12 XCHD A Ri D6 D7 1 2 4 12 BOOLEAN CLRC C3 1 2 4 12 CLR bit C2 2 2 6 12 SETB C D3 1 2 4 12 SETB bit D2 2 2 6 12 CPLC B3 1 2 4 12 CPL bit B2 2 2 6 12 ANL C bit 82 2 4 8 24 ANL C bit BO 2 4 8 24 ORL C bit 72 2 4 8 24 ORL C bit AO 2 4 8 24 MOV C bit A2 2 2 6 12 MOV bit C 92 2 4 8 24 BRANCHING ACALL 11 11 gt 1 2 4 24 16 12 3 4 10 24 22 1 4 4 24 32 1 4 24 AJMP addr 11 01 gt
139. 23 Interrupt priority 5 21 Interrupt request flags 5 22 Interrupt response time 5 24 Interrupt source and vector 5 2 5 8 Interrupt system 5 1 Register description 5 9 J JTAG ID 14 9 15 2 V 0 2 2005 01 Infineon technologies XC866 K Kernel registers 6 5 Direction control register 6 7 Offset addresses 6 5 L Limit checking 13 17 LIN 10 14 10 18 Baud rate detection 10 17 Break field 10 15 Header transmission 10 16 LIN frame 10 14 LIN protocol 10 14 Synch byte 10 15 M Maskable interrupt 5 1 Extended 5 2 External 5 2 Internal 5 1 Memory organization 3 1 Special Function Registers 3 4 Address extension by mapping 3 4 Mapped 3 4 Standard 3 4 Address extension by paging 3 6 Local address extension 3 6 Save and restore 3 7 Minimum erase width 4 3 Modulation 12 13 Monitor mode control 14 2 Monitor RAM 14 2 Data 14 6 Stack 14 6 Monitor ROM 14 2 Multi channel mode 12 17 Multifold replications 4 4 Multiprocessor communication 10 7 N Non maskable interrupt 5 1 Events 5 1 User s Manual 15 3 Keyword Index O On Chip Debug Support 14 1 Register description 14 7 Register map 14 7 On chip oscillator 7 9 P PO register description 6 5 6 16 P1 register description 6 21 P2 register description 6 26 P3 register description 6 31 Parallel ports 6 1 Bidirectional port structure 6 3 Driver 6 2 6 7 General port structure 6 3 General register description 6 5 Input port structure 6 4 Ker
140. 3 Infineon BESS technologies Introduction The block diagram of the XC866 is shown in Figure 1 2 XC866 Internal Bus 8 Kbyte 5 BootROM N Y 7 lt gt 0 0 0 5 800 256 byte RAM A 64 byte monitor en HARI UN TL P1 0 P1 1 Hc RAM 1 5 1 7 gt AE voor _ 512 byteXRAM lt SSP sse KS 5 P20 P27 8 16 Flash ROM 2 K ADe V AREF XTALI Clock Generator um Vieno XTAL2 10 MHz On chip OSC OCDS P30 P37 PLL a 1 Includes 1 Kbyte monitor ROM 2 Includes additional 4 Kbyte Flash Figure 1 2 XC866 Block Diagram User s Manual 1 4 V 0 2 2005 01 Intro V 0 3 866 technologies Introduction 1 2 Pin Configuration The pin configuration of the XC866 based on the PG TSSOP 38 package is shown in Figure 1 3 MBC 10 38 RESET PO 3 SCLK 1 COUT
141. 3 state the passive level defined in register PSLR is COUT62PS 5 driven by the output pin Bits CC6xPS and COUT6xPS COUT63PS 6 are related to T12 while bit CC63PS is related to T13 1 0 The corresponding compare output drives passive level while CC6xST is O 1 The corresponding compare output drives passive level while CC6xST is 1 In capture mode these bits are not used 131 2 7 rwh 13 Inverted Modulation Bit T131M inverts the T13 signal for the modulation of the CC6x and COUT6x x 0 2 signals 0 T13 output is not inverted 1 T13 output is inverted for further modulation 1 These bits have shadow bits and are updated in parallel to the capture compare registers of T12 and T13 respectively A read action targets the actually used values whereas a write action targets the shadow bits 2 This bit has a shadow bit and is updated in parallel to the compare and period registers of T13 A read action targets the actually used values whereas a write action targets the shadow bit User s Manual CCUG V 0 4 12 46 V 0 2 2005 01 techno ogies Capture Compare Unit 6 Register CMPMODIF contains control bits that allow modification by software of the capture compare state bits CMPMODIFL Compare State Modification Register Low Reset Value 00 7 6 5 4 3 2 1 0 0 MCC 0 MCC 63 62 61 60 r Ww r Ww WwW Ww CMPMODIFH
142. 37 V 0 2 2005 01 technologies Serial Interfaces 10 3 4 4 Transmit and Receive Buffer Register The SSC transmitter buffer register TB contains the transmit data value STE Buffer Register Low Reset Value 00 7 6 5 4 3 2 1 0 VALUE Field Bits Type Description TB VALUE 7 0 nw Transmit Data Register Value TB VALUE is the data value to be transmitted Unselected bits of TB are ignored during transmission The SSC receiver buffer register RB contains the receive data value RBL Receiver Buffer Register Low Reset Value 00 7 6 5 4 3 2 1 0 VALUE rh Field Bits Type Description RB VALUE 7 0 rh Receive Data Register Value RB contains the received data value RB VALUE Unselected bits of RB will not be valid and should be ignored User s Manual 10 38 V 0 2 2005 01 Serial Interfaces V 0 3 Cnfineon XC866 techno ogies Timers 11 Timers The XC866 provides three 16 bit timers Timer 0 Timer 1 and Timer 2 They are useful in many timing applications such as measuring the time interval between events and generating signals at regular intervals Timer 0 and Timer 1 Features Four operational modes Mode 0 13 bit timer Mode 1 16 bit timer Mode 2 8 bit timer with auto reload Mode 3 Two 8 bit timers Timer 2 Features e Selectable up down counting 16 bit auto reload m
143. 3R is set if an edge of signal T13HR is detected 0 7 4 r Reserved Returns 0 if read should be written with 0 User s Manual 12 54 V 0 2 2005 01 CCU6 V 0 4 _ nfineon XC866 techno ogies Capture Compare Unit 6 Register TCTR4 allows the software control of the run bits T12R and T13R through independent set and reset conditions Furthermore the timers can be reset while running and the bits STE12 and STE13 can be controlled by software TCTR4L Timer Control Register 4 Low Reset Value 00 7 6 5 4 3 2 1 0 T12 T12 0 DT T12 T12 T12 STD STR RES RES RS RR r Field Bits Type Description T12RR 0 w Timer T12 Run Reset Setting this bit resets the T12R bit 0 T12R is not influenced 1 T12R is cleared T12 stops counting T12RS 1 Ww Timer T12 Run Set Setting this bit sets the T12R bit 0 T12R is not influenced 1 T12R is set T12 counts T12RES 2 Timer T12 Reset 0 No effect on T12 1 The T12 counter register is reset to zero The switching of the output signals is according to the switching rules Setting of T12RES has impact on bit T12R DTRES 3 Ww Dead Time Counter Reset 0 No effect on the dead time counters 1 The three dead time counter channels are reset to zero T12STR 6 Timer T12 Shadow Transfer Request 0 No action 1 STE12 is set enabling the shadow transfer T12STD 7 Ww Timer
144. 63 1 2 37 P3 5 COUT62 0 POA4IMTSR 1 CC62 1 3 36 P34 CC62 0 PO 5 MRST 1 EXINTO O COUT62 1 4 35 P3 3 COUT61 0 XTAL2 5 34 P32 CC61 0 XTAL1 6 33 P3 1 COUT60 0 Vasc 7 32 P3 0 CC60 0 Voc 8 311 P37 EXINTA4 COUT63 0 P1 6 CCPOS1 1 T12HR O EXINTe 9 30 P3 6 CTRAP OIRSTOUT P1 7 CCPOS2 1 T13HR O 10 XC866 29 P1 5 CCPOSO 1 EXINT5 TMS 11 28 P1 1 EXINT3 TDO 1 TXD 0 PO O TCK O T12HR 1 CC61 1 CLKOUT 12 27 P10 RXD O T2EX PO 2 CTRAP 2700 O TXD 1 13 26 P2 7 AN7 PO 1 TDI O T13HR 1 RXD 1 COUT61 1 14 25 2 0 50 O EXINT1 T12HR 2 TCK 1 ANO 15 24 Vacno P2 1 CCPOS1 O EXINT2 T13HR 2 TDI 1 AN1 16 23 P2 6 AN6 P2 2 CCPOS2 1 AN2 17 22 P2 5 AN5 Vopp _ 18 21 P24 AN4 Vsp 19 20 P2 3 AN3 Figure 1 3 XC866 Pin Configuration PG TSSOP 38 Package top view User s Manual 1 5 V 0 2 2005 01 Intro V 0 3 Cnfineon XC866 techno ogies Introduction 1 3 Pin Definitions and Functions After reset all pins are configured as input with one of the following Pull up device enabled e Pull down device enabled PD High impedance with both pull up and pull down devices disabled Hi Z The functions and default states of the XC866 external pins are provided in Table 1 2 Table 1 2 Pin Definitions and Functions Symbol Pin Type Reset Function Number State PO Port 0 Port 0 is a 6 bit bidirectional general purpos
145. 78 ISL 12 77 ISRH 12 83 ISRL 12 82 ISSH 12 81 ISSL 12 80 L LCBR 13 56 M MCMCTR 12 70 MCMOUTH 12 69 MCMOUTL 12 67 MCMOUTSH 12 66 MCMOUTSL 12 65 MMBPCR 14 7 MMCR 14 7 MMCR2 14 7 MMDR 14 7 MMICR 14 7 MMSR 14 7 MODCTRH 12 58 MODCTRL 12 57 MODPISEL 8 8 10 13 N NMICON 5 11 NMISR 5 17 O OSC_CON 7 14 8 10 P PO ALTSELO 6 18 PO ALTSEL1 6 18 PO DATA 6 16 PO DIR 6 16 PO OD 6 17 User s Manual Register Index PO PUDEN 6 18 PO PUDSEL 6 17 P1 ALTSELO 6 23 P1 ALTSEL1 6 23 P1 DATA 6 21 P1 DIR 6 21 P1 OD 6 22 P1 PUDEN 6 23 P1 PUDSEL 6 22 P2 DATA 6 26 P2 PUDEN 6 27 P2 PUDSEL 6 26 P3 ALTSELO 6 33 ALTSEL1 6 33 P3 DATA 6 31 P3 DIR 6 31 P3 OD 6 32 P3 PUDEN 6 33 P3 PUDSEL 6 32 PASSWD 3 12 PCON 2 7 8 7 10 10 PISEL 10 32 PISELOH 12 33 PISELOL 12 31 PISEL2 12 34 PLL CON 7 15 7 7 8 6 9 8 PMCON1 8 8 13 7 PORT_PAGE 6 11 PRAR 13 33 PSLR 12 63 PSW 2 5 Px ALTSELn 6 10 Px DATA 6 6 Px DIR 6 7 Px OD 6 7 Px PUDEN 6 8 Px PUDSEL 6 8 Q QORO 13 40 QBURO 13 42 QINRO 13 43 15 7 V 0 2 2005 01 _ Infineon technologies XC866 QMRO 13 38 QSRO 13 40 R RBL 10 38 RC2H 11 20 2 11 20 RCRx x 0 3 13 50 RESRAXH x 0 3 13 49 RESRAXxL x 0 3 13 49 x 0 3 13 49 RESRXxL x 0 3 13 49 S SBUF 10 7 SCON 5 17 10 8 SCU PAGE 3 10 SP 2 4 SYSCONO 3 4 T T12DTCH 12 39 T12DTCL 12 39 T12H 12 35 T12L 12 35 T
146. 866 techno ogies Processor Architecture 2 Processor Architecture The XC866 is based on a high performance 8 bit Central Processing Unit CPU that is compatible with the standard 8051 processor While the standard 8051 processor is designed around a 12 clock machine cycle the XC866 CPU uses a 2 clock machine cycle This allows fast access to ROM or RAM memories without wait state Access to the Flash memory however requires an additional wait state one machine cycle See Section 2 3 The instruction set consists of 45 one byte 41 two byte and 14 three byte instructions The XC866 CPU provides a range of debugging features including basic stop start single step execution breakpoint support and read write access to the data memory program memory and SFRs Features Two clocks per machine cycle architecture for memory access without wait state Wait state support for Flash memory Program memory download option 15 source 4 level interrupt controller Two data pointers Power saving modes Dedicated debug mode and debug signals Two 16 bit timers Timer 0 and Timer 1 Full duplex serial port UART User s Manual 2 1 V 0 2 2005 01 Processor Architecture V 0 3 866 technologies Processor Architecture 2 1 Functional Description Figure 2 1 shows the CPU functional blocks The CPU consists of the instruction decoder the arithmetic section and the program control section Each pro
147. AP Control modes for multi channel AC drives Output levels can be selected and adapted to the power stage User s Manual 12 1 V 0 2 2005 01 6 V 0 4 Infineon XC866 technologies i Capture Compare Unit 6 module kemel compare decoder T12 control channel 1 Bd PE channel 2 clock control start E Z 5 9S 5 T13 channel 8 8 8 8 8 2 interrupt 3 21242 3 1 8 8 control input output control 88388883 81818 5 port control T12HR T13HR 4 S 2 V4 4 AJ NZ NA Ad NA CCU6_block_diagram Figure 12 1 CCU6 Block Diagram User s Manual 12 2 V 0 2 2005 01 CCU6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 Functional Description 12 1 1 Timer T12 The timer T12 is built with three channels in capture compare mode The input clock for timer T12 can be from to a maximum of fecyg 128 and is configured by bit field T12CLK In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler of T12 if bit T12PRE 1 The timer period compare values passive state selects bits and passive levels bits are written to shadow registers and not directly to the actual registers while the read access targets the registers actually used except for the three compare channels where both
148. ATA or used by the same or another peripheral as input data This enables testing of peripheral functions or provides additional connections between on chip peripherals via the same pin without external wires Internal Bus Px PUDSEL Pull up Pull down Select Register Control Logic Px PUDEN Pull up Pull down Enable Register OD Open Drain Control Register Px DR Diredion Register Altemate Select Register ALTSEL1 y Altemate Seled Register Pull Device AltDataOut 2 Output gt 10 AltDataOuti gt o m gt 00 Input Px Data Data Register Driver 4 AltDataln Schmit Trigger Pad Figure 6 1 General Structure of Bidirectional Port User s Manual 6 3 V 0 2 2005 01 Parallel Ports V 0 3 techno ogies Parallel Ports Figure 6 2 shows the structure of an input only port pin Each P2 pin can only function in input mode The actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt Trigger device and can be read via the register P2 DATA Each can also be programmed to activate an internal weak pull up or pull down device Register P2 PUDSEL selects whether a pull up or the pull down device is activated while register P2 PUDEN enables disables the pull device The analog input Analogln bypasses the digital circuitry and Schmitt Trigger device for
149. BSTR Global Status Register Reset Value 00 7 6 5 4 3 2 1 0 0 CHNR 0 SAMPLE BUSY r rh r rh rh Field Bits Type Description BUSY 0 rh Analog Part Busy This bit indicates that a conversion is currently active 0 The analog part is idle 1 A conversion is currently active SAMPLE 1 rh Sample Phase This bit indicates that an analog input signal is currently sampled 0 The analog part is not in the sampling phase 1 The analog part is in the sampling phase CHNR 5 3 rh Channel Number This bit field indicates which analog input channel is currently converted This information is updated when a new conversion is started 0 2 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual 13 32 V 0 2 2005 01 ADC V 0 3 _ nfineon XC866 techno ogies Analog to Digital Converter 13 7 2 Priority and Arbitration Register Register PRAR contains bits that define the request source priority and the conversion start mode It also contains bits that enable disable the conversion request treatment in the arbitration slots PRAR Priority and Arbitration Register Reset Value 00 7 6 5 4 3 2 1 0 ASEN1 ASENO 0 ARBM CSM1 PRIO1 CSMO PRIOO rw rw r rw rw rw rw rw Field Bits Type Description PRIOO 0 rw Priority of Request Source 0 This bit defines the priority of the sequential request source 0 0 Low priority 1 High priority CSMO
150. C V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter 13 4 7 2 Limit Checking The limit checking and the data reduction filter are based on a common add subtract structure The incoming result is compared with BOUNDO then with BOUND1 Depending on the result flags lower than compare the limit checking unit can generate a channel interrupt It can become active when the valid result of the data reduction filter is stored in the selected result register new result in buffer compare result with BOUNDO compare result with BOUND1 BOUNDO rw BOUND1 rw T channel data reduction filter limit checking interupt Figure 13 9 Limit Checking Flow User s Manual 13 17 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter 13 4 7 3 Data Reduction Filter Each result register can be controlled to enable or disable the data reduction filter The data reduction block allows the accumulation of conversion results for anti aliasing filtering or for averaging A pseudo parallel sampling on two analog inputs is possible by converting the channels B Ain a quick sequence The result register for A stores the sum of both conversions of channel A and the result register B works similarly for channel B e Ee Ce Fe Pe ee E Ee 9 D contin ize data reduction
151. CC62R 4 detected while T12 was counting up In capture mode a rising edge has been detected at the input CC6x x 0 2 0 The event has not occurred since this bit was reset 1 The event described above has been detected ICC60F 1 rh Capture Compare Match Falling Edge Flag ICC61F 3 In compare mode a compare match has been ICC62F 5 detected while T12 was counting down In capture mode a falling edge has been detected at the input 0 2 0 The event has not occurred since this bit was reset 1 The event described above has been detected T120M rh Timer T12 One Match Flag 0 A timer T12 one match while counting down has not been detected since this bit was reset 1 A timer T12 one match while counting down has been detected T12PM rh Timer T12 Period Match Flag 0 A timer T12 period match while counting up has not been detected since this bit was reset 1 A timer T12 period match while counting up has been detected User s Manual 6 V 0 4 12 77 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 ISH Capture Compare Interrupt Status Register High Reset Value 00 7 6 5 4 3 2 1 0 TRP TRP T13 T13 STR IDLE WHE CHE S E PM CM rh rh rh rh rh rh rh rh Field Bits Type Description T13CM 0 rh Timer T13 Compare Match Flag 0 A timer T13 compare match has not been detected since this bit was reset 1 A timer T13 compare match has
152. CCG2R if enabled by bit ENCC62R or for bit ICC62F if enabled by bit ENCC62F 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPCHE 7 6 rw Interrupt Node Pointer for the CHE Interrupt This bit field defines the interrupt output line which is activated due to a set condition for bit CHE if enabled by bit ENCHE or for bit STR if enabled by bit ENSTR 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected E AREA Interrupt Node Pointer Register High Reset Value 39 7 6 5 4 3 2 1 0 0 T13 12 r rw IW rw User s Manual 12 89 V 0 2 2005 01 CCUG V 0 4 _ Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description INPERR 1 0 Interrupt Node Pointer for Error Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit TRPF if enabled by bit or for bit WHE if enabled by bit ENWHE 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPT12 3 2 Interrupt Node Pointer for Timer T12 In
153. Channel Result trigger interrupt interrupt interrupt Y Sample Phase Conversion Phase Y Y fpc L eee eee BUSY Bit SAMPLE Bit Write Result Phase twr Figure 13 3 Conversion Timing User s Manual 13 4 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter Synchronization Phase period is required for synchronization between the conversion start trigger from the digital part and the beginning of the sample phase in the analog part The BUSY and SAMPLE bits will be set with the conversion start trigger Sample Phase ts During this period the analog input voltage is sampled The internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted The analog voltage is internally fed to a voltage comparator With the beginning of the sampling phase the SAMPLE and BUSY flags in register GLOBSTR are set The duration of this phase is common to all analog input channels and is controlled by bit field STC in register INPCRO ts 2 STC x 13 1 Conversion Phase During the conversion phase the analog voltage is converted into an 8 bit or 10 bit digital value using the successive approximation technique with a binary weighted capacitor network At the beginning of the conversion phase t
154. Compare State Modification Register High Reset Value 00 7 6 5 4 3 2 1 0 0 MCC 0 MCC MCC MCC 63R 62R 61R 60R r Ww r Ww Ww Ww Field Bits Type Description mcceos 0 w Capture Compare Status Modification Bits 61 1 1 These bits are used to set MCC6xS or reset MCC62s 2 MCC6xR the corresponding CC6xST bits by MCC63S 6 software MCC60R2 0 This feature allows the user to individually change the MCC61R2 1 status of the output lines by software e g when the MCC62R2 2 corresponding compare timer is stopped This enables MCC63R2 6 a manipulation of CC6xST bits by a single data write action MCC6xR MCC6xS 0 0 Bit CC6xST is not changed 0 1 Bit CC6xST is set 1 0 Bit CC6xST is reset 1 21 Reserved toggle 0 5 3 r Reserved 7 Returns 0 if read should be written with 0 1 This bit field is contained in the Compare State Modification Register Low 2 This bit field is contained in the Compare State Modification Register High User s Manual 12 47 V 0 2 2005 01 6 V 0 4 techno ogies Capture Compare Unit 6 Register TCTRO controls the basic functionality of both timers T12 and T13 TCTROL Timer Control Register 0 Low Reset Value 00 7 6 5 4 3 2 1 0 CTM CDIR STE12 T12R 112 T12CLK PRE nw rh rh rh nw rw Field Bits Type Description T12CLK 2 0 rw Timer T12 Input Clock Select Selects the input clock for timer T12 which is derived fr
155. D Timer Mode Register Reset Value 00 7 6 5 4 3 2 1 0 GATE1 0 1 GATEO 0 TOM nw r IW rw r rw Field Bits Description TOM 1 0 1 0 Mode select bits T1M 1 0 5 4 TOM T1M Function 1 0 00 13 bit timer M8048 compatible mode 01 16 bit timer 10 8 bit auto reload timer 11 Timer 0 Timer 0 is divided into two parts TLO is an 8 bit timer controlled by the standard Timer O control bits and THO is the other 8 bit timer controlled by the standard Timer 1 control bits Timer 1 TL1 and TH1 are held Timer 1 is stopped GATEO 3 rw Timer 0 Gate Flag 0 Timer 0 will only run if TCON TRO 1 software control 1 Timer 0 will only run if EXINTO pin 1 hardware control and is set GATE1 7 rw Timer 1 Gate Flag 0 Timer 1 will only run if TCON TR1 1 software control 1 Timer 1 will only run if EXINT1 pin 1 hardware control and is set User s Manual 11 11 V 0 2 2005 01 Timers V 0 4 techno ogies Timers Field Bits Description 0 2 6 r Reserved Returns 0 if read should be written with 0 Register IENO contains bits that enable interrupt operations in Timer 0 and Timer 1 IENO Interrupt Enable Register Reset Value 00 7 6 5 4 3 2 1 0 EA 0 ET2 ES ET1 EX1 ETO EXO rw r rw rw rw rw rw rw The functions of the shaded bits are not described here Field Bits Description ETO
156. D Flash programming is in progress 1 DPTRO is not pointing to valid D Flash WL address is incremented by 204 Flash Timer is enabled NMICON NMIFLASHTIMER 1 Stack size 8 required Resources PSW CY A SCU PAGE DPTR1 used destroyed Resources RO R7 of Register Bank IRAM address 184 1 1 reserved IRAM address 36 3Dy Machine cycles 904 taken 2 User s Manual 4 11 V 0 2 2005 01 Flash Memory V 0 3 techno ogies Flash Memory 1 The data in the reserved resources must not be altered throughout the programming period including Flash Timer NMI servicing to ensure correct programming flow 2 Estimated value without wait state Upon completing the D Flash programming sequence the Flash Timer NMI will be disabled NMICON NMIFLASHTIMER 0 by the program subroutine For end of D Flash programming indication the user can check one of the following Bit NMICON NMIFLASHTIMER is cleared of Register Bank IRAM address 1 is A manual check on the D Flash data is necessary to determine the success of the programming via using the MOVC instruction to read out the D Flash data User s Manual 4 12 V 0 2 2005 01 Flash Memory V 0 3 Infineon technologies 4 7 2 D Flash Erasing The Flash erase subroutine can be called by the user to erase the sector s of the D Flash bank For each erasing sequence i
157. DIR P5 1g Output PO ALTSELO P5 0g PO ALTSEL1 P5 1g User s Manual 12 24 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Table 12 2 CCU6 I O Control Selection cont d Port Lines PISEL Register Bit Input Output Control Register Bits P3 7 COUT63 0 DIR P7 1g Output ALTSELO P7 1g P3 ALTSEL1 P7 7 0g PO 3 COUT63 1 DIR P3 1g Output PO ALTSELO P3 0g PO ALTSEL1 P3 7 1g P1 6 T12HR 0 IST12HR 00 P1 DIR P6 Input PO 0 T12HR 1 IST12HR 01 DIR PO Input P2 0 T12HR 2 IST12HR 10 P2 DIR PO Input 1 7 113 0 IST13HR 00 P1 DIR P7 Input PO 1 T13HR 1 IST13HR 01 PO DIR P1 Input P2 1 T13HR 2 IST13HR 10 P2 DIR P1 Input User s Manual 12 25 V 0 2 2005 01 CCUG V 0 4 techno ogies Capture Compare Unit 6 12 2 Register Map The CCU6 SFRs are located the standard memory area 0 and organized into 4 pages The CCU6_PAGE register is located at address It contains the page value and the page control information CCU6_PAGE Page Register for CCU6 Reset Value 00 7 6 5 4 3 2 1 0 OP STNR 0 PAGE w w r w Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page address When read the value indicates the currently active page addr y x 1
158. E1 2 4 8 24 User s Manual 2 13 V 0 2 2005 01 Processor Architecture V 0 3 Cnfineon XC866 techno ogies Processor Architecture Table 2 1 CPU Instruction Timing cont d Mnemonic Hex Code Bytes Number of fcc Cycles XC866 8051 no ws 1 ws LJMP addr 16 02 d 4 10 24 SJMP rel 80 2 4 8 24 JC rel 40 2 4 8 24 JNC rel 50 2 4 8 24 JB bit rel 20 d 4 10 24 JNB bit rel 30 9 4 10 24 JBC bit rel 10 3 4 10 24 JMP A DPTR 73 1 4 4 24 JZ rel 60 2 4 8 24 JNZ rel 70 2 4 8 24 CJNE 5 3 4 10 24 CJNE A d rel 4 3 4 10 24 CJNE Rn d rel B8 BF d 4 10 24 CJNE Ri d rel B6 B7 3 4 10 24 DJNZ D8 DF 2 4 8 24 DJNZ dir rel D5 3 4 10 24 MISCELLANEOUS NOP 00 1 2 4 12 ADDITIONAL INSTRUCTIONS MOVC DPTR A A5 1 4 4 TRAP A5 1 2 tbd User s Manual 2 14 V 0 2 2005 01 Processor Architecture V 0 3 Infineon technologies 3 Memory Organization XC866 Memory Organization The XC866 CPU operates in the following five address spaces 8 Kbytes of Boot ROM program memory 256 bytes of internal RAM data memory 512 bytes of XRAM memory XRAM can be read written as program memory or external data memory a 128 byte Special Function Register area e 8 16 Kbytes of Flash program memory Flash devices or 8 16 Kbytes of ROM program memory with additional 4 Kbytes of Flash ROM devices Figure 3 1
159. Figure 11 6 A logic 1 at pin T2EX sets the Timer 2 to up counting mode The timer therefore counts up to a maximum of FFFF Upon overflow bit TF2 is set and the timer register is reloaded with a 16 bit reload value of the RC2 register A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence This reload value is chosen by software prior to the occurrence of an overflow condition A logic 0 at pin T2EX sets the Timer 2 to down counting mode The timer counts down and underflows when the THL2 value reaches the value stored at register RC2 The underflow condition sets the TF2 flag and causes FFFFy to be reloaded into the THL2 User s Manual 11 14 V 0 2 2005 01 Timer V 0 4 technologies register fresh down counting sequence is started and the timer counts down as in the previous counting sequence In this mode bit EXF2 toggles whenever an overflow or an underflow condition is detected This flag however does not generate an interrupt request FFFF y Down count reload prescaler Overflow T2EX Figure 11 6 Auto Reload Mode 1 User s Manual 11 15 V 0 2 2005 01 Timer V 0 4 techno ogies Timer 11 2 2 Capture Mode In order to enter the 16 bit capture mode bits CP RL2 and 2 in register T2CON must be set In this mode the down count function must remain disabled The timer
160. G V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description DTRO 4 rh Dead Time Run Indication Bits DTR1 5 Bits DTRx x 0 2 indicate the status of the dead DTR2 6 time generation for each compare channel 0 1 2 of timer T12 0 The value of the corresponding dead time counter channel is 0 1 The value of the corresponding dead time counter channel is not O 0 3 7 r Reserved Returns 0 if read should be written with 0 Note The dead time counters are clocked with the same frequency as T12 This structure allows symmetrical dead time generation in center aligned and in edge aligned PWM mode A duty cycle of 50 leads to CC6x COUT6x is switched on for 0 5 period dead time Note The dead time counters are not reset by bit T12RES but by bit DTRES User s CCUSG Manual 0 4 12 40 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 3 3 Timer 13 Related Registers The generation of the patterns for a single channel PWM is based on timer T13 The registers related to timer T13 can be concurrently updated with well defined conditions in order to ensure consistency of the PWM signal Timer T13 can be synchronized to several timer T12 events Timer T13 supports only compare mode on its compare channel CC63 T13L Timer T13 Counter Register Low Reset Value 00 7 6 5 4 3 2 1 0
161. GPI P3 DATA P3 ALT 1 ALT 2 ALT 3 Output GPO P3 DATA P3 ALT1 COUTe61 0 CCU6 ALT2 P3 4 Input GPI P3 DATA P4 ALT 1 62 0 CCU6 ALT 2 ALT 3 Output GPO DATA P4 ALT1 CC62 0 CCU6 ALT2 5 Input GPI P3 DATA P5 ALT 1 ALT 2 ALT 3 Output GPO P3 DATA P5 ALT1 COUT62 0 CCU6 ALT2 User s Manual 6 29 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 Parallel Ports Table 6 12 Port 3 Input Output Functions cont d PortPin Input Output Select Connected Signal s From to Module P3 6 Input GPI P3 DATA P6 ALT1 0 CCU6 ALT 2 ALT 3 Output GPO P3 DATA P6 ALT1 ALT2 RSTOUT Internal reset P3 7 Input GPI P3 DATA P7 ALT 1 ALT 2 EXINT4 External interrupt 4 ALT 3 Output GPO P3 DATA P7 ALT1 COUT63 CCU6 ALT2 User s Manual 6 30 V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon XC866 techno ogies Parallel Ports 6 6 2 Register Description P3 DATA Port 3 Data Register Reset Value 00 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 PO nw rw rw rw rw rw rw rw Field Bits Description Pn n rw Port 3 Pin n Data Value n 0 7 0 Port 3 pin data value 0 default 1 Port 3 pin n data value 1 P3_DIR Port 3 Direction Register Reset Va
162. JTAG CCU6 UART and the SSC P1 0 27 PU RXD_0 UART Receive Input T2EX Timer 2 External Trigger Input P1 1 28 PU EXINT3 External Interrupt Input 3 1 JTAG Serial Data Output TXD 0 UART Transmit Output P1 5 29 PU CCPOSO 1 CCU6 Hall Input 0 5 External Interrupt Input 5 P1 6 9 PU CCPOS1 1 CCU6 Hall Input 1 T12HR 0 CCU6 Timer 12 Hardware Run Input EXINT6 External Interrupt Input 6 P1 7 10 PU CCPOS2 1 CCU6 Hall Input 2 T13HR O CCU6 Timer 13 Hardware Run Input P1 5 and P1 6 can be used as a software chip select output for the SSC User s Manual Intro 0 3 0 2 2005 01 Infineon technologies XC866 Introduction Table 1 2 Pin Definitions and Functions cont d Symbol Pin Type Reset Function Number State P2 Port 2 Port 2 is an 8 bit general purpose input only port It can be used as alternate functions for the digital inputs of the JTAG and CCUG It is also used as the analog inputs for the ADC P2 0 15 Hi Z CCPOSO 0 CCU6 Hall Input 0 EXINT1 External Interrupt Input 1 T12HR 2 CCU6 Timer 12 Hardware Run Input TCK 1 JTAG Clock Input ANO Analog Input 0 P2 1 16 Hi Z CCPOS1 0 CCU6 Hall Input 1 EXINT2 External Interrupt Input 2 T13HR 2 CCU6 Timer 13 Hardware Run Input TDI 1 JTAG Serial Data Input AN1 Analog Input 1 P2 2 17 Hi Z CCPOS2 0 CCU6 Hall Input 2 CTRAP 1 CCUG6 Trap Input AN2 Analog Input 2 P2 3 20 Hi Z AN3 Analog Input 3 P2 4 21 Hi Z
163. NFR If a hardware event triggers the setting of a bit EVINFx and EVINCx 1 the bit EVINFx is cleared software overrules hardware EVINCR Event Interrupt Clear Flag Register Reset Value 00 7 6 5 4 1 0 EVINC7 EVINC6 EVINC5 EVINC4 0 EVINC1 EVINCO Ww Ww Ww Ww r Ww Ww Field Bits Type Description EVINCx 1 0 Clear Interrupt Flag for Event x 0 1 4 7 7 4 0 No action 1 Bit EVINFR x is reset 0 3 2 r Reserved Returns 0 if read should be written with 0 User s Manual 13 54 V 0 2 2005 01 ADC V 0 3 Infineon technologies XC866 Analog to Digital Converter Writing a 1 to a bit position in register EVINSR sets the corresponding event interrupt flag in register EVINFR and generates an interrupt pulse if the interrupt is enabled EVINSR Event Interrupt Set Flag Register Reset Value 00 7 6 5 4 1 0 EVINS7 EVINS6 EVINS5 EVINS4 0 EVINS1 EVINSO Ww r Ww Field Bits Type Description EVINSx 1 0 Set Interrupt Flag for Event x 0 1 4 7 7 4 0 No action 1 Bit EVINFR x is set 3 2 Reserved Returns 0 if read should be written with 0 The bits in register EVINPR define the service request output line SRx x 0 or 1 that is activated if an event interrupt is generated EVINPR Event Interrupt Node Pointer Register Reset Value 00
164. NT ASENO 0 ARBM CSM1 PRIO1 CSMO PRIOO Priority and Arbitration Register Type rw rw r rw rw rw rw rw CDy ADC_LCBR Reset 7 Bit Field BOUND1 BOUNDO Limit Check Boundary Register Type rw rw User s Manual 3 17 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 5 ADC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 ADC_INPCRO Reset 00 Bit Field STC Input Class Register 0 Type rw CFy ADC_ETRCR Reset 00 Bit Field SYNEN SYNEN ETRSEL1 ETRSELO External Trigger Control Register 1 0 rw rw rw rw RMAP 0 Page 1 ADC CHCTRO Reset 00 Bit Field 0 LCC 0 RESRSEL Channel Control Register 0 Type r rw r rw ADC CHCTR1 Reset 00 Bit Field 0 LCC 0 RESRSEL Channel Control Register 1 Type r rw r rw CCy ADC_CHCTR2 Reset 00 Bit Field 0 LCC 0 RESRSEL Channel Control Register 2 Type r rw r rw CDy ADC_CHCTR3 Reset 00 Bit Field 0 LCC 0 RESRSEL Channel Control Register 3 Type r rw r rw CEy ADC_CHCTR4 Reset 00 Bit Field 0 LCC 0 RESRSEL Channel Control Register 4 Type r rw r rw CFy ADC CHCTR5 Reset 00 Bit Field 0 LCC 0 RESRSEL Channel Control Register 5 Type r rw r rw D2u ADC CHCTR6 Reset 00 Bit Field 0 LCC 0 RE
165. O rwh External Interrupt 0 Request Flag Set by hardware when external interrupt O edge is detected Cleared by hardware when the processor vectors to interrupt routine IT1 External Interrupt 1 Level Edge Trigger Control Flag 0 Low level triggered external interrupt 1 is selected 1 Falling edge triggered external interrupt 1 is selected IE1 rwh External Interrupt 1 Request Flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when the processor vectors to interrupt routine TFO rwh Timer 0 Overflow Flag Set by hardware on Timer Counter 0 overflow Cleared by hardware when processor vectors to interrupt routine User s Manual Interrupt System V 0 5 5 16 V 0 2 2005 01 _ Infineon technologies XC866 Interrupt System Field Bits Type Description TF1 7 rwh Timer 1 Overflow Flag Set by hardware on Timer Counter 1 overflow Cleared by hardware when processor vectors to interrupt routine SCON Serial Channel Control Register Reset Value 00 7 6 5 4 3 2 1 0 SMO SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rwh rwh rwh The functions of the shaded bits are not described here Field Bits Description RI 0 rwh Serial Interface Receiver Interrupt Flag Set by hardware if a serial data byte h
166. PO ALT1 CLKOUT On chip OSC ALT2 CC61 1 CCU6 PO 1 Input PO DATA P1 ALT1 TDI 0 JTAG ALT2 T13HR 1 CCU6 ALT3 RXD_1 UART Output GPO PO DATA P1 ALT1 ALT2 COUT61 1 CCU6 User s Manual 6 14 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 Parallel Ports Table 6 4 Port 0 Input Output Functions cont d Port Pin Input Output Select Connected Signal s From to Module P0 2 Input GPI PO DATA P2 ALT1 ALT2 CTRAP 2 CCU6 ALT3 Output GPO PO DATA P2 ALT1 TDO 0 JTAG ALT2 TXD 1 UART P0 3 Input GPI PO DATA P3 ALT1 SCK 1 SSC ALT2 ALT3 Output GPO PO DATA P3 ALT1 SCK 1 SSC ALT2 COUTS63 1 CCU6 P0 4 Input GPI PO_DATA P4 ALT1 MTSR 1 SSC ALT2 ALT3 CC62_1 CCU6 Output GPO PO DATA P4 ALT1 MTSR 1 SSC ALT2 CC62 1 CCU6 P0 5 Input GPI PO DATA P5 ALT1 MRST 1 SSC ALT2 EXINTO 0 External interrupt 0 ALT3 Output GPO PO DATA P5 ALT1 MRST 1 SSC ALT2 COUT62 1 CCU6 User s Manual 6 15 V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon technologies XC866 Parallel Ports 6 3 2 Register Description PO DATA Port 0 Data Register Reset Value 00 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw Field Bits Description Pn n rw Port 0 Pin n D
167. Returns 0 if read should be written with 0 User s Manual Interrupt System V 0 5 5 13 V 0 2 2005 01 _ Infineon technologies XC866 Interrupt System 5 4 2 Interrupt Request Flags The interrupt request flags for the different sources are located in several Special Function Registers SFRs This section details the locations and meanings of these interrupt request flags IRCONO Interrupt Request Register 0 Reset Value 00 7 6 5 4 3 2 1 0 0 EXINT6 EXINT5 4 2 EXINT1 EXINTO r rwh rwh rwh rwh rwh rwh rwh Field Bits Description EXINTx 6 0 rwh_ Interrupt Request Flag for External Interrupts x 0 6 This bit is set by hardware and can only be cleared by software 0 Interrupt request is not active 1 Interrupt request is active 0 7 r Reserved Returns 0 if read should be written with O User s Manual Interrupt System V 0 5 5 14 V 0 2 2005 01 _ Infineon technologies IRCON1 XC866 Interrupt Request Register 1 7 6 5 Interrupt System Reset Value 00 4 3 2 1 0 0 ADCSRC1 ADCSRCO RIR TIR EIR rwh rwh rwh rwh rwh Field Bits Type Description EIR rwh Error Interrupt Request Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt request is not active 1 Inter
168. S1 0 ISPOS1 00g P2 DIR P1 Input P1 6 CCPOS1 1 ISPOS1 01g P1 DIR P6 Input P2 2 0CPOS2 0 ISPOSG2 00g P2 DIR P2 0p Input P1 7 OCPOS2 1 ISPOSG2 01g P1 DIR P7 Input P3 0 CC60 DIR PO Input P3 DIR PO 1g Output ALTSELO PO 1g ALTSEL1 P0 0g P3 1 COUT60 P3 DIR P1 1g Output P3 ALTSELO P1 7 1g ALTSEL1 P1 0g User s Manual 12 23 V 0 2 2005 01 6 V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Table 12 2 CCU6 I O Control Selection cont d Port Lines PISEL Register Bit Input Output Control Register Bits P3 2 CC61 0 ISCC61 00 DIR P2 Input P3 DIR P2 1g Output ALTSELO P2 1g ALTSEL1 P2 0g 0 61 1 ISCC61 01 PO DIR PO Input DIR PO 1g Output PO ALTSELO PO 0g PO ALTSEL1 PO 1g P3 3 COUT61 O DIR P3 1g Output ALTSELO P3 1g P3 ALTSEL1 P3 7 0g P0 0 COUT61_ 1 PO DIR PO 1g Output PO ALTSELO PO 0g PO ALTSEL1 PO 1g P3 4 CC62 0 ISCC62 00 P3 4 0g Input DIR P4 1g Output ALTSELO P4 1g ALTSEL1 P4 0p 4 62 1 ISCC62 01 PO DIR P4 0p Input PO DIR P4 1g Output PO ALTSELO P4 0p PO ALTSEL1 P4 1g 5 9 620 DIR P5 1g Output P3 ALTSELO P5 1g ALTSEL1 P5 0p P0 5 COUT62 1 PO
169. SRSEL Channel Control Register 6 Type r rw r rw D3y ADC_CHCTR7 Reset 00 Bit Field 0 LCC 0 RESRSEL Channel Control Register 7 Type r rw r rw RMAP 0 Page 2 ADC RESROL Reset 00 Bit Field RESULT 1 0 0 VF DRC CHNR Result Register 0 Low Type rh r rh rh rh ADC_RESROH Reset 00 Bit Field RESULT 9 2 Result Register 0 High Type rh CCy ADC RESR1L Reset 00 Bit Field RESULT 1 0 0 VF DRC CHNR Result Register 1 Low Type rh r rh rh rh CDy ADC_RESR1H Reset 00 Bit Field RESULT 9 2 Result Register 1 High Type rh ADC RESR2L Reset 00 Bit Field RESULT 1 0 0 VF DRC CHNR Result Register 2 Low Type rh r rh rh rh ADC RESR2H Reset 00 Bit Field RESULT 9 2 Result Register 2 High Type rh D2u ADC RESR3L Reset 00 Bit Field RESULT 1 0 0 VF DRC CHNR Result Register 3 Low Type rh r rh rh rh D3y ADC_RESR3H Reset 00 Bit Field RESULT 9 2 Result Register 3 High Type rh RMAP 0 Page 3 ADC RESRAOL Reset 00 Bit Field RESULT 2 0 VF DRC CHNR Result Register 0 View A Low Type rh rh rh rh ADC RESRAOH Reset 00 Bit Field RESULT 10 3 Result Register 0 View A High Type rh CCy ADC_RESRA1L Reset 00 Bit Field RESULT 2 0 VF DRC CHNR Result Register 1 View A Low Type rh rh rh rh CDy ADC_RESRA1H Reset 00 Bit Field RESULT 10 3 Result Register 1 View A High Type rh ADC RESRA2L Reset 00 Bit Field RESULT 2 0 VF DRC CHNR Result Register 2 View A Low Type rh rh rh rh User s Manual 3
170. ST indicates the occurrence of a capture or compare event of the corresponding channel It can be set if it is 0 by the following events e a software set MCC6xS acompare set event T12 counter value above the compare value if the T12 runs and if the T12 set event is enabled upon capture set event The bit CC6xST can be reset if it is 1 by the following events e a software reset MCC6xR a compare reset event T12 counter value below the compare value if the T12 runs and if the T12 reset event is enabled including in single shot mode at the end of the T12 period areset event in the hysteresis like control mode The bit CC6xPS represents passive state select bit The timer T12 s two output lines CC6x COUT6x can be selected to be in the passive state while CC6xST is 0 with CC6xPS 0 or while CC6xST is 1 with CC6xPS 1 The output level that is driven while the output is in the passive state is defined by the corresponding bit in bit field PSL Hardware modifications of the compare state bits are only possible while timer T12 is running Therefore the bit T12R can be used to enable disable the modification by hardware User s Manual 12 6 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 period value compare value CC6xST CC6xPS 0 passive active passive PSL 0 Pin COUT6x COUT6xPS 1 active passiv
171. To access SFRs in the mapped area bit RMAP in SFR SYSCONO must be set Alternatively the SFRs in the standard area be accessed by clearing bit RMAP The SFR area can be selected as shown in Figure 3 3 SYSCONO System Control Register 0 Reset Value 00 7 6 5 4 3 2 1 0 0 RMAP r rw Field Bits Type Description RMAP 0 rw Special Function Register Map Control 0 The access to the standard SFR area is enabled 1 The access to the mapped SFR area is enabled 0 7 1 r Reserved Returns 0 if read should be written with 0 As long as bit RMAP is set the mapped SFR area can be accessed This bit is not cleared automatically by hardware Thus before standard mapped registers are accessed bit RMAP must be cleared set respectively by software User s Manual 3 4 V 0 2 2005 01 Memory Organization V 0 2 866 technologies Memory Organization Standard Area RMAP 0 FF Module 1 SFRs SYSCONO RMAP Module 2 SFRs Modulen SFRs 00 apped Area RMAP 1 FF Module n 1 SFRs Module n 2 SFRs Module m SFRs 00 Direct Internal D ata Memory Address Figure 3 3 Address Extension by Mapping User s Manual 3 5 V 0 2 2005 01 Memory Organization V 0 2 techno ogies Memory Organization 3 3 2 Address Extension by Paging Address extension is further
172. Trap Enable Control Setting these bits enables the trap functionality for the following corresponding output signals Trap functionality of CC60 Bit 1 Trap functionality of COUT60 Bit 2 Trap functionality of CC61 Bit 3 Trap functionality of COUT61 Bit 4 Trap functionality of CC62 Bit5 Trap functionality of COUT62 The enable feature of the trap functionality is defined as follows 0 The trap functionality of the corresponding output signal is disabled The output state is independent of bit TRPS 1 The trap functionality of the corresponding output signal is enabled The output is set to the passive state while TRPS 1 TRPEN13 Trap Enable Control for Timer T13 0 The trap functionality for T13 is disabled Timer T13 if selected and enabled provides PWM functionality even while TRPS 1 1 The trap functionality for T13 is enabled The timer T13 PWM output signal is set to the passive state while TRPS 1 TRPPEN Trap Pin Enable 0 The trap functionality based on the input pin CTRAP is disabled A trap can only be generated by software by setting bit TRPF 1 The trap functionality based on the input pin CTRAP is enabled A trap can be generated by software by setting bit TRPF or by CTRAP 0 User s Manual 6 V 0 4 12 62 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 Register PSLR defines the passive state level driven by the output pi
173. User s Manual V 0 2 Jan 2005 XC866 8 Bit Single Chip Microcontroller Microcontrollers Min technologies Never stop thinking Edition 2005 01 Published by Infineon Technologies AG St Martin Strasse 53 81669 M nchen Germany Infineon Technologies AG 2005 Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to
174. V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon XC866 techno ogies Parallel Ports 6 4 2 Register Description P1 DATA Port 1 Data Register Reset Value 004 7 6 5 4 3 2 1 0 P7 P6 P5 0 P1 PO rw rw rw r nw rw Field Bits Type Description Pn n rw Port 1 Pin n Data Value n 0 1 5 7 0 Port 1 pin n data value 0 default 1 Port 1 pin n data value 1 0 4 2 r Reserved Returns 0 if read should be written with 0 1 DIR Port 1 Direction Register Reset Value 00 7 6 5 4 3 2 1 0 P7 P6 P5 0 P1 PO rw rw rw r rw rw Field Bits Type Description Pn n rw Port 1 Pin n Direction Control n 0 1 5 7 0 Direction is to input default 1 Direction is set to output 0 4 2 r Reserved Returns 0 if read should be written with 0 User s Manual 6 21 V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon XC866 techno ogies Parallel Ports P1_OD Port 1 Open Drain Control Register Reset Value 00 7 6 5 4 3 2 1 0 P7 P6 P5 0 1 nw rw rw r rw rw Field Bits Type Description Pn n rw Port 1 Pin n Open Drain Mode 0 1 5 7 0 Normal mode output is actively driven for 0 and 1 state default 1 Open drain mode output is actively driven only for 0 state 0 4 2 r Reserved Returns 0 if read shou
175. VCO Bypass Operation In VCO bypass operation the system clock is derived from the oscillator clock divided by the P and K factors 1 fsys fosc PLL Mode The system clock is derived from the oscillator clock divided by the P factor multiplied by the N factor and divided by the K factor Both VCO bypass and PLL bypass must be inactive for this PLL mode N fsys fosc py In normal running mode the system works in the PLL mode For different source oscillator the selection of typical output frequency fsys 80 MHz is shown in Table 7 4 Table 7 4 System frequency 80 MHz Oscillator fosc N P K fsys On chip 10 MHz 16 1 2 80 MHz External 10 MHz 16 1 2 80 MHz 8 MHz 20 1 2 80 2 5 2 32 1 2 80 2 For the XC866 the values of P and are fixed to 1 and 2 respectively In order to obtain the required fsys the value of N can be selected by bit NDIV for different oscillator inputs See Table 7 4 The output frequency needs to be within the range 75 MHz to 80 MHz User s Manual 7 12 V 0 2 2005 01 Power Reset and Clock V 0 4 technologies Power Supply Reset and Clock Management Table 7 5 shows the VCO range in the XC866 Table 7 5 VCO Ranges Unit MHz fycoFREEmax 130 fycomax fVCOFREEmin 200 40 fycomin 150 7 3 3 Clock Management The Clock Management sub module generates all clock signals required w
176. a length from 2 bit characters up to 8 bit characters Starting with the LSB CON HB 0 allows communication with SSC devices in synchronous mode or with serial interfaces such as the one in 8051 Starting with the MSB CON HB 1 allows operation compatible with the SPI interface Regardless of the data width selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers TB and RB with the LSB of the User s Manual 10 20 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces transfer data in bit 0 of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of TB are ignored the unselected bits of RB will not be valid and should be ignored by the receiver service routine The Clock Control allows the transmit and receive behavior of the SSC to be adapted to a variety of serial interfaces A specific shift clock edge rising or falling is used to shift out transmit data while the other shift clock edge is used to latch in receive data Bit CON PH selects the leading edge or the trailing edge for each function Bit CON PO selects the level of the shift clock line in the idle state Thus for an idle high clock the leading edge is a falling one 1 to 0 transition see Figure 10 10 PO PH Shift Clock po fa MS CLK SS CLK po fal mE Pins W W
177. ag is automatically reset when this bit field is set to 1 VF 4 rh Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid 0 The result register x does not contain valid data 1 The result register x contains valid data User s Manual 13 48 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter Normal Read View RESRx This view delivers the 8 bit or 10 bit conversion result and a 3 bit channel number The corresponding valid flag is cleared when the high byte of the register is accessed by a read command provided that bit RCRx VFCR is set RESRxL x 0 3 Result Register x Low Reset Value 00 7 6 5 4 3 2 1 0 RESULT 1 0 0 VF DRC CHNR rh r rh rh rh RESRxH x 0 3 Result Register x High Reset Value 00 7 6 5 4 3 2 1 0 RESULT 9 2 rh Accumulated Read View RESRAx This view delivers the accumulated 9 bit or 11 bit conversion result and a 3 bit channel number The corresponding valid flag is cleared when the high byte of the register is accessed by a read command provided that bit RCRx VFCR is set RESRAXL x 0 3 Result Register x View A Low Reset Value 00 7 6 5 4 3 2 1 0 RESULT 2 0 VF DRC CHNR rh rh rh rh RESRAXxH x 0 3 Result Register x View A High Reset Value 00 7 6 5 4 3 2 1 0 RESULT 1
178. age 12 46 CMPMODIFL Compare State Modification Register Low Page 12 47 CMPMODIFH Compare State Modification Register High Page 12 47 TCTROL Timer Control Register 0 Low Page 12 48 TCTROH Timer Control Register 0 High Page 12 49 TCTR2L Timer Control Register 2 Low Page 12 52 TCTR2H Timer Control Register 2 High Page 12 54 TCTR4L Timer Control Register 4 Low Page 12 55 TCTR4H Timer Control Register 4 High Page 12 56 Modulation Control Registers MODCTRL Modulation Control Register Low Page 12 57 MODCTRH Modulation Control Register High Page 12 58 TRPCTRL Trap Control Register Low Page 12 60 TRPCTRH Trap Control Register High Page 12 61 PSLR Passive State Level Register Page 12 63 MCMOUTSL Multi Channel Mode Output Shadow Register Page 12 65 Low MCMOUTSH Multi Channel Mode Output Shadow Register Page 12 66 High MCMOUTL Multi Channel Mode Output Register Low Page 12 67 MCMOUTH Multi Channel Mode Output Register High Page 12 69 MCMCTR Multi Channel Mode Control Register Page 12 70 T12MSELL T12 Capture Compare Mode Select Register Page 12 72 Low User s Manual 12 30 V 0 2 2005 01 CCUG V 0 4 _ Infineon technologies XC866 Table 12 4 CCU6 Module Registers cont d Capture Compare Unit 6 Register Register Full Name Description Short Name see T12MSELH T12 Capture Compare Mode Select Register Page 12 73 High Interrupt Control Registers ISL Interrupt Status Register Low Pa
179. ak is used to signal the beginning of a new frame It is the only field that does not comply with Figure 10 5 A break is always generated by the master task in the master mode and it must be at least 13 bits of dominant value including the start bit followed by a break delimiter as shown in Figure 10 6 The break delimiter will be at least one nominal bit time long A slave node will use a break detection threshold of 11 nominal bit times Start Break Bit delimit Figure 10 6 The Break Field Synch Byte is a specific pattern for determination of time base The byte field is with the data value 55 as shown in Figure 10 7 A slave task is always able to detect the Break Synch sequence even if it expects a byte field assuming the byte fields are separated from each other If this happens detection of the Break Synch sequence will abort the transfer in progress and processing of the new frame will commence Start Stop Bit Bit Figure 10 7 The Synch Byte Field User s Manual 10 15 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces The slave task will receive and transmit data when an appropriate ID is sent by the master 1 Slave waits for Synch Break 2 Slave synchronizes on Synch Byte 3 Slave snoops for ID 4 According to ID slave determines whether to receive or transmit data or do nothing 5 When transmitting the slave sends 2 4 or 8 data bytes followed
180. all sensor mode 1001 Hysteresis like mode see Table 12 6 101X Multi input capture modes see Table 12 7 11XX Multi input capture modes see Table 12 7 User s Manual 12 72 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 T12MSELH T12 Capture Compare Mode Select Register High Reset Value 00 7 6 5 4 3 2 1 0 BYP HSYNC MSEL62 Field Bits Type Description MSEL62 3 0 rw Capture Compare Mode Selection These bit fields select the operating mode of the three timer T12 capture compare channels Each channel n 0 2 can be programmed individually either for compare or capture operation according to 0000 Compare outputs disabled pins CC6n and COUTE6n can be used for I O pins No capture action 0001 Compare output on CC6n pin COUT6n can be used for I O pins No capture action 0010 Compare output on pin CC6n can be used for I O pins No capture action 0011 Compare output on pins COUT6n and 01XX Double register capture modes see Table 12 5 1000 Hall sensor mode see Table 12 6 In order to enable the hall edge detection all three MSEL6x must be programmed to hall sensor mode 1001 Hysteresis like mode see Table 12 6 101X Multi input capture modes see Table 12 7 11XX Multi input capture modes see Table 12 7 User s Manual 12 73 V 0 2 2005 01 CCU6 V 0 4
181. allel Ports e Analog to Digital Converter ADC Capture Compare Unit 6 CCU6 System Control Registers User s Manual 3 7 V 0 2 2005 01 Memory Organization V 0 2 Cnfineon XC866 techno ogies Memory Organization The page register has the following definition MOD_PAGE Page Register for module MOD Reset Value 004 7 6 5 4 3 2 1 0 OP STNR 0 PAGE r nw Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page When read the value indicates the currently active page STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10g the contents of PAGE are saved in STx before being overwritten with the new value If OP 11g the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STO is selected 01 ST1is selected 10 ST2is selected 11 131 selected User s Manual 3 8 V 0 2 2005 01 Memory Organization V 0 2 Infineon technologies XC866 Memory Organization Field Bits Type Description OP 7 6 Ww Operation OX 10 11 Manual page mode The value of STNR is ignored and PAGE is directly written New page programming with automatic page saving The value written to the bit positions of PAGE is st
182. amming can be done the user must first write 32 bytes of data into the IRAM using MOV instructions Then the BootStrap Loader BSL routine see Section 4 6 or D Flash program subroutine see Section 4 7 1 will transfer these IRAM data to the corresponding write buffer of the targeted Flash bank After 32 bytes of data are assembled in the write buffers the programming sequence will start the charge pumps storing the data content into the Flash cells along the selected WL The WL is selected via the WL addresses shown in Figure 4 3 It is necessary to fill the IRAM with 32 bytes of data otherwise the previous values stored in the write buffers will remain and be programmed into the WL For the P Flash banks a programmed WL must be erased before it can be reprogrammed again as the Flash cells can only withstand one gate disturb This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL For the D Flash bank the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs Hence it is possible to program the same WL for example with 16 bytes of data in two times see Figure 4 4 32 bytes 1 WL 16 bytes 16 bytes 0000 0000 0000 0000 Program 1 0000 0000 TAWA 114115 0000 0000 1111 1411 Program 2 1111 0000 0000 v 0000
183. are Shadow Register for Channel CC61 High Type rwh FE CCU6 CC62SRL Reset 00 Bit Field CC62SL Capture Compare Shadow Register for Channel CC62 Low Type rwh FFy CCU6_CC62SRH Reset 00 Bit Field CC62SH Capture Compare Shadow Register for Channel CC62 High Type rwh RMAP 0 Page 1 CCU6_CC63RL Reset 00 Bit Field CC63VL Capture Compare Register for Channel CC63 Low Type rh 9By CCU6_CC63RH Reset 00 Bit Field CC63VH Capture Compare Register for Channel CC63 High Type rh 9Cy CCU6_T12PRL Reset 004 Bit Field T12PVL Timer T12 Period Register Low Type rwh User s Manual 3 21 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 7 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 9 CCU6_T12PRH Reset 004 Bit Field T12PVH Timer T12 Period Register High Type rwh 9E CCU6 T13PRL Reset 00 Bit Field T13PVL Timer T13 Period Register Low Type rwh CCU6_T13PRH Reset 004 Bit Field T13PVH Timer T13 Period Register High Type rwh A4y CCU6_T12DTCL Reset 00 Bit Field DTM Dead Time Control Register for Timer Type rw T12 Low 5 CCU6_T12DTCH Reset 00 Bit Field 0 DTR2 DTR1 DTRO 0 DTE2 DTE1 DTEO Dead Time Control Register fo
184. are breakpoint type is continuously compared against certain registers where addresses for the breakpoints have been programmed The hardware breakpoints can be classified under two types depending on the address bus supervised Breakpoints on Instruction Address Program Memory Address PROGA is observed Breakpoints on IRAM Address Internal Data Memory Addresses SOURCE DESTIN A are observed depending on the way comparison is done Equal breakpoints Comparison is done only against one value the break event is raised when only this value is matched Range breakpoints Comparison is done against two values the break event is raised when a value observed is found belonging to the range between two programmed values inclusively Breakpoints on Instruction Address These Instruction Pointer IP breakpoints are generated when a break address is matched for the first byte of an instruction that is going to be executed i e for the address within Program Memory where an instruction opcode is to be fetched from Note In the cases of 2 and 3 byte instructions the break will not be generated for addresses of the second and third instruction bytes If the IP breakpoints are of the Break Before Make type the instruction at the breakpoint will be executed only after the proper debug action is taken The OCDS in XC866 supports both equal breakpoints and range breakpoints on Instruction address see Configuratio
185. as been received Must be cleared by software Tl 1 rwh Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission Must be cleared by software NMISR NMI Status Register Reset Value 00 7 6 5 4 3 2 1 0 0 FNAN FLASH FNMIPLL FNMIWDT VDDP VDD OCDS TIMER r rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description FNMIWDT 0 rwh Watchdog Timer NMI Flag 0 No Watchdog NMI occurred 1 WDT prewarning has occurred User s Manual 5 17 V 0 2 2005 01 Interrupt System V 0 5 Cnfineon XC866 techno ogies Interrupt System Field Bits Type Description FNMIPLL 1 rwh PLL NMI Flag 0 No PLL NMI occurred 1 The PLL has lost the lock to the external crystal FNMIFLASH 2 rwh Flash Timer NMI Flag TIMER 0 No Flash NMI occurred 1 Flash Timer has overflowed FNMIOCDS 3 rwh OCDS NMI Flag 0 No OCDS NMI occurred 1 JTAG receiving or user interrupt requested in monitor mode FNMIVDD 4 rwh VDD Prewarning NMI Flag 0 No VDD NMI occurred 1 Vpp is below the prewarning voltage level 2 3 V FNMIVDDP 5 rwh VDDP Prewarning NMI Flag 0 No VDDP NMI occurred 1 Vppp is below the prewarning voltage level 4 0 V if the external power supply is 5 0 V FNMIECC 6 rwh ECC NMI Flag 0 No ECC error occurred 1 ECC error has occurred 0 7 r Reserved Returns 0 if read should be written with 0 Register NMISR can on
186. ata Value n 0 5 0 Port 0 pin n data value 0 default 1 Port 0 data value 1 0 7 6 r Reserved Returns 0 if read should be written with 0 PO DIR Port 0 Direction Register Reset Value 00 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 0 Pin n Direction Control n 0 5 0 Direction is set to input default 1 Direction is set to output 0 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual Parallel Ports V 0 3 6 16 V 0 2 2005 01 _ Infineon technologies XC866 Parallel Ports PO OD Port 0 Open Drain Control Register Reset Value 00 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 1 rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 0 Pin n Open Drain Mode n 0 5 0 Normal mode output is actively driven for 0 1 state default 1 Open drain mode output is actively driven only for 0 state 0 7 6 r Reserved Returns 0 if read should be written with 0 PO PUDSEL Port 0 Pull Up Pull Down Select Register Reset Value FF 7 6 5 4 3 2 1 0 0 P5 P4 P3 P2 P1 r rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 0 Bit n n 0 5 0 Pull down device is selected 1 Pull up device is selected default 0 7 6 r Reserved Returns 0 if read should be written with 0
187. ata bits loads RB8 SCON 2 with the stop bit and sets the RI bit provided RI 0 and either SM2 0 see Section 10 1 2 or the received stop bit 1 If none of these conditions is met the received byte is lost The associated timings for transmit receive in mode 1 are illustrated in Figure 10 1 User s Manual 10 3 V 0 2 2005 01 Serial Interfaces V 0 3 technologies XC866 Serial Interfaces Transmit A E cm m 5 c 9 o N gt lt n gt lt m L gt a 7O e D gt a a r A us e p UM a 8 E a n 35 5 5 x ow N 4 E 5 V J EO 8 5 Figure 10 1 Serial Interface Mode 1 Timing Diagram User s Manual 10 4 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces 10 1 1 2 Mode 2 9 Bit UART Fixed Baud Rate In mode 2 the UART behaves as a 9 bit serial port A start bit 0 8 data bits plus a programmable 9th bit and a stop bit 1 are transmitted TXD or received on RXD The 9th bit for transmission is taken from TB8 SCON 3 while for reception the 9th bit received is placed in RB8 5 2 The transmission cycle is activated by a write to SBUF T
188. ate timer Rate Timer Reload Register Reset Value 00 7 6 5 4 3 2 1 0 BR VALUE rw Field Bits Description BR_VALUE 7 0 rw Baud Rate Timer Reload Value Reading returns the 8 bit content of the baud rate timer writing loads the baud rate timer reload value Note BG should only be written if R 0 10 1 5 Interfaces of UART The UART has two input output lines TXD for data transmission and RXD for data reception Data that is shifted into the UART module through RXD can be selected from two different sources RXD 0 and RXD 1 This selection is performed by the SFR bit MODPISEL URRIS MODPISEL Peripheral Input Select Register Reset Value 00 7 6 5 4 3 2 1 0 0 JTAGTDIS JTAGTCK 0 EXINTOIS URRIS r rw rw r rw rw The functions of the shaded bits are not described here Field Bits Description URRIS 0 rw UART Receive Input Select 0 UART Receiver Input RXD 0 is selected 1 UART Receiver Input RXD 1 is selected User s Manual 10 13 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces 10 2 LIN The UART can be used to support the Local Interconnect Network LIN protocol for both master and slave operations The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using Timer 2 This allows the UART to be synchronized t
189. bit fields CC6xV during a shadow transfer In capture mode the captured value of T12 can be read from these registers User s Manual 12 38 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 T12DTCL Dead Time Control Register for Timer T12 Low Reset Value 00 7 6 5 4 3 2 1 0 DTM rw Field Bits Type Description DTM 7 0 Dead Time Bit field DTM determines the programmable delay between switching from the passive state to the active state of the selected outputs The switching from the active state to the passive state is not delayed T12DTCH Dead Time Control Register for Timer T12 High Reset Value 004 7 6 5 4 3 2 1 0 0 DTR2 DTR1 DTRO 0 DTE2 DTE1 DTEO r rh rh rh r nw rw rw Field Bits Type Description DTEO 0 rw Dead Time Enable Bits DTE1 1 Bits DTEx x 0 2 enable and disable the dead DTE2 2 time generation for each compare channel 0 1 2 of timer T12 0 Dead time generation is disabled The corresponding outputs switch from the passive state to the active state according to the actual compare status without any delay 1 Dead time generation is enabled The corresponding outputs switch from the passive state to the active state according to the compare status with the delay programmed in bit field DTM User s Manual 12 39 V 0 2 2005 01 CCU
190. ble Baud Rate In mode 1 the UART behaves as an 8 bit serial port A start bit 0 8 data bits and a stop bit 1 are transmitted on TXD or received on RXD at the baud rate set by the underflow rate on the dedicated baud rate generator This baud rate is variable The transmission cycle is activated by a write to SBUF The data is transferred to the transmit register and a 1 is loaded to the 9th bit position At phase 1 of the machine cycle after the next rollover in the divide by 16 counter the start bit is copied to TXD and data is activated one bit time later One bit time after the data is activated the data starts getting shifted right with zeros shifted in from the left When the MSB gets to the output position the control block executes one last shift and sets the TI bit Reception is started by a high to low transition on RXD sampled at 16 times the baud rate The divide by 16 counter is then reset and 1111 1111 is written to the receive register If a valid start bit 0 is then detected based on two out of three samples it is shifted into the register followed by 8 data bits If the transition is not followed by a valid start bit the controller goes back to looking for a high to low transition on RXD When the User s Manual 10 2 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces start bit reaches the leftmost position the control block executes one last shift then loads SBUF with the 8 d
191. collisions on the receive line due to different slave data Only one slave drives the line i e enables the driver of its MRST pin All the other slaves must have their MRST pins programmed as input so only one slave can put its data onto the master s receive line Only the receiving of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a de selection signal or command The slaves use open drain output on MRST This forms a wired AND connection The receive line needs an external pull up in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master send ones only Because this high level is not actively driven onto the line but only held through the pull up device the selected slave can pull this line actively to a low level when transmitting a zero bit The master selects the User s Manual 10 22 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing the necessary initialization of the SSC the serial interfaces can be enabled For a master device the clock line will now go to its programme
192. ction Bit LDEV can be written with 1 by software to trigger the load event In this case the load event does not contain any information about the channels to be converted but always takes the contents of the conversion request control register This allows the conversion request control register to be written at a second address without triggering the load event User s Manual 13 14 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter 13 4 5 5 Autoscan The autoscan is a functionality of the parallel source If autoscan mode is enabled the load event takes place when the conversion is completed while PND 0 provided the parallel request source has triggered the conversion This automatic reload feature allows channels 4 and 7 to be constantly scanned for pending conversion requests without the need for external trigger or software action 13 4 6 Wait for Read Mode The wait for read mode can be used for all request sources to allow the CPU to treat each conversion result independently without the risk of data loss Data loss can occur if the CPU does not read a conversion result in a result register before a new result overwrites the previous one In wait for read mode the conversion request generated by a request source for a specific channel will be disabled and conversion not possible if the targeted result register contains valid data indicated by its valid flag being set C
193. d polarity The data line will go to either 0 or 1 until the first transfer starts After a transfer the data line will always remain at the logic level of the last transmitted data bit When the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register TB This value is copied into the shift register assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the TXD line on the next clock from the baud rate generator transmission starts only if CON EN 1 Depending on the selected clock phase a clock pulse will also be generated on the MS_CLK line At the same time with the opposite clock edge the master latches and shifts in the data detected at its input line RXD This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line With the start of the transfer the busy flag CON BSY is set and the TIR will be activated to indicate that register TB may be reloaded again After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all the slaves shift registers while the master s shift register holds the data of the selected
194. data reduction filter is enabled The reload value for DRC is 1 so the accumulation is done over 2 conversions IEN Interrupt Enable This bit enables the event interrupt related to the result register x An event interrupt can be generated when DRC is set to O after decrementing or by reload 0 The event interrupt is disabled 1 The event interrupt is enabled FEN FIFO Enable This bit enables the FIFO functionality for result register x 0 The FIFO functionality is disabled 1 The FIFO functionality is enabled WFR Wait for Read Mode This bit enables the wait for read mode for result register x 0 The wait for read mode is disabled 1 The wait for read mode is enabled VFCTR Valid Flag Control This bit enables the reset of valid flag by read access to high byte for result register x 0 VF unchanged by read access to RESRxH RESRAXxH default 1 VF reset by read access to RESRxH RESRAXH 3 1 Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 51 V 0 2 2005 01 Infineon technologies 13 7 9 Register CHINFR monitors the activated channel interrupt flags XC866 Analog to Digital Converter Interrupt Registers CHINFR Channel Interrupt Flag Register Reset Value 00 7 6 5 4 3 2 1 0 CHINF7 CHINF6 CHINF5 CHINF4 CHINF3 CHINF2 CHINF1 CHINFO rh rh rh rh rh rh rh rh Field Bits Ty
195. des a highly reliable and secure way to detect and recover from software or hardware failures The WDT is reset at a regular interval that is predefined by the user The CPU must service the WDT within this time interval to prevent the WDT from causing an XC866 system reset Hence routine service of the WDT confirms that the system is functioning properly This ensures that an accidental malfunction of the XC866 will be aborted in a user specified time period Features e 16 bit Watchdog Timer Programmable reload value for upper 8 bits of timer Programmable window boundary e Selectable input frequency of fpc 2 or fpc 4 128 User s Manual 9 1 V 0 2 2005 01 Watchdog Timer V 0 4 Cnfineon XC866 techno ogies Watchdog Timer 9 1 Functional Description The Watchdog Timer WDT is a 16 bit timer which is incremented by a count rate of 2 or fpc 128 This 16 bit timer is realized as two concatenated 8 bit timers The upper 8 bits of the WDT can be preset to a user programmable value via a watchdog service access in order to modify the watchdog expire time period The lower 8 bits are reset on each service access Figure 9 1 shows the block diagram of the WDT unit Overflow Time out Control amp Window boundary control WDTWINB WDTTO WDTRST WDTIN ENWDT Logic ENWDT P Figure 9 1 Block Diagram If the WDT is enabled by setting bit WDTEN to 1 the tim
196. des checking the latched values of pins MBC TMS and P0 0 to enter the selected Boot ROM operating modes Refer to Chapter 7 2 3 for the selection of different Boot ROM operating modes The memory organization of the XC866 shown in this document is after the address space switch where the different operating modes are executed FFFF FFFF Address space 000 switch E000 Memory Space C000 2000 Memory Space CPU starts execution Ed Immediately After address after reset space switch Figure 3 6 Boot ROM Address Space Switch 3 4 1 User Mode If TMS 0 1 x x the Boot ROM will jump to program memory address 0000 to execute the user code in the Flash or ROM memory This is the normal operating mode of the 866 User s Manual 3 26 V 0 2 2005 01 Memory Organization V 0 2 techno ogies Memory Organization 3 4 2 BootStrap Loader Mode If MBC TMS 0 0 0 0 x the software routines of the BootStrap Loader BSL located in the Boot ROM will be executed allowing the XRAM and Flash memory if available to be programmed erased and executed Refer to Chapter 4 6 for the different BSL working modes 3 4 3 OCDS Mode If MBC TMS 0 0 0 1 1 the OCDS mode will be entered for debugging program code The OCDS hardware is initialized and a jump to program memory address 0000 is next performed The user code in th
197. dge aligned mode or one match while counting down in center aligned mode synchronized to T13 PWM after TRPF is reset T13 period match no synchronization to T12 or T13 T12 T13 ur active TRPS sync to T13 TRPS 112 no sync CCUG trap sync Figure 12 13 Trap State Synchronization with TRM2 0 User s Manual 12 16 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 5 Multi Channel Mode The multi channel mode offers the possibility of modulating all six T12 related outputs The bits in bit field MCMP are used to select the outputs that may become active If the multi channel mode is enabled bit MCMEN 1 only those outputs that have a 1 at the corresponding bit positions in bit field MCMP may become active This bit field has its own shadow bit field MCMPS which can be written by software The transfer of the new value MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events This structure permits the software to write the new value which is then taken into account by the hardware at a well defined moment and synchronized to a PWM period This avoids unintended pulses due to unsynchronized modulation sources T12 T13 SW SW write by software SEL 6 Correct Hall Event reset MCMPS TL A set Maei mE T12c1cm MCMP clear no action 6 to mo
198. document with CCU6_CC63SRL The addresses non mapped of the CCU6 SFRs are listed in Table 12 3 the module name prefix CCUG eg Table 12 3 SFR Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 CC63SRL CC63RL T12MSELL MCMOUTL CC63SRH CC63RH T12MSELH MCMOUTH 9C TCTR4L T12PRL IENL ISL 9 T12PRH IENH ISH 9E MCMOUTSL T13PRL INPL PISELOL MCMOUTSH T13PRH INPH PISELOH A4 ISRL T12DTCL ISSL PISEL2 Ady ISRH T12DTCH ISSH A64 CMPMODIFL TCTROL PSLR ATy CMPMODIFH TCTROH MCMCTR CC60SRL CC60RL TCTR2L T12L CC60SRH CC60RH TCTR2H T12H FC CC61SRL CC61RL MODCTRL T13L FD CC61SRH CC61RH MODCTRH T13H FEY CC62SRL CC62RL TRPCTRL CMPSTATL CC62SRH CC62RH TRPCTRH CMPSTATH User s Manual 12 28 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 12 3 Table 12 4 shows all registers associated with the CCU6 module Capture Compare Unit 6 Register Description Table 12 4 CCU6 Module Registers Register Register Full Name Description Short Name see System Registers PISELOL Port Input Select Register 0 Low Page 12 31 PISELOH Port Input Select Register O High Page 12 33 PISEL2 Port Input Select Register 2 Page 12 34 T12 Registers T12L Timer T12 Counter Register Low Page 12 35 T12H Time
199. ds CC63V contain the values that are 7 0 of compared to the T13 counter value CC63RH User s Manual 12 43 V 0 2 2005 01 CCUG V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 CC63SRL Capture Compare Shadow Register for Channel CC63 Low Reset Value 004 7 6 5 4 3 2 1 0 CC63SL nw CC63SRH Capture Compare Shadow Register for Channel CC63 High Reset Value 00 7 6 5 4 3 2 1 0 635 1 Field Bits Type Description CC63S 7 0 of rw Shadow Register for Channel CC63 Compare CC63SRL Value 7 0 of The contents of bit fields CC63S are transferred to CC63SRH the bit fields CC63V during a shadow transfer User s Manual 12 44 V 0 2 2005 01 CCUG V 0 4 Infineon technologies 12 3 4 Register CMPSTAT contains status bits that monitor the current capture and compare state and control bits that define the active passive state of the compare channels XC866 Capture Compare Unit 6 Capture Compare Control Registers CMPSTATL Compare State Register Low Reset Value 00 7 6 5 4 3 2 1 0 CC CC CC CC CC CC 63ST i is 62997 61ST 60ST r rh rh rh rh rh rh rh Field Bits Type Description CC60ST 0 rh Capture Compare State Bits CC61ST 1 Bits CC6xST monitor the state of the capture compare CC62ST 2 channels Bits CC6xST x 0 2 are related to T12 CC63ST 6 b
200. duction 1 1 Feature Summary The following list summarizes the main features of the XC866 High performance XC800 Core compatible with standard 8051 processor two clocks per machine cycle architecture for memory access without wait state two data pointers On chip memory 8 Kbytes of Boot ROM 256 bytes of RAM 512 bytes of XRAM 8 16 Kbytes of Flash or 8 16 Kbytes of ROM with additional 4 Kbytes of Flash I O port supply at 3 0 to 5 5 V and core logic supply at 2 5 V generated by embedded voltage regulator Power on reset generation Brownout detection for core logic supply On chip OSC and PLL for clock generation PLL loss of lock detection Power saving modes slow down mode idle mode power down mode with wake up capability via RXD or EXINTO clock gating control to each peripheral Programmable 16 bit Watchdog Timer WDT Four ports 19 pins as digital I O 8 pins as digital analog input e 8 channel 10 bit ADC Three 16 bit timers Timer 0 and Timer 1 TO and T1 Timer 2 Capture compare unit for PWM signal generation CCU6 Full duplex serial interface UART e Synchronous serial channel SSC e On chip debug support 1 Kbyte of monitor ROM part of the 8 Kbyte Boot ROM 64 bytes of monitor RAM e PG TSSOP 38 pin package e Temperature range SAF 40 to 85 C SAK 40 to 125 C User s Manual 1 3 V 0 2 2005 01 Intro 0
201. dulation JL selection write to T13zm JL bitfield direct shadow transfer MCMPS interrupt with pet CCUG6 mod sync int Figure 12 14 Modulation Selection and Synchronization Figure 12 14 shows the modulation selection for the multi channel mode The event that triggers the update of bit field MCMP is chosen by SWSEL If the selected switching event occurs the reminder flag R is set This flag monitors the update request and it is automatically reset when the update takes place In order to synchronize the update of MCMP to a PWM generated by T12 or T13 bit field SWSYN allows the selection of the User s Manual 12 17 V 0 2 2005 01 6 V 0 4 technologies Capture Compare Unit 6 synchronization event which leads to the transfer from MCMPS to MCMP Due to this structure an update takes place with a new PWM period The update can also be requested by software by writing to bit field MCMPS with the shadow transfer request bit STRMCM set If this bit is set during the write action to the register the flag R is automatically set By using this the update takes place completely under software control A shadow transfer interrupt can be generated when the shadow transfer takes place The possible hardware request events are e a T12 period match while counting up T12pm aT12 one match while counting down T120m e a T13 period match T13pm e aT12 compare match of channel 1 T12c1cm acorrect Ha
202. dule may be disabled by resetting the GLOBCTR ANON bit This feature causes the generation of fapc to be stopped and allows a reduction in power consumption when no conversion is needed User s Manual 8 4 V 0 2 2005 01 SCU V 0 4 techno ogies Power Saving Modes In order to save power consumption when the on chip oscillator is used XTAL should be powered down by setting bit OSC_CON XPD However when the external oscillator is used the on chip oscillator cannot be powered down by setting bit OSC_CON OSCPD User s Manual 8 5 V 0 2 2005 01 SCU V 0 4 Cnfineon XC866 techno ogies Power Saving Modes 8 2 Register Description PMCONO Power Mode Control Register 0 Reset Value See Table 8 1 7 6 5 4 3 2 1 0 0 WDTRST WKRS WKSEL SD PD WS r rwh rwh rw rw rwh rw The functions of the shaded bits are not described here Field Bits Type Description WS 1 0 rw Wake up Source Select 00 No wake up is selected 01 Wake up source RXD is selected 10 Wake up source EXINTO is selected 11 Wake up source RXD or EXINTO is selected PD 2 rwh Power down Enable Active High Setting this bit will cause the chip to enter power down mode It is reset by wake up circuit The PD bit is a protected bit When the Protection Scheme see Chapter 3 3 4 1 is activated this bit cannot be written directly SD 3 rw Slow down Enable Active High Setting this bit
203. e port It can be used as alternate functions for the CCU6 UART and the SSC P0 0 12 Hi Z 0 JTAG Clock Input T12HR 1 CCU6 Timer 12 Hardware Run Input CC61 1 Input Output of Capture Compare channel 1 CLKOUT 10 MHz On Chip OSC Clock Output PO 1 14 Hi Z TDI_O JTAG Serial Data Input T13HR_1 CCU6 Timer 13 Hardware Run Input RXD_1 UART Receive Input COUT61_1 Output of Capture Compare channel 1 P0 2 19 _2 CCU6 Trap Input 0 JTAG Serial Data Output TXD 1 UART Transmit Output P0 3 2 Hi Z 5 1 SSC Clock Input Output COUT63 1 Output of Capture Compare channel 3 0 4 3 Hi Z MTSR 1 SSC Master Transmit Output Slave Receive Input CC62 1 Input Output of Capture Compare channel 2 User s Manual 1 6 V 0 2 2005 01 Intro V 0 3 Infineon technologies XC866 Introduction Table 1 2 Pin Definitions and Functions cont d Symbol Pin Type Reset Function Number State 5 4 Hi Z MRST_1 SSC Master Receive Input Slave Transmit Output EXINTO O External Interrupt Input 0 COUT62 1 Output of Capture Compare channel 2 User s Manual Intro V 0 3 1 7 V 0 2 2005 01 Infineon technologies XC866 Introduction Table 1 2 Pin Definitions and Functions cont d Symbol Pin Type Reset Function Number State P1 I O Port 1 Port 1 is a 5 bit bidirectional general purpose port It can be used as alternate functions for the
204. e active PSL 0 CCU6_T12_ comp states Figure 12 4 Compare States of Timer T12 For the hysteresis like compare mode MSEL6x 1001g see Section 12 1 1 9 the setting of the compare state bit is possible only while the corresponding input CCPOSx 1 inactive If the hall sensor mode MSEL6x 1000g is selected see Section 12 1 6 the compare state bits of the compare channels 1 and 2 are modified by the timer T12 in order to indicate that a programmed time interval has elapsed The set is only generated when bit CC6xST is reset a reset can only take place when the bit is set Thus the events triggering the set and reset actions of the CC6xST bit must be combined This OR combination of the resulting set and reset permits the reload of the dead time counter to be triggered see Figure 12 5 This is triggered only if bit CC6xST is changed permitting a correct PWM generation with dead time and the complete duty cycle range of 096 to 10096 in edge aligned and center aligned modes 12 1 1 5 Duty Cycle of 0 and 100 These counting and switching rules ensure a PWM functionality in the full range between 0 and 100 duty cycle duty cycle active time total PWM period In order to obtain a duty cycle of 0 compare state never active a compare value of T12P 1 must be programmed for both compare modes A compare value of 0 will lead to a duty cycle of 10096 compare state always active User s Manual 12 7 V 0 2 2005 01
205. e Flash or ROM memory is executed and the debugging process may be started During the OCDS mode the lowest 64 bytes 00 in the internal data memory address range may be alternatively mapped to the 64 byte monitor RAM or the internal data RAM User s Manual 3 27 V 0 2 2005 01 Memory Organization V 0 2 techno ogies Flash Memory 4 Flash Memory The Flash memory provides an embedded user programmable non volatile memory allowing fast and reliable storage of user code and data It is operated from a single 2 5 V supply from the Embedded Voltage Regulator EVR and does not require additional programming or erasing voltage The sectorization of the Flash memory allows each sector to be erased independently Features In System Programming ISP via UART In Application Programming IAP Error Correction Code ECC for dynamic correction of single bit errors 32 byte minimum program width 1 sector minimum erase width 1 byte read access 3x CCLK period read access time inclusive of one wait state User s Manual 4 1 V 0 2 2005 01 Flash Memory V 0 3 techno ogies Flash Memory 4 1 Flash Memory Map The XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of embedded Flash memory These Flash memory sizes are made up of two or four 4 Kbyte Flash banks respectively Each Flash device consists of Program Flash P Flash bank s and a single
206. e JTAG which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application The dedicated MBC pin is used for external configuration and debugging control Note All the debug functionality described here can normally be used only after XC866 has been started in OCDS mode Note For more information on boot configuration options see Chapter 7 2 3 Memory Control Primary Unit Debug lt Interface User Boot Program Monitor Memory ROM Monitor amp MBC Monitor Mode Control Bootstrap loader Control line OCDS Interrupt NMI Report System Control Unit Reset Clock Debug PROG PROG Memory Interface amp IRAM Data Control Addresses XC800 Figure 14 1 866 OCDS Block Diagram 1 The pins of the JTAG port can be assigned to either Port 0 primary or Ports 1 and 2 secondary User must set the JTAG pins TCK and TDI as input during connection with the OCDS system User s Manual 14 2 V 0 2 2005 01 OCDS V 0 2 Cnfineon XC866 techno ogies On Chip Debug Support 14 2 Debugging The on chip debug system can be described in two parts The first part covers the generation of Debug Events and the second part describes the Debug Actions that are taken when a debug event is generated Debug events Hardware Breakpoints Software Breakpoints External Breaks Debug event action
207. e Register P1 ALTSELO Port 1 Alternate Select Register 0 P1 ALTSEL1 Port 1 Alternate Select Register 1 6 4 1 Functions Table 6 7 Port 1 Input Output Functions Port Pin Input Output Select Connected Signal s From to Module P1 0 Input P1 DATA PO ALT 1 RXD 0 UART ALT 2 T2EX Timer 2 ALT 3 Output GPO P1 DATA PO ALT1 ALT2 1 1 Input GPI P1 DATA P1 ALT 1 ALT 2 External interrupt 3 ALT 3 Output GPO P1 DATA P1 ALT1 TDO 1 JTAG ALT2 TXD 0 UART User s Manual 6 19 V 0 2 2005 01 Parallel Ports V 0 3 Cnfineon XC866 techno ogies Parallel Ports Table 6 7 Port 1 Input Output Functions cont d Port Pin Input Output Select Connected Signal s From to Module P1 5 Input P1 DATA P5 ALT 1 CCPOSO 1 CCU6 ALT 2 EXINT5 External interrupt 5 ALT 3 Output GPO P1 DATA P5 1 ALT1 ALT2 1 6 Input GPI P1 DATA P6 ALT 1 CCPOS1 1 CCU6 ALT 2 T12HR 0 CCU6 ALT 3 EXINT6 External interrupt 6 Output GPO P1 DATA P6 ALT1 ALT2 1 7 Input GPI P1 DATA P7 ALT 1 52 1 CCU6 ALT 2 T13HR 0 CCU6 ALT 3 Output GPO P1 DATA P7 ALT1 ALT2 1 1 5 be used as software Chip Select function for the SSC 2 P1 6 can be used as a software Chip Select function for the SSC User s Manual 6 20
208. e aborted conversion is requested before taking into account what is requested by QORO RF rh Refill This bit is updated by bit QORO RF when the conversion requested by QORO is started ENSI rh Enable Source Interrupt This bit is updated by bit QORO ENSI when the conversion requested by QORO is started EXTR rh External Trigger This bit is updated by bit QORO EXTR when the conversion requested by QORO is started Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 42 V 0 2 2005 01 Cnfineon XC866 techno ogies Analog to Digital Converter Register QINRO is the entry register for sequential requests QINRO Queue Input Register 0 Reset Value 00 7 6 5 4 3 2 1 0 EXTR ENSI RF 0 REQCHNR r Field Bits Type Description REQCHNR 2 0 Request Channel Number This bit field defines the requested channel number RF 5 Ww Refill This bit defines the refill functionality ENSI 6 Enable Source Interrupt This bit defines the source interrupt functionality EXTR 7 External Trigger This bit defines the external trigger functionality 0 4 3 r Reserved Returns 0 if read should be written with 0 User s Manual 13 43 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter 13 7 7 Parallel Source Registers The
209. e acknowledge or error byte User can program erase or execute the P Flash and or D Flash bank s The available working modes are Transfer user program from host to XRAM and or Flash Execute user program in XRAM Execute user program in Flash Erase Flash sector s from the same or different bank s User s Manual 4 9 V 0 2 2005 01 Flash Memory V 0 3 Cnfineon XC866 techno ogies Flash Memory 4 7 In Application Programming In most applications data in the D Flash needs to be modified during program execution In Application Programming IAP is supported so that users can program or erase the D Flash data from their Flash user program by calling some special subroutines that utilize the Flash Timer NMI Hence it is necessary to incorporate a Flash Timer NMI service routine code as part of the Flash user program The Flash Timer NMI service routine is required as part of the D Flash program and erase sequences Boot ROM special D Flash program erase subroutines user program user NMI routine Flash Timer NMI service routine Flash Timer NM 9 00734 RETI instruction Figure 4 6 D Flash Program Erase Flow User s Manual 4 10 V 0 2 2005 01 Flash Memory V 0 3 techno ogies Flash Memory 4 7 1 D Flash Programming The Flash program subroutine can be called by the user to program 32 bytes of data
210. e counting up e A T12 compare match of channel 0 while counting down User s Manual 12 19 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 This correct Hall event can be used as a transfer request event for register MCMOUTS The transfer from MCMOUTS to MCMOUT transfers the new CURH pattern as well as the next EXPH pattern In case the sampled Hall inputs were neither the current nor the expected Hall pattern the bit WHE wrong Hall event is set which can also cause an interrupt and set the IDLE mode to clear MCMP modulation outputs are inactive To restart from IDLE the transfer request of MCMOUTS must be initiated by software bit STRHP and bit fields SWSEL SWSYN 12 1 6 2 Brushless DC Control For Brushless DC motors there is a special mode MSEL6x 1000 which is triggered by a change of the Hall inputs CCPOSx In this case T12 s channel 0 acts in capture function channel 1 and 2 act in compare function without output modulation and the multi channel block is used to trigger the output switching together with a possible modulation of T13 After the detection of a valid Hall edge the T12 count value is captured to channel 0 representing the actual motor speed and the T12 is reset When the timer reaches the compare value in channel 1 the next multi channel state is switched by triggering the shadow transfer of bit field MCMP if enabled in bit field SWEN This trigger eve
211. e measurements between consecutive edges on pins CC6n COUT6n is pin Table 12 6 Combined T12 Modes Description Combined T12 Modes 1000 Hall sensor mode Capture mode for channel 0 compare mode for channels 1 and 2 The contents of T12 are captured into CC60 at a valid hall event which is a reference to the actual speed CC61 can be used for a phase delay function between hall event and output switching CC62 can act as a time out trigger if the expected hall event is too late The value 1000g must be programmed to MSELO MSEL1 and MSEL2 if the hall signals are used In this mode the contents of timer T12 are captured in CC60 and T12 is reset after the detection of a valid hall event In order to avoid noise effects the dead time counter channel 0 is started after an edge has been detected at the hall inputs On reaching the value of 0000015 the hall inputs are sampled and the pattern comparison is done 1001 Hysteresis like control mode with dead time generation The negative edge of the CCPOSx input signal is used to reset bit CC6nST As a result the output signals can be switched to passive state immediately and switched back to active state with dead time if the CCPOSx is high and the bit CC6nST is set by a compare event User s Manual 12 75 V 0 2 2005 01 6 V 0 4 techno ogies Capture Compare Unit 6 Table 12 7 Multi Input Capture Modes Description Multi Input Capture Modes 1
212. e mode When an error is detected the respective error flag is set and an error interrupt request will be generated by activating the Error Interrupt Request line EIR see Figure 10 15 The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled error flag s to prevent repeated interrupt requests User s Manual 10 27 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces Bits in Register Error Interrupt EIR Figure 10 15 SSC Error Interrupt Control A Receive Error master or slave mode is detected when a new data frame is completely received but the previous data was not read out of the register RB This condition sets the error flag CON RE and when enabled via CON REN sets the EIR The old data in the receive buffer RB will be overwritten with the new value and this lost data is irretrievable A Phase Error master or slave mode is detected when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the module clock changes between one cycle before and two cycles after the latching edge of the sh
213. e registers of P2 are summarized in Table 6 9 Table 6 9 Port 2 Registers Register Short Name Register Full Name P2 DATA Port 2 Data Register P2 PUDSEL Port 2 Pull Up Pull Down Select Register P2 PUDEN Port 2 Pull Up Pull Down Enable Register 6 5 1 Functions Table 6 10 Port 2 Input Functions Port Pin Input Output Select Connected Signal s From to Module P2 0 Input P2 DATA PO ALT 1 50 0 CCU6 ALT 2 EXINT1 External interrupt 1 ALT 3 T12HR_2 CCU6 ALT 4 TCK_1 JTAG ANALOG ANO ADC P2 1 Input P2 DATA P1 ALT 1 CCPOS1 0 CCU6 ALT 2 EXINT2 External interrupt 2 ALT 3 T13HR_2 CCU6 ALT 4 TDI 1 JTAG ANALOG 1 ADC P2 2 Input P2 DATA P2 ALT 1 CCPOS2 0 CCU6 ALT 2 ALT 3 CTRAP 1 CCU6 ALT 4 ANALOG 2 User s Manual 6 24 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 Parallel Ports Table 6 10 Port 2 Input Functions cont d Port Pin Input Output Select Connected Signal s From to Module P2 3 Input P2 DATA P3 ALT 1 ALT 2 ALT 3 ANALOG 2 4 Input GPI P2 DATA P4 ALT 1 ALT 2 ALT 3 ANALOG 4 2 5 Input GPI P2 DATA P5 ALT 1 ALT 2 ALT 3 ANALOG 5 2 6 Input GPI P2 DATA P6 ALT 1
214. e regulator continues to operate Therefore all functions of the microcontroller are stopped and only the contents of the FLASH on chip RAM XRAM and the SFRs are maintained The port pins hold the logical state they had when the power down mode was activated For the digital ports the user must take care from external side that the ports are not floating in power down mode This can be done with external pull up pull down or putting the port to output In power down mode the clock is turned off Hence it cannot be awakened by an interrupt or by the WDT It will be awakened only when it receives an external wake up signal or reset signal Entering Power down Mode Software requests power down mode by setting the bit PMCONO PD to 1 If the external wake up from power down is used software must prepare the external environment of the XC866 to trigger one of these signals under the appropriate conditions before entering power down mode A wake up circuit is used to detect a wake up signal and activate the power up During power down this circuit remains active It does not depend on any clocks Exit from power down mode can be achieved by applying a falling edge trigger into the EXINTO RXD pin RXD pin or EXINTO pin The wake up source can be selected by the WS bit of the PMCONO register The wake up with reset or without reset is selected by bit PMCONO WKSET The wake up source and wake up type must be selected before the syste
215. e reset which includes 1 Startup of the main voltage regulator and the low power voltage regulator 2 When Vppp and Vpp reach the threshold of the and Vpp detectors the reset of EVR becomes inactive When the system starts up the PLL is disconnected from the oscillator and will run at its base frequency Once the EVR is stable provided the oscillator is running the PLL is connected and the continuous lock detection ensures that PLL starts functioning Following this as soon as the system clock is stable each 4 Kbyte Flash bank will enter the ready to read mode The status of pins MBC TMS and 0 is latched by the reset The latched values are used to select the boot options see Section 7 2 3 A correctly executed reset leaves the system a defined state The program execution starts from location 0000 Figure 7 2 shows the power on reset sequence User s Manual 7 3 V 0 2 2005 01 Power Reset and Clock V 0 4 techno ogies Power Supply Reset and Clock Management FLASH go to Reset is Ready to Read released and Mode start of program Typ 300 us Max 200 us 160 us EVR is stable PLL is locked Figure 7 2 Power on Reset 7 2 4 2 Hardware Reset An external hardware reset sequence is started when the reset input pin RESET is asserted low The RESET pin must be held low for at least 1ms After the RESET pin is deasserted the reset sequence is t
216. e state when the counter value reaches the compare value while counting up e reset to the passive state when the counter value reaches the compare value while counting down reset to the passive state in case of a zero match without compare match while counting up set to the active state in case of a zero match with a parallel compare match while counting up T12cik compare match 0 compare active passive state CCUG6 T12 center cm2 Figure 12 3 Compared States for Compare Value 2 The switching rules are considered only while the timer is running As a result write actions to the timer registers while the timer is stopped do not lead to compare actions User s Manual 12 5 V 0 2 2005 01 6 V 0 4 techno ogies Capture Compare Unit 6 12 1 1 4 Compare Mode of T12 In compare mode the registers CC6xR x 0 2 are the actual compare registers for T12 The values stored in CC6xR are compared all three channels in parallel to the counter value of T12 The register CC6xR can only be read by software and the modification of the value is done by a shadow register transfer from register CC6xSR Register T12PR contains the period value for timer T12 The period value is compared to the actual counter value of T12 and the resulting counter actions depend on the defined counting rules Figure 12 4 shows an example in the center aligned mode without dead time The bit CC6x
217. ead to corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones that is their transmit buffers must be loaded with FFFF prior to any transfer Note A slave with push pull output drivers not selected for transmission will normally have its output drivers switched off However in order to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer The cause of an error interrupt request receive phase baud rate or transmit error can be identified by the error status flags in control register CON Note In contrast to the EIR the error status flags CON TE CON RE CON PE and CON BE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software User s Manual 10 29 V 0 2 2005 01 Serial Interfaces V 0 3 techno ogies Serial Interfaces 10 3 2 Interrupts An overview of the various interrupts in SSC is provided in Table 10 4 Table 10 4 SSC Interrupt Sources Interrupt Signal Description Transmission TIR Indicates that the transmit buffer can be reloaded with new starts data Transmission RIR The configured number of bits have been transmitted and ends shifted to the receive buffer Receive EIR This interru
218. ead to the setting of the corresponding interrupt status flags in register IS In order to monitor the selected capture events at the CCPOSx inputs in the multi input capture modes the 6 5 bits of the corresponding channel set when detecting the selected event The interrupt status bits and the CC6xST bits must be reset by software User s Manual 6 V 0 4 12 74 0 2 2005 01 techno ogies Capture Compare Unit 6 Table 12 5 Double Register Compare Modes Description Double Register Capture Modes 0100 The contents of T12 are stored in CC6nR after a rising edge and in CC6nSR after a falling edge on the input pin CC6n 0101 The value stored CC6nSR is copied to CC6nR after a rising edge on the input pin CC6n The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR This feature is useful for time measurements between consecutive rising edges on pins CC6n COUTEn is I O pin 0110 The value stored in CC6nSR is copied to CC6nR after a falling edge on the input pin CC6n The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR This feature is useful for time measurements between consecutive falling edges on pins CC6n COUTEn is pin 0111 The value stored in CC6nSR is copied to CC6nR after any edge on the input pin The actual timer value of T12 is simultaneously stored the shadow register CC6nSR This feature is useful for tim
219. ed 1 The additional prescaler for T13 is enabled T13R 4 rh T13 Run Bit T13R starts and stops timer T13 It is set reset by software by setting bit T13RR or T13RS or it is set reset by hardware according to the function defined by bit T13SSC and bit fields T13TEC and T13TED 0 Timer 13 is stopped 1 Timer T13 is running STE13 5 rh Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value the compare value and passive state select bit and level from their shadow registers to the actual registers if a T13 shadow transfer event is detected Bit STE13 is cleared by hardware after the shadow transfer 13 shadow transfer event is a period match 0 The shadow register transfer is disabled 1 The shadow register transfer is enabled 0 7 6 r Reserved Returns 0 if read should be written with 0 1 A concurrent set reset action on T13R from T13SSC T13TEC T13RR or T13RS will have no effect The bit T12R will remain unchanged User s Manual CCUG V 0 4 12 50 V 0 2 2005 01 techno ogies Capture Compare Unit 6 Note A write action to the bit field T12CLK or bit T12PRE is only taken into account when the timer T12 is not running T12R 0 A write action to the bit field T13CLK or bit T13PRE is only taken into account when the timer 13 is not running T13R 0 User s Manual 12 51 V 0 2 2005 01 CCU6 V 0 4 _ Infineo
220. ed default 1 Watchdog Window Boundary feature is enabled 7 6 Reserved Returns 0 if read should be written with 0 User s Manual Watchdog Timer V 0 4 9 6 V 0 2 2005 01 Infineon technologies XC866 Watchdog Timer WDTL Watchdog Timer Register Low Reset Value 00 7 6 5 4 3 2 1 0 WDT n WDTH Watchdog Timer Register High Reset Value 00 7 6 5 4 3 2 1 0 WDT rh Field Bits Type Description WDT 7 0 of rh Watchdog Timer Current Value WDTL 7 0 of WDTH WDTWINB Watchdog Window Boundary Count Reset Value 00 7 6 5 4 3 2 1 0 WDTWINB 1 Field Bits Description WDTWINB 7 0 Watchdog Window Boundary Count Value This value is programmable The WDT cannot do a refresh within the Window Boundary range from 0000 to the value obtained from the concatenation of WDTWINB and 00 as it would cause WDTRST to be asserted WDTWINB is matched to WDTH User s Manual Watchdog Timer V 0 4 9 7 V 0 2 2005 01 _ Infineon technologies XC866 Watchdog Timer PMCONO Power Mode Control Register 0 Reset Value See Table 8 1 7 6 5 4 3 2 1 0 0 WDTRST WKRS WKSEL SD PD WS r rwh rwh rw rw rwh rw The functions of the shaded bits are not described here Field Bits Description WDTRST 6 Wa
221. ed mode CRMR1 Conversion Request Mode Register 1 Reset Value 00 7 6 5 4 3 2 1 0 0 LDEV CLRPND SCAN ENSI ENTR 0 ENGT r rw rw rw r rw Field Bits Type Description ENGT 0 rw Enable Gate This bit enables the gating functionality for the request source 0 The gating line is permanently 0 The source is switched off 1 The gating line is permanently 1 The source is switched on ENTR 2 rw Enable External Trigger This bit enables the external trigger possibility If enabled the load event takes place if a rising edge is detected at the external trigger input REQTR 0 The external trigger is disabled 1 The external trigger is enabled ENSI 3 rw Enable Source Interrupt This bit enables the request source interrupt This interrupt can be generated when the last pending conversion is completed for this source while PND 0 0 The source interrupt is disabled 1 The source interrupt is enabled SCAN 4 rw Autoscan Enable This bit enables the autoscan functionality If enabled the load event is automatically generated when a conversion requested by this source is completed and PND 0 0 The autoscan functionality is disabled 1 The autoscan functionality is enabled User s Manual 13 46 V 0 2 2005 01 ADC V 0 3 _ Infineon technologies XC866 Analog to Digital Converter Field Bits Type Description CLRPND 5 Clear Pendin
222. ed by the arbiter and a conversion can only be started if REQCHNRV 1 and REQPND 1 If both request sources are programmed with the same priority the channel number specified by request source 0 will be converted first since it is connected to arbitration slot O The period of a complete arbitration round is fixed at tars 4 tapcp 13 3 Refer to Section 13 7 2 for register description of priority and arbitration control User s Manual 13 9 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter 13 4 2 Conversion Start Modes At the end of each arbitration round the arbiter would have found the request source with the highest priority and a pending conversion request It stores the arbitration result namely the channel number the sample time and the targeted result register for further actions If the analog part is idle a conversion can be started immediately If a conversion is currently running the arbitration result is compared to the priority of the currently running conversion If the current conversion has the same or a higher priority it will continue to completion Immediately after its completion the next conversion can begin As soon as the analog part is idle and the arbiter has output a conversion request the conversion will start In case the new conversion request has a higher priority than the current conversion two conversion start modes exist selectable by bit CSMx x
223. ed up by resetting bit XPD 4 The source of external oscillator is selected by setting bit OSCSS 5 Wait for 50 us until the external oscillator is stable 6 Restart the Oscillator Run Detection by setting bit OSC CON ORDRES If bit OSC_CON OSCR is set then 1 Select the VCO bypass mode VCOBYP 1 2 Reconnect oscillator to the PLL OSCDISC 0 3 Reprogram the NDIV factor to the required value 4 The RESLD bit must be set and the LOCK flag checked Only if the LOCK flag is set again can the VCO bypass mode be deselected and normal operation resumed In order to minimize power consumption while the on chip oscillator is used XTAL is powered down by setting bit XPD but when the external oscillator is used the on chip oscillator cannot be powered down by setting bit OSCPD 7 3 2 Clock Source Control The clock system provides four ways to generate CPU clock Direct Drive PLL Bypass Operation In PLL bypass operation the system clock has exactly the same frequency as the external clock source The PLL bypass is set inactive in the XC866 fosc User s Manual 7 11 V 0 2 2005 01 Power Reset and Clock V 0 4 Cnfineon XC866 techno ogies Power Supply Reset and Clock Management PLL Base Mode The system clock is derived from the VCO base frequency clock divided by the K factor Both VCO bypass and PLL bypass must be inactive for this PLL mode 1 fsys fyvcobase Prescaler Mode
224. eld Bits Type Description MCMEN 7 rw Multi Channel Mode Enable 0 The modulation of the corresponding output signal by a multi channel pattern according to bit field MCMP is disabled 1 The modulation of the corresponding output signal by a multi channel pattern according to bit field MCMP is enabled 0 6 r Reserved Returns 0 if read should be written with 0 MODCTRH Modulation Control Register High Reset Value 00 7 6 5 4 3 2 1 0 ECT 130 0 T13MODEN TW TE Field Bits Type Description T13MODEN 5 0 rw T13 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T13 The bit positions correspond to the following output signals Modulation of CC60 Bit 1 Modulation of COUT60 Bit 2 Modulation of CC61 Bit 3 Modulation of COUT61 Bit 4 Modulation of CC62 Bit 5 Modulation of COUT62 The enable feature of the modulation is defined as follows 0 The modulation of the corresponding output signal by a T13 PWM pattern is disabled 1 The modulation of the corresponding output signal by a T13 PWM pattern is enabled User s Manual 12 58 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description ECT130 7 rw Enable Compare Timer T13 Output 0 The alternate output function COUT63 is disabled 1 The alternate o
225. en no conversion is required in order to reduce power consumption The analog part of the ADC module may be disabled by resetting the ANON bit This causes the generation of fapc to be stopped and results in a reduction in power consumption Conversions are possible only by enabling the analog part ANON 1 again The wake up time is approximately 100 ns Refer to Section 13 7 1 for register description of disabling the ADC analog part e If the ADC functionality is not required at all it can be completely disabled by gating off its clock input fapc for maximal power reduction This is done by setting bit ADC DIS in register PMCON 1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management 1 Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 0 T2 DIS CCU DIS SSC DIS ADC DIS r rw rw rw rw The function of the shaded bit is not described here Field Bits Description ADC_DIS 0 rw ADC Disable Request Active high 0 ADC is in normal operation default 1 Request to disable the ADC 0 7 4 r Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 7 V 0 2 2005 01 _ nfineon XC866 techno ogies Analog to Digital Converter 13 4 Functional Description The ADC module functionality includes Two different conversion request sources Sequential and parallel
226. eon XC866 techno ogies Interrupt System 5 3 Interrupt Source and Vector Each interrupt input has an associated interrupt vector address This vector is accessed in order to service the corresponding interrupt source The assignment of the XC866 interrupt sources is summarized in Table 5 1 Table 5 1 Interrupt Vector Addresses Interrupt Vector Address Interrupt Sources Input NMI 00734 Watchdog Timer PLL Flash Interface Timer OCDS VDD and VDDP prewarning Flash ECC XINTRO 0003 External Interrupt 0 XINTR1 OOOBy Timer 0 XINTR2 0013 External Interrupt 1 XINTR3 001By Timer 1 XINTR4 0023 5 002By Timer 2 XINTR6 00334 ADC_SRC 1 0 XINTR7 003By SSC XINTR8 0043 External Interrupt 2 XINTR9 004By External Interrupt 6 3 XINTR10 0053 CCU6 INPO XINTR11 005 CCU6 INP1 XINTR12 0063 CCU6 INP2 XINTR13 006 CCU6 INP3 User s Manual 5 8 V 0 2 2005 01 Interrupt System V 0 5 _ Infineon XC866 techno ogies Interrupt System 5 4 Interrupt Register Description 5 4 1 Interrupt Enable Registers Each interrupt input can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO or IEN1 Register IENO also contains the global enable disable bit EA which can be cleared to disable all interrupts The NMI interrupt is shared by a number of sources each of which can
227. er clock into lower frequencies for power savings 7 1 Power Supply System with Embedded Voltage Regulator The XC866 microcontroller requires two different levels of power supply 3 3V or 5 0 V for the Embedded Voltage Regulator EVR and Ports 2 5 V for the core memory on chip oscillator and peripherals Figure 7 1 shows the XC866 power supply system A power supply of 3 3 V or 5 0 V must be provided from the external power supply pin The 2 5 V power supply for the logic is generated by the EVR The EVR helps reduce the power consumption of the whole chip and the complexity of the application board design CPU amp Peripheral Memory OSC logic Vp 25V GPIO Ports 3 3V 5 0V SSP Figure 7 1 866 Power Supply System User s Manual 7 1 V 0 2 2005 01 Power Reset and Clock V 0 4 Cnfineon XC866 techno ogies Power Supply Reset and Clock Management EVR Features Input voltage Vppp 3 3 V 5 0 V Output voltage Vpp 2 5 V 7 5 Low power voltage regulator provided in power down mode Vpp and Vppp prewarning detection Vpp brownout detection The EVR consists of a main voltage regulator and a low power voltage regulator In active mode both voltage regulators are enabled In power down mode the main voltage regulator is switched off while the low power
228. er event The event flag bit EV indicates if an external event has taken place and a conversion can be requested 0 Bit EV not used to start conversion request 1 Bit EV is used to start conversion request Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 41 V 0 2 2005 01 Infineon technologies XC866 Analog to Digital Converter The registers QBURO and QINRO share the same register address A read operation at this register address will deliver the rh bits of the QBURO register while a write operation to the same address will target the w bits of the QINRO register Register QBURO contains bits that monitor the status of an aborted sequential request QBURO Queue Backup Register 0 7 6 5 Reset Value 00 4 3 2 1 0 EXTR ENSI RF V 0 REQCHNR rh rh rh rh r rh Field Bits Type Description REQCHNR 2 0 Request Channel Number This bit field is updated by bit field QQRO REQCHNR when the conversion requested by QORs is started rh Request Channel Number Valid This bit indicates if the data in REQCHNR RF ENSI and EXTR is valid Bit V is set if a running conversion is aborted It is reset when the conversion is started 0 The backup register does not contain valid data because the conversion described by this data has not been aborted 1 The data is valid Th
229. er is set to a user defined start value and begins counting up It must be serviced before the counter overflows Servicing is performed through the refresh operation setting WDTRS to 1 This reloads the timer with the start value and normal operation continues If the WDT is not serviced before the timer overflows a system malfunction is assumed and normal mode is terminated A WDT NMI request WDTTO is then asserted and prewarning is entered The prewarning lasts for 30 count During the prewarning period refreshing of the WDT is ignored and the WDT cannot be disabled A reset WDTRST of the XC866 is imminent and can no longer be stopped The occurrence of a WDT reset is indicated by the bit WDTRST which is set to 1 once hardware detects the assertion of the signal WDTRST If refresh happens at the same time an overflow occurs WDT will not go into prewarning period The WDT must be serviced periodically so that its count value will not overflow Servicing the WDT clears the low byte and reloads the high byte with the preset value in bit field WDTREL Servicing the WDT also clears the bit WDTRS The WDT has a programmable window boundary which disallows any refresh during the WDT s count up A refresh during this window boundary constitutes an invalid User s Manual 9 2 V 0 2 2005 01 Watchdog Timer V 0 4 Cnfineon XC866 techno ogies Watchdog Timer access to the WDT and causes the WDT to activate WDTRST althou
230. er to specific details of the XC866 in terms of its architecture its functional units or functions A Accumulator 2 4 Alternate functions 6 10 Input 6 10 Output 6 3 6 10 Analog input clock 13 3 Analog to Digital Converter 13 1 Interrupt 13 21 Channel 13 23 Event 13 22 Node pointer 13 24 Low power mode 13 7 Module clock 13 3 Register description 13 31 Register map 13 28 Arbitration round 13 9 Arbitration slot 13 9 Arithmetic 2 2 Asynchronous modes 10 2 Automatic refill 13 11 Autoscan 13 15 B Baud rate 10 11 Baud rate clock 10 11 Baud rate generation 10 26 Baud rate generator 10 10 Bit protection scheme 3 12 Bitaddressable 3 9 Boot options 7 6 BSL mode 7 6 OCDS mode 7 6 User mode 7 6 User s Manual Boot ROM 3 1 Boot ROM operating mode 3 26 BootStrap Loader Mode 3 27 OCDS mode 3 27 User mode 3 26 Booting scheme 7 6 BootStrap Loader 3 27 4 6 4 9 Brownout reset 7 5 Buffer mechanism 4 4 C Cancel Inject Repeat 13 10 Capture Compare Unit 6 12 1 Register description 12 29 Register map 12 28 Central Processing Unit 2 1 Circular stack memory 4 4 Clock source 7 11 Clock system 7 9 Continuous transfer operation 10 25 Conversion error 13 4 Conversion phase 13 5 Correction algorithm 4 8 CPU 2 1 D Data Flash 4 2 4 3 Data memory 3 3 Data pointer 2 4 Data reduction 13 17 Counter 13 18 Debug 14 3 Events 14 3 15 1 V 0 2 2005 01 Infineon technologies XC866 D Flash 4 2 4
231. errupts Activated by the completion of any input channel conversion They are enabled according to the control bits for the limit checking The settings are defined individually for each input channel The interrupt compressor is an OR combination of all incoming interrupt pulses for each of the SR lines event interrupt unit channel interrupt routing Figure 13 12 Interrupt Overview Refer to Section 13 7 9 for description of the interrupt registers User s Manual 13 21 ADC V 0 3 to SRO to SR1 to SRO to SR1 interrupt SRO SR1 com pressor V 0 2 2005 01 _ Infineon XC866 techno ogies Analog to Digital Converter 13 4 8 1 Event Interrupts event 7 event 6 event 5 p SRO event 4 SRO rh to SRO interrupt PRI trigger O 5R1 to SR1 rw rw event 1 2 event O SRO to SRO interrupt trigger 0 5R1 to SR1 rw rw Figure 13 13 Event Interrupt Structure Event interrupts can be generated by the request sources and the result registers The event interrupt enable bits are located in the request sources ENSI and result register control IEN An interrupt node pointer EVINP for each event allows the selection of the targeted service output line A request source event is generated when the requested channel conversion is completed Event 0 Request source event of sequential reques
232. es Capture Compare Unit 6 Register ISR contains the individual interrupt request reset bits to reset the corresponding flags by software ISRL Capture Compare Interrupt Status Reset Register Low Reset Value 00 7 6 5 4 3 2 1 0 R R R R R R T12 T12 CC CC CC CC CC CC PM OM 62F 62R 61F 61R 60F 60R Ww Ww Field Bits Type Description RCC60R 0 w Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC60R in register IS will be reset RCC60F 1 Ww Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC60F in register IS will be reset RCC61R 2 Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS will be reset RCC61F 3 w Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC61F in register IS will be reset RCC62R 4 Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC62R in register IS will be reset RCC62F 5 Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC62F in register IS will be reset RT120M 6 Reset Timer T12 One Match Flag 0 No action 1 Bit T12OM in register IS will be reset RT12PM 7 Reset Timer T12 Period Match Flag 0 No action 1 Bit T12PM in register IS will be reset User s Manual 12 82 V 0 2 2005 01 6 V 0 4 _ lnfineon XC866 techno ogies Capture Compare Unit 6
233. es the port pin that is used for the CCPOS input signal 00 The input pin is selected for CCPOS1 0 01 The input pin is selected for CCPOS1 1 10 Reserved 11 Reserved ISPOS2 5 4 rw Input Select for CCPOS2 This bit field defines the port pin that is used for the CCPOS2 input signal 00 The input pin is selected for CCPOS2_0 01 The input is selected for CCPOS2 1 10 Reserved 11 Reserved IST12HR 7 6 rw Input Select for T12HR This bit field defines the port pin that is used for the T12HR input signal 00 The input pin is selected for T12HR 0 01 The input pin is selected for T12HR 1 10 The input pin is selected for T12HR 2 11 Reserved User s Manual 6 V 0 4 12 33 0 2 2005 01 techno ogies Capture Compare Unit 6 PISEL2 Port Input Select Register 2 Reset Value 00 7 6 5 4 3 2 1 0 0 IST13HR r rw Field Bits Type Description IST13HR 1 0 rw Input Select for T13HR This bit field defines the port pin that is used for the T13HR input signal 00 The input pin is selected for TT3HR O 01 The input pin is selected for TT3HR 1 10 input pin is selected for T1T3HR 2 11 Reserved 0 7 2 r Reserved Returns 0 if read should be written with 0 User s Manual 12 34 V 0 2 2005 01 CCUG V 0 4 _ Infineon XC866 techno ogies Capture Compare Unit 6 12 3 2 Timer T12 Related Registers The
234. ess MS 6 rw Master Select Bit 0 Slave mode Operate on shift clock received via SCLK 1 Master mode Generate shift clock and output it via SCLK EN 7 rw Enable Bit 1 Transmission and reception enabled Access to status flags and Master Slave control 0 5 r Reserved Returns 0 if read should be written with 0 Note The target of an access to CON control bits or flags is determined by the state of CON EN prior to the access that is writing CO57 to CON in programming mode CON EN 0 will initialize the SSC CON EN was 0 and then turn it on CON EN 1 When writing to CON ensure that reserved locations receive Zeros User s Manual Serial Interfaces V 0 3 10 36 V 0 2 2005 01 _ Infineon technologies XC866 Serial Interfaces 10 3 4 3 Baud Rate Timer Reload Register The SSC baud rate timer reload register BR contains the 16 bit reload value for the baud rate timer BRL Baud Rate Timer Reload Register Low Reset Value 00 7 6 4 3 2 1 0 BR_VALUE 7 0 AW Baud Rate Timer Reload Register High Reset Value 00 7 6 4 3 2 1 0 BR VALUE 15 8 nw Field Bits Type Description BR VALUE 7 0 of nw Baud Rate Timer Reload Register Value BRL Reading BR returns the 16 bit contents of the 7 0 of baud rate timer Writing to BR loads the baud rate BRH timer reload register with BR VALUE User s Manual Serial Interfaces V 0 3 10
235. et 00 Bit Field LB PO PH HB BM Control Register Low Type rw rw rw rw rw Programming Mode Operating Mode Bit Field 0 BC Type r rh 55 Reset 00 Bit Field EN MS 0 AREN BEN PEN REN TEN Control Register High Programming Mode Type rw rw r rw rw rw rw rw Operating Mode Bit Field EN MS 0 BSY BE PE RE TE Type rw rw r rh rwh rwh rwh rwh AC SSC_TBL Reset 004 Bit Field TB_VALUE Transmitter Buffer Register Low Type rw ADy SSC_RBL Reset 00 Bit Field RB_VALUE Receiver Buffer Register Low Type rh AEy SSC_BRL Reset 00 Bit Field BR_VALUE 7 0 Baudrate Timer Reload Register Low Type rw AFy SSC_BRH Reset 00 Bit Field BR_VALUE 15 8 Baudrate Timer Reload Register High Type rw User s Manual 3 24 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization 3 3 5 9 OCDS Registers The OCDS SFRs can be accessed in the mapped memory area RMAP 1 Table 3 9 OCDS Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 1 E94 MMCR2 Reset 00 Bit Field MMOD JENA Monitor Mode Control Register 2 P w rw w rwh w rwh rh rh Reset 00 BitField MRAM TRF RRF Monitor Mode Control Reg
236. etected while counting up f STE12 1 shadow transfer takes place when a period match is detected while counting up aone match is detected while counting down The timer T12 prescaler is reset when T12 is not running to ensure reproducible timings and delays 12 1 1 3 Switching Rules Compare actions take place in parallel for the three compare channels Depending on the count direction the compare matches have different meanings In order to get the User s Manual 12 4 V 0 2 2005 01 CCUG V 0 4 techno ogies Capture Compare Unit 6 PWM information independent of the output levels two different states have been introduced for the compare actions the active state and the passive state Both these states are used to generate the desired PWM as a combination of the control by T13 the trap control unit and the multi channel control unit If the active state is interpreted as a 1 and the passive state as a 0 the state information is combined with a logical AND function active AND active active e active AND passive passive passive AND passive passive The compare states change with the detected compare matches and are indicated by the CC6xST bits The compare states of T12 are defined as follows passive if the counter value is below the compare value active if the counter value is above the compare value This leads to the following switching rules for the compare states Set to the activ
237. f T13 reaches its period value In parallel to the reset action of bit T13R the bit CC63ST is reset User s Manual CCU6 V 0 4 12 52 V 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 Field Bits Type Description T13TEC 4 2 rw T13 Trigger Event Control Bit field T13TEC selects the trigger event to start T13 automatic set of T13R for synchronization to T12 compare signals according to following combinations 000 No action 001 Set T13R ona T12 compare event on channel 0 010 Set 1 T12 compare event on channel 1 011 Set T13R ona T12 compare event on channel 2 100 Set T13R on any T12 compare event on channel 0 1 or 2 101 Set T13R upon a period match of T12 110 Set T13R upon zero match of T12 while counting up 111 Set T13R on any edge of inputs CCPOSx T13TED 6 5 w Timer T13 Trigger Event Direction Bit field T13TED delivers additional information to control the automatic set of bit T13R in case the trigger action defined by T13TEC is detected 00 Reserved no action 01 While T12 is counting up 10 While T12 is counting down 11 Independent of the count direction of T12 0 7 r Reserved Returns 0 if read should be written with 0 Example If the timer T13 is intended to start at any compare event on T12 T13TEC 100p the trigger event direction can be programmed to counting up gt gt a T12 channel 0 1 2 compare
238. fected by the various reset types A m means that this function is reset to its default state Table 7 1 Effect of Reset on Device Functions Module Wake Up Watchdog Brownout Function Reset Reset Reset Reset Reset CPU Core H m On Chip Not affected Not affected Not affected Affected un Affected un Static RAM reliable reliable reliable reliable reliable Oscillator Not affected H E PLL Port Pins See Chapter 6 Parallel Ports EVR The voltage Not affected L regulator is switched on FLASH H NMI E Disabled Disabled 7 2 3 Booting Scheme When the XC866 is reset it must identify the type of configuration with which to start the different modes once the reset sequence is complete Thus boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins After power on reset or hardware reset the pins MBC TMS and 0 0 collectively select the different boot options Table 7 2 shows the available boot options in the 866 Table 7 2 XC866 Boot Selections MBC TMS 0 0 of Mode PC Start Value X X User Mode OSC PLL non bypassed 0000 0 0 X BSL Mode OSC PLL non bypassed 0000 1 0 OCDS Mode OSC PLL non bypassed 0000 User s Manual 7 6 V 0 2 2005
239. fetch execute timing related to the internal states and phases Execution of an instruction occurs at C1P1 For a 2 byte instruction the second reading starts at C1P1 Figure 2 2 a shows two timing diagrams for a 1 byte 1 cycle 1 x machine cycle instruction The first diagram shows the instruction being executed within one machine cycle since the opcode C1P2 is fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over two machine cycles instruction time extended with one wait state inserted for opcode fetching from the Flash memory Figure 2 2 b shows two timing diagrams for a 2 byte 1 cycle 1 x machine cycle instruction The first diagram shows the instruction being executed within one machine cycle since the second byte C1P1 and the opcode C1P2 are fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over three machine cycles instruction time extended with one wait state inserted for each access to the Flash memory two wait states inserted in total Figure 2 2 c shows two timing diagrams of a 1 byte 2 cycle 2 x machine cycle instruction The first diagram shows the instruction being executed over two machine cycles with the opcode C2P2 fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed
240. functions as a 16 bit timer and always counts up to FFFFy after which an overflow condition occurs Upon overflow bit TF2 is set and the timer reloads its registers with 0000 The setting of TF2 generates an interrupt request to the core Additionally with a falling rising edge chosen by T2MOD EDGESEL on T2EX the contents of the timer register THL2 are captured into the RC2 register If the capture signal is detected while the counter is being incremented the counter is first incremented before the capture operation is performed This ensures that the latest value of the timer register is always captured When the capture operation is completed bit EXF2 is set and can be used to generate an interrupt request Figure 11 7 describes the capture function of Timer 2 PB CLK 12 Overflow Figure 11 7 Capture Mode User s Manual 11 16 V 0 2 2005 01 Timer V 0 4 techno ogies Timer 11 2 3 Register Map All Timer 2 register names described in the following sections will be referenced in other chapters of this document with the module name prefix T2_ e g T2_T2CON The Timer 2 SFRs are located in the standard non mapped SFR area Table 11 3 lists the addresses of these SFRs Table 11 5 SFR Address List Address Register 2 T2MOD 2 RC2L RC2H C44 T2L 5 T2H 11 2 4 Register Description Register T2MOD is used to config
241. g Bits 0 No action 1 The bits in register CRPR1 are reset LDEV 6 Generate Load Event 0 No action 1 The load event is generated 0 1 7 r Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 47 V 0 2 2005 01 techno ogies Analog to Digital Converter 13 7 8 Result Registers The result registers deliver the conversion results and optionally the channel number that has lead to the latest update of the result register The result registers are available as different read views at different addresses The following bit fields can be read from the result registers depending on the selected read address For details on the conversion result alignment and width see Section 13 4 7 5 Field Bits Type Description RESULT RESRxL 7 6 rh Conversion Result RESRxH This bit field contains the conversion result or the or result of the data reduction filter RESRAxL 7 5 RESRAxH CHNR 2 0 rh Channel Number This bit field contains the channel number of the latest register update DRC 3 rh Data Reduction Counter This bit indicates how many conversion results have still to be accumulated to generate the final result for data reduction 0 The final result is available in the result register The valid flag is automatically set when this bit field is set to 0 1 One more conversion result must be added to obtain the final result in the result register The valid fl
242. g register is not 0 The highest bit position number among the pending bits with values equal to 1 specifies the channel number for conversion To take part in the source arbitration both the REQCHNRV and REQPND signals must be 1 Refer to Section 13 7 7 for description of the parallel request source registers 13 4 5 2 Request Source Control All conversion pending bits are ORed together to deliver an intermediate signal PND for generating REQCHNRV and REQPND The signal PND is gated with bit ENGT allowing the user to enable disable conversion requests See Figure 13 7 data written by CPU conversion request control register V7 parallel load conversion request pending register LDE bitwise set reset by arbiter PND REQPND REQCHNRV Figure 13 7 Parallel Request Source Control User s Manual 13 13 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter The load event for a parallel load can be External trigger at the input line REQTR See Section 13 4 5 3 Write operation to a specific address of the conversion request control register See Section 13 4 5 4 e Write operation with LDEV 1 to the request source mode register See Section 13 4 5 4 Source internal action conversion completed and 0 for autoscan mode See Section 13 4 5 5 Each bit bit x x 4 7 in the conversion request control pending registers corresponds to one analog inpu
243. ge 12 77 ISH Interrupt Status Register High Page 12 78 ISSL Interrupt Status Set Register Low Page 12 80 ISSH Interrupt Status Set Register High Page 12 81 ISRL Interrupt Status Reset Register Low Page 12 82 ISRH Interrupt Status Reset Register High Page 12 83 IENL Interrupt Enable Register Low Page 12 84 IENH Interrupt Enable Register High Page 12 85 INPL Interrupt Node Pointer Register Low Page 12 88 INPH Interrupt Node Pointer Register High Page 12 89 hh Note For all CCU6 registers the write only bit positions indicated by always deliver the value of 0 when they are read out If a hardware and a software request to modify a bit occur simultaneously the software wins 12 3 1 System Registers 12 3 1 1 Port Input Selection Registers PISELO and PISEL2 contain bit fields that select the actual input signals for the module inputs This permits the pin functionality of the device to be adapted as per the application s requirements The output pins are chosen according to the registers in the ports PISELOL Port Input Select Register 0 Low Reset Value 00 7 6 5 4 3 1 0 ISTRP ISCC62 ISCC61 ISCC60 rw rw rw rw User s Manual 12 31 V 0 2 2005 01 CCUG V 0 4 technologies Capture Compare Unit 6 Field Bits Type Description ISCC60 1 0 Input Select for CC60 This bit field defines the port pin that is used for the CC60 capture input signal 00 The input pin
244. general overview of the interrupt sources and illustrate the request and control flags User s Manual 5 2 V 0 2 2005 01 Interrupt System V 0 5 Infineon technologies XC866 Interrupt System WDT Overflow FNMIWDT NMIISR O NMIWDT 0 PLL Loss of Lock FNMIPLL o NMIISR 1 NMIPLL NMICON 1 Flash Timer Overflow FNMIFLASH TIMER NMIISR 2 NMIFLASH TIMER NMICON 2 Int 0 Int 1 Int 2 Int 3 Int 4 Int 5 OCDS int t FNMIOCDS Int 7 e RIMIS S NMIOCDS Maskable Int 10 NMICON 3 Interrupt Int 11 Int 12 Int 13 VDD Pre Warning FNMIVDD O NMIISR 4 NMIVDD NMICON 4 VDDP Pre Warning FNMIVDDP LL 9 o NSS NMIVDDP NMICON 5 Flash ECC Error FNMIECC _ o NMIISR 6 NMIECC NMICON 6 Figure 5 1 Non Maskable Interrupt Request Source User s Manual 5 3 V 0 2 2005 01 Interrupt System V 0 5 866 technologies Interrupt System Timer 0 Overflow Timer 1 Overflow Q277770 VU UART EINTO o EINT1 EXINT1 EXICONO 2 3 Y Bit addressable 4 Request flag is cleared by hardware
245. generation of the patterns for a 3 channel PWM is based on timer T12 The registers related to timer T12 can be concurrently updated with well defined conditions in order to ensure consistency of the three PWM channels Timer T12 supports capture and compare modes which can be independently selected for its three channels CC60 61 and 62 T12L Timer T12 Counter Register Low Reset Value 00 7 6 5 4 3 2 1 0 T12CVL rwh T12H Timer T12 Counter Register High Reset Value 00 7 6 5 4 3 2 1 0 T12CVH rwh Field Bits Type Description T12CV 7 0 of Timer T12 Counter Value T12L This register represents the 16 bit counter value of 7 0 of timer T12 T12H Note Once timer T12 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays User s Manual 12 35 V 0 2 2005 01 6 V 0 4 Infineon technologies XC866 Capture Compare Unit 6 T12PRL Timer T12 Period Register Low Reset Value 00 7 6 5 4 3 2 1 0 T12PVL rwh T12PRH Timer T12 Period Register High Reset Value 00 7 6 5 4 3 2 1 0 T12PVH rwh Field Bits Type Description T12PV 7 0 of rwh 1T12 Period Value T12PRL The value T12PV defines the counter value for T12 7 0 of which leads to a period match On reaching this T12PRH value the timer T12 is set to zero edge aligned mode
246. gh no NMI request is generated in this instance The window boundary is from 0000 to the value obtained from the concatenation of WDTWINB and 00 This feature can be enabled by WINBEN After being serviced the WDT continues counting up from the value lt WDTREL gt 28 The time period for an overflow of the WDT is programmable in two ways the input frequency to the WDT be selected via bit WDTIN in register WDTCON to be either 2 or 1 28 the reload value WDTREL for the high byte of WDT be programmed in register WDTREL The period Pwpr between servicing the WDT and the next overflow can be determined by the following formula _ 2 1 WDTIN 6 x 216 WDTREL x 28 WDT If the Window Boundary Refresh feature of the WDT is enabled the period between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL See also Figure 9 2 This period can be calculated by the same formula by replacing WDTREL with WDTWINB In order for this feature to be useful WDTWINB cannot be smaller than WDTREL Count WDTWINB 1 1 1 WDTREL 1 1 1 1 1 1 gt time No refresh Refresh allowe allowed Figure 9 2 WDT Timing Diagram User s Manual 9 3 V 0 2 2005 01 Watchdog Timer V 0 4 Infineon technologies XC866 Watchdog Timer Table 9 1 lists the possible ranges for the watchdog time
247. gram instruction is decoded by the instruction decoder This instruction decoder generates internal signals that control the functions of the individual units within the CPU The internal signals have an effect on the source and destination of data transfers and control the arithmetic logic unit ALU processing L N Internal Data 7 TENE Memory Core SFRs Register Interface Extemal Data Memory 2224 Extemal SFRs N 16 bit Registers amp Memory Interface rd amp Immediate Multiplier Divider Registers Opcode Decoder Timer 0 Timer 1 fo Memory Wait an Machine 5 UART Power Saving Reset Legacy External Interrupts IENO IEN1 External Interrupts Interrupt j Controller TT Non Maskable Interrupt Figure 2 1 CPU Block Diagram User s Manual 2 2 V 0 2 2005 01 Processor Architecture V 0 3 techno ogies Processor Architecture The arithmetic section of the processor performs extensive data manipulation and consists of the ALU ACC register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs both ar
248. h rwh rwh 5 1 Reset 00 Bit Field 0 ADCS ADCS RIR TIR EIR Interrupt Request Register 1 RC1 RCO Type r rwh rwh rwh rwh rwh B74 EXICONO Reset 00 Bit Field EXINT3 EXINT2 EXINT1 EXINTO External Interrupt Control Register 0 Type rw rw rw rw 1 Reset 00 Bit Field 0 EXINT6 EXINT5 4 External Interrupt Control Register 1 Type r rw rw rw Reset 00 Bit Field 0 NMI NMI NMI NMI NMI NMI NMI NMI Control Register ECC VDDP VDD OCDS FLASH PLL WDT TIMER Type r rw rw rw rw rw rw rw BC NMISR Reset 00 Bit Field 0 FNMI FNMI FNMI FNMI FNMI FNMI FNMI NMI Status Register ECC VDDP VDD OCDS FLASH PLL WDT TIMER Type r rwh rwh rwh rwh rwh rwh rwh BDy BCON Reset 00 Bit Field BGSEL 2 5 BREN BRPRE R Baud Rate Control Register Type rw rw rw rw rw BEy BG Reset 00 Bit Field BR_VALUE Baud Rate Timer Reload Register Type rw User s Manual 3 14 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 2 System Control Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 Page 1 ID Reset 01 Bit Field PRODID VERID Identity Register Type r r B44 Reset 00 Bit Field 0 WDT WKRS WK SD PD WS Power Mode Control Register O RST SEL
249. he SAMPLE flag is reset to indicate the sample phase is over while the BUSY flag continues to be asserted The BUSY flag is deasserted only at the end of the conversion phase with the corresponding source interrupt of the source that started the conversion asserted Write Result Phase twr At the end of the conversion phase the corresponding channel interrupt of the converted channel is asserted three periods later after the limit checking has been performed The result interrupt is asserted once the conversion result has been written into the target result register User s Manual 13 5 V 0 2 2005 01 ADC V 0 3 Infineon technologies XC866 Analog to Digital Converter Total Conversion Time The total conversion time synchronizing sampling charge redistribution tcowy is given by tconv tapc x 1 3 STC where 2 for 00g 01g or 10g 32 for 11g Conversion Time Control STC Sample Time Control n 8 or 10 for 8 bit and 10 bit conversion respectively 1 fApc 5 00 CTC 015g fapc 26 7 MHz 10 x 1 3 3 10 0 1 5 us User s Manual 13 6 ADC V 0 3 13 2 V 0 2 2005 01 Infineon technologies XC866 13 3 Low Power Mode Analog to Digital Converter The ADC module may be disabled either partially or completely wh
250. he data is transferred to the transmit register and TB8 is copied into the 9th bit position At phase 1 of the machine cycle following the next rollover in the divide by 16 counter the start bit is copied to TXD and data is activated one bit time later One bit time after the data is activated the data starts shifting right For the first shift a stop bit 1 is shifted in from the left and for subsequent shifts zeros are shifted in When the 8 bit gets to the output position the control block executes one last shift and sets the TI bit Reception is started by a high to low transition on RXD sampled at 16 times the baud rate The divide by 16 counter is then reset and 1111 1111 is written to the receive register If a valid start bit 0 is then detected based on two out of three samples it is shifted into the register followed by 8 data bits If the transition is not followed by a valid start bit the controller goes back to looking for a high to low transition on RXD When the start bit reaches the leftmost position the control block executes one last shift then loads SBUF with the 8 data bits loads RB8 SCON 2 with the 9th data bit and sets the RI bit provided RI 0 and either SM2 0 see Section 10 1 2 or the 9th bit 1 If none of these conditions is met the received byte is lost The baud rate for the transfer is either fpc 64 or fpc 32 depending on the setting of the top bit SMOD of the PCON Power Control reg
251. he same as the power on reset sequence as shown in Figure 7 2 A hardware reset through RESET pin will terminate the idle mode or the power down mode The status of pins MBC TMS and P0 0 is latched by the reset The latched value is used to select the boot options see Section 7 2 3 7 2 1 3 Watchdog Timer Reset The watchdog timer reset is an internal reset The Watchdog Timer WDT maintains a counter that must be refreshed or cleared periodically If the WDT is not serviced correctly and in time it will generate an NMI request to the CPU and then reset the device after a predefined time out period Bit PMCONO WDTRST is used to indicate the watchdog timer reset status For watchdog timer reset as the EVR is already stable and PLL lock detection is not needed the timing for watchdog timer reset is approximately 200 us which is shorter as compared to the other types of reset 7 2 1 4 Power Down Wake Up Reset Power is still applied to the XC866 during power down mode as the low power voltage regulator is still operating If power down mode is entered appropriately all important system state will have been preserved in the Flash by software If the XC866 is in power down mode three options are available to awaken it e through RXD through EXINTO through RXD or EXINTO User s Manual 7 4 V 0 2 2005 01 Power Reset and Clock V 0 4 techno ogies Power Supply Reset and Clock Management Selectio
252. ift clock signal SCLK This condition sets the error flag CON PE and when enabled via CON PEN sets the EIR A Baud Rate Error slave mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 i e it is either more than double or less than half the expected baud rate This condition sets the error flag CON BE and when enabled via CON BEN sets the EIR Using this error detection capability requires that the slave s baud rate generator be programmed to the same baud rate as the master device This feature detects false additional or missing pulses on the clock line within a certain frame User s Manual 10 28 V 0 2 2005 01 Serial Interfaces V 0 3 Cnfineon XC866 techno ogies Serial Interfaces Note If this error condition occurs and bit CON REN 1 an automatic reset of the SSC will be performed This is done to re initialize the SSC if too few or too many clock pulses have been detected A Transmit Error slave mode is detected when a transfer was initiated by the master SS_CLK gets active but the transmit buffer TB of the slave had not been updated since the last transfer This condition sets the error flag CON TE and when enabled via CON TEN sets the EIR If a transfer starts without the transmit buffer having been updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may l
253. imer register is always captured When the capture operation is completed bit T2CON EXF2 is set and can be used to generate an interrupt request The software will use the RC2 value of Timer 2 to retrieve the reload value BG VALUE and prescaler BRPRE of the baud rate generator The software updates the baud rate generator with the new BG value and prescaler value and generates the new baud rate The reload register of Timer 2 RC2 is reloaded with value 0000 by software User s Manual 10 18 V 0 2 2005 01 Serial Interfaces V 0 3 Cnfineon XC866 techno ogies Serial Interfaces 10 3 High Speed Synchronous Serial Interface The SSC supports full duplex and half duplex synchronous communication The serial clock signal can be generated by the SSC internally master mode using its own 16 bit baud rate generator or can be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPI compatible devices or devices using other synchronous serial interfaces Data is transmitted or received on lines TXD and RXD which are normally connected to the pins MTSR Master Transmit Slave Receive and MRST Master Receive Slave Transmit The clock signal is output via line MS_CLK Master Serial Shift Clock or input via line SS_CLK Slave Serial Shift Clock Both lines are normally connected to the pin SCLK Transmission and reception of data are d
254. ineon XC866 techno ogies Capture Compare Unit 6 INPL Capture Compare Interrupt Node Pointer Register Low Reset Value 404 7 6 5 4 3 2 1 0 62 CC61 CC60 Field Bits Type Description INPCC60 1 0 rw Interrupt Node Pointer for Channel 0 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit ICC6OR if enabled by bit ENCC6O0R or for bit ICC6OF if enabled by bit ENCC6OF 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPCC61 3 2 rw Interrupt Node Pointer for Channel 1 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit ICC61R if enabled by bit ENCC61R or for bit ICC61F if enabled by bit ENCC61F 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected User s Manual 12 88 V 0 2 2005 01 6 V 0 4 _ lnfineon XC866 techno ogies Capture Compare Unit 6 Field Bits Type Description INPCC62 5 4 rw Interrupt Node Pointer for Channel 2 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit I
255. inished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames For example two byte transfers would look the same as one word transfer This feature can be used to interface with devices that can operate with or require more than 8 data bits per transfer It is just a matter of software specifying the total data frame length This option can also be used to interface with byte wide and word wide devices Note This feature allows only multiples of the selected basic data width because it would require disabling enabling of the SSC to reprogram the basic data width on the fly 10 3 1 5 Port Control The SSC uses three lines to communicate with the external world as shown in Figure 10 13 Pin SCLK serves as the clock line while pins MRST and MTSR serve as the serial data input output lines Interrupt System 3 5 1 SSC PO 4 MTSR 1 Module MTSR Port Kernel MRST Control Slave PO 5 MRST_1 Master Slave Figure 10 13 SSC Module I O Interface Operation of the SSC I O lines depends on the selected operating mode master or slave The direction of the port lines depends on the operating mode The SSC will User s Manual 10 25 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces automatically use
256. into a single D Flash wordline WL At the beginning of this subroutine the Flash Timer NMI is enabled to enter the Flash Timer NMI service routine at each of the several timer underflows throughout the programming sequence Before calling this subroutine the user must ensure that the 32 byte WL contents are stored incrementally in the IRAM starting from the address specified in RO of Register Bank 3 In addition the input DPTRO EO DPSELO 0 must contain the D Flash WL address Otherwise bit PSW CY will be set and no programming will occur If valid inputs are available before calling the subroutine the microcontroller will continue to initialize the programming sequence includes transferring the 32 byte IRAM data to the D Flash write buffers exit the subroutine and then return to the user program code User program code will continue execution from where it last stopped until the next Flash Timer NMI is triggered and the Flash Timer NMI service routine entered see Figure 4 6 The Flash Timer NMI service routine will first check the Flash Timer NMI status bit NMISR FNMIFLASHTIMER 1 to ensure that the NMI source is from the Flash Timer before executing the remaining service routine instructions Table 4 1 D Flash Program Subroutine Subroutine DFF64 DFLASH PROG Input DPTRO D Flash WL address RO of Register Bank IRAM address 18 IRAM start address for 32 byte D Flash data 32 byte D Flash data Output PSW CY 0
257. ion Rotate Right Mode User s Manual 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 7 Interrupt Generation The interrupt generation can be triggered by the interrupt event or the setting of the corresponding interrupt bit in register IS by software The interrupt is generated independently of the interrupt flag in register IS Register IS can only be read write actions have no impact on the contents of this register The software can set or reset the bits individually by writing to register ISS or register ISR respectively If enabled by the related interrupt enable bit in register IEN an interrupt will be generated The interrupt sources of the CCU6 module can be mapped to four interrupt output lines by programming the interrupt node pointer register INP 12 1 8 Port Connection Table 12 2 shows how bits and bit fields must be programmed for the required functionality of the CCU6 I O lines This table also shows the values of the peripheral input select registers Table 12 2 CCU6 I O Control Selection Port Lines PISEL Register Bit Input Output Control Register Bits P3 6 CTRAP 0 ISTRP 00g DIR P6 Input P2 2 CTRAP 1 ISTRP 01g P2 DIR P2 Input 2 2 ISTRP 10g PO DIR P2 Input 2 0 50 0 ISPOSO 00g P2 DIR PO Input P1 5 CCPOSO 1 ISPOSO 01g P1 DIR P5 0p Input P2 1 CCPO
258. ion for bit CHE in register IS occurs The interrupt line that will be activated is selected by bit field INPCHE ENWHE 5 rw Enable Interrupt for Wrong Hall Event 0 No interrupt will be generated if the set condition for bit WHE in register IS occurs 1 An interrupt will be generated if the set condition for bit WHE in register IS occurs The interrupt line that will be activated is selected by bit field INPERR User s Manual 12 86 V 0 2 2005 01 CCU6 V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description ENIDLE Enable Idle This bit enables the automatic entering of the idle state bit IDLE will be set after a wrong hall event has been detected bit WHE is set During the idle state the bit field MCMP is automatically cleared 0 The bit IDLE is not automatically set when a wrong hall event is detected 1 The bit IDLE is automatically set when a wrong hall event is detected ENSTR Enable Multi Channel Mode Shadow Transfer Interrupt 0 No interrupt will be generated if the set condition for bit STR in register IS occurs 1 An interrupt will be generated if the set condition for bit STR in register IS occurs The interrupt line that will be activated is selected by bit field INPCHE Reserved Returns 0 if read should be written with 0 User s Manual CCU6 V 0 4 12 87 V 0 2 2005 01 Cnf
259. ister which acts as a Double Baud Rate selector 10 1 1 3 Mode 3 9 Bit UART Variable Baud Rate Mode 3 is the same as mode 2 in all respects except that the baud rate is variable and is set by the underflow rate on the dedicated baud rate generator In all modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in the modes by the incoming start bit if REN 1 The serial interface also provides interrupt requests when transmission or reception of the frames has been completed The corresponding interrupt request flags are TI or RI respectively If the serial interrupt is not used i e serial interrupt not enabled TI and RI can also be used for polling the serial interface The associated timings for transmit receive in modes 2 and 3 are illustrated in Figure 10 2 User s Manual 10 5 V 0 2 2005 01 Serial Interfaces V 0 3 866 technologies Serial Interfaces Transmit x C N m Q i a gt lt ES M 8 g j gt lt e rcl Cc E 8 em be ei i5 _ 3 8 E a _ _ a is a gt LITT lt 5 a gt lt ci Cc Mn ei 5 LIT lt
260. ister ED SP S Type hw rw w rwh rh rh F24 MMSR Reset 00 Bit Field MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWBO Monitor Mode Status Register M F F rw rh rwh rwh rwh rwh rwh rwh MMBPCR Reset 00 BitField SWBC HWB3C HWB2C HWB1 HWBOC BreakPoints Control Register rw rw rw rw rw F4y MMICR Reset 00 Bit Field DVECT DRETR 0 MMUIE MMUIE RRIE_ Monitor Mode Interrupt Control Register ED rwh rwh r w rw w rw F5 MMDR Reset 00 Bit Field MMRR Monitor Mode Data Register Receive Type rh Transmit Bit Field MMTR Type w F6y HWBPSR Reset 00 Bit Field 0 BPSEL BPSEL Hardware Breakpoints Select Register _ r rw F7y HWBPDR Reset 00 Bit Field HWBPxx Hardware Breakpoints Data Register Type rw User s Manual 3 25 V 0 2 2005 01 Memory Organization V 0 2 techno ogies Memory Organization 3 4 Boot ROM Operating Mode After a reset the CPU will always start by executing the Boot ROM code which occupies the program memory address space 00004 1 The Boot ROM start up procedure will first switch the address space for the Boot ROM to C000 DFFFy as shown in Figure 3 6 As a result the program memory Flash or ROM previously occupying the address range C000 DFFF will be mapped to 0000 1FFF instead After the address space switch the remaining Boot ROM start up procedure will be executed from 00 This inclu
261. ister Maps suas make GE Ee pner ERE E E RR UE eR aed n 11 17 11 2 4 Register Description 11 17 12 Capture Compare Unit 6 12 1 12 1 Functional Description 12 3 12 1 1 Timer MAS EP 12 3 12 1 1 1 Timer Configuration 12 4 12 1 1 2 Counting Rules 12 4 12 1 1 3 Switching Rules 12 4 12 1 1 4 Compare Mode 12 12 6 12 1 1 5 Duty Cycle of 0 and 100 12 7 12 1 1 6 Dead time Generation 12 8 12 1 1 7 Capture Mode 12 9 12 1 1 8 Single Shot Mode 12 9 12 1 1 9 Hysteresis Like Control Mode 12 10 12 1 2 Fimer T13 ssn COEM eoe A E RUE mee 12 11 12 1 2 1 Timer x noe es ERE RE WEE 12 11 12 1 2 2 Compare Mode 12 12 12 1 2 3 Single Shot Mode 12 12 12 1 2 4 Synchronization of T13 to 12 12 13 12 1 3 Modulation Control cse sexe aa 12 13 12 1 4 Trap handing M Tr 12 16 12 1 5 Multi Channel 12 17 12 1 6 Hall Sensor Mode
262. ister Selection This bit field defines which result register will be the target of a conversion of this channel 00 The result register 0 is selected 01 The result register 1 is selected 10 The result register 2 is selected 11 The result register 3 is selected LCC 6 4 rw Limit Check Control This bit field defines the behavior of the limit checking mechanism See coding in Section 13 4 8 2 0 32 7 r Reserved Returns 0 if read should be written with 0 User s Manual 13 36 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter 13 7 5 Input Class Register Register INPCRO contains bits that control the sample time for the input channels INPCRO Input Class 0 Register Reset Value 00 7 6 5 4 3 2 1 0 STC 1 Field Bits Type Description STC 7 0 rw Sample Time Control This bit field defines the additional length of the sample time given in terms of fApc clock cycles A sample time of 2 analog clock cycles is extended by the programmed value User s Manual 13 37 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter 13 7 6 Sequential Source Registers These registers contain the control and status bits of sequential request source 0 Register QMRO contains bits that are used to set the sequential request source in the desired mode QMRO
263. it CC63ST is related to T13 1 O In compare mode the timer count is less than the compare value In capture mode the selected edge has not been detected since the bit was reset by software 1 In compare mode the counter value is greater than or equal to the compare value In capture mode the selected edge has been detected CCPOSO 2 rh Sampled Hall Pattern Bits CCPOS1 4 Bits CCPSOx x 0 2 indicate the value of the input CCPOS2 5 Hall pattern that has been compared to the current and expected value The value is sampled when the event Hall compare ready occurs 0 The input CCPOSx has been sampled as 0 1 The input CCPOSx has been sampled as 1 0 7 r Reserved Returns 0 if read should be written with O 1 These bits are set and reset according to the T12 and T13 switching rules User s Manual 12 45 CCUG V 0 4 V 0 2 2005 01 Infineon technologies XC866 Capture Compare Unit 6 CMPSTATH Compare State Register High Reset Value 00 7 6 5 4 3 2 1 0 T13 C C C CC C cc IM OUT63PS OUT62PS 62PS OUT61PS 61PS OUT60PS 60PS rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description CC60PS 0 rwh Passive State Select for Compare Outputs CC61PS 2 Bits CC6xPS and COUT6xPS x 0 2 select the CC62PS 4 state of the corresponding compare channel which is COUT60PS 1 considered to be the passive state During the passive COUT61PS
264. ith automatic reload as shown in Figure 11 3 for Timer 0 An overflow from TLx not only sets TFx but also reloads TLx with the contents of THx that has been preset by software The reload leaves THx unchanged IL Interrupt Reload GATEO Timer Mode2 Figure 11 3 Timer 0 Mode 2 8 bit Timer with Auto Reload User s Manual 11 5 V 0 2 2005 01 Timers V 0 4 techno ogies Timers 11 1 2 4 Mode 3 In mode 3 Timer 0 and Timer 1 behave differently Timer 0 in mode 3 establishes TLO and THO as two separate counters Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 The logic for mode 3 operation for Timer 0 is shown in Figure 11 4 TLO uses the Timer 0 control bits TRO and TFO while THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now sets TF1 upon overflow and generates an interrupt if ET1 is set Mode 3 is provided for applications requiring an extra 8 bit timer When Timer 0 is in mode 3 and TR1 is set Timer 1 be turned on by switching it to any of the other modes and turned off by switching it into mode 3 Timer Clock TO Interrupt Control 1 GATEO THO EXINTO 8 Bits s Interrupt TR1 Timer Mode3 Figure 11 4 Timer 0 Mode 3 Two 8 bit Timers User s Manual 11 6 V 0 2 2005 01 Timers V 0 4
265. ithin the microcontroller from the basic clock It consists of Basic clock slow down circuitry Centralized enable disable circuit for clock control Figure 7 5 shows the clock generation from the system frequency In normal running mode the typical frequencies of different modules are as follows CPU clock SCLK 26 7 MHz e CCU6 clock 26 7 MHz Other peripherals PCLK 26 7 MHz Flash Interface clock CCLK3 80 MHz and CCLK 26 7 MHz Furthermore the oscillator clock outputs to pin CLKOUT PO 0 In idle mode only the CPU clock CCLK is disabled In power down mode CCLK SCLK CCLK3 and PCLK are all disabled If slow down mode is enabled the clock to the core and peripherals will be divided by a programmable factor that is selected by the bit field CMCON CLKREL CLKREL fsys 80MHz CLKOUT FLASH Interface Figure 7 5 Clock Generation from fsys User s Manual 7 13 V 0 2 2005 01 Power Reset and Clock V 0 4 techno ogies Power Supply Reset and Clock Management 7 3 4 Register Description OSC_CON OSC Control Register Reset Value 0000 1000 7 6 5 4 3 2 1 0 0 OSCPD XPD OSCSS ORDRES OSCR r rw rw rw rwh rh Field Bits Description OSCR 0 rh Oscillator Run Status Bit This bit shows the state of the oscillator run detection 0 The oscillator is not running 1 The oscillator is running ORDRES 1 r
266. ithmetic and logic operations Arithmetic operations include add subtract multiply divide increment decrement BCD decimal add adjust and compare Logic operations include AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations such as set clear complement jump if set jump if not set jump if set and clear and move to from carry The ALU can perform the bit operations of logical AND or logical OR between any addressable bit or its complement and the carry flag and place the new result in the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit Program Counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence User s Manual 2 3 V 0 2 2005 01 Processor Architecture V 0 3 Cnfineon XC866 techno ogies Processor Architecture 2 2 CPU Register Description The CPU registers occupy direct Internal Data Memory space locations in the range 80 to 2 2 1 Stack Pointer SP The SP register contains the Stack Pointer SP The SP is used to load the Program Counter PC into Internal Data Memory during LCALL and ACALL instructions and to retrieve the PC from memory during RET and RETI inst
267. kes approximately 500 ns to stabilize The PLL will be locked within 200 us after the on chip oscillator clock is detected for stable nominal frequency 5 Subsequently the FLASH will enter ready to read mode This does not require the typical 160 us as is the case for the normal reset The timing for this part can be ignored 6 The CPU operation is resumed If wake up source is EXINTO pin the interrupt will be serviced if EXINTO is enabled before entering power down mode Upon RETI instruction the core will return to execute the next instruction after the instruction which sets the PD bit If wake up source is RXD pin the core will return to execute the next instruction after the instruction which sets the PD bit 8 1 4 Peripheral Clock Management The degree of reduction in power consumption that can be achieved by this feature depends on the number of peripherals running Peripherals that are not required for a particular functionality can be disabled by gating off the clock inputs For example in idle mode if all timers are stopped and ADC CCU6 and the serial interfaces are not running maximum power reduction can be achieved However the user must take care in determining which peripherals should continue running and which must be stopped during active and idle modes The ADC SSC CCU6 and Timer 2 can be disabled clock is gated off by setting the corresponding bit in the PMCON 1 register Furthermore the analog part of the ADC mo
268. l Register Reset Value 304 7 6 5 4 3 2 1 0 ANON DW CTC 0 rw rw rw Field Bits Type Description CTC 5 4 rw Conversion Time Control This bit field defines the divider ratio for the divider stage of the internal analog clock fapc This clock provides the internal time base for the conversion and sample time calculations 00 fADCI 1 2 x 01 fADCI 1 3 10 fADCI 1 4 11 fADCI 1 32 x default DW 6 rw Data Width This bit defines the conversion resolution 0 The result is 10 bits wide default 1 The result is 8 bits wide ANON 7 rw Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode 0 The analog part is switched off and conversions are not possible To achieve minimal power consumption the internal analog circuitry is in its power down state and the generation of fapc is stopped 1 The analog part of the ADC module is switched on and conversions are possible The automatic power down capability of the analog part is disabled User s Manual 13 31 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter Field Bits Type Description 0 3 0 r Reserved Returns 0 if read should be written with 0 Register GLOBSTR contains bits that indicate the current status of a conversion GLO
269. ld be written with 0 P1 PUDSEL Port 1 Pull Up Pull Down Select Register Reset Value FFy 7 6 5 4 3 2 1 0 P7 P6 P5 0 P1 PO rw rw rw r rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 1 Bit n n 0 1 5 7 0 Pull down device is selected 1 Pull up device is selected default 0 4 2 r Reserved Returns 0 if read should be written with 0 User s Manual 6 22 V 0 2 2005 01 Parallel Ports V 0 3 technologies Parallel Ports P1 PUDEN Port 1 Pull Up Pull Down Enable Register Reset Value 7 6 5 4 3 2 1 0 P7 P6 P5 0 1 rw rw rw r rw rw Field Bits Description Pn n rw Pull Up Pull Down Enable at Port 1 Bit n n 0 1 5 7 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled default 0 4 2 Reserved Returns 0 if read should be written with 0 P1 ALTSELn n 0 1 Port 1 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 P6 P5 0 P1 PO nw rw rw r rw rw Table 6 8 Function of Bits P1 ALTSELO Pn and P1_ALTSEL1 Pn P1 ALTSELO Pn P1 ALTSEL1 Pn Function 0 0 Normal GPIO 1 0 Alternate Output 1 0 1 Alternate Output 2 1 1 Reserved User s Manual 6 23 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 Parallel Ports 6 5 Port 2 Port P2 is an 8 bit general purpose input only port Th
270. lid entry TREV 6 Trigger Event 0 No action 1 A trigger event is generated by software If the source waits for a trigger event a conversion request is started CEV 7 Clear Event Bit 0 No action 1 Bit EV is cleared 0 1 r Reserved Returns 0 if read should be written with 0 User s Manual ADC V 0 3 13 39 V 0 2 2005 01 nfineon XC866 techno ogies Analog to Digital Converter Register QSRO contains bits that indicate the status of the sequential source QSRO Queue Status Register Reset Value 204 7 6 5 4 3 2 1 0 0 EMPTY EV 0 r rh rh r Field Bits Type Description EV 4 rh Event Detected This bit indicates that an event has been detected while V 1 Once set this bit is reset automatically when the requested conversion is started 0 An event has not been detected 1 An event has been detected EMPTY 5 rh Queue Empty This bit indicates if the queue QORO contains a valid entry It is incremented each time a new entry is written to QINRO It is decremented each time a conversion request from the queue is started A new entry is ignored if the queue is filled 0 0 The queue is filled 1 valid entry 1 The queue is empty 0 3 0 r Reserved 7 6 Returns 0 if read should be written with 0 Register QORO contains bits that monitor the status of the current sequential request QORO Queue
271. ll event The possible hardware synchronization events are aT12 zero match while counting up T12zm e T13 zero match T13zm User s Manual 12 18 V 0 2 2005 01 CCUG V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 6 Hall Sensor Mode In Brushless DC motors the next multi channel state values depend on the pattern of the Hall inputs There is a strong correlation between the Hall pattern CURH and the modulation pattern MCMP Because of different machine types the modulation pattern for driving the motor can vary Therefore it is beneficial to have wide flexibility in defining the correlation between the Hall pattern and the corresponding modulation pattern The CCU6 offers this by having a register which contains the actual Hall pattern CURHS the next expected Hall pattern EXPHS and its output pattern MCMPS At every correct Hall event a new Hall pattern with its corresponding output pattern can be loaded from a predefined table by software into the register MCMOUTS This shadow register can also be loaded by a write action on MCMOUTS with bit STRHP 1 In case of a phase delay generated by T12 channel 1 a new pattern can be loaded when the multi channel mode shadow transfer indicated by bit STR occurs 12 1 6 1 Sampling of the Hall Pattern The Hall pattern on CCPOSx is sampled with the module clock fecus By using the dead time counter mode MSEL6x 1000p a hardware
272. lue 00 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 nw nw nw nw nw nw nw nw Field Bits Type Description Pn n nw Port 3 Pin n Direction Control n20 7 0 Direction is set to input default 1 Direction is set to output User s Manual 6 31 V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon technologies XC866 Parallel Ports P3 OD Port 3 Open Drain Control Register Reset Value 00 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 3 Pin n Open Drain Mode n 0 7 0 Normal mode output is actively driven for 0 and 1 state default 1 Open drain mode output is actively driven only for 0 state P3_PUDSEL Port 3 Pull Up Pull Down Select Register Reset Value BFy 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 3 Bit n n 0 7 0 Pull down device is selected 1 Pull up device is selected User s Manual 6 32 V 0 2 2005 01 Parallel Ports V 0 3 technologies Parallel Ports P3 PUDEN Port 3 Pull Up Pull Down Enable Register Reset Value 404 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port
273. ly be cleared by software or reset to the default value after the power on reset hardware reset brownout reset The register value is retained on any other reset such as watchdog timer reset or power down wake up reset This allows the system to detect what caused the previous NMI User s Manual 5 18 V 0 2 2005 01 Interrupt System V 0 5 Infineon technologies 5 4 3 Each interrupt source can be individually programmed to one of the four possible priority levels Two pairs of interrupt priority registers are available to program the priority level of each interrupt vector The first pair of registers is SFRs IP and IPH XC866 Interrupt System Interrupt Priority Registers IP Interrupt Priority Register Reset Value 00 7 5 4 3 2 1 0 0 2 PT1 PX1 PTO rw rw rw rw rw rw IPH Interrupt Priority Register High Reset Value 00 7 5 4 3 2 1 0 0 PT2H PSH PT1H PX1H PTOH r rw rw rw rw rw rw Field Bits Type Description PXO 0 rw Priority Level for External Interrupt 0 1 rw Priority Level for Timer 0 Overflow Interrupt 1 2 rw Priority Level for External Interrupt 1 PX1H PT1 3 rw Priority Level for Timer 1 Overflow Interrupt PT1H PS 4 rw Priority Level for Serial Port Interrupt PSH PT2 5 rw Priority Level for Timer 2 Interrupt PT2H 0 7 6 r Reserved Returns 0 if read should be written with
274. ly be read read only The bit or bit field can only be written write only Reading always return O h The bit or bit field can also be modified by hardware such as a status bit This attribute can be combined with rw or r bits to rwh and rh bits respectively User s Manual 1 13 V 0 2 2005 01 Intro V 0 3 Infineon technologies XC866 Introduction 1 6 Acronyms Table 1 4 lists the acronyms used in this document Table 1 4 Acronyms ADC Analog to Digital Converter ALU Arithmetic Logic Unit BSL BootStrap Loader CCU6 Capture Compare Unit 6 CGU Clock Generation Unit CPU Central Processing Unit ECC Error Correction Code EVR Embedded Voltage Regulator FIFO First In First Out GPIO General Purpose IAP In Application Programming I O Input Output ISP In System Programming JTAG Joint Test Action Group LIN Local Interconnect Network NMI Non Maskable Interrupt OCDS On Chip Debug Support PC Program Counter POR Power On Reset PLL Phase Locked Loop PSW Program Status Word PWM Pulse Width Modulation RAM Random Access Memory ROM Read Only Memory SFR Special Function Register SPI Serial Peripheral Interface SSC Synchronous Serial Controller UART Universal Asynchronous Receiver Transmitter WDT Watchdog Timer User s Manual Intro 0 3 1 14 0 2 2005 01 Cnfineon XC
275. m enters the power down mode Exiting Power down Mode If power down mode is exited via a hardware reset the device is put into the hardware reset state When the wake up source and wake up type have been selected prior to entering power down mode the power down mode can be exited via EXINTO pin RXD pin User s Manual 8 3 V 0 2 2005 01 SCU V 0 4 Cnfineon XC866 techno ogies Power Saving Modes Bit MODPISEL URRIS is used to select one of the two RXD inputs and bit MODPISEL EXINTOIS is used to select one of the two EXINTO inputs If bit WKSEL was set to 1 before entering power down mode the system will execute a reset sequence similar to the power on reset sequence Therefore all port pins are put into their reset state and will remain in this state until they are affected by program execution If bit WKSEL was cleared to 0 before entering power down mode a fast wake up sequence is used The port pins continue to hold their state which was valid during power down mode until they are affected by program execution The wake up from power down without reset uses the following procedures 1 In power down mode EXINTO pin RXD pin must be held at high level 2 Power down mode is exited when EXINTO pin RXD pin goes low for at least 100 ns 3 The main voltage regulator is switched on and takes approximately 150 us to become stable 4 The on chip oscillator and the PLL are started Typically the on chip oscillator ta
276. match triggers T13R only while T12 is counting up counting down gt gt a T12 channel 0 1 2 compare match triggers T13R only while T12 is counting down independent of bit CDIR gt gt each T12 channel 0 1 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR As a result if T12 is running in edge aligned mode counting up only T13 can only be started automatically if bit field T13TED 01g or 11g User s Manual 12 53 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 TCTR2H Timer Control Register 2 High Reset Value 00 7 6 5 4 3 2 1 0 0 T13 T12 RSEL RSEL 2 2 Field Bits Type Description T12RSEL 1 0 rw Timer T12 External Run Selection Bit field T12RSEL defines the event of signal T12HR that can set the run bit T12R by hardware 00 external setting of T12R is disabled 01 Bit T12R is set if a rising edge of signal T12HR is detected 10 Bit T12R is set if a falling edge of signal T12HR is detected 11 Bit T12R is set if an edge of signal T12HR is detected T13RSEL 3 2 rw Timer T13 External Run Selection Bit field T13RSEL defines the event of signal T13HR that can set the run bit T13R by hardware 00 external setting of T13R is disabled 01 Bit T13R is set if a rising edge of signal T13HR is detected 10 Bit T13R is set if a falling edge of signal TT3HR is detected 11 Bit T1
277. mmediate update of bit field MCMP by the value written to bit field MCMPS This functionality permits an update triggered by software When read this bit always delivers O 0 Bit field MCMP is updated according to the defined hardware action The write access to bit field MCMPS does not modify bit field MCMP 1 Bit field MCMP is updated by the value written to bit field MCMPS 0 6 r Reserved Returns 0 if read should be written with 0 User s Manual 12 65 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 MCMOUTSH Multi Channel Mode Output Shadow Register High Reset Value 00 7 6 5 4 3 2 1 0 STR 1h 0 CURHS EXPHS Ww r rw rw Field Bits Type Description EXPHS 2 0 rw Expected Hall Pattern Shadow Bit field EXPHS is the shadow bit field for bit field EXPH The bit field is transferred to bit field EXPH if an edge on the hall input pins CCPOSx x 0 2 is detected CURHS 5 3 rw Current Hall Pattern Shadow Bit field CURHS is the shadow bit field for bit field CURH The bit field is transferred to bit field CURH if an edge on the hall input pins CCPOSx x 0 2 is detected STRHP 7 Shadow Transfer Request for the Hall Pattern Setting these bits during a write action leads to an immediate update of bit fields CURH and EXPH by the value written to bit fields CURHS and EXPHS This functionality permits an update triggered by
278. n technologies XC866 Capture Compare Unit 6 Register TCTR2 controls the single shot and the synchronization functionality of both timers T12 and T13 Both timers can run in single shot mode In this mode they stop their counting sequence automatically after one counting period with a count value of zero The single shot mode and the synchronization of T13 to T12 allow the generation of events with a programmable delay after well defined PWM actions of T12 For example this feature can be used to trigger AD conversions after a specified delay to avoid problems due to switching noise synchronously to a PWM event TCTR2L Timer Control Register 2 Low Reset Value 00 7 6 5 4 3 2 1 0 0 T13 T13 T13 T12 TED TEC SSC SSC r IW nw rw rw Field Bits Type Description T12SSC 0 rw Timer 12 Single Shot Control This bit controls the single shot mode of T12 0 The single shot mode is disabled no hardware action on T12R 1 The single shot mode is enabled the bit T12R is reset by hardware if T12 reaches its period value edge aligned mode 12 reaches the value 1 while counting down in center aligned mode In parallel to the reset action of bit T12R the bits CC6xST x 0 2 are reset T13SSC 1 rw Timer T13 Single Shot Control This bit controls the single shot mode of T13 0 1 No hardware action on T13R The single shot mode is enabled the bit T13R is reset by hardware i
279. n Wake up Reset 0010 0000p User s Manual 7 8 Power Reset and Clock V 0 4 V 0 2 2005 01 _ Infineon XC866 techno ogies Power Supply Reset and Clock Management 7 3 Clock System The XC866 clock system performs the following functions Acquires and buffers incoming clock signals to create a master clock frequency Distributes in phase synchronized clock signals throughout the system Divides a system master clock frequency into lower frequencies for power saving mode 7 3 1 Clock Generation Unit The Clock Generation Unit CGU in the 866 consists of an oscillator circuit and a Phase Locked Loop PLL In the XC866 the oscillator can be from either of these two sources the on chip oscillator 10 MHz or the external oscillator 3 MHz to 12 MHz The term oscillator is used to refer to both on chip oscillator and external oscillator unless otherwise stated After the reset the on chip oscillator will be used by default The external oscillator can be selected via software The PLL can convert a low frequency external clock signal from the oscillator circuit to a high speed internal clock for maximum performance Figure 7 4 shows the block diagram of CGU osc fail detect lock detect gt core 1 PLLBYP OSCDISC NDIV VCOBYP Figure 7 4 CGU Block Diagram User s Manual 7 9 V 0
280. n of these options is made via the control bit PMCONO WS The wake up from power down can be with reset or without reset this is chosen by the PMCONO WKSET bit The wake up status with or without reset is indicated by the PMCONO WKRS bit Figure 7 3 shows the power down wake up reset sequence The EVR takes approximately 150 us to become stable which is a shorter time period as compared to the power on reset FLASH go to Reset is Ready to Read released Mode start of program 160 us EVR is stable PLL is locked yp 150 us Max 200 us Figure 7 3 Power down Wake up Reset In addition to the above mentioned three options the power down mode can also be exited by the hardware reset through RESET pin 7 2 1 5 Brownout Reset In active mode the Vpp detector in EVR detects brownout when the core supply voltage Vpp dips below the threshold voltage 2 1 V brownout will cause the device to be reset In power down mode the Vpp is monitored by the POR in EVR and a reset is generated when Vpp drops below 1 6 V Once the brownout reset takes place the reset sequence is the same as the power on reset sequence as shown in Figure 7 2 User s Manual 7 5 V 0 2 2005 01 Power Reset and Clock V 0 4 Infineon technologies 7 2 2 866 Power Supply Reset and Clock Management Module Reset Behavior Table 7 1 shows how the functions of the XC866 are af
281. nd reception disabled Access to control bits Reserved Returns 0 if read should be written with 0 User s Manual Serial Interfaces V 0 3 10 34 V 0 2 2005 01 _ Infineon technologies CON EN 1 Operating Mode XC866 Serial Interfaces CONL Control Register Low Reset Value 00 7 6 5 4 3 2 1 0 0 BC r rh Field Bits Type Description BC 3 0 rh Bit Count Field 0001 1111 Shift counter is updated with every shifted bit 0 7 4 Ir Reserved Returns 0 if read should be written with 0 CONH Control Register High Reset Value 00 7 6 5 4 3 2 1 0 EN MS 0 BSY BE PE RE TE rw rw r rh rwh rwh rwh rwh Field Bits Type Description TE 0 rwh Transmit Error Flag 0 No error 1 Transfer starts with the slave s transmit buffer not being updated RE 1 rwh Receive Error Flag 0 No error 1 Reception completed before the receive buffer was read PE 2 rwh Phase Error Flag 0 No error 1 Received data changes around sampling clock edge User s Manual 10 35 V 0 2 2005 01 Serial Interfaces V 0 3 Infineon technologies XC866 Serial Interfaces Field Bits Type Description BE 3 rwh Baud rate Error Flag 0 No error 1 More than factor 2 or 0 5 between slave s actual and expected baud rate BSY 4 rh Busy Flag Set while a transfer is in progr
282. nd written by software Register T13PR contains the period value for timer T13 The period value is compared to the actual counter value of T13 and the resulting counter actions depend on the defined counting rules The bit CC63ST indicates the occurrence of a compare event of the corresponding channel It can be set if it is 0 by the following events asoftware set MCC63S acompare set event T13 counter value above the compare value if the T13 runs and if the T13 set event is enabled The bit CC63ST can be reset if it is 1 by the following events asoftware reset MCC63R acompare reset event T13 counter value below the compare value if the T13 runs and if the T13 reset event is enabled including in single shot mode at the end of the T13 period Timer T13 is used to modulate the other output signals with T13 PWM In order to decouple COUT63 from the internal modulation the compare state can be selected independently by bits 1 and COUT63PS 12 1 2 3 Single Shot Mode The single shot mode of timer T13 is selected when bit T13SSC is set to 1 In single shot mode the timer T13 stops automatically at the end of its counting period If the end of period event is detected while bit T13SSC is set the bit T13R and the bit CC63ST are reset User s Manual 12 12 V 0 2 2005 01 6 V 0 4 techno ogies Capture Compare Unit 6 12 1 2 4 Synchronization of T13 to T12 The timer T13 can be synchro
283. nel registers Open drain control register 6 7 Normal mode 6 2 6 7 Open drain mode 6 2 6 7 Parallel request source 13 13 Permanent arbitration 13 9 Personal computer host 4 9 P Flash 4 2 4 3 Phase Locked Loop 7 9 Changing PLL parameters 7 11 Loss of Lock operation 7 10 Loss of Lock recovery 7 10 Pin Configuration 1 5 Definitions and functions 1 6 PLL Loss of lock 7 10 Startup 7 10 PLL base mode 7 12 PLL bypass 7 11 PLL mode 7 12 Power control 2 7 Power saving modes 8 1 Power supply system 7 1 Power down mode 7 13 8 3 V 0 2 2005 01 Infineon technologies XC866 Entering power down mode 8 3 Exiting power down mode 8 3 Power down wake up reset 7 4 Power on reset 7 2 7 3 Prescaler mode 7 12 Prewarning period 9 2 Processor architecture 2 1 Instruction timing Machine cycle 2 8 Register description 2 4 Program counter 2 3 Program Flash 4 2 4 3 Program memory 3 3 Program status word 2 5 Pull down device 6 8 Pull up device 6 8 Pulse width modulation 12 1 R Read access time 4 1 Receive buffered 10 2 Request gating 13 12 Request trigger 13 12 13 14 13 25 CCU6 Event 13 25 Reset control 7 3 Module behavior 7 6 Result FIFO 13 19 Result read view 13 19 Accumulated 13 19 Normal 13 19 ROM devices 3 1 3 2 ROM program memory 3 1 RS 232 4 9 S Sample phase 13 5 Schmitt Trigger 6 2 6 4 Sectorization 4 3 Sequential request source 13 11 Serial data 6 2 Serial interfaces 10 1 10 18 Serial port 6 2
284. neon a E naan ur 27 C eem ep m m reo em E ee Je gt 8 L E gt pe i m m m m m p e pae fe fe fe panie am am lt o S A MEM SUN 1 MEN _ y o SR f hp H H r H H H ml t d a v o N e N LI ME NE p Q 0 0 6 8 amp 8 P B 0 0 0 N o D o o 5 a O 2 2 AE MES S aO 6 5 5 0 2 2005 01 12 22 Figure 12 17 Block Commutat
285. ng the Instruction Pointer configuring OCDS and setting removing breakpoints executing single instruction step mode Note Detailed descriptions of the Monitor program functionality and the JTAG communication protocol are not provided in this document 14 2 2 2 Activate the MBC pin The MBC pin can be driven actively low by OCDS in reaction to debug events This functionality allows two alternative configurations asan action additional to the Monitor program start as the only OCDS response while temporarily for 4 SCLK clock cycles suspending the core activity this is the fastest reaction to the external world User s Manual 14 6 V 0 2 2005 01 OCDS V0 2 techno ogies On Chip Debug Support 14 3 Register Description From the programmer s point of view OCDS is represented by a total of 8 register addresses see Table 14 1 all located within the mapped SFR area Table 14 1 OCDS Directly Addressable Registers Register Address Register Full Name Short Name mapped MMCR Monitor Mode Control Register MMSR 2 Monitor Mode Status Register MMBPCR Monitor Mode Breakpoints Control Register MMICR Monitor Mode Interrupt Control Register MMCR2 Monitor Mode Control Register 2 MMDR 5 Monitor Mode Data Register HWBPSR F6 Hardware Breakpoints Select Register HWBPDR F7 Hardware Breakpoints Data Register Additionally there are 8 Hard
286. nge line is connected to both the MTSR and MRST pins of each device the shift clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to one data exchange line serial data may be moved between arbitrary stations As in full duplex mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enable its transmit pin driver the non transmitting devices use open drain output and send only ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By this method any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data Master Device 1 Device 2 Slave Shift Register Transmit Transmit Receive Device Line Figure 10 12 SSC Half Duplex Configuration User s Manual 10 24 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces 10 3 1 4 Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer TB is empty and ready to be loaded with the next transmit data If TB has been reloaded by the time the current transmission is f
287. nized a 12 event The events include e T12 compare event on channel 0 e T12 compare event on channel 1 e T12 compare event on channel 2 any 12 compare event on channel 0 1 or 2 a period match of T12 e azero match of T12 while counting up any edge of inputs CCPOSx The bit fields T13TEC and T13TED select the event that is used to start timer T13 This event sets bit T13R by hardware and T13 starts counting Combined with the single shot mode this can be used to generate a programmable delay after a T12 event compare match while 4 counting up a 3 2 13 CCUG T13 sync Figure 12 9 Synchronization of T13 to T12 Figure 12 9 shows the synchronization of T13 to a T12 event The selected event in this example is a compare match compare value 2 while counting up The clocks of T12 and T13 can be different use other prescaler factor but in this example T12CLK is shown as equal to T13CLK for the sake of simplicity 12 1 3 Modulation Control The modulation control part combines the different modulation sources CC6x T12 o and COUT6x T12 oare the output signals that are configured with CC6xPS COUT6xPS MOD T13 o is the output signal after T13 Inverted Modulation T131M Each modulation source can be individually enabled per output line Furthermore the User s Manual 12 13 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 tra
288. noise filter can be implemented to suppress spikes on the Hall inputs In case of a Hall event the DTCO is reloaded and it starts counting and generates a delay between the detected event and the sampling point After the counter value of 1 is reached the CCPOSx inputs are sampled without noise and spikes and are compared to the current Hall pattern CURH and to the expected Hall pattern EXPH If the sampled pattern equals to the current pattern it means that the edge on CCPOSx was due to a noise spike and no action will be triggered implicit noise filter by delay If the sampled pattern equals to the next expected pattern the edge on CCPOSx was a correct Hall event and the bit CHE is set which causes an interrupt If it is required that the multi channel mode and the Hall pattern comparison work independently of timer T12 the delay generation by DTCO can be bypassed In this case timer T12 can be used for other purposes Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields The hall compare action can also be triggered by software by writing a 1 to bit SWHC The triggering sources for the sampling by hardware include e Any edge at one of the inputs CCPOSx x 0 2 e AT13 compare match e A T13 period match e A T12 period match while counting up e A T12 one match while counting down e T12 compare match of channel 0 whil
289. nput Select Register 2 Type r rw CCU6_T12L Reset 00 Bit Field T12CVL Timer T12 Counter Register Low Type rwh User s Manual 3 23 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 7 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 0 6 12 Reset 004 Bit Field T12CVH Timer T12 Counter Register High Type rwh FC CCU6 T13L Reset 00 Bit Field T13CVL Timer T13 Counter Register Low Type rwh FDy CCU6_T13H Reset 004 Bit Field T13CVH Timer T13 Counter Register High Type rwh FE CCU6 CMPSTATL Reset 00 Bit Field 0 CC63 CCPO CCPO CCPO CC62 CC61 CC60 Compare State Register Low ST S2 51 50 5 ST ST Type r rh rh rh rh rh rh rh FFy CCU6_CMPSTATH Reset 00 4 Bit Field COUT COUT CC62 COUT CC61 COUT CC60 Compare State Register High 63PS 62PS PS 61PS PS 60PS PS Type rwh rwh rwh rwh rwh rwh rwh rwh 3 3 5 8 SSC Registers The SSC SFRs can be accessed in the standard memory area RMAP 0 Table 3 8 SSC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 9 SSC PISEL Reset 00 BitField 0 CIS SIS MIS Port Input Select Register Type r rw rw rw SSC CONL Res
290. ns of Hardware Breakpoints Page 14 5 Breakpoints on IRAM Address These breakpoints are generated when a break address is matched with the address from the Internal Data Memory IRAM to which location an instruction performs read or write access The IRAM breakpoints are of the Break After Make type the proper debug action is taken immediately after the operation to the breakpoint address is already performed The OCDS in XC866 supports only range breakpoints on IRAM address User s Manual 14 4 V 0 2 2005 01 OCDS V0 2 Cnfineon XC866 techno ogies On Chip Debug Support When the Internal Data Memory is RAM the OCDS differentiates between a breakpoint on read and a breakpoint on write operation to this IRAM Configurations of Hardware Breakpoints The OCDS in XC866 allows the setting of up to 4 hardware breakpoints labeled HWBPx x 0 3 16 bit values in various configurations as follows HWBPO HWBP1 two equal breakpoints on Instruction Address HWBPO and Instruction Address HWBP 1 or one range breakpoint on HWBPO Instruction Address HWBP1 HWBP2 one equal breakpoint on Instruction Address HWBP2 or one range breakpoint on HWBP2L IRAM Read Address HWBP2H HWBP3 one equal breakpoint on Instruction Address HWBP3 or one range breakpoint HWBP3L lt IRAM Write Address lt HWBP3H In XC866 the Program Memory address is 16 bit wide while the I
291. ns of the module The passive state level is the value that is driven by the port pin during the passive state of the output During the active state the corresponding output pin drives the active state level which is the inverted passive state level The passive state level permits the adaptation of the driven output levels to the driver polarity inverted or not inverted of the connected power stage PSLR Passive State Level Register Reset Value 00 7 6 5 4 3 2 1 0 PSL 63 0 PSL rwh r rwh Field Bits Type Description PSL 5 0 rwh Compare Outputs Passive State Level The bits of this bit field define the passive level driven by the module outputs during the passive state The bit positions are Passive level for output CC60 Bit 1 Passive level for output COUT60 Bit2 Passive level for output CC61 Bit 3 Passive level for output COUT61 Bit4 Passive level for output CC62 Bit5 Passive level for output 62 The value of each bit position is defined as 0 The passive level is O 1 The passive level is 1 PSL63 7 rwh Passive State Level of Output COUT63 This bit field defines the passive level of the output pin COUT63 0 The passive level is 0 1 The passive level is 1 0 6 r Reserved Returns 0 if read should be written with 0 1 Bit field PSL has a shadow register to allow for updates without undesired pulses on the output lines The bit
292. nt can be combined with several conditions which are necessary to implement noise filtering correct Hall event and to synchronize the next multi channel state to the modulation sources avoiding spikes on the output lines This compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back EMF technique is used instead of Hall sensors The compare value in channel 2 can be used as a time out trigger interrupt indicating that the motor s destination speed is far below the desired value which can be caused by an abnormal load change In this mode the modulation of T12 must be disabled T12MODENXx 0 CC60 capture CCPOSO CCPOS1 CCPOS2 COUT6y Figure 12 15 Timer T12 Brushless DC Mode all MSEL6x 1000p User s Manual 12 20 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Table 12 1 lists an example of block commutation in BLDC motor control If the input signal combination CCPOSO CCPOS2 changes its state the outputs CC6x and COUTSx are set to their new states Figure 12 16 shows the block commutation in rotate left mode and Figure 12 17 shows the block commutation in rotate right mode These figures are derived directly from Table 12 1 Table 12 1 Block Commutation Control Table Mode CCPOSO CC60 CC62 COUT60
293. nternal Data Memory addresses both for Read and Write are 8 bit wide This is why the complete HWBP2 HWBP3 values are used to generate IP breakpoints while the low and high bytes HWBPxL and HWBPxH x 2 3 are used separately to generate IRAM breakpoints Setting both the values to the same address for a range breakpoint leads to generation of an equal breakpoint 14 2 1 2 Software Breakpoints These breakpoints use the XC800 specific not 8051 standard TRAP instruction decoded by the core while at the same time the TRAP EN bit within the Extended Operation EO register is set to 1 Upon fetching a TRAP instruction a Break Before Make breakpoint is generated and the relevant Break Action is taken The software breakpoints are in fact similar in behavior to the equal breakpoints on Instruction address except that they are raised by a program code instead of specialized compare logic An unlimited number of software breakpoints can be set by replacing the original instruction opcodes in the user program However this is possible only at addresses where a writable memory RAM Flash is implemented Note In order to continue user program execution after the debug event an external Debugger must restore the original opcode at the address of the current software breakpoint User s Manual 14 5 V 0 2 2005 01 OCDS V0 2 techno ogies Debugging 14 2 1 3 External Breaks These debug events are of the Break No
294. nversion results Businterface to the device internal data bus for controlling the interrupts and register accesses The block diagram of the ADC module is shown in Figure 13 1 The analog input channel x x 0 7 is available at port pin P2 x ANx analog part digital part AD converter conversion control analog input O data result handling analog input 7 analog Clock digital clock f fine Figure 13 1 Overview of ADC Building Blocks User s Manual 13 2 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter 13 2 Clocking Scheme common module clock generates the various clock signals used by the analog and digital parts of the ADC module e fapca is input clock for the analog part is internal clock for the analog part defines the time base for conversion length and the sample time This clock is generated internally in the analog part based on the input clock fapca to generate a correct duty cycle for the analog components fapcp is input clock for the digital part This clock is used for the arbiter defines the duration of an arbitration round and other digital control structures e g registers and the interrupt generation The internal clock for the analog part fApc is limited to a maximum frequency of 10 MHz Therefore the ADC clock prescaler must be programmed to a
295. o the LIN baud rate for data transmission and reception 10 2 1 LIN Protocol LIN is a holistic communication concept for local interconnected networks in vehicles The communication is based on the SCI UART data format a single master multiple slave concept a clock synchronization for nodes without stabilized time base An attractive feature of LIN is self synchronization of the slave nodes without a crystal or ceramic resonator which significantly reduces the cost of hardware platform Hence the baud rate must be calculated and returned with every message frame The structure of a LIN frame is shown in Figure 10 4 The frame consists of the e header which comprises a Break 13 bit time low Synch Byte 55 4 and ID field response time data bytes according to UART protocol checksum Frame slot Response Header Response Synch Protected Data 1 Data2 DataN Checksum identifier Figure 10 4 Structure of LIN Frame Each byte field is transmitted as a serial byte as shown in Figure 10 5 The LSB of the data is sent first and the MSB is sent last The start bit is encoded as a bit with value zero dominant and the stop bit is encoded as a bit with value one recessive User s Manual 10 14 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces Byte field Figure 10 5 The Structure of Byte Field The bre
296. o the stack but it does not save the PSW and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in the Table 5 1 Program execution returns to the next instruction after calling the interrupt when the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the PC Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is important because it informs the processor that the program has left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system on the assumption that an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged 5 6 Interrupt Response Time If an interrupt is recognized its corresponding request flag is set at phase 2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two machine cycles Thus a minimum of three complete machine cycles will elapse from activation of the interrup
297. ode 1 16 bit capture mode 11 1 Timer 0 and Timer 1 Timer 0 and Timer 1 count up timers which are incremented every machine cycle or in terms of the input clock every 2 PCLK cycles Both have four modes of operation that are used in a variety of applications 11 1 1 Basic Timer Operations The operations of the two timers are controlled using the Special Function Registers SFRs TCON and TMOD To enable a timer i e allow the timer to run its control bit TCON TRx is set Note The x e g TCON TRx in this chapter denotes either or 1 Each timer consists of two 8 bit registers TLx low byte and THx high byte which default to 00 on reset Setting or clearing TCON TRx does not affect the timer registers Timer Overflow When a timer overflow occurs the timer overflow flag TCON TFx is set and an interrupt may be raised if the interrupt enable control bit IENO ETx is set The overflow flag is automatically cleared when the interrupt service routine is entered When Timer 0 operates in mode 3 the Timer 1 control bits TR1 TF1 and ET1 reserved for THO See Section 11 1 2 4 User s Manual 11 1 V 0 2 2005 01 Timers V 0 4 Cnfineon XC866 techno ogies Timers External Control In addition to pure software control the timers can be enabled or disabled through external port control When a timer is enabled TCON TRx 1 and is set the respective
298. ol Register Reset Value 00 7 6 5 4 3 2 1 0 TF2 EXF2 0 EXEN2 TR2 0 CP RL2 rwh rwh r rw rwh r rw Field Bits Type Description CP RL2 0 rw Capture Reload Select 0 Reload upon overflow or upon negative positive transition at pin 2 when 2 1 1 Capture Timer 2 data register contents on the negative positive transition at pin T2EX provided EXEN2 1 The negative or positive transition at pin T2EX is selected by bit EDGESEL TR2 2 rwh Timer 2 Start Stop Control 0 Stop Timer 2 1 Start Timer 2 EXEN2 3 rw Timer 2 External Enable Control 0 External events are disabled 1 External events are enabled in capture reload mode EXF2 6 rwh Timer 2 External Flag In capture reload mode this bit is set by hardware when a negative positive transition occurs at pin T2EX if bit EXEN2 1 An interrupt request to the core is generated unless bit DCEN 1 This bit must be cleared by software TF2 7 rwh Timer 2 Overflow Underflow Flag Set by a Timer 2 overflow underflow Must be cleared by software 0 1 5 4 r Reserved Returns 0 if read should be written with 0 User s Manual 11 19 V 0 2 2005 01 Timer V 0 4 Infineon technologies XC866 Timer Register RC2 is used for a 16 bit reload of the timer count upon overflow or a capture of current timer count depending on the mode selected RC2L Timer 2 Reload Capture Register Lo
299. om the peripheral clock according to the equation fr12 fccug 27 CH 000 fr42 7 fccue 001 ft12 2 010 fecue 4 011 fr42 fccug 8 100 fr42 1 6 101 fr42 32 110 fr42 fccug 64 111 fr42 1 28 12 3 rw Timer T12 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler for T12 0 The additional prescaler for T12 is disabled 1 The additional prescaler for T12 is enabled T12R 4 rh T12 Run Bit T12R starts and stops timer T12 It is set reset by software by setting bit T12RR or T12RS or it is reset by hardware according to the function defined by bit T12SSC 0 Timer T12 is stopped 1 Timer T12 is running User s Manual 12 48 V 0 2 2005 01 CCUG V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 Field Bits Type Description STE12 5 rh Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected Bit STE12 is cleared by hardware after the shadow transfer A 12 shadow transfer event is a period match while counting up or a one match while counting down 0 The shadow register transfer is disabled 1 The shadow register
300. onal Description This section describes the various power saving modes their operations and how they are entered and exited 8 1 1 Idle Mode The idle mode is used to reduce power consumption by stopping the core s clock In idle mode the oscillator continues to run but the core is stopped with its clock disabled Peripherals whose input clocks are not disabled are still functional The user should disable the Watchdog Timer WDT before the system enters the idle mode otherwise it will generate an internal reset when an overflow occurs and thus will disrupt the idle mode The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The port pins hold the logical state they had at the time the idle mode was activated Software requests idle mode by setting the bit PCON IDLE to 1 The system will return to active mode on occurrence of any of the following conditions The idle mode can be terminated by activating any enabled interrupt The CPU operation is resumed and the interrupt will be serviced Upon RETI instruction the core will return to execute the next instruction after the instruction which sets the IDLE bit to 1 An external hard reset signal RESET is asserted 8 1 2 Slow Down Mode The slow down mode is used to reduce power consumption by decreasing the internal clock in the device The slow
301. ont d Interrupt Source Request Flags SFR CCU6 Node 3 Interrupt See note INPL INPH Watchdog Timer NMI FNMIWDT NMISR PLL NMI FNMIPLL NMISR Flash Timer NMI FNMI NMISR FLASHTIMER OCDS NMI FNMIOCDS NMISR VDD NMI FNMIVDD NMISR VDDP NMI FNMIVDDP NMISR ECC NMI FNMIECC NMISR 1 Different CCU6 interrupts can be assigned to different CCUG interrupt nodes 3 0 which are selected via registers INPL INPH 5 5 Interrupt Handling The interrupt flags are sampled at phase 2 in each machine cycle The sampled flags are then polled during the following machine cycle If one of the flags was in a set condition at phase 2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions e An interrupt of equal or higher priority is already in progress The current polling cycle is not in the final cycle of the instruction in progress The instruction in progress is RETI or any write access to registers IENO IEN1 or IP IPH IP1 IP1H Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1
302. onversion of the requested channel will not start unless the valid flag of the targeted result register is cleared data is invalid The wait for read mode for a result register can be enabled by setting bit WFR see Section 13 7 8 User s Manual 13 15 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter 13 4 7 Result Generation 13 4 7 1 Overview The result generation of the ADC module consists of several parts Alimit checking unit comparing the conversion result to two selected boundary values BOUNDO and BOUND 1 A channel interrupt can be generated according to the limit check result Adata reduction filter accumulating the conversion results The accumulation is done by adding the new conversion result to the value stored in the selected result register Four result registers storing the conversion results The software can read the conversion result from the result registers The result register used to store the conversion result is selected individually for each input channel analog part conversion from channel result control result buffer boundary values result register 0 add sub result register 1 result register 3 result path control limit check control channel interrupt DRC data reduction control DRC event interrupt Figure 13 8 Result Path Refer to Section 13 7 8 for description of the result generation registers User s Manual 13 16 V 0 2 2005 01 AD
303. opcode of the next instruction while executing the current instruction Table 2 1 provides a reference for the number of clock cycles required by each instruction The first value applies to fetching operand s and opcode from fast program memory e g Boot ROM and XRAM without wait state The second value applies to fetching operand s and opcode from slow program memory e g Flash with one wait state inserted The instruction time for the standard 8051 processor is provided in the last column for performance comparison with the XC866 CPU Even with one wait state inserted for each byte of operand opcode fetched the XC866 CPU executes instructions faster than the standard 8051 processor by a factor of between two e g 2 byte 1 cycle instructions to six e g 1 byte 4 cycle instructions Table 2 1 CPU Instruction Timing Mnemonic Hex Code Bytes Number of fcc Cycles XC866 8051 no ws 1 ws ARITHMETIC ADD 28 2F 1 2 4 12 ADD AJir 25 2 2 6 12 ADD A Ri 26 27 1 2 4 12 ADD A data 24 2 2 6 12 ADDC 38 3F 1 2 4 12 ADDC 35 2 2 6 12 ADDC A Ri 36 37 1 2 4 12 ADDC A data 34 2 2 6 12 SUBB 98 9F 1 2 4 12 SUBB Air 95 2 2 6 12 SUBB A Ri 96 97 1 2 4 12 SUBB A data 94 2 2 6 12 INCA 04 1 2 4 12 INC Rn 08 1 2 4 12 User s Manual 2 10 V 0 2 2005 01 Processor Architecture V 0 3 Infineon technologies XC866
304. or IP IPH IP1 IP1H then at least one more instruction will be executed before any interrupt is vectored to this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at phase 2 of the previous machine cycle Note that if any interrupt flag is active but was not responded to for one of the conditions already mentioned or if the flag was no longer active at the time of removal of the blocking condition the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests Figure 5 6 shows the timing example for extended interrupts User s Manual 5 23 V 0 2 2005 01 Interrupt System V 0 5 techno ogies Interrupt System C P2 C P2 C1P2 C2P1 C2P2 XINTR SCR 1 XINTR ACK 1 v Interrupts sampled here Figure 5 6 Timing for Extended Interrupt The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases hardware also clears the flag that generated the interrupt while in other cases the flag must be cleared by the user s software The hardware generated LCALL pushes the contents of the Program Counter PC ont
305. ored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR Reserved Returns 0 if read should be written with 0 3 3 3 Bit Addressing SFRs that have addresses in the form of 1XXXX000g e g 80 88 90 FOH are bitaddressable The addresses of these bitaddressable SFRs appear in bold typeface in Table 3 1 to Table 3 9 User s Manual Memory Organization V 0 2 3 9 V 0 2 2005 01 Cnfineon XC866 techno ogies Memory Organization 3 3 4 System Control Registers The system control SFRs are used to control the overall system functionalities such as interrupts variable baud rate generation clock management bit protection scheme oscillator and PLL control The SFRs are located in the standard memory area RMAP 0 and organized into 2 pages The SCU PAGE register is located at B2 It contains the page value and page control information SCU_PAGE Page Register for System Control Reset Value 00 7 6 5 4 3 2 1 0 OP STNR 0 PAGE Ww r rw Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page When read the value indicates the currently active page
306. ouble buffered Figure 10 9 shows the block diagram of the SSC PCLK Baud rate Clock 4 SS_CLK Generator Control gt MS Shift Clock SSC Control Block Register CON Receive Int Request Eo Transmit Int Request Error Int Request Status Control TXD Master RN RXD Slave Register TXD Slave T RX D Master Transmit Buffer Receive Buffer Register TB Register RB Intemal Bus Figure 10 9 Synchronous Serial Channel SSC Block Diagram User s Manual 10 19 V 0 2 2005 01 Serial Interfaces V 0 3 _ Infineon XC866 techno ogies Serial Interfaces 10 3 1 General Operation 10 3 1 1 Operating Mode Selection The operating mode of the serial channel SSC is controlled by its control register CON This register has a double function During programming SSC disabled by CON EN 0 it provides access to a set of control bits During operation SSC enabled by CON EN 1 it provides access to a set of status flags The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control logic Transmission and reception of serial data are synchronized and take place at the same time i e the same number of transmitted bits is also received Transmit data is written into the Transmitter Buffer
307. over three machine cycles instruction time extended with one wait state inserted for opcode fetching from the Flash memory User s Manual 2 8 V 0 2 2005 01 Processor Architecture V 0 3 e Infineon technologies XC866 Processor Architecture Read next opcode without wait state 2 next instruction Read next opcode one wait state WAIT next instruction a 1 byte 1 cycle instruction e g INC A Read 2 byte Read next opcode without wait state without wait state C1P1 2 next instruction Read 2 byte __ Read next opcode one wait state one wait state b 2 byte 1 cycle instruction e g ADD A data Read next opcode without wait state C1P1 C2P2 next instruction __ Read next opcode one wait state b 1 byte 2 cycle instruction e g MOVX Figure 2 2 Instruction Timing User s Manual 2 9 V 0 2 2005 01 Processor Architecture V 0 3 Cnfineon XC866 techno ogies Processor Architecture Instructions are 1 2 or 3 bytes long as indicated in the Bytes column of Table 2 1 For the 866 the time taken for each instruction includes decoding executing the fetched opcode fetching the operand s for instructions gt 1 byte fetching the first byte opcode of the next instruction due to XC866 CPU pipeline Note The XC866 CPU fetches the
308. p functionality is taken into account to disable the modulation of the corresponding output line during the trap state if enabled CC6x T12 o COUT6x T12 o 0 passive state 1 7 active state to output pin CC6x COUT6x TRPENx 1 x for each T12 related output CCU6_mod_ctr Figure 12 10 Modulation Control of T12 related Outputs For each of the six T12 related output lines represented by x in the Figure 12 10 e T12MODENXx enables the modulation by a PWM pattern generated by timer T12 e T13MODENXx enables the modulation by PWM pattern generated by timer T13 MCMPx chooses the multi channel patterns e TRPENx enables the trap functionality PSLx defines the output level that is driven while the output is in the passive state As shown in Figure 12 11 the modulation control part for the T13 related output COUT63 combines the T13 output signal COUT63 T13 o is the output signal that is configured by COUT63PS and the enable bit ECT130 with the trap functionality The output level of the passive state is selected by bit PSL63 User s Manual 12 14 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 0 passive state 1 active state ECT130 COUT63 T13 o TRPEN13 to output pin COUT63 CCUG T13 mod ctr Figure 12 11 Modulation Control of the T13 related Output COUT63 Figure 12 12 shows a modulation control example for CC60 and
309. pe Description CHINFx X rh Interrupt Flag for Channel x x 0 7 This bit monitors the status of the channel interrupt x 0 A channel interrupt for channel x has not occurred 1 A channel interrupt for channel x has occurred Writing a 1 to a bit position in register CHINCR clears the corresponding channel interrupt flag in register CHINFR If a hardware event triggers the setting of a bit CHINFx and CHINCx 1 the bit CHINFx is cleared software overrules hardware CHINCR Channel Interrupt Clear Register Reset Value 00 7 6 5 4 3 2 1 0 CHINC7 6 CHINC5 4 CHINC3 CHINC2 CHINC1 CHINCO WwW Ww Ww WwW Ww Field Bits Type Description CHINCx X Clear Interrupt Flag for Channel x x 20 7 0 No action 1 Bit CHINFR x is reset User s Manual 13 52 V 0 2 2005 01 ADC V 0 3 _ Infineon technologies XC866 Analog to Digital Converter Writing a 1 to a bit position in register CHINSR sets the corresponding channel interrupt flag in register CHINFR and generates an interrupt pulse CHINSR Channel Interrupt Set Register Reset Value 00 7 6 5 4 3 2 1 0 CHINS7 CHINS6 CHINS5 CHINS4 CHINS3 CHINS2 CHINS1 CHINSO WwW WwW Field Bits Type Description CHINSx X Set Interrupt Flag for Channel x x 20 7 0 No action 1 Bit CHINFR x is set and an in
310. pe rw rw rw rw 8A TLO Reset 00 Bit Field VAL Timer 0 Register Low Type rwh 8By TL1 Reset 00 Bit Field VAL Timer 1 Register Low Type rwh 8Cy THO Reset 00 Bit Field VAL Timer 0 Register High Type rwh 8 1 Reset 00 Bit Field VAL Timer 1 Register High Type rwh 984 SCON Reset 00 Bit Field SMO SM1 SM2 REN TB8 RB8 TI RI Serial Channel Control Register Type rw rw rw rw rw rwh rwh rwh 99 SBUF Reset 00 Bit Field VAL Serial Data Buffer Register Type rwh A2u EO Reset 00 Bit Field 0 TRAP 0 DPSEL Extended Operation Register EN 0 Type r rw r rw 8 IENO Reset 00 Bit Field EA 0 ET2 ES ET1 EX1 ETO EXO Interrupt Enable Register 0 Type rw rw rw rw rw rw rw 8 Reset 00 Bit Field 0 PT2 PS PT1 PX1 PTO PXO Interrupt Priority Register Type r rw rw rw rw rw rw B94 IPH Reset 00 Bit Field 0 PT2H PSH PT1H PX1H PTOH PXOH Interrupt Priority Register High Type r rw rw rw rw rw rw PSW Reset 00 Bit Field CY AC FO RS1 RSO OV F1 Program Status Word Register Type rw rwh rwh rw rw rwh rwh rh User s Manual 3 13 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 1 CPU Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 E0 ACC Reset 00 Bit Field ACC ACC6 ACC5 4 ACC3 ACC2 ACC1 ACCO Accumulator Register Type rw rw rw rw rw rw
311. pt occurs if a new data frame is completely Error received and the last data in the receive buffer was not read Phase Error EIR This interrupt is generated if the incoming data changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK Baud Rate EIR This interrupt is generated when the incoming clock signal Error Slave deviates from the programmed baud rate by more than mode only 100 Transmit EIR This interrupt is generated when TB was not updated since Error Slave the last transfer if a transfer is initiated by a master mode only User s Manual 10 30 V 0 2 2005 01 Serial Interfaces V 0 3 Infineon technologies XC866 10 3 3 Register Mapping Serial Interfaces The addresses of the kernel SFRs are listed in Table 10 5 Table 10 5 SFR Address List Address Register 9 PISEL AAH CONL ABy CONH ACy TBL RBL AEy BRL AFy BRH User s Manual 10 31 V 0 2 2005 01 Serial Interfaces V 0 3 _ 866 techno ogies Serial Interfaces 10 3 4 Register Description All SSC register names described in this section will be referenced in other chapters of this document with the module name prefix SSC_ e g SSC_PISEL 10 3 4 1 Port Input Select Register The PISEL register controls the receiver input selection of the SSC module
312. pture Compare Match Rising Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit ICC60R in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC60R in register IS occurs The interrupt line that will be activated is selected by bit field INPCC60 ENCC6OF 1 rw Capture Compare Match Falling Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit ICC60F in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC6OF in register IS occurs The interrupt line that will be activated is selected by bit field INPCC60 ENCC61R 2 rw Capture Compare Match Rising Edge Interrupt Enable for Channel 1 0 No interrupt will be generated if the set condition for bit ICC61R in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC61R in register IS occurs The interrupt line that will be activated is selected by bit field INPCC61 ENCC61F 3 rw Capture Compare Match Falling Edge Interrupt Enable for Channel 1 0 No interrupt will be generated if the set condition for bit ICC61F in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC61F in register IS occurs The interrupt line that will be activated is selected by bit field INPCC61 User s Manual 12 84 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Captu
313. quest signals go directly to the XC800 Core and their interrupt status is maintained by the core Two interrupt flags TFO and TF1 in the TCON register are set whenever Timer O or Timer 1 respectively overflows TFO and TF1 are automatically cleared by hardware on entry to the corresponding interrupt service routine User s Manual 5 1 V 0 2 2005 01 Interrupt System V 0 5 techno ogies Interrupt System The UART interrupt source comprises the logical OR of the two serial interface interrupts The interrupt flags RI and in register SCON are set automatically upon receipt or transmission of a data frame These two bits must be cleared by software 5 2 2 External Interrupts Seven external interrupts EXT_INT 6 0 are driven into the XC866 from the ports External interrupts can be positive negative or double edge triggered Registers EXICONO and 1 specify the active edge for the triggering of the external interrupt Among the external interrupts external interrupt 0 and external interrupt 1 can also be selected without edge detection The interrupt request signal caused with without the edge triggered to the core can further be programmed to either level activated or negative transition activated by setting or clearing bit ITx x 0 or 1 respectively in the TCON register If the external interrupt is positive negative edge triggered the external source must hold the request pin low high for at lea
314. r Architecture 2 2 5 Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU PSW Program Status Word Register Reset Value 00 7 6 5 4 3 2 1 0 CY AC FO RS1 RSO OV F1 P rw rwh rwh rw rw rwh rwh rh Field Bits Description P 0 rh Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity 1 1 rwh General Purpose Flag OV 2 rwh Overflow Flag Used by arithmetic instructions RSO 3 rw Register Bank Select RS1 4 These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 00 07 0 1 Bank 1 selected data address 08 1 0 Bank 2 selected data address 104 17 1 1 Bank selected data address 18 1 FO 5 rwh General Purpose Flag AC 6 rwh Auxiliary Carry Flag Used by instructions that execute BCD operations CY 7 rw Carry Flag Used by arithmetic instructions User s Manual 2 5 V 0 2 2005 01 Processor Architecture V 0 3 _ Infineon XC866 techno ogies Processor Architecture 2 2 6 Extended Operation Register EO The instruction set includes an additional instruction MOVC DPTR A which allows program memory to be written This instruction may be used to download code into the program
315. r High 7 6 5 Reset Value 004 4 3 2 1 0 STR IDLE EN WHE EN CHE EN EN EN 0 T13 T13 rw rw User s Manual CCU6 V 0 4 rw r rw rw rw 12 85 V 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 Field Bits Type Description ENT13CM 0 rw Enable Interrupt for T13 Compare Match 0 No interrupt will be generated if the set condition for bit T13CM in register IS occurs 1 An interrupt will be generated if the set condition for bit T13CM in register IS occurs The interrupt line that will be activated is selected by bit field INPT 13 ENT13PM 1 rw Enable Interrupt for T13 Period Match 0 No interrupt will be generated if the set condition for bit T13PM in register IS occurs 1 An interrupt will be generated if the set condition for bit T13PM in register IS occurs The interrupt line that will be activated is selected by bit field INPT 13 ENTRPF 2 rw Enable Interrupt for Trap Flag 0 No interrupt will be generated if the set condition for bit TRPF in register IS occurs 1 An interrupt will be generated if the set condition for bit TRPF in register IS occurs The interrupt line that will be activated is selected by bit field INPERR ENCHE 4 rw Enable Interrupt for Correct Hall Event 0 No interrupt will be generated if the set condition for bit CHE in register IS occurs 1 An interrupt will be generated if the set condit
316. r SEL Type r rw rw rw rw C24 T2 RC2L Reset 00 Bit Field RC2 7 0 Timer 2 Reload Capture Register Low Type rwh 2 2 Reset 00 Bit Field RC2 15 8 Timer 2 Reload Capture Register High Type rwh T2 T2L Reset 00 Bit Field THL2 7 0 Timer 2 Register Low Type rwh 2 2 Reset 004 Bit Field THL2 15 8 Timer 2 Register High Type rwh 3 3 5 7 CCUG Registers The CCU6 SFRs can be accessed in the standard memory area RMAP 0 Table 3 7 CCU6 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 0 CCU6 PAGE Reset 00 Bit Field OP STNR 0 PAGE Page Register for CCUG Type w w r rw RMAP 0 Page 0 0 6 CC63SRL Reset 00 Bit Field CC63SL Capture Compare Shadow Register for Channel CC63 Low Type rw User s Manual 3 20 V 0 2 2005 01 Memory Organization V 0 2 e Infineon technologies XC866 Memory Organization Table 3 7 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 9By CCU6_CC63SRH Reset 00 Bit Field CC63SH Capture Compare Shadow Register for Channel CC63 High Type rw 9 CCU6_TCTR4L Reset 00 Bit Field T12 T12 0 DTRES T12 T12RS T12RR Timer Control Register
317. r T12 Counter Register High Page 12 35 T12PRL Timer T12 Period Register Low Page 12 36 T12PRH Timer T12 Period Register High Page 12 36 CC6xRL Capture Compare Register for Channel CC6x Page 12 37 Low CC6xRH Capture Compare Register for Channel CC6x Page 12 37 High CC6xSRL Capture Compare Shadow Register for Channel Page 12 38 CC6x Low CC6xSRH Capture Compare Shadow Register for Channel Page 12 38 CC6x High T12DTCL Dead Time Control Register for Timer T12 Low Page 12 39 T12DTCH Dead Time Control Register for Timer T12 High Page 12 39 T13 Registers T13L Timer T13 Counter Register Low Page 12 41 T13H Timer T13 Counter Register High Page 12 41 T13PRL Timer T13 Period Register Low Page 12 42 T13PRH Timer T13 Period Register High Page 12 42 CC63RL Capture Compare Register for Channel CC63 Page 12 43 Low CC63RH Capture Compare Register for Channel CC63 Page 12 44 High User s Manual 12 29 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Table 12 4 CCU6 Module Registers cont d Register Register Full Name Description Short Name see CC63SRL Capture Compare Shadow Register for Channel Page 12 44 CC63 Low CC63SRH Capture Compare Shadow Register for Channel Page 12 44 CC63 High CCU6 Control Registers CMPSTATL Compare State Register Low Page 12 45 CMPSTATH Compare State Register High P
318. r Timer T12 High Type rh rh rh r rw rw rw CCU6 TCTROL Reset 00 Bit Field CDIR STE12 T12R T12 T12CLK Timer Control Register 0 Low PRE Type rw rh rh rh rw rw A7y CCU6_TCTROH Reset 004 Bit Field 0 5 13 T13R T13 T13CLK Timer Control Register 0 High PRE Type r rh rh rw rw FAy CCU6_CC60RL Reset 00 Bit Field CC60VL Capture Compare Register for Channel CC60 Low Type rh CCU6 CC60RH Reset 00 Bit Field CC60VH Capture Compare Register for Channel CC60 High Type rh FC CCU6_CC61RL Reset 00 Bit Field CC61VL Capture Compare Register for Channel CC61 Low Type rh CCU6 CC61RH Reset 00 Bit Field CC61VH Capture Compare Register for Channel CC61 High Type rh FEy CCU6_CC62RL Reset 00 Bit Field CC62VL Capture Compare Register for Channel CC62 Low Type rh FFy CCU6_CC62RH Reset 00 Bit Field CC62VH Capture Compare Register for Channel CC62 High Type rh RMAP 0 Page 2 9 CCU6 T12MSELL Reset 00 Bit Field MSEL61 MSEL60 T12 Capture Compare Mode Select Register Low Type rw rw 9By CCU6_T12MSELH Reset 004 Bit Field DBYP HSYNC MSEL62 T12 Capture Compare Mode Select Register High Type rw rw rw 9 CCU6_IENL Reset 00 Bit Field 12 12 Capture Compare Interrupt Enable PM OM 62F 62R 61F 61R 60F 60R Register Low Type rw rw rw rw rw rw rw rw 9Du CCU6_IENH Reset 00 Bit Field ENSTR EN EN EN 0 1
319. rces supported and additional status registers for detecting and determining the interrupt source 5 1 Non maskable Interrupt The Non Maskable Interrupt NMI is similar to regular interrupts except it has the highest priority over other regular interrupts when addressing important system events In the XC866 any one of the following seven events can generate an NMI WDT prewarning has occurred The PLL has lost the lock to the external crystal e Flash Timer has overflowed JTAG receiving or user interrupt is requested in monitor mode e VDD is below the prewarning voltage level 2 3 V VDDP is below the prewarning voltage level 4 0 V if the external power supply is 5 0 V e Flash ECC error has occurred The NMISR register is used to hold the NMI request flags for these events Corresponding bits in the NMICON register determine whether the NMI requests will be accepted or ignored When any enabled NMI request is serviced the software routine may clear the NMI request flags in the NMISR register 5 2 Maskable Interrupts All regular interrupts are called maskable interrupts A maskable interrupt can be masked or temporarily ignored by the processor while it completes its task These interrupts can be classified into three types internal interrupts external interrupts and extended interrupts 5 2 1 Internal Interrupts There are three internal interrupts that proceed from Timer 0 Timer 1 and UART These interrupt re
320. re 12 1 The timer T12 can function in capture and or compare mode for its three channels The timer T13 can work in compare mode only The multi channel control unit generates output patterns which can be modulated by T12 and or T13 The modulation sources can be selected and combined for the signal modulation Timer T12 Features Three capture compare channels each channel can be used either as a capture or as a compare channel Supports generation of a three phase PWM six outputs individual signals for highside and lowside switches 16 bit resolution maximum count frequency peripheral clock frequency Dead time control for each channel to avoid short circuits in the power stage Concurrent update of the required T12 13 registers Generation of center aligned and edge aligned PWM Supports single shot mode Supports many interrupt request sources Hysteresis like control mode Timer T13 Features One independent compare channel with one output 16 bit resolution maximum count frequency peripheral clock frequency Can be synchronized to T12 Interrupt generation at period match and compare match Supports single shot mode Additional Features Implements block commutation for Brushless DC drives Position detection via Hall sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling e Fast emergency stop without CPU load via external signal CTR
321. re Compare Unit 6 Field Bits Type Description ENCC62R 4 Capture Compare Match Rising Edge Interrupt Enable for Channel 2 0 1 No interrupt will be generated if the set condition for bit ICC62R in register IS occurs An interrupt will be generated if the set condition for bit ICC62R in register IS occurs The interrupt line that will be activated is selected by bit field INPCC62 ENCC62F 5 Capture Compare Match Falling Edge Interrupt Enable for Channel 2 0 1 No interrupt will be generated if the set condition for bit ICC62F in register IS occurs An interrupt will be generated if the set condition for bit ICC62F in register IS occurs The interrupt line that will be activated is selected by bit field INPCC62 ENT120M 6 Enable Interrupt for T12 One Match 0 1 No interrupt will be generated if the set condition for bit T12OM in register IS occurs An interrupt will be generated if the set condition for bit T12OM in register IS occurs The interrupt line that will be activated is selected by bit field INPT12 ENT12PM 7 Enable Interrupt for T12 Period Match 0 1 No interrupt will be generated if the set condition for bit T12PM in register IS occurs An interrupt will be generated if the set condition for bit T12PM in register IS occurs The interrupt line that will be activated is selected by bit field INPT12 IENH Capture Compare Interrupt Enable Registe
322. register TB and is moved to the shift register as soon as this is empty An SSC master CON MS 1 immediately begins transmitting while an SSC slave CON MS 0 will wait for an active shift clock When the transfer starts the busy flag CON BSY is set and the Transmit Interrupt Request line TIR will be activated to indicate that register TB may be reloaded again When the programmed number of bits 2 8 have been transferred the contents of the shift register are moved to the Receiver Buffer register RB and the Receive Interrupt Request line RIR will be activated If no further transfer is to take place TB is empty CON BSY will be cleared at the same time Software should not modify CON BSY as this flag is hardware controlled Note Only one SSC can be the master at a given time The transfer of serial data bits can be programmed in a number of ways The data width can be specified from 2 to 8 bits e A transfer may start with either the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading edge or the trailing edge of the shift clock signal The baud rate may be set within a certain range depending on the module clock The shift clock be generated MS CLK or can be received 55 CLK These features allow the SSC to be adapted to a wide range of applications requiring serial data transfer The Data Width Selection supports the transfer of frames of any dat
323. rogram to run from one bank while programming or erasing another bank In System Programming ISP is available through the Boot ROM based BootStrap Loader BSL enabling convenient programming and erasing of the embedded Flash via an external host e g personal computer Other key features of the XC866 include a Capture Compare Unit 6 CCU6 for the generation of pulse width modulated signal with special modes for motor control and a 10 bit Analog to Digital Converter ADC with extended functionalities like autoscan and result accumulation for anti aliasing filtering or for averaging Local Interconnect Network LIN applications are also supported through extended UART features and the provision of LIN low level drivers for most devices For low power applications various power saving modes are available for selection by the user Control of the numerous on chip peripheral functionalities is achieved by extending the Special Function Register SFR address range with an intelligent paging mechanism optimized for interrupt handling Figure 1 1 shows the functional units of the XC866 Flash or ROM L o 8K 16K x 8 On Chip Debug Support 2 2 6 bit Digital I O Boot ROM Capture Compare Unit TM 8Kx8 46 bit Port 1 5 bit Digital XC800 Core XRAM Compare Unit mS 512x8 46 bit Port 2 2 1 8 bit Digital Analog Input RAM Timer 0 Timer 1 Timer2 Watchdog ADE 256x8 16 bit 16bit 16 bit Timer 1001 gt
324. rol Register 2 Low SSC SSC Type r rw rw rw rw CCU6 TCTR2H Reset 004 Bit Field 0 T13RSEL T12RSEL Timer Control Register 2 High Type rw rw FCy CCU6_MODCTRL Reset 00 Bit Field MC 0 T12MODEN Modulation Control Register Low MEN Type rw r rw CCU6 MODCTRH Reset 00 Bit Field ECT13 0 T13MODEN Modulation Control Register High rw r rw FEy CCU6_TRPCTRL Reset 00 Bit Field 0 2 Trap Control Register Low Type rw rw rw FFy CCU6_TRPCTRH Reset 00 Bit Field TRPPE TRPEN TRPEN Trap Control Register High N 13 Type rw rw rw RMAP 0 Page 3 CCU6 MCMOUTL Reset 00 Bit Field 0 R Multi Channel Mode Output Register Low Type r rh rh 9By CCU6_MCMOUTH Reset 00 Bit Field 0 CURH EXPH Multi Channel Mode Output Register High Type r rh rh 9Cu CCU6_ISL Reset 00 Bit Field T12PM T12OM ICC62F 62 ICC61F ICC61 ICC60F ICC60 Capture Compare Interrupt Status R R R Register Low Type rh rh rh rh rh rh rh rh 9Du CCU6_ISH Reset 00 Bit Field STR IDLE WHE TRPS 1 13 Capture Compare Interrupt Status Register High Type rh rh rh rh rh rh rh rh 9Ey CCU6_PISELOL Reset 00 Bit Field ISTRP ISCC62 ISCC61 ISCC60 Port Input Select Register 0 Low Type rw rw rw rw CCU6_PISELOH Reset 00 Bit Field IST12HR ISPOS2 ISPOS1 ISPOSO Port Input Select Register 0 High Type rw rw rw rw A4y CCU6_PISEL2 Reset 00 Bit Field 0 IST13HR Port I
325. ructions Data may also be saved on or retrieved from the stack using PUSH and POP instructions respectively Instructions that use the stack automatically pre increment or post decrement the stack pointer so that the stack pointer always points to the last byte written to the stack i e the top of the stack On reset the SP is reset to 07 This causes the stack to begin at a location 084 above register bank zero The SP be read or written under software control 2 2 2 Data Pointer DPTR The Data Pointer DPTR is stored in registers DPL Data Pointer Low byte and DPH Data Pointer High byte to form 16 bit addresses for External Data Memory accesses A DPTR MOVX DPTR A for program byte moves MOVC A A DPTR and for indirect program jumps JMP A DPTR Two true 16 bit operations are allowed on the Data Pointer load immediate MOV DPTR data and increment INC DPTR 2 2 3 Accumulator ACC This register provides one of the operands for most ALU operations While ACC is the symbol for the accumulator register the mnemonics for accumulator specific instructions refer to the accumulator simply as 2 2 4 B Register The B register is used during multiply and divide operations to provide the second operand For other instructions it can be treated as another scratch pad register User s Manual 2 4 V 0 2 2005 01 Processor Architecture V 0 3 Cnfineon XC866 techno ogies Processo
326. rupt controller continue to run using a half speed clock In power down mode the clock to the entire CPU is stopped PCON Power Control Register Reset Value 00 7 6 5 4 3 2 1 0 SMOD 0 GF1 GFO 0 IDLE nw r rw rw r rw The functions of the shaded bits are not described here Field Bits Description IDLE 0 rw Idle Mode Enable 0 Do not enter idle mode 1 Enter idle mode 2 nw General Purpose Flag Bit 0 GF1 rw General Purpose Flag Bit 1 User s Manual 2 7 V 0 2 2005 01 Processor Architecture V 0 3 techno ogies Processor Architecture 2 3 Instruction Timing For memory access without wait state a CPU machine cycle comprises two input clock periods referred to as Phase 1 P1 and Phase 2 P2 that correspond to two different CPU states A CPU state within an instruction is denoted by reference to the machine cycle and state number e g C2P1 is the first clock period within machine cycle 2 Memory accesses take place during one or both phases of the machine cycle SFR writes only occur at the end of P2 An instruction takes one two or four machine cycles to execute Registers are generally updated and the next opcode read at the end of P2 of the last machine cycle for the instruction With each access to the Flash memory instruction execution times are extended by one machine cycle one wait state starting from either P1 or P2 Figure 2 2 shows the
327. rupt request is active TIR rwh Transmit Interrupt Request Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt request is not active 1 Interrupt request is active RIR rwh Receive Interrupt Request Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt request is not active 1 Interrupt request is active ADCSRCO rwh Interrupt Request 0 Flag for ADC This bit is set by hardware and can only be cleared by software 0 Interrupt request is not active 1 Interrupt request is active ADCSRC1 rwh Interrupt Request 1 Flag for ADC This bit is set by hardware and can only be cleared by software 0 Interrupt request is not active 1 Interrupt request is active 7 5 Reserved Returns 0 if read should be written with 0 User s Manual Interrupt System V 0 5 5 15 V 0 2 2005 01 _ Infineon technologies XC866 Interrupt System TCON Timer Control Register Reset Value 00 7 6 5 4 3 2 1 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO rwh rw rwh rw rwh rw rwh rw The functions of the shaded bits are not described here Field Bits Type Description ITO rw External Interrupt 0 Level Edge Trigger Control Flag 0 Low level triggered external interrupt 0 is selected 1 Falling edge triggered external interrupt 0 is selected IE
328. s Call the Monitor Program Activate the MBC pin The 866 debug operation is based on close interaction between the OCDS hardware and a specialized software called the Monitor program 14 2 1 Debug Events The OCDS system recognizes a number of different debug events which are also called breakpoints or simply breaks Depending on how the break events are processed in time they can be classified into three types of breakpoints Break Before Make The break happens just before the break instruction i e the instruction causing the break is executed Therefore the break instruction itself will be the next instruction from the user program flow but executed only after the relevant debug action has been taken Break After Make The break happens immediately after the break instruction causing it has been executed Therefore the break instruction itself has already been executed when the relevant debug action is taken e Break Now The events of this type are asynchronous to the code execution inside the XC866 and there is no instruction causing the debug event in this case The debug action is performed by OCDS as soon as possible once the debug event is raised User s Manual 14 3 V 0 2 2005 01 OCDS V0 2 Cnfineon XC866 techno ogies Debugging 14 2 1 1 Hardware Breakpoints Hardware breakpoints are generated by observing certain address buses within the XC866 system The bus relevant to the hardw
329. s are updated with the T12 shadow transfer A read action targets the actually used values while a write action targets the shadow bits User s Manual 12 63 V 0 2 2005 01 CCU6 V 0 4 866 technologies Capture Compare Unit 6 2 Bit PSL63 has a shadow register to allow for updates without undesired pulses on the output line The bit is updated with the T13 shadow transfer A read action targets the actually used values while a write action targets the shadow bits User s Manual 12 64 V 0 2 2005 01 CCU6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 3 5 2 Multi Channel Control Register MCMOUTS contains bits that control the output states for multi channel mode Furthermore the appropriate signals for the block commutation by Hall sensors can be selected This register is a shadow register that can be written for register MCMOUT which indicates the currently active signals MCMOUTSL Multi Channel Mode Output Shadow Register Low Reset Value 00 7 6 5 4 3 2 1 0 STR 0 5 r rw Field Bits Type Description MCMPS 5 0 rw Multi Channel PWM Pattern Shadow Bit field MCMPS is the shadow bit field for bit field MCMP The multi channel shadow transfer is triggered according to the transfer conditions defined by register STRMCM 7 Shadow Transfer Request for MCMPS Setting this bit during a write action leads to an i
330. s Manual 6 6 V 0 2 2005 01 Parallel Ports V 0 3 techno ogies Parallel Ports 6 1 1 2 Direction Register The direction of port pins is controlled by the respective direction register Px_DIR Px_DIR Port x Direction Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port x Pin n Direction Control n 0 7 0 Direction is set to input 1 Direction is set to output 6 1 1 3 Open Drain Control Register Each pin in output mode can be switched to open drain mode If driven with 1 no driver will be activated and the pin output state depends on the internal pull up pull down device setting If driven with 0 the driver s pull down transistor will be activated The open drain mode is controlled by the register Px_OD Px_OD Port x Open Drain Control Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 1 nw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port x Pin n Open Drain Mode n 0 7 0 Normal mode output is actively driven for 0 and 1 state 1 Open drain mode output is actively driven only for 0 state User s Manual 6 7 V 0 2 2005 01 Parallel Ports V 0 3 _ Infineon XC866 techno ogies Parallel Ports 6 1 1 4 Pull Up Pull Down Device Register Internal pull up pull down devices can be optionally applied to a port pin This
331. s one request trigger input REQTRx x 0 1 each through which a conversion request can be started The input to REQTRx is selected from eight external trigger inputs ETRxO to ETRx7 a multiplexer depending on bit field ETRSELx It is possible to bypass the synchronization stages for external trigger requests that come synchronous to ADC This selection is done via bit SYNENx Refer to Section 13 7 9 for description of the external trigger control registers rising edge detect ETRx0 ETRx1 REQTRx ETRx7 SYNENx iim gt m Figure 13 16 External Trigger Input The external trigger inputs to the ADC module are driven by events occuring in the CCUG module See Table 13 2 Table 13 2 External Trigger Input Source External Trigger Input CCU6 Event ETRxO T13 period match ETRx1 T13 compare match ETRx2 T12 period match ETRx3 T12 compare match for channel 0 ETRx4 T12 compare match for channel 1 ETRx5 T12 compare match for channel 2 ETRx6 Shadow transfer event for multi channel mode ETRx7 Correct hall event for multi channel mode User s Manual 13 25 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter 13 5 ADC Module Initialization Sequence The following steps is meant to provide a general guideline on how to initialize the ADC module Some steps may be varied or omitted depending on the application requirements
332. sconnect 0 Oscillator is connected to the PLL 1 Oscillator is disconnected from the PLL VCOBYP 3 rw PLL VCO Bypass Mode Select 0 Normal operation default 1 VCO bypass mode PLL output clock is derived from input clock divided by P and K dividers User s Manual Power Reset and Clock V 0 4 7 15 V 0 2 2005 01 _ Infineon XC866 techno ogies Power Supply Reset and Clock Management Field Bits Description NDIV 7 4 rw PLL N Divider 0000 14 00016 15 0010 16 0011 17 0100 18 0101g 19 0110 20 0111 21 10006 24 1001 28 1010 30 10115 32 1100 40 11015 42 11106 45 11115 50 The bit is a protected bit When the Protection Scheme see Chapter 3 3 4 1 is activated this bit cannot be written directly Note The reset value of register PLL CON is 0010 0000g One clock cycle after reset bit LOCK will be set to 1 if the PLL is locked then the value 0010 0001g will be observed User s Manual 7 16 V 0 2 2005 01 Power Reset and Clock V 0 4 Infineon technologies XC866 CMCON Clock Control Register 7 6 Power Supply Reset and Clock Management Reset Value 00 4 3 2 1 0 CLKREL rw Field Bits Type Description CLKREL 3 0 Clock Divider 00006 5 1 00016 fsys 2 00106 fsys 4 00116 fsys 8 01006 5 16
333. se registers contain the control and status bits of parallel request source 1 Register CRCR1 contains the bits that are copied to the pending register CRPR1 when the load event occurs This register can be accessed at two different addresses one read view two write views The first address for read and write access is the address given for CRCR1 The second address for write actions is given for CRPR1 A write operation to CRPR1 leads to a data write to the bits CRCR1 with an automatic load event one clock cycle later CRCR1 Conversion Request Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 0 rwh rwh rwh rwh r Field Bits Type Description CHx X rwh Channel Bit x x 4 7 Each bit corresponds to one analog channel the channel number x is defined by the bit position in the register The corresponding bit x in the conversion request pending register will be overwritten by this bit when the load event occurs 0 The analog channel x will not be requested for conversion by the parallel request source 1 The analog channel x will be requested for conversion by the parallel request source 0 3 0 r Reserved Returns 0 if read should be written with 0 User s Manual 13 44 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter Register CRPR1 contains bits that request a conversion of the corresponding analog channel The bits in this
334. sful execution conversion start Otherwise the pending request will be discarded once it is executed While the automatic refill feature is enabled software should not write data to the queue input register The write address in which to enter a conversion request is given by the write only queue input register QINRO If the queue stage is empty V 0 the written value will be stored there bit V becomes set or else the write action is ignored User s Manual 13 11 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter Refer to Section 13 7 6 for description of the sequential request source registers 13 4 4 2 Request Source Control If the conversion requested by the source is not related to an external trigger event EXTR 0 the valid bit V 1 directly requests the conversion by setting signals REQPND and REQCHNRYV to 1 In this case no conversion will be requested if V 0 A gating mechanism allows the user to enable disable conversion requests according to bit ENGT conversion started REQPND REQCHNRV Figure 13 6 Sequential Request Source Control If the requested conversion is sensitive to an external trigger event EXTR 1 the signal REQTR can be taken into account with ENTR 1 or the software can write TREV 1 Both actions set the event flag EV The event flag EV 1 indicates that external event has taken place and a conversion can be requested
335. should be written with O Enable Register 1 Reset Value 00 7 6 5 4 3 2 1 0 ECCIP3 ECCIP2 ECCIP1 ECCIPO EXM EX2 ESSC EADC rw rw rw rw rw rw rw rw Field Bits Type Description EADC 0 rw ADC Interrupt Enable 0 ADC interrupts are disabled 1 ADC interrupts are enabled ESSC 1 rw SSC Interrupt Enable 0 SSC interrupts are disabled 1 SSC interrupts are enabled EX2 2 rw External Interrupt 2 Enable 0 External interrupt 2 is disabled 1 External interrupt 2 is enabled EXM 3 rw External Interrupts 6 3 Enable 0 External interrupts 6 3 are disabled 1 External interrupt 6 3 are enabled ECCIPO 4 rw CCU6 Interrupt Node Pointer 0 Enable 0 CCU6 Interrupt Node Pointer 0 is disabled 1 CCU6 Interrupt Node Pointer 0 is enabled ECCIP1 5 rw CCU6 Interrupt Node Pointer 1 Enable 0 CCU6 Interrupt Node Pointer 1 is disabled 1 CCU6 Interrupt Node Pointer 1 is enabled User s Manual 5 10 V 0 2 2005 01 Interrupt System V 0 5 _ Infineon technologies XC866 Interrupt System Field Bits Type Description ECCIP2 6 rw CCU6 Interrupt Node Pointer 2 Enable 0 CCU6 Interrupt Node Pointer 2 is disabled 1 CCU6 Interrupt Node Pointer 2 is enabled ECCIP3 7 rw CCU6 Interrupt Node Pointer 3 Enable 0 CCU6 Interrupt Node Pointer is disabled 1 CCU6 Interrupt Node Poin
336. st one CCLK cycle and then hold it high low for at least one CCLK cycle to ensure that the transition is recognized If edge detection is bypassed for external interrupt 0 and external interrupt 1 the external source must hold the request pin high or low for at least two CCLK cycles 5 2 3 Extended Interrupts The extended interrupts are mainly for on chip peripherals which send interrupt requests to the core There are nine interrupt request signals XINTR SRC 13 5 that are driven to the core and each in turn receives an acknowledge signal XINTR ACK 13 5 from the core Some interrupt sources have their own request flag s located in a special function register e g TCON T2CON 5 Registers IRCONO and IRCON1 are used to hold other interrupt request flags for extended and external interrupts As the peripherals devices have more interrupts lines than the core supports some interrupts can be multiplexed and use the same interrupt input to the core A few critical peripheral e g timers CCU6 interrupts are connected directly to the interrupt inputs of the core Each interrupt input requested by the corresponding flag can be individually enabled or disabled by the enable disabled bit in the SFR IENO or IEN1 In addition there is a global enable bit EA contained in Register IENO for all interrupts which when cleared disables all interrupts independent of their individual enable bits Figure 5 1 to Figure 5 5 give a
337. starts to count up to a maximum of FFFF once the timer is started by setting the bit TR2 in register T2CON to 1 Upon overflow bit TF2 is set and the timer register is reloaded with the 16 bit reload value of the RC2 register This reload value is chosen by software prior to the occurrence of an overflow condition A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence If EXEN2 1 the timer counts up to a maximum of FFFF once TR2 is set A 16 bit reload of the timer registers from register RC2 is triggered either by an overflow condition or by a negative positive edge chosen by the bit EDGESEL in register T2MOD at input pin T2EX If an overflow caused the reload the overflow flag TF2 is set If a negative positive transition at pin T2EX caused the reload bit EXF2 in register T2CON is set In either case an interrupt is generated to the core and the timer proceeds to its next count sequence The EXF2 flag similar to the TF2 must be cleared by software Note When 2 is used for the Timer 2 function the bit BCON T2bXIS must be set User s Manual 11 13 V 0 2 2005 01 Timer V 0 4 techno ogies Timer T2EX Figure 11 5 Auto Reload Mode DCEN 0 11 2 1 2 Up Down Count Enabled If DCEN 1 the up down count selection is enabled The direction of count is determined by the level at input pin T2EX The operational block diagram is shown in
338. t channel The bit position directly defines the channel number The bits in the conversion request pending register can be set or reset bitwisely by the arbiter The corresponding bit in the conversion request pending register is automatically reset when the arbiter indicates the start of conversion for this channel The bit is automatically set when the arbiter indicates that the conversion has been aborted A source interrupt can be generated if enabled when a conversion requested by this source is completed while 0 These rules apply only if the request source has triggered the conversion 13 4 5 3 External Trigger The conversion request for the parallel source and also the sequential source can be synchronized to an external trigger event For the parallel source this is done by coupling the reload event to a request trigger input REQTR 13 4 5 4 Software Control The load event for the parallel source can also be generated under software control in two ways The conversion request control register can be written at two different addresses CRCR1 and CRPR1 Accessed at CRCR1 the write action changes only the bits in this register Accessed at CRPR1 the load event will take place one clock cycle after the write access This automatic load event can be used to start conversions with a single move operation In this case the information about the channels to be converted is given as an argument in the move instru
339. t is possible to select one sector a combination of several sectors or all 10 sectors to be erased At the beginning of this subroutine the Flash Timer NMI is enabled to enter the Flash Timer NMI service routine at each of the several timer underflows throughout the erasing sequence Before calling this subroutine the user must ensure that R3 and R4 of Register Bank 3 are set accordingly The microcontroller will first initialize the erasing sequence exit the subroutine then return to the user program code User program code will continue execution from where it last stopped until the next Flash Timer NMI is triggered and the Flash Timer NMI service routine is entered see Figure 4 6 The Flash Timer NMI service routine will first perform a check on the Flash Timer NMI status bit NMISR FNMIFLASHTIMER 1 to ensure that the source is from the Flash Timer before executing the remaining service routine instructions XC866 Flash Memory Table 4 2 D Flash Erase Subroutine Subroutine DFF9 DFLASH ERASE Input of Register Bank IRAM address 1 Select sector s to be erased for D Flash bank LSB represents sector 0 MSB represents sector 7 of Register Bank IRAM address 1 Select sector s to be erased for D Flash bank LSB represents sector 8 bit 1 represents sector 9 Output Flash Timer NMI is enabled NMICON NMIFLASHTIMER 1 Stack size 8 required Resources PSW CY A SCU PAGE
340. t request to the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request is blocked by one of the three previously listed conditions If an User s Manual 5 24 V 0 2 2005 01 Interrupt System V 0 5 techno ogies Interrupt System interrupt of equal or higher priority is already in progress the additional wait time will depend on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than three machine cycles The longest instructions MUL and DIV are only four machine cycles long If the instruction in progress is RETI or a write access to registers IENO IEN1 or IP H IP1 H the additional wait time cannot be more than five cycles a maximum of one more machine cycle to complete the instruction in progress plus four machine cycles to complete the next instruction if the instruction is MUL or DIV Thus in a single interrupt system if the wait states are not considered the response time is between three and nine machine cycles User s Manual 5 25 V 0 2 2005 01 Interrupt System V 0 5 Cnfineon XC866 techno ogies Parallel Ports 6 Parallel Ports The XC866 has 27 port pins organized into four parallel ports Port 0 PO to Port 3 P3 Each pin has a pair of internal pull up and pull down devices that can be individually enabled or disabled
341. t source 0 arbitration slot 0 Event 1 Request source event of parallel request source 1 arbitration slot 1 A result event is generated according to the data reduction control see Section 13 4 7 3 Event 4 Result register event of result register 0 Event 5 Result register event of result register 1 Event 6 Result register event of result register 2 Event 7 Result register event of result register 3 User s Manual 13 22 V 0 2 2005 01 ADC V 0 3 techno ogies Analog to Digital Converter 13 4 8 2 Channel Interrupts The channel interrupts occur when a conversion is completed and the selected limit checking condition is met As a result only one channel interrupt can be activated at a time An interrupt can be triggered according to the limit checking result by comparing the conversion result with two selectable boundaries for each channel bounda 5 BOUNDO BOUND1 conversion finished arbiter to SRO limit channel interupt channel interrupt unit channel number routing to SR1 Figure 13 14 Channel Interrupt Overview The limit checking unit uses two boundaries BOUNDO and BOUND1 to compare with the conversion result With these two boundaries the conversion result space is split into three areas e Area The conversion result is below both boundaries Area Il The conversion result is between the two boundaries Area Ill The conversion
342. tchdog Timer Reset Indication Bit 0 No WDT reset has occurred 1 WDT reset has occurred 0 7 r Reserved Returns 0 if read should be written with 0 User s Manual Watchdog Timer V 0 4 9 8 V 0 2 2005 01 techno ogies Serial Interfaces 10 Serial Interfaces The XC866 contains two serial interfaces the Universal Asynchronous Receiver Transmitter UART and the High Speed Synchronous Serial Interface SSC for serial communication with external devices Additionally the UART can be used to support the Local Interconnect Network LIN protocol UART Features Full duplex asynchronous modes 8 bit or 9 bit data frames LSB first fixed or variable baud rate Receive buffered Multiprocessor communication nterrupt generation on the completion of a data transmission or reception LIN Features Master and slave mode operation SSC Features Master and slave mode operation Full duplex or half duplex operation Transmit and receive buffered Flexible data format Programmable number of data bits 2 to 8 bits Programmable shift direction LSB or MSB shift first Programmable clock polarity idle low or high state for the shift clock Programmable clock data phase data shift with leading or trailing edge of the shift clock e Variable baud rate Compatible with Serial Peripheral Interface SPI Interrupt generation a transmitter empty condition
343. te Detection of LIN In the LIN communication a slave task is required to be synchronized at the beginning of the protected identifier field of frame For this purpose every frame starts with a sequence consisting of a break field followed by a synch byte field This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field In order to detect the baud rate of LIN the bit timing is calculated by measuring the time between the falling edges of pattern In baud rate detection mode the timing of the two bits in Synch Byte field is captured which is shown in Figure 10 8 Synch Byte START 0 1 2 3 4 5 6 7 STOP BIT BIT Figure 10 8 The Bit Timing in Synch Byte Register bits 4 7 of BCON register see Page 10 12 are used for the LIN baud rate detection Register bit BRDIS is used to enable disable the baud rate detection Register bit T2EXIS is used to choose the T2EX pin P1 0 for the baud rate detection purpose or for the normal Timer 2 function use Users should specify the baud rate range via the register bit BGSEL if they know the range of the LIN baud rate The baud rate detection unit will use different sampling rates for different baud rates according to this information This will result in accurate baud rate detection The following sequence is generally executed to start the baud rate detection Step1
344. ted synchronization to T13 10 Reserved 11 The trap state is left return to normal operation according to TRPM2 immediately without any synchronization to T12 or T13 User s Manual 12 60 V 0 2 2005 01 CCUG V 0 4 techno ogies Capture Compare Unit 6 Field Bits Type Description TRPM2 2 rw Trap Mode Control Bit 2 0 The trap state can be left return to normal operation bit TRPS 0 as soon as the input CTRAP becomes inactive Bit TRPF is automatically cleared by hardware if the input pin CTRAP becomes 1 Bit TRPS is automatically cleared by hardware if bit TRPF is 0 and if the synchronization condition according to and 1 is detected 1 The trap state can be left return to normal operation bit TRPS 0 as soon as bit TRPF is reset by software after the input CTRAP becomes inactive TRPF is not cleared by hardware Bit TRPS is automatically cleared by hardware if bit TRPF 0 and if the synchronization condition according to TRPMO and TRPM1 is detected 0 7 3 Reserved Returns 0 if read should be written with 0 TRPCTRH Trap Control Register High Reset Value 00 7 6 5 4 3 2 1 0 TRP TRP PEN EN TRPEN 13 rw rw rw User s Manual 12 61 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description TRPEN 5 0 rw
345. ter 3 is enabled NMICON NMI Control Register Reset Value 00 7 6 5 4 3 2 1 0 NMI 0 NMIECC NMIVDDP NMIVDD NMIOCDS MER NMIPLL NMIWDT r rw rw rw rw rw rw rw Field Bits Type Description NMIWDT 0 rw Watchdog Timer NMI Enable 0 WDT NMI is disabled 1 WDT NMI is enabled NMIPLL 1 rw PLL Loss of Lock NMI Enable 0 PLL Loss of Lock NMI is disabled 1 PLL Loss of Lock NMI is enabled NMIFLASH 2 rw Flash Timer NMI Enable TIMER 0 Flash Timer NMI is disabled 1 Flash Timer NMI is enabled NMIOCDS 3 rw OCDS NMI Enable 0 OCDS is disabled 1 OCDS NMI is enabled NMIVDD 4 rw VDD Prewarning NMI Enable 0 VDD NMI is disabled 1 VDD NMI is enabled NMIVDDP 5 rw VDDP Prewarning NMI Enable 0 VDDP is disabled 1 VDDP NMI is enabled Note When the external power supply is 3 3 V the user must disable NMIVDDP User s Manual Interrupt System V 0 5 5 11 V 0 2 2005 01 Cnfineon XC866 techno ogies Interrupt System Field Bits Type Description NMIECC 6 rw ECC NMI Enable 0 ECC NMI is disabled 1 ECC NMI is enabled 0 7 r Reserved Returns 0 if read should be written with 0 EXICONO External Interrupt Control Register 0 Reset Value 00 7 6 5 4 3 2 1 0 EXINT3 EXINT2 EXINT1 EXINTO rw rw rw rw Field Bits Type Description EXINTO 1 0 rw External Interrupt 0 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 In
346. terrupt on both rising and falling edge 11 Bypass the edge detection EXINT1 3 2 rw External Interrupt 1 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Bypass the edge detection EXINT2 5 4 rw External Interrupt 2 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved EXINT3 7 6 rw External Interrupt 3 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved User s Manual 5 12 V 0 2 2005 01 Interrupt System V 0 5 Infineon technologies XC866 Interrupt System EXICON1 External Interrupt Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 0 EXINT6 EXINT5 EXINT4 r rw rw rw Field Bits Type Description EXINT4 1 0 rw External Interrupt 4 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved EXINT5 3 2 rw External Interrupt 5 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved EXINT6 5 4 rw External Interrupt 6 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edge 11 Reserved 0 7 6 r Reserved
347. terrupt pulse is generated The bits in register CHINPR define the service request output line SRx x 0 or 1 that is activated if a channel interrupt is generated CHINPR Channel Interrupt Node Pointer Register Reset Value 00 7 6 5 4 3 2 1 0 CHINP7 CHINP6 CHINP5 4 CHINP3 CHINP2 CHINP1 CHINPO rw rw rw rw rw rw rw rw Field Bits Type Description CHINPx X rw Interrupt Node Pointer for Channel x x 20 7 This bit defines which SR lines becomes activated if the channel x interrupt is generated 0 The line SRO becomes activated 1 The line SR1 becomes activated User s Manual 13 53 ADC V 0 3 V 0 2 2005 01 Infineon technologies Register EVINFR monitors the activated event interrupt flags XC866 Analog to Digital Converter EVINFR Event Interrupt Flag Register Reset Value 00 7 6 5 4 1 0 EVINF7 EVINF6 EVINF5 EVINF4 0 EVINF1 EVINFO rh rh rh rh r rh rh Field Bits Type Description EVINFx 1 0 rh Interrupt Flag for Event x x 0 14 4 7 7 4 This bit monitors the status of the event interrupt x 0 An event interrupt for event x has not occurred 1 An event interrupt for event x has occurred 3 2 Reserved Returns 0 if read should be written with 0 Writing a 1 to a bit position in register EVINCR clears the corresponding event interrupt flag in register EVI
348. terrupts This bit field defines the interrupt output line which is activated due to a set condition for bit T12OM if enabled by bit ENT12OM or for bit T12PM if enabled by bit ENT12PM 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPT13 5 4 Interrupt Node Pointer for Timer T13 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit T13CM if enabled by bit ENT13CM or for bit T13PM if enabled by bit ENT13PM 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected 0 7 6 Reserved Returns 0 if read should be written with 0 User s Manual 6 V 0 4 12 90 0 2 2005 01 _ Infineon XC866 techno ogies Analog to Digital Converter 13 Analog to Digital Converter The XC866 includes a high performance 10 bit Analog to Digital Converter ADC with eight multiplexed analog input channels The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources Features Successive approximation 8 bit or 10 bit resolution TUE of 1 LSB and 2 LSB respectively Eight analog channels Four independent result registers config
349. th bit WHE wrong hall event and it must be reset by software 0 No action 1 Bit field MCMP is cleared the selected outputs are set to passive state STR 7 rh Multi Channel Mode Shadow Transfer Request This bit is set when a shadow transfer from MCMOUTS to MCMOUT takes places in multi channel mode 0 The shadow transfer has not taken place 1 The shadow transfer has taken place 1 During the trap state the selected outputs are set to the passive state The logic level driven during the passive state is defined by the corresponding bit in register PSLR Bit TRPS 1 and TRPF 0 can occur if the trap condition is no longer active but the selected synchronization has not yet taken place equal bit CHE is set On every valid hall edge the contents of EXPH are compared with the pattern on pin CCPOSx and if both are On every valid hall edge the contents of EXPH are compared with the pattern on pin CCPOSx If both comparisons CURH EXPH with CCPOSx are not true bit WHE wrong hall event is set 4 Bit field MCMP is held to 0 by hardware as long as IDLE 1 Note Not all bits in register 15 can generate an interrupt Other status bits have been added which have a similar structure for their set and reset actions Note The interrupt generation is independent of the value of the bits in register IS e g the interrupt will be generated if enabled even if the corresponding bit is already set The trigger for an
350. the actual and the shadow registers can be read The transfer from the shadow registers to the actual registers is enabled by setting the shadow transfer enable bit STE12 If this transfer is enabled the shadow registers are copied to the respective registers as soon as the associated timer reaches the value zero the next time being cleared in edge aligned mode or counting down to 1 in center aligned mode When timer T12 is operating in center aligned mode it will also copy the registers if enabled by STE 12 if it reaches the currently programmed period value counting up When timer T12 is stopped the shadow transfer takes place immediately if the corresponding bit STE12 is set Once the transfer is complete the respective bit STE12 is cleared automatically Figure 12 2 shows an overview of Timer T12 one match zero match period match period shadow transfer compare shadow transfer capture events according to bitfield MSEL6x counter register T12 CCUG T12 overv Figure 12 2 T12 Overview User s Manual 12 3 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 1 1 1 Timer Configuration Register T12 represents the counting value of timer T12 It can be written only while timer T12 is stopped Write actions while T12 is running are not taken into account Register T12 can always be read by software In edge aligned mode T12 only coun
351. the correct kernel output or kernel input line of the ports when switching modes Since the SSC I O lines are connected with the bidirectional lines of the general purpose I O ports software I O control is used to control the port pins assigned to these lines The port registers must be programmed for alternate output and input selection When switching between master and slave modes port registers must be reprogrammed 10 3 1 6 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability allowing baud rate generation independent of the timers Figure 10 14 shows the baud rate generator 16 Bit Reload Register Nu f fus 2 16 Bit Counter f MS_CLK max in Master Modes f 2 PCLK fss max In Master Modes foo 4 Figure 10 14 SSC Baud rate Generator baud rate generator is clocked with the module clock fpc The timer counts downwards Register BR is the dual function Baud rate Generator Reload register Reading BR while the SSC is enabled returns the contents of the timer Reading BR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to BR Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the
352. the data bytes that will be coming The slaves that were not being addressed retain their SM2s as set and ignore the incoming data bytes Bit SM2 can be used in mode 1 to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received 10 1 3 Register Description The UART uses two Special Function Registers SFRs SCON and SBUF SCON is the control register and SBUF is the data register On reset both SCON and SBUF return The serial port control and status register is the SFR SCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits TI and RI SBUF is the receive and transmit buffer of the serial interface Writing to SBUF loads the transmit register and initiates transmission This register is used for both transmit and receive data Transmit data is written to this location and receive data is read from this location but the two paths are independent Reading out SBUF accesses a physically separate receive register SBUF Serial Data Buffer Reset Value 004 7 6 5 4 3 2 1 0 VAL rwh User s Manual 10 7 V 0 2 2005 01 Serial Interfaces V 0 3 _ lnfineon XC866 techno ogies Serial Interfaces Field Bits Description VAL 7 0
353. then can the desired access be performed If an interrupt routine is initiated between the page register access and the module register access and the interrupt needs to access a register located in another page the current page setting can be saved the new one programmed and finally the old page setting restored This is possible with the storage fields STx x 0 3 for the save and restore action of the current page setting By indicating which storage bit field should be used in parallel with the new page value a single write operation can e Save the contents of PAGE in STx before overwriting with the new value this is done in the beginning of the interrupt routine to save the current page setting and program the new page number or Overwrite the contents of PAGE with the contents of STx ignoring the value written to the bit positions of PAGE this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred STNR value update from CPU Figure 3 5 Storage Elements for Paging With this mechanism a certain number of interrupt routines or other routines can perform page changes without reading and storing the previously used page information The use of only write operations makes the system simpler and faster Consequently this mechanism significantly improves the performance of short interrupt routines The XC866 supports local address extension for Par
354. timer will only run if the core external interrupt EXINTx 1 This facilitates pulse width measurements However this is not applicable for Timer 1 in mode 3 If TMOD GATEx is cleared the timer reverts to pure software control 11 1 2 Timer Modes Timers 0 and 1 are fully compatible and can be configured in four different operating modes as shown in Table 11 1 The bit field TxM in register TMOD selects the operating mode to be used for each timer In modes 0 1 2 the two timers operate independently but in mode 3 their functions are specialized Table 11 1 Timer 0 and Timer 1 Modes Mode Operation 0 13 bit timer The timer is essentially an 8 bit counter with a divide by 32 prescaler This mode is included solely for compatibility with Intel 8048 devices 1 16 bit timer The timer registers TLx and THx are concatenated to form a 16 bit counter 2 8 bit timer with auto reload The timer register TLx is reloaded with a user defined 8 bit value in THx upon overflow 3 Timer 0 operates as two 8 bit timers The timer registers TLO and THO operate as two separate 8 bit counters Timer 1 is halted and retains its count even if enabled User s Manual 11 2 V 0 2 2005 01 Timers V 0 4 techno ogies Timers 11 1 2 1 Mode 0 Putting either Timer 0 or Timer 1 into mode 0 configures it as 8 bit timer with a divide by 32 prescaler Figure 11 1 shows the mode 0 operation In this mode
355. torage It is used to distinguish the different Flash bank sectorizations 128 byte Sector 2 128 byte Sector 9 128 byte Sector 1 128 byte Sector 8 128 byte Sector 7 128 byte Sector 6 256 byte Sector 5 256 byte Sector 4 512 byte Sector 3 3 75 Kbyte Sector 0 512 byte Sector 2 1 Kbyte Sector 1 1 Kbyte Sector 0 P Flash D Flash Figure 4 2 Flash Bank Sectorization Sector Partitioning in P Flash One 3 75 Kbyte sector Two 128 byte sectors Sector Partitioning in D Flash Two 1 Kbyte sectors Two 512 byte sectors Two 256 byte sectors Four 128 byte sectors The internal structure of each Flash bank represents a sector architecture for flexible erase capability The minimum erase width is always a complete sector and sectors can be erased separately or in parallel Contrary to standard EPROMs erased Flash memory cells contain Os User s Manual 4 3 V 0 2 2005 01 Flash Memory V 0 3 techno ogies Flash Memory The D Flash bank is divided into more physical sectors for extended erasing and reprogramming capability even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements For example the user s program can implement a buffer mechanism for each sector Double copies of each data set can be stored in separate sectors of similar size to ensure
356. transfer is enabled CDIR 6 rh Count Direction of Timer T12 This bit is set reset according to the counting rules of 12 0 T12 counts up 1 T12 counts down CTM 7 rw T12 Operating Mode 0 Edge aligned mode T12 always counts up and continues counting from zero after reaching the period value 1 Center aligned mode T12 counts down after detecting a period match and counts up after detecting a one match 1 A concurrent set reset action on T12R from T12SSC T12RR or T12RS will have no effect The bit T12R will remain unchanged TCTROH Timer Control Register 0 High Reset Value 00 7 6 5 4 3 2 1 0 STE T13 0 13 13 T13CLK r rh rh nw rw User s Manual 12 49 V 0 2 2005 01 CCUG V 0 4 Infineon technologies XC866 Capture Compare Unit 6 Field Bits Type Description T13CLK 2 0 rw Timer T13 Input Clock Select Selects the input clock for timer T13 which is derived from the peripheral clock according to the equation fccug 27 000 fr43 focus 001 ft13 fccue 2 010 fr43 fccug 4 011 fecue 8 100 1 fccug 16 101 fr43 32 110 fr43 64 111 fr43 1 28 T13PRE 3 rw Timer T13 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler for T13 0 The additional prescaler for T13 is disabl
357. ts Type Description WDTREL 7 0 Watchdog Timer Reload Value for the high byte of WDT A new reload value can be written to WDTREL and this value is loaded to the upper 8 bits of the WDT upon the enabling of the timer or the next service for refresh User s Manual 9 5 V 0 2 2005 01 Watchdog Timer V 0 4 Infineon technologies XC866 WDTCON Watchdog Timer Watchdog Timer Control Register Reset Value 00 7 6 5 4 3 2 1 0 WINBEN WDTPR 0 WDTEN WDTRS WDTIN rw rh r rw rwh rw Field Bits Type Description WDTIN 0 Watchdog Timer Input Frequency Selection 0 Input frequency is fyyp1 2 1 Input frequency is 128 WDTRS 1 rwh WDT Refresh Start Active high Set to start refresh operation on the WDT Cleared automatically by hardware WDTEN 2 WDT Enable 0 WDT is disabled 1 WDT is enabled WDTEN is a protected bit If the Protection Scheme see Chapter 3 3 4 1 is activated then this bit cannot be written directly WDTPR 4 Watchdog Prewarning Mode Flag 0 Normal mode default after reset 1 The Watchdog is operating in prewarning mode This bit is set to 1 when a Watchdog error is detected The WDT has issued an NMI trap and is in prewarning mode A reset of the chip occurs after the prewarning period has expired WINBEN 5 Watchdog Window Boundary Enable 0 Watchdog Window Boundary feature is disabl
358. ts up whereas center aligned mode T12 count up and down Timer T12 can be started and stopped by using bit T12R by hardware or software Bit field T12RSEL defines the event on pin T12HR rising edge falling edge or either of these two edges that can set the run bit T12R by hardware If bit field T12RSEL 00g the external setting of T12R is disabled and the timer run bit can only be controlled by software Bit T12R is set reset by software by setting bit T12RR or T12RS n single shot mode bit T12R is reset by hardware according to the function defined by bit T12SSC If bit T12SSC 1 the bit T12R is reset by hardware when T12 reaches its period value edge aligned mode T12reaches the value 1 while counting down in center aligned mode Register T12 can be reset to zero by setting bit T12RES Setting of T12RES has no impact on run bit T12R 12 1 1 2 Counting Rules With reference to the T12 input clock the counting sequence is defined by the following counting rules T12 in edge aligned mode Bit CTM 0 The count direction is set to counting up CDIR 0 The counter is reset to zero if a period match is detected and the T12 shadow register transfer takes place if STE12 1 T12 in center aligned mode Bit CTM 1 The count direction is set to counting up CDIR 0 if a one match is detected while counting down The count direction is set to counting down CDIR 1 if a period match is d
359. ue 00 7 6 5 4 3 2 1 0 OP STNR 0 PAGE w w r w Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page When read the value indicates the currently active page STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10 the contents of PAGE are saved in STx before being overwritten with the new value If OP 11g the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STOis selected 01 ST1is selected 10 ST2is selected 11 ST3is selected User s Manual 6 11 V 0 2 2005 01 Parallel Ports V 0 3 Infineon technologies XC866 Parallel Ports Field Bits Type Description OP 7 6 Ww Operation OX 10 11 Manual page mode The value of STNR is ignored and PAGE is directly written New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR Reserved Returns 0 if read should be written with 0 User s Manual Parallel Ports V 0 3
360. urable for FIFO functionality Result data protection for slow CPU access wait for read mode e Single conversion mode e Autoscan functionality Limit checking for conversion results Data reduction filter accumulation of up to 2 conversion results Two independent conversion request sources with programmable priority Selectable conversion request trigger Flexible interrupt generation with configurable service nodes Programmable sample time Programmable clock divider e Cancel restart feature for running conversions Integrated sample and hold circuitry Compensation of offset errors Low power modes User s Manual 13 1 V 0 2 2005 01 ADC V 0 3 _ Infineon XC866 techno ogies Analog to Digital Converter 13 1 Structure Overview The ADC module consists of two main parts i e analog and digital with each containing independent building blocks The analog part includes Analog input multiplexer for selecting the channel to be converted Analog converter stage e g capacitor network and comparator as part of the ADC Digital control part of the analog converter stage for controlling the analog to digital conversion process and generating the conversion result The digital part defines and controls the overall functionality of the ADC module and includes Digital data and conversion request handling for controlling the conversion trigger mechanisms and handling the co
361. ure 12 6 shows the functionality at the end of the timer period in edge aligned and center aligned modes If the end of period event is detected while bit 1255 is set the bit T12R and all CC6xST bits are reset edge aligned mode center aligned mode T12P veu d while counting up T12P 1 T12P 2 one match while if T12SSC 1 counting down T12 1255 1 T12 T12R T12R CC6xST CCU6_T12_singleshot Figure 12 6 End of Single Shot Mode of T12 User s Manual 12 9 V 0 2 2005 01 CCU6 V 0 4 techno ogies Capture Compare Unit 6 12 1 1 9 Hysteresis Like Control Mode The hysteresis like control mode MSEL6x 10015 offers the possibility of switching off the PWM output if the input CCPOSx becomes 0 by resetting bit CC6xST This can be used as a simple motor control feature by using a comparator to indicate for example over current While CCPOSx 0 the PWM outputs of the corresponding channel are driving their passive levels The setting of bit CC6xST is only possible while CCPOSx 1 Figure 12 7 shows an example of hysteresis like control mode This mode can be used to introduce a timing related behavior to a hysteresis controller A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result Depending on the operating conditions the switching frequency and the duty cycle may change constantly Period
362. ure Timer 2 for the various modes of operation T2MOD Timer 2 Mode Register Reset Value 00 7 6 5 4 3 2 1 0 0 EDGESEL T2PRE DCEN r rw rw rw rw Field Bits Type Description DCEN 0 rw Up Down Counter Enable 0 Up Down Counter function is disabled 1 Up Down Counter function is enabled and controlled by pin T2EX Up 1 Down 0 User s Manual 11 17 V 0 2 2005 01 Timer V 0 4 Infineon technologies XC866 Timer Field Bits Type Description T2PRE 3 1 rw Timer 2 Prescaler Bit Selects the input clock for Timer 2 which is derived from the peripheral clock 000 001 2 010 fr2 4 011 8 100 fr2 fpc 1 6 Others reserved PREN Prescaler Enable 0 Prescaler is disabled and the 2 12 divider takes effect 1 Prescaler is enabled see T2PRE bit and the 2 12 divider is bypassed EDGESEL Edge Select in Capture Mode Reload Mode 0 The falling edge at pin T2EX is selected 1 The rising edge at pin T2EX is selected 7 6 Reserved Returns 0 if read should be written with 0 User s Manual Timer V 0 4 11 18 V 0 2 2005 01 technologies Timer Register T2CON controls the operating modes of Timer 2 In addition it contains the status flags for interrupt generation T2CON Timer 2 Contr
363. utput function COUT63 is enabled for the PWM signal generated by T13 0 6 Reserved Returns 0 if read should be written with 0 User s Manual CCUG V 0 4 12 59 V 0 2 2005 01 Cnfineon XC866 techno ogies Capture Compare Unit 6 Register TRPCTR controls the trap functionality It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition The trap condition is a low level on the CTRAP input pin which is monitored inverted level by bit TRPF in register IS While TRPF 1 trap input active the trap state bit TRPS in register IS is set to 1 TRPCTRL Trap Control Register Low Reset Value 00 7 6 5 4 3 2 1 0 0 TRP TRP TRP M2 M1 MO r rw rw rw Field Bits Type Description TRPMO 1 0 rw Trap Mode Control Bits 0 1 TRPM1 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again A synchronization to the timer driving the PWM pattern avoids unintended short pulses when leaving the trap state The combination TRPMO and 1 leads to 00 The trap state is left return to normal operation according to TRPM2 when a zero match of T12 while counting up is detected synchronization to T 12 01 The trap state is left return to normal operation according to TRPM2 when a zero match of T13 is detec
364. value that ensures fApci does not exceed 10 MHz The prescaler ratio is selected by bit field CTC in register GLOBCTR A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required fanc digital part 1 Condition f lt 10 MHz Figure 13 2 Clocking Scheme User s Manual 13 3 V 0 2 2005 01 ADC V 0 3 Cnfineon XC866 techno ogies Analog to Digital Converter For module clock fapc 26 7 MHz the analog clock fapc frequency can be selected as shown in Table 13 1 Table 13 1 fapc Frequency Selection Module Clock fapc CTC Prescaling Ratio Analog Clock fApci 26 7 MHz 00g 2 13 3 MHz N A 01g 3 8 9 2 106 4 6 7 2 11 default 32 833 3 2 As fapc cannot exceed 10 MHz bit field CTC should not be set to 00g when 1 is 26 7 MHz During slow down mode where fApc be reduced to 13 3 MHz 6 7 MHz etc can be set to 00g as long as the divided analog clock fApc does not exceed 10 MHz However it is important to note that the conversion error could increase due to loss of charges on the capacitors becomes too low during slow down mode 13 2 1 Conversion Timing The analog to digital conversion procedure consists of the following phases e Synchronization phase Sample phase ts Conversion phase e Write result phase twp conversion start Source
365. w Reset Value 00 7 6 5 4 3 2 1 0 RC2L 2 Timer 2 Reload Capture Register High Reset Value 00 7 6 5 4 3 2 1 0 RC2H rwh Field Bits Type Description RC2 7 0 of rwh Reload Capture Value RC2L If CP RL2 0 these contents are loaded into the 7 0 of timer register upon an overflow condition RC2H If CP RL2 1 this register is loaded with the current timer count upon a negative positive transition at pin 2 when 2 1 User s Manual Timer V 0 4 11 20 V 0 2 2005 01 _ Infineon XC866 techno ogies Timer Register T2 holds the current 16 bit value of the Timer 2 count T2L Timer 2 Register Low Reset Value 00 7 6 5 4 3 2 1 0 THL2 rwh T2H Timer 2 Register High Reset Value 00 7 6 5 4 3 2 1 0 THL2 Field Bits Type Description THL2 7 0 of rwh Timer 2 Value T2L These bits indicate the current timer value 7 0 of T2H User s Manual 11 21 V 0 2 2005 01 Timer V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 12 Capture Compare Unit 6 The Capture Compare Unit 6 CCU6 provides two independent timers T12 T13 which can be used for Pulse Width Modulation PWM generation especially for AC motor control The CCU6 also supports special control modes for block commutation and multi phase machines The block diagram of the CCU6 module is shown in Figu
366. w type and can be raised in two ways by a request via the JTAG interface using a special sequence an external device connected to the JTAG can break a user program running on the XC866 and start a debug session by asserting low the dedicated Monitor and BootStrap loader Control line MBC while the XC866 is running used for reaction to asynchronous events from the external world 14 2 2 Debug Actions In case of a debug event the OCDS system can respond in two ways depending on the current configuration 14 2 2 1 Call the Monitor Program XC866 comes with an on chip Monitor program factory stored into the non volatile Monitor ROM see Figure 14 1 Activating this program is the primary and basic OCDS reaction to recognized debug events The OCDS hardware ensures that the Monitor is always safely started and fully independent of the current system status at the moment the debug action is taken Also additional interrupt requests raised meanwhile will not disturb the Monitor s functioning Once started the Monitor runs with own stack and data work memory see Monitor RAM in Figure 14 1 which guarantees that all of the core and memory resources will be found untouched when returning control back to the user program The functions of the XC866 Monitor include communication with an external Debugger via the JTAG interface read write access to arbitrary memory locations and Special Function Registers SFRs includi
367. ware 14 5 14 2 1 3 Exiciiial BreakS e a EnEn 14 6 14 2 2 Debug ACHONS tab a ae a ae a a aE 14 6 14 2 2 1 Call the Monitor 14 6 14 2 2 2 Activate the MBC pin 14 6 14 3 Register Description 14 7 14 3 1 JTAG ID Register 14 9 15 jr 2555 54 a e a 15 1 15 1 ceca ca e a 15 1 15 2 Regist r ee eee be oh bens tone RE E 15 6 User s Manual 7 V 0 2 2005 01 techno ogies Introduction 1 Introduction The XC866 is a member of the high performance XC800 family of 8 bit microcontrollers It is based on the XC800 Core that is compatible with the industry standard 8051 processor The XC866 features a great number of enhancements to enable new application technologies through its highly integrated on chip components such as on chip oscillator or an integrated voltage regulator allowing a single voltage supply of 3 0 to 5 5 V In addition the XC866 is equipped with either embedded Flash memory to offer high flexibility in development and ramp up or compatible ROM versions to provide cost saving potential in high volume production The multi bank Flash architecture supports In Application Programming IAP allowing user p
368. ware Breakpoint registers which are accessible indirectly via HWBPSR and HWBPDR see Table 14 2 Table 14 2 OCDS Indirectly Accessible Registers Register Register Full Name Short Name HWBPOL Hardware Breakpoint 0 Low Register HWBPOH Hardware Breakpoint O High Register HWBP1L Hardware Breakpoint 1 Low Register HWBP1H Hardware Breakpoint 1 High Register HWBP2L Hardware Breakpoint 2 Low Register HWBP2H Hardware Breakpoint 2 High Register HWBP3L Hardware Breakpoint 3 Low Register HWBP3H Hardware Breakpoint 3 High Register Note The OCDS registers are dedicated primarily to the on chip Monitor program and the user is strongly advised not to access them as this can cause an unexpected behavior of the system User s Manual 14 7 V 0 2 2005 01 OCDS V0 2 techno ogies Register Description The Hardware Breakpoint registers can be used for general purposes only if the XC866 is not started in OCDS mode and no external device is connected to the JTAG interface See Table 14 1 Table 14 2 and the description below HWBPSR Hardware Breakpoints Select Register mapped SFR F6 Reset value 004 7 6 5 4 3 2 1 0 0 BPSEL_P BPSEL r nw Field Bits Type Description BPSEL 3 0 rw BreakPoint Register Select BPSEL_P 4 Bit Protection 0 BPSEL unchangeable 1 BPSEL can be changed 0 7 5 r Reserved Returns 0 if read should be written with 0
369. wh Oscillator Run Detection Reset 0 No operation 1 The oscillator run detection logic is reset and restarted This bit will automatically be reset to 0 OSCSS 2 rw Oscillator Source Select 0 On chip oscillator is selected 1 External oscillator is selected XPD 3 rw XTAL Power down Control 0 XTAL is not powered down 1 XTAL is powered down OSCPD 4 rw On chip OSC Power down Control 0 The on chip oscillator is not powered down 1 The on chip oscillator is powered down 0 7 5 r Reserved Returns 0 if read should be written with 0 Note The reset value of register OSC CON is 0000 10005 One clock cycle after reset bit OSCR will be set to 1 if the oscillator is running then the value 0000 1001g will be observed User s Manual 7 14 V 0 2 2005 01 Power Reset and Clock V 0 4 Infineon technologies XC866 Power Supply Reset and Clock Management PLL CON PLL Control Register Reset Value 0010 0000 7 5 4 3 2 1 0 VCOBYP OSCDISC RESLD LOCK nw rw rw rwh rh Field Bits Description LOCK 0 rh PLL Lock Status Flag 0 PLL is not locked 1 PLL is locked RESLD 1 rwh Restart Lock Detection Setting this bit will reset the PLL lock status flag and restart the lock detection This bit will automatically be reset to 0 and thus always be read back as 0 0 No effect 1 Reset lock flag and restart lock detection OSCDISC 2 rw Oscillator Di
370. which can be achieved using a certain module clock Some numbers are rounded to 3 significant digits Table 9 1 Watchdog Time Ranges Reload value Prescaler for fpc in WDTREL 2 WDTIN 0 128 WDTIN 1 20 MHz 16 MHz 12 MHz 20MHz 16MHz 12 MHz 25 6 us 32 0 us 42 67 us 1 64 2 05 2 73 ms 3 3 4 13 5 5 211 264 352 ms 00 6 55 ms 8 19 10 92 ms 419 ms 5245 699 ms Note For safety reasons the user is advised to rewrite WDTCON each time before the WDT is serviced User s Manual Watchdog Timer V 0 4 9 4 V 0 2 2005 01 Cnfineon XC866 techno ogies Watchdog Timer 9 2 Register Map The WDT SFRs are located in the mapped SFR area Table 9 2 lists the addresses of these SFRs Table 9 2 SFR Address list Address Name WDTCON BC WDTREL WDTWINB BE WDTL WDTH 9 3 Register Description The current count value of the WDT is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register The operation of the WDT is controlled by its bitaddressable WDT Control Register WDTCON This register also selects the input clock prescaling factor The register WDTREL specifies the reload value for the high byte of the timer WDTREL Watchdog Timer Reload Register Reset Value 00 7 6 5 4 3 2 1 0 WDTREL Ani Field Bi
371. will be set ST12PM 7 Set Timer T12 Period Match Flag 0 No action 1 Bit T12PM in register IS will be set Note If the setting by hardware of the corresponding flags leads to an interrupt the setting by software has the same effect User s Manual 12 80 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogies Capture Compare Unit 6 ISSH Capture Compare Interrupt Status Set Register High Reset Value 00 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 T13 T13 STR IDLE WHE CHE WHC TRPF PM CM Ww Ww Ww Ww Ww Ww Ww Ww Field Bits Type Description ST13CM 0 Ww Set Timer T13 Compare Match Flag 0 No action 1 Bit T13CM in register IS will be set ST13PM 1 Set Timer T13 Period Match Flag 0 No action 1 Bit T13PM in register IS will be set STRPF 2 Set Trap Flag 0 No action 1 Bits TRPF and TRPS in register IS will be set SWHC 3 Software Hall Compare 0 No action 1 The Hall compare action is triggered SCHE 4 Set Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be set SWHE 5 Set Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be set SIDLE 6 Set IDLE Flag 0 No action 1 Bit IDLE in register IS will be set SSTR 7 Set STR Flag 0 No action 1 Bit STR in register IS will be set User s Manual 12 81 V 0 2 2005 01 6 V 0 4 Cnfineon XC866 techno ogi
372. with independent registers The request sources are used to trigger conversions due to external events synchronization to PWM signals sequencing schemes etc An arbiter that regularly scans the request sources to find the channel with the highest priority for the next conversion The priority of each source can be programmed individually to obtain the required flexibility to cover the desired range of applications Control registers for each of the eight channels that define the behavior of each analog input such as the interrupt behavior a pointer to a result register a pointer to a channel class etc An input class register that delivers general channel control information sample time from a centralized location Four result registers instead of one result register per analog input channel for storing the conversion results and controlling the data reduction This allows the creation of result data FIFOs A decimation stage for conversion results adding the incoming result to the value already stored in the targeted result register This stage allows fast consecutive conversions without the risk of data loss for slow CPU clock frequency parallel request source 1 arbitration slot 1 sequential request source 0 arbitration slot 0 channel control 7 channel control O analog input 7 input dass 0 analog input 0 result register 3 result register 0 data reduction Figure 13 4

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