MimoStar3 User Manual - IPHC
Contents
1. Ck1SM E ckratp ANNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN A eee ne aaa Super mul a d ace bei 1 i RstMk t 1 HEEN 1 1 SSync t 1 1 re ea E MxFirst LastCol LastRow Appen AoutP lt B gt 8 081 4U8m 1 1 Appen 0 Aout lt 1 gt 8 08 cy 464m 1 L L 1 fi 3 2u 3 4u 3 6u 3 8u 4 8u 42u 4 4u 4 Bu 4 8u 5 time sl Initialisation phase ji row readout phase k nnana Figure 5 3 6 2 Test mode readout The initialisation phase if the test mode is the same than in the normal mode But it has to be noticed than the LastCol and LastRow makers are unavailable because the test mode has nothing to deal with the matrix and its line and column addressing registers For the same reason the MxFirst maker is unavailable in the First Pixel of frame mode but only continuous mode March 2007 MimoStar3 User Manual 12 Mimo 3 CkRdLp E RBD Syne RstMk alee e E 5S oe nuque i MxFirst Bee SERGE CEA d ee i i LastGol i l LastRow z i 566m 4 Aout lt g gt m sfavo sf2vo sfovo sf3vo Sf1V2. iPHC Institut Plyridisci linaire URIEN Bert SERIEN MimoStar3 User Manual MimoStar2 User Manual C Colledani W Dulinski H Himmi Ch Hu I Valin Institut de Recherches Subatomiques IN2P3 CNRS ULP Strasbourg France IN2P3 B Cae E a SCIENTIFIQUE m UNIVERSIT M LOUIS PASTEUR D Istrrur NATIONAL DE PHYSIQUE NUCL AIRE STRASBOURG ET DE PHYSIQUE DES PARTICULES Mimok Document history March 2007 Based on MimoStar2 Version March 2007 MimoStar3 User Manual 1 2 Mimo 3 reiege ss RI RU PCR OM E CO in Mu M MENS DUM sa eine 3 COOL USAC egene 4 21 JTAG Instruction ET 4 22 JTAG RO ISO SR e ea S an nE EE cats teed E S TESA naoi En 5 2 2 1 Lustr ction Register 4 erii ui cut EH AH Ob Le a up PRU dS 5 2 2 2 Bypass Re ristet enoei a a o yee 5 2 2 3 Boundary Scan RE 5 2 2 4 ID CODE Resister nn nn E EE E E E 5 2 2 5 II CO TROIS EE 6 2 2 6 RO Mod REMISE en nt nn in 6 2 2 7 BIAS DAC Corr nana 6 mue MIIBOSUES eut EES 7 3 1 Atter reset a 7 3 2 IE idit ejr anna eebe ee 7 3 3 Setting the Readout_Mode eege 8 3A EE 8 3 4 1 Signal Protocol eec 8 3 4 2 Successive frames and resynchronisation essere 8 3 5 Analogue Data Format iie erbe io oet idee de 8 3 5 1 Normal mod data format EN 9 3 5 2 Test mode data format 9 m5 MimoStar3 CROIS aS ee a ne As 10 3 6 1 Normal Read tt s serienn ce 10 SOIL Readout NERO MSNM e RR does 10 3 6 2 Te
3. SfAPx 0 63 gt Sf3Px lt 0 63 gt Sf 2Px lt 0 63 gt Sf1Px lt 0 63 gt Sf0Px lt 0 63 Gud 0 62 Sro 0L62 S8 29x EE Sr4ex lt 0 0 gt BEE OL Di BEE 0 OF Stiex lt 0 0 gt cO lt 0 O gt 3 5 2 Test mode data format During the test mode the pixel matrix is not connected to the multiplexing electronic In place of it two test levels V4TEST1 V1 VATESTO VO are available They emulate the readout shift from one column of pixel to the other column of pixel Actually these levels correspond to those of Marker 1 and Marker 0 They are adjustable via 2 DACs Even and odd columns amplifiers are alternatively connected to one of them The V1 and V1 levels are connected to the multiplexing electronic with a specific patter This pattern allows seeing the output signal changing Thus the test data stream has the following format March 2007 MimoStar3 User Manual 9 H Mimox3 Analogue output lt 1 gt format Sf9V1 Sf8V0 Sf7V1 Sf6VO Sf5V1 Sf9VO Sf8V1 Sf7VO Sf6V1 Sf5VO Sf9VO S f8V1 Sf7VO Sf6V1 Sf5VO Sf9V1 Sf8VO Sf7V1 Sf6VO Sf5VI1 Analogue output 0 format Sf4v0 Sf3V1 Sf2VO Sf1V1 SfOVO Sf4V1 Sf3VO Sf2V1 Sf1VO SfOV1 SfAV1 Sf3VO Sf2V1 Sf1VO SfOV1 Sf4V0 Sf3V1 Sf2VO Sf1V1 SfOVO 3 6 MimoStar3 Chronograms The following chronograms describe typical access to the chip Reset JTAG download sequence and then the readout This one starts with the initialisation phase followed by the suc
4. performed at any time by setting up the SYNC token again In addition some test features have been implemented in this version e 2 single ended voltage output buffers one per bank allows a simpler readout at low frequency The purpose is to verify coarse parameters like analogue baseline directly on the wafer with a probe card e An 8 bit ADC running at 100 kHz word allows some parameter measurements like voltage supplies and current consumption e Anembedded temperature probe provides its analogue output via 2 output pads 2 Control Interface The control interface of MimoStar3 complies with the Boundary Scan JTAG IEEE 1149 1 Rev 1999 standard It allows the access to the internal registers of the chip like the bias register and the readout mode selection register On Power On Reset an internal reset for the control interface is generated The finite state machine of the Test Access Port TAP of the controller enters in the Test Logic Reset state and the ID register is selected 2 1 JTAG Instruction Set The Instruction Register of the JTAG controller is loaded with the code of the desired operation to perform or with the code of the desired data register to access Instruction 5 Bit Codex Selected Register Notes EXTEST 01 BSR JTAG mandatory instruction HIGHZ 02 BYPASS JTAG optional instruction INTEST 03 BSR JTAG optional instruction CLAMP 04 BYPASS JTAG optional instruction SAMPLE PRELOAD 05 BSR JT AG mandatory
5. vdda gnd Bias Tests IFASTBUF IFASTINTBUF IAMP IREGAMP IPIX IKIMO vddaln Power Supplies 2 A AA Oe e a 220 XOF Ass AA A i ccc APSO O02 520028 20 CMOS Signals viva e D II EZPOOP vy i LVDS Signals sss xxo NNT RY S 3 x oo US cux0n Ba x Analogue Signals 2 ER S lt ER 2 gt gt MimoStar3 is very simple to operate e Power On Reset or Reset on RSTB pad e Setup of the chip It is performed with programmable registers accessed via an embedded slow control interface It consists to e Load the DACs which bias the analogue blocks March 2007 MimoStar3 User Manual 3 Mimo 3 e If necessary load the ReadOut Register with a specific configuration The default setup on power on reset allows a normal readout once the biases have been set e Readout of the chip e The chip is driven by a 50 MHz clock The readout starts when the input SYNC token has its falling signal sampled by the internal 5 MHz clock It happens at the first falling edge of the internal clock which follows the SYNC falling edge e Readout synchronisation is achieved by the digital marker MxFirst which becomes active when the analogue signal of the first pixel appears e Other digital makers are available for the control of the readout process e Pixels are sequentially read out in a specific order explained later in the document e Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be
6. 0 Sf4Vl ne VAN SN TIRE RER RER s 3v1 sf1vl sf4v s 2vi Sf0V1 Sim AoutP lt 1 gt sn F S9V1 S 7V1 Sf5V1 Sf8V1 Sf6MV1 SE E EE 58m 1 l L 4 gu du 4 2u s 8vo st6vo st9v0 s 7vo T 180 1 80 RES See Initialisation phase Repeated pattern KE ag FE 1 1 J 4 7u 4 Bu 4 9u e E ee 3 6 3 Main Signal Specifications Parameter Typical Value INIT RSTB Pulse Width gt l US Active Low Asynchronous Power on Reset TCK Frequency 10 MHz Boundary Scan Clock JTAG e D E EES ee edge on irst CKRD amplis Se ee ra SE Ke with Zioad 2 100 Ohm and 2 5pF Pod Output Current Range 2 2 2 2 mA Note 1 The differential current output buffer can be modelled as an ideal current source Its performances in terms of raising and falling times are limited by its load s time constant Rjoag x Cioad Note 2 Simple source follower 3 7 ADC 3 7 4 ADC_SEL register Bit Selected signal for the measure 19 DAC V4FASTBUF1 18 DAC V4FASTBUFO 17 DAC V4REG9 16 DAC V4REG8 15 DAC V4REG7 14 DAC V4REG6 13 DAC V4REG5 12 DAC V4REG4 11 DAC V4REG3 10 DAC V4REG2 9 DAC V4REG1 8 DAC V4REGO 7 DAC VTESTI March 2007 MimoStar3 User Manual 13 Mimo 3 6 DAC VTESTO 2 VDDA chip Supply 4 VDDA IN Pad 3 VDDD Chip supply 2 VDDD IN Pad 1 VMUX lt 1 gt
7. 255 pA I4INTBUF 64 100 100 100 HA 1 pA From 0 up to 255 pA V4BUF1 0 5C 92 92 0 92 V 10 mV From 0 up to 2 55 V I4BUF 28 40 40 40unA lpA JjFromO0 up to 255 uA Note 1 The HRES polysilicon used in the bias block is missing for this submission Experimental values correspond to the recalculated parameters that allow nevertheless the chip be operated A new submission of the chip is in progress March 2007 MimoStar3 User Manual 7 Mimo 3 Bias synthetic block diagram o m 14PIX I4TNTBUF V4REG i V4BUF 1 i I4BUF n 0 1 2 9 for 10 sub matrices m 0 1for 2 output buffers V4TEST1 V4TESTO vv Notel Vrefn V4REGn 1V 3 3 Setting the Readout_Mode Register If the desired operating mode does not correspond to the default one set the Readout_Mode register following the 2 2 6 3 4 Readout 3 4 1 Signal protocol Ones JTAG registers have been loaded the readout of MimoStar3 may initiate with the following signal protocol e The readout clock is started This allows the CK10M output pad to generate a 10 MHz clock This clock follows the input clock with a 1 10 ratio if the 100 MHz is selected e The SYNC signal is set e The readout starts at the first rising edge of CK10M of after SYNC signal disappears e Signal markers allow the readout monitoring and the analogue data sampling o RstMk maker confirms the internal reset of the readout logic o SSync marker shows that the readout starts o 4 ext
8. 8Px lt 318 62 gt S 7PxX lt 318 63 gt SF6Px lt 318 62 gt SF5Px lt 318 62 gt Sf9Px 318 0 gt SF8Px lt 318 0 5 Sf7Px 318 O gt Sf6Px lt 318 0 gt SF5Px lt 318 O0 Sf9Mk1 r S 8Mk1 p Sie THIS dE r S 6Mk1 e Sie Sta 7 S 9MkO r S 8MkO r S t 7MkO S 6MkO S 5MkO europee 0 632 Sr8P2 lt U 632 9 79 0 G63 9c o0P 0 63 gt Sr5Px lt 0 635 europe 0 62 gt Sr8P2 lt 0 62 gt Sr7Px lt 0 632 Sr6RP2 lt 0 62 gt Sr5Px lt 0 625 GE O O0 9t8 0 OF SEIRx lt 0 OF SEHOPx lt O 0 gt SiP WS For bank the format on the analogue output lt 0 gt is SfAMk1 S 3Mk1 S 2Mk1 S 1Mk1 S 0Mk1 S 4Mk0 pono Mia S 2Mk0O S 1MkO S 0MkO 5 Eee iG GIE SESS 19 63 gt Suc 2E rS LO OSS Sic Mese dL 9 OSS Si OPR lt 319 65325 SiEMIPsec 3G EE 9 62 gt Sut 2I se 1L 9 OSS Iib Mg See SS 62 gt Su S519 62 gt EE E Wl SE Ee E OF BEE LE Wi El Ee E OF ScO0Px lt 3i9 OS Sf4Mk1 r S 3Mk1 r S 2Mk1 r Sf1Mk1 r SfOMk1 Sf4MkO Sf3MkO r S 2Mk0 r S 1MkO r SfOMKO Sf4Px lt 318 63 gt SF3Px lt 318 63 gt Sf2Px lt 318 63 gt SfF1Px lt 318 63 gt SF0PX lt 318 63 gt Sf4Px lt 318 62 gt Sf3Px lt 318 62 gt Sf2Px lt 318 63 gt Sf1Px lt 318 62 gt S OPx lt 318 62 gt Sf4Px lt 318 0 gt Sf3Px lt 318 0 gt Sf2Px lt 318 0 gt Sf1Px lt 318 0 gt Sf0Px lt 318 0 gt Sf4Mk1 S 3Mk1 S 2Mk1 S 1Mk1 S 0Mk1 F Sf4MkO S 3MkO r S 2MkO S 1MkO S 0MkO 5
9. B active low signal All BIAS registers are set to the default value i e 0 DIS COL is set to 0 i e all columns are selected RO Mode is set to 0 JTAG state machine is in the Test Logic Reset state JTAG ID CODE instruction is selected Then the bias register has to be loaded The same for the RO MODEO and DIS COL registers if the running conditions differ from defaults Finally the readout can be performed either in normal mode or in test mode 3 2 Biasing MimoStar3 The BIAS DAC register has to be loaded before operating MimoStar3 The 20 DACs constituting this register are built with the same 8 bits DAC current generator which has a 1 HA resolution Specific interfaces like current mirror for current sourcing or sinking and resistors for voltages customise each bias output The following table shows the downloaded codes which set the nominal bias Internal Simulation Resol Range Experimental 1 DAC Code DacInternal Output ution Codes Codey Name Codex current uA value IKIMO 64 100 100 IN 10 mV From 0 up to 2 55 V I4PIX 1E 30 30 30uA luA From 0 up to 255 HA VATEST1 C3 195 195 1 95 V 10 mV From 0 up to 2 55 V V4TESTO B9 185 185 1 85 V 10 mV From 0 up to 2 55 V V4REG 9 0 23 35 35 2 95 V 10 mV From 3 3 down to 0 75 V I4REG1 21 33 33 33 HA luA From0 up to 255 yA I4AMP 64 100 100 100 HA 1 pA From 0 up to
10. Output buffer supply VDD3OP Output buffer supply IQ DIN nu Ie RS ID o nis D O 00 1 pot ring segment E Pad Name Pad General Function PadType Function for the chip CKRN LVDS In Full Custom Readout Clock Signal CKRP LVDS In 96 CKRP pb Simple metal for probing Full Custom Analogue Pad Supply AVDDALLP Supply periphery amp core 98 vddd Analogue Pad Supply AVDDALLP Supply periphery amp core March 2007 MimoStar3 User Manual 17 Mimo 3 Pad ring segment P D2 Pad Name Pad General Function PadType Function for the chip 99 vddd Core logic and periphery cells supply VDD3RP Digital supply periphery amp core Digital supply periphery amp core Digital supply periphery amp core Digital supply periphery amp core Digital supply periphery amp core Digital supply periphery amp core Probing Probing Pad Tam Pad General Function PadType Function for the chip 140 AoutON pb Simple metal for probing Ju Custom March 2007 MimoStar3 User Manual 18 Mimo 3 Analogue Pad Supply AVDDALLP Supply periphery amp core Analogue Pad Supply AVDDALLP Supply periphery amp core Analogue Pad Supply AVDDALLP Supply periphery amp core Analogue Pad Supply AVDDALLP Supply periphery amp core Analogue Pad Supply AVDDALLP Supply periphery amp core 171 vdda Analogue Pad Supply AVDDALLP Supply periphery amp core A
11. Pad 0 VMUX lt 0 gt Pad March 2007 MimoStar3 User Manual 14 Mimo 3 4 PadRing The pad ring of the chip is build with e Pads full custom designed for some of the analogue signals and power supplies e Pads from the AMS library for the digital signals and power supplies The pad ring is split in 7 functional independent parts e Readoutanalogue output lt 1 gt amp analogue supplies CMOS JTAG amp digital supplies LVDS read out drivers Digital read out control amp digital supplies Read out analogue output lt 0 gt amp analogue supplies Test ADC input signals Test ADC control signals amp supplies 4 1 MimoStar3 Pad Ring and Floor Plan View RdO Cntl Hi OE n I I bat y E Bei TOFI i TEL y L T HE 1 f i H IOC H A E attt RER EET EE EH TTETTR EH SIEHE ETE HEEL ibt iR RETE LE TU EEG ELEC HEEL AHA HELENE EEE EE HD LT ER KE E amaaa ry 1 P A1 PDI PL P D2 P_A2 PAdci 187 PAdc2 Foundry submission information Mimostar3 has been designed in AMS C35B401 CMOS 0 35 um epitaxial and opto process with 2 poly and 4 metal layers The Process Design Kit V3 70 has been provided by CMP CAD tools are CADENCE DFII 5 0 with DIVA and ASSURA rules The chip has been submitted in an engineering run via CMP the June 2006 4 2 Pad List March 2007 MimoStar3 User Manual 15 Mimo 3 Pad ring segment 1 P A1 Pad Name Pad General Function PadType Function for the chip 1 gnd Core logi
12. S 2M1 S 1M1 S 0M1 Sf3Px lt 318 63 gt _ S 4Px lt 318 63 gt S COUCHE UE Er CU 3 3 EU 0 EA HEI CET sf5px lt 319 0 gt S 4M0 S 3M0 S 2M0 S 1M0 Sf0M0 s 8px lt 318 63 gt S 9Px lt 318 63 gt time s S 5Px lt 319 0 gt S 9M1 S 8M1 S 7M1 S 6M1 S 5M1 End of 1 st row readout 2 d row readout March 2007 MimoStar3 User Manual 11 Mimo 3 Figure 3 CkRdLp F UJ Ck18ME Syne 1 1 1 fi L 1 1 RstMk L L L L L L SSync i 1 1 1 1 1 L MxFirst i 1 1 f L L bi ett LATTE L L aaa daa rar beans d 1 L 1 LastRowr aia dd EE ES Maca ua dota laagadadds Letia rei etine aae d r L f f Sf4M1 EN S 2M1 Bree apne S f4M0 S 3M0 S 2M0 S 1MO S OMO tP lt B gt Sf1Px lt 0 0 gt Sf0Px lt 0 p S 3Px lt 319 63 S 2Px lt 319 63 gt 300m Aou A ERU uuum eec uu P nmi m m 250m i 4 L LastCol 1 L L 1 J 30 0u 34 1u ER 2u ER 3u 38 4u 38 Du 34 6u l 34 7u 34 8u 34 9u 31 8u time s 1 End of last row readout Next Frame 1 S row readout Figure 4
13. c and periphery cells supply AGNDALLP Ground periphery amp core IFASTBUF Analog I O pad 0 Q serial APRIOP DAC Out Test Purpose Only 6 IFASTINBUF Analog I O pad 0 Q serial APRIOP DAC Out Test Purpose Only IAMP Analog I O pad 0 Q serial APRIOP DAC Out Test Purpose Only 8 IREGAMP Analog I O pad 0 Q serial APRIOP DAC Out Test Purpose Only 9 IPIX Analog I O pad 0 Q serial APRIOP DAC Out Test Purpose Only 11 ITEST Analog I O pad 0 Q serial APRIOP Internal Current Ref Source 46 AoutiP pb Simple metal for probing J Custom O March 2007 MimoStar3 User Manual 16 Mimo 3 Analogue Pad Supply AGNDALLP Ground periphery amp core Analogue Pad Supply AGNDALLP Ground periphery amp core Analogue Pad Supply AGNDALLP Ground periphery amp core vddd Core logic and periphery cells supply VDD3RP Digital supply periphery amp core dja Q Q c Digital supply periphery amp core ON US lt vddd_ Output buffer supply VDD3OP jOutputbuffersupply 67 lt Qa c c Simple metal for probing 80 TDO TriStateOutputBuffer 4 mA SD JTAGSerilDataOu S gnd Core logic and periphery cells gnd GND3RP Digital ground periphery amp core S9 gnd Core logic and periphery cells gnd GND3RP Digital ground periphery amp core 90 gnd Core logic and periphery cells gnd__ GND3RP_ Digital ground periphery amp core
14. cessive row readouts as showed in the zoom 3 6 1 Normal Readout Figure 1 show the beginning of a typical normal data readout mode After Reset and JTAG settings one can see the initialisation phase of the readout of the first pixel row The LastCol signal is active meanwhile the last pixel of a row is read The last row of the frame makes the LastRow signal to be active The 2 serial analogue outputs are showed One can distinguish the 2 makers placed at the beginning of each row 3 6 1 4 Readout synchronisation The simplest way to get a readout synchronisation on the analogue data is to use the MxFirst signal in First Pixel of Frame mode which becomes active when the first pixel is ready on the analogue output It makes the data acquisition independent of the latency which exists between the start of the readout Sync and the appearance of the data Nevertheless if it is impossible for the user to use MxfFirst the synchronisation on the analogue data is possible by counting the number of the CK10M cycles The latency between the Sync signal falling edge and the rising edge of the MxFirst signal is Latency Ck10Count 1 modulo 2 6 Where e Latency is given in CK10M cycles It begins at the first Ck10M rising edge which follows the Sync falling edge e CklOCount is the value of a CK10M counter at the falling edge of SYNC Cursor Baseline 600ns Name v am ckinL im Sync Baseline 1712ns TimeA 1112ns Cur
15. e 7 SelltagCk Select TCK as the ADC clock in place of the O Ext CKADC selected external CKADC signal aM 6 SelFull Set the row shift register to 640 in place of 320 0 Normal mode 320 row shift bits This option is designed to emulate a 640 x register selected 640 pixel matrix 5 DisLVDS Disable LVDS readout clock is not active 0 LVDS selected anymore 4 SelMux On MxFirst output select MuxFirst signal or 1 MuxFirst Signal active First Pixel of First Frame signal __ See 3 4 Readout 3 EnaGain3 Select gain 3 for the serial differential output 0 Gain 5 buffer 2 Not used 1 BufCopy 0 EnaTstCol Test Mode Select the 2 Test Levels IVTEST1 0 Normal mode and IVTESTO which emulate a pixel output 2 2 7 BIAS DAC Register The BIAS_DAC register is 160 bits large it sets simultaneously the 20 DAC registers As show bellow these 8 bit DACs set voltage and current biases After reset the register is set to 0 a value which fixes the minimum power consumption of the circuit The current values of the DACs are read while the new values are downloaded during the access to the register The image of the value of some critical biases can be measured on corresponding test pads Bit DACH DAC Internal DAC purpose Corresponding range Name Test Pad 159 152 DACI9 IKIMO External circuit monitoring IKIMO 151 144 DACIS8 I4PIX Pixel source follower bias DAC w
16. e NUI NUIO 0 Not implemented For future use 2 2 1 Instruction Register The Instruction register is a part of the Test Access Port Controller defined by the IEEE 1149 1 standard The Instruction register of MimoStar2 is 5 bits long On reset it is set with the ID_CODE instruction When it is read the 2 last significant bits are set with the markers specified by the standard the remaining bits contain the current instruction X X X 1 0 2 2 2 Bypass Register The Bypass register consists of a single bit scan register It is selected when its code is loaded in the Instruction register during some actions on the BSR and when the Instruction register contains an undefined instruction 2 2 3 Boundary Scan Register The Boundary Scan Register according with the JTAG instructions tests and set the IO pads The MimoStar3 BSR is 11 bits long and allows the test of the following input and output pads Bit Corresponding Pad Type Signal Notes 10 LVDS CkRdP CkRdN __ Input CkRd Resulting CMOS signal after LVDS Receiver 9 ASync Input Sync 8 CkADC Input CkADC 7 StartADC Input StarADC 6 SSync Output SSync 5 Ck5M Output Ck5M 4 Ck10M Output Ck10M 3 RstMk Output RstMk 2 LastRow Output LastRow 1 LastCol Output LastCol 0 MxFirst Output MxFirst 2 2 4 ID CODE Register The Device Iden
17. e first maker This option is set via the RoMode register RstB Teki CkRdLp Ck19M Syne RstMk SSync MxFirst LastCol LastRow 300m AoutP lt a gt zr I gt l 25 m I 300m 0 Aout lt 1 gt m I 250m 6 9 3 8 Ou 16u 32u Reset idle lime s i i Jtag access Init 1 strow readout Successive row readouts Last row readout Figure 1 I TCK fi fi fi L fi i 1 fi j l rate EU UUUUUUUUUUUUUUUUUUUUUUU UUU UUUUUUUUUUUU UUU UUUUUUUUUUYUUUUUUUU UU UUU UUU UUU UCD DUU DCD ciae ELT 7 n 7 a x F m E m F ER henri ed ast patte 1 l 1 1 RatMk E Bee l i l SSyne t 1 aaa daa as 1 L MxFirst LastCol LastRow se4px lt 319 63 gt S 3Px lt 319 63 gt Sf3Px lt 319 63 gt 35m AoutP lt gt S 4M1 S 3M1 S 2M1 S 1M1 gt 456m i S 4M0 3M0 8 2M0 S 1MO i i stopx lt 319 63 gt Sf8Px lt 319 63 gt Sf7Px lt 319 63 gt 35 m A Aout lt 1 gt S 9M1 Sf8M1 Sf7M1 sfe6M1 brsMi a SCH S 9M0 Sf 8M0 S 7M0 Sf6M0 456m fi i L 1 1 3 2u 3 4u 3 Bu 3 8u 4 gu 42u 4 4u 4 6u 4 Bu 5 8 time si Initialisation phase 1 row readout phase Figure 2 SFOPx lt 319 0 gt sf4mi pe
18. ight side Each row contains 2 makers acting as dummy pixels and 64 active pixels One can use the adjustable level of the 2 markers as a pattern recogniser If the pixel coordinate format is specified as Px Line Column then for each subframe the upper left pixel is Px 319 63 gt while the lower right is Px 0 0 and the markers of each beginning row are named Mk1 and MKO The 10 subframes are themselves gathered in 2 banks The two banks are readout in parallel each one has its own analogue serial output Thus in each bank the readout consists to access successively one pixel of each of the 5 subframes and then turning back to the first subframe in order to read its next pixel For Mimostar3 the left hand side subframe is named Sf9 and the right hand side is Sf0 Thus the normal data stream format for the bank1 on the analogue output lt 1 gt is Sf9Mk1 r S 8Mk1 ore r S 6Mk1 5 Sie Sr IL B S 9MkO S 8MkO e SE TNO r S 6MkO 7 Sie S0 5 Stt 99s SL 9 63S EE DE 635 E MSSL 63 gt iSc ole 3 9 GS gt ISTE SIEX S 9 63 gt Stt Ei 3L 9 62 gt STARSI LI 62 gt Sit d Ee E 63 gt Itt oleo 3L 9 62 STE 3IES S1 9 62 gt Su SESI9 OS STRESS OS SrVEx lt sil S Q S89 685319 0 S9 75b5 519 OS Sf9Mk1 r S 8Mk1 Sf 7Mk1 Sf6Mk1 r Sf5Mk1 Sf9MkO r S 8MkO r S 7MkO S 6MkO r S 5MkO Sf9Px lt 318 63 gt Sf8Px lt 318 63 gt Sf7Px lt 318 63 gt Sf6Px lt 318 63 gt Sf5Px lt 318 63 gt S 9Px lt 318 62 gt S
19. instruction ID CODE OE ID register JTAG optional instruction BIAS_GEN OF BIAS register User instruction DIS_COL 10 Disable Columns User instruction ADC_SEL 11 AnalogIn Select reg User instruction ADC ROR 12 ReadOut Register User instruction NUI 13 Reserved Not Used NU2 14 Reserved Not Used NU3 15 Reserved Not Used NUA 16 Reserved Not Used NUS 17 Reserved Not Used NU6 18 Reserved Not Used NU7 19 Reserved Not Used NUS 1A Reserved Not Used NU9 1B Reserved Not Used NU10 1C Reserved Not Used RO MODEI 1D Read Out Model User instruction RO MODEO 1E Read Out Mode0 User instruction BYPASS 1F BYPASS JTAG mandatory instruction March 2007 MimoStar3 User Manual 4 Mimo 3 2 2 JTAG Register Set JT AG registers are implemented with a Capture Shift register and an Update register JTAG standard imposes that the last significant bit of a register is downloaded shifted first Register Name Size Access Notes INSTRUCTION REG 5 R W Instruction Register BYPASS 1 R Only BSR 11 R W ID_CODE 32 R Only Pattern fixed at OXFFFF0001 BIAS GEN 20 DACs 160 R W Previous value shifted out during write DIS COL 640 R W Previous value shifted out during write ADC SEL 20 R W Previous value shifted out during write ADC ROR 11 R Only Previous ADC value shifted RO MODEI 8 R W Previous value shifted out during write RO MODEO 8 R W Previous value shifted out during writ
20. ith IPIX positive slope 0 to 255 uA 1 uA step 143 136 DACI7 V4TESTI Test Level emulates a pixel output DAC No pad with positive slope 0 to 2 55V 10 mV step Markerl 135 128 DACI6 VATESTO IDEM Marker0 No pad 127 120 DACI5 V4REG9 Regulator voltage bias for the column No pad amplifier Gain 3 amp 5 DAC with negative slope 3 3 to 0 75 V by step of 10 mV 119 112 DACI4 V4REG8 Idem No pad 111 104 DACI3 V4REG7 Idem No pad 103 96 DACI2 V4REG6 Idem No pad 95 88 DACII V4REGS Idem No pad March 2007 MimoStar3 User Manual 6 Mimo 3 87 80 DACIO V4REG4 Idem No pad 79 72 DACH VAREG3 Idem No pad 71 64 DAC8 V4REG2 Idem No pad 63 56 DAC7 VAREGI Idem No pad 55 48 DAC6 V4REGO Idem No pad 47 40 DAC5 I4REG1 Idem IREGAMP 39 32 DAC4 I4AMP Bias of column amplifier DAC with IAMP positive slope 0 to 255 uA 1 uA step 31 24 DAC3 I4INTBUF Bias of the Intermediate Buffer DAC with IFASTINTBUF positive slope 0 to 255 uA 1 uA step 23 16 DAC2 V4BUFI Bias of the differential current Output No pad Buffer DAC with positive slope 0 to 2 55 V by step of 10 mV 15 8 DACI V4BUFO Idem No pad 7 0 DACO I4BUF Bias of the two differential current output IFASTBUF buffers DAC with positive slope 0 to 255 uA 1 uA step 3 Running MimoStar3 The following steps describe how to operate Mimostar3 3 1 After reset On RST
21. nalogue Pad Supply AVDDALLP Supply periphery amp core Analogue Pad Supply AVDDALLP Supply periphery amp core Pad Name Pad General Function I76 vddain DIRECTPAD ADCinut 177 vdddim DIRECTPAD ADCinut 178 VMUXin1 DIRECTPAD ADCipu i IRECTPAD ADC input ISI WpADC DIRECTPAD ADCinpt O gnd ADC supply StartADC 186 March 2007 MimoStar3 User Manual 19
22. ra CK10M clock cycles after SYNC sampling are necessary before the first pixel analogue signal appears on the selected output s o The MxFirst digital signal helps for a better sampling of the analogue output signals The way it acts is set by the RO Mode 4 bit RO Mode 4 0 MxFirst is active only on the first pixel oft the frame RO Mode 4 1 MxFirst is active on each pixel change on the parallel analogue output i e itis a10 MHz periodic signal Used with the 100 MHz serial mode see serial data format bellow its period shows when one pixel index has been read in all the subframes 2 real 8 virtual o LastCol is active when the last column of the current row is selected o LastRow is active when the last row of the frame is selected 3 4 2 Successive frames and resynchronisation Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be performed at any time by setting up the SYNC token again 3 5 Analogue Data Format Two types of signal can be generated on the serial analogue outputs e Normal pixel signal e Test signal March 2007 MimoStar3 User Manual 8 Mimo 3 3 5 1 Normal mode data format In order to improve the readout speed Mimostar3 is organized in subframes i e 10 subframes for this prototype During the readout the 10 subframes are accessed in parallel For each subframe the addressing is done row by row each pixel is accessed sequentially from the left side to r
23. sor 400ns 800ns 1200ns 1600ns 2000ns y y ry 6 clock cycles of latency Baseline 1212ns Cursor Baseline 700ns a TimeA 1912ns Name Cursor 400ns 800ns 1200ns 1600ns 2000ns 2400ns Ei pf ckinL ll j r Nl r I f f I cB Sync BB CKIO Lm MxFirst CK10Counter 1 i j2 GHG ye p y 9 oa Aa ji ji 19 20 j21 22 23 IG Yes e Tei 17312 I3 1 715 7165 ET 10 E Es Els Latency 7 clock cycles of latency Figure 2 zoom on the readout start After a latency of 6 or 7 CK10M cycles Mxfirst goes active and the analogue signal generated in respect with the serial format Figure 3 zoom on the transition between 2 consecutive rows of the same frame The markers are clearly showed Figure 4 shows the end of the last row readout followed by the first row of the next frame March 2007 MimoStar3 User Manual 10 Mimo 3 Figure 5 show the alternate option of the MxFirst signal It is permanently running being active high on th
24. st Mode readout isisisi nn eus need 12 3 6 3 KEE e 13 3 7 ADC eebe 13 3 7 1 ADC SEL register E 13 IUE SD m 15 4 1 MimoStar3 Pad Ring and Floor Plan View 15 4 2 Jas PRECES 15 March 2007 MimoStar3 User Manual 2 Mimo 3 1 Introduction Mimostar3 the third version of the MimoStar family has been designed in C35B401 the AMS 0 35 um opto process Like MimoStar 1 and 2 it is a Monolithic Active Pixel Sensor prototype dedicated to vertex particle tracking in a future update of the STAR vertex detector The matrix is composed by 320 x 640 pixels of 30 um pitch and based on self biased diode architectures It is organised in 10 matrices or subframes of 320 lines x 64 columns accessed in parallel during the readout The individual pixel architecture should meet the radiation tolerance and the low leakage current requirements Actually Mimostar3 prototype has the half size of the final circuit which is foreseen with 640 lines The addressing of each subframe is sequential and starts from the upper left pixel up to the lower right pixel The beginning of each subframe row is stamped by 2 pixels acting as makers and having programmable levels The 10 subframes are gathered in 2 banks Each bank has its own analogue serial output a differential current output buffer running up to 50 MHz allowing a readout time of 2 ms frame Digital ADC Analog Supplies Supplies Supplies gnd vdd Vdd_ADC gnd Vdd_diode
25. tification register is implemented is this third version It is 32 bits long and has fixed value hardwired into the chip When selected by the ID CODE instruction or after the fixed value is shifted via TDO the JTAG serial output of the chip Mimostar3 ID CODE register value is OXFFFF0001 March 2007 MimoStar3 User Manual 5 Mimo 3 2 2 5 DIS COL Register The DIS COL register is 640 bit wide The purpose of this register is to disable the column current sources if a short circuit is suspected on a specific column During the readout even if a current source is disabled the corresponding column is selected i e no columns are skipped Obviously the signal of the corresponding pixel has not signification The default value of the DIS COL register is 0 it means that all current sources can be activated by the readout logic Setting a bit to 1 disables the corresponding current source In MimoStar2 the column lt 639 gt is on the left hand side while column 0 is on the right hand side The organisation of the chip in 10 subframes of 64 columns has no matter to do with the DIS COL register 640 Msb 0 Lsb DisCol lt 639 gt DisCol lt 0 gt 2 2 6 RO Mode RegisterO The RO Mode registers are 8 bits large they allow the user to select specific features of the chip MimoStar3 only use RO Mode RegisterO Bit Bit Name Purpose Default valu
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