Notification of correction for Incorrect Description and Extended
Contents
1. l l T je e je 2 2 e e je 2 2 2 2 e j2 e 2 j2 2 2 c 2014 Renesas Electronics Corporation All rights reserved Page 3 of 17 sC NEZ S AE RENESAS TECHNICAL UPDATE TN RL A028A E Date July 1 2014 Correct Table 4 4 PMxx Pxx PUxx PIMxx POMxx PMCxx registers and the bits mounted on each product 1 2 PMxx PUxx PIMxx POMxx PMCxx ne TA o a pmo Puoo PIMoo PPro E PMO02 PU02 _ POM0O2 PMCO02 S as oe T ds oo r ra eos poa puos Tona Tau speet e ms PT PM06 PU06 carro emo re eu pane pone ri Penis en eun em row wert ra ewe er ru romz Puei rs ews prs eus rows wets e eme pre pure emis paz fofo eo ri Pew ee ra ewe re rs ewes es ra ewes ree rs ewes ms re pues rs rr ewer ee l l L2 je 2 2 2 eT l l e lt j 2 je 2 2 fel ee eee EE 2 je e je 2 je 2 2 j2 2 2 2 j2 2 2 2 2 j2 2 c 2014 Renesas Electronics Corporation All rights reserved Page 4 of 17 sC NEZ S AE RENESAS TECHNICAL UPDATE TN RL A028A E 2 5 3 9 High speed on chip oscillator trimming register HIOTRM Incorrect 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 10 Format of High Speed On Chip Oscil2. 15 of 17 sC NEZ S AE RENESAS TECHNICAL UPDATE TN RL A028A E 7 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Old 29 7 Data Memon TOP Mode Low only Voltage Data Retention Characteristics Ta 40 to 85 C Vss 0 V Symbol Data retention supply VDDDR 1 46 3 6 voltage Note The value depends on the POR de ion voltage When the voltage drop data is retained before a POR reset is effected but data is not retained when a POR reset is effected N STOP mode r a Operation mode Data retention mode _ gt STOP instruction execution T Standby release signal interrupt request c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Date July 1 2014 New 29 7 RAM Data Retention Characteristics Ta 40 to 85 C Vss 0 V Data retention supply Voppr 1 46 3 6 V voltage Note This depends on the POR detection voltage For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated STOP mode j Operation mode STOP instruction execution Standby release signal interrupt request oo Page 16 of 17 RENESAS TECHNICAL UPDATE TN RL A028A E 8 30 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Old 0 7 Data Memory STOP Mode Low only V
3. Circuit Incorrect descriptions revised Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit p and Voltage Detector 1 3 29 6 1 A D converter characteristics 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics l 30 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics p Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware c 2014 Renesas Electronics Corporation All rights reserved Page 1 of 17 stEN ESAS RENESAS TECHNICAL UPDATE TN RL A028A E Date July 1 2014 Corrections in the User s Manual Hardware No Corrections and Applicable Items Pages in this document English RO1UH0305EJ0200 for corrections 4 3 Registers Controlling Port Function Page 3 and Page 4 p 5 3 9 High speed on chip oscillator trimming register HIOTRM p 157 Page 5 12 5 7 SNOOZE mode function p 495 p 497 Page 6 and 7 12 6 3 SNOOZE mode function p 522 12 6 3 SNOOZE mode function 16 4 3 Multiple interrupt servicing Table 16 5 Relationship Between Interrupt 710 Pade 12 Requests Enabled for Multiple Interrupt Servicing P g During Interrupt Servicing 20 2 Configuration of Power on reset Circuit Figure 20 2 Timing of Generation of Internal N Reset Signal by Power on reset Circuit pero Pade and Voltage Detector 1 3 8 29 6 1 A D converter characteristics p 896 Page 14 and 15 29 7 Data Memory STOP Mo
4. Clock request signal internal signal SDROO a oe po PUL F E Receive data 2 AEN Receive data 1 TT _ t ETE Shift H register 00 S Feoeption Rai operation es ee ee ran S T 9 Data reception Data reception lt 2 gt lt 5 gt lt 6 gt lt 7 gt lt 2 gt lt 5 gt lt 6 gt omitted Page 7 of 17 RENESAS TECHNICAL UPDATE TN RL A028A E 3 12 6 3 Attention added of SNOOZE mode function 12 6 3 SNOOZE mode function Incorrect 12 6 3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode However using the SNOOZE mode enables the UART to perform reception Normally the UART stops communication in the STOP mode operations without CPU operation omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fix is selected for fcLk omitted 4 If a parity error framing error or overrun error occurs while the SSECm bit is set to 1 the PEFmn FEFmn or OVFmn flag is not set and an error interrupt INTSREq is not generated Therefore when the setting of SSECm 1 is made clear the PEFmn FEFmn or OVFmn flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDq register of the SDRm1 register c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Date July 1 2014 Correct 12 6 3 SNOOZE mode function The SNOOZ
5. of the HIOTRM register see the application note for RL78 MCU series High speed On chip Oscillator HOCO Clock Frequency Correction RO1AN0464 Page 5 of 17 RENESAS TECHNICAL UPDATE TN RL A028A E Date July 1 2014 3 12 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation It is correction of Clock request signal internal signal and TSF00 in this Figure Correct Incorrect 1 SNOOZE mode operation once startup 1 SNOOZE mode operation once startup Figure 12 70 Timing Chart of SNOOZE Mode Operation Once Startup Type 1 DAPmn 0 CKPmn 0 DAPmn 0 CKPmn 0 CPU operation status Normal operation _ Normal operation STOP mode SNOOZE mode CPU operation status Normal operation STOP mode SNOOZE mods SNe operation Is E lt 4 gt SS00 lt 3 gt lt 3 gt ss00 lt lt n gt eS a _ STOO lt 1 gt L SE00 SEOO Po ioe swo r nl SSECO L Clock request signal internal signal Figure 12 70 Timing Chart of SNOOZE Mode Operation Once Startup Type 1 Receive data 2 Receive data 1 l Clock request signal internal signal i SDROO S L Receive data 2 lote gt gt rer a i SDROO Receive data 2 a Pee icc nee oo ny Aa ee SCKOO pin f r S100 pin L Receivedatat l S SI00 pin Reccwedaa i Y Receive data2 Shift L L i L scone dala geo 8 Roasfon anit operon Xi H H register 00 K_Fiegception amp shit operati
6. 19 ms max when the LVD is off Reset processing time whe 2 external reset is released after the second release of POR is shown below After th ond rel f POR 0 531 ms typ 0 675 ms max when the LVD is in use 0 259 ms typ 0 362 ms max when the LVD is off omitted c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Date July 1 2014 Correct Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 3 1 When the externally input reset signal on the RESET pin is used Notes 3 omitted The time until normal operation starts includes the following reset processing time when the external reset is released release from the first external reset following release from the POR state after the RESET signal is driven high 1 as well as the voltage stabilization wait time after VPOR 1 51 V typ is reached Reset processing time when the external reset is released is shown below Release from the first external reset following release from the POR state 0 672 ms typ 0 832 ms max when the LVD is in use 0 399 ms typ 0 519 ms max when the LVD is off Reset times in cases of release from an external reset other than the above are listed below Release from the reset state for external resets other than the above case 0 531 ms typ 0 675 ms max when the LVD is in use 0 259 ms typ 0 362 ms m
7. Date July 1 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPumcu Document TN RL A028A E Rev 1 00 Category No Notification of correction for Incorrect Description and Title Extended Specification Information Technical Notification RL78 G1A Descriptions in the Hardware User s Manual Category Rev 2 00 Changed Lot No Applicable RL78 G1A tarn RL78 G1A User s Manual Hardware Product R5F10Exx D ete roquc All lots OcUMEN R01UH0305EJ0200 Jul 2013 This document describes misstatements found and Extended Specification in the RL78 G1A Users Manual Hardware Rev 2 00 RO1UHO0305EJ0200 Corrections Applicable Item Applicable Page 4 3 Registers Controlling Port Function Incorrect descriptions revised p 5 3 9 High speed on chip oscillator trimming register Incorrect descriptions revised HIOTRM p 12 5 7 SNOOZE mode function Incorrect descriptions revised Timing Chart of SNOOZE Mode Operation p 495 p 497 Figure12 70 12 72 12 6 3 SNOOZE mode function p 522 attention added 103 157 Timing Chart of SNOOZE Mode Operation p 524 p 525 p 527 Figure12 89 12 90 12 92 16 4 3 Multiple interrupt servicing Incorrect descriptions revised Table 16 5 Relationship Between Interrupt Requests 0 710 Enabled for Multiple Interrupt Servicing During Interrupt Servicing 20 2 Configuration of Power on reset
8. E mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode However using the SNOOZE mode enables the UART to perform reception Normally the UART stops communication in the STOP mode operations without CPU operation omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fix is selected for fcuk omitted 4 If a parity error framing error or overrun error occurs while the SSECm bit is set to 1 the PEFmn FEFmn or OVFmn flag is not set and an error interrupt INTSREq is not generated Therefore when the setting of SSECm 1 is made clear the PEFmn FEFmn or OVFmn flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDq register of the SDRm1 register 5 The CPU shifts from the STOP mode to the SNOOZE mode on detecting the valid edge of the RxDq signal Note however that transfer through the UART channel may not start and the CPU may remain in the SNOOZE mode if an input pulse on the RxDq pin is too short to be detected as a start bit In such cases data may not be received correctly and this may lead to a framing error or parity error in the next UART transfer Page 8 of 17 RENESAS TECHNICAL UPDATE TN RL A028A E 3 12 6 3 SNOOZE mode function Timing Chart of SNOOZE Mode Operation It is correction of Clock request signal internal signal in this Figure Incorrect Figure 12 89 Timing Chart o
9. P mode SNOOZE mode lt 4 gt n Abnormal rati lt 3 gt aA T ao Receive data y 7 r m ee Receive data 1 X P SP Bi Receive data 2 e o o S lt 2 gt lt 5 gt lt 6 gt lt T gt lt 5 gt lt 6 gt lt T gt lt 11 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Date July 1 2014 Correct Figure 12 92 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation CPU operation status Normal operation STOP mode lt 4 gt STOP mode Sso1 lt 3 gt ST01 lt 1 gt SE01 SWCO EOC01 SSECO Clock request signal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO L TSFO1 lt 2 gt lt 8 gt omitted Page 11 of 17 lt 7 gt lt 10 gt lt 11 gt RENESAS TECHNICAL UPDATE TN RL A028A E 4 16 4 3 Multiple interrupt servicing Table 16 5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Incorrect Table 16 5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Software Interrupt Multiple Interrupt Maskable Interrupt Request Priority Level 3 Request Request Priority Level O Priority Level 1 Priority Level 2 PR 00 PR 01 PR 10 PR 11 EO fen eoe een eo Interrupt Being Serviced Maskable inte
10. Renesas Electronics Corporation All rights reserved Page 14 of 17 sCENESAS RENESAS TECHNICAL UPDATE TN RL A028A E Date July 1 2014 New 1 When reference voltage AVrere ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target for conversion ANI2 to ANI12 Ta 40 to 85 C 2 4 V lt AVrerp lt AVpp lt Voo lt 3 6 V Vss 0 V AVss 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V HALT mode eon H H H HT T 9 CI T T H H TEH saare Te aore o zmr sae ids Differential linearity erroriaies 2 12 bit resolution 9 at2 LB Notes 1 TYP Value is the average value at AVpp AVrerp 3 V and Ta 25 C MAX value is the average value 30 at normalized distribution 2 These values are the results of characteristic evaluation and are not checked for shipment 3 Excludes quantization error 1 2 LSB Cautions 1 Route the wiring so that noise will not be superimposed on each power line and ground line and insert a capacitor to suppress noise In addition separate the reference voltage line of AVreFP from the other power lines to keep it free from the influences of noise 2 During A D conversion keep a pulse such as a digital signal that abruptly changes its level from being input to or output from the pins adjacent to the converter pins and P20 to P27 and P150 to P154 c 2014 Renesas Electronics Corporation All rights reserved Page
11. SSo1 lt 3 gt lt 12 gt ST01 lt 1 gt SE01 SWCO EOCO1 SSECO L Clock request signal internal signal Po Receive data 2 SDRO1 ee Oe Receive data 1 a Sra Real RxDO pin a Receive data1 A P SP Sl Receive data2 AP SP Shift S register 01 PY gn XY T A hit operation XX INTSRO as 5 fo S es ee TSFO1 lt 2 gt lt 5 gt lt 6 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Normal operation j Date July 1 2014 Correct Figure 12 90 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 CPU operation status SS01 ST01 SE01 SWCO EOCO1 SSECO Clock request signal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO TSF01 Normal operation STOP mod Normal operation Receive data 2 Receive data 1 a a Receive data 1 XP SP Receive data 2 P SP D 0 GS GS T T lt 2 gt lt 8 gt Data reception omitted Page 10 of 17 RENESAS TECHNICAL UPDATE TN RL A028A E It is correction of Clock request signal internal signal in this Figure Incorrect Figure 12 92 CPU operation status SSU ST01 SE01 SWCO EOCO1 SSECO Clock request signal intemal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO TSFO1 Timing Chart of SNOOZE M r n lt 2 gt Normal operation Normal operation STOP mode SNOOZE mode STO
12. ax when the LVD is off omitted Page 13 of 17 RENESAS TECHNICAL UPDATE TN RL A028A E Date July 1 2014 6 29 6 1 A D converter characteristics Voltage Range of A D conversion was extended Old 1 When reference voltage AVrere ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target for conversion ANI2 to ANI12 Ta 40 to 85 C 2 7 V lt AVrere lt AVop lt Von lt 3 6 V Vss 0 V AVss 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V HALT mode Reon o e H H HHT T CI a T H H THH comersontine few TH HHH Differential linearity erroriaies t 3 12 bit resolution 9 03 LB Notes 1 TYP Value is the average value at AVpp AVrerfP 3 V and Ta 25 C MAX value is the average value 30 at normalized distribution 2 These values are the results of characteristic evaluation and are not checked for shipment 3 Excludes quantization error 1 2 LSB Cautions 1 Route the wiring so that noise will not be superimposed on each power line and ground line and insert a capacitor to suppress noise In addition separate the reference voltage line of AVrere from the other power lines to keep it free from the influences of noise 2 During A D conversion keep a pulse such as a digital signal that abruptly changes its level from being input to or output from the pins adjacent to the converter pins and P20 to P27 and P150 to P154 c 2014
13. de Low Supply 9 Voltage Data Retention Characteristics poua Page 16 30 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics BS agent Bol with underline Correct Gray hatched Incorr Id Bold with underline New Gray hatched Revision History RL78 G1A User s Manual Hardware Rev 2 00 Notification of correction for Incorrect Description and Extended Specification Document Number TN RL A028A E July 1 2014 First edition issued No 1 to 10 in corrections This notice c 2014 Renesas Electronics Corporation All rights reserved Page 2 of 17 sC NEZ S AE RENESAS TECHNICAL UPDATE TN RL A028A E Date July 1 2014 Incorrect 1 4 3 Registers Controlling Port Function Table 4 4 PMxx Pxx PUxx PIMxx POMxx PMCxx registers and the bits mounted on each product 1 2 PMxx PUxx PIMxx POMxx PMCxx DEA san ko a S a a on Port 0 pmo Puoo PiMoo teeth ra ewe ro ruo rowoa won Tas poa puos Tona Pomos rs ews ros rus rs eos roe rus per of emo f ee eoo ane romo emm PM11 PU11 PIM11 POM11 OCORRE rs ews er eus rows aea e eme ee eus emis paz ofe eo Tae ee ra eee ee rs ewes ex ra ewes ree rs ewes es rs ens me rr ewer ee L lt e l l L je e 2 2 2
14. f SNOOZE Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation STOP mode SNOOZE mode Sso1 ST01 lt 1 gt SE01 SWCO EOCO1 L SSECO L Clock request signal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO L TSFO1 Normal operation ST Receive data2 XP SP a E lt 2 gt lt 5 gt lt 6 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Receive data 2 5 Receive data 1 x Date July 1 2014 Correct Figure 12 89 Timing Chart of SNOOZE Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation STOP mod SS01 ST01 lt 1 gt SE01 SWCO EOC01 L SSECO L Clock request signal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO L TSF01 Page 9 of 17 lt 4 gt lt 3 gt lt 12 gt lt 10 gt lt 1 9 gt A Read Note ST Receive data 1 P SP Nyy Shift operation Data reception lt 7 gt lt 2 gt lt 8 gt omitted Normal operation Receive data 1 Receive data 2 ST Receive data 2 P SP Shift operation X X Data reception RENESAS TECHNICAL UPDATE TN RL A028A E It is correction of Clock request signal internal signal in this Figure Incorrect Figure 12 90 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 CPU operation status Normal operation STOP mode SNOOZE mode 4 gt 4
15. lator Trimming Register HIOTRM Address FOOAQOH After reset undefined R W Symbol HIOTRM Ca HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator Minimum speed Minimum speed G S G G G la l a ee N The value after reset is the value adjusted at shipment Note Remarks 1 The HIOTRM_ register the high speed on chip illat lock ithin about 0 05 2 For the usage example of the HIOTRM register see the application note for RL78 MCU series High speed On chip Oscillator HOCO Clock Frequency Correction RO1AN0464 c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Date July 1 2014 Correct 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 10 Format of High Speed On Chip Oscillator Trimming Register HIOTRM undefined ote R W Address FOOAOH After reset Symbol HIOTRM VER HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator Minimum spesad Minimum spesad Stet t ttt ft a The value after reset is the value adjusted at shipment Note Remarks 1 The HIOTRM register holds a six bit value used to adjust the high speed on chip oscillator with an increment of 1 corresponding to an increase of frequency by about 0 05 2 For the usage example
16. oltage Data Retention Characteristi Ta 40 to 105 C Vss 0 V Data retention supply VDDDR 1 44 3 6 V voltage Date July 1 2014 New 30 7 RAM Data Retention Characteristics Ta 40 to 105 C Vss 0 V Data retention supply VDDDR 1 44Note 3 6 V voltage Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected STOP mode j Operation mode a Data hold mode STOP instruction execution o S Standby release signal inerrupt request c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Note This depends on the POR detection voltage For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated STOP mode e Operation mode STOP instruction execution Standby release signal interrupt request Page 17 of 17
17. on TE E Reception amp shiffoperation L INTCS00 i Pf G OOOO O ees Des 7 aa TSFOO lt 2 gt lt 5 gt lt 6 gt lt 7 gt lt 2 gt lt lt 2 gt lt 5 gt lt 6 gt lt gt omitted omitted c 2014 Renesas Electronics Corporation All rights reserved Page 6 of 17 sC NC S AS RENESAS TECHNICAL UPDATE TN RL A028A E It is correction of Clock request signal internal signal in this Figure Incorrect 2 SNOOZE mode operation continuous startup Figure 12 72 Timing Chart of SNOOZE Mode Operation Continuous Startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode lt 4 gt SS00 lt 3 gt il lt 3 gt ij STOO lt 1 gt G G y M IT SWCO lt 10 gt SSECO L Clock request signal Eal int signal sea SDROO S STT SCKOO pin sa O ee L Heception amp shift operation X Shift register 00 C_ een e T lt R gt ioga L a IT L L i Data reception l Data reception TSF00 lt 2 gt lt 5 gt lt 6 gt lt 7 gt lt 2 gt lt 5 gt lt 6 gt omitted lt R gt c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS Date July 1 2014 Correct 2 SNOOZE mode operation continuous startup Figure 12 72 Timing Chart of SNOOZE Mode Operation Continuous Startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Normal operation STOP mode Normal operation STOP mode SNOOZE mode
18. rrupt Software interrupt C omitted c 2014 Renesas Electronics Corporation All rights reserved sC NC S AS px HHHH HHHH IIE Date July 1 2014 Correct Table 16 5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Software Interrupt Multiple Interrupt Maskable Interrupt Request Priority Level 3 Request Request Priority Level O Priority Level 1 Priority Level 2 PR 00 PR 01 PR 10 PR 11 HE Interrupt Being Serviced Maskable ISP1 interrupt ISPO ISP1 ISPO b x ISP1 1 ISPO 0 ISP1 1 ISPO 1 an Ba POP E e PP e PeT e RSS omitted Page 12 of 17 RENESAS TECHNICAL UPDATE TN RL A028A E 5 20 2 Configuration of Power on reset Circuit Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 3 Incorrect Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 3 1 When the externally input reset signal on the RESET pin is used Notes 3 omitted Th im ntil normal ration rts includ the following r t ro ing time when the external reset is rel after the first relea of POR after the RESET signa Q en nign a BIL 2 e voltage xternal r i Reset pr ing time when th is rele is shown below 0 672 ms typ 0 832 ms max when the LVD is in use 0 399 ms typ 0 5
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