HI5760EVAL1 User Guide
Contents
1. HI5760EVAL1 Evaluation Board User s Manual Application Note October 1998 AN9821 1 Description Features The HI5760EVAL1 evaluation board provides a quick and HI5760 125 MSPS CMOS DAC easy method for evaluating the HI5760 125 MSPS high speed DAC The converter outputs a current into a load resistor to form a voltage which can be measured by using Standard VME DSP Interface HSP EVAL Compatible the included SMA connector The amount of current out of SMA Outputs the DAC is determined by an external resistor and either an Simple and Easy to Use internal or external reference voltage The CMOS digital Easily Selectable Internal or External Reference inputs have optional external termination resistors The evaluation board also includes a VME digital interface that is Applications compatible with the HSP EVAL board so DDS Direct Digital Synthesis can be performed with minimal setup time Single MUP Corner Tone Generation Modulated Carrier Generation Ordering Information General DAC Performance Evaluation Amplitude Modulation Via External Reference PART TEMP CLOCK NUMBER RANGE C PACKAGE SPEED HI5760EVAL1 25 Evaluation Platform 125MHz Functional Block Diagram U1 VME 96PIN CONNECTOR HI5760 DAC CLOCK REF SELECT EXTERNAL REFERENCE OPTIONAL SMA1 3 1 1 888 INTERSIL or 321 724 7143 Intersil and Design is a trademark of Intersil2. 26 DCOM Digital ground 27 Digital supply 3V to 5V 28 CLK Input for clock Positive edge of clock latches data 3 4 intersil Application Notes 9821 Appendix C Circuit Board Layout FIGURE 2 PRIMARY SIDE FIGURE 3 POWER LAYER 2 3 5 intersil Application Notes 9821 Appendix Circuit Board Layout continued OO FIGURE 4 GROUND LAYER 3 FIGURE 5 SECONDARY SIDE 3 6 intersil lt Appendix D Schematic SMA1 _ EXT_REF 5 OPTIONAL VME CONNECTOR 96 PIN A28 isp L P1 28 C28 P1 92 C27 P1 91 A26 P1 26 C28 P1 90 A25 P1 25 C25 P1 89 A24 P1 24 DVDD1 O DCOM1 Q ACOM1 O AVDD1 R4 500 R5 500 R6 500 R7 502 R8 500 R9 500 R10 500 R11 500 R12 500 R13 500 NOTE ALL OTHER PINS ON THE 96 PIN VME CONNECTOR ARE DISCONNECTED FB2 104H 10 c6 10uF FB1 10uH NOTE JUMPERS SHOWN IN SHIPPED MODE J1 SLEEP IS UNINSTALLED E1 J2 INTERNAL REFERENCE IS ENABLED J3 EXTERNAL REFERENCE IS UNINSTALLED 5 IXE 22 _ _ 23 24 ___ 27 c9 0 1uF A A E SUadWNr SMA3 OUTB 0 SMA2 R3 R2 500 500 TP1 TEST POINT GND al R1 13 500 1210 PACKAG
3. Learning Your Way Around Direct Digital Synthesis To ensure that everything on the board is configured properly and functional it is suggested that the following test be performed The board test requires 1 HI5760 Evaluation Board 2 Spectrum analyzer HSP EVAL HSP45116 NCOM EVALUATION BOARD OR A DATA GENERATOR CLOCK CIRCUIT HSP EVAL HSP45116DB NUMERICALLY CONTROLLED OSCILLATOR EVAL KIT PC INTERFACE SOFTWARE INCLUDED WITH HSP EVAL PERSONAL COMPUTER 3 HSP EVAL Board with the HSP45116 NCOM Daughter Board attached and included software NCOMCTRL ora data pattern generator 4 Personal computer with a parallel port 5 50Q SMA cable Two 5V power supplies One for the DAC Eval Board and one for the HSP Eval Board Connections Note If the HSP EVAL Board is to be used it is highly recommended that the user obtain the User s Manual the datasheet for the HSP45116 NCOM and the User s Manual for the HSP45116 DB This platform is capable of testing the converter up to 25 MSPS which is the speed of the HSP EVALs on board clock The user can choose to substitute this clock with a slower one but the DSP chip and DSP Eval Board are only designed to work at a maximum of 25MHz a 52MHz version of this DSP chip does exist but not in this evaluation platform see the HSP45116A For testing of the HI5760 at higher speeds it is recommended that the user obtain a high speed dat
4. and signal sources needed to operate the board is given below 1 5V for HI5760 2 Data generator capable of generating 10 bit patterns The HSP EVAL with the HSP45116 NCOM daughter board is an option see Learning Your Way Around 3 Square wave clock source usually part of the Data Generator 4 Spectrum analyzer or oscilloscope for viewing the output of the converter Attach a 5V power supply to the evaluation board Connect the 10 input bits from the data generator to the evaluation board preferably by using a male 64 or 96 pin VME Versa Module Eurocard connector that mates with the eval board Connect the clock source to the eval board also preferably through the 64 pin connector Failure to make clean and short connections to the data input lines and clock source will result in a decrease in spectral performance 3 2 intersil Application Notes 9821 Using a coaxial cable with the proper SMA connector attach the output of the converter either IOUTA or IOUTB to the measurement equipment that will be evaluating the converter s performance Make sure that the jumpers are in their proper placement Consult the Voltage Reference section and the Sleep section of this document for a definition of the jumpers functionality Optimum single ended performance is usually achieved by either grounding or equally terminating the unused output so that its loading matches that of the output being measured
5. 7000 1130 Brussels Belgium Republic of China FAX 321 724 7240 TEL 32 2 724 2111 TEL 886 2 2716 9310 FAX 32 2 724 22 05 FAX 886 2 2715 3029 3 8 intersil
6. Corporation Copyright Intersil Corporation 2000 Application Notes 9821 Functional Description Voltage Reference The HI5760 has an internal 1 2V voltage reference with a 60ppm C drift coefficient over the full temperature range of the converter The REFLO pin 16 selects the reference Access to pin 16 is provided through the center pin of Jumper J2 To enable the internal reference it is necessary that the jumper be placed such that pin 16 is grounded if facing the evaluation board so that the SMAs are on the user s left hand side then the jumper should be placed in the right position of the three stemmed jumper The REFIO pin 17 provides access to the internal voltage reference or can be overdriven if the user wishes to use an external source for the reference Notice that a 0 1uF capacitor is placed as close as possible to the REFIO pin This capacitor is necessary for ensuring a noise free reference voltage If the user wishes to use an external reference voltage jumper J3 must be in place and an external voltage reference provided via SMA1 labeled EXT REF The recommended limits of the external reference are between 15mV and 1 2V Performance of the converter can be expected to decline as the reference voltage is reduced due to the reduction in LSB voltage size If the user wants to amplitude modulate the DAC they can overdrive the REFIO pin with a waveform The input multiplying bandwidth of the REFIO
7. E R14 2 1206 PACKAGE C1 5 8 9 0 1UF 1206 PACKAGE C6 7 10UF CASE B PACKAGE FB1 2 10uH FERRITE BEAD SMA1 3 STRAIGHT JACK PCB MOUNT P1 96 PIN VME CONNECTOR 1 3 1X2 HEADERS J2 1X3 HEADER U1 HI5760BIB E2 1286 Application Notes 9821 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com Sales Office Headquarters NORTH AMERICA EUROPE ASIA Intersil Corporation Intersil SA Intersil Taiwan Ltd P O Box 883 Mail Stop 53 204 Mercure Center 7F 6 No 101 Fu Hsing North Road Melbourne FL 32902 100 Rue de la Fusee Taipei Taiwan TEL 321 724
8. a generator capable of generating 10 bit patterns at clock speeds to at least 125MHz HI5760EVAL1 DAC MODULE HI5760 DAC 500 SMA CABLE POWER SUPPLY SPECTRUM ANALYZER FIGURE 1 INTERSIL HI5760 DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM 3 3 intersil Application Notes 9821 HSP Eval Setup DDS Attach the HSP EVAL and the HSP45116 Daughter Board together Consult their respective user manuals for details Connect the HI5760EVAL1 board to the P2 connector of the HSPEVAL board Then connect these to an IBM compatible PC via the parallel port Provide power to both boards To run the software NCOMCTRL that accompanied the HSP evaluation kit place the diskette into the A drive of the PC and type A NCOMCTRL which will run the HSP45116 Control Panel software Set the control panel s selections to the following and check the output of the DAC at either IOUTA or IOUTB for a frequency equal to 1 63MHz The clock select of the control panel should be set to Osc CLK The control signals should be as follows OENPHREG OCLROFR 1LOAD OBINFMT 1PMSEL The amplitude of the real output RINO 15 should be 8000 for full scale output The center frequency register can be set to 10ABCDEFugx for a 1 63MHz tone The Offset Frequency Phase Offset and Time Accumulator Registers should all be set to zeros The spurious free dynamic range that can be expected is typically 70dBc with this setup ope
9. er code transition points in the code ramp from 0 to 1023 so that the total glitch energy is distributed more evenly PIN NO PIN NAME PIN DESCRIPTION 1 10 D9 MSB Through Digital data bit 9 most significant bit through digital data bit 0 least significant bit DO LSB 11 14 NC No Connect Recommend ground 15 SLEEP Control Pin for Power Down Mode Sleep mode is active high Connect to ground for normal mode Sleep pin has internal 20uA active pull down current 16 REFLO Connect to analog ground to enable internal 1 2V reference or connect to AVpp to disable internal reference 17 REFIO Reference voltage input if internal reference is disabled Reference voltage output if internal reference is enabled Use 0 1uF cap to ground when internal reference is enabled 18 FSADJ Full Scale Current Adjust Use a resistor to ground to adjust full scale output current Full scale output current 32 x VREFIO RSET 19 COMP1 For use in reducing bandwidth noise Recommended Connect 0 1uF to AVpp 20 ACOM Analog Ground 21 IOUTB The complementary current output of the device Full scale output current is achieved when all input bits are set to binary 0 22 IOUTA Current output of the device Full scale output current is achieved when all input bits are set to binary 1 23 COMP2 Connect to ACOM directly or through a capacitor 24 Analog supply 3V to 5V 25 NC No connect
10. input is approximately 1 4MHz It is necessary that the multiplying signal be DC offset so that the minimum and maximum peaks of the signal do not exceed the limits imposed above Jumper J2 must be changed so that pin 16 is tied high the supply voltage which is the left position of J2 when using an external reference The output current of the converter IOUTA and IOUTB is a function of the voltage reference used and the value of Rsg R14 on the schematic Outputs The output current of the device is set by choosing RSET and VREF such that the resultant of the following equation is between 2mA and 20mA lout 32 VREF RSET For example using the internal VREF of 1 2V and an Rset R14 on the schematic value of 1 91kQ results in an louT of approximately 20mA maximum allowed Choose the output loading so that the Output Voltage Compliance Range is not violated 0 to 1 25V If an external VREF is chosen it should not exceed 1 2V The output can be configured to drive a load resistor a transformer an operational amplifier or any other type of output configuration so long as the output voltage compliance range and the maximum output current is not violated Load Resistor Output The evaluation board comes with the simple resistor load output configuration Both IOUTA and IOUTB have a 50Q resistor connected to ground next to their respective SMAs See the attached schematic for clarification Sleep The conve
11. rating at this frequency Appendix B Pin Descriptions Appendix A Description of Architecture The segmented current source architecture has the ability to improve the converter s performance by reducing the amount of current that is switching at any one time In traditional architectures major transition points required the converter to switch on or off large amounts of current In a traditional 10 bit R 2R ladder design for example the midscale transition required approximately equal amounts of currents switching on and off In a segmented current source arrangement transitions such as midscale become one in which you simply have an additional intermediate current source turning on and several minor ones turning off In the case of the HI5760 there are 31 intermediate current segments that represent the 5 MSBs and five binary weighted current sources representing each of the five LSBs See the Functional Block Diagram in the datasheet for a visual representation To relate the midscale transition example to the HI5760 consider the following The code 0111111111 would be represented by 15 intermediate current segments and each of the 5 LSB current sources all turned on To transition to code 1000000000 would simply require turning off the 5 LSB current sources and turning on the next intermediate current segment bringing the total amount of current switching at this major code transition equal to the same amount switching at 30 oth
12. rter can be put into sleep mode by connecting pin 15 to either of the converter s supply voltages For normal operation it is recommended that pin 15 be tied to ground However the sleep pin does have an active pulldown current so the pin can be left disconnected for normal operation On the evaluation board jumper J1 is provided for controlling the sleep pin Remove the jumper from J1 for normal operation and replace it for sleep mode Power Supply s and Ground s The user can operate from either a single supply or dual supplies The DAC is designed to function with the digital and analog voltages at the same value The evaluation board contains two power supply connections to allow for measuring the current drawn from the digital and analog sections independently For single supply mode it is recommended that a single power supply wire be attached to either DVpp i or and then a jumper wire placed from E2 to E3 holes A single ground wire should be attached to either DCOM1 or ACOM1 from the power supply These grounds are identical as the evaluation board uses a single ground plane The user can select to use dual ground planes in their design connected at a single point near the converter this is the recommended configuration For dual supply mode connect a power supply wire to both AVppi and DVppj and ground wires to DCOM1 and ACOM1 independently Getting Started A summary of the external supplies equipment
Download Pdf Manuals
Related Search