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GMS81C2112 GMS81C2120 User`s Manual

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Contents

1. 40PDIP o RA gt 01 407 lt gt R34 OK B8 020 39D gt R33 SIN R54 lt gt 13 38 1 lt R32 SOUT R55 lt gt 4 37 R31 PWM10 T10 R56 lt gt 5 36H lt gt R30 R57 lt gt g6 35 R27 RESET 7 34 1 R26 8 33D R25 XO 9 3211 R24 vss 10 o 31 lt gt R23 ANO R60 011 30 5 R22 AN1 R61 lt gt 012 29H lt gt R21 AN2 R62 gt 013 S 28D R20 AN3 R63 lt gt 14 o 27 lt gt R07 ANA 864 lt gt 15 26 1 lt gt R06 AN5 R65 4 16 257 gt i R05 ANG R66 gt 117 24D R04 AN7 R67 lt gt 18 230 lt gt BUZO VDD 19 22 lt gt ROO 4 gt 20 210 INTI High Voltage Port JUNE 2001 Ver 1 00 5 GMS81C2112 GMS81C2120 4 PACKAGE DIAGRAM 42SDIP 0 UNIT INCH B 1 470 2 1 450 0 600 BSC 3 0 550 5 lt 0530 gt 1 0 140 N 0 015 012017 Fa a E JL T _ gt lt 0 045 ii 0 070 BSC 44MQFP UNIT MM
2. 428DIP 2 HJ 1 42 R34 SCLK R53 4 20 S AB lt gt R33 SIN R54 lt gt 3 400 lt gt R32 SOUT R55 lt gt 4 39 lt gt R31 PWM10 T10 R56 lt gt 5 38 O lt gt R30 R57 6 371 lt gt R27 RESET gt 7 36 5 R26 Xl 8 351 R25 XO n9 34 gt R24 vss 10 9 33 lt gt R23 AVSS gt 11 5 32 lt gt R22 R60 12 31 lt gt R21 AN1 R61 13 D 300 lt gt R20 AN2 R62 lt gt 14 N 29 lt gt R07 AN3 R63 015 e 28 0 lt gt R06 AN4 R64 lt gt 16 27 gt R05 5 R65 gt r 17 26H lt gt R04 AN6 R66 lt gt 18 250 BUZO AN7 R67 lt gt 19 24 lt gt R02 ECO AVDD 20 23 0 gt R01 INT1 VDD 21 22 lt gt ROO INTO 44MQFP 5 2 0 00 NC R56 R55 R54 R53 M pee cj 2 O 325 R26 Xi c 315 R25 Ty 4 R24 vss 5 29 5 R23 AVSS 6 GMS81C2112 700 28 R22 ANO R60 cj 7 27E3 R21 AN R61 Cj 8 26 R20 R62 9 251 R07 AN3 R63 r 10 24 R06 ANA R64 11 238 805 CO f LO QN UUUUUUUUUUU 98588858829 ergo 2595 High Voltage Port 4 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120
3. 4 INCW d 9D 2 6 Nees 7 T dp 1 dp lt dp t dp 1 Load YA 5 LDYA dp 7D 2 5 YA dp 1 dp NS P Store YA 6 STYA dp DD 2 5 16 Bits subtract without carry 7 SUBW dp 3D 2 5 YA lt YA 1 NV H ZC Bit Manipulation Op Byte Cycle Flag No Mnemonic Code No No Operation 1 AND1 M bit 8B 3 4 Bit AND C flag C lt C A M bit C 2 AND1B M bit 8B 3 4 Bit AND C flag and NOT C C A M bit 1 C 3 BIT dp 0C 2 4 Bit test A with memory MM Z 4 BIT labs 1C 3 5 Ze Ne 7 Ve 5 CLR1 dp bit y1 2 4 Clear bit 00221 6 CLRA1 A bit 2B 2 2 Clear Abit Abit 7 CLRC 20 1 2 Clear C lag 07 0 8 CLRG 40 1 2 Clear G flag G 0 0 9 80 1 2 Clear V flag 0 0 0 10 EOR1 M bit AB 3 5 Bit exclusive OR C flag C C 11 EOR1B M bit AB 3 5 Bit exclusive OR C flag and NOT C lt C M bit C 12 LDC M bit CB 3 4 Load C flag e Mbit C 13 LDCB M bit CB 3 4 Load C flag with NOT C lt M bit G 14 NOT1 M bit 4B 3 5 Bit complement M bit M bit 9 15 OR1 M bit 6B 3 5 Bit OR C flag C C v M bi C 16 OR1B M bit 6B 3 5 Bit OR C flag and NOT C lt C v M bit 1 17 dp bit 2 4 Setbit 4 202020222221
4. Interrupt or WDT Interrupt STOP Instruction Execution Clear Basic Interval Timer Y tne N Na N 2 0 01 i FF 00 Normal Operation lt RCWDT Mode lt Stabilization Time Normal Operation tsr gt 20mS Figure 17 5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt RCWDT Mode Oscillator XI pin uf RA Z KA NU XU Uf NO RC Clock 22 Internal Clock 22 RESET RESET by WDT j Internal 2222 RESET STOP Instruction Execution m Stabilization Time E Time can not be control by software 64mS 4MHz Figure 17 6 Internal RCWDT Mode Releasing by RESET 17 5 Minimizing Current Consumption The Stop mode is designed to reduce power consumption ciated with the oscillator and the internal hardware is low To minimize current drawn during Stop mode the user ered however the power dissipation associated with the should turn off output drivers that are sourcing or sinking pin interface depending on the external circuitry and pro gram is not directly determined by the hardware operation ofthe STOP feature This point should be little current flows when the input level is stable at the power voltage lev
5. 38 39 4 0 V 26 27 28 29 3 0 V VoL VoL 1 2 1 4 V 0 6 08 10 12 1 4 V lon VoL 06 08 10 12 14 V 06 08 RO R2 RA loH VOH R30 R34pins loH loH VoH 10 20 30 40 5 0 V 10 20 18 Vou Vou 4 0 5 0 V 10 20 30 4 0 5 0 V JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 RESET R55 SIN SCLK Vpp ViHi XIN pins Vpp Vin2 INTO INT1 ECO pins Vpp Vir3 R53 R57 R6 pins fxiN 4 5MH Ta 25 C 2 3 4 5 6 V 1 2 3 4 5 6 V 1 2 3 4 5 6 V RESET R55 SIN SCLK Vpp VIu1 XIN pins Vpp VIL2 INTO INT1 ECO pins Vpp Vi3 53 57 6 pins 4 5 fxin 4 5MHz Ta 25 C Ta 25 C 2 3 4 5 6 V 1 2 3 4 5 6 V 1 2 3 4 5 6 V Normal Operation Stand by Mode Istop Vpp Stop Mode Ipp lop Ipp mA Ta 25 C mA Ta 25 C uA 4 0 4 0 2 0 3 0 3 0 1 5 4 5MHz 20 T 20 m 85 C 25 C 1 0 2 5MHz 1 0 05 20 C 0 Voo 0 0 Ws 2 3 4 5 6 V 2 3 4 5 6 V 2 3 4 5 6 V JUNE 2001 Ver 1 00 19 GMS81C2112 GMS81C2120
6. R57 R53 SCLK Vpp TPull up Selection N MOS Tr Open Drain Select M 4 Vi Vi Mask DD Dp 4 Option SEDE Output n PUE 4 5 Data Reg DZE x r ut Mask Ir gt Data Reg Option Bt ne Eoi eR POI s E Direction E 7 mace L VSS S c 8 W MUX Rd SS I Q lt ROO INTO RO1 INT1 R02 EC0 D DE SCLK Input Selection Vpp gt Data Reg 9 _ gt R54 SIN Mask i 3 Dir Option Pin m Reg Ld electio Vpp E Pull uj Rd N MOS ie Open Drain Select Mask Vdisp ur 4 2 lt Vpp Option gt Data Reg T D 41 EX INTO 1 Alternate Function eee f Direction Pin 2 gt lt E E a W ss lt lt 2 SIN Input 10 JUNE 2001 Ver 1 00 layuix GMS81C2112 GMS81C2120 R55 SOUT RESET Selection N MOS Vpp V Open Drain Select T Pull up DD Tr ZN fi rs phe ask MUX Option F1 Vpp 1 gt
7. No Mnemonic mee Operation Fi 1 ADC imm 04 2 2 Add with carry 2 ADC dp 05 2 3 lt 3 ADC dp X 06 2 4 4 ADC abs 07 3 4 NV H ZC 5 ADC abs Y 15 3 5 6 ADC dp X 16 2 6 7 ADC Y 17 2 6 8 ADC X 14 1 3 9 AND imm 84 2 2 Logical AND 10 AND dp 85 2 3 A lt A A M 11 AND dp X 86 2 4 12 AND labs 87 3 4 N 2 13 AND abs Y 95 3 5 14 AND dp X 96 2 6 15 AND dp Y 97 2 6 16 AND X 94 1 3 17 ASL A 08 1 2 Arithmetic shift left 18 ASL dp 09 2 4 C 76543210 N 2 19 ASL dp X 19 2 5 20 ASL abs 18 3 5 21 CMP imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp X 46 2 4 24 CMP labs 47 3 4 Compare accumulator contents with memory contents NI 2 25 CMP labs Y 55 3 5 A M 26 CMP dp X 56 2 6 27 dp Y 57 2 6 28 CMP X 54 1 3 29 CMPX imm 5E 2 2 Compare X contents with memory contents 30 CMPX dp 6C 2 3 X M N ZC 31 CMPX abs 7C 3 4 32 CMPY imm 7E 2 2 Compare Y contents with memory contents 33 CMPY dp 8C 2 3 Y M N ZC 34 CMPY abs 9C 3 4 35 COM dp 2C 2 4 1 S Complement dp dp N Z 36 DAA DF 1 3 Decimal adjust for addition N ZC 37 DAS CF 1 3 Decimal adjust for subtraction N ZC 38 DEC A A8 1 2 Decrement N Z 39 DEC dp A9 2 4 M 1 N Z 40 DEC dp X B9 2 5 N Z 41 DEC labs B8 3 5 N Z 42 DEC X AF 1 2 N Z 43 DEC Y BE
8. LOW 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 HIGH 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 000 BPL CLR1 BBC BBC ADC ADC ADC ADC ASL ASL TCALL JMP BIT ADDW LDX JMP rel dp bit A bitrel X labs Y dp X dp Y abs dp X 1 labs labs dp imm labs 001 BVC SBC SBC SBC SBC ROL ROL TCALL CALL TEST SUBW LDY JMP rel X labs Y dp X dp Y labs dp X 3 labs labs dp imm dp 010 BCC CMP CMP CMP CMP LSR LSR TCALL MUL TCLR1 CMPW CMPX CALL rel X labs Y dp X dp Y abs dp X 5 labs dp imm dp 011 BNE OR OR OR OR ROR ROR TCALL DBNE CMPX LDYA CMPY RETI rel X labs Y dp X dp Y labs dp X 7 Y labs dp imm 100 BMI AND AND AND AND INC INC TCALL DIV CMPY INCW INC TAY rel X labs Y dp X dp Y abs dp X 9 labs dp Y 101 BVS EOR EOR EOR EOR DEC DEC TCALL XMA XMA DECW DEC TYA rel X labs Y dp X dp Y labs dp X 11 X dp dp Y 110 BCS LDA LDA LDA LDA LDY LDY LDA LDX STYA XAY DAA rel X labs Y dp X dp Y labs dp X 13 X labs dp 111 BEQ STA STA STA STA STY STY STA STX CBNE XYX NOP rel X labs Y dp X dp Y labs dp X 15 X labs dp iv JUNE 2001 GMS800 Series B 3 Instruction Set Arithmetic Logic Operation
9. PASS y PASS Report First Address Location Programming OK Next address location Y Y VPP 0V N 1 Y VDD 0V N N 1 Y Y EPROM Write 100uS program time PASS Y Apply 3x program cycle YES Figure 21 5 Programming Flow Chart JUNE 2001 Ver 1 00 87 GMS81C2112 GMS81C2120 88 JUNE 2001 Ver 1 00 APPENDIX GMS800 Series A CONTROL REGISTER LIST Address Register Name Symbol R W EA 76 5141321110 00C0 RO port data register RO R W Undefined 34 00C1 RO port I O direction register ROIO 00000000 34 00C4 R2 port data register R2 R W Undefined 35 00C5 R2 port I O direction register R2IO 00000000 35 00C6 R3 port data register R3 R W Undefined 35 00C7 port I O direction register 1 010000 35 00CA R5 port data register R5 R W Undefined 35 00CB R5 port I O direction register R5IO W 00000 35 00CC R6 port data register R6 R W Undefined 35 00CD R6 port I O direction register R6IO W 00000000 35 0000 Timer mode register 0 TM0 R W 1 101010101010 44 0 register TO R 00000000 48 0001 Timer 0 data register TDR0 111141111 44 Capture 0 data register CDRO R 00000000 50 0002 Timer mode register 1 TM1 R W 00000000 44 Tim
10. 13 Recommended Operating Conditions 13 A D Converter Characteristics 13 DC Electrical Characteristics for Standard Pins 5V 14 DC Electrical Characteristics for High Voltage Pins 15 AC Characteristics 16 AC Characteristics 17 Typical Characteristics 18 8 MEMORY ORGANIZATION 20 Registers 20 Program Memory 23 Data Memory 26 Addressing Mode 30 9 O PORTS u PEDE 34 10 BASIC INTERVAL TIMER 37 11 WATCHDOG TIMER 39 12 TIMER EVENT COUNTER 42 8 bit Timer Counter Mode 44 16 bit Timer Counter Mode 48 8 bit Compare Output 16 bit 49 8 bit Capture Mode 49 16 bit Capture Mode 52 PWM M00661 trente tds 53 13 ANALOG DIGITAL CONVERTER 56 14 SERIAL PERIPHERAL INTERFACE 59 Transmission Receiving Timing 61 The method of Serial 62 The Method to Test Correct Transmission 62 15 BUZZER FUNCTION 63 16 INT
11. 42PDIP RA 1 421 R34 GIL R53 lt gt 20 Sed 410 lt gt R33 854 lt gt 3 400 R32 R55 lt gt 4 390 lt gt R31 R56 lt gt 5 38 1 lt gt R30 R57 lt gt 6 370 lt gt R27 RESET H7 36 lt gt R26 EPROM Enable Xl 8 350 R25 XO 9 340 lt gt R24 vss VSS 10 330 R23 AVSS 011 320 lt gt R22 A DO R60 lt gt 12 310 lt gt R21 AD R61 13 30 1 R20 AD R62 lt gt 14 291 lt gt R07 AD R63 115 28 1 gt R06 A_D4 R64 16 27 R05 05 R65 17 260 R04 A D6 R66 lt gt 118 250 R67 lt gt 19 240 lt gt R02 AVDD gt 20 231 4 R01 vo VDD gt 21 2211 lt gt ROO Figure 21 2 Pin Assignment t User Mode EPROM MODE Pin No a Pin Name Pin Name Description 2 R53 CTL3 Read Write Control 3 R54 CTL2 Address Data Control 4 R55 CTL1 Write Control 1 5 R56 CTLO Write Control 0 7 RESETB VPP Programming Power OV 12 75V 8 Xl EPROM Enable High Active Latch Address in falling edge 9 XO NC No connection 10 vss vss Connect to VSS 0V 12 R60 A_DO A8 A0 D0 13 R61 A_D1 Address Input AQ Al D1 14 R62 D2 Data Input Output A10 A2 02 15 R63 A_D3 A11 A3 D3 16 R64 A_D4 A12 A4 D4 17 R65 A_D5 Address Input A13 A5 D5 18 R66 A_D6 Data Input Output A14 A
12. 32 64 128 MUX 256 512 1024 Xin PIN Prescaler Select Input clock 3 oECu Basic Interval Timer clock control register CKCTLR Basic Interval overflow Timer Interrupt BITIF gt To Watchdog timer WDTCK Read Internal bus line N Figure 10 1 Block Diagram of Basic Interval Timer JUNE 2001 Ver 1 00 37 GMS81C2112 GMS81C2120 CKCTLR Interrupt overflow Period ms 2 0 Source clock 4MHz 000 8 0 512 001 fx n 16 1 024 010 fx n 32 2 048 011 64 4 096 100 128 8 192 101 256 16 384 110 512 32 768 111 1024 65 536 Table 10 1 Basic Interval Timer Interrupt Time 4 78 85 d 2 CKCTLR iwakEuP RCWDT WOTON BTCL BTS2 BTS1 BTSO 1 0 ADDRESS 0EC4 INITIAL VALUE 001 0111 Caution Both register are in same address when write to be a CKCTLR when read to be a BITR L Basic Interval Timer source clock select Clear bit 0 Normal operation free run 1 Clear 8 bit counter BITR to 0 This bit becomes 0 automatically after one machine cycle and starts counting 0 Operate as a 7 bit general timer 1 Enable Watchdog Timer operation See the section Watchdog Timer 0 Disable Internal RC Watchdog Timer 1 Enable Internal RC Watchdog Timer 0 Disable Wake up Timer 7 6 5 4 3
13. i C1 C2 C3 C4 C5 C6 C7 PCALL Area 256 Bytes DO OFFFFH DF NOTE means that the BRK software interrupt is using same address with TCALL0 Figure 8 7 PCALL and TCALL Memory Area PCALL rel TCALL gt 4F35 PCALL 35H 4A TCALL 4 seso a ida 1 Saa taa sb 52452336 2 5 ae 01001010 R 35 l o everse i 1 0D125 NEXT PC 11111111 11010110 TH FH DH 6H OFFO0 iab OFF35y NEXT OFFOu e e OFFD6 25 lt OFFD7H D1 OFFFF 24 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Example The usage software example of Vector address for GMS81C2120 ORG OFFEOH DW NOT_USED DW NOT_USED DW SIO Serial Interface DW BIT_TIMER Basic Interval Timer DW WD_TIMER Watchdog Timer DW ADC ADC DW NOT_USED DW NOT_USED DW NOT_USED DW NOT_USED DW IMER1 Timer 1 DW IMERO Timer 0 DW ntl DW INTO Int 0 DW NOT_USED Fr DW RESET Reset ORG GMS81C2120 20K ROM Start address ORG GMS81C2112 12K ROM Start address EERE qk de ko CREE LEBER ERE OR ESKER RE MAIN PROGRAM ERA EAS IRR ARS KR BB IR BR A RESET DI Disable All Interrupts CLRG LDX 0 RAM CLR LDA 0 RAM Clear 0000H 00BFH ST
14. 8 MEMORY ORGANIZATION The GMS81C2112 and GMS81C2120 have separate ad dress spaces for Program memory and Data Memory Pro gram memory can only be read not written to It can be up 8 1 Registers This device has six registers that are the Program Counter PO a Accumulator A two index registers X Y the Stack Pointer SP and the Program Status Word PSW The Program Counter consists of 16 bit register ACCUMULATOR X REGISTER Y REGISTER STACK POINTER 79 lo lt gt C C PROGRAM COUNTER PROGRAM STATUS PSW WORD Figure 8 1 Configuration of Registers Accumulator The Accumulator is the 8 bit general pur pose register used for data operation such as transfer tem porary saving and conditional judgement etc The Accumulator can be used as a 16 bit register with Y Register as shown below Two 8 bit Registers can be used as a YA 16 bit Register Figure 8 2 Configuration of YA 16 bit Register X Y Registers In the addressing mode which uses these index registers the register contents are added to the spec ified address which becomes the actual address These modes are extremely effective for referencing subroutine tables and memory tables The index registers also have in crement decrement comparison and data transfer func tions and they can be used as simple accumulators Stack Pointer The Stack Pointer is an 8 bit register used for occur
15. 1 PWM1HR 16BIT CAP1 T1CK1 T1CK0 TIST x 0 1 0 X X X X i 2 X X X X Period High TO clock source TOCK 15 0 Stop 1 Clear Start ADDRESS D2H RESET VALUE 00000000 ADDRESS D5H RESET VALUE 0000 Bit Manipulation Not Available 2 Duty High X The value 0 or 1 corresponding your operation Y T1PPR 8 bit Master 2 bit PWM1HR 1 0 T1 8 bit T1PDR 8 bit R56 COMPARATOR PWM10 T10 D 50 CLEAR PWM1O POL R5FUNC 6 54 Figure 12 12 PWM Mode JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 coe J LELE LE LILO LPL Lt LPL ULI Le H my e y o yw yoy y ye jy v yo PWM1E 15 T1CN PWM1O POL 1 PWM10 POL 0 i Duty Cycle 80H x 250nS 32uS Period Cycle 3FFH x 250nS 255 75uS 3 9KHz 5 PWM1HR 0CH 1 FFH 0 0 80H Figure 12 13 Example of PWM at 4MHz T1CK 1 0 10 1uS PWM1HR 00H T1PPR T1PDR 05H Write T1PPR to OAH Period changed gt Duty Cycle Duty Cycle Duty Cycle 05H x 2uS 10uS 05H x 2uS 10uS OSH x 2uS 1005 lt gt Period Cycle OEH x 2uS 28uS 35 5KHz Period Cycle OAH x 2uS 20uS 50KHz Figure 12 14 Example of Changing the Peri
16. 35 00F7 R6 Function selection register R6FUNG 00000000 35 0029 5 N MOS open selection register R5MPDR 00000 35 System clock mode register SCMR R W 1 0 0 1 73 00 RA port data register RA R Undefined 34 ii JUNE 2001 GMS800 Series B INSTRUCTION B 1 Terminology List Terminology Description A Accumulator X X register Y Y register PSW Program Status Word imm 8 bit Immediate data dp Direct Page Offset Address labs Absolute Address Indirect expression Register Indirect expression Register Indirect expression after that Register auto increment bit Bit Position A bit Bit Position of Accumulator dp bit Bit Position of Direct Page Memory M bit Bit Position of Memory Data 000 rel Relative Addressing Data upage U page Offset Address n Table CALL Number 0 15 Addition Upper Nibble Expression in Opcode x Bit Position 1 Upper Nibble Expression in Opcode y p i Bit Position Subtraction x Multiplication Division Contents Expression AND v OR Exclusive OR NOT lt Assignment Transfer Shift Left gt Shift Right gt Equal Not Equal JUN
17. a GMS81C2112 GMS81C2120 layuix Internal bus line I flag is in PSW it is cleared by DI set by OE24 IENH Interrupt Enable El instruction When it goes interrupt service H Register Higher byte l flag is cleared by hardware thus any other interrupt are inhibited When interrupt service is completed by RETI instruction I flag is set to 1 by hardware INTO LT 5 LH Release STOP Timer Q e Timer 1 To CPU c n Interrupt Master Enable Flag A D Converter Interrupt Watchdog Timer Vector BIT Address Generator Serial Communication 0E3 Interrupt Enable DDE3HI Register Lower byte Internal bus line 5 Figure 16 2 Block Diagram of Interrupt RW RW RW RW ADDRESS 0 2 INITIAL VALUE 0000 Timer Counter 1 interrupt enable flag Timer Counter 0 interrupt enable flag External interrupt 1 enable flag External interrupt 0 enable flag VALUE RW RW RW RW i s 0 Disable ADDRESS 1 Enabl DE WDTE BITE SPIE 5 IENL ADE wore SPIE INITIAL VALUE 0000 g MSB LSB Serial Communication interrupt enable flag Basic Interval imer interrupt enable flag Watchdog timer interrupt enable flag A D Convert interrupt enable flag Figure 16 3 Interrupt Enable Flag 66 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 16 1 Interrupt Sequence An interrupt request is held until the interrupt
18. Input Output data ADDRESS 0C1H RO Direction Register RESET VALUE 00 ROIO Port Direction 0 Input 1 Output ADDRESS RO Function Selection Register RESET VALUE 00005 0 ROO 1 INTO 0 R01 1 1 INT JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 R2 and R2IO register R2 is an 8 bit high voltase CMOS bidirectional I O port address 4 Each port can be set individually as input and output through the R2IO register address 5 Each port can directly drive a vacuum flu orescent display ADDRESS 0C4 RESET VALUE Undefined R2 R27 R26 R25 R24 R23 822 R21 R20 82 Data Register Input Output data irecti i ADDRESS 0 5 R2 Direction Register RESET VALUE 00 Port Direction 0 Input 1 Output R3 and R3IO register R3 is a 5 bit high voltage CMOS bidirectional I O port address Each port can be set individually as input and output through the R3IO register address ADDRESS 0C6 RESET VALUE Undefined R3 i 1 1 34 R32 R31 R30 R3 Data Register Input Output data ADDRESS 7 R3 Direction Register RESET VALUE 00000 R3IO Port Direction 0 Input 1 Output R5 and RSIO register R5 is an 5 bit bidirectional I O port address Each pin can be set
19. ns SIN Input Setup Time Internal SCLK tsus SIN 200 ns SIN Input Hold Time tus SIN tsys 70 ns Serial Output Clock Cycle Time tscyc SCLK 4tsys 16tsys ns Serial Output Clock Pulse Width tsckw SCLK tsys 30 ns m t Serial Output Clock Pulse Transition FSCK SCLK 30 e Time trsck Serial Output Delay Time SOUT SOUT 100 ns 0 8Vpp SCLK SIN SOUT 0 8Vpp Figure 7 2 Serial I O Timing Chart JUNE 2001 Ver 1 00 17 GMS81C2112 GMS81C2120 7 8 Typical Characteristics This graphs and tables provided in this section are for de sign guidance only and are not tested or guaranteed In some graphs or tables the data presented are out side specified operating range e g outside specified Vpp range This is for information only and devices are guaranteed to operate properly only within the specified range R40 R43 R6 R53 R57 BUZO PWM10 T10 lou Vou SCLK SOUT pins data presented this section 15 statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represents mean 3o and mean 3o respectively where o is standard deviation 46 47 48 49 5 0 36 37 R40 R43 R6 R53 R57 BUZO PWM10 T10 loL VOL SOUT pins
20. 18 SETA1 A bit 0B 2 2 Set A bit Abit Pf 19 SETC AO 1 2 SetC flag 1 20 SETG 1 2 Set G flag Ge 1 1 21 STC M bit 3 6 Store C flag M bit C 2 2 HP Test and clear bits with A 22 TCLR1 abs 5C 3 6 Nus 7 A M lt M a A Test set bits with A 23 TSET1 abs 3C 3 6 N Z A M lt M v A viii JUNE 2001 GMS800 Series Branch Jump Operation pc lt Table vector L lt Table vector H Byte Cycle Flag No Mnemonic Code No No Operation 1 BBC A bit rel y2 2 4 6 Branchifbitclear ____ 2 dp bit rel y3 3 5 7 if bit 0 then pc lt pc rel 3 BBS A bit rel x2 2 4 6 Branchifbitset 002220202201 4 BBS dp bit rel x3 3 5 7 if bit 1 then pc lt pc rel Branch if carry bit clear 2 12255 39 2 24 if C 20 then pc lt rel Branch if carry bitse ____ 8 Po 2 2 4 if C 1 then pc pc rel Branchifequal _______ _ j _____ c Fo 24 if Z 1 then pe lt rel Branch if minus 8 90 2 24 it N 1 then pee Branchifnotequal f 70 2 24 if Z lt 0 then po e rel Branch if minus io BEES 10 2 4 11 BRA rel 2F 2 eee lt pc rel Branch
21. 62 5mS at 4 19MHz RESET Process Step 1 tgt 256 ST main 1024 Figure 19 2 Timing Diagram after RESET 19 2 Watchdog Timer Reset Refer to 11 WATCHDOG TIMER on page 39 80 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 20 POWER FAIL PROCESSOR The GMS81C21xx has an on chip power fail detection cir cuitry to immunize against power noise A configuration register PFDR can enable or disable the power fail detect circuitry Whenever Vpp falls close to or below power fail voltage for 100ns the power fail situation may reset or freeze MCU according to PFDM bit of PFDR Refer to 7 4 DC Electrical Characteristics for Standard Pins 5V on page 14 In the in circuit emulator power fail function is not imple mented and user can not experiment with it Therefore af ter final development of user program this function may be experimented or evaluated Note User can select power fail voltage level according to PFDO PFD1 bit of CONFIG register 703F at the OTP GMS87C21xx but must select the power fail voltage level to define PFD option of Mask Order amp Verification Sheet at the mask chip GMS81C21xx Because the power fail voltage level of mask chip GMS81C21xx is determined according to mask option Note power fail voltage is selected to 3 0V on oper ation MCU is freezed at all the times Power FailFunction OTP MASK Enable Disable PFDIS flag PFDI
22. Data Reg T AX d gt ZN _ Direction tet g Vss 8 E i 8 s 198 8 4 Vis XIN XOUT Rd 2 lt YY A lt lt 9 IOSWIN Input Vpp AX XOUT 4 RA Vdisp A T Mainclk Off ZN Vpp T XIN ZN Data bus lt D gt A Mask gt Option Vss Vdisp lt R03 BUZO R04 R07 R20 R27 R30 R34 tm Ie S d lt gt Data Reg lt gt Data Reg um 4 asi noa 2 Dir Option Pin 3 ir Option Pin a Reg 5 8 Vdisp MUX MUX 4277 4 JUNE 2001 Ver 1 00 11 GMS81C2112 GMS81C2120 R56 PWM10 T10 Selection N MOS Open Drain Select Vpp Pull up SOUT output E Tr MUX Mask g Vpp f Option Data Reg T H gt e Pn E Y V s Rd R60 R67 AN0 AN7 Vpp Pull up Tr Mask r VDD Option lt D Reg DOAL n b Reg Ado 75 Pin 2 v a Rd A D Converter Analog Input Mode D A D Ch Selection 12 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 7 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Ratings Supply voltage Storage Temper
23. 0000 byte OF6H R5FUNC 0 byte OF7H R6FUNC 0000_0000 byte OF9H R5NODR w 0000_0 byte OFAH SCMR R W 0_0000 byte OFBH RA R Undefined 3 Table 8 1 Control Registers 1 byte bit means that register can be addressed by not only bit but byte manipulation instruction 2 byte means that register can be addressed by only byte manipulation instruction On the other hand do not use any read modify write instruction such as bit manipulation for clearing bit is one bit high voltage input only port pin In addition RA serves the functions of the Vdisp special features Vdisp is used as a high voltage input power supply pin when selected by the mask option JUNE 2001 Ver 1 00 Table 8 2 Various Register Name in Same Address 27 GMS81C2112 GMS81C2120 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COH RO RO Port Data Register Bit 7 0 C1H ROIO RO Port Direction Register Bit 7 0 C4H R2 R2 Port Data Register Bit 7 0 C5H R2 Port Direction Register Bit 7 0 C6H R3 R3 Port Data Register Bit 4 0 C7H R3IO R3 Port Direction Register Bit 4 0 CAH R5 R5 Port Data Register Bit 7 3 CBH R5IO R5 Port Direction Register Bit 7 3 CCH R6 R6 Port Data Register Bit 7 0 CDH R6
24. PozZug By qu t Lt Et ti t E H Example 2 E Timer0 8 bit event counter mode Timer1 0 5ms 8 bit timer mode at 4MHz LDM TDRO 250 LDM TDR1 250 LDM TMO 0001_1111B LDM 1 0000 1011 SE OE SE 1E EI JUNE 2001 Ver 1 00 Note The contents of Timer data register TDRx should be initialized 1 not because it is undefined after re set These timers have each 8 bit count register and data regis ter The count register is increased by every internal or ex ternal clock input The internal clock has a prescaler divide ratio option of 2 4 8 32 128 512 2048 selected by con trol bits TOCK 2 0 of register TMO and 1 2 8 selected by control bits TICK 1 0 of register TM1 In the Timer 0 timer register TO increases from 00g until it matches and then reset to 00 The match output of Timer 0 generates Timer 0 interrupt latched in TOIF bit As TDRx and Tx register are in same address when reading it as a Tx written to TDRx In counter function the counter is increased every 0 to 1 1 to 0 rising amp falling edge transition of ECO pin In order to use counter function the bit ECO of the RO Func tion Selection Register ROFUNC 2 is set to 1 The Timer 0 can be used as a counter by pin ECO input but Timer 1 can not 45 GMS81C2112 GMS81C2120 8 bit Timer Mode In the timer mode the internal clock is used for counting Counti
25. Prescaler re SCLK PIN 1 not 11 MUX 9 ci CONTROL SIOST SIOSF Start Complete overflow Octal Counter SPI CIRCUIT Clock SIOIF gt Serial communication Interrupt SCK 1 0 SSW SOUT IOSWIN SOUT IOSWIN SIN PIN L gt Input shift register Internal Bus Figure 14 1 SPI Block Diagram JUNE 2001 Ver 1 00 59 GMS81C2112 GMS81C2120 Serial I O Mode Register SIOM controls serial I O func tion According to SCK1 and SCKO the internal clock or external clock can be selected The serial transmission op eration mode is decided by setting the SM1 and SMO and the polarity of transfer clock is selected by setting the POL Serial I O Data Register SIOR is a 8 bit shift register First LSB is send or is received When receiving mode se rial input pin is selected by IOSW The SPI allows 8 bits of data to be synchronously transmitted and received To accomplish communication typically three pins are used Serial Data In R54 SIN Serial Data Out R55 SOUT Serial Clock R53 SCLK RW R W 7 6 5 4 3 2 SIOM RW RW RW RW RW R POL ilOSW SM1 SMO SCK1 SCK0 ISIOSTISIOSF 1 0 ADDRESS 0E0 INITIAL VALUE 0000 00015 Serial transmission status bit 0 Serial transmission is in progress 1 Serial transmission is completed Serial transmission start bit Setting this bit star
26. SEE DETAIL A CAT 147 04 9 45 0 80 B 0 80 BSC e 6 JUNE 2001 Ver 1 00 ix GMS81C2112 GMS81C212 0 40PDIP po uo O UNIT INCH 2 075 oe lt 5915 gt 0 600 BSC x G 8 S NES B RS s 0 F F Y Bk SR 012 0 022 0 065 0 100080 1 9 012 90i5 70045 ls 0 15 0 008 JUNE 2001 1 00 GMS81C2112 GMS81C2120 5 FUNCTION Supply voltage VSS Circuit ground AVDD Supply voltage to the ladder resistor of ADC cir cuit To enhance the resolution of analog to digital convert er use independent power source as well as possible other than digital power source AVSS ADC circuit ground RESET Reset the MCU XIN Input to the inverting oscillator amplifier and input to the internal clock operating circuit XOUT Output from the inverting oscillator amplifier RA V RA is one bit high voltage input only port pin In addition RA serves the functions of the special features Vaisp is used as a high voltage input power supply pin when selected by the mask option Port pin Alternate function RA V disp High voltage input power supply R00 R07 RO is 8 bit
27. 0V 11 PFD 2 4V 3 H V Port OPTION Check Pull down Option Check Option Port ON OFF ROO INTO RO1 INT1 RO2 ECO ROS BUZO ON with pull down resistor OFF without pull down resistor Port ON OFF R54 SIN R61 AN1 R66 AN6 ON with pull up resistor R67 AN7 OFF without pull up resistor hynix
28. 1 2 N Z JUNE 2001 V GMS800 Series 18 Mnemonic eis Ne kon Operation 44 DIV 9B 1 12 Divide YA XQ A R Y NV H Z 45 EOR fimm A4 2 2 Exclusive OR 46 EOR dp A5 2 3 lt 47 EOR X A6 2 4 48 EOR abs A7 3 4 Mese z 49 EOR abs Y B5 3 5 50 EOR dp X B6 2 6 51 EOR dp Y B7 2 6 52 EOR X B4 1 3 53 INC A 88 1 2 Increment N ZC 54 INC dp 89 2 4 M e M 1 N Zz 55 INC dp X 99 2 5 7 56 INC abs 98 3 5 N Z 57 INC X 8F 1 2 Neren 7 58 INC Y 9E 1 2 Neos 59 LSR A 48 1 2 Logical shift right 60 LSR dp 49 2 4 76543210 C 2 61 LSR dp X 59 2 0 gt 3l 62 LSR labs 58 3 5 63 MUL 5B 1 9 Multiply N Z 64 OR imm 64 2 2 Logical OR 65 OR dp 65 2 3 lt A v M 66 OR dp X 66 2 4 67 OR labs 67 3 4 Num Z 68 OR labs Y 75 3 5 69 OR dp X 76 2 6 70 OR dp Y 77 2 6 71 OR X 74 1 3 ROLNA 28 1 2 Rotate left through Carry 73 ROL dp 29 2 4 C 76543210 N ZC 74 ROL dp X 39 2 5 75 ROL abs 38 3 5 non 68 2 Rotate right through Carry 77 ROR dp 69 2 4 76543210 C N ZC 78 ROR dp X 79 2 5 gt gt 79 ROR abs 78 3 5 80 SBC imm 24 2 2 Subtract with Carry 81 SBC dp 25 2 3 lt
29. 30 STY dp E9 2 4 Store Y register contents in memory 31 STY dp X F9 2 5 M Y 32 STY labs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X register X A N 2 34 9F 1 2 Transfer accumulator contents to Y register Y A N 2 35 TSPX AE 1 2 Transfer stack pointer contents to X register X sp N 2 36 C8 1 2 Transfer X register contents to accumulator A X N 7 37 8E 1 2 Transfer X register contents to stack pointer sp X N 2 38 BF 1 2 Transfer Y register contents to accumulator A lt Y N 2 39 1 4 Exchange X register contents with accumulator lt 40 XAY DE 1 4 Exchange Y register contents with accumulator gt 41 XMA dp BC 2 5 Exchange memory contents with accumulator 42 XMA dp X AD 2 6 N 2 43 XMA X BB 1 5 44 XYX FE 1 4 Exchange X register contents with Y register JUNE 2001 vii GMS800 Series 16 operation Byte Cycle Flag No Mnemonic Code No No Operation NVGBHIZC j ADDW dp 1D 2 5 16 Bits add without Carry NV H ZC lt YA 1 dp Compare YA contents with memory pair contents 2 CMPW d 5D 2 4 N 2 YA dp 1 dp Decrement memory pair 3 DECW d BD 2 6 cs 7 i 1 lt dp 1 1 Increment memory pair
30. 4 3 2 1 0 ADDRESS 0D3 DP T I TI L T NAL VALUE Undetnec Read Count value read Write Compare data write Figure 12 1 TMO TM1 Registers JUNE 2001 Ver 1 00 43 GMS81C2112 GMS81C2120 12 1 8 bit Timer Counter Mode The GMS81C21xx has two 8 bit Timer Counters Timer 0 as an 8 bit timer counter mode bit CAPO of TMO is Timer 1 as shown in Figure 12 2 cleared to 0 and bits 16BIT of TM1 should be cleared to The timer or counter function is selected by mode reg credit D isters TMx as shown in Figure 12 1 and Table 12 1 To use ADDRESS 0D0 7 6 5 4 3 2 1 0 TMO CAP0 T0CK2 TOCK1T0CK0 TOCN TOST INITIAL VALUE 0000006 0 X x X x x X means don t care 5 2 4 3 1 0 ADDRESS 002 TM1 16BIT CAP1 T1CK1T1CK0 TICN T1ST INITIAL VALUE 00 x 0 0 0 x x x X X means don t care TOCK 2 0 EDGE DETECTOR TOST 0 Stop 1 Clear and start clear TIMER 0 TOCN TOIF gt INTERRUPT TIMER 0 TDRO 8 bit Prescaler T1ST 0 Stop 1 Clear and start clear TIMER 1 TICN THIF as Dx INTERRUPT TIMER 1 TDR1 8 bit Figure 12 2 8 bit Timer Counter 0 1 44 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Example 1 Timer 2ms 8 bit timer mode at 4MHz Timerl 0 5ms 8 bit timer mode at 4MHz DM DM DM DM RO 250 R1 250 0 0000_1111B 1 0000_1011B E E
31. A M C 82 SBC X 26 2 4 83 SBC abs 27 3 4 NV HZC 84 SBC abs Y 35 3 5 85 SBC dp X 36 2 6 86 SBC dp Y 37 2 6 87 SBC X 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero dp 00H N 2 89 XCN CE 1 5 within the accumulator EE je vi JUNE 2001 GMS800 Series Register Memory Operation No Mnemonic 2 po poss Operation mu 1 LDA imm C4 2 2 Load accumulator 2 LDA dp C5 2 3 A 3 LDA dp X C6 2 4 4 LDA abs C7 3 4 5 LDA abs Y D5 3 5 N 2 6 LDA dp X D6 2 6 7 LDA dp Y D7 2 6 8 LDA X D4 1 3 9 LDA X DB 1 4 X register auto inorement A M X X 1 10 LDM dp imm E4 3 5 Load memory with immediate data M imm 11 LDX imm 1E 2 2 Load X register 12 LDX dp CC 2 3 X M N 2 13 LDX dp Y CD 2 4 14 LDX abs DC 3 4 15 LDY imm 3E 2 2 Load Y register 16 LDY dp C9 2 3 Y M N 2 17 LDY dp X D9 2 4 18 LDY abs D8 3 4 19 STA dp E5 2 4 Store accumulator contents in memory 20 STA dp X E6 2 5 lt 21 STA abs E7 3 5 22 STA abs Y F5 3 6 23 STA dp X F6 2 7 24 STA dp Y F7 2 7 25 STA X F4 1 4 26 STA X FB 1 4 X register auto increment lt A Xe X 1 27 STX dp EC 2 4 Store X register contents in memory 28 STX dp Y ED 2 5 e X 29 STX labs FC 3 5
32. GMS81C2120 17 1 Operating Mode Main clock frequency fSYS fXI fXI 4 fXI 8 fXI 32 cpu system clock tmr timerO clock peri peripheral clock CKCTLR CKCTLR 6 5 STANDBY Mode ACTIVE Mode CKCTLR 10 oscillation SIOP oscillation stop gt fSYS 11 fx TIMERO fSYS stop EXT_INT fSYS RESET RC_WDT CKCTLR 00 EXT INT RESET STOP RC_WDT STOP Mode System Clock Mode Register ADDRESS FAH CS 1 0 Clock selection enable bits 00 fXI 10 51 8 01 2 4 11 5 32 JUNE 2001 Ver 1 00 73 GMS81C2112 GMS81C2120 17 2 Stop Mode In the Stop mode the on chip oscillator is stopped With the clock frozen all functions are stopped but the on chip RAM and Control registers are held The port pins out the values held by their respective port data register port di rection registers Oscillator stops and the systems internal operations are all held up The states of the RAM registers and latches valid immediately before the system is put in the STOP state are all held The program counter stop the address of the instruction to be executed after the instruction STOP which starts the STOP operating mode The Stop mode is activated by execution of STOP in struction after clearing the bit WAKEUP of CKCTLR to 0 This register should be written by byte opera tion If this register is set by bit manipulation instruc tion for example
33. bit of timer mode register TM1 for Timer 1 as shown in Figure 12 8 As mentioned above not only Timer 0 but Timer 1 can also be used as a capture mode The Timer Counter register is increased in response inter nal or external input This counting function is same with normal timer mode and Timer interrupt is generated when timer register TO T1 increases and matches TDRO TDR1 This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer For example in Figure 12 10 the pulse width of captured signal is wider than the timer data value FFy over 2 times When external interrupt is occurred the captured value 13g is more little than wanted value It can be ob JUNE 2001 Ver 1 00 tion 16 bit Compare output mode is available also This pin output the signal having a 50 50 duty square wave and output frequency is same as below equation f Oscillation Frequency COMP 7 2x Prescaler Value x TDR 1 tained correct value by counting the number of timer over flow occurrence Timer Counter still does the above but with the added fea ture that a edge transition at external input INTx pin causes the current value in the Timer x register 0 1 to be cap tured into registers CDRx CDR1 respectively After captured Timer x register is cleared and restarts by hardware Note The CDRx TDRx and Tx are in same a
34. example by en tering the STOP mode The other type is a prescaled system clock The watchdog timer consists of 7 bit binary counter and the watchdog timer data register When the value of 7 bit binary counter is equal to the lower 7 bits of WDTR the interrupt request flag is generated This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON Note Because the watchdog timer counter is enabled af ter clearing Basic Interval Timer after the bit WDTON set to 1 maximum error of timer is depend on prescaler ratio of Basic Interval Timer The 7 bit binary counter is cleared by setting WDTCL bit7 of WDTR and the WDTCL is cleared automatically after 1 machine cycle The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below LDM CKCTLR 3FH enable the RC osc WDT LDM WDTR 0FFH set the WDT period STOP enter the STOP mode NOP NOP RC osc WDT running The RCWDT oscillation period is vary with temperature VDD and process variations from part to part approxi mately 40 120uS The following equation shows the RCWDT oscillated watchdog timer time out CLK pcwprx2ex W DTR 6 0 CLK 28 2 where CLKpcwpr 40 120uS In addition this watchdog timer can be used as a simple 7 bit timer by interrupt WDTIF The interval of watchdog timer interrupt is decided by Basic Interval Timer Interval equation is as below Twpr WDTR 6 0 x Inte
35. fins a ns 1 uA Input Pull up Current Option 153 57 6 PU 50 100 180 uA Power Fail V V Detect Voltage Dp em 2 Current dissipation V in dctiveanade DD DD fXIN 4 5MHz 8 mA Current dissipation V in standby mode DD STBY fxIN 4 5MHz 3 mA Current dissipation fxINZOff V stop mode DD RIPE fSXIN 32 7KHz 10 RESET SIN R55 SCLK Hysteresis INTO INT1 ECO V1 0 4 V Internal RO WDT 1 Frequency ad RCWDT 8 30 KHz RC Oscillation f Frequency XOUT RCOSC R 120KQ 1 5 2 2 5 MHz 1 Data Typ column is at 4 5V 25 C unless otherwise stated These parameters for design guidance only and are not tested 14 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 7 5 DC Electrical Characteristics for High Voltage Pins 5 0V 10 Vss OV Ta 40 85 C 4 MHz Vdisp Vpp 40V to Vpp Specification Parameter Pin Symbol Test Condition Unit Min Input High Voltage RO R2 R30 R34 RA Vin 0 7Vpp Vpp 0 3 Input Low Voltage RO R2 R30 R34 RA Vpp 40 0 3Vpp loH 15mA Vpp 3 0 Output High Ro R2 R30 R34 lou 10mA Vpp 2 0 V 9 4 Vpp 1 0 Vdisp Vpp 40 Output Low Vpp 37 V _ Voltage R0 R2 R30 R34 OL 150KQ atVpp Vpp 37 V 40 Input High t VIN Vpp 40V Leakage Current to Vpp a si Input Pull down Vdisp Vpp 35V Current Option R0 R2 R
36. if overflow bit clear 12 irel ae 2 24 li O thenpce posrel Branch if overflow bit set 13 ENS rel En 24 lit y 1 thenpcc pce srel 14 CALL abs 3B 3 8 Subroutine call lt 1 M sp lt peL sp esp 1 15 CALL dp a 2 8 iflabs pee abs if dp pere pene 1 16 CBNE dp rel FD 3 5 7 Compare andbranchifnotequal 17 CBNE dp X rel 8D 3 6 8 if A z M then pc lt rel 18 DBNE dp rel AC 3 5 7 Decrement and branch if not equal 1 19 DBNE 7B 2 4 6 if M 0 then pc lt pc rel 20 JMP abs 1B 3 Unconditional jump 21 JMP labs 1F 3 lt jump address 22 JMP dp 3F 2 U page call 23 PCALL upage 4F 2 6 M sp lt lt 1 lt Sp lt sp 1 pc lt lt Table call sp sp lt sp 1 24 nA 1 8 M sp pceL spesp 1 JUNE 2001 GMS800 Series Control Operation amp Etc No Mnemonic 2 po pos Operation mu m Software interrupt B lt 71 M sp lt sp sp 1 1 BRK OF 1 8 M s lt pci sp lt sp 1 M sp lt PSW sp lt sp 1 1 0 per lt 0FFDEH lt OFFDFy 2 DI 60 1 3 Disable all interrupts 1 lt 0 0 3 EI EO 1 3 Enable all interrup
37. input pin ECO In addition the capture function the register is increased in response external or internal clock sources same with timer or counter function When external clock edge input the count register is captured into capture data register CDRx Timer is shared with PWM function and Compare out put function It has seven operating modes 8 bit timer counter 16 bit timer counter 8 bit capture 16 bit capture 8 bit compare output 16 bit compare output and 10 bit which are selected by bit in Timer mode register and as shown in Figure 12 1 and Table 12 1 16BIT PWM1E Bo n 2 PWM10 TIMER 0 TIMER 1 0 0 0 0 XXX XX 8 bit Timer 8 bit Timer 0 0 1 0 111 XX 8 bit Event counter 8 bit Capture 0 1 0 0 XXX XX 1 8 bit Capture internal clock 8 bit Compare Output 0 X 0 1 XXX XX 1 8 bit Timer Counter 10 bit PWM 1 0 0 0 XXX 11 0 16 bit Timer 1 0 0 0 111 11 0 16 bit Event counter 1 1 X 0 XXX 11 0 16 bit Capture internal clock 1 0 0 0 XXX 11 1 16 bit Compare Output Table 12 1 Operating Modes of and Timer1 42 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 RW RW RW RW RW RW ADDRESS 000 5 4 3 2 1 0 TMO TOCN TOST INITIAL VALUE 0000005 Bit Name Bit Position Description CAPO TMO 5 0 Timer Counter mode 1 Capture mode sel
38. 06 27 6 250 3 125 1 563 0 781 08 27 778 13 889 6 944 3 472 28 6 098 3 049 1 524 0 762 09 25 000 12 500 6 250 3 125 29 5 952 2 976 1 488 0 744 OA 22 727 11 364 5 682 2 841 2A 5 814 2 907 1 453 0 727 0B 20 833 10 417 5 208 2 604 2B 5 682 2 841 1 420 0 710 0C 19 231 9 615 4 808 2 404 2C 5 556 2 778 1 389 0 694 17 857 8 929 4 464 2 232 2 5 435 2 717 1 359 0 679 16 667 8 333 4 167 2 083 2 5 319 2 660 1 330 0 665 15 625 7 813 3 906 1 953 2 5 208 2 604 1 302 0 651 10 14 706 7 353 3 676 1 838 30 5 102 2 551 1 276 0 638 11 13 889 6 944 3 472 1 736 31 5 000 2 500 1 250 0 625 12 13 158 6 579 3 289 1 645 32 4 902 2 451 1 225 0 613 13 12 500 6 250 3 125 1 563 33 4 808 2 404 1 202 0 601 14 11 905 5 952 2 976 1 488 34 4 717 2 358 1 179 0 590 15 11 364 5 682 2 841 1 420 35 4 630 2 315 1 157 0 579 16 10 870 5 435 2 717 1 359 36 4 545 2 273 1 136 0 568 17 10 417 5 208 2 604 1 302 37 4 464 2 232 1 116 0 558 18 10 000 5 000 2 500 1 250 38 4 386 2 193 1 096 0 548 19 9 615 4 808 2 404 1 202 39 4 310 2 155 1 078 0 539 1A 9 259 4 630 2 315 1 157 3A 4 237 2 119 1 059 0 530 1B 8 929 4 464 2 232 1 116 3B 4 167 2 083 1 042 0 521 1 8 621 4 310 2 155 1 078 3C 4 098 2 049 1 025 0 512 1D 8 333 4 167 2 083 1 042 3D 4 032 2 016 1 008 0 504 1E 8 065 4 032 2 016 1 008 3E 3 968 1 984 0 992 0 496 1F 7 813 3 906 1 953 0 977 3F 3 907 1 953 0 977 0 488 64 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 16 INTERRUPTS The GMS81C21xx interrupt circuits cons
39. 100 1100B 16bit Mode LDM TDRO lt 62500 815 X 62500 LDM TDR1 gt 62500 7 0 5s 5 0 2 Timer0 16 bit event counter mode LDM ROFUNC 0000_0100B ECO Set LDM TMO 0001_1111B Counter Mode LDM TM1 0100_1100B 16bit Mode LDM TDRO lt OFFH LDM TDR1 gt 0 5 OE EI 12 6 PWM Mode The GMS81C2120 has a high speed PWM Pulse Width Modulation functions which shared with Timerl In PWM mode pin R56 PWM10 T10 outputs up to a 10 bit resolution PWM output This pin should be configured as a PWM output by setting 1 bit PWM1O in RSFUNC 6 register The period of the PWM output is determined by the TIPPR PWMI Period Register and PWMIHR 3 2 bit3 2 of High Register and the duty of the PWM output is determined by the TIPDR PWMI Duty Regis ter and PWMIHR 1 0 bit1 0 of PWM1 High Register The user writes the lower 8 bit period value to the TIPPR and the higher 2 bit period value to the PVMIHR 3 2 JUNE 2001 Ver 1 00 Example 3 Timer0 16 bit capture mode LDM ROFUNC 0000_0001B INTO set LDM TMO 0010_1111B Capture Mode LDM TM1 0100_1100B 16bit Mode LDM TDRO lt OFFH 2 LDM TDR1 gt 0 LDM IEDS 01H Falling Edge SET1 OE EI And writes duty value to the TIPDR and the PWMIHR 1 0 same way The TIPDR is configured as a double buffering for glitch less PWM output In Figure 12 12 th
40. 10C025H PROGRAM MEMORY pro gt 0 025 25 0E026H E7 jump to E30AH 0E725H NEXT lt address 0E30 25 EO JUNE 2001 Ver 1 00 33 GMS81C2112 GMS81C2120 9 PORTS The GMS81C21xx has five ports R2 R3 R5 and R6 These ports pins may be multiplexed with an alternate function for the peripheral features on the device All pins have data direction registers which can define these ports as output or input A 1 in the port direction register configure the corresponding port pin as output Conversely write 0 to the corresponding bit to specify it as input pin For example to use the even numbered bit of RO as output ports and the odd numbered bits as input ports write 55 to address RO port direction reg ister during initial setting as shown in Figure 9 1 All the port direction registers in the GMS81C2120 have 0 written to them by reset function On the other hand its in itial status is input WRITE 55 TO PORT RO DIRECTION REGISTER m 0 1 0 1 0 1 0 1 76543210 Figure 9 1 Example of Port I O Assignment RA Vdisp register RA is one bit high voltage input only port pin In addition RA serves the functions of the Special features is used as a high voltage input power supply pin when selected by the mask optio
41. 2 1 0 BITR 8 BIT FREE RUN BINARY COUNTER 1 Enable Wake up Timer ADDRESS 0EC INITIAL VALUE Undefined Figure 10 2 BITR Basic Interval Timer Mode Register Example 1 Basic Interval Timer Interrupt request flag is generated every 4 096ms at 4MHz DM L CKCTLR 03H SETE BITE EI 38 Example 2 Basic Interval Timer Interrupt request flag is generated every 1 024ms at 4MHz LDM CKCTLR 01H SET1 BITE EI JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 11 WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like and re sumes the CPU to the normal state The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request When the watchdog timer is not being used for malfunc tion detection it can be used as a timer to generate an in terrupt at fixed intervals The purpose of the watchdog timer is to detect the malfunction runaway of program due to external noise or other causes and return the opera tion to the normal condition The watchdog timer has two types of clock source The first type is an on chip RC oscillator which does not require any external components This RC oscillator is sep arate from the external oscillator of the Xin pin It means that the watchdog timer will run even if the clock on the Xin pin of the device has been stopped for
42. 30 R34 PD 200 600 1000 uA Input High Voltage RO R2 R30 R34 RA Vin 0 7Vpp Vpp 0 3 V 1 Data in Typ column is at 4 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested JUNE 2001 Ver 1 00 15 GMS81C2112 GMS81C2120 7 6 Characteristics 40 85 C Vpp 5V 10 Vss 0V Symbol Pins pee Unit Min Typ Max Operating Frequency fcp XIN 1 8 MHz External Clock Pulse Width tcpw XIN 80 ns External Clock Transition Time trop tecp XIN 20 ns Oscillation Stabilizing Time tsT XIN XOUT 20 mS External Input Pulse Width tepw INTO INT1 ECO 2 tsys oe ae Pulse Transi IREP FEP INTO INT1 ECO _ 20 ns RESET Input Width tRST RESET 8 5 tsys Xl RESETB INTO INT1 ECO Figure 7 1 Timing Chart 16 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 7 7 AC Characteristics 40 85 Vpp 5V 10 Vss 0V fyxijN 4MHz Specifications Parameter Symbol Pins Unit Min Typ Max Serial Input Clock Pulse tecvc SCLK 2tsys 200 3 8 ns Serial Input Clock Pulse Width isckw SCLK tsys 70 8 ns m t Serial Input Clock Pulse Transition FSCK SCLK N 30 trsck t SIN Input Pulse Transition Time dos SIN x 30 ns SIN Input Setup Time External SCLK tsus SIN 100
43. 4 AN3 AN2 AN1 AN0 R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 SCMR CS1 CSO MAINOFF FBH RA RAO Table 8 3 Control Registers of GMS81C2120 These registers of shaded area can not be access by bit manipulation instruction as SET1 CLR1 but should be access by reg ister operation instruction as LDM dp imm 1 The register BITR and CKCTLR are located at same address Address ECH is read as BITR written to CKCTLR 2 The register PFDR only be implemented on devices not on In circuit Emulator JUNE 2001 Ver 1 00 29 GMS81C2112 GMS81C2120 8 4 Addressing The GMS800 series MCU uses six addressing modes Register addressing Immediate addressing Direct page addressing Absolute addressing Indexed addressing Register indirect addressing 1 Register Addressing Register addressing accesses the A X Y C and PSW 2 Immediate Addressing imm In this mode second byte operand is accessed as a data immediately Example 0435 ADC 35H MEMORY 04 35 A 35H C gt A When G flag is 1 then RAM address is defined by 16 bit address which is composed of 8 bit RAM paging register RPR and 8 bit immediate data Example G 1 45535 LDM 35H 55H petet gap it ae pa 0135H data data 55H 9 OF100H E4 OF101H 55 0F102H 35 1 iii die
44. 6 AN5 Analog Input 5 R66 AN6 Analog Input 6 R67 AN7 Analog Input 7 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 PIN NAME In Out DO Basic Alternate VDD Supply voltage VSS Circuit ground RA 1 1 bit high voltage Input only port High voltage input power supply pin RESET Reset signal input XIN Oscillation input XOUT Oscillation output ROO INTO I External interrupt 0 input RO1 INT1 I O 1 External interrupt 1 input R02 EC0 I O 1 8 bit high voltage I O ports Timer Counter 0 external input R03 BUZO I O O Buzzer driving output R04 R07 R20 R27 8 bit high voltage ports R30 R34 5 bit high voltage ports R53 SCLK I O Serial clock source R54 SIN 1 Serial data input R55 SOUT 5 bit high voltage ports Serial data output R56 PWM1O T1O VO O b 1 pulse output Timer Counter 1 out R57 R60 R67 ANO AN7 I 8 bit general I O ports Analog voltage input AVDD Supply voltage input pin for ADC AVSS Ground level input pin for ADC VDD Supply voltage VSS Circuit ground JUNE 2001 Ver 1 00 Table 5 1 GMS81C2120 Port Function Description GMS81C2112 GMS81C2120 6 PORT STRUCTURES
45. 6 D6 19 R67 A D7 A15 A7 D7 21 VDD VDD Connect to VDD 6 0V Table 21 1 Pin Description in EPROM Mode GMS81C2120 84 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Tse 1 TuLp2 TpLy2 gt lt Le EPROM Enable lt Vip VPP n Poe lt Tvppr CTLO 1 CTL2 OV Topi Tcpi VDD1H Tcp CTL3 ov A_D7 DATA DATA NEL pe see Xs pss Oen VDD1H VDD lt gt lt gt lt gt lt p lt p High 8bit Low 8bit Write Mode Verify Low 8bit Write Mode Verify Address Address Address Input Input Input Figure 21 3 Timing Diagram in Program Write amp Verify Mode JUNE 2001 Ver 1 00 85 GMS81C2112 GMS81C2120 After input high address output data following low address input Anothe high address step gt lt gt TsET1 es THLD2 Enable Tvpps Viup VPP Tvpps oss CTLO 1 ov VDD2H ov 2 Vpp2H T CTL3 ov 4 a X A Xt Ne e Xov Co High 8bit Low DATA Low 8bit DATA High 8bit Low DATA Address Address Output Address Output Address Address Output Input Input Input Input Input Figure 21 4 Timing Diagram in READ Mode Parameter S
46. A X CMP X OCOH BNE RAM CLR LDX OFFH Stack Pointer Initialize TXSP LD RO 0 Normal Port 0 LD ROIO 82H Normal Port Direction LD TDRO 125 8us x 125 1mS LD TMO 0 Start Timer0 8us at 4MHz LD IRQH 0 LD IRQL 0 LD IENH OEOH Enable Timer0O INTO LD IENL 0 LD IEDS 05H Select falling edge detect on INT pin LD ROFUNC 03H Set external interrupt pin INTO INT1 EI Enable master interrupt NOT USED NOP RETI JUNE 2001 Ver 1 00 25 GMS81C2112 GMS81C2120 8 3 Data Memory Figure 8 8 shows the internal Data Memory space availa ble Data Memory is divided into two groups a user RAM including Stack and control registers 00004 User Memory PAGEO When G flag 0 this page is selected 00 0 Control O0FF Registers 01004 User Memory or Stack Area gt PAGE1 When G flag 1 O1FFy Figure 8 8 Data Memory Map User Memory The GMS81C21xx have 448 x 8 bits for the user memory RAM Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device Therefore these registers contain control and status bits for the interrupt system the timer counters analog to 26 digital converters and I O ports The control registers are in address range of 0COg to OFFy Note that unoccupied addresse
47. A D result register Ree ANe gt A 6 RezAN7 gt ANSEL7 Figure 13 2 A D Block Diagram JUNE 2001 Ver 1 00 57 GMS81C2112 GMS81C2120 ENABLE A D CONVERTER v A D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT v A D START ADST 1 READ ADCR Figure 13 3 A D Converter Operation Flow A D Converter Cautions 1 Input range of AN7 to ANO The input voltage of AN7 to ANO should be within the specification range In particular if a voltage above AVDD or below AVSS is input even if within the absolute maximum rating range the conversion value for that channel can not be in determinate The conversion values of the other channels may also be affected 58 2 Noise countermeasures In order to maintain 8 bit resolution attention must be paid to noise on pins AVDD and AN7 to ANO Since the effect increas es in proportion to the output impedance of the analog in put source it is recommended that a capacitor be connected externally as shown in Figure 13 4 in order to reduce noise Analog Input AN11 ANO 100 1000pF q Figure 13 4 Analog Input Pin Connecting Capacitor 3 Pins AN7 R67 to AN0 R60 The analog input pins AN7 to ANO also function as input output port PORT R6 pins When A D conversion is per formed with any of pins AN7 to ANO selected be sure
48. E 2001 iii GMS800 Series 2 Instruction Low 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH 00 01 02 03 04 05 06 07 08 09 oa oc op 0E OF ios SET BBs BBs ADC ASL ASL TCALL POP PUSH dp bit A bit rel dp bit rel imm dp dp X labs A dp 0 bit dp A A jog ssc ssc SBC ROL ROL COM POP PUSH BRA imm dp dp X labs A dp 2 bit dp x x rel LSR LSR TCALL NOTI TST POP PUSH PCALL imm dp dp X labs A dp 4 M bit dp Y Y Upage B OR OR OR OR ROR ROR TCALL ORI CMPX POP PUSH imm dp dp X labs A dp 6 OR1B dp PSW PSW AND AND AND AND INC INC TCALL AND1 CBNE INC 100 PEERY imm dp dp X labs A dp 8 dp apx SP x EOR EOR EOR EOR DEC DEC TCALL EOR1 DBNE XMA DEC dp dp X labs A dp 10 EORIB dp apex x LDA LDA LDA LDA LDY TCALL LDC LDX LDX 140 SENG mm dp dpeX labs A dp 12 LDCB dp dp y XON DAS LDM STA STA STA sty TCALL STC STX STX E El dp imm dp dp x labs dp 14 Mbit dp STOP
49. ERRUPTS 65 Interrupt Sequence 67 Multi Interrupt a 69 External Interrupt 70 17 Power Saving 72 Operating Mode 73 Stop 74 Wake up Timer Mode 75 Internal RC Oscillated Watchdog Timer Mode 76 Minimizing Current Consumption 77 18 OSCILLATOR CIROUIT 79 19 HESE T u cata 80 External Reset Input 80 Watchdog Timer Reset 80 20 POWER FAIL PROCESSOR 81 21 OTP PROGRAMMING 83 DEVICE CONFIGURATION AREA 83 A CONTROL REGISTER LIST i B INSTRUCTION ili Terminology iii Instruction iv Instruction Set eee bete MASK ORDER xi GMS81C2112 GMS81C2120 GMS81C2112 GMS81C2120 CMOS Single Chip 8 Bit Microcontroller with A D Converter amp VFD Driver 1 OVERVIEW 1 1 Description The GMS81C2112 and GMS81C2120 are advanced CMOS 8 bit microcontroller with 12K 20K bytes of ROM These are a powerful microcontroller which provides a highly flexible
50. Function R60 ANO ADC input 0 R61 AN1 ADC input 1 R62 AN2 ADC input 2 R63 AN3 ADC input 3 R64 ADC input 4 R65 AN5 ADC input 5 R66 AN6 ADC input 6 R67 AN7 ADC input 7 The control register R6FUNC address 0F7g controls to select alternate function After reset this value is 0 port may be used as general I O ports To select alternate func 35 GMS81C2112 GMS81C2120 such as Analog Input write 1 to the corresponding bit of ROFUNC Regardless of the direction register R6IO R6FUNC is selected to use as alternate functions port pin can be used as a corresponding alternate features AN7 ANO i ADDRESS R6 Data Register RESET VALUE Undefined R6 R67 R66 R65 R64 R63 R62 R61 R60 5 Input Output data irecti i ADDRESS 0CD R6 Direction Register RESET VALUE 00 Reio Port Direction 0 Input 1 Output ADDRESS 7 R6 Function Selection Register RESET VALUE oo 0 R67 0 R60 1 AN7 1 ANO 0 R66 0 R61 1 AN6 1 AN1 36 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 10 BASIC INTERVAL TIMER The GMS81C21xx has one 8 bit Basic Interval Timer that is free run can not stop Block diagram is shown in Figure 10 1 In addition the Basic Interval Timer generates the time base for watchdog timer counting It also provides a Basic interval timer interrupt BITIF The 8 bit Basic
51. GMS87C2120 K 20K bytes OTP 448 bytes 42SDIP OTP version GMS87C2120 Q 20K bytes OTP 448 bytes 44MQFP GMS87C2120 20K bytes OTP 448 bytes 40PDIP JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 2 BLOCK DIAGRAM R07 R06 ROS ADC Power R04 Supply R03 BUZO R02 EC0 i RO1 INT1 z z ROO INTO R20 R27 R30 R34 Vdisp RA Driver Buzzer 4 Pointer Data Memory 448 bytes Program Memory Interrupt Controller Data Table System controller 8 bit Basic i Interval System Clock Controller 8 bit 8 bit serial PC Timing generator Watchdog Timer Interface Timer Counter Clock Generator R53 SCLK R60 ANO im 8 8 R54 SIN R61 AN1 gt gt gt R55 SOUT R62 AN2 s R56 PWM10 T10 ANa R57 Supiy R65 AN5 R66 AN6 R67 AN7 High Voltage Port JUNE 2001 Ver 1 00 3 GMS81C2112 GMS81C2120 3 ASSIGNMENT
52. H XY SAVE Y REG interrupt processing POP Y RESTORE Y REG POP X RESTORE X REG POP A RESTORE ACC RETI RETURN General purpose register save restore using push and pop instructions main task acceptance of interrupt service task saving registers restoring registers 68 16 2 BRK Interrupt Software interrupt can be invoked by BRK instruction which has the lowest priority order Interrupt vector address of BRK is shared with the vector of TCALL 0 Refer to Program Memory Section When BRK interrupt is generated B flag of PSW is set to distin guish BRK from TCALL 0 Each processing step is determined by B flag as shown in Figure 16 5 BRK or TCALLO BRK INTERRUPT ROUTINE TCALLO ROUTINE Figure 16 5 Execution of BRK TCALLO JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 16 3 Multi Interrupt If two requests of different priority levels are received si multaneously the request of higher priority level is ser viced If requests of the interrupt are received at the same time simultaneously an internal polling sequence deter mines by hardware which request is serviced Main Program service TIMER 1 service INTO hable INTO Service disable other 1 El Occur gt Occur TIMER1 interrupt INTO enable INTO enable other In this example the INTO inter
53. IO R6 Port Direction Register Bit 7 0 DOH TMO CAPO TOCK2 TOCK1 TOCKO TOCN TOST D1H quu TimerO Register TimerO Data Register CaptureO Data Register D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CKO T1CN 15 D3H Timer1 Data Register PWM1 Period Register D4H Pe Timer1 Register Capture1 Data Register PWM1 Duty Register D5H PWM1HR PWM1 High Register Bit 3 0 DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BURO EOH SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR SPI DATA REGISTER E2H IENH INTOE INT1E TOE IENL ADE WDTE BITE SPIE E4H IRQH INTOIF INT1IF TOIF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF E6H IEDS IED1H IED1L IEDOH IEDOL ADCM ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register Basic Interval Timer Data Register CKCTLR WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 EDH WDTR WDTCL 7 bit Watchdog Counter Register EFH PFDR2 PFDIS PFDM PFDS F4H ROFUNG BUZO ECO INT1 INTO Table 8 3 Control Registers of GMS81C2120 These registers of shaded area not be access by bit manipulation instruction as SET1 CLR1 but should be access by reg ister operation instruction as LDM dp imm 28 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F6H R5FUNC 4 F7H AN6 AN5 AN
54. J 22 External Interrupt Executed 22 Instruction mnngunninni BIT Counter n Yn Yn 2 Stop Operation Clear Ux 1 X 2 gt 20ms by software Before executing Stop instruction Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms Figure 17 2 STOP Mode Release Timing by External Interrupt Oscillator XI pin 22 F STOP Internal Clock Internal We TEM uu RESETB STOP Instruction Execution Time can not be control by software dan Stabilization Time EI tsr 64mS 4MHz Figure 17 3 Timing of STOP Mode Release by RESET 17 3 Wake up Timer Mode In the Wake up Timer mode the on chip oscillator is not stopped Except the Prescaler only 2048 divided ratio and Timer0 all functions are stopped but the on chip RAM and Control registers are held The port pins out the values held by their respective port data register port direction registers The Wake up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to 1 This register should be written by byte operation If this register is set by bit manipulation instruction for example set1 or
55. JUNE 2001 Ver 1 00 HYNIX SEMICONDUCTOR 8 BIT SINGLE CHIP MICROCONTROLLERS GMS81C2112 GMS81C2120 User s Manual Semiconductor HYNIX SEMICONDUCTOR 8 BIT SINGLE CHIP MICROCONTROLLERS GMS81C2112 GMS81C2120 User s Manual Ver 1 00 n hynix Semiconductor Version 1 00 Published by MCU Application Team 2001 HYNIX Semiconductor All right reserved Additional information of this manual may be served by HYNIX Semiconductor offices in Korea or Distributors and Rep resentatives listed at address directory HYNIX Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however HYNIX Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual Table of Contents OVERVIEW ui ctc doo 1 Description e ote a e ae fe d 1 oce ule eite es 1 Development Tools 2 Ordering Information 2 2 BLOCK DIAGRAVM 3 3 PIN ASSIGNMENT 4 4 PACKAGE DIAGRAM 6 5 PIN FUNCTION 8 6 PORT STRUCTURES 10 7 ELECTRICAL CHARACTERISTICS 13 Absolute Maximum Ratings
56. Mask Data 120 2000 Set 00 in blanked area Please check markv into O Customer s logo Customer logo is not required If the customer logo must be used in the special mark please submit a clean original of the logo see ceca Ol EDU 4 Delivery Schedule Customer sample Quantity HYNIX Confirmation Risk order 5 ROM Code Verification Please confirm out verification data Approval date E mail address Name amp Signature YYYY MM DD Verification date Check sum Tel Fax I agree with your verification data and confirm you to make mask set Tel Fax E mail address Name amp Signature GMS81C21XX MASK OPTION LIST Customer should write inside thick line box 1 RA Vdisp RA without pull down resistor Please check markV into D 2 CONFIG OPTION Check X X HFEA CONFIG Default Value XX00X0X0 ADDRESS 703 INITIAL VALUE 00 0 0g CONFIG es oes External RC OSC Selection 0 Crystal or Resonator Oscillator 1 External RC Oscillator PFD Level Selection Code Protect 00 PFD 2 7V 0 Allow Code Read Out 01 PFD 27 1 Lock Code Read Out 10 PFD 3
57. OFUNC Port selection OF 4y Internal bus line Figure 15 1 Block Diagram of Buzzer Driver ADDRESS RESET VALUE 0000g ADDRESS 0DE RESET VALUE Undefined W W W W W W W W ROFUNC ECO INT INTO L BUR 5 0 Buzzer Period Data R0O3 BUZO Selection Source clock select 0 port Turn off buzzer 00 8 1 BUZO port Turn buzzer 01 16 10 32 11 64 Figure 15 2 ROFUNC and Buzzer Register JUNE 2001 Ver 1 00 63 GMS81C2112 GMS81C2120 Note BUR is undefined after reset so it must be initialized to between and by software Note that BUR is a write only register The 6 bit counter is cleared and starts the counting by writ ing signal at BUR register It is incremental from 00g until it matches 6 bit BUR value When main frequency is 4MHz buzzer frequency is shown as below table 5 0 00 01 10 11 5 0 00 01 10 11 00 250 000 125 000 62 500 31 250 20 7 576 3 788 1 894 0 947 01 125 000 62 5001 31 250 15 625 21 7 353 3 676 1 838 0 919 02 83 333 41 667 20 833 10 417 22 7 143 3 571 1 786 0 893 03 62 5001 31 250 15 625 7 813 23 6 944 3 472 1 736 0 868 04 50 000 25 000 12 500 6 250 24 6 757 3 378 1 689 0 845 05 41 667 20 833 10 417 5 208 25 6 579 3 289 1 645 0 822 06 35 714 17 857 8 929 4 464 26 6 410 3 205 1 603 0 801 07 31 250 15 625 7 813 3 9
58. OP mode is hardware reset or external in terrupt Reset re defines all the Control registers but does not change the on chip RAM External interrupts allow both on chip RAM and Control registers to retain their val ues If I flag 1 the normal interrupt response takes place If I flag 0 the chip will resume execution starting with the instruction following the STOP instruction It will not vec tor to interrupt service routine refer to Figure 17 1 When exit from Stop mode by external interrupt enough oscillation stabilization time is required to normal opera tion Figure 17 2 shows the timing diagram When release the Stop mode the Basic interval timer is activated on wake up It is increased from 00g until The count overflow is set to start normal operation Therefore before STOP instruction user must be set its relevant prescaler di vide ratio to have long enough time more than 20msec This guarantees that oscillator has started and stabilized By reset exit from Stop mode is shown in Figure STOP INSTRUCTION STOP Mode Interrupt Request Corresponding Interrupt Enable Bit IENH IENL 1 STOP Mode Release Master Interrupt Enable Bit PSW 2 Interrupt Service Routine Next INSTRUCTION Figure 17 1 STOP Releasing Flow by Interrupts JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Oscillator Xin pin TILL Internal Clock 11 LJ LJ L
59. Port 38 I O Lines Noise Immunity Circuit Enhanced EMS 34 Programmable I O pins Improvement Included 21 high voltage pins Max 40V Power Fail Processor Three Input Only pins 1 high voltage pin Noise Immunity Circuit One Output Only pin Eight Interrupt Sources Two External Sources INTO INT1 Two Timer Counter Sources 0 Timer1 Four Functional Sources SPI ADC WDT BIT JUNE 2001 Ver 1 00 1 GMS81C2112 GMS81C2120 1 3 Development Tools The GMS81C21xx are supported by a full featured macro assembler an in circuit emulator CHOICE Dr and OTP programmers There are third different type program mers such as emulator add on board type single type gang type For mode detail Refer to 21 OTP PROGRAM MING on page 83 Macro assembler operates under the MS Windows 95 98 Please contact sales part of HynixSemiconductor In Circuit Emulators CHOICE Dr Socket Adapter OA87C21XX 42SD 42SDIP for OTP OA87C21XX 44QF 44MQFP POD CHPOD81C21D 42SD 42SDIP CHPOD810C21D 40PD 40PDIP Assembler HYNIX Macro Assembler 1 4 Ordering Information Device name ROM Size RAM size Package GMS81C2112 12K bytes 448 bytes 42SDIP GMS81C2112 Q 12K bytes 448 bytes 44MQFP Mask version GMS81C2112 12K bytes 448 bytes 40PDIP GMS81C2120 K 20K bytes 448 bytes 42SDIP GMS81C2120 Q 20K bytes 448 bytes 44MQFP GMS81C2120 20K bytes 448 bytes 40PDIP
60. R01 1 INT1 0 R02 1 ECO 0 R03 1 BUZO MSB LSB RW RW RW RW I ADDRESS 0E6 IEDS iED1HiIED1L IEDOH IEDOL INITIAL VALUE 00008 Edge selection register 00 Reserved 01 Falling 1 to 0 transition 10 Rising 0 to 1 transition 11 Both Rising amp Falling Figure 16 9 ROFUNC and IEDS Registers JUNE 2001 Ver 1 00 71 GMS81C2112 GMS81C2120 17 Power Saving For applications where power consumption 15 critical factor device provides four kinds of power saving func tions STOP mode Sub active mode and Wake up Timer mode Stand by mode Watch mode Table 17 1 shows the status of each Power Saving Mode The power saving function is activated by execution of STOP instruction and by execution of STOP instruction af ter setting the corresponding status WAKEUP of CKCTLR We shows the release sources from each Power Saving Mode Wake up Timer Wake up Timer Peripheral STOP Mode Mode Release Source STOP Mode Mode Stand by Mode Stand by Mode RAM Retain Retain RESET Control Registers Retain Retain RCWDT I O Ports Retain Retain EXT INTO CPU Stop Stop EXT INT1 v P 0 Stop Operation Timer0 X O Oscillation Stop Oscillation Table 17 2 Release Sources from Power Saving Mode Prescaler Stop 2048 only Entering Condition 0 1 WAKEUP Table 17 1 Power Saving Mode 72 JUNE 2001 Ver 1 00 GMS81C2112
61. R53 POL 0 E Yor L TEA ser Hi HO HH HH sw rss 55 EH SIOSF I SPI Status SPIIF SPI Int Req Figure 14 3 SPI Timing Diagram at POL 0 SIOST SCLK R53 POL 1 a E 0000 0 os 050180 UD rdi 25 SIOSF SPI Status SPIIF SPI Int Req Figure 14 4 SPI Timing Diagram at POL 1 JUNE 2001 Ver 1 00 61 GMS81C2112 GMS81C2120 14 2 The method of Serial I O D Select transmission receiving mode 4 The SIO interrupt is generated at the completion of SIO and SIOSF is set to 1 In SIO interrupt service routine Note When external clock is used the frequency should correct transmission should be tested be less than 1MHz and recommended duty is 5076 5 In case of receiving mode the received data is acquired by reading the SIOR 2 In case of sending mode write data to be send to SIOR 8 Set SIOST to 1 to start serial transmission Note If both transmission mode is selected and transmis sion is performed simultaneously it would be made error 14 3 The Method to Test Correct Transmission Serial Interrupt Service Routine 0 SIOSF 1 SE 0 Abnormal Write SIOM gt 1 Normal Operation Overrun Error SE Interrupt Enable Register Low IENL Bit3 SR Interrupt Request F
62. S flag PFSO bit Level Selection PFS1 bit Mask option Table 20 1 Power fail processor RW R W R W 1 0 PFDR PFDIS PEDM ADDRESS OEFy __________________ Disable Flag INITIAL VALUE 100g Power Fail Status 0 Normal operate 1 Set to 1 if power fail is detected Operation Mode 0 Normal operation regardless of power fail 1 will be reset by power fail detection 0 Power fail detection enable 1 Power fail detection disable Figure 20 1 Power Fail Voltage Detector Register JUNE 2001 Ver 1 00 81 GMS81C2112 GMS81C2120 RESET VECTOR ee YES NO RAM CLEAR INITIALIZE RAM DATA INITIALIZE ALL PORTS INITIALIZE REGISTERS 0 FUNTION EXECUTION Skip the initial routine Figure 20 2 Example S W of RESET flow by Power fail When PFR 1 Vpp Internal RESET Internal RESET Vpp Internal RESET Peseta ee cee VprpMAX ME SM Soap MARS SSI UD Ua kuya ars e VprEpMIN re PON TS DuC SUP de M B gt VprpMIN lt gt 64 5 t 64mS B 4 VpFDMIN 82 Figure 20 3 Power Fail Processor Situations JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 21 OTP PROGRAMMING 21 1 DEVICE CONFIGURATION AREA The Device Configuration Area ca
63. STOP Instruction 4 Interrupt Execution Request Normal Operation gt lt Wake up Timer Mode gt lt Normal Operation stop the CPU clock Do not need Stabilization Time Figure 17 4 Wake up Timer Mode Releasing by External Interrupt or 0 Interrupt 17 4 Internal RC Oscillated Watchdog Timer Mode In the Internal RC Oscillated Watchdog Timer mode the on chip oscillator is stopped But internal RC oscillation circuit is oscillated in this mode The on chip RAM and Control registers are held The port pins out the values held by their respective port data register port direction regis ters The Internal RC Oscillated Watchdog Timer mode is activated by execution of STOP instruction after set ting the bit WAKEUP and RCWDT of CKCTLR to 01 This register should be written by byte operation If this register is set by bit manipulation instruction for example set1 or clr1 instruction it may be unde sired operation Note Caution After STOP instruction at least two or more NOP instruction should be written Ex LDM WDTR 1111 1111B LDM CKCTLR 0010_1110B STOP NOP NOP The exit from Internal RC Oscillated Watchdog Timer mode is hardware reset or external interrupt Reset re de fines all the Control registers but does not change the on chip RAM External interrupts allow both on chip RAM 76 and Control registers to retain
64. The PSW is described in Figure 8 3 It contains the Negative flag the Overflow flag the Break flag the Half Carry for BCD operation the Interrupt enable flag the Zero flag and the Carry flag Carry flag C This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction Zero flag Z This flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 MSB NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when G 1 page is selected to page 1 BRK FLAG psw 1 7 varus 00 LSB CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 8 3 PSW Program Status Word Register Interrupt disable flag I This flag enables disables all interrupts except interrupt caused by Reset or software BRK instruction All inter rupts are disabled when cleared to 0 This flag immedi ately becomes 0 when an interrupt is served It is set by the EI instruction and cleared by the DI instruction Half carry flag H After operation this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU This bit can not be set or cleared except CLR V instruction wi
65. When write Addr Timer Capture PWM Timer PWM Mode Mode Mode Mode Mode D1H TO CDRO TDR0 D3H TDR1 D4H T1 CDR1 TIPDR T1PDR ECH BITR CKCTLR Address Symbol R W i e RO R W Undefined byte bit 0 ROIO W 0000_0000 byte 0C4H R2 R W Undefined byte bit 0C5H R2IO W 0000_0000 byte 0C6H R3 R W Undefined byte bit 0C7H W 0 0000 byte OCAH R5 R W Undefined byte bit OCBH R5IO W 0000 0 byte 0CCH R6 R W Undefined byte bit OCDH R6IO W 0000_0000 byte 0D0H TMO R W 00 0000 byte bit 0D1H TO R 0000_0000 byte 0D1H TDR0 1111 1111 byte OD1H CDRO R 0000_0000 byte 0D2H TM1 R W 0000_0000 byte bit 0D3H TDR1 w 1111 1111 byte 0D3H T1PPR 1111 1111 byte 0D4H T1 R 0000_0000 byte 0D4H CDR1 R 0000_0000 byte 0D4H T1PDR R W 0000_0000 byte bit OD5H PWM1HR W 0000 byte ODEH BUR W 1111 1211 byte OEOH SIOM R W 0000_0001 byte bit OE1H SIOR R W Undefined byte bit OE2H IENH R W 0000 byte bit IENL R W 0000 byte bit 4 R W 0000_ byte bit OE5H IRQL R W 0000 byte bit OE6H IEDS R W _0000 byte bit OEAH ADCM R W 000_0001 byte bit OEBH ADCR R Undefined byte OECH BITR R 0000 0000 byte CKCTLR W 001 0111 byte OEDH WDTR R 0000 0000 byte OEDH WDTR 0111_1111 byte OEFH PFDR R W _ 100 byte bit OF4H ROFUNC
66. and cost effective solution to many VFD applications These pro vide the following standard features 12K 20K bytes of ROM 448 bytes of RAM 8 bit timer counter 8 bit A D converter 10 bit High Speed PWM Output Programmable Buzzer Driving Port 8 bit Basic Interval Timer 7 bit Watch dog Timer Serial Peripheral Interface on chip oscillator and clock circuitry They also come with high voltage I O pins that can directly drive a VFD Vacuum Fluorescent Display In addition the GMS81C2112 and GMS81C2120 support power saving modes to reduce power consumption Device name ROM Size RAM Size OTP Package GMS81C2112 12K bytes 42SDIP 44MQFP 448 bytes GMS81C2120 20K bytes GMS87C2120 40PDIP 1 2 Features 20K 12K bytes ROM EPROM 8 Channel 8 bit On Chip Analog to Digital Con 448 Bytes of On Chip Data RAM verter Including STACK Area Oscillator Minimum Instruction Execution time Crystal 1uS at 4MHz 2cycle NOP Instruction Ceramic Resonator External R Oscillator One 8 bit Basic Interval Timer Low Power Dissipation Modes One 7 bit Watch Dog Timer STOP mode Two 8 bit Timer Counters Wake up Timer Mode 5 M 10 bit High Speed PWM Output Standby Mode One 8 bit Serial Peripheral Interface Operating Voltage 2 7V 5 5V at 4 5MHz Operating Frequency 1MHz 4 5MHz Two External Interrupt Ports Enhanced EMS Improvement Power Fail Processor One Programmable 6 bit Buzzer Driving
67. ar amp Start Timer Stop Figure 12 9 Input Capture Operation Ext INTO Pin Interrupt Request INTOF lt Interrupt Interval Period FF 01 014 134 213 Interrupt Request TOF TO Figure 12 10 Excess Timer Overflow in Capture Mode JUNE 2001 Ver 1 00 51 GMS81C2112 GMS81C2120 12 5 16 bit Capture 16 bit capture mode is the same as 8 bit capture except or external clock by bit TOCK2 and Q In 16 bit mode the bits TICK1 T1CKO and 16BIT of TM1 The clock source of the Timer 0 is selected either internal should be set to 1 respectively 9 X S ce d om ADDRESS 0D0 H TM0 TOCK2 TOCK1TTOCKO TOST INITIAL VALUE 0000005 1 x x x X x X means don t care 7 6 5 4 3 2 1 0 ADDRESS 0D2 TM1 16BIT CAP1 T1CK1T1CK0 1 T1ST NIAE VALUE 00 x 1 0 x 1 1 X X TOCK 2 0 X means don t care Edge Detector TOST 0 Stop 1 Clear and start TDR1 TDRO E 16 bit a TOCN Capture CDR1 16 bit IEDS 1 0 Higher byte Lower byte CAPTURE DATA or INTO PIN pppoe INToF MIO INTERRUPT Ar Figure 12 11 16 bit Capture Mode 52 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Example 1 Timer0 16 bit timer mode 0 5s at 4MHz LDM TMO 0000_1111B 8uS LDM TM1 40
68. atically when A D conversion is completed cleared when A D conver sion is in process The conversion time takes maximum 20 uS at fXI 4 MHz 7 6 5 4 3 2 ADCM F ADENI RW RW RW RW RW R 0 ADS2 ADS1 ADS0 ADST ADSF ADDRESS INITIAL VALUE 0 0 00018 A D status bit 0 A D conversion is in progress 1 A D conversion is completed A D start bit Setting this bit starts an A D conversion After one cycle bit is cleared to O by hardware Analog input channel select 000 Channel 0 ANO 001 Channel 1 AN1 010 Channel 2 AN2 011 Channel 3 AN3 100 Channel 4 AN4 101 Channel 5 AN5 110 Channel 6 AN6 111 Channel 7 AN7 A D converter Enable bit 0 ADCR A D Conversion Data ADDRESS INITIAL VALUE Undefined 0 A D converter module turn off and current is not flow 1 Enable A D converter Figure 13 1 A D Converter Control Register 56 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 R6FUNC 7 0 ADS 2 0 Y Reo ANO gt w A ANSELO gt LADDER RESISTOR ANSELI RezAN2 gt 8 bit DAC sam ResANS gt 1 A D ANSEL3 SUCCESSIVE INTERRUPT i i APPROXIMATION Resana gt S H CIRCUIT ANSEL4 Sample amp Hold Resans gt ADDRESS E94 ADR 8 bit RESET VALUE Undefined 5
69. ature Voltage on Normal voltage pin with respect to Ground Vss Voltage on High voltage pin with respect to Ground Vss Maximum current out of pin Maximum current into Vpp pin Maximum current sunk by per I O Pin 0 3 to 7 0 V 40 to 85 C 7 2 Recommended Operating Conditions Maximum output current sourced by per I O Pin 8 Maximum current 10102 100 mA Maximum current 50 mA Note Stresses above those listed under Absolute Maxi mum Ratings may cause permanent damage to the de vice This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability Parameter Symbol Condition Unit Min Max Supply Voltage Vpp fy 4 5 MHz 2 7 5 5 V Operating Frequency 1 4 5 MHz Operating Temperature ToPR 40 85 C 7 3 A D Converter Characteristics Ta 25 C Vpp 5V Vss 0V 5 12 AVss 0V 4MHz Specifications Parameter Symbol Condition Unit Min Typ Max Analog Power Supply Input Voltage Range AVpp AVss AVpp Analog Input Voltag
70. ces POL 4 own songe Push Pop puse IPOp VET OIFD PCL down 01FD OIFD _ PCL up 01FC PSW lt 01FG 01FC PSW lt 01FB 01FB 01 OFB SP before execution 01 01 01FC 01FB SP after execution 01FC 01FB 01 01 At execution At execution of PUSH instruction of POP instruction PUSH A X Y PSW POP A X Y PSW O1FE en O1FE d 0100H 7 W u Stack 01FD 01FD depth 01FC 01FC gt 1FB 1FB ITE 9 01FEH SP before execution 01 01FD SP after execution 01 Figure 8 4 Stack Operation 22 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 8 2 Program Memory A 16 bit program counter is capable of addressing up to 64K bytes but this device has 20K bytes program memory space only physically implemented Accessing a location above FFFFy will cause a wrap around to 0000 Figure 8 5 shows a map of Program Memory After reset the CPU begins execution from reset vector which is stored in address FFFEy and FFFFy as shown in Figure 8 6 As shown in Figure 8 5 each area is assigned a fixed loca tion in Program Memory Program Memory area contains the user program TCALL area Interrupt Vector Area PCALL area L GMS81C2120 20K ROM 1 1 GMS81C2112 12K ROM Figure 8 5 Program Memory Map Page Call PCALL area contains subroutine program to reduce program byte length by usin
71. clr1 instruction it may be undesired operation Note After STOP instruction at least two or more NOP in JUNE 2001 Ver 1 00 struction should be written Ex LDM TDRO 0FFH LDM 0 40001 1011B LDM CKCTLR 20100 1110B STOP NOP NOP In addition the clock source of timerO should be selected to 2048 divided ratio Otherwise the wake up function can not work And the timer0 can be operated 16 bit timer with timerl refer to timer function The period of wake up function is varied by setting the timer data register 0 TDRO 75 GMS81C2112 GMS81C2120 Release the mode The exit from Wake up Timer mode is hardware reset Timer0 overflow or external interrupt Reset re defines all the Control registers but does not change the on chip RAM External interrupts and Timer0 overflow allow both on chip RAM and Control registers to retain their values If I flag 1 the normal interrupt response takes place If I flag 0 the chip will resume execution starting with the instruction following the STOP instruction It will not vec tor to interrupt service routine refer to Figure 17 1 When exit from Wake up Timer mode by external inter rupt or timer0 overflow the oscillation stabilization time is not required to normal operation Because this mode do not stop the on chip oscillator shown as Figure 17 4 Oscillator XI pin 22 CPU Clock
72. ddress In the capture mode reading operation is read the CDRx not Tx because path is opened to the CDRx and TDRx is only for writing operation It has three transition modes falling edge rising edge both edge which are selected by interrupt edge selection register IEDS Refer to External interrupt section In ad dition the transition at INTx pin generate an interrupt 49 GMS81C2112 GMS81C2120 7 ADDRESS 0D0 6 5 4 3 2 1 0 1251 INITIAL VALUE 000000 1 X xX X X X X means don t care 7 6 5 4 3 2 1 0 ADDRESS 0D2 TM1 16BIT CAP1 T1CK1T1CK0 1 TIST INITIAL VALUE 00 X 0 0 1 x X x X means don t care TOCK 2 0 Edge Detector PIN TOST 0 Stop XIN PIN 1 Clear and start TO 8 bit Prescaler Capture CDRO 8 bit IEDS 1 0 E 01 10 gt INTO INTO PIN menm EX INTOIF NTERR RT Ajar TIST 0 Stop 1 Clear and start T1 8 bit TICN MUX Capture CDR1 8 bit IEDS 1 0 A rn 10 INT INT1 PIN d gt INTERRUPT Figure 12 8 8 bit Capture Mode 50 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 n This value is loaded to CDRO TO TIME Ext INTO Pin Interrupt Request INTOF Interrupt Interval Period Ext INTO Pin Interrupt Request INTOF ra lt Delay Capture Cle
73. e Range VAN AV ss 0 3 AVpp 0 3 Current Following PEN _ _ 200 Between AVpp Overall Accuracy CAN 2 LSB Non Linearity Error NNLE 2 LSB Differential Non Linearity Error NpNLE 2 LSB Zero Offset Error NzoE 2 LSB Full Scale Error Nese 2 LSB Gain Error NNLE 2 LSB Conversion Time TcoNv 4 2 20 us 1 Data in Typ column is at 25 C unless otherwise stated These parameters are for design guidance only and are not tested JUNE 2001 Ver 1 00 13 GMS81C2112 GMS81C2120 7 4 DC Electrical Characteristics for Standard Pins 5V Vpp 5 0V 10 Vss TA 40 85 C 4 MHz Vpp 40V to Specification Parameter Pin Symbol Test Condition Unit Min 1 XIN External Clock 0 9Vpp Vpp 0 3 RESET SIN R55 SCLK Input High Voltage INTO amp 1 ECO Vino 0 8Vpp 0 3 V R53 R57 R6 0 7 Vpp 0 3 XIN Vii External Clock 0 3 0 1Vpp RESET SIN R55 SCLK 5 33 5 E 2V Input Low Voltage INTO amp 1 ECO Vite 0 3 0 2Vpp V R53 R57 R6 0 3 0 3Vpp Output High R53 R57 R6 BUZO V lauz 0 5mA Vnn 0 5 Voltage PWM10 T10 SCLK SOUT Output Low R53 R57 R6 BUZO Vout lo 1 6mA 0 4 V Voltage PWM10 T10 SCLK SOUT Vote lo 10mA 2 Input High x Leakage Current fos n 1 uA Input Low m Leakage Current
74. e duty data is trans ferred from the master to the slave when the period data matched to the counted value i e at the beginning of next duty cycle PWM Period PWM1HR 3 2 T1PPR X Source Clock PWM Duty PWM1HR 1 0 T1PDR X Source Clock The relation of frequency and resolution is in inverse pro portion Table 12 2 shows the relation of PWM frequency vs resolution 53 GMS81C2112 GMS81C2120 If it needed more higher frequency of PWM it should be reduced resolution The bit POL of TMI decides the polarity of duty cycle If the duty value is set same to the period value the PWM output is determined by the bit POL 1 High 0 Low And if the duty value is set to 00g the PWM output is deter mined by the bit POL 1 Low 0 High It can be changed duty value when the PWM output How ever the changed duty value is output after the current pe riod is over And it can be maintained the duty value at present output when changed only period value shown as Frequency Resolution T4CK 1 0 T1CK 1 0 T1CK 1 0 00 250nS 01 500nS 10 2uS 10 bit 3 9KHz 0 98KHZ 0 49KHZ 9 bit 7 8KHz 1 95KHz 0 97KHz 8 bit 15 6KHz 3 90KHz 1 95KHz 7 bit 31 2KHz 7 81KHz 3 90KHz Figure 12 14 As it were the absolute duty time is not changed in varying frequency But the changed period val Table 12 2 PWM Frequency vs Resolution at 4MHz ue must greater than the duty value
75. ection flag TOCK2 TMO 4 000 8 bit Timer Clock source is 2 TOCK1 TM0 3 001 8 bit Timer Clock source is 4 TOCKO 0 2 010 8 bit Timer Clock source is 8 011 8 bit Timer Clock source is 32 100 8 bit Timer Clock source is fq 128 101 8 bit Timer Clock source is 512 110 8 bit Timer Clock source is 2048 111 ECO External clock TOCN TMO 1 0 Stop the timer 1 A logic 1 starts the timer TOST 0 0 0 When cleared stop the counting 1 When set Timer 0 Count Register is cleared and start again RW RW RW RW RW RW RW RW ADDRESS 0D24 7 6 5 4 3 2 1 0 INITIAL VALUE 00 Bit Name Position Description POL TM1 7 0 PWM Duty Active Low 1 PWM Duty Active High 16BIT TM1 6 0 8 bit Mode 1 16 bit Mode PWMIE TM1 5 0 Disable PWM 1 Enable PWM CAP1 TM1 4 0 Timer Counter mode 1 Capture mode selection flag T1CK1 TM1 3 00 8 bit Timer Clock source is fxIN T1CKO TM1 2 01 8 bit Timer Clock source is 2 10 8 bit Timer Clock source is 8 11 8 bit Timer Clock source is Using the the Timer 0 Clock TOCN TM1 1 0 Stop the timer 1 A logic 1 starts the timer TOST 1 0 0 When cleared stop the counting 1 When set Timer 0 Count Register is cleared and start again R W RW R W RW R W RW R W R W 7 6 5 4 3 2 1 0 ADDRESS 0D1 H T T T T MPAEVALUE nates R W R W R W R W R W R W R W R W 7 6 5
76. el Note In the STOP operation the power dissipation asso Vss however when the input level becomes higher current if it is practical JUNE 2001 Ver 1 00 77 GMS81C2112 GMS81C2120 than the power voltage level by approximately 0 3V rent begins to flow Therefore if cutting off the output tran sistor at an I O port puts the pin signal into the high impedance state a current flow across the ports input tran sistor requiring it to fix the level by pull up or other means It should be set properly in order that current flow through port doesn t exist First conseider the setting to input mode Be sure that there is no current flow after considering its relationship with external circuit In input mode the pin impedance viewing from external MCU is very high that the current doesn t flow But input voltage level should be or Vpp Be careful that if unspecified voltage i e if unfirmed voltage level not Vssor Vpp is applied to input pin there can be little current max ImA at around 2 V flow If it is not appropriate to set as an input mode then set to output mode considering there is no current flow Setting to High or Low is decided considering its relationship with external circuit For example if there is external pull up re sistor then it is set to output mode i e to High and if there is external pull down register it is set to low INPUT PIN Vpp Vpp internal pu
77. er 1 data register TDR1 11111111 44 PWM 1 period register T1PPR w 1311114111 54 Timer 1 register T1 R 00000000 48 0004 PWM 1 duty register T1PDR R W 00000000 54 Capture 1 register CDR1 R 00000000 50 0005 PWM 1 High register PWM1HR W 00 0 0 54 00DE Buzzer driver register BUR w 11111111 63 00 0 Serial mode register SIOM R W 00000001 60 00E1 Serial I O data register SIOR R W Undefined 60 00E2 Interrupt enable register high IENH R W 0000 66 00 Interrupt enable register low IENL R W 0000 66 00 4 Interrupt request register high IRQH R W 0000 65 0025 Interrupt request register low IRQL R W 0 0 0 0 1 65 00 6 External interrupt edge selection register IEDS R W 010010 71 A D converter mode register ADCM R W 1010101001011 56 00 A D converter data register ADCR R Undefined 56 Basic interval timer mode register BITR R 00000000 38 Clock control register CKCTLR w 0 0111011111 38 00ED Watchdog Timer Register WDTR R 00000000 40 Watchdog Timer Register WDTR W 011111111114 40 00 Power fail detection register PFDR R W 1 0 0 81 JUNE 2001 i GMS800 Series Address Register Name Symbol R W au Page 76 5141321110 00 4 R0 Function selection register ROFUNG 10101010 34 00 6 R5 Function selection register R5FUNG O
78. g 2 bytes PCALL in stead of 3 bytes CALL instruction If it is frequently called it is more useful to save program byte length Table Call TCALL causes the CPU to jump to each TCALL address where it commences the execution of the service routine The Table Call service area spaces 2 byte for every TCALL OFFCOg for TCALL15 OFFC2q for TCALLI14 etc as shown in Figure 8 7 JUNE 2001 Ver 1 00 Example Usage of TCALL LDA 5 TCALL OFH 1BYTE INSTRUCTION INSTEAD OF 3 BYTES NORMAL CALL TABLE CALL ROUTINE FUNC A DA RGO gt RE FUNC_B DA RG1 RE TABLE CALL ADD AREA ORG OFFCOH TCALL ADDRESS AREA DW FUNC A DW FUNC B The interrupt causes the CPU to jump to specific location where it commences the execution of the service routine The External interrupt 0 for example is assigned to loca tion The interrupt service locations spaces 2 byte interval OFFF8g and OFFF9q for External Interrupt 1 OFFFAy and OFFFBy for External Interrupt 0 etc Any area from OFF00g to OFFFFy if it is not going to be used its service location is available as general purpose Program Memory Address Vector Area Memory OFFEOH E2 FE RESET Vector Area NOTE means reserved area Figure 8 6 Interrupt Vector Area 23 GMS81C2112 GMS81C2120 Address PCALL Area Memory Address Program Memory OFFOO
79. high voltage CMOS bidirectional I O port RO pins 1 or 0 written to the Port Direction Reg ister can be used as outputs or inputs In addition RO serves the functions of the various following special fea tures Port pin Alternate function R00 INTO External interrupt 0 R01 INT1 External interrupt 1 R02 ECO Event counter input ROS BUZO Buzzer driver output R20 R27 R2 is an 8 bit high voltage CMOS bidirectional I O port R2 pins 1 or 0 written to the Port Direction Reg ister can be used as outputs or inputs R30 R34 R3 is a 5 bit high voltage CMOS bidirectional I O port R3 pins 1 or 0 written to the Port Direction Reg ister can be used as outputs or inputs R53 R57 R5 is an 5 bit CMOS bidirectional I O port R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs In addition R5 serves the func tions of the various following special features Port pin Alternate function R53 SCLK Serial clock R54 SIN Serial data input R55 SOUT Serial data output R56 PWM10O PWM1 Output T1O Timer Counter 1 output R60 R67 R6 is an 8 bit CMOS bidirectional I O port R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs In addition R6 is shared with the ADC input Port pin Alternate function R60 ANO Analog Input O R61 AN1 Analog Input 1 R62 AN2 Analog Input 2 R63 ANS Analog Input 3 R64 ANA Analog Input 4 R6
80. igned to be used either with a ce ramic resonator or crystal oscillator Since each crystal and ceramic resonator have their own characteristics the user should consult the crystal manufacturer for appropriate values of external components Oscillation circuit is designed to be used either with a ce ramic resonator or crystal oscillator Since each crystal and ceramic resonator have their own characteristics the user should consult the crystal manufacturer for appropriate values of external components In addition see Figure 18 2 for the layout of the crystal Note Minimize the wiring length Do not allow the wiring to intersect with other signal conductors Do not allow the wir ing to come near changing high current Set the potential of the grounding position of the oscillator capacitor to that of Vss Do not ground it to any ground pattern where high cur rent is present Do not fetch signals from the oscillator JUNE 2001 Ver 1 00 22 22422 Figure 18 2 Layout of Oscillator PCB circuit 79 GMS81C2112 GMS81C2120 19 RESET The GMS81C21xx have two types of reset generation pro cedures one is an external reset input the other is a watch dog timer reset Table 19 1 shows on chip hardware ini tialization by reset action On chip Hardware Initial Value On chip Hardware Initial Value Program counter PC FFFFH FFFE Peri
81. individually as input and output through the R5IO register address OCBy In addition Port R5 is multiplexed with Pulse Width Modulator PWM Port Pin Alternate Function PWM1 Data Output Timer 1 Data Output R56 The control register RSFUNC address controls to select PWM function After reset the R5IO register value is 0 port may be used as general I O ports To select PWM function write 1 to the corresponding bit of JUNE 2001 Ver 1 00 R5FUNC The control register RSNODR address 9 controls to select N MOS open drain port To select N MOS open drain port write 1 to the corresponding bit of RSFUNC ADDRESS RESET VALUE Undefined R5 57 R56 55 54 53 l p R5 Data Register Input Output data ADDRESS R5 Direction Register RESET VALUE 00000 p R5IO Port Direction 0 Input 1 Output ADDRESS R5 Function Selection Register RESET VALUE o 0 R56 1 PWM10 T10 R5 N MOS Open Drain Selection Register R5NODR ADDRESS 0F9 RESET VALUE 00000 H Open Drain Selection 0 Disable 1 Enable R6 and R6IO register R6 is an 8 bit bidirectional I O port address OCC Each port be set individually as input and output through the R6IO register address OCD y R67 R60 ports are multiplexed with Analog Input Port Port Pin Alternate
82. interval timer register BITR is increased every internal count pulse which is divided by prescaler Since prescaler has divided ratio by 8 to 1024 the count rate is 1 8 to 1 1024 of the oscillator frequency As the count overflows from FFq to 00g this overflow causes to generate the Basic interval timer interrupt The BITIF is in terrupt request flag of Basic interval timer The Basic In terval Timer is controlled by the clock control register CKCTLR shown in Figure 10 2 When write 1 to bit BTCL of CKCTLR BITR register is cleared to 0 and restart to count up The bit BTCL be comes 0 after one machine cycle by hardware If the STOP instruction executed after writing 1 to bit WAKEUP of CKCTLR it goes into the wake up timer mode In this mode all of the block is halted except the os cillator prescaler only fXIN 2048 and 0 If the STOP instruction executed after writing 1 to bit RCWDT of CKCTLR it goes into the internal RC oscillat ed watchdog timer mode In this mode all of the block is halted except the internal RC oscillator Basic Interval Timer and Watchdog Timer More detail informations are explained in Power Saving Function The bit WDTON de cides Watchdog Timer or the normal 7 bit timer Source clock can be selected by lower 3 bits of CKCTLR BITR and CKCTLR are located at same address and ad dress OEC is read as a BITR and written to CKCTLR Internal RC OSC WAKEUP d STOP
83. is accepted or the interrupt latch is cleared to 0 by a reset or an in struction Interrupt acceptance sequence requires 8 fxiN 2 us at fA m 74 19 2 after the completion of the current instruction execution The interrupt service task is termi nated upon execution of an interrupt return instruction RETI Interrupt acceptance 1 The interrupt master enable flag I flag is cleared to 0 to temporarily disable the acceptance of any follow ing maskable interrupts When a non maskable inter rupt is accepted the acceptance of any following interrupts is temporarily disabled 2 Interrupt request flag for the interrupt source accepted is cleared to 0 3 The contents of the program counter return address and the program status word are saved pushed onto the stack area The stack pointer decreases 3 times 4 The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter 5 The instruction stored at the entry address of the inter rupt service program is executed Instruction Fetch LJ LJ LJ LJ LJ LJ LI Address Bus SP Y sea SP 2 Y V L Noh Data Bus Internal Read Internal Write V L and V H are vector addresses X Y Pony PCL Y Psw ve Y aot Y m OF code Interrupt Processing Step lt ADL and ADH are s
84. ist of Interrupt enable register IENH IENL Interrupt request flags of IRQL Priority circuit and Master enable flag T flag of PSW Nine interrupt sources are provided The configuration of interrupt circuit is shown in Figure 16 2 The External Interrupts INTO and INTI each can be transi tion activated 1 10 0 or 0 to 1 transition by selection IEDS The flags that actually generate these interrupts are bit INTOF and INTIF in register IROH When an external in terrupt is generated the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated The Timer 0 Timer 1 Interrupts are generated by TxIF which is set by a match in their respective timer counter register The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion The Watchdog timer Interrupt is generated by WDTIF which set by a match in Watchdog timer register The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer counter register The interrupts are controlled by the interrupt master enable flag I flag bit 2 of PSW on page 21 the interrupt enable register IENH IENL and the interrupt request flags in IRQH and IRQL except Power on reset and software BRK interrupt Below tab
85. ister TDRO is compared with the contents of the up counter TO If a match is found an timer interrupt request flag TOIF is generated and the counter is cleared to 0 The counter is restart and count up continuously by every falling edge or rising edge of the ECO pin input The maximum frequency applied to the ECO pin is 2 Hz In order to use event counter function the bit 2 of the R5 function register RSFUNC 2 is required to be set to 1 After reset the value of timer data register TDRO is unde fined it should be initialized to between 1 FFy not to O The interval period of Timer is calculated as below equation Period sec x x 2 x Divide Ratio x TDRO XIN Start count Up counter TDR1 T1IF interrupt coat LI L Figure 12 5 Event Counter Mode Timing Chart TDR1 stop clear amp start disable DN Timer 1 T1IF Interrupt Occur interrupt T1ST Start amp Stop TIST 0 T1CN Control count T1ST 1 gt TIME Occur interrupt TICN 1 0 Figure 12 6 Count Operation of Event counter JUNE 2001 Ver 1 00 47 GMS81C2112 GMS81C2120 12 2 16 bit Timer Counter Mode The Timer register is being run with 16 bits A 16 bit timer counter register are increased from 0000 until it matches TDRI and then resets to 00004 The match output generate
86. it 30 3 Direct Page Addressing dp In this mode a address is specified within direct page Example G 0 C535 LDA 35H RAM 35H scc aet V 35H data data A 0E550H C5 0E551H 35 4 Absolute Addressing abs Absolute addressing sets corresponding memory data to Data i e second byte Operand I of command becomes lower level address and third byte Operand II becomes upper level address With 3 bytes command it is possible to access to whole memory area ADC AND CMP CMPX CMPY EOR LDA LDX LDY OR SBC STA STX STY Example 0735F0 ADC 0 035 ROM 0F035H OF035H data 1 1 A data C gt OF100H 07 0 101 35 address 0F035 0F102H FO y ipt operation within data memory RAM ASL BIT DEC INC LSR ROL ROR Example Addressing accesses the address 0135 regard less of G flag JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 983501 INC 10135 lt ROM 135H E S 135H data 725 pu data 1 gt data OF100H 98 9 OF101H 35 address 0135 OF102H 01 k sasaqa NE 5 Indexed Addressing X indexed direct page no offset X In this mode a address is specified by the X register ADC AND CMP EOR LDA OR SBC STA XMA Example 15 G 1 4 LDA X ACC RAM X e e e S 2 2 ds
87. lag Register Low IRQL Bit3 Figure 14 5 Serial Method to Test Transmission 62 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 15 BUZZER FUNCTION The buzzer driver block consists of 6 bit binary counter buzzer register BUR and clock source selector It gener ates square wave which has very wide range frequency 480Hz 250kHz at 4MHZ by user software A 50 duty pulse can be output to RO3 BUZO pin to use for piezo electric buzzer drive Pin R03 is assigned for output port of Buzzer driver by setting the bit 3 of ROFUNC address OF4g to 1 At this time the pin must be defined as output mode the bit 3 of ROIO 1 Example 5kHz output at 4MHz LDM ROIO XXXX_1XXXB LDM BUR 0011_0010B LDM ROFUNC XXXX_1XXXB X means don t care The bit 0 to 5 of BUR determines output frequency for buzzer driving Equation of frequency calculation is shown below f _ JxIN BUZ 2xDivideRatio X BUR 1 fguz Buzzer frequency Oscillator frequency Divide Ratio Prescaler divide ratio by BUCK 1 0 BUR Lower 6 bit value of BUR Buzzer period value The frequency of output signal is controlled by the buzzer control register BUR The bit 0 to bit 5 of BUR determine output frequency for buzzer driving XIN PIN Prescaler jl 6 bit binary 6 BIT COUNTER Comparator 3 6 1 R03 port data 7 2 0 Y R03 BUZO PIN F F R
88. le shows the Interrupt priority Reset Interrupt Symbol Priority Hardware Reset RESET External Interrupt 0 INTO 1 External Interrupt 1 INT1 2 Timer Counter 0 TIMERO 3 Timer Counter 1 TIMER1 4 ADC Interrupt ADC 5 Watchdog Timer WDT 6 Basic Interval Timer BIT 7 Serial Communication SCI 8 Vector addresses are shown in Figure 8 6 on page 23 In terrupt enable registers are shown in Figure 16 3 These registers are composed of interrupt enable flags of each in terrupt source and these flags determines whether an inter rupt will be accepted or not When enable flag is 0 a corresponding interrupt source is prohibited Note that PSW contains also a master enable bit I flag which dis ables all interrupts at once RW RW RW RW ADDRESS 0E4u INITIAL VALUE 0000 g Timer Counter 1 interrupt request flag Timer Counter 0 interrupt request flag External interrupt 1 request flag RW RW RW RW External 0 request flag ADDRESS 0E5 INITIAL VALUE 0000 Serial Communication interrupt request flag Basic Interval imer interrupt request flag Watchdog timer interrupt request flag A D Conver interrupt request flag Figure 16 1 Interrupt Request Flag JUNE 2001 Ver 1 00 65
89. ll up X ru GND __ 10 When port is configured as an input input level should be closed to OV or 5V to avoid power consumption Figure 17 7 Application Example of Unused Input Port OUTPUT PIN EL lLorrF JO Vpp Ex OFF In the left case much current flows from port to GND OUTPUT PIN 7 Vpp LorF X Y gt GND X O In the left case Tr base current flows from port to GND To avoid power consumption there should be low output to the port Figure 17 8 Application Example of Unused Output Port 78 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 18 OSCILLATOR CIRCUIT The GMS81C21xx has an oscillation circuits internally and are input and output for main frequency re spectively inverting amplifier which can be configured for being used as an on chip oscillator as shown in Figure 18 1 Recommend Crystal Oscillator C1 C2 20pF Ceramic Resonator C1 C2 30pF Open Xout External Clock External Oscillator Crystal or Ceramic Oscillator Xout Rext For selection R value XIN Refer to AC Characteristics RC Oscillator mask option Figure 18 1 Oscillation Circuit Oscillation circuit is des
90. n ADDRESS RA Data Registe RESET VALUE Undefined RA Input data Port pin Alternate function RA High voltage input power supply 34 RO and ROIO register RO is an 8 bit high voltage CMOS bidirectional I O port address Each port can be set individually as input and output through the ROIO register address 1 Each port can directly drive a vacuum flu orescent display R03 port is multiplexed with Buzzer Out put Port BUZO 2 port is multiplexed with Event Counter Input Port and RO1 ROO are multiplexed with External Interrupt Input Port INT1 INTO Port Pin Alternate Function ROO INTO External interrupt 0 Input Port R01 INT1 External interrupt 1 Input Port R02 ECO Event Counter Input Port R03 BUZO Buzzer Output Port The control register ROFUNC address F44 controls to select alternate function After reset this value is 0 port may be used as general I O ports To select alternate func tion such as Buzzer Output External Event Counter Input and External Interrupt Input write 1 to the correspond ing bit of ROFUNC Regardless of the direction register ROIO ROFUNC is selected to use as alternate functions port pin can be used as a corresponding alternate features BUZO ECO INT1 INTO ADDRESS RESET VALUE Undefined RO R07 806 ROS 804 RO3 R02 R01 ROO RO Data Register
91. n be programmed or left unprogrammed to select device configuration such as secu rity bit Sixteen memory locations 70304 703Fg are designated as Customer ID recording locations where the user can store check sum or other customer identification numbers This area is not accessible during normal execution but is readable and writable during program verify 70304 DEVICE CONFIGURATION AREA 703F 5 4 CONFIG 70304 70314 7032 70334 70344 70354 70364 7037 70384 70394 703By 703C 703 ID 703Ey CONFIG 703Fy ADDRESS 703Fy INITIAL VALUE 00 0 0g External RC OSC Selection 0 Crystal or Resonator Oscillator 1 External RC Oscillator Code Protect 0 Allow Code Read Out 1 Lock Code Read Out PFD Level Selection 00 PFD 2 7V 01 PFD 2 7V 10 PFD 3 0V 11 PFD 2 4V Figure 21 1 Device Configuration Area JUNE 2001 Ver 1 00 83 GMS81C2112 GMS81C2120
92. ng up is resumed after the up counter is cleared up Thus you can think of it as counting internal clock in put The contents of are compared with the contents of up counter Tn If match is found a timer 1 interrupt T1IF is generated and the up counter is cleared to 0 As the value of TDRn is changeable by software time in terval is set as you want Start count Y sourcectock L U LJ LI LJ LILI LILI LI UU Up counter 0 TDR1 n interrupt Figure 12 3 Timer Mode Timing Chart Example Make 2ms interrupt using by Timer0 at 4MHz LDM TMO 0 divide by 32 LDM TDRO 125 8us x 125 1ms SET1 OE Enable Timer 0 Interrupt EI Enable Master Interrupt When TMO 0000 1111g 8 bit Timer mode Prescaler divide ratio 32 125p 7Dy L 4 MHz 1 INTERRUPT PERIOD x32 125 1 ms 4 x 106 Hz TDR1 4 Count Pulse 7D A 0 gt TIME Interrupt period 8 us x 125 Timer 1 T1IF Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 12 4 Timer Count Example 46 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 8 bit Event Counter Mode In this mode counting up is started by an external trigger This trigger means falling edge or rising edge of the ECO pin input Source clock is used as an internal clock selected with timer mode register TMO The contents of timer data reg
93. not to execute a PORT input instruction while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion 4 AVDD pin input impedance A series resistor string of approximately 10KQ is connected be tween the AVDD pin and the AVSS pin Therefore if the output impedance of the reference voltage source is high this will result in parallel connection to the series resistor string between the AVDD pin and the AVSS pin and there will be a large reference voltage error JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 14 SERIAL PERIPHERAL INTERFACE The Serial Peripheral Interface SPI module is a serial in terface useful for communicating with other peripheral of microcontroller devices These peripheral devices may be serial EEPROMs shift registers display drivers A D con verters etc The Serial Peripheral Interface SPI is 8 bit clock synchronous type and consists of serial I O register serial I O mode register clock selection circuit octal counter and control circuit The SOUT pin is designed to input and output So Serial Peripheral Interface SPI can be operated with minimum two pin SCK 1 0 XIN PIN L Overflow
94. od in Absolute Duty Cycle 4MHz JUNE 2001 Ver 1 00 55 GMS81C2112 GMS81C2120 13 ANALOG DIGITAL CONVERTER The analog to digital converter A D allows conversion of an analog input signal to a corresponding 8 bit digital value The A D module has eight analog inputs which are multiplexed into one sample and hold The output of the sample and hold is the input into the converter which gen erates the result via successive approximation The analog supply voltage is connected to of ladder resistance of A D module The A D module has two registers which are the control register ADCM and A D result register ADR The register ADCM shown in Figure 13 1 controls the operation of the A D converter module The port pins can be configured as analog inputs or digital I O To use analog inputs each port is assigned analog input port by setting the bit ANSEL 7 0 in RGFUNC register And selected the corresponding channel to be converted by setting ADS 3 0 How to Use A D Converter The processing of conversion is start when the start bit ADST is set to 1 After one cycle it is cleared by hard ware The register ADCR contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCR the A D conversion status bit ADSF is set to 1 and the A D interrupt flag ADIF is set The block diagram of the A D module is shown in Figure 13 2 The A D status bit ADSF is set autom
95. pheral clock Off RAM page register RPR 0 Watchdog timer Disable G flag G 0 Control registers Refer to Table 8 1 on page 27 Operation mode Main frequency clock Power fail detector Disable Table 19 1 Initializing Internal Status by Reset Action 19 1 External Reset Input The reset input is the RESET pin which is the input to a Schmitt Trigger A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods within the operating voltage range and oscillation stable it is applied and the internal state is initialized After reset 64ms at 4 MHz add with 7 oscillator periods are required to start ex ecution as shown in Figure 19 2 Internal RAM is not affected by reset When Vpp is turned on the RAM content is indeterminate Therefore this RAM should be initialized before read or tested it When the RESET pin input goes to high the reset opera tion is released and the program execution starts at the vec tor address stored at addresses A connection for simple power on reset is shown in Figure 19 1 to the RESET Oscillator pin RESET ADDRESS 2 BUS 2 x 2 2 2 DATA ad or gt lt gt lt MAIN PROGRAM Stabilization Time tsr
96. plexed with general I O ports ROO and RO1 To use as an external interrupt pin the bit of R4 port mode register ROFUNC should be set to 1 cor respondingly Example To use as an INTO and INTI Set port as an input port R00 R01 LDM ROIO 1111_1100B Set port as an interrupt port LDM ROFUNC 0000 0011B Set Falling edge Detection LDM IEDS 40000 0101B Response Time The INTO and INTI edge are latched into INTOIF and INTIIF at every machine cycle The values are not actually polled by the circuitry until the next machine cycle If a re quest is active and conditions are right for it to be acknowl edged a hardware subroutine call to the requested service routine will be the next instruction to be executed The DIV itself takes twelve cycles Thus a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine Figure 16 8shows interrupt response timings max 12 fy 8 in Interrupt Interrupt Interrupt goes latched processing active Interrupt routine Figure 16 8 Interrupt Response Timing Diagram 70 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 w w w w w w w w I 7 ADDRESS 0 4 i i INT1 INT H ROFUNC BUZO ECO INTO INITIAL VALUE 00008 MSB LSB 0 ROO 1 INTO 0
97. pt source Example 7 bit timer interrupt set up LDM CKCTLR xx0xxxxxB WDTON lt 0 LDM WDTR 7FH WDTCL lt 1 Binary counter WDTR WDTIF interrupt WDT reset Source clock BIT overflow L L Counter Figure 11 3 Watchdog timer Timing If the watchdog timer output becomes active a reset is gen erated which drives the RESET pin low to reset the inter nal hardware JUNE 2001 Ver 1 00 The main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode 41 GMS81C2112 GMS81C2120 12 TIMER EVENT COUNTER The GMS81C21xx has two Timer Counter registers Each module can generate an interrupt to indicate that an event has occurred i e timer match Timer 0 and Timer 1 are can be used either two 8 bit Tim er Counter or one 16 bit Timer Counter with combine them In the timer function the register is increased every in ternal clock input Thus one can think of it as counting in ternal clock input Since a least clock consists of 2 and most clock consists of 2048 oscillator periods the count rate is 1 2 to 1 2048 of the oscillator frequency in Timer0 And Timer can use the same clock source too In addition Timer has more fast clock source 1 1 to 1 8 In the counter function the register is increased in re sponse to a 1 to 0 falling edge 0 to 1 rising edge tran sition at its corresponding external
98. rence interrupts and calling out subroutines Stack Pointer identifies the location in the stack to be access save or restore 20 to 12K 20K bytes of Program memory Data memory can be read and written to up to 448 bytes including the stack area Generally SP is automatically updated when a subroutine call is executed or an interrupt is accepted However if it is used in excess of the stack area permitted by the data memory allocating configuration the user processed data may be lost The stack can be located at any position within 100g to 1FFy of the internal data memory The SP is not initialized by hardware requiring to write the initial value the loca tion with which the use of the stack starts by using the ini tialization routine Normally the initial value of is used Stack Address 100 1FE Bit 15 87 Bit 0 014 00 Hardware fixed Note The Stack Pointer must be initialized by software be cause its value is undefined after RESET Example To initialize the SP LDX OFFH TXSP SP FFy Program Counter The Program Counter is a 16 bit wide which consists of two 8 bit registers PCH and PCL This counter indicates the address of the next instruction to be executed In reset state the program counter has reset rou tine address PCy 0FFy 0FErp Program Status Word The Program Status Word PSW contains several bits that reflect the current state of the CPU
99. rupt can be serviced without any pending even TIMER1 is in progress Because of re setting the interrupt enable registers IENH IENL and master enable in the TIMER1 routine Figure 16 6 Execution of Multi Interrupt JUNE 2001 Ver 1 00 However multiple processing through software for special features is possible Generally when an interrupt is accept ed the I flag is cleared to disable any further interrupt But as user sets I flag in interrupt routine some further inter rupt can be serviced even if certain interrupt is in progress Example During Timerl interrupt is in progress INTO in terrupt serviced without any suspend TIMER1 PUSH A PUSH X PUSH Y LDM IENH 80H Enable INTO only LDM IENL 0 Disable other EI Enable Interrupt LDM IENH OFOH Enable all interrupts LDM IENL 0 POP Y POP X POP A RETI 69 GMS81C2112 GMS81C2120 16 4 External Interrupt The external interrupt on INTO and INTI pins are edge triggered depending on the edge selection register IEDS address 0 8 as shown in Figure 16 7 The edge detection of external interrupt has three transition activated mode rising edge falling edge and both edge INT1 pin C INT1IF gt fV INTERRUPT FS INTO pin INTOIF gt fu INTO INTERRUPT 2 12 Edge selection IEDS Register OE6H Figure 16 7 External Interrupt Block Diagram INTO and INT are multi
100. rval of BIT BASIC INTERVAL TIMER OVERFLOW Cout Counter 7 bit clear Watchdog source to reset CPU comparator WDTCL 7 bit compare data WDTON in CKCTLR 0ECri 7 11 1 Watchdog Timer interrupt WDTR Watchdog Timer Register OED Internal bus line JUNE 2001 Ver 1 00 Figure 11 1 Block Diagram of Watchdog Timer 39 GMS81C2112 GMS81C2120 Watchdog Control Figure 11 2 shows the watchdog timer control register The watchdog timer is automatically disabled after reset The CPU malfunction is detected during setting of the de tection time selecting of output and clearing of the binary counter Clearing the binary counter is repeated within the detection time If the malfunction occurs for any cause the watchdog tim er output will become active at the rising overflow from the binary counters unless the binary counter is cleared At this time when WDTON 1 a reset is generated which drives the RESET pin to low to reset the internal hardware When WDTON 0 a watchdog timer interrupt WDTIF is generated The watchdog timer temporarily stops counting in the STOP mode and when the STOP mode is released it au tomatically restarts continues counting ADDRESS INITIAL VALUE 0111 1111g Clear count flag 0 Free run count 7 bit compare data 1 When the WDTCL is set to 1 binary counter is cleared
101. s Timer 0 interrupt not Timer in terrupt The clock source of the Timer 0 is selected either internal or external clock by bit TOCK 2 0 In 16 bit mode the bits TICK 1 0 and 16BIT of TM1 should be set to 1 respectively TMO 0 X xX TM1 1 0 0 TOCK 2 0 EDGE DETECTOR Prescaler TIMER 0 TIMER 1 gt TIMER 0 16 bit 5 4 3 2 1 0 2 1 7 6 1 7 6 5 4 3 2 1 0 x 1 x Higher byte Lower byte ADDRESS 0D0 INITIAL VALUE 000000g 0 x x x X means don t care ADDRESS 0D2y INITIAL VALUE 00 4 1 X X means don t care TOST 0 Stop 1 Clear and start T1 TO 16 bit TIMER 0 INTERRUPT Not Timer 1 interrupt Comparator TDR1 TDRO 16 bit COMPARE DATA Figure 12 7 16 bit Timer Counter 48 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 12 3 8 bit Compare Output 16 bit The GMS81C21xx has a function of Timer Compare Out put To pulse out the timer match can goes to port pin TOO 10 as shown in Figure 12 2 and Figure 12 7 Thus pulse out is generated by the timer match These op eration is implemented to pin TOO PWMIO TIO In this mode the bit PWM10 T10 of R5 function register R5FUNC 6 should be set to 1 and the bit PWMIE of timer mode register TM1 should be set to 0 In addi 12 4 8 bit Capture Mode The Timer 0 capture mode is set by bit CAPO of timer mode register
102. s may not be implemented on the chip Read accesses to these addresses will in gen eral return random data and write accesses will have an in determinate effect More detailed informations of each register are explained in each peripheral section Note Write only registers can not be accessed by bit ma nipulation instruction Do not use read modify write instruc tion Use byte manipulation instruction for example LDM Example To write at CKCTLR LDM CLCTLR 09H Divide ratio 16 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt When returning from the processing routine executing the subroutine return instruction RET restores the contents of the program counter from the stack executing the interrupt return instruction RETT restores the contents of the pro gram counter and flags The save restore locations in the stack are determined by the stack pointed SP The SP is automatically decreased after the saving and increased before the restoring This means the value of the SP indicates the stack location number for the next save Refer to Figure 8 4 on page 22 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Note Several names are given at same address Refer to below table When read
103. set1 or clr1 instruction it may be undesired operation In the Stop mode of operation Vpp can be reduced to min imize power consumption Care must be taken however to ensure that Vpp is not reduced before the Stop mode is invoked and that Vpp is restored to its normal operating level before the Stop mode is terminated The reset should not be activated before V pp is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize Note After STOP instruction at least two or more NOP in struction should be written Ex LDM CKCTLR 0000_1110B STOP NOP NOP In the STOP operation the dissipation of the power asso ciated with the oscillator and the internal hardware is low ered however the power dissipation associated with the pin interface depending on the external circuitry and pro gram is not directly determined by the hardware operation of the STOP feature This point should be little current flows when the input level is stable at the power voltage level Vpp V ss however when the input level gets high er than the power voltage level by approximately 0 3 to 0 5V a current begins to flow Therefore if cutting off the output transistor at an I O port puts the pin signal into the high impedance state a current flow across the ports input transistor requiring to fix the level by pull up or other means 74 Release the STOP mode The exit from ST
104. t lt 1 1 4 NOP FF 1 2 No operation 5 POP A 1 4 sp lt sp 1 lt M sp 6 POP X 2D 1 4 spespet XeM sp 7 POP Y 4D 1 4 lt 1 Y lt M sp 8 POP PSW 6D 1 4 sp lt sp 1 PSW lt Msp restored 9 PUSH A 1 4 M sp lt A sp lt sp 1 10 PUSH X 2E 1 4 M speX spesp 1 J 11 PUSH Y 4E 1 4 M sp lt Y sp lt sp 1 12 PUSH PSW 6E 1 4 M sp lt PSW sp lt sp 1 is ar 2 Wes spespst pgueM sp Return from interrupt 14 RETI 7F 1 6 sp lt sp 1 PSW lt M sp sp lt sp 1 restored M sp sp sp 1 M sp 15 STOP EF 1 3 Stop mode haltCPU stop oscillator 1 X JUNE 2001 C MASK ORDER SHEET MASK ORDER amp VERIFICATION SHEET GMS81C21XX HJ Customer should write inside thick line box 1 Customer Information Company Name 2 Device Information Package 42SDIP 44MQFP 40PDIP Application Order Date Tel E mail address Name amp Signature 3 Marking Specification 12 or 20 D GMS81C21XX HJ YYWW KOREA D 27 GMS81C21XX HJ YYWW KOREA Chollian OTP Internet Hitel File Name ROM Size bytes 12K 20K Check Sum
105. t page indirect dp Assigns data address to use for accomplishing command which sets memory data or pair memory by Operand Also index can be used with Index register X Y JMP CALL Example G 0 3F35 JMP 35H SS SEPSE 35H 0A lt 36H E3 9 jump to address 0E30AH 3F 35 papa ai X indexed indirect dp X Processes memory data as Data assigned by 16 bit pair memory which is determined by pair data dp X 1 dp X Operand plus X register data in Direct page ADC AND CMP EOR LDA OR SBC STA Example G 0 10 32 1625 ADC 25H X guit 35H 05 a 36H EO 0E005H 0 005 data lt 25 10 35 OFAO0H 16 25 d L A data C gt A Y indexed indirect dp Y Processes memory data as Data assigned by the data dp 1 dp of 16 bit pair memory paired by Operand in Di rect page plus Y register data ADC AND CMP EOR LDA OR SBC STA Example G 0 10 1725 ADC 25H Y RT 25H 05 4 1 26H EO e 9 E015H 5 Y 10 0 015 data OEO15H 17 25 e L d A data C gt A Absolute indirect abs The program jumps to address specified by 16 bit absolute address JMP Example G 0 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 1F25E0 JMP
106. tart addresses of interrupt service routine as vector contents Interrupt Service Task Figure 16 4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Basic Interval Timer Vector Table Address Entry Address Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program A interrupt request is not accepted until the I flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced JUNE 2001 Ver 1 00 When nested interrupt service is required the I flag should be set to 1 by instruction in the interrupt service program In this case acceptable interrupt sources are se lectively enabled by the individual interrupt enable flags Saving Restoring General purpose Register During interrupt acceptance processing the program counter and the program status word are automatically saved on the stack but accumulator and other registers are not saved itself These registers are saved by the software if necessary Also when multiple interrupt services are nested itis necessary to avoid using the same data memory 67 GMS81C2112 GMS81C2120 area for saving registers The following method is used to save restore the general purpose registers Example Register save using push and pop instructions INTxx PUSH A SAVE ACC PUSH X SAVE X REG PUS
107. tei 115H data v 4 data gt 0E550H D4 kaq E X indexed direct page auto increment In this mode a address is specified within direct page by the X register and the content of X is increased by 1 LDA STA Example G 0 35 DB LDA QE JUNE 2001 Ver 1 00 35 data e data EA 36H X DB loss ne Or X indexed direct page 8 bit offset dp X This address value is the second byte Operand of com mand plus the data of X register And it assigns the mem ory in Direct page ADC AND CMP EOR LDA LDY OR SBC STA STY XMA ASL DEC INC LSR ROL ROR Example G 0 X 0F5g C645 LDA 45H X 3AH data datasA 0 550 C6 19 0E551H 45 N JA5HsOFSH T3AH Y indexed direct page 8 bit offset dp Y This address value is the second byte Operand of com mand plus the data of Y register which assigns Memory in Direct page This is same with above 2 Use Y register instead of X Y indexed absolute abs Y Sets the value of 16 bit absolute address plus Y register data as Memory This addressing mode can specify memo ry in whole area Example 55 31 GMS81C2112 GMS81C2120 D500FA LDA OFAOOH Y 0 100 D5 OF101H 00 0F102H FA 55 55 OFA55H data gt data A s NR 6 Indirect Addressing Direc
108. th Overflow flag V Break flag B This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad dress Direct page flag G JUNE 2001 Ver 1 00 This flag assigns RAM page for direct addressing mode In the direct addressing mode addressing area is from zero page 00g to when this flag is 0 If it is set to 1 addressing area is assigned 100g to 1FFg It is set by SETG instruction and cleared by CLRG Overflow flag V This flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs An overflow occurs when the result of an addition or subtraction ex ceeds 127 7 or 128 80 The CLRV instruction clears the overflow flag There is no set instruction When the BIT instruction is executed bit 6 of memory is copied to this flag Negative flag N This flag is set to match the sign bit bit 7 status of the re sult of a data or arithmetic operation When the BIT in struction is executed bit 7 of memory is copied to this flag 21 GMS81C2112 GMS81C2120 At execution of At acceptance At execution At execution a CALL TCALL PCALL of interrupt of RET instruction of RET instruction Push EPOD VITE DT Op c MER OIFE PCH d 01FE PCH 5 OIFE 5 OIFE PCH 5 fe
109. their values If I flag 1 the normal interrupt response takes place In this case if the bit WDTON of CKCTLR is set to 0 and the bit WDTE of IENH is set to 1 the device will execute the watchdog timer interrupt service routine Figure 17 5 However if the bit WDTON of CKCTLR is set to 1 the device will generate the internal RESET signal and exe cute the reset processing Figure 17 6 If I flag 0 the chip will resume execution starting with the instruction following the STOP instruction It will not vector to interrupt service routine refer to Figure 17 1 When exit from Internal RC Oscillated Watchdog Timer mode by external interrupt the oscillation stabilization time is required to normal operation Figure 17 5 shows the timing diagram When release the Internal RC Oscil lated Watchdog Timer mode the basic interval timer is ac tivated on wake up It is increased from 00 until FFy The count overflow is set to start normal operation Therefore before STOP instruction user must be set its relevant pres caler divide ratio to have long enough time more than 20msec This guarantees that oscillator has started and stabilized By reset exit from internal RC Oscillated Watchdog Tim er mode is shown in Figure 17 6 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Oscillator XI pin 1 INI A VAST OF I RC Clock T Internal Clock 22
110. to 0 And the WDTCL becomes 0 automatically after one machine cycle Counter count up again NOTE The WDTON bit is in register CKCTLR Figure 11 2 WDTR Watchdog Timer Data Register Example Sets the watchdog timer detection time to 0 5 sec at 4 19MHz LDM CKCTLR 3FH LDM WDTR 04FH WDTR 04FH Within WDT detection time LDM WDTR 04FH Within WDT detection time L LDM WDTR 04FH 40 Select 1 2048 clock source WDTON lt 1 Clear Counter Clear counter Clear counter Clear counter JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 Enable and Disable Watchdog Watchdog timer is enabled by setting WDTON bit 4 in CKCTLR to 1 WDTON is initialized to 0 during re set and it should be set to 1 to operate after reset is re leased Example Enables watchdog timer for Reset LDM CKCTLR xx1x_xxxxB WDTON lt 1 The watchdog timer is disabled by clearing bit 5 WD TON of CKCTLR The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is re leased Watchdog Timer Interrupt The watchdog timer can be also used as a simple 7 bit tim er by clearing bit5 of CKCTLR to 0 The interval of watchdog timer interrupt is decided by Basic Interval Tim er Interval equation is shown as below T WDTR x Interval of BIT The stack pointer SP should be initialized before using the watchdog timer output as an interru
111. ts an Serial transmission After one cycle bit is cleared to 0 by hardware Serial transmission Clock selection 00 4 01 16 10 TMROOV TimerO Overflow 11 External Clock Serial transmission Operation Mode 00 Normal Port R55 R54 R53 01 Sending Mode SOUT R54 SCLK 10 Receiving Mode R55 SIN SCLK 11 Sending amp Receiving Mode SOUT SIN SCLK Serial Input Pin Selection bit 0 SIN Pin Selection 1 IOSWIN Pin Selection R W RW R W RW R W RW R W R W 7 6 5 4 3 2 1 0 Sending Data at Sending Mode Receiving Data at Receiving Mode SIOR Serial Clock Polarity Selection bit 0 Data Transmission at Falling Edge Received Data Latch at Rising Edge 1 Data Transmission at Rising Edge Received Data Latch at Falling Edge ADDRESS 0E1 INITIAL VALUE Undefined Figure 14 2 SPI Control Register 60 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 14 1 Transmission Receiving Timing The serial transmission is started by setting SIOST bit of is latched at rising edge of SCLK pin When transmission SIOM to 1 After one cycle of SCK SIOST is cleared clock is counted 8 times serial I O counter is cleared as automatically to 0 The serial output data from 8 bit shift 0 Transmission clock is halted in H state and serial 1 register is output at falling edge of SCLK And input data O interrupt IFSIO occurred SIOST A lt lt s NTST ITA SCLK
112. ymbol MIN TYP MAX Unit Programming Supply Current lypp 50 mA Supply Current in EPROM Mode 20 VPP Level during Programming Viup 11 5 12 0 12 5 V VDD Level in Program Mode 5 6 6 5 V VDD Level in Read Mode VppeH 2 7 V CTL3 0 High Level in EPROM Mode 0 8Vpp V CTL3 0 Low Level in EPROM Mode 0 2Vpp V A_D7 A_D0 High Level in EPROM Mode ViHAD 0 9Vpp V D7 A DO Low Level in EPROM Mode ViLAD 2 0 1Vpp V VDD Saturation Time Typps 1 mS VPP Setup Time 1 mS VPP Saturation Time Typps 1 mS EPROM Enable Setup Time after Data Input 200 ns EPROM Enable Hold Time after Tuupi 500 ns Table 21 2 AC DC Requirements for Program Read Mode 86 JUNE 2001 Ver 1 00 GMS81C2112 GMS81C2120 EPROM Enable Delay Time after T p 200 nS EPROM Enable Hold Time in Write Mode 2 100 nS EPROM Enable Delay Time after Ty gt Tpive 200 nS CTL2 1 Setup Time after Low Address input and Data input 100 ns CTL1 Setup Time before Data output in Read and Verify Mode Tcpe 100 nS Table 21 2 AC DC Requirements for Program Read Mode START Y Set VDD Vpp1 H Y Verify of all address Report Set VPP Viyp Report Verify failure Programming failure FAIL FAIL Verify blank

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