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MIPS® SEAD(TM)-3 Board User`s Manual

1. 2 3 Uncached Access of Registers Table 2 3 SEAD 3 Physical Memory as Decoded by Target 3 Continued Base Address Size Device Function 0 1 00 0 4 MBytes M14K SRAM Base Address When used SRAM must be mapped Configuration Register to Address 0x0000 0000 0 1 40 0000 4 MBytes Optional SRAM TARGET 3 Data Ox1E80 0000 8 MBytes Reserved TARGET 3 Data Ox1F00 0 512 Bytes FPGA Internal Registers TARGET 3 Data Ox1F00 0200 8 Bytes P SWITCH TARGET 3 Data Ox1F00 0208 8 Bytes F SWITCH TARGET 3 Data 0 1 00 0 8 Bytes P LED TARGET 3 Data 0 1 00 0218 8 Bytes F_ LED TARGET 3 Data 0 1 00 0220 8 Bytes NEWSC Live TARGET 3 Data 0 1 00 0228 8 Bytes NEWSC Registered TARGET 3 Data Ox1F00 0230 16 Bytes NEWSC Control TARGET 3 Data Ox1F00 0 192 Bytes Reserved TARGET 3 Data Ox1F00 0 256 Bytes Reserved TARGET 3 Data 0 1 00 0 128Bytes LOD Display TARGET 3 Data 0 1 00 0480 128Bytes Device Reset TARGET 3 Data 021100 0500 256 Bytes Reserved TARGET 3 Data 0 1 00 0600 256 Bytes PIC32 Registers TARGET 3 Data Ox1F00 0700 256 Bytes Reserved TARGET 3 Data Ox1F00 0 256 Bytes UART CH 0 TARGET 3 Data Ox1F00 0900 256 Bytes UART 1 TARGET 3 Data 0 1 00 0 62 KBytes Reserved Reserved Ox1F01 0000 64 KBytes Ethernet Controller TARGET 3 Data 021102 0000 3968 Kbytes Reserved Reserved Ox1F40 0 4 MBytes User Expansion TARGET 3
2. 3 84 F LED REGL nn 8 0 19680151817 nu 3 8 0 NEWSC REG Register 3 8 7 NEWSC CTRL Register 3 8 8 2 Line 16 Character Alphanumeric LCD ASCII Display Registers 3 8 9 Device 556881156051817 eens Chapter 4 USB Download 1 00202 ss ssssosnesercencs Ai USB HUINI E onie a 4 2 USB Downlodd cnt eterna quet tn 4 21 Sending Data to the nito t Siete Chapter 5 EJTAG PDTrace Chapter 6 Reset Operation Chapter 7 1 Oe ene reer Chapter 8 DRAM Interface Chapter 9 Peripheral BUS __ __________ _ __ _ lt _ _ _23 _ _ _ _ 9 1 1 Read 9 1 2 WME ACCESS mn na none MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved eee ess 58 1585601664 Penpheral Bus 9 2 Chapter 10 SEAD 3 CoreBus Connector 55 Chapter 11 63
3. Figute 16 2 User Board Connectors en tant MIPS SEADTM 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved List of Tables Table list 12 Table 2 1 SEAD 3 X bus Controller First level Address Map 15 Table 2 2 Target 51 a cur ne nr 16 Table 2 3 SEAD 3 Physical Memory as Decoded 16 Table 2 4 SEAD3_CFG Register Field Descriptions Address 0 1 10 0110 18 Table 2 5 PIC32 USB STATUS Register Field Descriptions Address 0x1F00 0060 18 Table 2 6 SOFTENDIAN Register Field Descriptions Address 0 1 00 0070 19 Table 3 1 Module Voltage Control Truth Table pp 22 Table 3 2 24 Table 25 Table 3 4 ESWITGELROGISISE 25
4. 4 2 USB Download Format Table 4 4 Download Commands Opcode Meaning Argument Sets current writing erasing address to SEAD 3 Board physi 32 bit address 8 characters cal memory map format Addresses must be on 16 word boundaries Reset download system enter download mode No IL the current Flash sector 128 No IC Clear all Flash lock bits No 15 Set current Flash sector lock bit No Comment rest of line A string of ASCII values between 0x20 and 0 7 except the charac ter The controller continuously looks for the character to get in sync if some error occurs R is a reset So don t use this character in comments and display strings gt Print command shows next 8 characters in ASCII display A string of exactly 8 ASCII values the command needs exactly 8 non white space characters between 0x20 and Ox7f except the Please note that display strings starting with will be character preted as commands as well as specified in Table 4 5 data Data has to be in blocks of 16 words without interruption of No any Comments and Print Commands gt Display commands in which the string starts with will be displayed but will also be interpreted as commands according to Table 4 5 Table 4 5 Special Display Commands Display string Meaning DL_DONE This string brings the board out of USB download mode This display string should
5. 26 Table 3 62 4 BALISE 26 Table 3 7 NEWSOLIVE RegISIBI rinon aa O 26 Table 3 9 NEWSO REG R6GISIOE ee 27 Table 3 9 NEWSC CIRL Registe 27 3 10 28 Table 3 11 PILDEVRST 28 Tabl 3 _ 22 232 _ _ _ _ _ 31 Table 4 2 USB C 50 5C 0 3 Board 31 Table 4 9 Download File a A te 32 Table 4 4 Download Commal s 33 Table4 5 Special Display cocer pntat reet pane 00000 33 Jable 4 6 Flash Download Error Messages same act xt eet Qu scm EQ edu sans 34 Table 4 7 Boot Flash Layout USB sooo eit ue 34 Tabl 48 Boot Flash Layout FPGA si 0 35 Table 51 UN EE 37 Table 5 2 1Flewtrace Connector J20 37 Table 5 9 PDTrace 38 Elo xem reale E 42 Table 7 1 GL IV Selection Table rca nra rera aar art rti e ce ae ra haa 4
6. Big Endian MIPS SEAD 3 Board User s Manual Revision 01 03 19 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Map Decode 20 Chapter 3 CPLD Controller The following features are implemented in the CPLD Power Controller controls power to the board Module Voltage Control controls voltage level to modules on the board Board Controller controls state of the board Reset and Chip Selects to various devices on the board Periodic Pulse Generator LOD Interface controller Switch registers and LED registers drivers 3 1 Power Controller Board power is controlled by using the NMI push button Push NMI button to Power ON the turn off power push and hold NMI button for at least 7 seconds Power Controller states are OFF OFF2ON ON ON2OFF 21 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPLD Controller 3 2 Module Voltage Control CPLD will map VID codes from the Module board to Voltage Enable pins as shown in Table 3 1 Table 3 1 Module Voltage Control Truth Table Outputs vIXvYen Function inhibit No Module Inhibit Unused codes 2 5V 1 vVIXvYen Outputs where XvY is 2v5 1v8 1v5 1v2 1v1 1v0
7. All other combinations are also invalid and ignored 1 D Data on bus 2 Strobe to generate LCD cycle 3 DR LCD data register in CPLD 4 X Don t care Software needs to read the status in LCD Status and LCD contents Because it is not possible to retrieve the data from the LCD quickly enough for the software data reads will be done in 2 stages Software will issue a read to the LCD control data register LCD Interface controller in CPLD will generate a read on the LCD bus with RS set appropri ately and the data will be captured and written to CPLD LCD Data register DR Software should read CPLD LCD Data register DR to retrieve LCD control data value after LCD Interface Controller completes the read cycle Bit 0 in CPLD LCD Status register will be zero when LCD Interface Controller is IDLE Software should issue an LCD read write cycle only when the LCD Interface Controller is IDLE The LCD Status and Data register in CPLD can be read at any time 3 7 Switches and LEDs There are registers allocated in the CPLD to sample switches The switch registers are F SSWITCH P SWITCH NEWSC LIVE NEWSC REG and NEWSC CTRL The CPLD s P LED and F LED registers drive the LEDs on the board 24 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 8 CPLD Registers The switch and LED registers are CPU accessible Refer to the Peripheral Bus Register in t
8. Clock Frequency select Refer to Table 7 2 Clock Frequency select Refer to Table 7 3 Module clock control Refer to Table 7 1 SW BIGEND When Off Set the CPU to Little Endian mode Default When On Set the CPU to Big Endian mode SW XI PGM MODE When Off Enable EzUSB controller access to the FPGA JTAG chain Default When On Disable EzUSB controller access to the FPGA JTAG chain SW SRAM MAP ZERO When Off MAPS SRAM address 0 1 00 0000 Ox 1E3f ffff When On Maps SRAM address 0x0000 0000 SW FPGA OPTION currently unused This switch is directly connected to the FPGA This switch marked F SWITCH on the PCB provides a value which can be read via the peripheral bus when SEL 4 0 201001 SW3 1 maps to PI D 0 SW3 2 maps to PI D 1 and so forth This switch marked SWITCH on the provides a value which can be read via the peripheral bus when SEL 4 0 201001 SW4 1 maps to D 0 SW4 2 maps to D 1 and so forth Position SWI I SW1 2 SW1 3 SW1 4 SWI 5 SWI1 6 SWI T SW1 8 SW2 1 SW2 2 SW2 3 SW2 4 Type Push button Push button 8 DIP 4 way DIP 8 way DIP 8 way DIP Ref SW9 SW10 SWI SW2 SW3 SW4 MIPS SEAD 3 Board Users Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 13 1 Switches Con
9. MIPS SEAD 3 Board User s Manual Revision 01 03 13 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction Chapter 2 Memory Map Decode The X bus controller BIU which we will also refer to as the X bus controller in the following has BIU interface and four X bus master ports The address bus and write data bus originating from the X bus controller are actually shared between the X bus targets However each of the four targets has its own read data bus in order to avoid tri state busses 2 1 First level Address Mapping The X bus controller contains a fixed hardcoded first level address mapping which maps the physical address space from the CPU to the X bus ports An X bus may be used for data transfers typically memories and or register accesses For X busses with both types of functions the X bus controller decodes two segments The address map ping is shown in Table 2 1 Table 2 1 SEAD 3 X bus Controller First level Address Base Address Size Device Function 0 0000 0000 256 MByte DRAM Memory TARGET O Data 0 1000 0000 176 MByte DRAM Memory TARGET O Data 0 1 00 0000 1 MByte DRAM TARGET O Registers Ox1B10 0000 1 MByte CFG GIC TARGET 1 Registers Ox1B20 0000 1 MByte USB HS 2 0 01C TARGET 2 Registers 0x1B30 0000 1 MByte Rese
10. User Board Board Both versions of the SEAD 3 board A80209 and A80211 are pre equipped with a number of resources including I2C SPI 0210 ADC MicroSD slot Serial and USB UART Ethernet controller and SRAM and Flash memory The DDR2 Controller and USB 2 0 PHY are only available on A80209 There are either 238 or 356 FPGA signals depending on the FPGA type on the SEAD 3 Expansion Connectors which are available for the user board interface See Table 16 1 and Table 16 3 There are 264 FPGA signals the SEAD 3 CoreBus Connector used for the Module 3 See Table 10 1 1 1 SEAD 3 Board at a Glance e SEAD 3 CoreBus Connector accepts CPU module with a MIPS CPU core The CPU can either be synthe sized in an FPGA variant or be a Lead Vehicle variant in bond out mode and with the core interface connected to the FPGA Alternatively if the core and system controller are housed in the on board FPGA the connector can be used for a custom add on board e SEAD 3 CoreBus Connector signals are defined in CORE_B 264 1 This bus can be defined as an OCP or AHB bus Alternatively the user may define his own custom bus e A80209 has a Xilinx XCVLX110 FPGA with 800 I Os 155 000 LUTs 10 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 1 SEAD 3 Board at a Glance e 80211 has a Xilinx XCVLX50 FPGA with 56
11. 59 Table 10 1 SEAD 3 CoreBus Signal Cross Reference Continued SEAD 3 CoreBus Connector Signal Name FPGA U35 J14 CORE_B129 CORE_B130 CORE_B131 CORE_B132 CORE_B133 CORE_B134 CORE_B135 CORE_B136 CORE_B137 CORE_B138 CORE_B139 CORE_B140 CORE_B141 CORE_B142 CORE_B143 CORE_B144 CORE_B145 CORE_B146 CORE_B147 CORE_B148 CORE_B149 CORE_B150 CORE_B151 CORE_B152 CORE_B153 CORE_B154 CORE_B155 CORE_B156 CORE_B157 CORE_B158 CORE_B159 CORE_B160 CORE_B161 CORE_B162 CORE_B163 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved SEAD 3 CoreBus Connector Table 10 1 SEAD 3 CoreBus Signal Cross Reference Continued SEAD 3 CoreBus Connector FPGA U35 J14 MIPS SEAD 3 Board User s Manual Revision 01 03 Signal Name CORE_B164 CORE_B165 CORE_B166 CORE_B167 CORE_B168 CORE_B169 CORE_B170 CORE_B171 CORE_B172 CORE_B173 CORE_B174 CORE_B175 CORE_B176 CORE_B177 CORE_B178 CORE_B179 CORE_B180 CORE_B181 CORE_B182 CORE_B183 CORE_B184 CORE_B185 CORE_B186 CORE_B187 CORE_B188 CORE_B189 CORE_B190 CORE_B191 CORE_B192 CORE_B193 CORE_B194 CORE_B195 CORE_B196 CORE_B197 CORE_B198 60 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 61 T
12. A3_A 34 A3_A 35 A3_A 36 Table 16 1 A3 Connector Pins Al F5 A2 G5 A3 H5 A4 15 45 F4 A6 E4 A7 M6 8 L6 A9 J4 10 5 12 5 A13 14 14 K4 15 5 16 17 A18 01 19 79 20 110 21 10 A22 23 8 24 08 25 7 26 R6 27 6 28 07 29 5 A30 06 1 5 A32 A34 W9 A35 10 A36 WI10 MIPS SEAD 3 Board User s Manual Revision 01 03 L3 81 N K3 B2 P G1 B3 N F1 B4 P G2 85 N G3 B6 P El B7 N E2 88 L F3 B9 N E3 B10 P D1 B11 N D2 B12 P B2 B13 N 03 814 P Bl B15 N C2 B16 L H3 B17 N H2 B18 P N3 B19 N M3 B20 P M2 B21 N N2 B22 P R3 B23 N 2 24 25 26 R2 B27 N P1 B28 P U2 B29 N VI 830 L T3 B31 N U3 B32 P 19 833 N 34 F8 B35 N F9 B36 P Building a User Board Signal Name A3_B 1 A3_B 2 A3 B 3 A3 B 4 A3 B 5 A3 B 6 7 A3 B 8 A3 B 9 10 A3 11 12 13 14 15 16 17 18 19 20 A3 22 23 A3 24 25 26 27 28 A3 29 30 A3_B 31 A3_B 32 A3_B 33 A3_B 34 35 A3 36 Copyright 2009 2010 MIPS Technologies Inc rights reserved 78 79 Signal Name A3_A 37 A3_A 38 A3_A 39 A3_A 40 A3_A 41 A3_A 42
13. A3_A 43 A3_A 44 45 46 47 48 49 50 51 A3 A 52 A3 A 53 A3 A 54 A3 A 55 A3 A 56 A3 A 57 A3 A 58 A3 A 59 A3 A 60 Signal Name A4 A 1 A4 AQ A4 A 3 A4 A 4 A4 A 5 A4 A 6 4 7 Table 16 1 Connector Pins Continued A37 V8 A38 V9 A39 V5 A40 W5 41 V7 42 W7 A43 Y8 44 Y7 A45 W6 46 Y6 47 45 48 AA6 A49 C6 50 AF6 A51 AJ4 52 AH4 A53 AF4 54 4 55 AE6 56 AF5 57 AD6 59 ACS A60 86 Table 16 2 A4 Connector Pins 10 837 N M11 838 P L10 B39 N L11 B40 P E8 B41 N E7 B42 P E9 B43 N F10 B44 P J9 B45 N J10 B46 P G10 B47 N H10 B48 P K8 B49 N L8 B50 P J7 B51 N K7 B52 P M7 B53 N M8 B54 P G7 B55 N G6 B56 P N7 B57 N P7 B58 P N19 B59 N B60 P Pin Polarity 2 0 2 2 MIPS SEAD 3 Board User s Manual Revision 01 03 Bank 15 5 Signal Name A3_B 37 A3_B 38 A3_B 39 A3_B 40 A3_B 41 A3_B 42 A3_B 43 A3_B 44 A3_B 45 A3_B 46 A3_B 47 A3_B 48 A3_B 49 A3_B 50 A3 51 52 A3 53 54 55 56 A3 57 58 59 VDD Signal Name 4 A4 4 3 4 4 4 5 4 6 4 7 Copyright 2009 2010 5 Technologies Inc All rights reserved B
14. Boxed Connects to Xilinx DLCx cable to allow access to Header the FPGA PIC JTAG chain The PIC is pro grammed before the board is delivered using the PIC Debug header The FPGA re programming is usually achieved via the USB download mecha nism However this connector does allow the user JTAG to access both devices Note See description of jumper J16 See Table 11 7 U46 200 pin DDR 11 DRAM Accepts a standard DDR II 533 1 8V DRAM socket module J21 EJTAG 14 pin 0 1 header EJTAG connector See Table 5 1 J20 iFlowtrace 10 pin 0 1 Boxed Header iFlowtrace Connector See Table 5 2 J22 PDtrace 38 Pin Mictor PDtrace Connector See Table 5 3 J14 400 position BGA Interface to SEAD 3 CoreBus Connector See Table 10 1 2 14 pin 0 1 header Connects to the LCD module Table 11 2 J10 PSU Connector Description 1 2 11 3 3V supply to board 3 5 7 13 15 16 17 to ground plane 4 6 19 20 SV supply to board 64 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 65 Table 11 2 10 PSU Connector Continued Name Description Asserted when power is stable from the PSU Currently not used on the board but connects to Altera PLD SV standby power Always present when the PSU is connected to the main power supply outlet Used on SEAD 3 to turn on power when the ON OFF button is p
15. Data Ox1F80 0000 2 MBytes Reserved Reserved for FPGA 1 0000 2 MBytes Boot Flash Extension Reserved for System S W 0000 4 MBytes Boot Flash System Software 0010 4 Bytes Revision Register Overlays Boot Flash Note Address 0x1FC0 0010 is special in the sense that it is overridden and does not decode to an address in the SW EPROM but rather to register address REVISION This is done to ensure future compatibility the System ROM monitor uses the REVISION register to identify the hardware platform and configure its drivers accordingly 2 3 Uncached Access of Registers To avoid potential cache coherency problems all registers e g configuration registers internal to Basic RTL mod ules and registers in the peripheral bus devices must be accessed in uncached mode If the program runs in kernel mode the registers can be accessed via the kseg1 mapping since ksegl is always noncacheable In the rest of this document only 32 bit physical register addresses are provided a 32 bit physical address can be converted to a 32 bit MIPS SEAD 3 Board User s Manual Revision 01 03 17 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Map Decode kseg1 address by it with 0xA000 0000 For example if peripheral bus controller register TIMSRAM has physical address 0x1f00 0010 the virtual kseg1 a
16. by the CPU module when it is present and ready for reset to be removed The EPLD ignores this signal to allow imple mentation of a CPU in the FPGA SIgnal asserted when 5 supply is within 5 range Signal asserted when the 3 3V supply is within 5 range Signal asserted when 3V3 and 5V standby voltage is within 5 range If the user board contains circuit that must boot or otherwise prepare itself before reset is removed then it can use the USERBOARD_READY to indicate when it is ready This is a jumper that is available for user pur pose A reset will occur when the two pins in the jumper are shorted Connect to an emulator or similar to achieve remote reset Signal is generated by the EJTAG probe when connected to the probe header J21 A reset is generated when the user pushes the SW 16 button at the front of the board MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Signal XI DONE 2 0 DONE pins of the FPGAs FPGA_RESET MODULE_PRESENT_N D5V OK D3V3 OK DVSB OK USERBOARD READY AUX RESET N RST ATX RESET N Reset when Low High High Low Low Low Low Low Low Low Unit FPGA CPU Module Pwr Monitor User Board AUX EJTAG Push But ton 42 When power is initially turned on to the board it will be in the reset state Not
17. resources on the user board When the EzUSB controller has the bus it is used to program the FPGA and to display status messages on the LCD display The resistors on the peripheral bus assure that all units are disabled when not in use The peripheral bus is a 3 3V bus and is NOT 5V tolerant The CBT block are controlled by CPLD in conjunction with the EZUSB controller as shown in Table 9 1 Table 9 1 Peripheral Bus Switch Configuration Mode USB2PI EN N USB2PI EN Peripheral bus is disconnected from FPGA Pins are available to the USB controller Peripheral bus is connected to FPGA The following signals are part of group on the FPGA MIPS SEAD 3 Board User s Manual Revision 01 03 49 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Peripheral Bus Table 9 2 PI CTRL 11 0 Group Member name Function PI SEL 4 0 Unit select These 5 bits define the unit to access according to the list below SEL must be stable while one or more of the signals PI RD N PI CS NorPI WE Nare asserted 00000 System Flash 00001 Ethernet controller 00010 SRAM Bank low 00011 SRAM Bank high 00100 UART 0 00101 UART 1 00110 LCD Display 00111 PIC Microcontroller 01000 LED blocks P amp F 01001 DIP switches P amp F 01010 Revision code 01011 Boot Flash 01100 NEWSC switches 01101 Unused Reserved 01110 Unused Reserved 01111 Unused Reserved 11000 USER boar
18. 0 I Os and 46 000 LUTs e 32 MBytes of boot Flash containing FPGA boot code and boot software 8 bits wide e Fast and easy programming of boot Flash using USB at 12 MBit s e 32 MBytes of uncommitted Flash memory 32 bits wide e 4 MBytes of uncommitted SRAM 32 bits wide e DDR II PC2700 533MHz 200 pin SODIMM socket for A80209 only e Two DIP switches for board configuration SWI Table 7 1 Table 7 2 and Table 7 3 SW2 Table 13 1 e Two uncommitted 8 position DIP switches on peripheral bus for user defined purposes e 2 line 16 character alphanumeric LCD display e 16 LEDs attached to peripheral bus Table 14 1 e Two standard 16550 UARTS including a level translator and DB9 connector and an RS232 to USB con verter that provides a USB serial port e SEAD 3 Expansion Connector to user defined with approximately 238 undefined I Os connected to the FPGA A second connector provides the peripheral bus and Xilinx programming interface for an additional two FPGAs e Jumper selectable source for FPGA configuration Table 12 1 Download from PC or using a Xilinx cable DLCx through JTAG chain Automatic boot from boot Flash e HP Logic Analyzer probes can be connected to the SEAD 3 Expansion Connector via a small optional adaptor board e EJTAG PDtrace iFlowtrace connectors for connecting directly to an internal CPU enabling the use of debug ging tools 7 9 10 These connectors are also availabl
19. 00 0230 Access RW Reset Value N A The NEWSC CTRL register allows software to switch debounce time This is an 8 bit wide register Table 3 9 NEWSC CTRL Register Reserved DEBOUNCE This field indicates debounce count used in reading NEWSC switch values 3 8 8 2 Line 16 Character Alphanumeric LCD ASCII Display Registers ASCII Address Base 0 1 00 0400 MIPS SEADTM 3 Board User s Manual Revision 01 03 27 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 3 10 ASCII Display Registers Function LCD read write control register LCD read write data register 8 bit register Bit 7 reflects LED data port bit 7 bit 1 is a 10ms pulse used by the Linux kernel to calculate CPU frequency bit 0 is the BUSY bit when set to 1 it indicates that the LCD controller is busy processing a read write transaction ASCII character in position 3 Offset Address 0x0000 0000 0x0000 0008 0x0000 0010 0x0000 0018 3 8 9 Device Reset Register Name LCD Read Write Control LCD Read Write Data CPLD LCD Status CPLD LCD Data PI_DEVRST 1F00 0480 WO 0X0 CPLD Controller The registers are 8 bits wide and are used to display characters LCD Status and Data register reside in the CPLD See the documentation from HP for additional information on how to program the HDSP 2532 ASCII display Name Address Access Reset Value The CPU USB can reset pic32 by wri
20. 4 P LED 5 P LED 6 P LED 7 F LED 0 F LED 1 Type Green LED Yellow LED Green LED Red LED Green LED Green LED Green LED Green LED Green LED Red LED Blue LED Green LED Green LED Green LED Green LED Green LED Green LED Green LED Green LED Green LED Green LED Label Activity FDPLX PHY_INIT_DONE ERROR D5V OK D3V3 OK VCC5VO CONF DONE USB DL RESET VCCSVOSTBY PLDO PLD1 PLD2 PLD3 PLD4 PLDS PLD6 PLD7 FLDO FLD1 LED DI D2 D3 04 05 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 MIPS SEAD 3 Board Users Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Description Table 14 1 LEDs Continued F LED 2 F LED 3 F LED 4 F LED 5 F LED 6 F LED 7 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Type Green LED Green LED Green LED Green LED Green LED Green LED Label FLD2 FLD3 FLD4 FLDS FLD6 FDL7 LED D22 D23 D24 D25 D26 D27 LEDs 74 75 Chapter 15 Test Points Table 15 1 lists all the SEAD 3 board test points Table 15 1 Test Points Signal Name Description GND GND VCCSVO SV voltage supply mm VCC3V3 3V3 voltage supply VCC3V3STBY 3V3 s
21. 6 Table 7 2 Synthesizer O0 Switch 46 Table 7 3 Synthesizer T s Switch SOLOS 46 8 13 000 47 Table 9 1 Peripheral Bus oo ccrta x beri pase rte netu x epo ex 49 Table 92 50 9 39 Safe Read Timing Parameters E a E a Ne e NP ees ne 51 Table 9 4 53 Table 9 5 Bus 9 53 Table 10 1 SEAD 3 CoreBus Signal Cross Reference sens 55 T 63 Table 125310 PSU Gomme cian Seide ee SE arte e ERE nade eee 64 Table 11 35 Aux 65 Table 14 18 PICS2 Deblig Gadel 65 Table 11 5 PIG32 OvG dede dan tn te in nn 65 Table 11 6 49 and J4 00 66 Table 7 7 ingaand oiana 66 6 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS
22. 9 2 X Don t care 3 Undriven 3 3 Board Controller The board controller controls the state of SEAD 3 board The SEAD 3 Board will be in one of the states at any given time The controller states are POWER UP PROGRAM FPGA PROGRAM WAIT RESET 058 DOWNLOAD ACTIVE Figure 3 1 describes the flow of board state transitions The SEAD 3 board can be used for normal operations when the controller state is ACTIVE In the ACTIVE state the controller monitors requests from the USB download port and processes the requests immediately as shown in the flow diagram In USB DOWNLOAD PROGRAM and PROGRAM _ WAIT states the peripheral bus is controlled by the Cypress EZ USB Controller CPLD drives the selects on CBT isolation switches to give control to the USB bus The FPGA gains control of the peripheral bus when the board controller returns to the ACTIVE state 22 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 4 Reset and Chip Selects Figure 3 1 SEAD 3 Board State Transitions POWER_UP Power OK FPGA_PGM Skip Program Program Done FPGA_PGM_WT USB Download Request No Request ACTIVE USB Download Request USB DWNLD USB Download Complete 3 4 Reset and Chip Selects When board is in RESET state it is held in RESET for 36ms and board becomes ACTIVE if there are no active
23. A JTAG Connector Description Supply voltage to the download cable Ground FPGA JTAG mode select FPGA JTAG clock FPGA JTAG data out FPGA JTAG data in MIPS SEAD 3 Board User s Manual Revision 01 03 Name VCC 3 3Volt GND USB_TMS USB_TCK USB_TDO USB_TDI NC NC Connectors gt 2 1 3 5 7 9 11 13 66 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 67 Table 11 8 15 CPLD JTAG Connector CPLD_TCK CLPD JTAG clock CPLD_TDO CPLD JTAG data out CPLD_TDI CPLD JTAG data in NC MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Connectors 68 Chapter 12 Jumpers Jumpers settings are listed in Table 12 1 jumpers are standard 0 1 pitch It is worthwhile getting some spares in case you lose any Pin 1 is marked with 1 On all jumpers pin numbering is cross wise 1 the end pins 1 and 2 this is not always the case on other connectors 69 Table 12 1 Jumpers Description Fit jumpers as shown in Positions 1 2 3 4 to route 10 power to the CPU module Fit jumpers as shown in Positions 7 8 9 10 to route CORE power to the CPU module Positions 5 6 are unused Network AU
24. C bus OCP bus and AHB Lite Table 10 1 SEAD 3 CoreBus Signal Cross Reference SEAD 3 CoreBus Connector J14 A30 55 FPGA U35 AD30 Signal Name CORE B6 CORE B7 CORE B8 CORE B9 CORE 8610 CORE CORE 812 CORE 813 CORE 814 CORE 815 CORE 16 CORE 817 CORE 818 CORE 8619 CORE B20 CORE B21 CORE B22 CORE B23 CORE B24 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved SEAD 3 CoreBus Connector Table 10 1 SEAD 3 CoreBus Signal Cross Reference Continued SEAD 3 CoreBus Connector FPGA U35 J14 MIPS SEAD 3 Board User s Manual Revision 01 03 Signal Name CORE_B25 26 27 28 29 CORE 830 1 831 32 833 34 835 CORE 836 837 CORE B38 CORE B39 CORE B40 CORE 841 CORE B42 CORE B43 CORE B44 CORE B45 CORE B46 CORE B47 CORE B48 CORE B49 CORE B50 CORE 851 CORE B52 CORE B53 CORE B54 CORE B55 CORE B56 CORE B57 CORE B58 56 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 57 Table 10 1 SEAD 3 CoreBus Signal Cross Reference Continued SEAD 3 CoreBus Connector Signal Name FPGA U35 J14 CORE_B59 CORE_B60 CORE_B61 CO
25. Chapter 12 69 Chapter 13 71 Chapter dE c 73 Chapter MI dull s 75 Chapter 16 Building User BOSE 0 77 161 SEAD M 3 Expansion Connector Layout Mating 83 16 2 USer Board __ _ _ ___ _ 83 Appendix V M M 9 85 Appendix B Revision III510IV 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 en ansa ansa 87 4 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved List of Figures 1 1 SOG 851 16 SEAD M 3 Board ie Figure 1 2 SEAD M 9 Board Block Diag fan 0000 Figure 3 1 SEAD 3 Board State 2 gt iem 1 USB 6 1 Reset GondIlorS Figure 9 i Rond ACOS S 0 22 0 1 1 1 10000000 Figure 16 I Front
26. IPS SEAD 3 Board User s Manual Revision 01 03 80 81 Signal Name 4 44 4 45 4 46 4 47 4 48 4 49 4 50 4 51 4 A 52 4 A 53 4 54 4 55 4 56 4 57 4 58 4 59 A4 60 1 A2 LI 4 LI 7 8 9 A A PI LOC A6 A PI LOC A7 Table 16 2 A4 Connector Pins Continued FPGA A44 AJ20 45 115 46 14 47 AK23 A48 AK22 A49 AL16 ASO AL15 51 12 52 13 54 18 55 AL19 56 118 57 AL21 58 0 59 24 60 AL23 Pin Polarity Bank 15 AL13 B44 L 45 46 Z Ul 2 gt 12 48 10 849 9 850 12 47 6 5 ALS B52 B53 AH23 22 54 55 Z vl 2 Zi 6 56 18 57 17 58 AK16 B59 B60 2 Table 16 3 86 Connector Pins Signal Name PI_LOC_AO 9 10 1 1 2 1 1 1 12 PI LOC A13 0 1 A12 A13 14 5 PI LOC 14 Signal Name PI LOC 08 PI LOC D9 PI LOC 010 PI LOC DII PI LOC 12 PI LOC D13 PI LOC 014 PI LOC DI5 PI LOC D16 PI LOC 017 PI LOC 018 PI LOC 19 PI LOC D20 PI LOC 021 PI LOC D22 Copyright 2009 2010 MIPS Technologies Inc All rights reserve
27. Mis TECHNOLOGI MIPS SEAD 3 Board User s Manual Document Number MD00682 Revision 01 03 July 1 2010 MIPS Technologies Inc 955 East Arques Avenue Sunnyvale CA 94085 4521 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Copyright 2009 2010 MIPS Technologies Inc All rights reserved Unpublished rights if any reserved under the copyright laws of the United States of America and other countries This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying reproducing modifying or use of this information in whole or in part that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited At a minimum this information is protected under unfair competition and copyright laws Violations thereof may result in criminal penalties and fines Any document provided in source format in a modifiable form such as in FrameMaker or Microsoft Word format is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions UNDER NO CIRCUMSTANCES MAY DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES INC MIPS Technologies reserves the right to change the information contained in this document to improve function design or otherwise MIPS Techno
28. RE_B62 CORE_B63 CORE_B64 865 66 67 68 69 70 71 72 873 74 75 76 77 78 79 80 81 CORE 882 83 84 885 CORE 886 87 88 89 90 91 92 93 MIPS SEADTM 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved SEAD 3 CoreBus Connector Table 10 1 SEAD 3 CoreBus Signal Cross Reference Continued SEAD 3 CoreBus Connector Signal Name FPGA U35 J14 CORE_B94 CORE_B95 CORE_B96 CORE_B97 CORE_B98 CORE_B99 CORE_B100 CORE_B101 CORE_B102 CORE_B103 CORE_B104 CORE_B105 CORE_B106 CORE_B107 CORE_B108 CORE_B109 CORE_B110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 58 MIPS SEADTM 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved
29. Reset inputs or USB download request as shown in Fig 3 1 CPLD drives reset pin of FPGAs Peripheral Bus PIC32 Ether net Controller and other devices on Peripheral bus PIC32 reset is software programmable see Section 3 8 9 Device Reset Register CPLD also drives Chip Selects of FPGAs devices on Peripheral Bus like bootflash flash sram LCD ethernet con troller and PIC32 MIPS SEAD 3 Board User s Manual Revision 01 03 23 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPLD Controller 3 5 Periodic Pulse Generator CPLD provides access to a periodic pulse generator Period is fixed to 20 ms bit 1 in CPLD Status register see Section 3 8 8 2 Line 16 Character Alphanumeric LCD ASCII Display Registers will be high for 10ms and low for 10ms with a 50 duty cycle 3 6 LCD Interface Controller The LCD Module 32610A on the SEAD 3 board is a slower device compared to the operational speed of the CPU The LCD Interface Controller in CPLD acts a synchronizer and ensures that the CPU does not overflow the display buffer Table 3 2 shows the Interface Controller functions Fig 3 2 illustrates state transitions of the LCD controller Table 3 2 LCD Interface Functional Table USB FPGA Drivers LCD Bus Function Data D7 D0 E Data D7 D0 LCD write control 2 D LCD write data LCD Read control D gt DR LCD Read Data D gt DR i D Illegal invalid write from USB 1 X 1 0 X X 0 X D
30. Sense for I O NO Pin The iFlowtrace connector J20 is a 10 pin 0 1 IDC header connected directly to the FPGA See Ref 9 for addi tional information on iFlowtrace Table 5 2 iFlowtrace Connector J20 IF TRCLK Trace Clock 1 3 IF_TRDATAO Trace Data 0 5 Trace 1 MIPS SEAD 3 Board Users Manual Revision 01 03 37 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG PDTrace iFlowtrace Table 5 2 iFlowtrace Connector J20 Description Trace Data2 Trace Data 3 GROUND IF_TRDATA2 9 IF_TRDATA3 2 4 6 8 10 GND The PDtrace connector J22 is a 38 pin Mictor connector connected directly to the FPGA See Ref 10 for addi tional information on PDTrace Table 5 3 PDTrace Connector J22 Description Trace Probe Enable Trace Clk Trace Data 15 Trace Data 14 Trace Data 13 Trace Data 12 Trace Data 11 Trace Data 10 Trace Data 9 Trace Data 8 Trace Data 7 Trace Data 6 Trace Data 5 Trace Data 4 Trace Data 3 Trace Data 2 Trace Data 1 Trace Data 0 No Connect Voltage Sense for I O Trace Clk Trace Clock Input Trace Test Mode Select Trace Test Data Input Trace Test Data Output Trace Reset Input System Reset Trace Debug Interrupt MIPS SEAD 3 Board User s Manual Revision 01 03 Pin Signal TR_PROBE_EN 5 TR_CLK TR_DATA15 TR_DATA14 1 TR_DATA13 1 13 TR_DATA12 15 17
31. Status register Soft endian register TARGET 0 Register Decode 0 1800 0040 64 bytes SD_SPDCNF 0x1B00 0050 64 bytes TARGET 1 Register Decode Ox1BIO 0110 14 bytes SEAD3 Configuration Register OxIBIC 0000 32 Kbytes 0000 16 Kbytes VPE Local Section 0000 16 Kbytes VPE Other Section Ox1B1 0000 64 Kbytes UserMode Visible Section D TARGET 2 Register Decode 0 1 20 0000 512 bytes USB 2 0 HS Controller base address 0x1B20 0000 256 bytes USB 2 0 HS Controller 0x1B20 0100 64 bytes USB 2 0 HS Controller Ox1B20 0140 192 bytes USB 2 0 HS Controller TARGET 3 Register Decode Ox1F00 0010 16 bytes PI TIMSRAM Ox1F00 0020 16 bytes Ox1F00 0040 8 bytes PI_NMISTATUS 0 1 00 0048 8 bytes PI NMIACK 0 1 00 0050 16 bytes PI SWRESET Ox1F00 0060 16 bytes PI PIC32 USB STATUS 0 1 00 0070 16 bytes PI SOFTENDIAN 2 2 Second level Address Mapping The TARGET 3 device is responsible for subdecoding in the 0x1C000 0000 Ox 1FFF FFFF address space See Table 2 3 for the memory map Table 2 3 SEAD 3 Physical Memory Map as Decoded by Target 3 Base Address Size Device Function 0 1 00 0000 32 MBytes System FLASH TARGET 3 Data 0 1 00 0000 4 MBytes System SRAM TARGET 3 Data 16 MIPS SEAD 3 Board Users Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved
32. TO DIX enable network cable auto switching for uplink In Disable Out Enable Default Enable Fit jumpers as shown in the Position column to close the FPGA chain normal operation Default is fitted If further devices are added to the chain J16 must be left open Connects to an auxiliary reset Connecting pin 1 to pin 2 GND will cause a reset Default is OPEN Fit jumpers as shown in the Position column to route the FPGA temperature sensor to the temperature monitor IC normal opera tion Default is fitted Position 1 2 3 4 5 6 7 8 9 10 2 pin 0 1 header 1 2 2 pin 0 1 header 1 2 3 4 5 6 7 8 9 10 Reserved Pins 10 pin 0 1 header 2 pin 0 1 header AUX RESET 10 pin 2mm header Ref J19 19 16 J18 J12 MIPS SEAD 3 Board Users Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Jumpers 70 71 Chapter 13 Switches Switches are listed in Table 13 1 together with their functions Table 13 1 Switches Description NMI Power ON button In benchtop environment this button will bring the ATX power supply out of standby It can also be used to generate NMI to the CPU for example to shut down the PSU again Reset button
33. TR_DATA10 19 TR_DATA9 2 TR_DATA8 1 23 TR_DATA7 5 2 TR_DATA6 27 TR_DATAS 9 2 TR_DATA4 3 TR_DATA3 33 TR_DATA2 37 TR_DATAO 6 TR_CLK 8 TR_TCK 12 14 6 1 TR_TRSTN 1 TR_RSTN 20 TR_DINT 22 TR_DM Copyright 2009 2010 MIPS Technologies Inc All rights reserved 38 39 Table 5 3 PDTrace Connector 22 Continued 24 26 28 30 32 34 NC Description No Connect Trace Trigger Out Trace Trigger In 36 TR_TRIGOUT 38 TR_TRIGIN MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EJTAG PDTrace iFlowtrace 40 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 6 Reset Operation The reset signals the board are generated by Xilinx CPLD from a number of input signals as shown in Figure 6 1 mono stable circuit guarantees that reset is asserted at least 35 ms Figure 6 1 Reset Conditions VCC XI DONE RESET GND VCC vec AUX J18 MODULE PRESENT Module GND VCC D5V OK Pwr Moriior D3V3_OK ae EJTAG J21 DVSB_OK VCC V6C Push button SW16 User USERBOARD READY Board VCC GND GL_RST GL_RST_N Reset LED D10 GL 851 GL PI RST the input signals except MODULE PRESENT can cause reset Th
34. Technologies Inc All rights reserved Table 11 8 J15 6 M Table 12 1 Table 13 1 M M ______ _ _ _ _ __ _ _ _ _ _ __ _ ee Table 15 1 00000000 Table 16 1 AS Connector PINS _ _ Table 16 2 A4 Connector PINS essaie ainsi Fe Fa Table 16 9 AG Connector MIPS SEADTM 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 1 Introduction This document describes the MIPS SOC Evaluation And Development SEAD 3 board The SEADTM 3 board is basically playground where users can develop and verify their hardware and IP that includes MIPS CPU core The SEAD 3 board contains CoreBus Connector that accepts a small PCB with a MIPS 4K M14K 5K 24K or 34K core The CPU interfaces to a large Xilinx FPGA which is uncommitted and available for user IP The board is shipped with a ver
35. Ts 16 1 SEAD 3 Expansion Connector Layout and Mating The user board should have three mating connectors for stability even when not all signals are required See Figure 16 2 The Samtec Order Number for the connectors is QSH 060 01 L D A Figure 16 2 User Board Connectors and Mating PSU 0070 50 00 mm L El Debug Connector 16 2 User Board Power The user board receives 3 3V power from the SEAD 3 through the user connectors Each connector has 1 power pin Power should be limited to 1 per pin There is a secondary power socket J13 which can provide a 5 volt and 12 volt supply directly from the ATX connector See Table 11 3 MIPS SEAD 3 Board Users Manual Revision 01 03 83 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Building a User Board 84 Appendix A References 1 5 3 Board Getting Started MIPS Document 7 2 MIPS SEADTM 3 Basic RTL User s Manual MIPS Document MD00693 3 SEADIM 3 Basic RTL Reference Manual MIPS Document MD00692 4 SEAD 3 IO Processor User s Manual MIPS Document MD00630 5 SEAD 3 Board Schematics MIPS Document MD00648 6 MIPS Global Interrupt Controller User s Manual MIPS Document MD00695 7 Use
36. V DDR II DRAM module DRAM is not avail able on the LX50 equipped boards The controller is built into the FPGA The DRAM interface signals on the FPGA are e DRAM control pins See Table 8 1 below e MC_DQ 63 0 MC DQMB 7 0 DRAM data pins e A 13 0 MC BA 2 0 DRAM address The MC_CTRL pin group on the FPGA contains the following members Table 8 1 50 Group Member Name MC_RAS_N MC_CAS_N MC CS 1 B MC CKBE 1 0 MC CLK 1 0 P MC CLK 1 0 N DDTT 1 0 MC SDA NOTE Currently we only support single sided DRAM modules with a maximum size of 512 MB Only 432MB is accessible by software MIPS SEAD 3 Board User s Manual Revision 01 03 47 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved DRAM Interface 48 Chapter 9 Peripheral Bus The peripheral bus on the board is used primarily to access the on board resources such as UARTs Flash SRAM etc Use the bus to access the on board resources only and ignore the signals on the user connector Use the bus to access on board resources and resources on the user board When required signal members can be added to the bus using the uncommitted FPGA pins The user can change the timing and use different timing for the on board resources and
37. a write operation to the on board resources Figure 9 2 Write Access PI A 23 0 SEL 4 0 PI CS PI BE N 3 0 PI RD WE PI D 31 0 The events are e Setup a valid address and unit select vector A 13 0 PI SEL 4 0 e Assert chip select CS N PI CS is used together with SEL to generate a chip select to the addressed unit For units not using chip select SEL 3 0 is used with WE to generate a unit specific write strobe Then assert the write strobe s BE N 3 0 Valid write data must meet the setup hold time with respect to the rising edge of the write strobe s All combinations are valid even the case where no write strobes are asserted e After PI BE N 3 0 is de asserted the controller may de assert CS and finally when PI CS is de asserted the controller can change LI A 13 0 and LI SEL 4 0 Safe values for the parameters in the figure above are listed below Again these are very conservative values guaran teed to work for all units MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 52 9 2 Peripheral Bus Resources 53 Table 9 4 Write Timing Parameters Description Setup time of address and unit select vector before chip select assertion Chip select asserted to write strobe s asserted Write strobe s pulse wid
38. able 10 1 SEAD 3 CoreBus Signal Cross Reference Continued SEAD 3 CoreBus Connector Signal Name FPGA U35 J14 CORE_B199 CORE_B200 CORE_B201 CORE_B202 CORE_B203 CORE_B204 CORE_B205 CORE_B206 CORE_B207 CORE_B208 CORE_B209 CORE_B210 CORE_B211 CORE_B212 CORE_B213 CORE_B214 CORE_B215 CORE_B216 CORE_B217 CORE_B218 CORE_B219 CORE_B220 CORE_B221 CORE_B222 CORE_B223 CORE_B224 CORE_B225 CORE_B226 CORE_B227 CORE_B228 CORE_B229 CORE_B230 CORE_B231 CORE_B232 CORE_B233 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved SEAD 3 CoreBus Connector Table 10 1 SEAD 3 CoreBus Signal Cross Reference Continued SEAD 3 CoreBus Connector FPGA U35 J14 AD32 K39 AL34 K40 MIPS SEAD 3 Board User s Manual Revision 01 03 Signal Name CORE_B234 235 8236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 8263 264 62 Copyright 2009 2010 MIPS Tec
39. annel of the UART is connected to a 9 way Dtype via a level RS232 level shifter The other channel is connected to an FT232RL controller to provide USB to Serial conversion Access Type RW RW RW RW 00000 00001 00010 00011 00100 00101 PI SEL 4 0 Resource System Flash Ethernet Controller SRAM Low SRAM High UARTO UARTI MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 9 5 Peripheral Bus Resources Continued Description The display is driven by a state machine in the CPLD This allows the complex timing for the display to be handled in hardware Command Data interface to the PIC32 IO subsystem The Bar LEDs consist of two bank of 8 LEDs They are driven by the CPLD which contains programmable registers that allow the user to switch each LED to an on or off state After reset the register is cleared and all LEDs are off The DIP switches are connected to the CPLD which contains registers to allow the user to read the state of the switches All switch lines are pulled low when the switch is open A closed switch will result in the user reading a 1 The revision code is read through another register within the CPLD Bits 7 4 indicates the board ID which is 0001 for SEAD 3 Bit 3 0 indicates the board revision star ing with 0000 The boot Fl
40. ash contains the boot SW and the FPGA configuration as described in Section 4 2 1 Sending Data to the Board The device is organized as 32M x 8 bits There are 3 FPGA config blocks and 1 boot S W block Keypad switches Unused Reserved Unused Reserved Unused Reserved This PSEL is reserved for User I O added via the SEAD 3 Expansion Connector Access Type RW RW RW RO RO RW RW RW RW RW MIPS SEAD 3 Board User s Manual Revision 01 03 SEL 4 0 00110 01111 01000 01001 01010 01011 01100 01101 01110 01111 11000 lt Resource LCD Display PIC32 10 Controller LEDs F_LED D20 D27 P_LED D12 D19 DIP Switches F_SWITCH SW3 P_SWITCH SW4 Revision code Boot Flash NEWSC North SW5 East SW8 West SW6 South SW11 Center SW7 Reserved Reserved Reserved User Expansion Copyright 2009 2010 MIPS Technologies Inc All rights reserved 54 Chapter 10 SEAD 3 CoreBus Connector The CoreBus interface defined in Table 10 1 is the interface between the CPU and the FPGA The SEAD 3 board is designed to accept a module with a variety of CPU cores The bus is not defined as any particular bus type since the user may define any of the 264 signals to be any signal of a desired bus as long as both ends match MIPS has defined three bus types for various MIPS cores E
41. be the last line in all download files GET_MAN This string will place the board in a mode where a small manual can be retrieved by reading the USB port lt others gt Reserved Example of code download format Example IR 1fc00000 I n 12345678 23456789 3456789A 456789AB 56789ABC 6789ABCD 789ABCDE 89ABCDEF 9ABCDEFO 1 BCDEF012 123 DEF01234 EF012345 F0123456 01234567 always 16 words in a block gt DL_DONI MIPS SEAD 3 Board User s Manual Revision 01 03 33 Copyright 2009 2010 MIPS Technologies Inc All rights reserved USB Download The example will reset the download system erase the sector starting at 1fc00 0000 and write 16 words starting at this address Finally the board will return to normal operation due to the gt DL_DONE display command If an error should occur during Flash download the ASCII display will show an error message as described in Table 4 6 Table 4 6 Flash Download Error Messages Message Illegal command received e g is received not Illegal command received e g is received Illegal hex received in data or addr e g ABCDEFGH both is illegal characters Hex expected always data blocks of 16 words Happens if e g a comment is received in the middle of a block of 16 words Block erase suspended Err e
42. changing the default values in the BRTL build However most of the peripherals on this bus have minimum and max imum cycle timings The bus contains 32 data signals PI_D 31 0 25 address bits PI_A 24 0 and control signals See Chapter 9 Peripheral Bus on page 49 for details SEAD 3 128 238 Two connectors carry uncommitted signals from the FPGA Depending on the Expansion board variant you will have access to either 128 LX50 or 238 LX110 signals Connector A3 A4 A6 DRAM bus 101 The DDR II DRAM is connected to dedicated pins on the FPGA LX110 version only Check Chapter 8 DRAM Interface on page 47 for details 12 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 1 1 SEAD 3 Board at a Glance Table 1 1 Busses on SEAD 3 Board Continued Number of Signals Description EJTAG 7 These buses carry EJTAG iFlowtrace and PDTrace signals for debugging of the iFlowtrace 5 CPU PDTrace 28 The EJTAG connector is a standard 2x7 pin 100 mil header which can be connected to an EJTAG probe One pin is intentionally removed for polarization For more information on EJTAG See 7 The iFlowtrace connector is a 2x5 pin 100 mil header which can be connected to an iFlowtrace probe See Ref 9 The PDTrace connector is a 38 pin Mictor connector which can be connected to a Trace probe See 10
43. d Signal Name A4 B 44 A4 B 45 4 B 46 A4 B 47 A4 B 48 A4 B 49 A4 B 50 A4 B 51 A4 B 52 A4 B 53 A4 B 54 A4 B 55 A4 B 56 A4 B 57 A4 B 58 A4 B 59 VDD MIPS SEAD 3 Board User s Manual Revision 01 03 Building a User Board Table 16 3 A6 Connector Pins Continued Signal Name 3E Signal 16 19 2 2 22 PI_LOC_SELO 2 z 16 17 7 18 19 _ 20 gt 21 2 2 3 4 T 5 26 E 27 A29 PI_LOC_SEL3 A32 PI LOC BE NI 35 36 37 38 2 39 ed 0 1 2 2 3 4 5 6 7 8 E 9 50 PI_LOC_USER_INT A SP_SCK A4 PI LOC EXTRN 4 XI_DONEI 4 4 4 XI_WRITE_N A A XI PROGRAM A51 XI BUSY A52 PI LOC D7 MIPS SEAD 3 Board User s Manual Revision 01 03 PI LOC D24 B17 PI LOC D25 B18 PI LOC D27 PI LOC 030 PI LOC WE N GPIOI GPIO4 GPIO6 GPIO9 GPIO12 025 5 50 CL IV CLKO 5 82 Copyright 2009 2010 5 Technologies Inc All rights reserved 16 1 SEAD 3 Expansion Connector Layout and Mating Table 16 3 A6 Connector Pins Continued Signal Name Signal Name JT_TDO 53 PI LOC 06 FPGA CLK N NC PI LOC D3 PI LOC D2 A58 PI LOC DI PI LOC DO VDD B60 GL A3 LV CLKI E d XI TDO B54 54 PI LOC D5 FPGA CLK P PI LOC D4 pes
44. d PI RD N Read strobe PI CS N Common chip select PI BE N 3 0 Write enables PI BE N 3 corresponds to PI D 31 24 BE N 2 corresponds to D 23 16 PI BE corresponds to PI D 15 8 PI BE N 0 corresponds to D 7 0 PI UARTO INT N Interrupt from UARTO PI UARTI INT N Interrupt from UARTI 9 1 Access Timing The peripheral bus is a simple asynchronous bus with no external ready for access termination All on board resources are asynchronous devices The user may extend the bus to the user board and add additional signals such as acknowledge ready as required The user may even add synchronous devices because all clock inputs to the FPGA are available on the user connector as well 9 1 1 Read Access The basic peripheral bus read access pattern is shown in Figure 9 1 50 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 9 1 Access Timing Figure 9 1 Read Access PI A 23 0 SEL 4 0 CS RD PI D 31 0 The events are e Setup a valid address and unit select vector A 13 0 SEL 4 0 e Assert chip select CS PI CS is used together with SEL 4 0 to generate a chip select to the addressed unit For units not using chip select SEL 4 0 is used with RD to generate a unit specific read strobe Then assert the read strobe RD and the ad
45. ddress that kernel mode programs should use is 0x 1F00 0010 0xA000 0000 OxBF00 0010 2 4 Accesses to Illegal Reserved Addresses If the CPU attempts to access any of the above reserved areas the X bus controller will map those accesses to X bus Target 2 as type Data This target s normal function is Register only so it is easy for this target to detect these illegal accesses and it simplified the implementation of the X bus controller The X bus targets will generally signal read bus error to the master in case of illegal read accesses The master will forward any read bus error to the CPU which will take an exception In order to make sure that any illegal write access is noticed all the X bus targets are required to issue a write access error pulse to some extra NMI logic in the peripheral bus controller when they detect an illegal write access The NMI logic will then cause the CPU to take an NMI exception whenever a write access error pulse is detected from any of the targets 2 5 BRTL Register Definitions Table 2 4 SEAD3_CFG Register Field Descriptions Address 0x1B10 0110 Access RO RO Description Must be written as zero returns zero on read 0 Not present no USB support 1 Present USB HS 2 0 Controller Interface 0 Not present no dram support and sram will be mapped to address 0x0 1 Present DRAM interface is DDR2 0 SRAM size is 4MB FPGA OPT switch in OFF posi
46. dressed unit will drive data on the peripheral data bus LI D 31 0 controller must sample read data when RD is de asserted e After PI RD N is de asserted the controller may de assert CS and finally when CS de asserted the controller can change A 13 0 and SEL 4 0 Safe values for the parameters in the figure above are listed in Table 9 3 This is by no means the ideal timing for all units on the bus Some units are fast like SRAM while others are slow like the boot Flash However the values below which represent a kind of overall worst case timing will guarantee timing for all units Table 9 3 Safe Read Timing Parameters Symbol Signals Description max Unit PI CS N PI RD N Chip select asserted to read asserted ns tr3 PI RD N Read strobe pulse width 200 ns tr4 PI RD N PI CS N Chip select hold after read strobe de asser 5 ns tion MIPS SEAD 3 Board User s Manual Revision 01 03 51 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 9 3 Safe Read Timing Parameters Continued PI_A 23 0 PI SEL 4 0 Hold time of address and unit select vector after chip select de assertion PI RD N PI D 31 0 Read data valid after read strobe assertion PI RD MI D 31 0 Read data hold after read strobe de assertion 9 1 2 Write Access Peripheral Bus PI CS N Figure 9 2 shows the basic access pattern for
47. e Usage 1f80 0000 gt 1fOf ffff 2 MBytes Contains FPGA configuration DO NOT OVERWRITE 1fa0 0000 gt 1fff ffff Contains boot SW e g YAMON MIPS SEAD 3 Board User s Manual Revision 01 03 35 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved USB Download 36 Chapter 5 EJTAG PDTrace iFlowtrace Depending on the use model of the SEAD 3 board the CPU may either be placed on the small CPU module or if the debug connectors are required it be placed on the FPGA_module 3 by loading the CPU along with BRTL into the SEAD 3 FPGA There are three debug connectors on SEAD 3 e e PDTrace iFlowtrace On the EJTAG connector 121 one pin is intentionally removed 12 from the connector to assure correct tion with the probe header The connector signals are routed directly to the EJTAG interface on the CPU core The only exception is the EJTAG_RST_N signal which is routed to the CPLD where it can issue board reset See Ref erence 7 for additional information on EJTAG Table 5 1 EJTAG Connector J21 1 EJTRSTN Test Reset Input EJTDI Test Data Input EJTDO Test Data Output EJTMS Test Mode Select Input EJTCK Test Clock Input Description EJRST_N System Reset EJDINT Debug Interrupt 2 4 6 8 10 GND Ground 14 VIO Voltage
48. e intention of MODULE PRESENT was to keep the board in reset if no CPU module was present but this signal is intensionally ignored in the EPLD to allow implementation of the CPU in the FPGA MIPS SEADTM 3 Board User s Manual Revision 01 03 41 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Reset Operation The generates four reset output signals GL_PI_RST active high and GL_RST_N GL RST active low GL_PI_RST GL_PI_RST_N signals are used to reset units on peripheral bus while the other two reset signals are used for the rest user board CPU FPGA etc The two sets of reset allows the USB controller to access the peripheral bus for download and in the meantime keep the rest of the board in reset The reset state is observed on the red LED D10 When ON GL_RST GL_RST_N is asserted Table 6 1 summaries the reset conditions and contains references to the schematic sheets where the reset signals are generated Table 6 1 Reset Conditions Description The FPGAs assert their DONE signals high when the FPGA is successfully configured The FPGA validates the CRC on the configu ration data stream and if it fails it will not assert DONE The combined DONE state can be observed on LED D8 CONF DONE This signal is driven by a normal IO pin on the FPGA It allow the user to implement circuitry that can reset the board This signal is driven low
49. e on the FPGA based Module 3 7 Figure 1 2 shows a block diagram of the board with all the major busses MIPS SEAD 3 Board User s Manual Revision 01 03 11 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction Figure 1 2 SEAD 3 Board Block Diagram Debug conscie Generation Debug console RTC WDT User Defined Bus 119 pins Debug console Optional MIPS COREBUS 264 pins 861 Optional with LX110 155 LV or j User Defined Bus 119 pins 1 722 SDRAM Bus 8 PHY Optional with LX110 155 BOOT Option Config _jEzuse Flash Switches Peripheral Bus 119 pins Char 32Mb 4Mb Display Flash Table 1 1 describes the busses shown in Figure 1 2 PIC32 Cntrler Table 1 1 Busses on SEAD 3 Board Number of Signals Description CoreBus 264 The CoreBus bus 15 the signal interconnect between the module and the BRTL signals are not bus specific and several busses can share the signals The primary bus support is for EC AHB lite and OCP For users incorporating the CPU with the BRTL this connector can be used for other peripherals This bus is always connected to the FPGA J14 78 Peripheral Bus This is the main peripheral bus used to connect the peripheral devices The timing of this bus can be varied either by software or by
50. e that if the board is setup to download FPGA configuration via cable then the board will remain in reset until download is complete Otherwise the FPGA will boot from the boot Flash MIPS SEADTM 3 Board User s Manual Revision 01 03 43 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Reset Operation 44 Chapter 7 Clocking The board has three clock synthesizers The following clocks are routed to the FPGA e Synthesizer 0 Selectable e LV Clock output CI CLKO Clock output Synthesizer 1 Selectable e Clock output Clock output e 20MHZ 20 MHz fixed frequency clock to drive the PIC32 Synthesizer 2 Fixed USBPHY CLK 24MHZ 24 MHz clock to drive the USB Phy USB CLK 24MHZ 24 MHz clock to drive the EZUSB Microcontroller ETH 25 7 25 MHz clock to drive the Ethernet controller 24 576 24 576 MHz clock Not currently used e GL IN P P Side of the 200MHz differential clock for the DRAM controller N Side of the 200MHz differential clock for DRAM controller Module Clock e CI MOD Clock source for FRGA_Module 3 It can be derived from either Synthesizer 0 Synthesizer 1 The clock source for GL MOD LV CLK is con
51. ere are between 128 and 238 completely uncommitted signals depending on the FPGA version between the expansion connectors and the FPGA Furthermore the entire peripheral bus is avail able and the user can use this bus as is or modified with added functionality The SEAD 3 board interfaces to the user board through three high density connectors located on either side of the CPLD and to the north of the FPGA The connectors on the SEAD 3 board are from Samtec Order Number QTH 060 05 L D A Figure 16 1 Front Panel Connector 1 Expansion Samtec Connector 01 02 81 03 62 04 52 117 59 60 118 59 119 A60 120 B60 GND Expansion Connector Pin Mapping Samtec Expansion Connector The pin list for the SEAD 3 board is shown in Table 16 1 through Table 16 3 The color codes used in the pin tables are shown below CLK N CLK P VREF GCLK MIPS SEAD 3 Board User s Manual Revision 01 03 77 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Signal Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A3 16 17 18 19 20 A3_A 21 A3_A 22 A3_A 23 A3_A 24 A3_A 25 A3_A 26 A3_A 27 A3_A 28 A3_A 29 A3_A 30 A3_A 31 A3_A 32 A3_A 33
52. ess 0 1 00 0218 Access R W Reset Value 0x00000000 The FLED register allows software to program the state of the 8 F LED bits on the peripheral bus Table 3 6 FLED Register 8 bits corresponding to the 8 F LED bits 0 0 0 Off all P LED bits off 1 On 3 8 5 NEWSC LIVE Register Name NEWSC LIVE Address Ox1F00 0220 Access RO Reset Value 0 The NEWSC LIVE register allows software to read the present state of NEWSC switch This is an 8 bit wide regis ter Table 3 7 NEWSC LIVE Register Bits Field name Function Initial Value 7 5 Reserved 0 sw_cpld_e Switch position East sw_cpld_w Switch position West 0 sw_cpld_c Switch position Center 0 26 MIPS SEADTM 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 8 CPLD Registers 3 8 6 NEWSC REG Register Name NEWSC REG Address 0 1 00 0228 Access RO Reset Value 0 NEWSC REG register allows software to read the state of NEWSC switch after debounce This is an 8 bit wide register Table 3 8 NEWSC REG Register Bits Field name Function Initial Value 7 5 Reserved 0 Switch position North after debounce lo sw_cpld_e Switch position East after debounce sw_cpld_w Switch position West after debounce Switch position South after debounce 31 0 sw_cpld_c Switch position Center after debounce 0 3 8 7 NEWSC CTRL Register Name NEWSC CTRL Address 0 1
53. he LCD display which are both on the peripheral bus are the main targets of USB accesses The peripheral bus is normally connected to the so the controller in the peripheral can access the bus However when USB download is enabled the bus 15 disconnected from FPGA by tri stating and CBT switches connect the USB controller to the peripheral bus To boot the board must be configured with the CBT switches OFF Data will flow from the boot Flash through to the FPGA The USB controller has its own private serial port This is only intended for debug of the USB firmware so in most cases the user can ignore this port The CPLD controls the reset signals based on the FPGA mode of operation 30 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 2 USB Download Format Table 4 1 FPGA Configuration Modes Mode Comment USB download In this mode the USB controller takes the role as master on the peripheral bus It can access the ASCII display and the boot Flash FPGA config This is the mode in which the FPGA is configured In this mode the USB controller reads data from the system Flash and writes it to the configuration data port of the FPGA This state is entered after a reset or after a USB download NOTE We recommend the USB download for configuring the FPGAs because the config data is stored in flash and will be wr
54. he SEAD Basic RTL User s Manual for a description Software can only read a switch register with the exception of NEWSC CTRL and software can either read or write an LED register 3 8 CPLD Registers 3 8 1 P SWITCH Register Name PSWITCH Address 0 1 00 0200 Access RO Reset Value N A This register allows software to monitor the state of the 8 bit P SWITCH 53 on the peripheral bus Table 3 3 PSWITCH Register EST Faune 7 0 8 P SWITCH bits physical switches are num N A bered 8 to 1 0 OFF Open 1 ON Closed 3 8 2 F SWITCH Register Name FSWITCH Address Ox 1F00 0208 Access RO Reset Value N A This register allows software to monitor the state of the 8 bit F SWITCH 54 on the peripheral bus Table 3 4 FSWITCH Register Bits Field name Function Initial Value 7 0 8 F SWITCH bits physical switches are num bered 8 to 1 0 OFF Open 1 ON Closed 3 8 3 P LED Register Name PLED Address 0 1 00 0210 Access R W Reset Value 0x00000000 MIPS SEADTM 3 Board User s Manual Revision 01 03 25 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CPLD Controller The PLED register allows software to program the state of the 8 P LED bits on the peripheral bus Table 3 5 PLED Register N A 31 8 Reserved 7 0 VAL 8 bits corresponding to the 8 P LED bits 0 0 0 Off all P LED bits off 1 On 3 8 4 F LED Register Name FLED Addr
55. hnologies Inc rights reserved Chapter 11 Connectors All connectors on the board are listed in Table 11 1 On the PCB Pin 1 on connectors is marked with a 1 or a dot The Sheet column lists the diagram sheet instantiating the connector 63 Table 11 1 Connectors Description Connects to a standard ATX power supply A power supply with standby current supply of mini mum 720 mA is required 1A 1 5A peak recom mended for the 5V standby voltage See Table 13 2 Connector for a 3 wire 5Volt fan Pin 1 Fan Tach 2 5 0 Pin 3 GND These are the connectors that facilitate add on boards The A6 pin is pre defined A3 and A4 have undefined pins connected to FPGA Note Depending on the board variant not all of the pins on A4 are available Connects to Cypress EZ USB Controller for USB download to update Bitfiles and board Firmware Hi Speed USB 2 0 only available on A00 R00209 This connector contains all the I O from PIC32 I O controller See Table 11 5 Standard 10 100 Ethernet Port RS232 COMM Port 1 RS232 COMM Port 0 with built in FT232 driver to provide fast USB connection Provides a simple 3 wire connection for access to the serial port in the USB controller This is only intended for debug of the USB controller firmware so normally this connector is not used See Table 11 6 Type ATX PSU
56. itten on power up Normal operation The FPGA is in control of the peripheral bus When the board powers on it enters a reset state The board will remain in reset until the FPGA is successfully con figured either by data from the boot Flash or by cable download When the USB controller detects a file download it enters the USB download state resets the board and keeps the board in reset until all data has been downloaded Following the download if the FPGA is configured for Flash boot the FPGA is re configured Data sent to the board will have a start command R indicating the start of data and a stop command indicating the end of data gt DL_DONE Note that after the start command is received the board will remain in the USB down load state until the end command is received So if the data download is aborted the board will stay in the download state 4 2 USB Download Format The SEAD 3 board presents itself to the USB host as a bi directional printer device As a device in the printer class the SEAD 3 board can use existing printer drivers for example in Linux and Windows to access the board In addi tion to the control endpoint the board supports one bidirectional high speed 12 Mbit s bulk endpoint Table 4 2 USB Endpoints on SEAD 3 Board Endpoint Direction seen from host Type 0 IN Control 0 OUT Control 2 IN Bulk 2 OUT Bulk Endpoint 0 is the standard control endpoint and is used for exa
57. logies does not assume any liability arising out of the application or use of this information or of any error or omission in such information Any warranties whether express statutory implied or otherwise including but not limited to the implied warranties of merchantability or fitness for a particular purpose are excluded Except as expressly provided in any written license agreement from MIPS Technologies or an authorized third party the furnishing of this document does not give recipient any license to any intellectual property rights including any patent rights that cover the information in this document The information contained in this document shall not be exported reexported transferred or released directly or indirectly in violation of the law of any country or international law regulation treaty Executive Order statute amendments or supplements thereto Should a conflict arise regarding the export reexport transfer or release of the information contained in this document the laws of the United States of America shall be governing law The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United States government Government
58. mple as device descriptors and stall un stall end points Endpoint 0 supports all standard requests defined by the USB 1 1 standard and the additional requests defined for printer class devices MIPS SEAD 3 Board User s Manual Revision 01 03 31 Copyright 2009 2010 MIPS Technologies Inc All rights reserved USB Download Endpoint 2 15 a bidirectional bulk endpoint used for data transfer The host will use the bulk out pipe to send data to the board The use of the bulk in pipe is optional as described below 4 2 1 Sending Data to the Board Data is sent to the board through the bulk out pipe The exact method used to access the bulk out pipe depends on the operating system For Linux the user can issue command similar to cat xx fl gt dev usblp0 where xx fl contains the data to send to the board and dev usb1p0 is the device interface for the bulk pipe For Windows the user must open the file in the Wordpad editor and print it to the port representing the SEAD 3 board We suggest that all 1 files are associated with the Wordpad editor to assure that this editor is used to open the files See Ref 1 for more information on driver installation for Windows and Linux The file sent to the board is a pure text file containing ASCII characters Keep the number of characters per line below 40 characters to avoid line splitting when Windows assumes it prints to a true printer All lines mu
59. other trademarks referred to herein are the property of their respective owners Template nB1 03 Built with tags 2B MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table of Contents cca me 11 5 2 Board Glace Chapter 2 Memory Decode 2 1 ILCII51 ICV6I Address 2 2 Second level Address Mapping 2 9 Uncached Access Of 2 4 Accesses to lllegal Reserved Addresses 2 5 Register Definitions 97V Chapter CPLD Controller 1 61161616 2 2 Module Voltage Control antenne nettement 3 3 Board Controller sisi 3 4 Reset and Chip 3 5 Pulse Generator 3 6 LCD internace 3 7 Switches and LEDS RET M 9 8 2 3 88 PAVED aii cepe oa
60. pin 0 1 Fan connector Expansion connectors 120 pin Samtec connectors USB type Mini B con nector USB type Mini B con nector 3x18 pin 0 1 header RJ45 Ethernet connector 9 way D type connector USB type Mini B con nector 3 pin 0 1 header PCB Label USB DBG Ref J10 J11 A3 A4 A6 Pl MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Connectors Table 11 1 Connectors Continued PCB Label Type Description J3 PIC DBG 3 pin 0 1 header Provides a simple 3 wire connection for access to the serial port in the PIC32 controller This is only intended for debug of the PIC32 controller firm ware normally this connector 15 not used See Table 11 6 J PIC DEBUG 6 pin 0 1 dual row This connector allows the user to connect a Micro Header chip ICE probe to the PIC32 controller for firmware development See Table 11 4 J13 3 pin Plug header Green Provide auxiliary power for add on board Pin 1 5V Pin 2 GND Pin 3 12V These pins are directly connected to the ATX_PSU connector See Table 11 3 J15 CPLD JTAG 14 pin 2mm Boxed Connects to Xilinx DLCx cable to allow the CPLD Header to be programmed The CPLD is programmed before the board is delivered and normally it should not need to be re programmed See Table 11 8 J17 FPGA JTAG 14 pin 2mm
61. r s Manual MIPS Document MD00008 8 Specification MIPS Document MD00047 9 iFlowtrace Specification MIPS Document MD00526 10 PDTrace Specification MIPS Document MD00136 11 FPGA Module 3 Schematics MIPS Document MD00663 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved References 86 Appendix B Revision History Change bars vertical lines in the margins of this document indicate significant changes in the document since its last release Change bars are removed for changes that are more than one revision old This document may refer to Architecture specifications for example instruction set descriptions and EJTAG register definitions and change bars in these sections indicate changes since the previous version of the relevant Architecture document Revision Date Comments 01 00 November 24 2009 Initial release 01 01 February 19 2010 Fix error in Table 2 6 01 02 March 10 2010 Add description of CPLD registers Add new fields to SEAD 3_CFG register Add Periodoc Pulse Generator to CPLD 01 03 July 1 2010 Add description of expansion connector MIPS SEADTM 3 Board User s Manual Revision 01 03 87 Copyright 2009 2010 MIPS Technologies Inc All rights reserved
62. ra Error in block erasure or clear lock bits Err prog Error in programming or set block lock bits Low volt Low programming voltage detected Lock det Master lock bit Block lock bit or RP lock detected If an error occurs the USB controller ignores all data until the next R command A R command will always reset the download system regardless of state even if it occurs in the middle of a data stream The following commands will always bring the board out of download mode regardless of the previous state Get in sync Back to normal operation gt DL_DONE The boot Flash device is 32 MBytes see Table 4 7 In programming mode the USB controller can access all 32 Mbytes The USB controller uses 32 Kbyte pages together with a page address register to access the full 32 Mbytes Table 4 7 Boot Flash Layout USB Controller Table 1 Area Size Usage 1 00 0000 gt 1e7f ffff Contains FPGA configuration 1e80 0000 gt leff fff 1f00 0000 gt 1f7f ffff 1 80 0000 gt Contains FPGA configuration Contains FPGA configuration Contains FPGA configuration and boot SW e g YAMON When the CPU has control of the bus only the top 8 MBytes can be seen as listed in Table 4 8 34 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 2 USB Download Format Table 4 8 Boot Flash Layout FPGA Area Siz
63. rved Reserved 0 1840 0000 12 MBytes Reserved Reserved 0 1 00 0000 64 MBytes Memory 10 TARGET 3 The X bus controller decodes only address bits 28 20 in order to map the accesses to the correct target ports Since the BIU interface address bits 35 29 for EC bus 31 29 for AHB and 0CL are not included in the address decoding the address segment 0x0 0000 0000 0x0 1 FFF FFFF will be mirrored to 0x0 2000 0000 0x0 3FFFF FFFF and 0x0 4000 0000 0x0 5FFF FFFF etc MIPS SEADTM 3 Board User s Manual Revision 01 03 15 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Memory Map Decode Although the physical address bus width on the EC interface is 36 bits we will only show 32 bit addresses in the rest of this document because the upper 4 bits are not decoded and should always be zero Table 2 2 Target Register Decode Presence Detect Configuration Presence Detect Read Address register Presence Detect Read Data register GIC Interrupt Controller Base offset 0x0000 to Ox7fff Base offset 0x8000 to Oxbfff Base offset 000 to Oxffff Base offset 0x10000 to Ox 1 ffff Identification Registers 0x000 to Ox00fc Capability Registers 0x0100 to 0x0124 Operational Registers 0x0140 to OxO1fc SRAM timing parameters Timing parameters for other external peripherals Interrupt latch status register NMI interrupt acknowledge register SW board reset register PIC32 USB
64. sion of MIPS Basic RTL BRTL in the FPGA Subject to licensing the user can obtain this RTL as example code to use There are third party RTL modules in the BRTL which MIPS is not allowed to distribute in RTL form although MIPS will provide details on how users can obtain their own licences The SEAD 3 board is the ideal solution for customers who are designing a System On a Chip SOC ASIC which includes a MIPS CPU core An SOC design will typically contain the CPU bus controllers and other IP The IP can be synthesized to the FPGA and verified together with the CPU core at a speed which is beyond what any emulator or simulator can provide The user may extend board functionality by designing a custom PCB that interfaces to SEAD 3 through a number of SEAD 3 Expansion Connectors The board also enables software engineers to begin code development and testing before the final ASIC is available So instead of having a sequential development of ASIC and software the process can be speeded up by performing the tasks in parallel Figure 1 1 below illustrates how an SOC ASIC with CPU and user IP can be mapped to the SEAD 3 board MIPS SEAD 3 Board User s Manual Revision 01 03 9 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction Figure 1 1 SOC ASIC to SEAD 3 Board Mapping SOC ASIC CoreBus SOC ASIC SEAD 3 Board MIPS Module CoreBus Anything Peripheral bus SEAD 3
65. st be termi nated by line feed LF or carriage return line feed CR LF The file contents is case insensitive The boot Flash device is organized in sectors of 128 Kbytes Erase and Set Lock Bit commands operate exactly one sector this being the sector currently addressed After the last block of 16 words in a sector are written into flash the address counter has advanced to the next sector This implies that a Set Address to the sector has to be executed before a Set Lock Bit command S can be issued The file to be loaded into the Flash via USB contains 3 types of elements Commands data and separators as described in Table 4 3 Table 4 3 Download File Contents Type Description Command A command is build from an opcode and in some cases and argument see next table Separators are used to separate commands and or data One or more of the following are valid separators space tab LF or CR LF Separator Data A 32 bit value like 11223344 Data must appear in blocks of 16 starting on a 16 word boundary The boot Flash is 8 bits wide and the 32 bits are stored in Big Endian format so the value 11223344 is stored with 11 at the lowest address and 44 at the highest address A number of opcodes are used to control code download and Flash memory handling as described in Table 4 4 32 MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved
66. tandby voltage 0 Unused clock from synthesizer 0 GL_A3_LV_CLKO Expansion connector clock GL_LV_CCLKO Clock source for the Module clock selector CLK_BO Unused clock from synthesizer 1 TP10 PIC_CLK_20MHZ PIC32 controller clock 11 Expansion connector clock CL IV Synthesizer 1 clock Unused clock USBPHY_CLK_24MHZ Hi Speed USB PHY clock ETH_CLK_25MHZ Ethernet controller clock TP17 USB_CLK_24MHZ EZUSB Controller clock TP18 GL LV CCLKI Clock source for the Module clock selector from synthesizer 1 based on Table 7 2 GL LV CLKO Clock source for the Module clock selector from synthesizer 0 based on Table 7 1 GL MOD LV CLK FPGA Module 3 clock TP26 VCC2V5 2V5 voltage supply MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 15 1 Test Points Continued TP30 VCCIV8 DDRII DRAM Supply TP31 VCCINT Core voltage for the FPGA TP34 VTTDDR DDRII DRAM termination supply TP35 GND GND TP36 VTTVREF DDRII DRAM volatge reference MIPS SEAD 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Test Points 76 Chapter 16 Building a User Board One of the advantages of SEADTM 3 15 that the user can extend functionality by connecting user designed board to the SEAD 3 Epansion Connectors Th
67. th Chip select hold after write strobe s deasser Hold time of address and unit select vector after chip select de assertion PI_D 31 0 N 3 0 Write data setup to write strobe deassertion 20 PI_D 31 0 PI N 3 0 Write data hold after write strobe deassertion 10 Signals PL_A 23 0 PI SEL 4 0 CS PI CS N PI BE N 3 0 PI BE N 3 0 PI BE N 3 0 PI CS N tw3 PI A 23 0 PI SEL 4 0 PI CS N 9 2 Peripheral Bus Resources The table below summaries the characteristics of the peripheral bus resources The user should obtain data sheets from the vendor for detailed information The SEL 4 0 column is the value used to access the unit on peripheral bus The Access column shows the allowed operations RW or RO Table 9 5 Peripheral Bus Resources Description The Flash blocks contains two chips and each device is 16 bits wide Each is con nected to one half of the 32 bit bus Only 32 bit accesses are allowed The address bits used are A 24 2 The size of the Flash block is 32 MBytes Ethernet Command Data interface Each of the two SRAM blocks contains two chips in parallel for a 32 bit data width Writes of 0 1 2 3 or 4 bytes are allowed The address bits used are A 23 2 There is a dual 16C2550 UART The uses address bits A 4 2 i e addresses are word aligned The UART uses D 7 0 for data One ch
68. the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party MIPS MIPS I MIPS II MIPS III MIPS IV MIPS V MIPSr3 MIPS32 MIPS64 microMIPS32 microMIPS64 MIPS 3D MIPS16 MIPS16e MIPS Based MIPSsim MIPSpro MIPS Technologies logo MIPS VERIFIED MIPS VERIFIED logo 4K 4Kc 4Km 4Kp 4KE 4KEc 4KEm 4KEp 4KS 4KSc 4KSd MIAK 5 5Kf 24K 24 24Kf 24 24KEc 24KEf 34K 34 34Kf 74K 74 74Kf 1004K 1004Kc 1004Kf R3000 R4000 R5000 ASMACRO Atlas At the core of the user experience BusBridge Bus Navigator CLAM CorExtend CoreFPGA CoreLV EC FPGA View FS2 2 FIRST SILICON SOLUTIONS logo FS2 NAVIGATOR HyperDebug HyperJTAG JALGO Logic Navigator Malta MDMX MED MGB microMIPS OCI PDtrace the Pipeline Pro Series SEAD SEAD 2 SmartMIPS SOC it System Navigator and YAMON are trademarks or registered trademarks of MIPS Technologies Inc in the United States and other countries All
69. ting 0x01 to DEVRST register and pic32 can be brought out of reset by writing 0 0 to the PI DEVRST register Table 3 11 Pl DEVRST register Function Initial Value N A MIPS SEAD 3 Board User s Manual Revision 01 03 0 assert PIC32 reset 1 deassert PIC32 reset Field name Reserved PIC32 RST Copyright 2009 2010 MIPS Technologies Inc All rights reserved Bits 31 1 28 Chapter 4 USB Download The USB Download feature of the SEAD 3 is used to program the boot Flash containing the boot software 6 MBytes and FPGA configuration There is sufficient storage for LX155 and two LX330 size FPGAs 26 MBytes This section describes the board hardware involved in USB download and the format used 4 1 USB Hardware The USB controller on the board is an EZ USB device from Cypress Semiconductor Firmware for the device is located in an on board serial EPROM The figure below illustrates the components on the board that are used in USB download MIPS SEAD 3 Board User s Manual Revision 01 03 29 Copyright 2009 2010 MIPS Technologies Inc All rights reserved USB Download Figure 4 1 USB Download Boot ASCII FPGA ins Peripheral Bus GRG CBT CBT CBT FPGA control 5 amp USB bus Controller FPGA JTAG Code I2C EPROM CPLD JTAG Connector USB Connector The boot Flash and t
70. tinued Position Description These push buttons provide a simple 5 button keypad North South East West and Center This allows user to add simple interactive controls SW6 SWS are also used for Serial port boot up selection When SW6 is held down during a reset YAMON will select LCV1 RS232 J7 as the default port When SW8 is held down during a reset YAMON will select USB to Serial J67 as the default port MIPS SEAD 3 Board User s Manual Revision 01 03 Type Push buttons Copyright 2009 2010 MIPS Technologies Inc All rights reserved Ref SW5 SW6 SW7 SWS SWII Switches 72 73 Chapter 14 LEDs Table 14 1 lists all the LEDs and their purpose Table 14 1 LEDs Description Indicates MicroSD card activity Ethernet Full Duplex DDRII Phy initialized DDRII PHY Error LED will be ON when the 5V power is within 5 of the nominal value LED will be ON when the 3V3 power is within 5 of the nominal voltage LED will be ON when the board is power up Turned on when the FPGA is successfully configured either from cable or boot Flash This LED is turned on when USB download is active This LED will be ON while the board is in the reset state LED will be ON when the standby power is available from the ATX power supply This will be the case when the power supply is connected to the main outlet P LED 0 P LED 1 P LED 2 P LED 3 P LED
71. tion 1 SRAM size 15 8MB switch in ON position Only available for Rev03 boards 0 Not present Interrupts are directly mapped 1 Present Interrupt Controller is GIC 0 DRAM mapped to address 0x0 SRAM MAP ZERO switch in OFF position 1 SRAM mapped to address 0x0 SRAM MAP ZERO switch in ON position Fields USB PRESENT DDR2 PRESENT SRAM SIZE GIC PRESENT ADDRESS 0X0 DEVICE Table 2 5 PI PIC32 USB STATUS Register Field Descriptions Address 0x1F00 0060 Read Write Bits Description Fields Name 0 21 4 Must be written as zero return zero on read RO 0 Not active 1 Active 0 Not active 1 Active 1 0 Not active 1 Active MIPS SEAD 3 Board User s Manual Revision 01 03 GPIOB_INT GPIOA_INT SPI INT 18 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 2 5 BRTL Register Definitions Table 2 5 PI PIC32 USB STATUS Register Field Descriptions Address 0x1F00 0060 Description IO RDY 0 0 Not ready RO Ready Fields Read Name Bits Description Write SOFT ENDIAN EIC 31 0 Disable R W CONTROL 1 Enable SEAD3_CFG_PRESENT 30 0 Not present RO 1 Present 0 29 3 Must be written as zero returns zero on read RO EIC_MODE 2 0 Disable R W 1 Enable DONE 1 Set on write to bit 0 RO Cleared on write to PI SWRESET register ENDIANESS 0 0 Little Endian R W
72. trolled by a clock selection buffer which selects from an output of Sysnthesiser 0 or 1 using SW1 8 The MOD output can also be disabled using SW1 7 The three synthesizers have daisy chained clock source derived initially from a 25MHz oscillator which is fed into Synthesizer 1 and then buffered and fed to Synthesizer2 and again to Synthesizer 3 All clocks generated are 3 3V except the differential clocks which are 2 5V MIPS SEAD 3 Board User s Manual Revision 01 03 45 Copyright 2009 2010 MIPS Technologies Inc All rights reserved CI0CMI Table 7 1 GL MOD LV Selection Table Description Synthesizer 0 range Synthesizer 1 range Output disabled SW1 7 off off on SW1 8 on off Table 7 2 Synthesizer 0 Switch Settings SW1 4 Power 200 00 MHz 187 50 MHz 175 00 MHz 166 66 133 33 MHz 125 00 MHZ 100 00 MHz SW1 5 on on on on off on off on off SW1 6 Table 7 3 Synthesizer 1 Switch Settings SW1 1 Power 133 33 MHz 125 00 MHz 100 00 MHz 83 33 MHz 66 66 MHz 50 00 MHZ 40 00 MHz MIPS SEAD 3 Board Users Manual Revision 01 03 SW1 2 on on on on off on off on off SW1 3 46 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 8 DRAM Interface The DRAM socket on the board accepts a standard DDR II 533 1 8
73. uilding a User Board Table 16 2 A4 Connector Pins Continued Signal Name Pin Polarity Signal Name 4 9 89 N A9 AM6 A4_A 9 A4_B 10 10 AN7 A4 A 10 4 B 11 11 7 4_ 11 A4_B 12 AK8 812 P 12 AMS A4 A 12 4 B 13 A13 ANS A4 A 13 4 B 14 AN30 814 P 14 4 14 4 15 AL31 815 N 15 ALIO A4 A 15 A4 B 16 16 10 A4_A 16 4 807 AL24 B17 N A4_A 17 A4_B 18 AL25 818 P 18 AP15 4 A 18 4 19 19 AN14 4_ 19 A4_B 20 21 20 4_ 20 4 21 20 821 N 21 16 4_ 21 A4_B 22 A22 15 A4_A 22 A4_B 24 23 24 P A24 11 A4_A 24 A4_B 25 AM22 B25 N A25 A4_A 25 A4_B 27 18 827 N A27 17 4 27 4 28 AN18 B28 P A28 AP16 A4_A 28 A4_B 29 AP21 B29 N A29 17 A4_A 29 A4_B 30 AP22 B30 P A30 17 A4 A 30 A4 31 AP19 B31 N 31 AMII A4_A 31 4 32 19 B32 P A32 AN10 A4_A 32 A4_B 33 AL26 B33 N A33 A4_A 33 A4_B 34 AM26 B34 P A34 14 4_ 34 4 865 AL30 B35 N 35 4 A 35 4 36 AL29 B36 P A36 AH24 A4_A 36 A4_B 37 AP24 B37 N A37 15 4_ 37 A4_B 38 24 838 P A38 4 A 38 A4 B 39 AP25 B39 N A39 A4_A 39 A4_B 40 AP26 B40 P A40 1 4_ 40 4_ 41 06 841 N 41 ADI 4 A 41 A4 B 42 AP7 842 P A42 AJ22 A4_A 42 A4_B 43 ALIA B43 N A43 AK21 A4 A 43 Copyright 2009 2010 MIPS Technologies Inc All rights reserved M
74. ushed 12V supply to board Unused on board but available on user connector PS_ONN The PSU will be ON when this signal is low Table 11 3 J13 Aux Power Outlet Table 11 4 J8 PIC32 Debug Header Name Description Notes VCC3V3 3 3V GND GND ADC CHO PIC32 pin PDG1 NOTE The PDC1 PDG1 are dual use pins on the PIC32 15 pinC10 and ADC CHI J5 pin C11 must not be con ADC CHI PIC32 nected at same time ICS probe No Connect Table 11 5 PIC32 10 COnnector J5 VCC3V3 GND GND SP_CLK GND SP_MISO A4 GPIO3 B4 GND C4 SP_MOSI AS GPIO4 85 GND 5 5 50 MIPS SEADTM 3 Board User s Manual Revision 01 03 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table 11 5 21032 IO COnnector 45 Continued 2 5 Function SP_CS1 2 C7 SP_CS2 C8 SP_CS3 C10 ADC CHO Wl 1 6 eo 62 C Z Z Z C 2 ADC_CH3 06 ADC CH6 18 GND 2 Z o 2 w aja 9 5 VCC3V3 Function GPIOS GPIO6 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 15 5CL SDA Table 11 6 93 94 Serial Port Pinouts Direction Table 11 7 J17 FPG

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