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DSC56800EX Quick Start User Guide

1. Description ag 5 Lre EFPWMS SET CAPTURE B 1 EFPWM CAPTURE 1 XXX Set input capture B 1 edge sensitivity DIS 58 ABLE FALLING_EDGE RISI NG_EDGE ANY_EDGE EFPWMS SET CAPTURE B FIFO UWord16 Value 0 to 3 in 824 5 value O to 1 _WATERMARK EFPWMS SET CAPTURE B INP EFPWM RAW INPUT EFP Set input capture B source XN UT WM EDGE COUNTER EFPWMS SET CAPTURE B MO EFPWM FREE RUNNING Set capture mode PA DE EFPWM ONE SHOT EFPWMS SET CAPTURE X 0 EFPWM CAPTURE 0 XXX Set input capture X 0 edge sensitivity DIS zw ABLE FALLING EDGE RISI NG EDGE ANY EDGE EFPWMS SET CAPTURE X 1 EFPWM CAPTURE 1 XXX Set input capture X 1 edge sensitivity DIS XE ABLE FALLING EDGE RISI NG EDGE ANY EDGE EFPWMS SET CAPTURE X FIFO UWord16 Value 0 to 3 824 5 value 0 to 1 zw WATERMARK EFPWMS SET CAPTURE X INP EFPWM RAW INPUT EFP Set input capture X source e UT WM EDGE COUNTER EFPWMS SET CAPTURE X MO Set capture mode DE EFPWM FREE RUNNING viv EFPWM_ONE_SHOT EFPWMS_SET_CENTER_ALIGN_ UWord16 Range 0 to 216 2 writes modulo MODULO_INIT_REG value in to register and Init regis 20158 to prepare generating Center Align output signal EFPWMS SET CLOCK SOURCE EFPWM XXX CLOCK Set reload PWM clock source IPBUS EXT SUBO EFPWMS SET COMPARE A UWord16 Set Edge Compare A value value 0 to 255 EFPWMS SET COMPARE UWord16 Edge Compar
2. Description ag WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 2 G 25 25 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register 2 G 26 26 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 2 G 27 27 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 2 28 28 WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register _29 29 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register a G3 3 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register G4 4 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register G5 5 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register s G 6 6 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register Pp G7 7 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register viv G_8 8 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register 212 G 9 9 B INIT NULL Initialize B periheral registers using the appconfig h INIT values XBAR B READ CROSSBAR REG NULL Read and return the value of the sly 0 Crossbar B Select Register 0 XBAR_B_READ_CROSSBAR_REG NULL Read and return the value of the PP _1 Crossbar Select Register 1 XBAR B READ CROSSBAR REG NULL Read and return the value of the PET _2 Crossbar Select Reg
3. Description ag iO Lre EFPWMS_EDGE_ALIGN_UPDATE Word16 in Signed Fractional Range 0 to 1 Modulo register can be _CHANNEL_45_FRAC representation maximally 1024 Set Value4 BA Fractional4 Value5 and Fractional5 registers EFPWMS_EDGE_ALIGN_WRITE UWord16 Range 0 to 32767 Set Value2 and CHANNEL 23 Value3 registers to generate edge viv align output signal EFPWMS_EDGE_ALIGN_WRITE UWord16 Range 0 to 32767 Set Value4 and CHANNEL_45 Value5 registers to generate edge viv align output signal EFPWMS FULL CYCLE RELOAD EFPWM_ENABLE EFPWM__ Enable disable full cycle reload DISABLE EFPWMS HALF CYCLE RELOAD EFPWM_ENABLE EFPWM__ Enable disable middle cycle reload 2412 DISABLE EFPWMS_INT_DISABLE Enable selected interrupts note All RELOAD_ERROR RELOAD parameters are not supported in all COMPARE VALO COMPAR PWM submodules see documenta VAL1 COMPARE VAL2 C tion OMPARE_VAL3 COMPARE VEN _ VALA COMPARE VAL5 CA PTURE A1 CAPTURE AO0 C APTURE B1 CAPTURE B0 CAPTURE X1 CAPTURE X 0 EFPWMS INT ENABLE EFPWM xxx Enable selected interrupts note All RELOAD_ERROR RELOAD parameters are not supported in all COMPARE VALO COMPAR PWM submodules see documenta VAL1 COMPARE VAL2 C tion OMPARE_VAL3 COMPARE _VAL4 COMPARE_VAL5 CA PTURE_A1 CAPTURE_AO C APTURE B1 CAPTURE B0 CAPTURE X1 CAPTURE X 0 EFPWMS OUTPUT TRIGGER DI EFPWM TRIGO VALx
4. 8 1 Chapter 9 Revision history DSC56800EX Quick Start User s Guide Rev 2 04 2015 vi Freescale Semiconductor Inc Table Number 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 2 31 2 32 2 33 2 34 2 35 5 1 5 2 5 3 5 4 5 5 5 6 Tables Page Title Number archGetSetSaturationMode 2 10 2 10 EPPING isis ce 2 11 periphMemW rite armari RE 2 11 2 12 periphMemlnvBitSet arguments 5 2 12 periphBitClear arguments 2 13 2 14 2 14 BerbhBr carane AEE 2 15 UNITS 2 16 RH Den br GR D 2 17 10015121 115 2 17 2 18 See IPR TRS argumens serran a NOM 2 19 per
5. NENT x x Description m 5 i SYS SET TMRAO INPUT one of SYS TMRAO xxx TMRBO input selection 2 GPIO_C3 XB_OUT49 SYS SET TMRAO INPUT one of SYS TMRAO xxx TMRAO input selection 2 GPIOC3 XB_OUT34 SYS_SET_TMRA1_INPUT one of SYS TMRA1 xxx TMRB input selection 2 GPIO_C4 XB_OUT50 SYS_SET_TMRA1_INPUT one of SYS TMRA1 xxx TMRAt input selection GPIOC4 XB_OUT35 SYS_SET_TMRA2_INPUT one of SYS_TMRA2_xxx TMRB2 input selection GPIO C6 G8 TMRA2 XB Y OUT51 SYS_SET_TMRA2_INPUT one of SYS_TMRA2_xxx TMRA2 input selection 2 GPIOC6 XB_OUT36 SYS_SET_TMRA3_INPUT of SYS_TMRA3_ xxx TMRB3 input selection 2 GPIO_C13_G9 XB_OUT52 SYS_SET_TMRA3_ INPUT one of SYS TMRA3 xxx TMRAS input selection 2 GPIOC13 XB_OUT37 SYS SET TMRBO INPUT one of SYS TMRBO xxx TMRBO input selection GPIO C2 XB OUT34 SYS SET 1 INPUT one of SYS TMRB1 xxx 1 input selection GPIO_F8 XB_OUT35 SYS_SET_TMRB2_INPUT one of SYS_TMRB2_xxx 2 input selection GPIO_F6_FO_G6 XB_OUT3 Y 6 SYS SET TMRB3 INPUT one of SYS xxx TMRBS input selection 2 GPIO_F7_G11 XB_OUT37 SYS SET VERY LOW POWER SYS ENABLE SYS DISABL Causes the device to enter exit VLP 2 32 MODE E MODE SYS_SOFTWARE_RESET NULL Issue software reset viv SYS_STOP SYS_ENABLE _PERMANEN Enable disable the STOP instruction T SYS_DISABLE _PERMA DSC56800EX Quick St
6. Description e SPI GET ERROR NULL Test is any error is reported in the the Status and Control Register test viv OVRF and MODF bits SPI GET MODE FAULT NULL Test mode fault MODF bit viv SPI GET FULL NULL Test receiver full SPRF bit viv SPI GET RX OVERFLOW NULL Test overflow bit viv SPI_GET_STATUS NULL Get the status of read write functions A returns UWord16 SPI GET TX EMPTY NULL Test the transmitter empty SPTE bit viv SPI_INIT NULL Initialization of the SPI periheral regis ters using appconfig h INIT values SPI INT DISABLE SPI TX EMPTY Disable the selected SPI interrupts SPI RX FULL viv SPI ERROR SPI INT ENABLE SPI TX EMPTY Enable the selected SPI interrupts SPI RX FULL viv SPI ERROR SPI MULT BAUD DIV SPI MULT DIV 1x Set multiplication factor of the SPI MULT DIV 2x baudrate divisor value SPI OVERRIDE SS INPUT SPI ENABLE Override the internal SS input with 21 SPI DISABLE value of SPMSTR bit SPI QUEUED MODE SPI ENABLE Enable SPI FIFOs VS SPI DISABLE SPI READ CANCEL NULL Cancel non blocking read operation viv SPI READ CONTROL REG NULL Read and return the value of SPI Con VN trol Register SPI READ DATA NULL Read SPI Data Receive Register It ST ed contains previously received data SPI RX FULL INT SPI ENABLE Interrupt enable or disable for SPRIE 21 SPI DISABLE SPI SET BAUD DIV SPI DIVx 2 4 8 16 32 64 128 Set SPI baud rate clock divisor
7. Description ag 5 ive ADC WRITE ZERO CROSS ADC_Sx_ZC_xxx 0 7 Configure zero crossing detection RL xxx DIS logic for selected samples ABLE POSITIVE_NEGATIVE viv NEGATIVE_POSITIVE ANY _CROSS ADC_WRITE_ZERO_CROSS_CNT ADC_Sx_ZC1_xxx x 0 7 Configure zero crossing detection RL1 xxx DIS logic for selected samples ABLE POSITIVE_NEGATIVE viv NEGATIVE_POSITIVE ANY _CROSS ADC_WRITE_ZERO_CROSS_CNT ADC_Sx_ZC2_xxx x 8 15 Configure zero crossing detection RL2 xxx DIS logic for selected samples ABLE POSITIVE NEGATIVE viv NEGATIVE_POSITIVE ANY _CROSS ADC_ZERO_CROSS_CHO ADC_ZC_ xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 0 viv BOTH ADC_ZERO_CROSS_CH1 ADC_ZC_ xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 1 viv BOTH ADC_ZERO_CROSS_CH10 ADC 20 xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 10 4 ADC_ZERO_CROSS_CH11 ADC_ZC_ xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 11 ADC_ZERO_CROSS_CH12 ADC 20 xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 12 ADC ZERO CROSS CH13 7 xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 13 ADC_ZERO_CROSS_CH14 ADC_ZC_xxx xxx DIS C
8. trol register CTRL as UWord16 Description ag 55 HOME TRIGGERED INIT ENC ENABLE ENC DISAB Enable disable the initialization of the LE Upper and Lower Position Counter 2 Registers UPOS LPOS with the HOME signal ENC_INDEX_EDGE ENC_NEGATIVE ENC_POSI Set the rising or falling edge of the TIVE INDEX pulse to trigger the initialization of the Upper and Lower Position Counter Registers UPOS LPOS ENC_INDEX_TRIGGERED_INIT ENC_ENABLE ENC_DISAB Enable disable the initialization of the LE Upper and the Lower Position Counter 2 Registers UPOS LPOS using the INDEX pulse ENC_INIT NULL Initialize the ENC peripheral registers 2 using the appconfig h _INIT values ENC_INT_DISABLE combination of ENC_xxx Disable the selected interrupt xxx HOME INDEX WDTIM Y EOUT COMPARE ENC INT ENABLE combination of ENC xxx Enable the selected interrupt xxx HOME INDEX WDTIM Y EOUT COMPARE ENC INT REQUEST CLEAR combination of xxx Clear the selected interrupt flag Xxx HOME INDEX WDTIM Y EOUT COMPARE ENC INT ROLL DISABLE combination of Disable the selected interrupt ROLL xxx Y xxx OVER UNDER ENC INT ROLL ENABLE combination of Enable the selected interrupt ENC ROLL xxx Y xxx OVER UNDER ENC INT ROLL REQUEST CLEA combination of Clear the selected interrupt request R ENC ROLL xxx flag The roll over interrupt request is xxx OVER UNDER set wh
9. Description ag 55 ive IIC_SET_HOLD_OFF_TO_STOP IIC_ENABLE IIC_DISABLE Enable disable waiting to finish cur rently transferred data then enter to viv the stop mode IIC_SET_PRESCALER UWord16 Write directly into the IIC Bus Fre quency Divider Register register which controls several prescalers and v v delays applied to the IIC bit sampling and bit transmission process SET RANGE MODE ENABLE IIC DISABLE Enable disable the slave address matching between the values of the 1 RA registers IIC_SET_RANGE_SLAVE_ADDRE UWord16 value 0 127 Set the slave address range to by 55 used by the module nonzero viv write enables this register IIC_SET_SECOND_IIC_ADDRESS IIC_ENABLE IIC_DISABLE Enable disable the SMBus device TAN default address SET SLAVE BAUD RATE CT IIC MASTER INDEPENDE Enable disable the slave baud rate 0 RL NT IIC MASTER FOLLOW slave follows master baud rate SET SMBUS ADDRESS UWord16 value 0 127 Write the value into the Secondary Bus Address Register IIC_SET_SMBUS_RESPONSE_AD_ IIC_ENABLE IIC_DISABLE Enable disable the SMBUS alert s DRESS response address SET STOP START INT ENABLE IIC DISABLE Enable disable the interrupt for the IIC PN bus stop or the start detection SET TIME OUT CLOCK DIV64 IIC DIV1 Select the clock sources of the timeout 2112 counter IIC_SET_WAKEUP_IN_ STOP IIC_ENABLE IIC_DISABLE Enable disa
10. Y Y The Table 5 11 shows all commands dedicated for CRC Driver Table 5 11 CRC Driver Commands Cmd pParam Description 56F82xxx 56F84xxx CRC READ 16BIT CHECKSUM NULL Read and return the value low Word of the CRC Data register lt CRC READ 32BIT CHECKSUM NULL Read and return the value of the whole CRC Data register CRC READ CRC HIGH REG NULL Read and return the value of CRC High Byte register This register repre sents high byte of the CRC Generator result CRC READ CRC LOW REG NULL Read and return the value of CRC Low byte register This register repre sents low byte of the CRC Generator result CRC READ CRC REG NULL Read and return value of CRC Data register CRC READ RESULT NULL Read and return the value of CRC result bytes CRC READ CRC TRANSPOSE CRC READ CTRL REG NULL NULL Read and return value of the CRC Transpose register This register is using to convert data from MSb to LSb Read and return value of CRC Control register DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 37 Table 5 11 CRC Driver Commands module expects writing the low part of the initialization byte to the CRC Low byte register
11. Table 5 64 shows all commands dedicated for XBAR Driver Table 5 64 XBAR Driver Commands gt lt X gt lt X Cmd pParam Description xb LL LL iO NULL Initialize XBAR_A periheral registers v a using the appconfig h INIT values XBAR A READ CROSSBAR CTR NULL Read and return the value of the sly LO Crossbar A Control Register 0 XBAR_A_READ_CROSSBAR_CTR NULL Read and return the value of the Viv L 1 Crossbar A Control Register 1 XBAR A READ CROSSBAR REG NULL Read and return the value of the e x _0 Crossbar A Select Register 0 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the _1 Crossbar Select Register 1 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 210 Crossbar Select Register 10 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 14 Crossbar Select Register 11 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 412 Crossbar Select Register 12 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the sy _13 Crossbar Select Register 13 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 165 Table 5 64 Driver Commands Description ag ive XBAR_A_READ_CROSSBAR_REG
12. Description m LL LL 1 Lre QT_WRITE_COMPARE_REG2 UWord16 Write the parameter value into the timer counter Compare register 2 QT_WRITE_CONTROL_REG UWord16 Write the parameter value into the timer counter Control register QT_WRITE_COUNTER_REG UWord16 Write the parameter value into the 214 timer counter Counter register QT_WRITE_FILT_REG UWord16 Write the Filter register viv QT_WRITE_LOAD_REG UWord16 Write the parameter value into the timer counter Load register QT WRITE PRELOAD COMPARE UWord16 Write the parameter value into the REGI timer counter Comparator Load regis v v ter 1 QT WRITE PRELOAD COMPARE UWord16 Write the parameter value into the REG2 timer counter Comparator Load regis v v ter 2 QT WRITE STATUS CONTROL UWord16 Write the parameter value into the REG timer counter Status and Control reg viv ister 0 55 DISABLE combination of Mass disable selected timer channels QT_CHO QT_CH1 QT_CH2 viv QT_CH3 QTO MASS ENABLE combination of Mass enable selected timer channels QT CHO QT CH1 QT CH2 QT CH3 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 141 5 1 26 Queued Serial Communication Interface SCI Driver The SCI allows asynchronous serial communications with peripheral devices The SCI provides the following feautures Full duplex or single wire operation Standard mark space non return to zero NRZ format 16
13. ds dpa Mata ation 5 23 ldenuters tor AOI RR 5 30 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor vii Tables Table Page Number Title Number 5 7 AOI Driver M MM ME IM EI MP MEME M MM 5 30 5 8 ld ntifiers COP DOVBE e eR EAE EDO DOO A FAR DOE 5 35 5 9 COF Driver Command RH 5 35 5 10 Identifiers for CRC a d A dc onn d dada clie 5 37 5 11 CRG Driver Commana 5 37 5 12 Identifiers for DAC 5 40 5 13 DAC Driver COmmalitlb usa ace DR RUNE POR KUNA ER Md 5 40 5 14 Reser ets for DMA DEBE o ns E PR MUR MPH MERE OPE MD M ME 5 43 5 15 DMA Driver CommandS 5 43 5 16 KD I Hip KE 5 44 5 17 DAC x Driver COmMandS 5 44 5 18 Identifiers for EFPWM DIBVBE 5 48 5 19 EFPWM Driver Comma sisincscsrissndecdensiantaannddcenasaaaaaardiaseabarakoneatanetaainabsediondatanaeane 5 48 5 20 Identifiers tor ENG 5 68 5 21 ENG Driver Command E O TE 5 68 5 22 Identifiers for EWM
14. DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 28 Freescale Semiconductor Inc Table 5 5 ADC16 Driver Command Cmd pParam Description 56F82xxx lt 56F84xxx ADC16 WRITE SC3 REG UWord16 Write the parameter value to the Sta tus and Control register 3 Note an inappropriate write to the register can clear Write 1 to Clear CALF flag DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 29 5 1 3 Crossbar AND OR INVERT Driver The AND OR INVERT module known simply as the AOI module supports the generation of a configurable number of EVENT signals Each output EVENTn is a configurable and or invert function of four associated AOI inputs An Bn Cn and Dn The Table 5 6 shows module identifiers for AOI Driver The Table 5 7 shows all commands dedicated for AOI Driver Table 5 6 Identifiers for Driver Module identifier 56F82xxx 56F84xxx v Table 5 7 AOI Driver Commands gt lt Description LL AOI INIT NULL Initialize peripheral registers using the appconfig h _INIT values AOI READ BFCRTO010 NULL Return UWord16 value of AOI Bool ean Function Term register AOI READ BFCRTO 11 NULL Return UWord16 value of AOI Bool UT ean Fu
15. 12 ADC_WRITE_HIGH_LIMIT13 UWord16 Write High Limit Register for sample 13 ADC_WRITE_HIGH_LIMIT14 UWord16 Write High Limit Register for sample sy 14 ADC_WRITE_HIGH_LIMIT15 UWord16 Write High Limit Register for sample 15 ADC_WRITE_HIGH_LIMIT16 UWord16 Write High Limit Register for sample 2 16 ADC_WRITE_HIGH_LIMIT17 UWord16 Write High Limit Register for sample 2 17 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 17 Table 5 3 ADC Driver Commands x x X x Cmd pParam Description ag ADC_WRITE_HIGH_LIMIT18 UWord16 Write High Limit Register for sample E 18 ADC WRITE HIGH LIMIT19 UWord16 Write High Limit Register for sample 2 19 ADC WRITE HIGH LIMIT2 UWord16 Write High Limit Register for sample 2 v ADC WRITE HIGH LIMIT3 UWord16 Write High Limit Register for sample 3 v v ADC WRITE HIGH LIMITA4 UWord16 Write High Limit Register for sample 4 v v ADC_WRITE_HIGH_LIMIT5 UWord16 Write High Limit Register for sample 5 v WRITE HIGH LIMIT6 UWord16 Write High Limit Register for sample 6 v v ADC WRITE HIGH LIMIT7 UWord16 Write High Limit Register for sample 7 y v ADC WRITE HIGH LIMIT8 UWord16 Write High Limit Register for sample 8 v ADC WRITE HIGH LIMIT9 UWord16 Write High Limit Register for sample 9 v ADC WRITE LOW LIMITO UWord16 Write Low Limit Regis
16. A INPUT Set XBAR A OUTO input v XBAR A SET OUT GPIO C8 F2 XBAR A INPUT Set XBAR OUT6 input v XBAR SET OUT GPIO C9 F4 XBAR A INPUT xxx Set A input A XBAR SET OUT GPIO F 10 XBAR A INPUT xxx Set A input Y XBAR A SET OUT GPIO F 2 XBAR A INPUT xxx Set XBAR OUT6 input v XBAR A SET OUT GPIO F 3 XBAR A INPUT xxx Set XBAR A OUT7 input v XBAR A SET OUT GPIO F 3 XBAR A INPUT xxx Set XBAR A OUT7 input XBAR A SET OUT GPIO F 4 XBAR A INPUT xxx Set XBAR A OUTS8 input A SET OUT GPIO F 5 XBAR A INPUT xxx Set XBAR A OUTO input 2 SET_OUT_GPIO_F_8 XBAR_A_INPUT_xxx Set XBAR_A_OUT10 input Y XBAR SET OUT GPIO F 9 XBAR A INPUT xxx Set XBAR A OUT 11 input Y XBAR SET OUT GPIO F10 G XBAR A INPUT xxx Set A input 8 XBAR A SET OUT GPIO F9 G9 A Set XBAR A OUT11 input v XBAR A SET OUT GPIO G 8 XBAR A INPUT xxx Set OUT10 input XBAR A SET GPIO G 9 XBAR A INPUT xxx Set XBAR A OUT11 input SET OUT PDBO FAULT XBAR A INPUT xxx Set A OUT3969 input SET OUT PDBO FAULT XBAR A INPUT xxx Set A OUTA0O input SET OUT PDBO TRIGO XBAR A INPUT xxx Set 8 input A XBAR SET OUT PDB1 FAULT XBAR A INPUT xxx Set A OUT42 input 2 SET_OUT_PDB1_FAULT XBAR_A_INPUT_xxx Set XBAR_A_OUT43 input 2 DSC56800EX Quick Start User s Guide Rev 2
17. Description m 5 i i SYS SET C7PAD FUNCTION one of SYS C7PAD xxx Package pin function selection 2 5580 B TXDO SYS SET C7PAD FUNCTION one of SYS C7PAD xxx Package pin function selection 2 5580 B TXDO XB 1 8 SYS SET C8PAD FUNCTION one of SYS C8PAD xxx Package pin function selection MISOO RXDO XB IN9 SYS SET C8PAD FUNCTION one of SYS C8PAD xxx Package pin function selection XB OUT6 RXDO MISOO0 XB Y 9 SYS SET C9PAD FUNCTION one of SYS C9PAD xxx Package pin function selection SCLKO XB 4 8 Y XDO SYS SET C9PAD FUNCTION one of SYS C9PAD xxx Package pin function selection 2 XB_IN4 SCLKO SYS SET D5PAD FUNCTION one of SYS D5PAD xxx Package pin function selection 2 MASK XB IN5 XB OUT9 SYS SET D6PAD FUNCTION one of SYS D6PAD xxx Package pin function selection 2 TXD2 XB_IN4 XB_OUTS8 SYS SET D7PAD FUNCTION one of SYS D7PAD xxx Package pin function selection XB OUT11 XB IN 7 XB MI Y SO1 SYS SET E4PAD FUNCTION one of SYS E4PAD xxx Package pin function selection 2 PWMB2 XB 1 2 SYS SET E4PAD FUNCTION one of SYS E4PAD xxx Package pin function selection 2 PWMB2B XB 1 2 SYS_SET_E5PAD FUNCTION one of SYS_E5PAD_ xxx Package pin function selection 2 PWMA2 XB_IN3 SYS SET E5PAD FUNCTION of SYS E5PAD xxx Package pin function selection 2 PWMA2A XB IN3 SYS SET E6PAD FUNCTION one of SYS E6PAD xxx Package pin function selection 2 PWMB3 XB_IN4 SYS SET E6PAD FUNCTION one of SYS
18. Structure type information will be available in the FreeMASTER application OUTER STRUCT sol so2 INNER STRUCT sil si2 With TSA enabled the user describes the global and static variables using so called TSA tables There can be any number of tables defined in the project files Each table does have the identifier which should be unique across the project Note that you can declare variables as Read Only or Read Write The FreeMASTER driver denies any write access to the Read Only variables when TSA SAFETY is enabled FMSTR TSA TABLE BEGIN first table FMSTR TSA RO VAR var8 FMSTR TSA UINTS8 FMSTR TSA RO VAR varlo FMSTR TSA UINT16 FMSTR TSA RO VAR var32 FMSTR TSA UINT32 FMSTR TSA RW VAR varl6inc FMSTR TSA UINT16 FMSTR TSA RW VAR var32inc FMSTR TSA UINT32 FMSTR TSA RW VAR sol FMSTR TSA USERTYPE OUTER_STRUCT FMSTR TSA RW VAR sil FMSTR TSA USERTYPE INNER STRUCT FMSTR TSA STRUCT OUTER STRUCT FMSTR TSA MEMBER OUTER STRUCT FMSTR TSA UINT16 FMSTR TSA MEMBER OUTER STRUCT FMSTR TSA UINT32 FMSTR TSA MEMBER OUTER STRUCT inA FMST
19. 10 Submodule 2 Disable PWM Pins by Fault Submodule 3 Disable PWM Pins by Fault PWM FaultCh1 Common amp Fault Settings 0 1 29 8 NS qm 395 A 0 Pulse Width Modulator 0 State auk State A 1 Pulse Width Modulator 1 PwMA v M 50 2 Pulse Width Modulator 2 1550 PwMB 15950 PWM 3 Pulse Width Modulator 3 PwMx iw iw iv PwMX iv M iv 12 bit Cyclic Analog to Digital Converter Logic 0 mI Logie m DAC Digital to Analog Converter DAC Digital to Analog Converter DAC B Digital to Analog Converter HSCMP High Speed Comparator x Module Warming text occs Two module pins out of two are not available on any device pin See GPIO_C i sys The module signal CLKO_1 is not available on any device pin See GPIO_F Warning List m Show wamings even for non included modules NUM Figure 7 2 GCT Main Window 7 2 1 1 Peripheral Modules Tree This part of the main application window contains a tree like list of on chip peripherals There is a check box control at each item which can be used to enable or disable an appconfig h output for a given module When the box is unchecked no module s register values are written to the output file The GCT warns the user when there are changes made
20. Description ag 55 10O ive CRC_READ_GPOLY_REG NULL Read and return value of CRC Polyno 2 register CRC_SET_COMPLEMENT_READ CRC ENABLE CRC DISAB Enable disable on the fly comple OF DATA REG LE menting the read data Some CRC protocols require the final checksum Y to be XORed with OXFFFFFFFF or OxFFFF CRC SET PROTOCOL WIDTH CRC 16 BIT CRC 32 BIT Set the width of CRC protocol A CRC SET TRANSPOSE TYPE F xxx Set the transpose configuration of the OR READ TRANSPOSITION value read from the CRC Data regis BITS TRANSPOSED BITS ter Y AND BYTES TRANSPOSE D BYTES TRANSPOSED CRC SET TRANSPOSE TYPE F xxx Set the transpose configuration of the OR WRITES TRANSPOSITION data written into the CRC data regis BITS TRANSPOSED BITS ter Y AND BYTES TRANSPOSE D BYTES TRANSPOSED CRC SET WRITE AS SEED CRC ENABLE CRC DISAB When enabled any value written to LE the CRC data register is considered to be a seed value When deasserted a Y value written is taken as data for CRC computation CRC WRITE 16BIT CRC VALUE UWord32 value 0 65535 Write seed or data value used for CRC checksum generation CRC_WRITE_32BIT_CRC_VALUE UWord32 value 0 65535 Write seed or data value used for CRC checksum generation WRITE 8BIT VALUE UWord32 value 0 255 Write seed or data value used for CRC checksum generation CRC_WRITE_CRC_DATA UWord16 value 0 255 Write the parameter value into the CRC
21. Hold off entry to stop mode No Rx Idle Interrupt enabled Disable 227 define SCI 1 SCIBR INIT 0 0 2 0 define 1 5 INIT 0x000CU define 5 1 5 2 0 00000 define SCI 1 RX BUFFER OKLIMIT 0 000 define SCI 1 RX BUFFER LOWLIMIT 0x000AU define SCI 1 SCICR3 INIT 0x0000U FMSTR Configuration mA define FMSTR COMM INTERFAC define FMSTR LONG INTR define FMSTR SHORT INTR define FMSTR POLL DRIVEN define FMSTR USE SCOPE define FMSTR USE RECORDER DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 31 Freescale Semiconductor Inc 6 6 3 Code Listing freemaster demo2 The second FreeMASTER sample application demonstrates a usage of the TSA feature and both the callback and polled handling of the FreeMASTER Application Command E FK KK KKK Kk I KARR KK Ck I AAA kk ko A K ke kc koe ke ke k k ke k k k k Freescale Semiconductor Inc c Copyright 2013 Freescale Semiconductor Inc ALL RIGHTS RESERVED CkCkCk ck k ck Ck ck k ck k ck ck ck kk ck ck ck ck ck ck ck k ck ck ck kck ck ck k ck k ck kck kck ck ck ck ck ck ck ck ck ck kck k ck k ck k ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk kk k FILE NAME main c FreeMASTER software driver See also the freemaster demo application which demonstrates the key FreeMASTER features only without TSA security and app cmd callbacks
22. 1256 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 149 Table 5 60 SPI Driver Commands Description e 518 Lre SPI_SET_CLOCK_PHASE SPI_SCLK_EDGE Determine the condition which starts SPI_SS_EDGE data shift out of SLAVE device Trans mission is started by first SCLK edge viv or falling edge on SS pin which edge starts slave transmission SPI SET CLOCK POLARITY SPI RISING EDGE Set SPI clock edge which shifts out SPI FALLING EDGE data either falling edge or rising edge SPI SET MODE SPI MASTER SPI SLAVE Set SPI to MASTER or SLAVE mode v v SPI SET MODE FAULT SPI ENABLE Configure SPI device to use mode SPI DISABLE fault detection logic or to disable mode v v fault checking ena dis mode fault SPI SET ORDER SPI LSB FIRST Select SPI data shift bit ordering SPI MSB FIRST MSB bit first or LSB bit SPI SET RXFULL CONDITION SPI RXFULL WHEN xxxor Set how many words plus 1 in RX 2 value 0 3 FIFO causes the RXFULL condition SPI SET SS MODE one of SPI SS xxx the two Set the SS signal mode during SPI SS AUTO xxx may be SPI Master operation viv combined SPI SET SS OUTPUT boolean Set the SS pin value in 22152 SPI SS MANUAL OUT mode SPI SET 55 WIRED OR MODE Set the SS pin mode SPI OPEN DRAIN SPI NO viv RMAL SPI SET TX DATA SIZE data si
23. 2 5 Macros for peripheral memory 2 11 periphMemRead memory 2 11 periphMemWrite memory 4 48 2 11 periphBitSet set selected Jr 2 12 periphMemlnvBitSet invert memory content and set selected bits 2 12 pariphBitClear clear selected lt 2 13 periphBitGrpSR set bit group to given 2 14 periphBitGrpSRVar set bit group to given 2 14 periphBitGrpRS set bit group to given 2 15 periphBitGrpRSVar set bit group to given value 2 16 periphBitGrpRS32 set bit group to given 2 16 periphBitGrpZS set bit group to given 2 17 periphBitGrpZSVar set bit group to given 0002 02 2 18 periphBitGrpSet set bit group to given value 2 19 periphBitGrpSetVar set bit group to given 2 19 peri
24. Archive File 123 Existing Projects into Workspace File System ES Preferences gt C C 2 Next gt Figure 4 1 Import Dialog Box DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 1 Freescale Semiconductor Inc 3 Select root directory of the project stationary 25 56800 Quick Start r2 6NtationaryNDSC568500EX Quick Start r2 0Mq C6F82746NStandalone C applicationN The project template have to be copied into the CodeWarrior Workspace by ticking Copy project into workspace tick box and click on Finish im Gen fos lt Import Projects Select a directory to search for existing Eclipse projects 7 Projects 56F82748 Standalone C Application C Freescale DSC56800EX_Q Select All Deselect All l Working sets Add project to working sets Working sets Select Figure 4 2 Project Import Settings 4 Other method to add the project template to the Workspace is to copy 25 56800 Quick Start r2 6NtationaryNDSC56800EX Quick Start r2 065M C56F82746NSta ndalone C applicationN folder to your workspace directory and drag and drop project file to the CodeWarrior Workspace Project Tab DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 2 Y C C CodeWarrior Development Stud
25. OCCS Configuration Use Factory Trim Value Yes Enable internal 32 kHz oscillator Power Down crystal oscillator Yes Core frequency 50 MHz frequency 200 MHz Loss of lock interrupt Disable Loss of lock interrupt 1 Disable Loss of reference clock Interrupt Disable Li d define OCCS CTRL INIT exeesiu define OCCS DIVBY INIT ex2e18U define OCCS USE FACTORY TRIM OCCS USE FACTORY TRIM TEMP Configuration Power Saving Modes Stop enabled Wait enabled OnCE clock to processor core Enabled when core TAP enabled DMA Enable in RUN and WAIT modes DMA enabled in all power modes Enable External Reset Padcell Input Filter No SIM Clock on GPIO Enable CLKO No M Figure 7 8 The appconfig h File DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 7 10 Chapter 8 License 8 1 Software License Agreement IMPORTANT Read the following Freescale Semiconductor Software License Agreement Agreement completely FREESCALE SEMICONDUCTOR SOFTWARE LICENSE AGREEMENT SOFTWARE FOR DSC56800EX_Quick_Start Tool This is a legal agreement between you either as an individual or as an authorized representative of your employer and Freescale Semiconductor Inc Freescale It concerns your rights to use this file and any accompanying written materials produced by Freescale the Software In consideration for Freescale allowing you to access the Software
26. Description m 55 iO Lre SCI BUFFERED TX SCI ENABLE Enable disable the write operations if SCI DISABLE the SCI operates in a BUFFERED EXE mode The buffer pointers are initial ized and interrupts enabled SCI CLEAR EXCEPTION NULL Clear the read write functions excep PU tion if exists SCI CLEAR STATUS REG NULL Clear the SCI Status Register v SCI DATA FORMAT SCI WORD 9BIT Set SCI word length X SCI WORD 8BIT SCI DATA POLARITY SCI INVERTED Set polarity of transmitted and 501 NOT INVERTED received data SCI DMA RECEIVER SCI ENABLE Enable disable the DMA Receiver 22122 SCI_DISABLE SCI DMA TRANSMITTER SCI ENABLE Enable disable the DMA Transmitter XN SCI DISABLE SCI ERROR NULL Test any of Error flags in the SCI Sta tus Register Return non zero if any viv error bit is set SCI GET LIN SYNC ERROR NULL Test the LIN Sync Error flag in the SCI Status Register Return non zero ifthe v v bit is set SCI GET RX ACTIVE NULL Test the Receiver Active flag in the SCI Status Register Return non zero viv if the bit is set SCI GET RX BUFFER FREESPA NULL Return the free space in the receive CE buffer during the BUFFERED opera viv tion SCI_GET_RX_CHARS_READY NULL Number of characters pending in the receive buffer during the BUFFERED viv operation SCI GET RX FRAMING ERROR NULL Test the Framing Error flag in the SCI Status Register Return non zero v v bit is set SCI GET RX FULL NULL Test the Receive
27. FMSTR TSA 16 FMSTR TSA FRAC32 Fractional data types Although these types are treated as integer types in C language it may be beneficial to describe them using these macro con stants so the FreeMASTER treats them properly FMSTR TSA UFRAC16 FMSTR TSA UFRAC32 Unsigned fractional data types Although these types are treated as integer types in C language it may be beneficial to describe them using these macro constants so the FreeMASTER treats them properly FMSTR TSA FLOAT 4 byte standard IEEE floating point type FMSTR TSA DOUBLE 8 byte standard IEEE floating point type FMSTR TSA USERTYPE name Structure or union type You must specify the type name as an argument 6 6 1 12 2 TSA Table List There must be exactly one TSA Table List in the application The list contains one entry for each TSA table which is defined anywhere in the application The TSA Table List begins with the FMSTR_TSA_TABLE_LIST_BEGIN macro FMSTR_TSA_TABLE_LIST_BEGIN and continues with TSA table entries for each table FMSTR_TSA_TABLE table_id FMSTR_TSA_TABLE table_id2 FMSTR_TSA_TABLE table_id3 DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 25 Freescale Semiconductor Inc The list is finished with the FMSTR TSA TABLE LIST END macro FMSTR TSA TABLE LIST DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Se
28. File Edit Module 1 Target 56 274 SYS Clock 50 000 MHz 4 PINOUT Package z OCCS On Chip Computer SYS System Suppo INTC Interrupt Cor DMA Contro 24 QT_A Quad Timer A0 Counte QT A1 Counte QT 2 Counte Counte PIT Periodic Interr PIT 0 Periodic PIT 1 Periodic GPIO General Purp GPIO A GPIO Genera GPIO C Gener 4 D General Settings Wait disable Stop disable Stop disabled _ p Stop permanently enabled Stop permanently disabled OnCE clock to processor core Wait enabled E Enabled when TAP enabled Y Stop disabled r Clock on GPIO Peripheral Pins Enable CLKO 0 Continuous System Clock Enable CLKO 1 Continuous System Clock 1 GPIOC4 IPS registers and all periph pins configuration 4 m 7 2 1 5 Warnings View 5 0 09520 aspen AI CMPB ospi GPIOC DACA TMRA2 CMPC DACA GPIOD DACB TMRA3 CMPD GPIOD DACB GPIOE PITO 1 GPIOE PwMCHO GPIOF PwMCH1 PITI MSCAN GPIOF PWMCH1 500 FwMCH2 apc I CYCADC 500
29. IIC PWM TMR SCIO SCI1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 153 Table 5 62 SYS Driver Commands x x Description m niu SYS HS CLOCK DISABLE combination of SYS HS xxx Enable high speed clock 2 SCIO SCI1 SYS HS CLOCK ENABLE combination of SYS HS xxx Enable high speed clock 2 IIC PWM TMR SCIO SCI1 SYS HS CLOCK ENABLE combination of SYS HS xxx Enable high speed clock 2 SCIO SCI1 SYS INIT NULL Initialize SIM and LVI periheral regis ters using the appconfig h _ INIT val viv ues SYS_ONCE SYS_ENABLE SYS_DISABL OnCE module enable viv E SYS PERIPH CLK DISABLE combination of Disable peripheral clock sly SYS_xxx_MOD SYS_PERIPH_CLK_ENABLE combination of Enable peripheral clock sly SYS_xxx_MOD SYS_PERIPH_CLK_REG2_DISABL combination of Disable peripheral clock SYS xxx MOD2 SYS PERIPH CLK REG2 ENABL combination of Enable peripheral clock 52 12 SYS MOD2 SYS PERIPH SW RESET combination of Issue software reset of peripheral SYS xxx PSWR GPIO TA MSCAN IICO QSPI 2 1 QSPIO SCI1 SCIO DACA D ACB PIT1 PITO CRC CYCAD C CMP EWM PWMA SYS PERIPH SW RESET combination of Issue software reset of peripheral SYS xxx PSWR GPIO TB TA FLEX CAN IIC1 IICO QSPI1 QSPIO 2 SCH SCIO DAC PDB1 PDBO PIT1 PITO QDC CRC CYCA DC SARADC CMP EWM PW MA SYS READ IO SHO
30. SET EVENT1 TERM 2 INPU AOI LOGO AOI INVERT AO Set INPUT C the Term 2 for TC NOTINVERT AOI LOG1 SET EVENT1 TERM 3 combination of Set all inputs at once of the Term 3 for AOI INPUT n xxx EVENTI C D xxx viv LOGO INVERT NOTIN VER LOG1 SET EVENT2 TERM 0 combination of Set all inputs at once of the Term 0 for AOI INPUT n xxx EVENT2 C D xxx viv LOGO INVERT NOTIN VER LOG1 AOI SET EVENT2 TERM 1 combination of Set all inputs at once of the Term 1 for AOI INPUT n xxx EVENT2 C D xxx viv LOGO INVERT NOTIN VER LOG1 SET EVENT2 TERM 2 combination of Set all inputs at once of the Term 2 for AOI INPUT n xxx EVENT2 C D xxx viv LOGO INVERT NOTIN VER LOG1 5 2 3 combination of Set all inputs at once of the Term 3 for AOI INPUT n xxx EVENT2 C D xxx viv LOGO INVERT NOTIN VER LOG1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 33 Table 5 7 AOI Driver Commands Term register Description ag 5 5 0 combination of Set all inputs at once of the Term 0 for AOI INPUT n xxx EVENTS C D xxx viv LOGO INVERT NOTIN VER LOG1 SET TERM 1 combination of Set all i
31. Software must periodically service the COP in order to reload the counter and prevent a reset The Table 5 8 shows module identifiers for COP Driver The Table 5 9 shows all commands dedicated for COP Driver Table 5 8 Identifiers for COP Driver Module identifier 56F82xxx 56F84xxx COP Y Table 5 9 Driver Commands gt lt gt lt gt lt gt lt Description 5 iO COP CLEAR COUNTER NULL Clear COP counter both steps are X performed COP CLEAR COUNTER NULL Clear COP counter 1st step of the sequence COP_CLEAR_COUNTER_PART2 NULL Clear COP counter 2nd step of the E sequence COP DEVICE COP ENABLE COP DISAB Enable disable COP watchdog viv LE counter COP_INIT NULL Initialize COP peripheral registers using the appconfig h _INIT values COP_LOR_WATCHDOG COP_ENABLE COP_DISAB Enable disable Loss of reference I LE clock watchdog COP READ COUNTER NULL Read current value of COP counter viv COP RUN IN STOP COP ENABLE COP DISAB Control the state of COP in WAIT LE mode COP RUN IN WAIT Control the state of COP in STOP COP ENABLE COP DISAB mode viv LE COP SET CLOCK PRESCALER COP xxx Select COP clock source prescaler xxx DIV1024 DIV256 DIV16 viv DIV1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 35 Table 5
32. volatile UWord8 vars volatile UWordl6 16 volatile UWord16 varl6inc 1 volatile UWord32 var32 volatile UWord32 var32inc 100 void main void Initialize SYS and GPIO modules ioctl SYS SYS INIT NULL ioctl COP COP INIT NULL ioctl GPIO GPIO INIT ALL NULL initialize UART ioctl SCI RS232 SCI INIT NULL FreeMASTER initialization FMSTR Init initialize amp enable interrupts DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 27 Freescale Semiconductor Inc ioctl INTC INIT NULL archEnableInt other initializations var8 10 main application loop while 1 feed the dog ioctl COP COP CLEAR COUNTER NULL scope variables varl6 varl6inc var32 var32inc This call should be placed in the timer interrupt or anywhere where the recorder sampling should occur FMSTR Recorder The FreeMASTER polling call must be called periodically in the main application loop to handle the communication interface and protocol Only in LONG INTR FreeMASTER interrupt mode all the processing is done during the communication interrupt so the FMSTR Poll is not needed the function is compiled empty in this case FMSTR Poll The FreeMASTER GPIO SCI 1
33. ADC GET LIMIT STATUS LLS UWord16 sample number Read the Low Limit Status Register 0 15 LLSx bit Low Limit Sample x ADC_GET_LIMIT_STATUS12_HLS UWord16 sample number Read the Low Limit Status Register 2 0 19 HLSx bit High Limit Sample flag ADC GET LIMIT STATUS12 LLS UWord16 sample number Read the Low Limit Status Register 0 19 LLSx bit Low Limit Sample x flag ADC GET LIMIT STATUS2 HLS UWord16 sample number Read the Low Limit Status Register 22 16 19 HLSx bit High Limit Sample flag ADC_GET_LIMIT_STATUS2_LLS UWord16 sample number Read the Low Limit Status Register 2 16 19 LLSx bit Low Limit Sample x flag ADC_GET_POWER_STATUS ADC_CONVERTER_O ADC_ Read and test the power status of CONVERTER_1 selected ADC converters ADC GET STATUS NULL Read the Status Register CIP bit in ET the Status Register ADC GET STATUS EOSI NULL Read the Status Register EOSI bit in ADC CONVERTER O0 ADC the Status Register viv CONVERTER_1 ADC_GET_STATUS_HLMTI NULL Read the Status Register HLMTI bit in UM the Status Register ADC GET STATUS LLMTI NULL Read the Status Register LLMTI bit in sly the Status Register ADC_GET_STATUS_RDY UWord16 sample number Read the Status Register 1 RDYx bit 212 0 15 Ready Sample 0 15 ADC GET STATUS RDY12 UWord16 sample number Read the Status Register 1 and 2 sly 0 19 RDYx bit Ready Sample 0 19 flag ADC_GET_STATUS_RDY2 UWord16 sample number Read the Status Register 2 RDYx bit
34. SYS SET F1PAD FUNCTION one of SYS F1PAD xxx Package pin function selection CLKOUT1 Y CMPD O SYS SET F1PAD FUNCTION one of SYS F1PAD xxx Package pin function selection CLKOUT1 XB IN7 CMPD _ Y SYS SET F2PAD FUNCTION one of SYS F2PAD xxx Package pin function selection 2 SCLO XB_OUT6 MISO1 SYS SET F2PAD FUNCTION one of SYS F2PAD xxx Package pin function selection 2 SCL1 XB OUT6 SYS SET F3PAD FUNCTION one of SYS F3PAD xxx Package pin function selection 2 SDA0 XB_OUT7 MOSI1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 159 Table 5 62 SYS Driver Commands XB_OUT7 x x Description m 505 Lre SYS SET F3PAD FUNCTION one of SYS F3PAD xxx Package pin function selection 2 SDA1 XB_OUT7 SYS_SET_F4PAD_FUNCTION one of SYS_F4PAD_xxx Package pin function selection 2 TXD1 XB_OUTS8 SYS_SET_F4PAD_FUNCTION one of SYS_F4PAD_xxx Package pin function selection XB_OUT8 TXD1 PWMA_0X Y PWMA_FAULT6 SYS_SET_F5PAD_FUNCTION one of SYS F5PAD xxx Package pin function selection x RXD1 XB_OUT9 SYS_SET_F5PAD_FUNCTION one of SYS_F5PAD_xxx Package pin function selection RXD1 XB_OUT9 PWMA_1X Y PWMA FAULT7 SYS SET F6PAD FUNCTION one of SYS F6PAD xxx Package pin function selection 2 IN2 SYS SET F6PAD FUNCTION one of SYS F6PAD xxx Package pin funct
35. bits there Caution This macro is the optimal way how to set the specified group of bits to given value However it must be kept in mind that during the short time between these two bit operations the target memory location goes through the third state where the bit group might contain invalid value already set but zeroes not yet cleared Example 2 24 periphBitGrpSRVar macro usage periphBitGrpSRVar 0x007f 10 amp ArchlIO Pll plldb This code sets the lower 7 bits of PLL Divide By register to the value 10 Other bits in the register are not affected 2 5 8 periphBitGrpRS set bit group to given value Call s void periphBitGrpRS UWord16 GroupMask UWordl16 Mask UWordl16 pAddr Arguments Table 2 10 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpRS macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected These bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared This macro uses a single instruction to execute the operation and allows only constants as GroupMask and Mask arguments If the application requires the variable as argument the periphBitGrpRSVar macro must be used instead Example 2 25 periphBitGrpRS macro
36. DSC56800EX Quick Start one should install and become familiar with the CodeWarrior development environment together the DSC56800EX Quick Start the CodeWarrior and TWRs create a complete and scalable tool solution for easy fast and efficient development 1 1 1 Features The DSC56800EX Quick Start environment is composed of the following major components core system infrastructure on chip drivers with defined API sample example applications Graphical Configuration Tool and FreeMASTER software support This section brings very illustrative information about these components while the comprehensive description can be found in specially targeted chapters DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 1 1 1 1 1 1 Core system Infrastructure The core system infrastructure creates the fundamental infrastructure for the 56F82xxx and 56F84xxx device operation and enables further integration with other components e g on chip drivers The basic development support provided includes setting of the required operation mode commonly used macro definitions portable architecture dependent register declaration mechanism for static configuration of on chip peripherals as well as interrupt vectors and the project templates 1 1 1 2 On chip Drivers The on chip drivers isolate the hardware specific functionality into a set of driver commands with defined API The API standardizes the interfac
37. FMSTR AppCmdSetResponseData Hello 5 FMSTR AppCmdAck 0x13 break case 2 This code shows how to return a response data before the Application Command is finished DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 22 6 6 1 11 FMSTR_RegisterAppCmdCall Register Application Command callback function Call FMSTR_BOOL FMSTR RegisterAppCmdCall FMSTR APPCMD CODE nAppCmdCode FMSTR PAPPCMDFUNC pCallbackFunc Arguments nAppCmdCode in an Application Command code for which the callback is to be registered pCallbackFunc in pointer to a callback function which is to be registered Use NULL to un register a callback registered previously with this Application Command Description This function can be used to register a given function as a callback handler for an Application Command The Application Command is identified using the single byte code The callback function is invoked automatically by the FreeMASTER driver when the protocol decoder obtains a request to get the application command result code The prototype of the callback function should be 5 APPCMD RESULT HandlerFunction FMSTR APPCMD CODE FMSTR APPCMD PDATA pData FMSTR SIZE nDataLen Where nAppcmd is the Application Command code pData points to Application Command data received if any nDataLen is the information about Application Command data length The retu
38. NULL Read and return the value of the 52 _14 Crossbar Select Register 14 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the Vallee _15 Crossbar Select Register 15 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the Zi _16 Crossbar Select Register 16 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 217 Crossbar A Select Register 17 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the viv _18 Crossbar A Select Register 18 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the sly _19 Crossbar Select Register 19 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the _2 Crossbar Select Register 2 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 20 Crossbar A Select Register 20 XBAR A READ CROSSBAR REG NULL Read and return the value of the 2 _21 Crossbar Select Register 21 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 2 _22 Crossbar Select Register 22 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 2 _23 Crossbar Select Register 23 XBAR A READ CROSSBAR REG NULL Read and return the value of the _24 Crossbar Select Register 24 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the _25 Crossbar Select Register 25 XBAR A READ CROSSBAR REG NULL Read and return the value of the 52 26 Crossbar A Select Register 26 XBAR A READ CROSSBAR REG NULL Read a
39. OCCS READ OSC OK FLAG NULL Return a non zero value after the crys tal oscillator has started up the XOSC OK indicator This command returns zero when the oscillator clock is not stable or if XOSC is disabled OCCS READ STATUS REG NULL Read and return the content of the PLL Status register as UWord16 OCCS RETRIM OSC 200K UWord16 value 0 511 Adjust the 200 kHz Internal RC Oscil lator frequency by the parameter value OCCS RETRIM OSC 32K UWord16 value 0 511 Adjust the 32 kHz Internal RC Oscilla tor frequency by the parameter value OCCS SELECT EXT CLOCK SO URCE OCCS CLKIN CLKIN OCCS _CLKIN_EXTAL Select the external clock source There are only two clock sources to be chosen from One is direct clock input and second is crystal resonator input The second input can be configured as a standard EXTAL XTAL input or as a direct clock input on the XTAL pin The external clock source selected by OCCS_SELECT_EXT_CLOCK_SOU RCE may then become an official MSTR_OSC clock by using the OCCS_SET_PRESCALER_CLOCK command DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 119 Table 5 48 5 Driver Commands Cmd pParam Description 56F82xxx 56F84xxx OCCS_SELECT_EXT_CLOCK_SO URCE OCCS_CLKIN_PRI OCCS_C LKIN_ALT OCCS_CLKIN_O SC Select the source of external clock sig nal OCCS_SET_CLOCK_CHECK
40. OCCS_TEST_CLOCK_CHECK NULL Test if clock checking function has fin ished OCCS_TRIM_OSC_200K NULL Set the factory frequency trim value of the 200 kHz Internal RC Oscillator OCCS TRIM OSC 32K NULL Set the factory frequency trim value of the 32 kHz Internal RC Oscillator OCCS TRIM RELAX OSC 8MHZ NULL Adjust the Relaxation Oscillator fre quency to 8 2 using the factory set tings This command reads the factory TRIM value from the internal flash and modifies the TRIM bits in the Oscillator Control register The standard startup code of the applications created with DSC56800EX Quick Start is capa ble of setting the required frequency and trimming value automatically when this is enabled in the Graphical Configuration Tool DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 121 Table 5 48 OCCS Driver Commands Description m 55 ive 5 WPROTECT CLK SETTIN OCCS ENABLE PERMAN Set the write protection of the GS ENT OCCS DISABLE PE Clock related configuration bits RMANENT Depending on the PERMANENT parameter value the protection may viv be activated deactivated permanently until next reset or might be changed later OCCS_WPROTECT_OSC_SETTIN OCCS ENABLE PERMAN Set the write protection of the Oscilla GS ENT OCCS DISABLE PE tor related
41. Root Directory Structure Sample Applications Directory Structure Src Directory SIUDEDEBL Ek Yu EE FER ar Stationery Directory SI ctUre mporn Dialog sore RPNNATRRRR Tr Project Import Drag amp Drop CodeWarrior Project File DSC56800EX Quick Start Wc TORT Macro Expansion PEODBBE FreeMASTER Application 0 GCT Main Window Pinout Page ICONS Me UU UU Pinout PEU rrinin n acci o eerren d aa Redes Mi ad OO C MN NT The appconiig i File T TT DSC56800EX Quick Start User s Guide Rev 2 04 2015 Page Number Freescale Semiconductor Chapter 1 Introduction This user s manual is targeted for Freescale 56F82xxx and 56F84xxx application developers Its purpose is to describe the development environment the software modules and the tools for the 56F82xxx and 56F84xxx and the Application Programming Interface API Simply this manual describes how to use the Freescale DSC56800EX Quick Start tool to develop software for the Freescale 56F82xxx 56F84xxx Digital Signal Controllers DSC 1 1 Overview The DSC56800EX Quick Start development environment provides ful
42. SCI INT DISABLE SCI TX EMPTY Disable selected interrupt sources SCI TX IDLE sy SCI_RX_FULL SCI_RX_ERROR SCI_INT_ENABLE SCI_TX_EMPTY Enable selected interrupt sources SCI_TX_IDLE viv SCI_RX_FULL SCI_RX_ERROR SCI LIN MODE SCI ENABLE Enable disable the LIN slave opera va SCI DISABLE tion mode DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 144 Freescale Semiconductor Inc Table 5 58 SCI Driver Commands Description ag 5 Lre SCI_OPERATING_MODE SCI NORMAL MODE Set SCI loop mode operation SCI INTERNAL LOOP MO PIN DE SCI SINGLE WIRE MODE SCI PARITY SCI PARITY ODD Set SCI parity mode SCI PARITY EVEN SCI PARITY NONE SCI READ CANCEL NULL Clear RIEF flag clear RxCounter and disable interrupts in SCIO SCI1 viv module used SCI READ CONTROL REG NULL Read and return the value of SCI Con trol Register SCI READ DATA NULL Read and return the value of the SCI PAN Data Register SCI RECEIVE REQ NULL Test the RDMA bit if the SCI is cur rently requesting a DMA data transfer v v for received data SCI RECEIVER SCI ENABLE Enable disables the SCI Receiver EXE SCI DISABLE SCI RECEIVER IDLE INT SCI ENABLE Enable disable the Receiver Inter PN SCI DISABLE rupt SCI RECEIVER INPUT EDGE FL NULL Test the Receiver Input Edge Flag if AG an acti
43. Select archive file Projects E 1 r Working sets E Add project to working sets Working sets Select 0 _ gt Finish 1 Figure 1 7 Root Directory Selection DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 1 9 Select the corresponding directory according to your TWR DSC board Step 4 Select root directory of the example project e g DSCS6SO0EX_Quick_Start r2 6Nample applicationSNMC56F8200TWRNpwm demo Drag and drop project file to the CodeWarrior Workspace Project Tab C C CodeWarrior Development Studio oles File Edit Search Project Run MQXTools Processor Expert Window Help 375814 1 Fv Mt 2 4o Hr Gre orn E venus odeWarrior Project 25 BE Outline 53 Project 53 ESL gt An outline is not available mel B A File Name File Name 5682748 Standalone C Applicat gO sample applications MCSGFB200TWR demo gt Search pwm demo 2 rganize v Include in library v Share with v Burn New folder e DellTPad Name Date modified Type Size Pd F FH E 5 AE 1 settings File folder e rocej me ApplicationConfig p J 3 Syst FLASH SDM ero i LL user 4 Freescale SystemConfi Inte 56800 Flash Progr
44. The FreeMASTER driver and the SCI module are configured by GCT TARGET MC56F82xxx device DESCRIPTION Advanced sample application demonstrating the functionality of Fe KKK KKK KK K K A k kk k kk kk kkk kkk kkk kkk kkk kkk kkk kkk kk f include qs h include intc h Kinclude gpio h include occs h include sci h include mscan h Hinclude sys h Hinclude cop h include freemaster h board specific configuration include board h Test structure types demonstrates the TSA feature thanks to which the FreeMASTER is able to load a variable and type information directly from the embedded application Af typedef struct UWordl6 aa UWord32 bb 2 Wordl6 Word32 dd 3 UWord8 ee Word8 ff 5 INNER STRUCT typedef struct UWordl6 UWord32 b INNER STRUCT inA 4 INNER STRUCT inB DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 32 OUTER STRUCT Test variables will be displayed in the FreeMASTER application volatile UWord8 var8 volatile UWordl6 16 volatile UWordl6 varl6inc volatile UWord32 var32 volatile UWord32 var32inc 100 volatile UWord8 nAppCmdCounter 1
45. define TARGET CONSTDATA INTRAM Constants and const variables located in x RAM define TARGET INITDATA PFLASH Initialization values for global variables located in pFlash define TARGET DATA INTRAM Variables located in internal RAM pragma define section fardata fardata data fardata bss RW be used to put far data after 0x10000 pragma define section pramcode pramcode text RWX can be used to put code to program ram pragma define section fast interrupt fast interrupt text RX 1 Prefix file is unconditionaly included at the begining of every compiled C file DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 45 if 0 y 5 5 endif end of cod xcluded by C compiler 2 7 2 Inside Startup Code This section goes step by step through the processor initialization code described briefly in Section 2 1 2 on page 2 The startup code described here can be found in the startup c file located in the SystemConfig subdirectory of any project created using the 56800EX_Quick_Start tool stationery 2 7 2 1 Symbols Used in Startup Code 2 7 2 1 1 Included Header Files The master Quick_Start header file gs h is included in the startup code This file further includes other critical system files to define common C types peripheral module base addresses and other types and macros required by the star
46. endif ifdef SIM MISCO INIT define SIM CLK1 SIM MISCO INIT gt gt 1 amp 0 1 else define SIM CLK1 0 endif todo optimalise check correct functionality test all cases CLKIN EXTAL CRYSTAL external clock on CLKIN GPIO CO EXTAL for black XTAL CO EXTAL for black GPIOCO XTAL C1 dif 5 EXTSEL enable clock for GPIO C bfset 0x0010 ArchlIO Sim sim 0 enable CLKIN 0 or CLKIN 1 1 SIM CLK1 bfset 0 0002 ArchIO Sim sim miscO bfset 0 00 0 ArchIO Sim sim_gpscl bfset 0 0008 ArchIO PortC per else bfset 0 0001 ArchIO Sim sim_gpscl bfset 0 0001 ArchIO PortC per bfclr 0 0002 ArchIO Sim sim miscO external clock XTAL GPIO 0 else enable clock for GPIO_C bfset 0 0010 ArchIO Sim sim_pce0 bfclr 0 0001 ArchIO Sim sim_gpscl bfset 0 0001 ArchIO PortC per crystal on EXTAL XTAL pins GPIO C1 and GPIO CO dif 5 CLKMODE bfset 0x0002 ArchIO PortC per give it some time until crystal resonator stabilizes we now run from internal relaxation oscillator 2 i e 4MHz move w 5000 x0 wait 50ms do x0 waitosc rep 36 nop sigle loop pass takes 40 cycles move w 1 R5 and also clears the watchdog move w D1 X R5 waitosc DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor
47. out argument means that the parameter value is an output from the function only inout argument means that a parameter value is an input to the function but the same parameter is also an output from the function Note inout parameters are typically input pointer variables in which the caller passes the address of a pre allocated data structure to a function The function stores its results within that data structure The actual value of the inout pointer parameter is not changed ioctl call s The ioctl call is generally represented by the following form UWordl6 ioctl const int pModuleBase void cmd UWordl16 param UWordl6 ioctl const int pModuleBase void cmd void pParam Description The ioctl call changes peripheral module modes or accesses the module register s Keep in mind that ioctl is treated as macro and that in result it is mostly compiled to an optimal inline code 1 There are three types of ioctl commands Single Instruction ioctl commands are translated into one assembler instruction These commands write parameter configuration directly into the peripheral register Multi Instruction ioctl commands are translated into several assembler instructions The performing of these commands can be broken by the interrupt occurrence These commands write parameter configuration directly into the peripheral register Software Layer ioctl commands are translated into several assembler instructions The
48. 04 2015 Freescale Semiconductor Inc 5 169 Table 5 64 Driver Commands X X x x Cmd pParam Description ag 5 SET OUT PWMA EXT XBAR A INPUT xxx Set XBAR A OUT28 input 2 SET OUT PWMA FAUL A INPUT Set A OUT29 input 2 SET OUT PWMA FAUL A INPUT Set OUT930 input 2 T1 XBAR A SET OUT PWMA FAUL XBAR A INPUT xxx Set A OUTS1 input T2 XBAR_A_SET_OUT_PWMA_FAUL XBAR_A_INPUT_xxx Set XBAR_A_OUT32 input 2 T3 XBAR_A_SET_OUT_PWMA_FORC XBAR_A_INPUT_xxx Set XBAR A OUT33 input E XBAR A SET OUT PWMA FORC XBAR A INPUT xxx Set XBAR A OUT33 input 2 SET OUT PWMAO EXT A INPUT Set A 0 24 input 2 _ SET OUT PWMAO EXT INPUT Set 0 24 input 2 _ SET OUT PWMAO EXT INPUT Set XBAR_A_OUT20 input 2 SET OUT PWMAO EXT A INPUT Set A OUT20 input 2 SET OUT PWMA1 EXT A INPUT Set OUT25 input gt _ SET OUT PWMA1 EXT XBAR A INPUT xxx Set OUT25 input 32 _SYNC XBAR_A_SET_OUT_PWMA1_EXT XBAR_A_INPUT_xxx Set XBAR_A_OUT21
49. At the core level the interrupts can be in four states DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 37 e interrupts disabled default state use archDisableInt macro interrupts enabled use archEnableInt macro e Priority levels 1 2 and 3 enabled level 0 disabled use archEnableIntLv1123 macro e Priority levels 2 and 3 enabled levels 0 and 1 disabled use archEnableIntLv123 macro 2 6 3 Code Example The following example shows the installation of the ISR into the interrupt vector table and shows how to enable interrupts using the 56800EX Quick Start tool The following example shows the installation of the external interrupt IRQA the timer counter D2 interrupt and the PWM A reload interrupt The example shows a part of the code which must be included in appconfig h all three ISRs and the initialization code ISRs are declared as Zpragma interrupt to instruct the compiler to save restore all used registers and to terminate the ISRs with an RTI instruction Inside the appconfig h file INT VECTOR ADDR and INT PRIORITY xx define statements are used to install the ISR at the specified interrupt vector and to define the interrupt priority level The achEnableInt macro and the ITCN driver commands INIT GPRS and ITCN INIT IPR are used to enable interrupts Example 2 51 Installing ISRs and enabling interrupts 1 appconfig h file KK IK KK Ck
50. IPBus Clock Prescaler INIT regist VALI regist fclk 1 er 1700 er 1699 Fraction FRACVAL1 0 Sync source Local sync PWMX Reload source This module Reload Frequency Every 16 opportunity Half Cycle Reload Disable Full Cycle Reload Enable PWMA Mask Normal PWMB Mask Normal Mask Normal Output Output Output Output Output Output 3858858 Initializ and Polarity Active High Polarity Active High Polarity Active High enable Enabled enable Enabled enable Disabled Value 0 Di Valuel Dis Value 2 Di Value3 Dis Value 4 Di Value5 Dis Double Swit sable able sable able sable able ching PWM23 Deadtime count 1 0 Software Controlled Output Logic 0 Force Initi Logic 0 alization Enable No Source of FORCE OUTPUT signal Local force CTRL2 FORC Dead Time S Dead Time S PWM45 Initi ource 23 PWM23 ource 45 PWM45 al Value Logic 0 Logic 0 PWMX Initial Value Logic O0 Reload Enable Reload Erro r Disable Value 0 Compare Disable Value 1 Compare Disable Value 2 Compare Disable Value 3 Compare Disable Value 4 Compare Disable Value 5 Compare Disable Capture A0 Disable B Pair Operation Complementary value registers Disable lt State Logic 0 t State Logic 0 lt State Logic 0 GI os DSC56800EX Quick Start User s Guide
51. Logic 0 by Fault PWMB Fault State Logic 0 by Fault PWMX Fault State Logic 0 Submodule 0 Disable Pins PWMA by Fault Fault 0 No Disable Pins PWMA by Fault Fault 1 No Disable Pins PWMA by Fault Fault 2 No Disable Pins PWMA by Fault Fault 3 No Disable Pins PWMB by Fault Fault 0 No Disable Pins PWMB by Fault Fault 1 No Disable Pins PWMB by Fault Fault 2 No Disable Pins PWMB by Fault Fault 3 No Disable Pins PWMX by Fault Fault 0 No Disable Pins PWMX by Fault Fault 1 No Disable Pins PWMX by Fault Fault 2 No Disable Pins PWMX by Fault Fault 3 No Disable Pins PWMX by Fault PWMA Fault State Logic 0 Disable Pins PWMX by Fault PWMB Fault State Logic 0 Disable Pins PWMX by Fault PWMX Fault State Logic 0 Submodule 1 Disable Pins PWMA by Fault Fault 0 No Disable Pins PWMA by Fault Fault 1 No Disable Pins PWMA by Fault Fault 2 No Disable Pins PWMA by Fault Fault 3 No Disable Pins PWMB by Fault Fault 0 No Disable Pins PWMB by Fault Fault 1 No Disable Pins PWMB by Fault Fault 2 No Disable Pins PWMB by Fault Fault 3 No lt 0 No lt 1 No lt 2 No lt 3 No Faul W ct tu tu Submodule 2 Disable Pins Fault Fau Disable Pins P by Fault Fau Disable Pins P by Fault Fau Disable Pins P by Fault Fau Disable Pins P by Fault Fau Disable Pins P by Fault Fau 33885 Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disa
52. Master sync 0 Reload source 0 module Reload Frequency Every opportunity alf Cycle Reload Disable ull Cycle Reload Enable A Mask Normal Mask Normal Mask Normal Output Polarity Active High Output Polarity Active High Output Polarity Active High Output enable Enabled Output enable Enabled Output enable Disabled WMA and PWMB Pair Operation Independent Initialize value registers Disable Value 0 Disable Valuel Disable Value 2 Disable Value3 Disable Value 4 Disable Value5 Disable Software Controlled Output Logic 0 Logic 0 Force Initialization Enable No Source of FORCE OUTPUT signal Local force CTRL2 FORC Dead Time Source 23 PWM23 Dead Time Source 45 PWM45 PWM45 Initial Value Logic 0 Logic 0 PWMX Initial Value Logic 0 Reload Disable Reload Error Disable Value 0 Compare Disable Value 1 Compare Disable lt oe IM X A B X A B X U U U U U U U U U U HE GI DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 19 Freescale Semiconductor Inc Value 2 Compare Disable Value 3 Compare Disable Value 4 Compare Disable Value 5 Compare Disable Capture 0 Disable Capture Al Disable Capture BO Disable Capture Bl Disable Capture Disable Capture 1 Disable Capture A Input selec Capture B Inpu
53. PwMCH2 sch PwMCH3 CRC sch PWMCH3 SCI Internal Peripheral Select IPS0 Write Protect the System Configuration 7 Miscella GPIOC3 BCE SD and PCR registers protection Registers not protected Figure 7 5 Register View n 1 r Modules Enabled in STOP Master F _ wees Registers View SIM_CONROL 004 SIM_CLKOSR 090000 PMC_CONTROL 700000 SIM_GPSAL pono 0 SIM_GPSBL SIM_GPSCL 090000 1 SIM_GPSCH mono 1 SIM GPSEL Jooo SIM_GPSFL poo SIM GPSFH pono SIM PCR SIM_PCEO 08002 SIM PCET poo SIM PCE2 50000 SIM PCE3 04000 SIM PROT pono SIM 500 poo _ 7 NM Z Similarly as the Registers View bar the Warnings View bar can be shown or hidden any time when working with the GCT Warnings View shows a list of warnings collected from across all control pages in the GCT By default the Warnings View displays only the warnings from modules selected to be saved to an output file those with a checkmark sign in peripheral tree All other warnings can be displayed in the list if required A double click on a warning item in the list activates the control page where the potential conflict exists and a balloon like hint is shown as a notification The Warnings View bar can be activated or deactivated by a menu View Warnings Summary DSC56800EX Quick
54. Table 5 29 shows module identifiers for FTFL Driver Table 5 29 Identifiers for FTFL Driver Module identifier 56 82 56F84xxx FTFL Y The Table 5 30 shows all commands dedicated for FTFL Driver Table 5 30 FTFL Driver Command Cmd pParam Description 56F82xxx 56F84xxx FTFL INIT NULL Initialize the FTFL peripheral registers using the appconfig h INIT values lt DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 85 5 1 14 Flash Memory Controller FMC Driver The Flash Memory Controller FMC is a memory acceleration unit that provides e aninterface between the device and the dual bank nonvolatile memory Bank 0 consists of program flash memory and bank 1 consists of FlexNVM e buffers that can accelerate flash memory transfers The Flash Memory Controller manages the interface between the device and the dual bank flash memory The FMC receives status information detailing the configuration of the memory and uses this information to ensure a proper interface In addition for bank 0 the FMC provides three separate mechanisms for accelerating the interface between the device and the flash memory A 64 bit speculation buffer can prefetch the next 64 bit flash memory location and both a 4 way 8 set cache and a single entry 64 bit buffer can store previously accessed flash memory data for quick access times The Table 5 31 sh
55. Table 5 44 MSCAN Driver Commands Description ag LL LL ive MSCAN_CLEAR_RINT_FLAG NULL Clear the receiver buffer full interrupt flag Typically this command is used in the receiver interrupt service routine v to clear and acknowledge the inter rupt MSCAN CLEAR RXFRM NULL Clear the frame received flag Y MSCAN CLEAR WINT FLAG NULL Clear the wakeup interrupt flag Typi cally this command is used in the CAN wake up interrupt service routine v to clear and acknowledge the inter rupt MSCAN DEVICE MSCAN ENABLE MSCAN Enable disable the MSCAN periph DISABLE eral MSCAN ERINT DISABLE combination of Disable the selected MSCAN inter MSCAN xxx INT rupts 2 xxx WAKEUP STATCHNG OVERRUN RXFULL MSCAN_ERINT_ENABLE combination of Enable the selected MSCAN inter MSCAN xxx INT rupts xxx WAKEUP STATCHNG OVERRUN RXFULL MSCAN_GET_ENABLED_TINT NULL Return the mask of all Transmit Buffer Empty interrupts which are currently enabled The result value can then be v used to determine which transmit buffer needs servicing MSCAN GET RX ERR COUNT NULL Return the 8 bit value of the MSCAN Receive Error Counter CANRXERR MSCAN_GET_SLEEP_MODE NULL Return a non zero value as UWord16 if the MSCAN is in the sleep mode This command returns zero when the Y MSCAN module is active not sleep ing MSCAN GET TX ERR COUNT NULL R
56. from the date of purchase as evidenced by a copy of the receipt Freescale s entire liability and your exclusive remedy under this warranty will be replacement of the defective media returned to Freescale with a copy of the receipt Freescale will have no responsibility to replace any media damaged by accident abuse or misapplication This warranty extends only to you and may be invoked only by you for your customers Freescale will not accept warranty returns from your customers NO ADDITIONAL WARRANTY EXCEPT FOR THE LIMITED WARRANTY ON MEDIA PROVIDED ABOVE THE SOFTWARE AND 3RD PARTY PRODUCTS IF ANY ARE PROVIDED AS IS YOUR USE OF THE SOFTWARE OR 3RD PARTY PRODUCTS IS AT YOUR SOLE RISK SHOULD THE SOFTWARE OR ANY 3RD PARTY PRODUCT PROVE DEFECTIVE YOU AND NOT FREESCALE OR ANY FREESCALE REPRESENTATIVE ASSUME THE ENTIRE COST OF ALL NECESSARY SERVICING REPAIR OR CORRECTION FREESCALE EXPRESSLY DISCLAIMS ALL WARRANTIES WITH RESPECT TO THE SOFTWARE AND 3RD PARTY PRODUCTS WHETHER SUCH WARRANTIES ARE EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT YOU EXPRESSLY ASSUME ALL LIABILITIES AND RISKS FOR ANYONE S USE OR OPERATION OF ANY APPLICATION PROGRAMS YOU MAY CREATE WITH THE SOFTWARE INDEMNITY Freescale will defend at its expense any suits asserted against you based upon a claim that the Software as provided by Freescale infringes a U S pate
57. only the registers with non reset values are saved Omitting the reset value registers in the appconfig h file typically reduces a size of the module initialization code as those values not defined in the file are not written to the peripheral registers On the other side this approach requires all the modules being initialized to be in post reset state otherwise the result may be a most probably a mix of previous registers state and a GCT defined configuration This is a project specific option which is saved to the appconfig h file as a macro constant named DFLTS OMITTED This constant is set to non zero value when the Generate all register values option is turned off DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 7 8 e Set as default check box to save the selected options as default ones for the and the current project Options GCT Options Preserve user comments Current Project Options Generate all register values even if same as reset value Set as default Cancel Figure 7 7 Options dialog 7 2 2 Application Configuration File Structure The application configuration header file is common ANSI C language header file which mostly contains register initialization values but may contain o
58. performing of these commands can be broken by the interrupt occurrence These commands represent additional software functionality for complex peripheral control Arguments Table 5 1 Driver Arguments ioctl pModuleBase in Module identifier e g OCCS cmd in Command name pParam in inout Used to pass the relevant data to ioctl function call Items Separators Convention only one of the specified items is allowed DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 4 Freescale Semiconductor Inc consolidation of items is allowed iteml item2 item3 amp intersection of items is allowed iteml amp item2 amp item3 Device Driver Support Command tables contain two columns 56F82xxx and 56F84xxx The tick defines the command support for particular DSC members DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 1 1 12 bit Cyclic Analog to Digital Converter ADC Driver The analog to digital ADC converter function consists of two separate analog to digital converters each with eight analog inputs and its own sample and hold circuit A common digital control module configures and controls the functioning of the converters The Table 5 2 shows module identifiers for ADC Driver Table 5 2 Identifiers for ADC Driver Module identifier 56F82xxx 56F84xxx ADC Y ADC 1 Y Table 5 3 s
59. record the time stamp when a match Y occurs between the position counters POS and the compare value COMP Use REGS READ to record the time stamp when the UPOS LPOS REV or POSD regis ters are read ENC SET TEST COUNT UWord16 value 0 255 Set the number of quadrature advances to generate during self test Y operation ENC SET TEST COUNTER ENC ENABLE ENC DISAB Enable disable the test counter to LE generate the quadrature signal used Y for self test ENC SET TEST MODE ENC ENABLE ENC DISAB Enable disable the connection of LE self test signals to the inputs of the Y quadrature decoder module ENC SET TEST PERIOD Uword16 value 0 31 Set the period of quadrature phase in IPBus clock cycles for the self test Y operation ENC SET TRG CLEAR POSITIO ENC ENABLE ENC DISAB Enable disable the rising edge of N REGISTERS LE TRIGGER input to clear POSD REV Y UPOS and LPOS registers DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 72 Freescale Semiconductor Inc Table 5 21 ENC Driver Command Cmd pParam Description 56F82xxx 56F84xxx ENC_SET_TRG_UPDATE_HOLD_ REGISTERS ENC_ENABLE ENC_DISAB LE Enable disable the rising edge of the TRIGGER input to cause an update of the POSDH REVH UPOSH and LPOSH registers Note Updating the POSDH register will also cause the POSD register to be cleared lt ENC_SINGLE_PHASE_COUNT ENC_ENABLE ENC_DI
60. s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 6 2 FreeMASTER Communication Configuration Items for appconfig h Continued SYMBOL TYPE DESCRIPTION FMSTR_USE_WRITEVARMASK numeric When this constant is defined as a non zero value the zero non zero support for Masked Write Variable feature is imple mented This command enables a write access to 1 and 2 byte variables only This functionality is a subset of the Masked Write Memory feature Comparing it with the Masked Write Memory feature there is one byte saved on the communication line Default 0 false 6 6 Driver Usage The FreeMASTER driver was designed to be easily used in any DSP56F800EX Quick Start application and also in custom user code With DSP56F800EX Quick Start the following steps are necessary to enable a basic FreeMASTER connectivity in the application The FreeMASTER driver needs to be configured in the Graphical Configuration Tool or in the appconfig h file directly e freemaster h file needs to be included in any application source file which makes FreeMASTER API calls The FMSTR Init function has to be called before any other FreeMASTER driver API calls ForFMSTR LONG INTR or FMSTR SHORT INTR modes the SCI JTAG interrupts need to be directed to FMSTR Isr function This is done automatically when the FreeMASTER driver is configured using the Graphical Configuration Tool The interr
61. you are agreeing to be bound by the terms of this Agreement If you do not agree to all of the terms of this Agreement do not install or download the Software If you change your mind later stop using the Software and delete all copies of the Software in your possession or control Any copies of the Software that you have already distributed where permitted and do not destroy will continue to be governed by this Agreement Your prior use will also continue to be governed by this Agreement Please note that 3rd party products including but not limited to software 3rd Party Products may be distributed in conjunction with the Software This Agreement does not apply to those 3rd Party Products which will be subject to their own licensing terms LICENSE GRANTS Your license to the Software and applicable restrictions vary depending on the nature of the Software provided Review the following grants carefully to ensure your compliance IF SOFTWARE PROVIDED IN SOURCE FORM Freescale grants to you the non exclusive non transferable right 1 to use the Software exclusively in conjunction with a development platform from Freescale or other development prototype or production platform utilizing at least one 56800 E processor from Freescale Exclusive Use 2 to reproduce the Software as necessary to accomplish the Exclusive Use 3 to prepare derivative works of the Software as necessary to accomplish the Exclusive Use 4 to distribute the Soft
62. 0x0802U define SIM PCE2 INIT 0x0000U define SIM PCE3 INIT O0xOOFOU INTC Configuration DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 11 Freescale Semiconductor Inc 577 define INIT 0 00000 define INT_VECTOR_ADDR_86 pwm_reload_isr define INT PRIORITY LEVEL 86 INTC LEVELO GPIO_E Configuration Pin 0 Function PWMOB PullUp Disable Pin 1 Function PullUp Disable Pin 2 Function PWM1B PullUp Disable Pin 3 Function PWM1A PullUp Disable Pin 4 Function PWM2B PullUp Disable Pin 5 Function PWM2A PullUp Disable Pin 6 Function PWM3B PullUp Disable Pin 7 Function PWM3A PullUp Disable zy define GPIO E PER INIT OxOOFFU Rx GPIO_F Configuration Pin 0 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 1 Function GPIO Direction Input PullUp Disable Int Polarity Active high Pin 2 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 3 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 4 Function TXD1 PullUp Disable Pin 5 Function RXD1 PullUp Disable Pin 6 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int
63. 1 2 External Tool Configurations c Set the GCT launcher settings in Main tab Location path to the project folder should be less than 120 characters and must not contain a space character Working directory and Arguments as a system variable project_loc DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 1 5 Create manage and run configurations Run program Name GCT I type filter text C Main Refresh Build MI Environment 71 Common Program Location CAFreescale DSCSG800EX Quick Start 2 B tool gct gctS6FB00 exe oec ect Visi Working Directory Siprojectioc _ Browse Workspace Browse File System Arguments Filter matched 2 of 2 iter m Set project location for Working Directory and Arguments Apply click on Variables button Gee Figure 1 3 GCT Integration d Untick the Build before lanunch box and click Apply Run program pexa type filter text in 42 Build Environment 7 Common Q Program Buil 0 8 The entire workspace The project containing the selected resource Specific projects Projects Include referenced projects Filter matched 2 of 2 iter Filter by Project 135682748 Api gt Figure 1 4 Build Before Launch e Click on Run button f Optionally the key biddin
64. 1 4 fill memory with value testl move l 4 Linternal RAM addr r1 initialize verify memory pointer do r2 end intramcheckl start verify loop move w 1 R5 clear COP watchdog counter move w D1 X R5 cmp w xi rl xO0 TEST1 read amp compare beq lt tlpassed TEST1 OK debughlt tlpassed move w yO x rl TEST2 write test2 move wx rl l1 yl read from incremented address s TEST3 cmp w x rl1 y0 read written value amp compare should be test2 beq t2passed TEST2 OK nop debughlt MEMORY TEST FAILED stop t2passed move w lc b skip TEST3 for the last memory cell when LC 1 1 b ble lt t3passed 1 0 TEST3 value from incremented addr should be 1 beq lt t3passed TEST3 OK nop debughlt MEMORY TEST FAILED stop t3passed move w 0 rl clear checked memory location nop nop without nops the branch to t3passed above nop could confuse the hardware loop unit end intramcheckl1l DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 54 Freescale Semiconductor Inc 2 7 2 2 7 Stack Pointer Initialization The stack pointer SP register is initialized to the first odd value after Lstack addr symbol generated by linker command file The first stack location is t
65. 16 32 64 128 256 Set the post scaler factor OCCS_SET_POSTSCALER OCCS_CLOCK_OUT_DIVID 1 2 4 8 16 32 64 128 25 6 Set the postscaler DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 120 Freescale Semiconductor Inc Table 5 48 5 Driver Commands Cmd pParam Description 56F82xxx 56F84xxx OCCS_SET_PRESCALER_CLOCK OCCS_INTERNAL_RELAX_ OSC OCCS_CRYSTAL_OS Set the prescaler clock source OCCS_CRYSTAL_OSC should only be set if XTAL and EXTAL pin func tions are enabled in the appropriate GPIO control register lt lt OCCS_SET_ZCLOCK_SOURCE OCCS_POSTSCALER_OUT PUT OCCS PRESCALER OUTPUT 83xx only OCCS MSTR OSC OUTP UT 80xx only OCCS xxx OSC OUTPUT xxx PLL MSTR 800x amp 84 amp 827 Set the sys_clk_x2 source to the SIM which generates divided down ver sions of this signal for use by memo ries and the IP Bus If PLLPD is set ZSRC is automatically set to 0 to pre vent a loss of the reference clock to the core NOTE Before switching to a new clock source you must enable the new source The PLL should be on configured and locked before switching to it For extra assurance in cases where the PLL may be stressed confirm that the PLL remains locked for a period of time before switching to it OCCS_TEMP_TRIM_OSC_8MHZ UWord16 value 0 15 Set the temperature trim value
66. 2015 5 100 Freescale Semiconductor Inc 5 1 18 The Interrupt Controller INTC module arbitrates among the various interrupt requests IRQs module supports unique interrupt vectors and programmable interrupt priority It signals to the DSC core when an interrupt of sufficient priority exists and to what address to jump to service this interrupt Interrupt Controller INTC Driver The INTC module design has these distinctive features e Programmable priority levels for each IRQ e Two programmable fast interrupts Notification to System Integration Module SIM to restart clocks when exiting wait and stop modes Driving of initial address on the address bus after reset The Table 5 39 shows module identifiers for INTC Driver Table 5 39 Identifiers for INTC Driver Module identifier 56F82xxx 56F84xxx INTC Y Table 5 40 shows all commands dedicated for INTC Driver Table 5 40 INTC Driver Commands gt lt Description LL LL Lre GET INT LEVEL NULL Read and return the current level of the interrupt which is currently being sent to the processor core NULL Read and return the number of the currently processed interrupt which is zh the value of VAB field of the INTC Control Register INTC GET INT STATE NULL Read
67. 4 Identifiers for ADC16 Driver Module identifier 56F82xxx 56F84xxx ADC16 The Table 5 5 shows commands dedicated for ADC16 Driver Table 5 5 ADC16 Driver Command Description Sila io ADC16_CALIBRATION_START NULL Start the calibration sequence A ADC16 CLEAR CALIBRATION FA NULL Clear the Calibration Failed flag 2 ILED_FLAG DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 23 Table 5 5 ADC16 Driver Command Description ag 55 iO ADC16_INIT NULL Initialize the ADC16 peripheral regis ters using the appconfig h _ INIT val Y ues ADC16 READ CFG1 REG NULL Read and return value of the Configu ration register 1 as UWord16 ADC16_READ_CFG2_REG NULL Read and return value of the Configu 2 ration register 2 as UWord16 ADC16 READ CLPO REG NULL Read and return the Plus Side Gen eral Calibration Value 0 register as Y Uword16 ADC16 READ CLP1 REG NULL Read and return the Plus Side Gen eral Calibration Value 1 register as Y UWord16 ADC16 READ CLP2 REG NULL Read and return the Plus Side Gen eral Calibration Value 2 register as Y UWord16 ADC16 READ CLP3 REG NULL Read and return the Plus Side Gen eral Calibration Value 3 register as Y UWord16 ADC16 READ CLP4 REG NULL
68. 5 7 AOI Driver Commands DSC56800EX Quick Start User s Guide Rev 2 04 2015 Description ag 5 Lre SET EVENTO TERM combination of Set all inputs at once of the Term 3 for AOI INPUT n xxx EVENTO C D xxx viv LOGO INVERT NOTIN VER LOG1 SET EVENTO TERM 3 INPU AOI LOGO AOI INVERT AO Set INPUT A of the Term for Zl TA NOTINVERT AOI LOG1 EVENTO SET EVENTO TERM 3 INPU AOI LOGO AOI INVERT AO Set INPUT B of the Term for P T B NOTINVERT AOI LOG1 EVENTO SET EVENTO TERM 3 INPU AOI LOGO AOI INVERT AO Set INPUT C of the Term for 24152 TC NOTINVERT AOI LOG1 EVENTO SET EVENTO TERM 3 INPU AOI LOGO AOI INVERT AO Set INPUT D of the Term for pe T D NOTINVERT AOI LOG1 EVENTO AOI SET EVENT1 TERM combination of Set all inputs at once of the Term 0 for AOI INPUT n xxx EVENTI C D xxx viv LOGO INVERT NOTIN VER LOG1 SET EVENT1 TERM 0 INPU AOI LOGO AOI INVERT AO Set INPUT A of the Term 0 for PE TA NOTINVERT AOI LOG1 SET EVENT1 TERM 0 INPU AOI LOGO AOI INVERT AO Set INPUT B of the Term 0 for NOTINVERT AOI 10091 1 SET EVENT1 TERM 0 INPU AOI LOGO AOI INVERT AO Set INPUT_C the Term 0 for TC NOTINVERT AOI LOG1 SET EVEN
69. 9 Driver Commands Cmd pParam Description 56F82xxx 56F84xxx COP_SET_CLOCK_SOURCE COP_xxx xxx 1KHZ IPBUS COSC R OSC Select COP clock source lt lt SET INT VAL UWord16 Set COP interrupt value When the count value is equal to the COP inter rupt value an interrupt is generated COP SET TIMEOUT UWord16 Set COP Timeout Value COP SET WINDOW VAL UWord16 Set upper bound of the CNTR value that must be crossed prior to the CNTR being serviced If CNTR is above this value when a service occurs then a COP window reset is generated If the CNTR value is less than or equal to this value at the time of the service then the service is allowed to occur normally COP WRITE PROTECT NULL Write protect COP settings until Reset DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 36 Freescale Semiconductor Inc 5 1 5 Cyclic Redundancy Check CRC Driver The Cyclic Redundancy Check CRC generator module uses the 16 bit CRC CCITT polynomial x16 x12 x5 1 to generate CRC code for error detection The 16 bit code is calculated for 8 bits of data at a time and provides a simple check for all accessible memory locations whether they be in a flash memory or RAM The Table 5 10 shows module identifiers for CRC Driver Table 5 10 Identifiers for CRC Driver Module identifier 56 82 56 84
70. A OUTS31 input 2 LT2 XBAR A SET OUT PWMAB FAU XBAR A INPUT xxx Set A OUT32 input 2 LT3 XBAR A SET OUT PWMB FORC XBAR A INPUT xxx Set A OUT57 input v E XBAR A SET OUT PWMBO EXT XBAR A INPUT xxx Set OUT53 input SYNC XBAR A SET OUT PWMB1 EXT XBAR A INPUT xxx Set A OUT54 input 2 _SYNC XBAR_A_SET_OUT_PWMB2_EXT XBAR_A_INPUT_xxx Set XBAR_A_OUT55 input 2 _SYNC XBAR A SET OUT EXT XBAR A INPUT xxx Set OUT56 input _SYNC XBAR A SET OUT QD CAP XBAR A INPUT xxx Set A OUTA8 input A XBAR A SET OUT QD HOME XBAR A INPUT xxx Set A OUTZ47 input Y DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 171 Table 5 64 Driver Commands Description 5 5 8 A SET OUT QD INDEX XBAR A INPUT xxx Set XBAR A OUTA6 input v XBAR A SET OUT QD PHA XBAR A INPUT xxx Set XBAR OUTA4 input v XBAR A SET OUT QD PHB XBAR A INPUT xxx Set XBAR OUTA5 input e SET OUT IN XBAR A INPUT xxx Set A OUTA9 input A A SET OUT QT AO IN XBAR A INPUT xxx Set XBAR A OUT34 input v XBAR A SET OUT QT A1 IN XBAR A INPUT xxx Set XBAR OUT50 input v A SET OUT QT 1 IN XBAR A INPUT xxx Set XBAR OUT35 input v XBAR A SET OUT
71. Agreement is held for any reason to be invalid or unenforceable then the remaining provisions of this Agreement will be unimpaired and unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or Freescale of a material benefit in which case the Agreement will immediately terminate the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision NO WAIVER The waiver by Freescale of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision DSC56800EX Quick Start User s Guide Rev 2 04 2015 8 5 Freescale Semiconductor Inc Revision history Chapter 9 Revision history Table 9 1 Revision history Revision Date Substantial changes 0 04 2013 Initial release 1 05 2013 Updated Table 5 18 2 03 2015 Added the Var macro references to Chapter 2 Core System Infrastructure DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 9 1
72. E6PAD xxx Package pin function selection PWMBSB XB IN4 SYS SET E7PAD FUNCTION one of SYS E7PAD xxx Package pin function selection T DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 158 Freescale Semiconductor Inc Table 5 62 SYS Driver Commands x x Description m 5 Lre SYS SET E7PAD FUNCTION one of SYS E7PAD xxx Package pin function selection 2 PWMASA XB 1 5 SYS SET E8PAD FUNCTION one of SYS E8PAD xxx Package pin function selection 2 FAULTO SYS SET E9PAD FUNCTION one of SYS E9PAD xxx Package pin function selection 2 PWMA_FAULT1 SYS SET FOPAD FUNCTION one of SYS FOPAD xxx Package pin function selection SCLK1 XB_IN6 SYS_SET_FOPAD_FUNCTION one of SYS_FOPAD_xxx Package pin function selection 2 XB ING TB2 SCLK1 SYS SET F10PAD FUNCTION one of SYS F10PAD xxx Package pin function selection PWMA FAULT6 XB OUT1 Y 0 SYS SET F11PAD FUNCTION one of SYS F11PAD xxx Package pin function selection TXDO XB IN11 SYS SET F12PAD FUNCTION one of SYS F12PAD xxx Package pin function selection 2 5 1 SYS SET F18PAD FUNCTION one of SYS F18PAD xxx Package pin function selection 5 MOSI1 SYS SET F14PAD FUNCTION one of SYS F14PAD xxx Package pin function selection x SCLK1 SYS SET F15PAD FUNCTION one of SYS F15PAD xxx Package pin function selection 2 RXDO XB IN10
73. FAULT 0 1 2 3 Set fault normal mode PA ODE EFPWM SET FAULT SAFETY M EFPWM FAULT 0 1 2 3 Set fault safety mode EFPWM SET FAULTO FULL CYC EFPWM_FAULT_X 0 1 2 3 Set re enabling PWM outputs at start XN LE of a full cycle EFPWM SET FAULTO HALF FUL EFPWM FAULT 0 1 2 3 Set re enabling PWM outputs at start sly L CYCLE of a half or full cycle EFPWM SET FAULTO NORMAL EFPWM FAULT 0 1 2 3 Set fault normal mode 4112 EFPWM SET FAULTO SAFETY EFPWM FAULT 0 1 2 3 Set fault safety mode v ku MODE EFPWM SET FAULT1 FULL CYC EFPWM FAULT 0 1 2 3 Set re enabling PWM outputs at start Kw LE of a full cycle EFPWM SET FAULT1 HALF FUL EFPWM FAULT 0 1 2 3 Set re enabling PWM outputs at start PE L CYCLE of a half or full cycle EFPWM SET FAULT1 NORMAL EFPWM FAULT 0 1 2 3 Set fault normal mode Faller MODE EFPWM_SET_FAULT1_SAFETY_ EFPWM_FAULT_X 0 1 2 3 Set fault safety mode VA DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 52 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands Cmd pParam Description 56F82xxx 56F84xxx EFPWM_SET_FORCE_OUT EFPWM_SUB3_PWM23_SO URCE_xxx PWM INV_PWM SWOUT EXT EFPWM_SUB3_PWM4 5 SOURCE xxx PWM INV PWM SWOUT EXT EFPWM_SUB2_PWM2 3 SOURCE xxx PWM INV PWM SWOUT EXT EFPWM SUB2 PWM4 5 SOURCE xxx PWM INV PWM SWOUT EXT EFPWM_SUB1_PWM2 3 SOURCE xxx PWM INV PWM SWOUT EXT EF
74. FLAG QT_READ_HOLD_REG NULL Read and return the value of the timer counter Hold register as UWord16 QT_READ_LOAD_REG NULL Read and return the value of the timer counter Load register as viv UWord16 QT READ STATUS CONTROL R NULL Read and return the value of the EG timer counter Status and Control reg ister as UWord16 QT SET ALTERNATIVE LOAD QT ENABLE QT DISABLE Enable disable re initializing of the counter from alternative CMPLD2 reg v v ister QT SET CAPTURE MODE QT CAPTURE DISABLED Set Input Capture Mode QT RISING EDGE QT FAL PAP LING EDGE QT BOTH ED GES QT SET COUNT DIRECTION QT COUNT UP QT COUN Select if timer counter counts up or zx T DOWN down QT SET COUNT LENGTH QT ROLL OVER QT UNTIL Select if timer counter counts up to the COMPARE AND REINIT compare value and then re initializes itself to the value specified in the load register TES DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 138 Freescale Semiconductor Inc Table 5 56 QT Driver Commands Description m 515 SET COUNT MODE QT NO OPERATION Set timer counter count mode QT COUNT RISING EDGE 5 MODE QT COUNT BOTH EDGES MODE QT GATED COUNT MODE QT QUADRATURE COUNT MODE QT SIGNED COUNT MOD E Y Y QT TRIGGERED COUNT _ MODE QT CASCADE COUNT MO QT_ONE_SHOT_MODE QT_PULSE_OUTPUT
75. GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 11 Function CANTX PullUp Disable Pin 12 Function CANRX PullUp Disable Pin 13 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 14 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 15 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high 257 define GPIO C PER INIT 0x1800U GPIO_F Configuration Pin 0 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 1 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 2 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 37 Freescale Semiconductor Inc 1 Polarity Pin 4 Func Pin 5 Func Pin 6 Func Int Int Pin 7 Func Polarity Ac Pin 8 Func Polarity Ac Int Int xf define GPIO F P as SCI_1 Config 3 Function Polarity Active GPIO Dire high TXD1 Pull RXD1 Pull tive tion tion ction Input PullU Up Disable Up Disable GPIO Dire high GPIO tive high tion GPIO tive high tion tion Dire
76. INIT 0x0000U define A 0 FRACVAL2 INIT 0x0000U define A 0 FRACVAL3 INIT 0x0000U define PWM A 0 FRACVALA INIT 0x0000U define A 0 FRACVAL5 INIT 0x0000U define A 0 DTCNTO INIT 0 00000 define 0 DTCNT1 INI 0 00000 0 INTEN INIT 0 10000 define 0 DISMAPO INIT 0 0000 Rs PWM_A_1 Configuration Debug Mode Operation Stop Wait Mode Operation Stop Load Mode End cycle Load OK No PWM Clock Enable Yes Clock Source PWM 0 clock Prescaler fclk 1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 15 Freescale Semiconductor Inc INIT register 1700 VAL1 register 1699 Fraction FRACVAL1 0 Sync source Master sync 0 Reload source 0 module Reload Frequency Every opportunity Half Cycle Reload Disable Full Cycle Reload Enable PWMA Mask Normal PWMB Mask Normal PWMX Mask Normal PWMA Output Polarity Active High PWMB Output Polarity Active High PWMX Output Polarity Active High PWMA Output enable Enabled PWMB Output enable Enabled PWMX Output enable Disabled PWMA and PWMB Pair Operation Complementary Initialize value registers Disable Value 0 Disable Valuel Disable Value 2 Disable Value3 Disable Value 4 Disable Value5 Disable Double Switching PWM23 Deadtime count 1 0 Software Controlled Output Logic 0 Logic 0 Force Initialization Enable No
77. Inc 2 51 endif _OCCS_CLKMODE 0 endif _OCCS_EXTSEL 0 switch to external clock source set PRESC 1 nop bfset Ox4 A rchlIO Pll pllcr nop nop ifdef OCCS 05 1 INIT define OSCTL TEMP2 OCCS OSCTL1 INIT 0 000 shut down internal oscillator if required bfset OSCTL_TEMP2 ArchIO Pll osctll nop nop skip_set_ext endif defined OCCS_VERSION_6 defined OCCS VERSION 7 amp amp defined SIM VERSION 7 defined SIM VERSION 8 amp amp OCCS PLLCR INIT amp 0 4 When the PLL is to be turned on it is first decided whether the code is running on real chip or in software simulator The simulator mode is identified by looking at the clock source bit field value in the PLLCR register In the simulator mode the PLL setup is skipped because the loop waiting for the PLL lock would never finish if OCCS PLLCR INIT amp 1 PLL active define PLLCR TEMP OCCS PLLCR INIT amp Oxfe interrupts off and PLL bypassed brset O ArchIO Pll pllcr skip pll lock skip PLL in simulator mode While still running from an external oscillator the PLL lock detector is activated and it is waiting until the PLL lock is detected According to appcofing h setting the required lock state is either coarse or fine Which corresponds to the PLLSR bits LCK1 and LCKO Note that the COP counter is periodically cl
78. LOW POLYNOMINA UWord16 Write the parameter value into lower L Word of the CRC Polynominal regis Y ter DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 39 5 1 6 12 bit Digital to Analog Converter DAC Driver The 12 bit digital to analog converter DAC provides a voltage reference to on chip modules or an output to a package pin It can also be used as a waveform generator to generate square triangle and sawtooth waveforms The DAC can be put in powerdown mode if needed The Table 5 12 shows module identifiers for DAC Driver Table 5 12 Identifiers for DAC Driver Module identifier 56 82 56F84xxx DAC_A DAC The Table 5 13 shows all commands dedicated for DAC Driver Table 5 13 DAC Driver Commands Cmd pParam Description 56F82xxx 56F84xxx DAC_DISABLE_FILTER NULL Disable the glitch suppression filter See more details about the filter at DAC ENABLE FILTER lt lt DAC ENABLE DAC ENABLE DAC DISAB LE Enable disable the DMA to feed the DAC output DAC ENABLE FILTER NULL Enable the glitch suppression filter on the DAC output The glitch suppres sion filter introduces a latency between the DATA Register update both manual or automatic and the actual DAC output update DAC INIT NULL Initialize DAC peripheral registers using the appconfig h INIT values DA
79. Pin 3 Function GPIO Direction Input Pull Int Polarity Active high Pin 4 Function TXD1 PullUp Disable Pin 5 Function RXD1 PullUp Disable Pin 6 Function GPIO Direction Input Pull Int Polarity Active high Pin 7 Function GPIO Direction Input Pull Int Polarity Active high Pin 8 Function GPIO Direction Input Pull Int Polarity Active high SEJ define GPIO_F_PER_INIT 0x0030U Ls SCI 1 Configuration Baudrate 9601 bps Enable Receiver Enable Enable Transmitter Enable Data word length 8 bits Parity None Polarity Loop mode Function in Wait Mode Interrupts Enable RX and TX FIFO Queues True polarity Disable RX Full Disable RX Error Disable TX Empty Disable X Empty Disable Disable Up Up Up Up Up Up Up slave Disabl Disabl Disabl Disabl Disabl Disabl Disabl SCI module enabled in Wait Mode Le Le Le Le Le Le Le Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt DSC56800EX Quick Start User s Guide Rev 2 04 2015 Disabl Disabl Disabl Disabl Disabl Disabl Disabl le le le le le le le Freescale Semiconductor Inc 6 30 RX Active Edge Disable Enable TX DMA Disable Enable RX DMA Disable
80. READ CAPTURE B1 FI NULL Return value of FIFO counter c E FO COUNT EFPWMS READ CAPTURE CYCL NULL Return Capture Value 0 2152 VALO EFPWMS_READ_CAPTURE_CYCL NULL Return Capture Value 1 viv VAL1 EFPWMS_READ_CAPTURE_CYCL NULL Return Capture Value 2 Ve se E VAL2 EFPWMS READ CAPTURE CYCL NULL Return Capture Value 3 PP E VAL3 EFPWMS READ CAPTURE CYCL NULL Return Capture Value 4 e VAL4 EFPWMS READ CAPTURE CYCL NULL Return Capture Value 5 v ar E VAL5 EFPWMS READ CAPTURE VALO NULL Return Capture Value 0 viv EFPWMS READ CAPTURE VAL1 NULL Return Capture Value 1 viv EFPWMS_READ_CAPTURE_VAL2 NULL Return Capture Value 2 EFPWMS_READ_CAPTURE_VAL3 NULL Return Capture Value 3 viv EFPWMS_READ_CAPTURE_VAL4 NULL Return Capture Value 4 viv EFPWMS_READ_CAPTURE_VAL5 NULL Return Capture Value 5 viv EFPWMS READ CAPTURE XO0 FI NULL Return value of FIFO counter 1 FO COUNT EFPWMS READ CAPTURE X1 FI NULL Return value of FIFO counter FO COUNT EFPWMS READ COUNTER REG NULL Return value from the Counter Regis Fill ter DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 61 Table 5 19 EFPWM Driver Commands ABLE FALLING_EDGE RISI NG_EDGE ANY_EDGE DSC56800EX Quick Start User s Guide Rev 2 04 2015 Description ag i
81. Read and return the Plus Side Gen eral Calibration Value 4 register as Y UWord16 ADC16 READ CLPD REG NULL Read and return the Plus Side Gen eral Calibration Value register as Y UWord16 ADC16 READ CLPS REG NULL Read and return the Plus Side Gen eral Calibration Value register as Y UWord16 ADC16 READ CV1 REG NULL Read and return value of Compare 2 Value 1 register as UWord16 ADC16 READ CV2 REG NULL Read and return value of Compare Value 2 register as UWord16 ADC16 READ OFS REG NULL Read and return the Offset register as UWord16 ADC16_READ_PLUS_SIDE_GAIN NULL Read and return the Plus Side Gain T REG register as UWord16 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 24 Freescale Semiconductor Inc Table 5 5 ADC16 Driver Command Description ag 55 iO Lre ADC16_READ_RESULT NULL Read and return the ADC data result RA register as UWord16 The return value contains the result of an ADC conversion of the channel selected by the ADC16 SET INPUT CHANNEL ioctl command ADC16 READ SC1 REG NULL Read and return value of the Status and Control register 1 UWord16 ADC16 READ SC2 REG NULL Read and return value of the Status 2 and Control register 2 UWord16 ADC16_READ_SC3_REG NULL Read and return value of the Status 2 and Control register as UWord16 ADC16_SELECT_LONG_SAMPLE_ ADC1
82. Read and return the value of the OL REG timer counter Comparator Status Con v v trol register as UWord16 QT READ COMPARE FLAG COMPARE1 FLAG QT Return the status of selected PUN COMPARE2 FLAG timer counter compare flags QT READ COMPARE REG NULL Read and return the value of the timer counter Compare register 1 as viv UWord16 QT READ COMPARE REG2 NULL Read and return the value of the timer counter Compare register 2 as UWord16 QT READ CONTROL REG NULL Read and return the value of the timer counter Control register as UWord16 QT READ COUNTER REG NULL Read and return the value of the timer counter Counter register as UWord16 QT_READ_EXT_INPUT_PIN NULL Read the current state of the external input pin after application of the Input Polarity Select IPS bit return 0 0000 v Y input pin is 0 or 0 0100 input pin is 1 QT READ FILT REG NULL Read and return the value of fiter viv Fegister DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 137 Table 5 56 Driver Commands QT_UNTIL_COMPARE_AND_REINI T or the counter continues counting past the compare value up to the binary roll over QT_ROLL_OVER Description m 515 Lre QT_READ_FLAG QT_COMPARE_FLAG QT_ Read and return the status of selected OVERFLOW FLAG QT INP timer counter flags UT_EDGE_FLAG QT_VAL_
83. Resistor Enable Register GPIO_SET_SLEW_RATE_DISABL combination of BIT_x Disable the slew rate mode of the E 0 1 15 selected GPIO pin output driver by viv modifying the content of the Slew Rate Control Register GPIO_SET_SLEW_RATE_ENABLE combination of BIT_x Enable the slew rate mode of the 0 1 15 selected GPIO pin output driver by PE modifying the content of the Slew Rate Control Register GPIO SETAS GPIO combination of BIT x Set the selected GPIO pins of the 0 1 15 port GPIO pins by modifying sly content of the Peripheral Enable Register GPIO_SETAS_INPUT combination of BIT_x Set the selected GPIO pins as an x 0 1 15 input pins by modifying the content of viv the Data Direction Register DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 89 Table 5 34 GPIO Driver Commands gt lt Description 9 8 6 GPIO SETAS OPENDRAIN combination of BIT x Set the output driver of the selected 0 1 15 GPIO pins to open drain mode by modifying the content of the Push Pull Mode Register GPIO_SETAS_OPENDRAIN combination of BIT_x Set the output driver of the selected 0 1 15 GPIO pins to open drain mode by modifying the content of the Push Pull Mode Register GPIO_SETAS_OUTPUT combination of BIT_x Set the selected GPIO pins as an 0 1 15 output pins by modif
84. Rev 2 04 2015 Freescale Semiconductor Inc 4 14 Capture Al Disable Capture BO Disable Capture Bl Disable Capture Disable Capture 1 Disable Capture A Input select Raw PWMA input Capture B Input select Raw PWMA input Capture X Input select Raw PWMA input One Shot mode enable Disable Disable Disable Edge Counter Enable Disable Disable Disable Edge Compare A Value 0 Edge Compare B Value 0 Edge Compare X Value 0 Capture Edge Select Disabled Capture Al Edge Select Disabled Capture BO Edge Select Disabled Capture Bl Edge Select Disabled Capture Edge Select Disabled Capture 1 Edge Select Disabled PWMX Double Switching Enable Disable Capture 0 Disable Capture Al Disable Capture BO Disable Capture Bl Disable Capture Disable Capture 1 Disable Source of capture DMA DMA disabled Enable DMA Write Requests For alue Registers No Output Trigger 0 Source PWM_OUT_TRIGO Output Trigger 1 Source PWM_OUT_TRIG1 su define PWM A 0 CTRL INIT OxF400U define 0 CTRL2 INIT 0x0000U define A 0 INIT INIT OxF95CU define 0 VAL1 INIT 0x06A3U define 0 VALO INIT 0 00000 define 0 VAL2 INIT 0 00000 define 0 VAL3 INIT 0 00000 define 0 VAL4 INIT 0x0000U define 0 VAL5
85. SCI flags 2 5 28 periphMemForcedRead memory force read Never optimized out Call s UWordl6 periphMemForcedRead UWord16 pAddr Arguments Table 2 30 peripbhMemForcedRead arguments pAddr in The memory address from which to read a 16 bit word Description The periphMemForcedRead macro reads a 16 bit word from the memory location addressed by parameter pAddr This macro is never optimized out Example 2 45 periphMemForcedRead macro usage periphMemForcedRead amp ArchlO Sci scisr This code reads the SCI status register to clear SCI flags 2 5 29 Miscellaneous Routines This section describes some additional routines provided by the 56800EX_Quick_Start tool DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 29 2 5 291 impyuu integer multiply unsigned 16b x unsigned 16b Call s UWord32 impyuu UWord16 unsigA UWordl6 unsigB Arguments Table 2 31 impyuu arguments unsigA in first argument unsigB in second argument Description The impyuu inline function multiplies a 16 bit unsigned integer with a 16 bit unsigned integer and returns the 32 bit unsigned integer result Returns result of multiplication unsigA unsigB Example 2 46 impyuu function usage UWordl6 varl 655350 UWordl6 var2 655350 UWord32 result result impyuu varl var2 returns 4294836225 This code multiplies variables var and var2 an
86. SET INPUT CHANNEL ADC16 xxx Select one of the ADC input channels xxx AD0 AD23 VREFH VR Note Some of the input channel EFL DEACTIVATE BAND options might not be available for all GAP TEMP_SENSOR devices or packages ADC16_SET_INT ADC16 ENABLE ADC16 DI Enable disable the conversion com SABLE plete interrupt An interrupt is asserted 2 when COCO becomes set while the AIEN is high ADC16_SET_LONG_SAMPLE_TIM ADC16_ENABLE ADC16_DI Select between long and short sample E SABLE time When long sample time is selected the sample time might be 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 26 Freescale Semiconductor Inc Table 5 5 ADC16 Driver Command Description ag LL LL Lre ADC16_SET_LOW_POWER_CFG ADC16_xxx Select between the high sample rate _ _ or the power consumption optimized Y OWER sample rate ADC16 SET RESOLUTION ADC16 MODE xxx Set the converter s resolution xxx 8BIT 10BIT 12BIT 16BI Y ADC16_SET_VOLTAGE_REFERE ADC16 SOURCE xxx Select the voltage reference source used for conversions ADC16_TEST_CALIBRATION_FAIL NULL Return a non zero value when the cal ED FLAG ibration failed and zero when passed The calibration sequence fails if the HW trigger is enabled any ADC regis Y ter is written
87. Select Disabled Capture 1 Edge Select Disabled PWMX Double Switching Enable Disable Capture 0 Disable Capture Al Disable Capture BO Disable Capture Bl Disable Capture Disable Capture 1 Disable Source of capture DMA DMA disabled Enable DMA Write Requests For alue Registers No Output Trigger 0 Source PWM_OUT_TRIGO Output Trigger 1 Source PWM OUT TRIGI define 2 CTRL INIT 0 04000 define 2 CTRL2 INIT 0 02060 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 18 define 2 OxF95CU define 2 VAL1 INIT 0x06A3U 2 VALO INIT 0x0000U A 2 VAL2 INIT 0x0000U define PWM A 2 VAL3 INIT 0x0000U define 2 VAL4 INIT 0x0000U define PWM A 2 VAL5 INIT 0x0000U A 2 FRACVAL2 INIT 0x0000U A 2 FRACVAL3 INIT 0x0000U A 2 FRACVAL4 INIT 0x0000U define A 2 FRACVAL5 INIT 0x0000U define A 2 DTCNTO INIT 0x0000U define A 2 1 INIT 0x0000U define A 2 DISMAPO INIT 0 0000 3 Configuration Debug Mode Operation Stop Wait Mode Operation Stop Load Mode End cycle Load OK No PWM Clock Enable Yes Clock Source IPBus Clock Prescaler 1 1 INIT register 0 VAL1 register 3700 Fraction FRACVAL1 0 Sync source
88. Semiconductor Inc Description 56F82xxx 56F84xxx DMA GET LINK CHANNEL 2 NULL Get the DMA channel assigned as link channel 2 The link channel number cannot be the same as the currently executing channel lt lt DMA_GET_SOURCE_ADDRESS NULL Read and return the source address used by the DMA channel DMA READ BUS ERROR DESTI NATION NULL Get the bus error on destination BED flag cleared at hardware reset or by writing a 1 to the DONE bit DMA READ BUS ERROR SOUR CE NULL Get the bus error on source BES flag cleared at hardware reset or by writing a 1 to the DONE bit DMA READ BUSY NULL Get the busy BSY bit the bit is cleared when the DMA completes the last transaction and it is set the first time that the channel is enabled after a transfer is initiated DMA READ BYTES TO BE TRA NSFERRED NULL Return number of bytes yet to be transferred for a given block DMA READ CONFIG ERROR NULL Get the configuration error CE flag A configuration error occurs when any of the following conditions occurs BCR SAR or DAR does not match the requested transfer size SSIZE or DSIZE is set to an unsupported value BCR equals 0 when the DMA receives a start condition DMA READ DCR NULL Read and return channel n DCR register DMA READ DSR BCR NULL Read and return channel n DMA DSR BCR
89. Source of FORCE OUTPUT signal Local force CTRL2 FORC Dead Time Source 23 PWM23 Dead Time Source 45 PWM45 PWM45 Initial Value Logic 0 Logic 0 PWMX Initial Value Logic 0 Reload Disable Reload Error Disable GI oo Value 0 Compare Disable Value 1 Compare Disable Value 2 Compare Disable Value 3 Compare Disable Value 4 Compare Disable Value 5 Compare Disable Capture 0 Disable Capture Al Disable Capture BO Disable Capture Bl Disable Capture Disable Capture 1 Disable Capture A Input select Raw PWMA input Capture B Input select Raw PWMA input Capture X Input select Raw PWMA input One Shot mode enable Disable Disable Disable Edge Counter Enable Disable Disable Disable Edge Compare A Value 0 Edge Compare B Value 0 Edge Compare X Value 0 Capture Edge Select Disabled DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 16 Capture Al Edge Select Disabled Capture BO Edge Select Disabled Capture Bl Edge Select Disabled Capture Edge Select Disabled Capture 1 Edge Select Disabled PWMX Double Switching Enable Disable Capture 0 Disable Capture Al Disable Capture BO Disable Capture Bl Disable Capture Disable Capture 1 Disable Sourc
90. Start User s Guide Rev 2 04 2015 2 6 Freescale Semiconductor Inc 2 4 1 5 archResetLimitBit reset limit bit Call s void archResetLimitBit void Arguments None Description The archResetLimitBit macro resets limit bit L Bit 6 in the Status Register SR Example 2 7 archResetLimitBit macro usage archResetLimitBit 2 4 1 6 archSetNoSat set no saturation mode Call s void archSetNoSat void Arguments None Description The archSetNoSat macro disables the saturation mode This macro clears the saturation SA bit Bit 4 in the Operating Mode Register OMR Example 2 8 archSetNoSat macro usage archResetLimitBit 2 4 1 7 archSetSat32 set saturation mode Call s void archSetSat32 void Arguments None Description The archSetSat32 macro sets the saturation mode This macro sets the saturation SA bit Bit 4 in the Operating Mode Register OMR Example 2 9 archSetSat32 macro usage archSetSat32 2 4 1 8 archSet2CompRound set two s complement rounding mode Call s void archSet2CompRound void DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 7 Arguments None Description The archSet2CompRound macro sets the two s complement rounding mode This macro sets the rounding R bit Bit 5 in the Operating Mode Register OMR Example 2 10 archSet2CompRound macro usage archSet2CompRound 2 4 1 9 archSetConvRo
91. The memory address DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 22 Freescale Semiconductor Inc Description The periphSafeBitClear macro clears the selected bits and keeps value of the bit flags which are cleared by write one in a peripheral memory location addressed by parameter pAddr The FlagGroupMask specifies all flags which are cleared by write one The Mask value specifies bit bits to be cleared Caution TBD Example 2 35 periphSafeBitClear macro usage periphSafeBitClear 0x0002 0x0010 0x0004 amp ArchIO HscmpA scr This code disables the falling edge HSCMP A module The rising edge and falling edge interrupt flags are not cleared 2 5 19 periphSafeBitSet Set bits and keep value of bit flags which cleared by write one Call s void periphSafeBitSet UWordl6 FlagGroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 21 periphSafeBitSet arguments FlagGroupMask in Group mask of bit flags which are cleared by write one Mask in bit mask pAddr in The memory address Description The periphSafeBitSet macro sets the selected bits and keeps value of the bit flags which are cleared by write one in a peripheral memory location addressed by parameter pAddr The FlagGroupMask specifies all flags which are cleared by write one The Mask value specifies bit bits to be set This macro uses a single instruction to execute the operation and allows only constants
92. This switches data between legacy DSC 16bit FlexCAN implementation and the new 32bit implementation FCANMB_GET_DATAPTR NULL This command is not implemented intentionally The behavior would not be backward compatible with the same command implemented in 16bit FlexCAN module driver To get access to frame data use the GET DATAPTR32 com mand and be aware of different data byte endianness format GET DATAPTR32 NULL Get a pointer to data buffer of the MB as a pointer to UWord32 word Note that the endianness of the data regis ter is different than the one of the CAN bus Use the FCANMB REORDER BYTES com mand to switch between different data formats DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 83 5 1 12 Flash Memory Module Driver The driver has only 56F82xxx devices The flash memory module includes the following accessible memory regions e Program flash memory for vector space and code store Flash memory is ideal for single supply applications permitting in the field erase and reprogramming operations without the need for any external high voltage power sources The flash memory module includes a memory controller that executes commands to modify flash memory contents An erased bit reads 1 and a programmed bit reads 0 The programming operation is unidirectional it can only move bits from the 1 st
93. VECTOR ADDR 102 gpio f isr define INT PRIORITY LEVEL 102 LEVELO define INT VECTOR ADDR 105 gpio c isr define INT PRIORITY LEVEL 105 LEVELO Ka GPIO_C Configuration Pin 0 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 1 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 2 Function GPIO Direction Input PullUp Disable Interrupt Enable Int Polarity Active high DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Pin 3 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 4 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 5 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 6 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 7 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 8 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 9 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 10 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active
94. a base address of JTAG register space As the JTAG registers are located at the same address on all 56F82xxx and 56F84xxx processors this value needs not to be defined and its default value is OxFFFFOO FMSTR COMM BUFFER SIZE integer Defines the size of the FreeMASTER communication buffer This buffer is used to store the frames being received or frames to be sent over the SCI or JTAG If this constant is undefined or is defined as zero a suf ficient memory buffer is allocated by the driver Default 0 automatic FMSTR COMM RQUEUE SIZE integer The size of additional receive queue for short interrupt processing Needed only in FMSTR SHORT INTR mode Default 32 Application Commands DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 6 2 FreeMASTER Communication Configuration Items for appconfig h Continued SYMBOL TYPE DESCRIPTION FMSTR USE APPCMD numeric zero non zero When defined non zero this constant enables a sup port for FreeMASTER Application Commands Default 0 false FMSTR APPCMD BUFF SIZE integer A size of buffer which will receive the Application Com mand parameters The parameters are stored in the buffer until the application code processes and acknowledges the application command Default 16 FMSTR MAX APPCMD CALLS integer A number of different Application Commands for which
95. address once it is set e g by the INIT call SET ADDRESS EXTENSION UWord16 value of the 10bit address 8 Set the upper three bits of the slave address in the 10 bit address scheme SET ADDRESS EXTENSION MODE n 7 10 Set the number of bits used for the slave address SET TRANSFER ENABLE IIC DISABLE Enable disable the DMA function see documentation how FAST ACK mode affects the DMA receive and transmit functions SET FAST DISABLE Enable disable the fast set up ACK NACK response SET GENERAL CALL ADDRE SS DISABLE Enable disable the general call address IIC_SET_GLITCH_FILTER UWord16 value 0 disable or 1 7 enable Enable disable the glitch filter The value 1 7 represents the number of fil ter glitches up to width of n bus clock cycles IIC_SET_HIGH_DRIVE_PADS ENABLE IIC DISABLE Enable disable the high drive capabil ity of the 2 pads SET HIGH TIMEOUT2 INTER RUPT DISABLE Enable disable the high timeout 2 interrupt DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 97 Table 5 38 1 Driver Commands xxx STOP START
96. addressed by parameter pAddr Example 2 42 periphBitChange macro usage periphBitChange 0xC000 amp ArchIO PortB dr This code complements bits 15 and 14 in the Port B Data Register DR 2 5 26 periphBitTest test selected bits Call s UWordl6 periphBitTest UWord16 Mask UWordl6 pAddr Arguments Table 2 28 periphBitTest arguments Mask in Bit mask pAddr in The memory address Description The periphBitTest macro tests the selected bits if they are set in a memory location addressed by parameter pAddr Example 2 43 periphBitTest macro usage if periphBitTest 0 8000 amp ArchlIO TimerD ch0 scr periphBitClear 0x8000 amp ArchIO TimerD ch0O scr This code checks if Timer Compare Flag Bit 15 in the DO Status and Control Register SCR is set DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 28 Freescale Semiconductor Inc 2 5 27 periphMemDummyRead memory dummy read Call s void periphMemDummyRead UWord16 pAddr Arguments Table 2 29 periphMemDummyhRead arguments pAddr in The memory address from which to read a 16 bit word Description The periphMemDummyRead macro reads a 16 bit word from the memory location addressed by parameter pAddr The result is thrown away Example 2 44 periphMemDummyRead macro usage periphMemDummyRead amp ArchlO Sci scisr This code reads the SCI status register to clear
97. and return the nonzero value if the interrupt which is currently being sent to the processor core INTC_GET_IPL_n_RAW given interrupt use NULL Return two bit IPL value for given PAN as parameter interrupt INTC GET PENDING FLAG UWord16 value of the Read and return the bit in the INTC selected interrupt Pending Register for requested inter viv rupt INTC_INIT NULL Initialize the INTC peripheral registers using the appconfig h _INIT values DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 101 Table 5 40 INTC Driver Commands gt lt Description ag LL INTC_INIT NULL Initialize the INTC peripheral registers using the appconfig h _INIT values INTC_INTERRUPTS INTC_ENABLE INTC_DISAB Enable disable the interrupt process PES LE ing by the INTC module INTC READ CONTROL REG NULL Read and return the immediate value of the INTC Control Register INTC_READ_IRQPINS combination of INTC_IRQxxx Read and return the immediate state of the selected external interrupt pins as UWord16 INTC_SELECT_EDGE_MODE combination of INTC_IRQxxx the selected interrupts to be an sly falling edge sensitive INTC_SELECT_LEVEL_MODE combination of INTC_IRQxxx the selected interrupts to be S NT low level sensitive INTC_SET_FASTINTO NUL
98. are cleared by write one in a peripheral memory location addressed by parameter pAddr The FlagGroupMask specifies all flags which are cleared by write one All bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared Caution It might seem this macro is the proper way how to set the group of bits to certain value as there are no intermediate invalid values written in the target memory location However it is quite dangerous to use this macro when interrupts may occur between the read and write operations If the interrupt service routine would write the other portion of the target memory location the written value could be overwritten back with its previous state by the write accumulator operation of periphBitGrpSet32 Example 2 41 periphSafeBitGrpSet macro usage periphSafeBitGrpSet32 0 080808080 0x00F000000 1 amp ArchIO dma reqc This code selects the request 1 as the DMA source DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 27 2 5 25 periphBitChange change selected bits Call s void periphBitChange UWord16 Mask UWordl6 pAddr Arguments Table 2 27 periphBitChange arguments Mask in Bit mask pAddr in The memory address Description The periphBitChange macro complements the selected bits in a memory location
99. as GroupMask and Mask arguments If the application requires the variable as argument the periphSafeBitSetVar macro must be used instead Example 2 36 periphSafeBitSet macro usage periphSafeBitSet 0x0002 0x0004 0x0010 amp ArchlO HscmpA scr This code enables the rising edge HSCMP A module The rising edge and falling edge interrupt flags are not cleared DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 23 2 5 20 periphSafeBitSetVar Set bits and keep value of bit flags which cleared by write one Call s void periphSafeBitSetVar UWord16 FlagGroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 22 periphSafeBitSetVar arguments FlagGroupMask in Group mask of bit flags which are cleared by write one Mask in bit mask pAddr in The memory address Description The periphSafeBitSetVar macro sets the selected bits and keeps value of the bit flags which are cleared by write one in a peripheral memory location addressed by parameter pAddr The FlagGroupMask specifies all flags which are cleared by write one The Mask value specifies bit bits to be set Caution It might seem this macro is the proper way how to set the group of bits to certain value as there are no intermediate invalid values written in the target memory location However it is quite dangerous to use this macro when interrupts may occur between the read and write operations If
100. bit integer and 3 bit fractional baud rate selection Programmable 8 bit or 9 bit data format Separately enabled transmitter and receiver Separate receiver and transmitter DSC core interrupt requests Programmable polarity for transmitter and receiver Two receiver wake up methods idle line or address mark Clockless receiver wake up on active input edge Interrupt driven operation with multiple flags Transmitter empty Transmitter idle Receiver full Receiver overrun Receiver idle Receiver input edge Noise error Framing error Parity error Receiver framing error detection Hardware parity checking 1 16 bit time noise detection The Table 5 57 shows module identifiers for SCI Driver Table 5 57 Identifiers for SCI Driver Module identifier 56 82 56F84xxx SCI_O v v 1 Y SCI 2 Y Table 5 58 shows all commands dedicated for SCI Driver Table 5 58 SCI Driver Commands Cmd pParam Description 56F82xxx 56F84xxx SCI BUFFERED RX SCI ENABLE Enable disable the read operations if SCI DISABLE the operates in a BUFFERED mode The buffer pointers are initial ized and interrupts enabled lt lt DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 142 Freescale Semiconductor Inc Table 5 58 SCI Driver Commands
101. bits of PLL Divide By register to the value 10 Other bits in the register are not affected but see Caution above 2 5 15 periphBitGrpSet32 set bit group to given value Call s void periphBitGrpSet UWord32 GroupMask UWord32 Mask UWord16 pAddr Arguments Table 2 17 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpSet32 macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared This variant uses the accumulator and read modify write instructions to accomplish the requested operation The memory location is first read to accumulator the bfclr and bfset instructions are performed on accumulator and the result value is then written back to memory location DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 20 Freescale Semiconductor Inc Caution It might seem this macro is the proper way how to set the group of bits to certain value as there are no intermediate invalid values written in the target memory location However it is quite dangerous to use this macro when interrupts may occur between the read and write operations If the interrupt service routine would write the othe
102. bus transfer error EWM INIT NULL Initialize the EWM External watch dog monitor peripheral registers viv using the appconfig h INIT values EWM READ COMPAREH REG NULL Read and return the value of the Com AN pare High Register EWM READ COMPAREL REG NULL Read and return the value of the Com 21 pare Low Register EWM_SELECT_CLK EWM Select the low power clock sources for xxx ROSC_8M XTAL_OSC running the EWM counter Register EWM BUS CLK EWM ROS can be written only once afterthe CPU v v 32K reset Modifying these bits more than once generates a bus transfer error DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 75 Table 5 23 EWM Driver Commands Cmd pParam Description 56F82xxx 56F84xxx EWM_SET_PRESCALER UWORD 16 value 0 255 Set the EWM the prescaler value Call this command before enabling the EWM The register can be written to only once after the CPU reset Modify ing these bits more than once gener ates a bus transfer error lt lt EWM_WRITE_COMPAREH_REG UWord16 value 0 255 Set the maximum time to service the EWM counter The expiration happens only if EWM counter is greater than viv CMPH This register can be written only once after the CPU reset EWM_WRITE_COMPAREL_REG UWord16 value 0 255 Set the minimum time to service the EWM counter This register can be viv written only once after the CPU reset EWM_WRITE_SERVICE_REG UWord16 val
103. clear such events by using the MSCAN_READ_EINT_FLAGS return value as a parameter DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 106 Freescale Semiconductor Inc Table 5 44 MSCAN Driver Commands Cmd pParam Description 56F82xxx 56F84xxx MSCAN_READ_ERINT_FLAGS NULL Return a value of the Error and Receive interrupt flags This command can be used to poll the state of the error and receiver interrupts The value returned by this command may be used as a parameter to the MSCAN_CLEAR_ERINT_FLAGS ioctl command to acknowledge and clear the polled interrupt sources This com mand may also be used for read clear sequence within the interrupt service routine if this routine is used to handle both the error and receive interrupts Note that this command is not suitable for read clear sequence within the interrupt service routine when two dif ferent service routines exist for the error and receive interrupts If this is the case use the MSCAN_READ_EINT_FLAGS and MSCAN_CLEAR_EINT_FLAGS com mands for the error interrupt and the MSCAN_CLEAR_RINT_FLAGS com mand for the receiver interrupt MSCAN_READ_TINT_FLAGS NULL Get the transmitter interrupt status all TXEn bits MSCAN_RECOVER_BUSOFF_STA TE NULL Request a recovery from the bus off state This command needs to be used to recover from the bus off state if manual bus off recovery mode was configured
104. enabled globally in the core Status Register SR INIT NULL Initialize the peripheral registers ANT using the appconfig h INIT values DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 95 Table 5 38 1 Driver Commands Cmd pParam Description 56F82xxx 56F84xxx IIC_MASTER_SLAVE_MODE IIC MASTER IIC Select the mode the IIC module oper ates in When used as a master mode in a single master application this command may be used once after the initialization to set the Master mode In a multi master application the IIC is typically set to Slave listen mode by default and is momentarily switched to the Master mode when needed READ ADDRESS2 REG NULL Read and return the IIC Bus Address Register 2 as UWord16 READ CONTROL REG NULL Read and return the IIC Bus Control Register as UWord16 READ CONTROL2 REG NULL Read and return the IIC Bus Control Register 2 as UWord16 READ DATA NULL Read and return the fetched byte received from the bus by directly reading the IIC Data I O Register Typ v v ically reading of the byte is done in the interrupt service routine READ FREQ DIV REG NULL Read and return the Fre IE quency Divider Register as UWord16 IIC_READ_GLITCH_FILTER_REG NULL Read and return the Program mable Input Glitch Filter Register as viv
105. example of the full driver configuration file Such a file needs to be used and renamed to freemaster_cfg h in case the FreeMASTER driver is extracted and used outside the DSP56F800EX Quick Start environment freemaster private h Internal header file used by all driver source code The compile time verification of the configuration macros is done in this file Also the default values of undefined configuration values are defined here freemaster 56F8xxx c 56F82xxx and 56F84xxx hardware specific functions are implemented in this file freemaster 56F8xxx h 56F82xxx and 56 84 hardware specific macros and inline functions are in this file freemaster protocol c Implements the FreeMASTER protocol decoder which is independent on the communication interface used freemaster protocol h Internal header file which contains the FreeMASTER protocol constants freemaster serial c Physical SCI and interface is handled in this file The protocol decoder is invoked from this file when a valid FreeMASTER message is received This file also handles the response transmission back to the PC freemaster appcmd c Implementation of the FreeMASTER Application Commands freemaster rec c FreeMASTER Recorder implementation freemaster scope c FreeMASTER Oscilloscope implementation freemaster tsa c Target side Addressing TSA implementation freemaster tsa h TSA header file which is indirectly included in the user applicat
106. flags Y BOFFINT ERRINT WAK INT ITWRNINT RWRNINT FCAN CLEAR BOFF INT NULL Clear BusOff interrupt flag Y DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 79 Table 5 25 FCAN Driver Command FCAN_SET_RX14MASK_RAW register format Set MB14 RX mask register directly Description ag 55 re ive FCAN_CLEAR_ERR_INT NULL Clear Error interrupt flag FCAN_CLEAR_WAKE_INT NULL Clear WakeUp interrupt flag Y FCAN CLEAR RX WARNING INT NULL Clear Rx Warning Interrupt flag Y FCAN CLEAR TX WARNING INT NULL Clear Tx Warning Interrupt flag Y FCAN MBINT ENABLE UWord16 with MB bits or Enable selected MB interrupts combination of FCAN_MBINT_x x 0 MAXMB FCAN_MBINT_DISABLE UWord16 with MB bits or Disable selected MB interrupts combination of FCAN_MBINT_x x 0 MAXMB FCAN READ MBINT FLAGS NULL Get all MB interrupt flags Y FCAN CLEAR MBINT FLAGS UWord16 with MB bits or Clear selected MB interrupts combination of FCAN_MBINT_x x 0 MAXMB FCAN_SET_RXMGMASK UWord32 mask value Set Global RX mask which affects the optionally combined with MBO MB13 Logic ones in the mask FCAN ID EXT or determines bits which are compared FCAN ID RTR flags in ID filtering process Logic zeros identify don t care bits FCAN SET RXMGMASK V UWord32 mask value Set Global RX mask implemented as Y opti
107. for the MSCAN module and the bus off state is detected using the MSCAN_TEST_BUSOFF_HOLD command MSCAN SELECT NEXT TXBUFF NULL Find an empty TX buffer select it into address space and return its bit returns 0 when no buffer is available DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 107 Table 5 44 MSCAN Driver Commands Description ag 5 ive MSCAN_SELECT_TXBUFF combination of Look for an empty transmit buffer s MSCAN_TXBUFFERxxx from the ones specified by a parame xxx 0 1 2 or ter value If at least one empty buffer MSCAN_ANY_TXBUFFER is found it is selected mapped to the MSCAN peripheral space and made available for the CPU access A flag 2 identifying such a winning buffer is then returned to the caller The zero value is returned when no of the spec ified transmit buffers is empty In this case the buffer mapping is not changed MSCAN_SET_ACC_IDR_16_0 UWord16 portion of the ID Set 16bit acceptance ID 0 The value includes the RTR SRR and IDE bits MSCAN_SET_ACC_IDR_16_1 UWord16 portion of the ID Set 16bit acceptance ID 1 The value 2 acceptance value includes the RTR SRR and IDE bits MSCAN_SET_ACC_IDR_16_2 UWord16 portion of the ID Set 16bit acceptance ID 2 The value 2
108. h _ INIT val viv ues HSCMP_INT_FALLING_EDGE HSCMP ENABLE HSCMP Enable disable the falling edge inter PE DISABLE rupt DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 91 Table 5 36 Driver Commands G_EDGE Description ag 5 HSCMP_INT_RISING_EDGE HSCMP ENABLE HSCMP Enable disable the rising edge inter DISABLE rupt HSCMP_MINUS_INPUT HSCMP_INx 0 7 Select the negative input of the com XS parator HSCMP MODULE HSCMP ENABLE HSCMP Enable disable the HSCMP module 2032 DISABLE HSCMP PASS THROUGH MODE HSCMP_ENABLE HSCMP__ Enable disable the MUX pass through 21 DISABLE mode HSCMP_PLUS_INPUT 5 x 0 7 Select the positive input the com parator HSCMP_READ_FILT_COUNTER NULL Read and return the value of the filter sly counter HSCMP_READ_FILT_REG NULL Read and return the value of the Out put Filter register as UWord16 HSCMP REFERENCE SELECT HSCMP_VIN1IN Select the supply voltage for the com PE HSCMP VIN2IN parator reference source HSCMP SET HIGH SPEED HSCMP ENABLE HSCMP _ If enabled the comparator is put to the DISABLE high speed comparison mode If dis 221122 abled the comparator is put to power saving mode HSCMP_SET_INVERT HSCMP ENABLE HSCMP Enable disable the logic level inverter v DISABLE at the high speed comparator output HSC
109. hazardous dangerous to life or potentially life threatening environments requiring fail safe performance such as in the operation of nuclear facilities aircraft navigation or communication systems air traffic control direct life support machines or weapons systems DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 8 4 CHOICE OF LAW VENUE LIMITATIONS You agree that the statutes and laws of the United States and the State of Texas USA without regard to conflicts of laws principles will apply to all matters relating to this Agreement or the Software and you agree that any litigation will be subject to the exclusive jurisdiction of the state or federal courts in Texas USA You agree that regardless of any statute or law to the contrary any claim or cause of action arising out of or related to this Agreement or the Software must be filed within one 1 year after such claim or cause of action arose or be forever barred PRODUCT LABELING You are not authorized to use any Freescale trademarks brand names or logos ENTIRE AGREEMENT This Agreement constitutes the entire agreement between you and Freescale regarding the subject matter of this Agreement and supersedes all prior communications negotiations understandings agreements or representations either written or oral if any This Agreement may only be amended in written form executed by you and Freescale SEVERABILITY If any provision of this
110. high Pin 11 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 12 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 13 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 14 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 15 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high define GPIO C PER INIT 0x0000U define GPIO C IENR INIT 0x0004U Configuration Pin 0 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int Polarity Active high Output Mode Push pull Pin 1 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int Polarity Active high Output Mode Push pull Pin 2 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int Polarity Active high Output Mode Push pull Pin 3 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int Polarity Active high Output Mode Push pull Pin 4 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int Polarity Active high Output Mode Push pull Pin 5 Function GPIO Direction Output Init Value Lo
111. in Wait Mode Le Le Le Le Interrupt Interrupt Interrupt Interrupt DSC56800EX Quick Start User s Guide Rev 2 04 2015 Disab Disab Disab Disab le le le le Freescale Semiconductor Inc 6 38 Chapter 7 Graphical Configuration Tool 7 1 Introduction This section describes the functionality of the Graphical Configuration Tool GCT for the 56F82xxx and 56F84xxx family of Digital Signal Controllers The Graphical User Interface GUI settings file formats and the import export rules will be described The features and functionality of on chip peripheral modules are described in the MCS6F8xxxx Reference Manual GCT enables to create a static configuration of on chip peripheral modules in an easy to use graphical environment A graphical representation exists for all control bits or registers of each peripheral module On the other hand the status bits or bit fields and other run time only registers are not covered by GCT Typically the run time registers are accessed indirectly by the ioctl calls described in previous chapters 7 1 1 Features Main GCT features e Easy to use graphical environment Convenient navigation to individual peripheral modules Possibility to integrate into CodeWarrior IDE 10 3 or higher version Immediate register values view Configuration warnings list Supported peripheral modules e Processor block view package pinout v
112. input 2 SET OUT PWMA1 EXT INPUT Set 0 21 input 2 SET OUT 2 EXT A INPUT Set 26 input 2 _ 5 2 XBAR_A_INPUT_xxx Set XBAR_A_OUT26 input 2 _ DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 170 Freescale Semiconductor Inc Table 5 64 Driver Commands x x Description ag 6 lt i i XBAR A SET OUT PWMA2 EXT XBAR A INPUT xxx Set OUT22 input 2 A SET OUT 2 EXT XBAR A INPUT xxx Set XBAR A OUT22 input SET OUT EXT Set XBAR_A_OUT27 input 2 _SYNC XBAR A SET OUT PWMAS EXT XBAR A INPUT xxx Set A OUT27 input 2 _SYNC XBAR A SET OUT PWMAS EXT XBAR A INPUT xxx Set A OUT23 input 2 A SET OUT EXT Set XBAR_A_OUT23 input SET OUT PWMAB EXT XBAR A INPUT xxx Set A OUT28 input 2 _CLK XBAR A SET OUT PWMAB FAU XBAR A INPUT xxx Set A OUT29 input 2 LTO XBAR A SET OUT PWMAB FAU XBAR A INPUT xxx Set A OUT30 input 2 LT1 XBAR A SET OUT PWMAB FAU XBAR A INPUT xxx Set
113. interrupt service routine ISR When this interrupt occurs the JSR instruction is executed and the program control is passed to the ISR The program memory containing the JSR instructions with the addresses of the ISR is called interrupt vector table The interrupt vector table might be located at base address 0x0000 During the code execution the interrupt vector table base address can be changed by modifying the VBA register of interrupt controller unit INTC the 56800EX Quick Start tool the full interrupt vector table is always located at address 0x0000 The register is set to zero during the startup code See Section 2 1 1 on page 2 for closer description of the booting process In the 56800EX Quick Start tool the interrupt vector table is implemented in C code which enables to effectively use the C preprocessor The special macros defined in the global application configuration file appconfig h can be used to setup the interrupt vector and to assign the interrupt priorities The interrupt controller and its configuration are described in more details later in Section 2 6 1 2 Interrupt Processing Flow Figure 2 2 shows an interrupt processing flow The 56800EX Quick Start tool does not provide any intermediate step when calling the ISR When an interrupt occurs the currently executed program is interrupted and the JSR instruction from the interrupt vector table is fetched Executing the JSR instruction results in the
114. intrinsics 56800E h is included in core h header file if the macro MWERKS is defined 2 6 Interrupts This section describes interrupt processing and interrupt configuration using the 56800EX Quick Start tool For detailed information on interrupts and interrupt processing for the 56F800EX please see the DSP56800E and DSP56800EX Reference Manual and the target processor s Reference Manual 2 6 1 Processing Interrupts An interrupt is an event that is generated by a condition inside the microcontroller or from external sources When such event occurs the interrupt processing transfers control from the currently executing program to an interrupt service routine ISR with the ability to later return to the current program upon completion of the ISR Among the main uses of interrupts we can have data transfers between microcontroller memory and a peripheral device or begin of execution of an algorithm upon reception of a new sample An interrupt can also be used for example to exit the microcontroller s low power wait processing state 2 6 1 1 Interrupt Vector Table The interrupt system on 56F800E can be defined as vectored Each interrupt source has its own program memory location at a fixed address to which program control is passed when an interrupt occurs This DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 32 Freescale Semiconductor Inc program memory location must contain JSR instruction with the address of the
115. invalid value ones already set but zeroes not yet cleared Example 2 26 periphBitGrpRSVar macro usage periphBitGrpRSVar 0x0F00 0 0100 amp ArchIO Adcl adctll This code enables the High Limit exceeded interrupt if the current result value is greater than the high limit Other bits in the register are not affected 2 5 10 periphBitGrpRS32 set bit group to given value Call s void periphBitGrpRS32 UWord32 GroupMask UWord132 Mask UWordl16 pAddr Arguments DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 16 Freescale Semiconductor Inc Table 2 12 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpRS32 macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected These bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared The RS variant uses two non interruptible instructions bfclr and bfset to accomplish the requested operation The bfcir first clears the zero bits in the destination location and bfcir then sets the one bits there Caution This macro is the optimal way how to set the specified group of bits to given value However it must be kept in mind that during the short time between these two bit
116. is recommended to enable this feature Default 1 true FMSTR_USE_WRITEMEM numeric zero non zero When this constant is defined as a non zero value the support for Write Memory feature is implemented It is recommended to enable this feature Default 1 true FMSTR_USE_WRITEMEMMASK numeric zero non zero When this constant is defined as a non zero value the support for Masked bit wise Memory Write feature is implemented It is recommended to this feature Default 1 true Variable Access subset of Memory Access features implemented for backward compatibility only FMSTR_USE_READVAR FMSTR_USE_WRITEVAR numeric zero non zero numeric zero non zero When this constant is defined as a non zero value the support for Read Variable feature is implemented This command enables a read access to 1 2 or 4 byte vari ables This functionality is a subset of the Read Mem ory feature Comparing it with the Read Memory feature there is one byte saved on the communication line Default 0 false When this constant is defined as a non zero value the support for Write Variable feature is implemented This command enables a write access to 1 2 or 4 byte vari ables This functionality is a subset of the Write Mem ory feature Comparing it with the Write Memory feature there is one byte saved on the communication line Default 0 false DSC56800EX Quick Start User
117. kk kCkCk Ck k ck k ck k ck k ck k ck ck ck ck ck ck kc kk File Name appconfig h Description file for static configuration of the application initial values interrupt vectors A A kc k ck k ck k ck k ck k ck k ck ck ck ck ck ck ck oko f ifndef _ APPCONFIG define _ APPCONFIG kc k k ck kckck ck k ck ck ck k ck ck ck ck ck K File generated by Graphical Configuration Tool Thu 18 Apr 2013 10 30 51 Ck CK ck ck ck ck Ck Sk ck Ck ck Ck Ck Ck Ck Sk ck Ck Sk ck kk ck kk Ck ck KK KKK KKK KKK ck kk ck kk kk ck kk ck kk kk ck kk Sk kk ko kk kk Sk kk ck kc kc KKK define MC56F82748 define EXTCLK 8000000L define APPCFG_DFLTS_OMITTED 1 define APPCFG_GCT_VERSION 0 020602001 occs Configuration Use Factory Trim Value Yes DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 38 Freescale Semiconductor Inc Enable internal 32 kHz oscillator No Power Down crystal oscillator Yes Core frequency 50 MHz vco frequency 200 MHz Loss of lock interrupt 0 Disable Loss of lock interrupt 1 Disable Loss of reference clock Interrupt Disable SEA define OCCS CTRL INIT 0x0081U define OCCS DIVBY INIT 0x2018U define OCCS USE FACTORY TRIM 1 define OCCS_USE_FACTO
118. memory locations amp compare 1 memory is filled with test value 0XAAAA OxAAAA OxAAAA OxAAAA OxAAAA OxAAAA OxAAAA 2 Each memory location is read and compared with written value OxAAAA OxAAAA OxAAAA OxAAAA OxAAAA T TESTI read amp compare with OXAAAA 3 Another test value 0x5555 is written Then two consecutive locations are read Both locations are read TEST2 the newly written location is read amp compared with 0x5555 the second location should still contain the previous value OxAAAA Figure 2 3 Memory Checking Process In case if any of the three tests fails the application execution is halted by debughit and stop instructions The compile time warning is issued when the internal memory checking is activated in targets that do not use the internal memory DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 53 internal memory test ifdef INTXRAM CHECK ENABLED ifndef TARGET DATA INTRAM warning Internal Memory Checking is active but variables go elsewher move l 4 Linternal RAM addr r1 memory pointer move l 4 Linternal RAM size r2 memory size move w CONFIG INTRAM CHECKVALUE1 x0 x0 write test value 1 move w CONFIG INTRAM CHECKVALUE2 0 yO write test value 2 move w 0 b b020 bl will be used as b rep r2 move w 0
119. mode i e the mode of operation for the OFLAG out put signal QT SET OUTPUT POLARITY QT NORMAL POLARITY Q T INVERTED POLARITY Set the timer counter output signal polarity QT SET PRIMARY SOURCE QT COUNTERO INPUT COUNTER1 INPUT COUNTER2 INPUT QT_COUNTER3_ INPUT QT_COUNTERO_OUTPUT QT_COUNTER1_OUTPUT QT_COUNTER2_OUTPUT QT_COUNTER3_OUTPUT QT_IPBUS_DIV_1 QT IPBUS DIV 2 QT IPBUS DIV 4 QT IPBUS DIV 8 QT IPBUS 16 QT IPBUS 32 QT IPBUS 64 QT IPBUS 128 Set primary count source of timer counter QT SET RELOAD ON CAPTURE QT SET SECONDARY SOURCE DISABLE COUNTERO INPUT COUNTER 1 INPUT COUNTER2 INPUT COUNTERS3 INPUT Enable disable reload of the counter on a capture event Set secondary count source of timer counter QT TEST LAST COUNT DIRECTI ON NULL Return the direction of the last count QT WRITE CMP STATUS CONT ROL REG UWord16 Write the parameter value into the timer counter Comparator Status Con trol register QT WRITE COMPARE REG UWord16 Write the parameter value into the timer counter Compare register 1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 140 Freescale Semiconductor Inc Table 5 56 Driver Commands
120. n Dac 5 142 Identifiers tor SP aer ERUNT RUE DEM er EPI PORC EET 5 148 SPI Driver CommandS 5 148 ldentitiers 5 152 aro dE PET 5 152 Identifiers for ABAM DONVBE sei iaa daas iiia lada dtd baa dnce b bd adt 5 165 XBAR Driver Commande 5 165 Free MASTER Driver Interrupt 6 3 FreeMASTER Communication Configuration Items for appconfig h 6 5 153 PPE 05 c TTT 6 25 MISIO Y Eo bares Benef R 9 1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor ix Figure Number N Ss 1 1 I 1 1 1 I 1 1 FWD 7 8 Figures Title MIR D External Tool Configurations E9381 0 0 c Y Build Before LAUNCH CX T jo Mt impon Dialog Root Directory Selection Drag amp Drop CodeWarrior Project File Boot OC B a Processing ec Memory Checking Process cuiua etapa tna atat
121. name The type must be defined typedef before the TSA table entry references it 9 member Structure member name without the dot at the beginning The parent structure name is specified as a separate parameter in the FMSTR 5 MEMBER macro DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 24 Structure member entries 5 5 MEMBER must immediately follow the parent structure entry FMSTR_TSA_STRUCT order to write protect variables in the FreeMASTER driver FMSTR TSA RO VAR FMSTR USE TSA SAFETY needs to be defined non zero in the configuration file Despite of its name the 5 TSA STRUCT macro may also be used to describe union data types Table 6 3 TSA Type Constants CONSTANT Description FMSTR TSA UINT8 FMSTR TSA UINT16 FMSTR TSA UINT32 FMSTR TSA UINT64 1 2 4 byte unsigned integer type Use it for both the standard C language types like unsigned char unsigned short or unsigned long and the user defined types like UWord8 UWord16 or UWord32 8 byte integer values are not used on 56F82xxx and 56F84xxx platform FMSTR TSA SINT8 FMSTR TSA SINT16 FMSTR TSA SINT32 FMSTR TSA SINT64 1 2 4 byte signed integer type Use it for both the standard C language types like char short or long and the user defined types like Word8 Word16 or Word32 8 byte integer values are not used on 56F82xxx and 56F84xxx platform
122. of the MC56F82748EVM project Memory Used EVM Data Pa Target Name Board Target Description 9 Code Boot Data Initial Constant jum 3 P pers Location Data Data FLASH_SDM Small pFlash 0x0000 Int xRAM Int Int n a Stand Alone application 0 0000 0 0000 xRAM FLASH_LDM Large pFlash 0x0000 Int xRAM Int Int n a Stand Alone application 0 0000 0 0000 xRAM There is a different linker command file LCF for each target which defines the destination memory ranges used by the linker Although the syntax of the LCF and C header files are completely different The LCF for each target is also used as prefix header file in its target configuration The macros defined in the LCF identify the target for further conditional compilation of the project source files The trick which enables using a file with the LCF syntax as a header file is shown on Example 2 52 It successfully exploits the fact that the sign is treated as a start of comment line in LCF syntax so the C like define statements do not cause the LCF syntax errors On the other side the if 0 endif block excludes the LCF part of the file from C compilation Example 2 52 Internal_PFlash_SDM cmd linker command file include version h include hawkcpu h define TARGET SDM Small Data Model define TARGET CODE PFLASH Code located in internal flash
123. operations the target memory location goes through the third state where the bit group might contain invalid value ones already set but zeroes not yet cleared Example 2 27 periphBitGrpSR macro usage periphBitGrpRS32 0x00000007 3 amp ArchlO FCan ctrl1 This code set the length of the Propagation Segment in the bit time The valid programmable values are 0 7 This field can be written only in Freeze mode because it is blocked by hardware in other modes Other bits in the register are not affected 2 5 11 periphBitGrpZS set bit group to given value Call s void periphBitGrpZs UWord16 GroupMask UWordl16 Mask UWordl16 pAddr Arguments Table 2 13 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpZS macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 17 This macro uses a single instruction to execute the operation and allows only constants as GroupMask Mask arguments If the application requires the variable as argument the periphBitGrpZS Var macro must be used instead Exam
124. registers An example of a higher functionality are commands which perform the mathematical calculations for data scaling to fit the results into the desired data range Specifically a higher functionality is exemplified by recounting of the PWM duty cycle in percentage of the actual value to be written to the PWM Value register Example 5 1 Implementation details Figure 5 1 is intended to illustrate the macro expansion process In this example each corresponding item is represented by its matching color Figure 5 1 Macro Expansion Process ioctl command general syntax ioctlh module ID cmd name cmd spec param Real example iocti PWM SET MODULO 0x30ff Implementation Common include file periph h define ioctl id cmd pParams ioctl cmd id pParams On chip driver include file pwm h define PWM amp ArchIO PwmA i e base amp module ID Oxf140 define ioctIPWM SET MODULO pPwmBase param pPwmBase gt CounterModuloReg param Base amp displacement calculated by C preprocessor Generated assembly code move w 12543 X 0xf140 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 8 5 1 Specification This section briefly describes API macros and functions Function arguments for each routine are described as in out or inout 1 2 3 argument means that the parameter value is an input to the function only
125. right to use the distributed Software The Software is provided to you only in object machine readable form You may exercise the rights above only with respect to such object form You may not translate reverse engineer decompile or disassemble the Software except to the extent applicable law specifically prohibits such restriction In addition you must prohibit your sublicensees from doing the same If you violate any of the terms or restrictions of this Agreement Freescale may immediately terminate this Agreement and require that you stop using and delete all copies of the Software in your possession or control FOR TOOLS Freescale grants to you the non exclusive non transferable right 1 to use the Software exclusively in conjunction with a development platform from Freescale Exclusive Use and 2 to reproduce the Software The Software is provided to you only in object machine readable form You may not distribute or sublicense the Software to others You may exercise the rights above only with respect to such object form You may not translate reverse engineer decompile or disassemble the Software except to the extent applicable law specifically prohibits such restriction If you violate any of the terms or restrictions of this Agreement Freescale may immediately terminate this Agreement and require that you stop using and delete all copies of the Software in your possession or control COPYRIGHT The Software is licensed to
126. space All MCM registers must be accessed by supervisor code In addition each MCM register must be written in an access size equal to the register s width For example a 32 bit register must be written using a 32 bit access Table 5 41 shows module identifiers for Driver Table 5 41 Identifiers for MCM Driver Module identifier 56 82 56F84xxx MCM Y Y Table 5 42 shows all commands dedicated for Driver Table 5 42 MCM Driver Command Cmd pParam Description 56F82xxx 56F84xxx Initialize the MCM peripheral registers using the appconfig h INIT values lt lt NULL DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 103 5 1 20 Modular Scalable Controller Area Network MSCAN Driver The module is a communication controller implementing the CAN 2 0A B protocol as defined in the Bosch specification dated September 1991 For users to fully understand the MSCAN specification it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document Though not exclusively intended for automotive applications CAN protocol is designed to meet the specific requirements of a vehicle serial data bus real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidt
127. status flags or SPI operation can be interrupt driven The block contains six 16 bit memory mapped registers for control parameters status and data transfer The Table 5 59 shows module identifiers for SPI Driver Table 5 59 Identifiers for SPI Driver Module identifier 56F82xxx 56F84xxx SPI_O Y SPI 1 Y v SPI 2 Y Table 5 60 shows all commands dedicated for SPI Driver Table 5 60 SPI Driver Commands gt lt gt lt gt lt gt lt Description 222 LL LL SPI CAN READ DATA NULL Return non zero if valid data are wait 2122 SPI CAN WRITE DATA NULL Return non zero if free space in TX sly FIFO enables data write SPI_CLEAR_EXCEPTION NULL Clear read write functions exception if sly it exists SPI_CLEAR_MODE_FAULT NULL Clear Status and Control Register PIT MODF bit Mode Fault bit SPI DEVICE SPI ENABLE Enable disable SPI device sly SPI_DISABLE SPI_DMA_RX SPI_ENABLE Enable SPI RX DMA sy SPI_DISABLE SPI_DMA_TX SPI_ENABLE Enable SPI TX DMA SPI DISABLE SPI ERROR INT SPI ENABLE Interrupt enable or disable for ERRIE SPI DISABLE DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 148 Freescale Semiconductor Inc Table 5 60 SPI Driver Commands
128. the overall application might be built differently to reflect the hardware capability The general introductory description of on chip drivers can be found in Section 4 3 The following list contains useful tips On chip drivers usage considerations Peripheral module hardware and functionality knowledge The only efficient and in some cases safe usage of the on chip peripheral module is based on the user knowledge about the module itself A comprehensive description can be found in the MCS56F8xxx Reference Manual MC56F8xxx Data Sheet and in various Freescale Application Notes ANS The way in which the on chip driver s API is designed takes into consideration the entire hardware capability The self explaining names of the driver commands help users find the desired hardware feature On chip driver commands implemented as macros Almost all commands are implemented as efficient C function like macros The exceptions are the initialization commands and the read write commands of the SPI and the SCI which are implemented as regular functions This is documented in every detailed description of each command Implementation of most commands as macros is not only done for the sake of efficiency The other advantage is ease of use within the interrupt service routine where the unwanted overhead i e jump return to from function plus context store restore is eliminated Further the consistent implementation of commands takes care of the use
129. to a module configuration and the configuration is not selected to be saved 7 2 1 2 Peripheral Module Settings Pane This is the area where peripheral module control pages are displayed Default configuration displayed in the GCT control page is a post reset state of each peripheral module The graphical representation of peripheral module settings uses standard MS Windows control elements DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 7 4 Edit Box as numeric value string input numeric values are parsed as decimals by default specify hexadecimal number format use the standard Ox prefix The H D toolbar button can be used to convert the value just being edited between these two formats When using the Edit Box to specify an interrupt service routine ISR name in the GCT use the valid C language function name without the types parameters or even the brackets e Drop Down List Box Combo Box used as mode selectors typically affecting a multiple bits fields in a control register e Check Box typically representing a single bit configuration values 7 2 1 3 Pinout Page The pinout page is a welcome page displayed initially when the GCT is started This page shows a block diagram of the processor device as it is known from the data sheet The page content is actively generated by the GCT and displays several useful information about how the device is currently confi
130. undefined or set to zero It defines the size of the recorder buffer which is to be allocated by the Free MASTER driver Default 256 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 6 2 FreeMASTER Communication Configuration Items for appconfig h Continued SYMBOL TYPE DESCRIPTION FMSTR_REC_FARBUFF numeric zero non zero When defined non zero the recorder buffer allocated by the FreeMASTER driver is put in the fardata memory segment which is typically put to the external memory after the address 0x10000 by the linker Default 0 false zero non zero FMSTR_REC_TIMEBASE UWord16 This constant is used to describe the recorder sam stant pling rate as it is implemented in the application The time base value specified by this constant is used as the base X axis unit in the recorder graph You can use one of the following macros to build the value providing a 14bit value FMSTR REC BASE NANOSEOC x FMSTR REC BASE MICROSEC x FMSTR REC BASE MILLISEC x FMSTR REC BASE SECONDS x The default value of zero be used as unknown which forces the FreeMASTER recorder to display the X axis values as indexes instead of time Target side Addressing FMSTR USE TSA numeric When defined non zero this constant enables a sup port for so called Target side Addressing TSA This is a new feature
131. usage periphBitGrpRS 0xOF00 0 0100 amp ArchlIO Adcl adctl1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 15 This code enables the High Limit exceeded interrupt if the current result value is greater than the high limit Other bits in the register are not affected 2 5 9 periphBitGrpRSVar set bit group to given value Call s void periphBitGrpRSVar UWord16 GroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 11 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpRS Var macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected These bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared The RS variant uses two non interruptible instructions bfclr and bfset to accomplish the requested operation The first clears the zero bits in the destination location and bfclr then sets the bits there Caution This macro is the optimal way how to set the specified group of bits to given value However it must be kept in mind that during the short time between these two bit operations the target memory location goes through the third state where the bit group might contain
132. use debugger move w 0 r2 28188 fflush flush file jsr fflush console flush console IO end of program halt CPU DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 57 debughlt stop DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 58 Freescale Semiconductor Inc Chapter 3 Directory Structure This section describes the directory structure of the Freescale DSP56800EX Quick Start tool located in the WreescaleDSC56800EX Quick Start r2 6 directory Note that the root directory of the DSP56800EX Quick Start may be changed during installation by the user In general the DSP56800EX Quick Start software is organized by supported devices as it is explained this chapter 3 1 Root Directory The root or main directory is organized as shown in Figure 3 1 L3 Freescale C CW MCU v10 3 9 DSC56800EX Quick Start r2 6 applications 9 5 3 stationery tools C3 user manuals Figure 3 1 Root Directory Structure Where sample applications contains simple application examples to demonstrate the usage of the DSP56800EX Quick Start tool as well as the use of device or on chip peripherals see also Section 3 2 src contains the C source files see also Section 3 4 e stationery contains the templates for the newly created projects Note this directo
133. user may put his own global declarations and statements here This feature enables a user to use the appconfig h as a central application configuration file included also by his project source files and not only by Quick Start driver files DSC56800EX Quick Start User s Guide Rev 2 04 2015 7 9 Freescale Semiconductor Inc Edit Source Refactor Navigate Search Project Run PEMicro Processor Expert Window Help Wy eh y 63 16 06 TR Br 3248 m 1 1 1 R arch h board h B sys h File appconfig h Description file for static configuration of the application initial values interrupt vectors Ath ESSE SEE SEES ORE ifndef __APPCONFIG_H define __ FREER EERE SHEER EE EEE REESE EES EES REESE EEE File generated by Graphical Configuration Tool Wed 24 Apr 2013 08 43 32 VOR ARR HACER AU UO o o o rk define MC56F82748 define EXTCLK 8eeeeeeL define APPCFG_DFLTS_OMITTED 1 define APPCFG GCT VERSION 2 6 2
134. value is masked value of the L bit in SR It is either O limit bit is cleared or non zero 0x40 limit bit 1 set Example 2 15 archGetLimitBit function usage if archGetLimitBit DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 9 2 4 1 14 archGetSetSaturationMode get and set saturation mode Call s Wordl6 archGetSetSaturationMode bool bSatMode Arguments Table 2 1 archGetSetSaturationMode arguments bSatMode in State of the saturation mode to be set false set no saturation mode true set saturation mode Description The archGetSetSaturationMode inline function sets the saturation mode to a user specified value The function manipulates with the saturation SA bit Bit 4 in the Operating Mode Register OMR Returns Saturation mode prior to the new state the return value is masked SA bit from the previous OMR value Example 2 16 archGetSetSaturationMode function usage Wordl6 bSatMode bSatMode archGetSetSaturationMode true 2 4 1 15 archDelay delay Call s void archDelay UWordl16 Ticks Arguments Table 2 2 archDelay arguments Ticks in Number of CPU cycles to delay 0 to OXFFFF Description The archDelay inline function delays the program execution by the specified number of CPU cycles Returns None Special Issues The delay corresponds just roughly to the number of CPU cycles Exampl
135. when the FMSTR REC OWNBUFF configuration constant is set to a non zero value The user calls this function to give the data buffer he allocated to the FreeMASTER driver which will use it as a recorder buffer Up to 64kB buffer may be used as a recorder buffer Returns None Range Issues None Special Issues None Design Implementation None Example 6 6 FMSTR_SetUpRecBuff UWordl6 my rec buff 0x1000 FMSTR SetUpRecBuff my rec buff 0x1000 This code shows how the user allocated buffer can be set as the recorder buffer DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 18 6 6 1 7 FMSTR_GetAppCmd Get pending Application Command Call FMSTR APPCMD CODE FMSTR GetAppCmd void Arguments None Description This function can be used to detect if any Application Command is waiting to be processed by the application In case there is no command pending this function returns FMSTR APPCMDRESULT NOCMD constant Otherwise this function returns a code of the Application Command which needs to be processed Use the FMSTR AppCmdAck API call to acknowledge the Application Command after it is processed and to return the appropriate result code to the FreeMASTER tool The FMSTR GetAppCmd function does not report commands for which a callback handler function exists In case the FMSTR GetAppCmd function is called when a callback registered Command is pending and before it i
136. 0 2 j4 Disconnect selected output triggers SABLE EFPWM TRIG1 VALx 1 3 5 from OUT TRIGO and OUT TRIG1 signals EFPWMS OUTPUT TRIGGER EN EFPWM_TRIGO_VALx 0 2 4 Connect selected output triggers in to ABLE EFPWM TRIG1 VALx 1 3 5 OUT TRIGO and OUT sig viv nals EFPWMS PWMA FAULT DISABL EFPWM_FAULT_X 0 1 2 3 Disable selected faults at PWM A pin DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 59 Table 5 19 EFPWM Driver Commands x Xx gt gt gt x Cmd pParam Description EFPWMS_PWMA_FAULT_ENABLE EFPWM FAULT X 0 1 2 3 Enable selected faults at PWM v v EFPWMS PWMA FAULTO DISAB EFPWM FAULT 0 11213 Disable selected faults at PWM LE EFPWMS PWMA FAULTO ENABL EFPWM FAULT 011 213 Enable selected faults at PWM A E EFPWMS PWMA FAULT1 DISAB EFPWM FAULT 0 11213 Disable selected faults at PWM A LE EFPWMS PWMA FAULT1 ENABL EFPWM FAULT 0 11213 Enable selected faults at PWM A E EFPWMS PWMB FAULT DISABL EFPWM FAULT 0 11213 Disable selected faults at PWM E EFPWMS PWMB FAULT ENABLE EFPWM FAULT 0 11213 Enable selected faults at PWM B v v EFPWMS PWMB FAULTO DISAB EFPWM FAULT 0 11213 Disable selected faul
137. 0EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 73 Table 5 21 ENC Driver Command out and optionally generating an inter rupt Description ES 3 Lre ive ENC WRITE LOWER POSITION UWord16 Write the parameter value to the 2 _ Lower Position Compare register ENC_WRITE_POSITION Word32 Write the parameter value to the Lower and the Upper Position Counter Registers UPOS LPOS This value represents the required number of encoder pulses This command writes v the value to the Upper and the Lower Initialization Register followed by ini tialization of the position registers with the software trigger command ENC_WRITE_REVOLUTION Word16 Write the parameter value to the Rev olution Counter register REV This 2 value represents the required number of revolutions ENC_WRITE_UPPER_MODULUS_ UWord16 Write the parameter value to the 2 Upper Modulus register ENC_WRITE_UPPER_POSITION_ UWord16 Write the parameter value to the 2 COMPARE_REG Upper Position Compare register ENC_WRITE_WATCHDOG_TIMEO UWord16 Set the number of clock cycles plus UT one added by hardware that the watchdog timer counts before timing Y DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 74 Freescale Semiconductor Inc 5 1 10 External Watchdog Monitor EWM Driver For safety a re
138. 1 0 1 0 1 FIFO M DMA FIFO _ data the DMA Enable Register DMA FIFO 1 DM A FIFO B1 EFPWM FIFO A1 EFPWMS DMA FIFO WATERMA Select whether FIFO watermarks are RK CONTROL EFPWM WhARITE FIF OR ed or AND ed together Modify the O WATERMARK AND EFP DMA Enable Register viv WM_DMA_WRITE_FIFO_W ATERMARK_OR EFPWMS_DMA_SET_CLOCK_SO EFPWM_DMA_REQUEST_ Enable Source for Capture DMA URCE DIS according to command parameter ABLE EFPWM_DMA_REQU Modify the DMA Enable Register EST_FIFO_WATERMARK E PZN FPWM DMA REQUEST L OCAL SYNC EFPWM DMA REQUEST LOCAL RELO AD EFPWMS VALUE REGISTE EFPWM WRITE REQ Enable disable DMA write requests for RS UEST ENABLE EFPWM D the VALx and FRACVALx registers ll ae MA WRITE REQUEST DIS Modify the DMA Enable Register SABLE EFPWMS EDGE ALIGN UPDATE Word16 in Signed Fractional Range 0 to 1 Set Value2 and Value3 ers CHANNEL 23 representation registers EFPWMS EDGE ALIGN UPDATE Word16 in Signed Fractional Range 0 to 1 Modulo register can be CHANNEL 23 FRAC representation maximally 1024 Set Value2 21 Fractional2 Value3 Fractional3 registers EFPWMS EDGE ALIGN UPDATE Word16 in Signed Fractional Range 0 to 1 Set Value2 and Value3 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 58 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands
139. 15 Freescale Semiconductor Inc 6 12 6 6 1 2 FMSTR_Poll FreeMASTER polling method Call void FMSTR Poll void Arguments None Description Except when the driver is configured for the FMSTR LONG INTR mode the FMSTR Poll function must be called periodically in the application Typically such a call is placed to the application main loop while the application critical tasks are handled in the interrupts In the FMSTR SHORT INTR interrupt mode the FMSTR Poll function fetches all bytes which were received by the SCI or JTAG interrupt service routine and were put in the temporary receive queue The fetched bytes are then all fed to the protocol state machine If the state machine determines the protocol message is received without error the protocol message decoder is invoked If in turn the message is evaluated as a valid and supported message the protocol message handler function is invoked to process the message To prevent receive data overflow in FMSTR SHORT INTR mode the FMSTR Poll function must be called at least once FMSTR COMM RQUEUE SIZE Tchar time where Tchar is the time it takes to receive one byte In the FMSTR POLL DRIVEN mode there is no receive queue and no interrupt service routine which would handle character reception In this mode the FMSTR Poll function accesses the SCI or JTAG peripheral status registers to detect any character was received To prevent receive data overflow the F
140. 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 5 3 ADC Driver Commands Description ag 55 Lre ADC_GET_STATUS_RDY2 UWord16 sample number Read the Status Register 2 RDYx bit 16 19 Ready Sample 16 19 flag ADC_GET_STATUS_ 7 NULL Read the Status Register ZCI bit in the willy Status Register ADC_GET_ZERO_CROSS_STATU UWord16 sample number Read the Zero Crossing Status Regis S 2 5 0 15 ter ZCSx bit Zero Crossing flag viv ADC_ZXSTAT gt _ ADC_GET_ZERO_CROSS_STATU UWord16 sample number Read the Zero Crossing Status Regis 2 512 265 0 19 ter ZCSx bit Zero Crossing flag ADC_GET_ZERO_CROSS_STATU UWord16 sample number Read the Zero Crossing Status Regis S2 ZCS 16 19 ter ZCSx bit Zero Crossing x flag INIT NULL Initialize ADC periheral registers using sly the appconfig h _INIT values ADC_INT_DISABLE ADC_END_OF_SCAN ADC_ Disable selected ADC interrupts ZERO_CROSS ADC_LOW_ LIMIT ADC_HIGH_LIMIT AD alee C_END_OF_SCAN_CONVE RTER OJADC END OF SC AN CONVERTER 1 ADC INT ENABLE ADC END OF SCAN ADC Enable selected ADC interrupts ZERO CROSSJ ADC LOW LIMIT ADC_HIGH_LIMIT AD XN C END OF SCAN CONVE RTER OJADC END OF SC AN CONVERTER 1 ADC POWER DOWN ADC CONVERTER 0J ADC Power down the selected ADC con PIN CONVERTER 1 verte
141. 2 PDB SET DELAY INTERRUPT PDB ENABLE PDB DISABL Enable disable the interrupt on the 2 DELAYA successful compare request PDB SET DELAY B INTERRUPT PDB ENABLE PDB DISABL Enable disable the interrupt on the 2 DELAYB successful compare request PDB SET DELAY C INTERRUPT PDB ENABLE PDB DISABL Enable disable the interrupt on the 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 128 Freescale Semiconductor Inc Table 5 54 PDB Driver Command Description ag 5 Lre PDB_SET_DELAY_D_INTERRUPT PDB_ENABLE PDB_DISABL Enable disable the interrupt on the 2 DELAYD successful compare request PDB SET FAULT A PDB ENABLE PDB DISABL Enable disable the Fault A A logic 1 E on the Fault A input forces TriggerA output to initial value set by Y PDB SET INIT A VALUE command until a counter reload occurs PDB SET FAULT A LENGTH PDB xxx Select the minimum width number of 2 IPBUS CYCLES A IP bus clock cycles of the input fault P PBUS CYCLES when it is recognized as a valid fault condition PDB SET FAULT A POLARITY PDB xxx Select the Fault A polarity INDICATE FAU 2 LT FALSE_INDICATE_FAUL T PDB SET FAULT C PDB ENABLE PDB DISABL Enable disable the Fault C A logic 1 E on the Fault C input forces TriggerC output to initial value set by Y PDB SET INIT C VALUE com man
142. 2 function usage Wordl16 varl 1 UWordl6 var2 15 Wordl16 result result shl2 varl var2 returns 0x8000 This code shifts var variable var2 times to the left and returns the result in result variable 2 5 29 4 shr2 optimized version of shr intrinsic function Call s Wordl6 shr2 Wordl16 num UWordl6 shifts Arguments Table 2 34 shr2 arguments num in parameter to be shifted DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 31 Table 2 34 shr2 arguments shifts in number of shifts Description The shr2 function performs a multi bit arithmetic shift of the first parameter to the right by the amount specified in the second parameter The result is returned as a 16 bit integer This function is the optimized version of the shr intrinsic function see CodeWarrior Help for more information on shr Returns num parameter shifted shifts times to the right Example 2 49 shr2 function usage 16 varl 16 Wordl6 result result shr2 varl 3 returns 0x0002 This code shifts var variable three times to the right and returns the result in the result variable 2 5 30 Intrinsic Functions The 56800EX Quick Start tool can exploit the system intrinsic functions defined in intrinsics 568500E h header file distributed with the CodeWarrior Development Studio 56800 EX Hybrid Controllers To preserve compatibility with the DSP56800 Quick Start tool the
143. 2V Disable Low voltage 2 7V Disable High voltage 2 2V Disable High voltage 2 7V Disable Enable Voltage Reference Buffer No Bandgap trim 7 Use Factory Trim Value No zu define SIM CLKOSR INIT 0x1020U define SIM PCEO INIT 0x0012U define SIM 1 INIT 0x0802U define SIM PCE2 INIT 0x0000U define SIM PCE3 INIT 0x0000U Jes GPIO C Configuration Pin 0 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 1 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 2 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 3 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 4 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 5 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 6 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 7 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 8 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 29 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 10 Function
144. 32 kHz oscillator No Power Down crystal oscillator Yes Core frequency 50 MHz frequency 200 MHz Loss of lock interrupt 0 Disable Loss of lock interrupt 1 Disable Loss of reference clock Interrupt Disable 5 define OCCS_CTRL_INIT 0x0081U define OCCS DIVBY INIT 0x2018U define OCCS USE FACTORY TRIM 1 define OCCS_USE_FACTORY_TRIM_TEMP SYS Configuration SIM Power Saving Modes Stop enabled Wait enabled OnCE clock to processor core Enabled when core TAP enabled DMA Enable in RUN and WAIT modes DMA enabled in all power modes Enable External Reset Padcell Input Filter No SIM Clock on GPIO Enable CLKO 0 No SIM Clock on GPIO Enable CLKO 1 No SIM Peripheral Clock Enable GPIO F Yes GPIO E Yes GPIO D No GPIO C No GPIO B No GPIO A No TMR A0 No TMR Al No TMR A2 No TMR No SCIO SCI1 Yes QSPIO No QSPI1 No IICO No FLEXCAN No B C No D CYC ADC CRC QDC PITO No PIT1 No DACA DACB No PWMCHO Yes 1 Yes PWMCH2 Yes PWMCH3 Yes SIM Modules Enabled in Stop GPIO No SIM Modules Enabled in Stop GPIO E No SIM Modules Enabled in Stop GPIO D No SIM Modules Enabled in Stop GPIO C No SIM Modules Enabled in Stop GPIO B No SIM Modules Enabled in Stop GPIO A No SIM Modules Enabled in Stop TMR A0 No TMR A1 No TMR A2 No TMR A3 N
145. 56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 49 remains turned off and the system clock is still taken from default clock source now divided by prescaler value The default clock source is an external oscillator or an internal relaxation oscillator on some devices configure external oscillator and clock mode ifdef OCCS_OSCTL_INIT define OSCTL_TEMP OCCS_OSCTL_INIT amp Ox3fff keep internal osc enabled move w OSCTL_TEMP ArchIO Pll osctl OSCTL even if PLL not used nop nop endif setup the PLL according to appconfig h values ifdef OCCS_PLLDB_INIT move w OCCS_PLLDB_INIT ArchIO Pll plldb PLLDB even if PLL not used nop nop endif On the devices equipped with an internal relaxation oscillator a user may want to initialize the trimming value in the Oscillator Control Register by the factory measured value which is saved in the SIM Non Volatile Memory Option Register 2 High For the new devices e g 56F82xxx 56F84xxx the OCCS version 6 or 7 is valid load factory trimming value of the internal relaxation oscillator if OCCS_USE_FACTORY_TRIM first move factory value to Y1 if OCCS_VERSION lt 4 move w ArchIO Hfm fmopt1 y1 elif OCCS_VERSION lt 5 OCCS_VERSION 5 move w ArchIO Hfm fmopt0 y1 else OCCS_VERSION gt 6 move w ArchIO Sim sim_nvmopt2h y1 endif bfclr 0 00 1 Then i
146. 56F82xxx 56F84xxx PDB TEST DELAY A FLAG NULL Return a non zero value when a suc cessful compare of the values of counter and DELAYA occurred lt TEST DELAY B FLAG NULL Return a non zero value when a suc cessful compare of the values of counter and DELAYB occured PDB TEST DELAY C FLAG NULL Return a non zero value when a suc cessful compare of the values of counter and DELAYC occured PDB TEST DELAY D FLAG NULL Return a non zero value when a suc cessful compare of the values of counter and DELAYD occured PDB TEST FAULT A STATUS NULL Return a non zero value when Fault A input is set PDB TEST FAULT C STATUS NULL Return a non zero value when Fault C input is set PDB TEST LDOK NULL Return the non zero value when the LDOK bit is set Use this command to determine if the values in the DELAY and MOD registers are pending in buffers non zero or if the write has already taken effect zero PDB WRITE CTRLA REG UWord16 Write the parameter value to the Con trol A register Note an inappropriate write to register can clear Write 1 to Clear DAF DBF flags PDB WRITE CTRLC REG UWord16 Write the parameter value to the Con trol C register Note an inappropriate write to register can clear Write 1 to Clear DCF DDF flags PDB WRITE DELAYA UWord16 Write the parameter value to the DelayA re
147. 6 19 set Register for sample defined by the v parameter ADC READ POWER CONTROL NULL Read and return value of Power Con 2_ trol Register 2 ADC READ POWER CONTROL NULL Read and return the value of ADC PIE REG Power Control Register ADC READ SAMPLE UWord16 sample number Read Result Register The sample 0 15 number is determined by parameter 0 15 ADC_READ_SAMPLE12 UWord16 sample number Read Result Register This is univer 0 19 sal command and works for samples viv 0 19 ADC_READ_SAMPLE2 UWord16 sample number Read Result Register for extended 16 19 sample numbers The sample num viv ber is determined by parameter 16 19 ADC_READ_SCAN_CONTROL_RE NULL Read and return the value of Scan yy G Control Register ADC READ SCAN CONTROL RE NULL Read and return the value of Scan G2 Control Register 2 ADC READ SCAN HALTED INTE NULL Read and return the value of Scan sly RRUPT_REG Halted Interrupt Enable Register ADC_READ_SCAN_HALTED_INTE NULL Read and return the value of Scan RRUPT_REG2 Halted Interrupt Enable Register 2 ADC READ STATUS NULL Read and return the value of ADC Status Register ADC READ ZERO CROSS STAT NULL Read the ADC Zero Crossing Status VU US Register ADC READ ZERO CROSS STAT NULL Read and return values of ADC Zero 0612 Cross Status registers 1 and 2 ADC_READ_ZERO_CROSS_STAT NULL Read and return the value of Zero 2 052 Cross Status Register 2 ADC_SET_ADCA6_INPUT ADC_ANALOG_INP
148. 6 UWord16 portion of the ID Set 8bit acceptance ID 6 acceptance value lower byte Y only MSCAN SET IDR 8 7 UWord16 portion of the ID Set 8bit acceptance ID 7 acceptance value lower byte Y only MSCAN SET ACC MASKR 16 0 UWord16 portion of the mask Set 16bit acceptance mask 0 for the value including the RTR SRR case when using 16 bit mask and IDE bits MSCAN SET ACC MODE used with the MSCAN ACC MODE 4X16 parameter The 0 bits in the mask determine which bits are matched with v the acceptance value The bits set to 1 in the mask are the don t care bits The mask and ID values for the 4x16 mask mode affect all Standard ID bits and or Extended ID bits 28 15 MSCAN_SET_ACC_MASKR_16_1 UWord16 portion of the mask Set 16bit acceptance mask 1 for the value including the RTR SRR case when using 16 bit mask Y and IDE bits MSCAN SET ACC MASKR 16 2 UWord16 portion of the mask Set 16bit acceptance mask 2 for the value including the RTR SRR case when using 16 bit mask Y and IDE bits MSCAN SET ACC MASKR 16 3 UWord16 portion of the mask Set 16bit acceptance mask for the value including the RTR SRR case when using 16 bit mask Y and IDE bits MSCAN SET ACC MASKR 32 0 UWord32 mask value includ Set 32bit acceptance mask 0 for the ing the RTR EX RTR SRR case when using 32 bit mask and IDE bits MSCAN SET ACC MODE used with the MSCAN ACC MODE 4X16 parameter The 0 bits in the mask determine which bits are matched with v t
149. 63 49 cpio c13 1 OUT B GPIO C Gene GP 04 RESET 2 grote soane 55 14 _ 4 n e grou o raus 56 GPIO C15 xB_OUTS FAULTS GPIO E Gener GPIO PWMOB goes xg me GPIO_F Gener GPIO E1 46 exo F4 C cLKo_1 1 _ 2 GPIO 1 47 Sr ban m ox enm 39 2 x8 oure E3IV 48 gors 40 VA Cross gros orau 44 Gpio rs M pwma_ox FAULTe sci 1 XBAR Cros GPIO ESM PWM2B 2 51 E 7 AOI Crosbar GPIO ES 2 52 gon pona oryn sve 42 GPIO FS 1 ours FAULT7 PWM A Pulse Wi GPotelv PwwaB xe m4 53 SPOS 278 90 58 xB_N2 3X GPIO E7 xB NS 54 ror cuc ass v n 59 _ 2X PWM A o ewe ww 2 6 GPIOFS C PWM FaultC Shared Pins Status Icons PWM A Pu No pins are configured fo
150. 6_xxx Select between the extended sample TIME xxx 24ADCK 16ADCK 10A times when long sample time is DCK 6ADCk enabled by using v ADC16_SET_LONG_SAMPLE_TIME ioctl command ADC16_SET_ASSIST_TRIGGER ADC16_ENABLE ADC16_DI Enable disable writes to ADCSC1 SABLE COCO bit to be reflected on ADTRG Y register bit ADC16 SET ASYNCH CLOCK O ADC16 ENABLE ADC16 DI Enable disable the asynchronous UT SABLE clock source and output regardless of the conversion and status of CFG1 ADICLK Based on MCU con Y figuration the asynchronous clock may be used by other modules See the chip configuration information ADC16 SET CLOCK INPUT ADC16 CLOCK SEL xxx Select the ADC input clock source to xxx BUS BUS_DIV2 ALT generate the internal ADCK clock Y CLK ADATCK ADC16 SET COMPARE FUNCTI ADC16 ENABLE ADC16 DI Enable disable the compare function 2 SABLE of the conversion result ADC16_SET_COMPARE_FUNCTI ADC16_xxx Set compare function mode For the ON_MODE xxx LESS_THAN GREATE RANGE modes the selection whether R_THAN_OR_EQUAL RAN inside or outside of range is compared Y GE NON INCLUSIVE RAN depends on relation of CV1 and CV2 GE INCLUSIVE values ADC16 SET CONVERSION MOD ADC16 CONV xxx Select the conversion mode When E xxx SINGLE CONTINU the HW average is enabled the con 2 OUS version is completed when the aver age is calculated and COCO is set DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 25 Table 5 5 A
151. 7 ioctl PWM_SET_MODULO val variable used results in move w 32767 X 0x003012 move 1 0x003012 R1 move l 0 145 move w X R1 A move w 32767 move w Al X RO move w Al X 0xf145 Another possibility is to use the predefined symbolic constants to express the desired action like ioctl RELOAD INT ENABLE which results in move l Oxf140 RO0 ore bfset 0x20 X RO bfset 0 20 0 140 The predefined symbols or constants should be used whenever possible DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 2 Freescale Semiconductor Inc Some macros expand to a single assembly instruction as illustrated above Other macros expand to a more assembly instructions e g the different mode setting where it is necessary to clear the previous setting and then to set the new mode Assembly insructions are illustrated by the following example ioctl PWM SET PRESCALER PWM PRESCALER DIV 2 move l Oxf140 R0 or bfclr 0xc0 X RO bfceclr 0 0 140 bfset 0x40 X RO bfset 10 40 0 140 Note that the generated code depends on the selected compiler optimizations on the rest of the source code and on the selected target Even longer commands can be implemented These commands incorporate a functionality that is higher than a simple access to the peripheral
152. 748 peripheral JIsystem 3 CJ MC56F84550 S MC56F84789 3 support compat C3 freemaster Figure 3 3 Src Directory Structure 3 5 Stationery Directory The stationery directory contains the templates for the newly created DSP56800EX_Quick_Start projects This directory is also copied into the CodeWarrior development tool directory if a proper path was specified by the user This directory is needed to be copied manually or import into CodeWarrior present on the host computer 5 stationery 3 L3IDSC56800EX Quick Start r2 6 3 9 MC56F82736 56 82748 F3 MC56F82748EVM Application 3 Standalone C application 3 MC56F84550 3 9 MC56F84789 Figure 3 4 Stationery Directory Structure The device specific subdirectories MC56F 8xxxx are covered by the DSP56800EX Quick Start directory with the release version number The device specific subdirectory contains all needed support files for the proper memory system and application configuration and initialization 3 6 User manuals Directory The user manuals directory contains this DSP56800EX Quick Start User s Manual as well as other relevant documentation DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 3 3 Chapter 4 Developing Software This chapter describes in detail how to develop the applications using the D8C56800EX Quick Start It describes how to create new applications using
153. 8 Freescale Semiconductor Inc Table 5 34 GPIO Driver Commands Description ag Lre GPIO_SET_HIGH_DRIVE_STREN combination of BIT_x Set the high strength 8mA of the GTH 0 1 15 selected GPIO pin output driver by siy modifying the content of the Drive Strength Control Register DRIVE gt GPIO_SET_LOW_DRIVE_STRENG combination of BIT_x Set the low strength 4mA of the TH x 0 1 15 selected GPIO pin output driver by PM modifying the content of the Drive Strength Control Register DRIVE gt GPIO SET LOW PASS FILTER combination of BIT x Disable the low pass input filter of the DISABLE 0 1 15 selected GPIO pin by modifying the viv content of the Input Filter Control Register GPIO SET LOW PASS FILTER E combination of BIT x Enable the low pass input filter of the NABLE 0 1 15 selected GPIO by modifying the AE content of the Input Filter Control Register GPIO SET PIN combination of BIT x Set the selected GPIO pins by 0 1 15 modifying the content of the Data Register GPIO SET PULL DOWN combination of BIT x Enable pull down on the selected pins 0 1 15 by modifying the content of the Pull viv Resistor Enable Register GPIO_SET_PULL_UP combination of BIT_x Enable pull up on the selected pins by 0 1 15 modifying the content the Pull viv
154. 84xxx PIT_READ_MODULO_REG NULL Read and return the PIT modulo regis ter value as UWord16 lt lt PIT_ROLLOVER_INT PIT_ENABLE PIT_DISABLE Enable disable the PIT interrupt to be generated The PIT interrupt is gener ated when PIT counter value wraps to zero after reaching the modulo value PIT_SET_CLOCK PIT_IPBUS_CLOCK PIT_CL OCKxxx xxx 1 2 3 Select the source of the clocking for the PIT counter This field should not be changed when CNT EN is set PIT SET PRESCALER PIT PRESCALER xxx 1 2 4 8 16 32 64 128 25 6 512 1024 2048 4096 8192 16384 32768 Set the counter prescaler The PIT count clock is derived directly from the IP Bus clock divided by the prescaler value PIT_SLAVE_MODE PIT_ENABLE PIT_DISABLE Enable disable the PIT slave mode It is applicable to PIT_1 and PIT_2 only When slave mode is enabled on PIT enabling or disabling PIT 0 counter also enables or disables this PIT Slave mode can be used for simultaneous count enabling or dis abling of multiple PIT modules PIT_WRITE_MODULO_REG UWord16 Set the PIT modulo register which is the terminal value of the PIT counter When the counter reaches the modulo value it is wrapped to zero at the next counter clock and the PIT interrupt event is raised if enabled The mod ulo value of zero causes the PIT counter to remain zero and to gener ate the PIT interrupts at each counter clock I
155. A CH xxx 0 3 Set the DMA channel assigned as link 401122 channel 1 DMA SET LINK CHANNEL 2 DMA CH xxx 0 3 Set the DMA channel assigned as link P channel 2 DMA SET LINK CHANNEL MOD DMA xxx Set the DMA channels to have their E LINKING LCH1 T transfers linked The current DMA HEN LCH2 LCH1 AFTER channel triggers a DMA request to the PX CS LCH1 WHEN BCR 90 linked channels LCH1 or LCH2 depending on the condition described by the parameter DMA SET PERIPHERAL REQUE DMA ENABLE DMA DISAB Enable peripheral request to initiate ST LE the DMA transfer DMA SET SOURCE ADDRESS UWord32 source address Set the source address used by the PX DMA channel to read data DMA SET SOURCE ADDRESS xxx xxx DIS Set the size of the source data circular MODULO ABLE 16B 32B 64B 128B 25 buffer used by the DMA channel 6B 512B 1KB 2KB 4KB 8KB 16 32 64 128 25 6 DMA SET SOURCE INCREMENT ENABLE DMA DISAB Set source address increment after LE each successful transfer DMA_SET_SOURCE_SIZE _ Set the data size of the source bus xxx BYTE WORD LONG cycle for the DMA channel DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 46 Freescale Semiconductor Inc gt lt gt lt gt lt Description LL LL SET START TRANSFER DMA ENABLE DMA DISAB DMA be
156. ADC Driver Commands Description ag 55 ive ADC_SET_LIST_SAMPLE14 one of Set mapping of the physical ADC input sly ADC_ANAx ADC_ANBx to the sample 14 ADC_SET_LIST_SAMPLE15 one of Set mapping of the physical ADC input ADC_ANAx ADC_ANBx to the sample 15 ADC_SET_LIST_SAMPLE16 ADCx_TEMPERATURE_SE Set mapping of the physical ADC input NSOR ADCx_ANALOG_INP_ to the sample 16 Y UT ADC SET LIST SAMPLE17 ADCx TEMPERATURE SE Set mapping of the physical ADC input NSOR ADCx ANALOG INP to the sample 17 Y UT SET LIST SAMPLE18 ADCx TEMPERATURE SE Set mapping of the physical ADC input NSOR ADCx ANALOG INP to the sample 18 Y UT ADC SET LIST SAMPLE19 ADCx TEMPERATURE SE Set mapping of the physical ADC input NSOR ADCx ANALOG INP to the sample 19 Y UT ADC SET LIST SAMPLE2 one of Set mapping of the physical ADC input ADC_ANAx ADC_ANBx to the sample 2 ADC_SET_LIST_SAMPLE3 one of Set mapping of the physical ADC input 2142 ADC_ANAx ADC_ANBx to the sample 3 ADC_SET_LIST_SAMPLE4 one of Set mapping of the physical ADC input ADC_ANAx ADC_ANBx to the sample 4 ADC_SET_LIST_SAMPLE5 one of Set mapping of the physical ADC input gt ADC_ANAx ADC_ANBx to the sample 5 ADC_SET_LIST_SAMPLE6 one of Set mapping of the physical ADC input Vw ANAX ADC ANBx to the sample 6 ADC SET LIST SAMPL
157. ASTER driver and enables the communication interface SCI or This function does not change the configuration of communication module the module must be initialized before the FMSTR Init function is called For the SCI communication the SCI module has to be configured either dynamically in run time or using the GCT and the SC INIT ioctl call See for more details It is not necessary to set the transmitter and receiver enable bits in the SCI control register SCICR In case the interrupt driven SCI communication is to be used either in FMSTR SHORT INTR or FMSTR LONG INTR mode the SCI interrupt vectors need to be routed to FMSTR 15 function and interrupt priority levels should be set to Level 0 1 or 2 It is not necessary to set any of the interrupt enable bits in the SCI control register SCICR The SCI TX Idle interrupt is not used at all For the JTAG communication as there is no settings for the JTAG module the only what needs to be done is routing the JTAG interrupt vectors to FMSTR Isr function and setting proper interrupt priority levels For JTAG polling mode FMSTR POLL DRIVEN no setup operations are required at all Returns None Range Issues None Special Issues None Design Implementation None Example 6 1 FMSTR Init ioctl SCI 0 SCI INIT NULL FMSTR Init This code initializes the SCI module and then it initializes FreeMASTER driver DSC56800EX Quick Start User s Guide Rev 2 04 20
158. C MODULE DAC ENABLE DAC DISAB LE Enable disable the DAC module Before the DAC module is used the DAC device should be configured in disabled state and then enabled DAC_READ_CONTROL_REG DAC_READ_DATA NULL NULL Read and return the value of the DAC gt Control Register Read and return a value of the DAC viv Data Register DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 40 Freescale Semiconductor Inc Table 5 13 DAC Driver Commands Cmd pParam Description 56F82xxx 56F84xxx DAC READ FIFO EMPTY NULL Read and return the empty status of FIFO lt lt DAC_READ_FIFO_FULL NULL Read and return the full status of FIFO DAC_READ_MAXVAL NULL Read and return a value of the DAC Maximum Value Register DAC_READ_MINVAL NULL Read and return a value of the DAC Minimum Value Register DAC_READ_STEP NULL Read and return a value of the DAC Step Register DAC_SET_AUTO_MODE DAC AUTO xxx xxx OFF SAWTOOTH1 SA WTOOTH2 TRIANGLE Set generation of a shaped analog signal on the DAC output DAC_SET_DATA_FORMAT DAC_RIGHT_ALIGNED_FM T DAC_LEFT_ALIGNED_FM Configure the data alignment for the DATA STEP MINVAL and MAXVAL Registers The alignment defines what bits of the registers contain the 12 bit DAC value DAC_SET_FILTER UWord16 value 0 31 Set the number of IP Bus clock cyc
159. CS CMP A 0 D No GPIO B No No No SCIO No 0 5 SCIL GPIO E No 2 CMP B No CM GPIO D No TMR A3 DACA No PWMCH1 No DAC TMR Al No No QSPI CMP B No DACA No DAC PWMCH1 No SIM Modules Enabled 5 SIM Modules Enabled SIM Modules Enabled Stop Enabled in Stop TMR AO No CMP C No 2 0 2 2 No SCIO No SCIL CMP D No CYC ADC PWMCH3 GPIO E No GPIO C No GPIO A No TMR QSPI1 IIC No SIM SIM SIM D No CYC ADC No Protection Protection Protection Protection GPIO Peripheral select registers of IPS and GPSxx of PCE SD and PCR Registers not protected Registers not protected of GPIO Port D Registers not protected of PWRMODE Registers not protected Internal P Sel ANB1 CMPB_INO EXTAL TXDO TAO TAL DACA TA2 SSO_B MOSIO SCLKO MOSIO Reserved Reserved TA3 SDAO SCLO PWMA 2B PWMA 2A PWMA 3B PWMA 3A XB IN6 CLKOU
160. C_SAMPLEx x 0 19 Clear the delay condition and set con Y12 verter to immediately take the sample x after completion of previous sample ADC_SET_SAMPLE_IMMEDIATEL ADC_SAMPLEx x 16 19 Clear the delay condition and set con Y2 verter to immediately take the sample Y x after completion of previous sample ADC SET SCAN HALTED INTER Any combination of Disable Scan Halted Interrupt for PUN RUPT DISABLE SAMPLEx x 0 15 selected samples ADC SET SCAN HALTED INTER Any combination of Disable Scan Halted Interrupt for 2 RUPT_DISABLE12 ADC_SAMPLEx x 0 19 selected samples ADC_SET_SCAN_HALTED_INTER Any combination of Disable Scan Halted Interrupt for 2 RUPT_DISABLE2 ADC_SAMPLEx x 16 19 selected samples ADC_SET_SCAN_HALTED_INTER Any combination of Enable Scan Halted Interrupt for sly RUPT_ENABLE ADC_SAMPLEx x 0 15 selected samples ADC_SET_SCAN_HALTED_INTER Any combination of Enable Scan Halted Interrupt for 2 RUPT 12 SAMPLEx x 0 19 selected samples ADC_SET_SCAN_HALTED_INTER Any combination of Enable Scan Halted Interrupt for 2 RUPT_ENABLE2 ADC_SAMPLEx x 16 19 selected samples DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 15 Table 5 3 ADC Driver Commands ADC_ANBx_Sy x 0 7 y 4 7 samples 4 7 Description ag 515 ive ADC SET SCAN MODE ADC SCAN xxx Set S
161. C_SET_ANB7_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANB7 input viv ADC_SET_ANB9_ GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANB9 input A ADC SET CALIB SOURCE ANA7 xxx or Select internal source of ANA7 and ANB7 xxx xxx NOR ANB7 inputs in the ADC Calibration E MAL FROM DACO FROM D Register PASSTHRU ADC SET CHANNEL CONFIG ANAx ANAy zzz Configure the analog inputs for either 01 23 45 67 single ended or differential conver viv ZZzz SE DIFF sions ADC SET DIVISOR UWord16 5 bit value or one Clock Divisor Select of ADC_DIVxx ADC_SET_DMA_TRIGGER ADC_DMA_TRIGGER_END Select between EOSIO and RDY bits _SCAN ADC_DMA_TRIGGE as the DMA source viv R_RDY ADC SET LIST SAMPLEO one of Set mapping of the physical ADC input XE ANAX ADC ANBx to the sample 0 ADC SET LIST SAMPLE1 one of Set mapping of the physical ADC input ADC_ANAx ADC_ANBx to the sample 1 ADC_SET_LIST_SAMPLE10 one of Set mapping of the physical ADC input 21752 ADC_ANAx ADC_ANBx to the sample 10 ADC_SET_LIST_SAMPLE11 one of Set mapping of the physical ADC input za ADC ANAX ADC ANBx to the sample 11 ADC SET LIST SAMPLE12 one of Set mapping of the physical ADC input PAP ADC ANAX ADC ANBx to the sample 12 ADC SET LIST SAMPLE13 one of Set mapping of the physical ADC input P ADC_ANAx ADC_ANBx to the sample 13 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 13 Table 5 3
162. DC16 Driver Command selected by the ADC16_SELECT_LONG_SAMPLE_T IME ioctl command Description ES 3 8 ADC16 SET CONVERSION TRIG ADC16 SW TRIGGER ADC Setthe type of trigger used for initiat GER 16 HW TRIGGER ing a conversion Use ADC16 SW TRIGGER when a con version is initiated by writing to SC1A 2 register Use ADC16_HW_TRIGGER when a conversion is initiated by the assertion of the ADHWT input after a pulse of the ADHWTSn input ADC16_SET_DIVIDER ADC16_CLOCK_DIVIDER_x Select the divide ratio used by the 1 2 4 8 ADC to generate the internal clock Y ADCK ADC16 SET DMA ADC16 ENABLE ADC16 DI Enable disable the ADC DMA request SABLE When DMA is enabled assert the DMA request on an ADC conversion com plete event ADC16 SET HARDWARE AVERA ADC16 ENABLE ADC16 DI Enable disable the hardware average GE SABLE function of the ADC The number of samples is set by the Y ADC16 SET HARDWARE AVERAG E SAMPLES ioctl command ADC16 SET HARDWARE AVERA ADC16 xxx Select how many ADC conversions GE SAMPLES 4 SAMPLES 8 SAMPL will be averaged to create the ADC 2 5 16 SAMPLES 32 SAMP average result LES ADC16_SET_HIGH_SPEED ADC16_ENABLE ADC16_DI Enable disable the ADC for very SABLE high speed operation The conversion sequence is altered with 2 ADCK Y cycles added to the conversion time to allow higher speed conversion clocks ADC16
163. DSC56800EX Quick Start User Guide DSC56800EXQSUG eV 04 2015 4 A Ww 27 freescale How to Reach Us Home Page freescale com Web Support freescale com support Information in this document is provided solely to enable system and software implementers to use Freescale products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document Freescale reserves the right to make changes without further notice to any products herein Freescale makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey license under its patent rights nor the rights of others Freescale sells products pursuant to standard terms and conditions of sale which can be found at the following address freescale com SalesTermsandConditions Free
164. Dire ER INIT uration ction ction ction Input PullU Input PullU Disab Disab Disab Input PullU 0x0030U Baudrate 9601 bps Parity None Polarity 7 Enable Receiver Enable Transmitter Data word length 8 bits Enable Enable True polarity Loop mode Disable Function in Wait Mode Interrupts RX Full Disable RX Error Disable Empty Disable Enable RX RX Active Enable TX Rx Idl TX X Empty Disable and TX FIFO Queues Edge DMA Enable RX DMA Hold off entry to stop mode No Disable Disable Disable nabled Di define define define define define define Interrupt SCI_1_SCIBR_INIT SCI_1_SCICR_INIT SCI_1_SCICR2_INIT SCI 1 RX BUFFER OKLIMIT SCI 1 RX BUFFER LOWLIMIT SCI 1 SCICR3 INIT FMSTR Configuration Disable sable 0 0 2 0 0 000 0 0 00000 0 000 0 000 0 0 00000 eS define def de pp 3 5 H la 0 MSTR 05 MSTR COMM INTERFACI MSTR LONG INTR MSTR SHORT INTR LL DRIVEN MSTR USE APPCMD E E SCOPE Fh Fh Eh Fh H define TR_USE RECORDER define ine FMSTR_PO 5 051 5 define R_USE Disab SCI module enabled
165. E FCAN DIS Enable disable Low power Doze Y ABLE Stop Mode FCAN STOP MODE FCAN ENABLE FCAN DIS Backward compatibility alias for v ABLE FCAN DOZE MODE FCAN DEBUG MODE FCAN ENABLE FCAN DIS Enter Leave Freeze Debug halt Y ABLE mode FCAN SOFT RESET NULL Trigger the soft reset of the FlexCAN module Do not use in when FlexCAN is in low power mode FCAN_SELF_WAKEUP_MODE FCAN_ENABLE FCAN_DIS Enable or disable Self Wakeup mode Y ABLE when bus activity is detected FCAN TEST READY NULL Test if FlexCAN module is ready Y MCR NOTRDY bit cleared FCAN TEST DEBUG NULL Test if FlexCAN is in the Freeze mode Y MCR FREEZ ACK bit DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 77 Table 5 25 Driver Command Cmd pParam Description FCAN_TEST_STOP NULL Test if FlexCAN module is in the Low power mode MCR LPMACK bit 56F82xxx lt 56F84xxx FCAN_INT_ENABLE xxx BUSOFF ERROR WAK EUP TX_WARNING RX_WA Enable selected interrupts Note that Y the RX and TX Warning interrupts first need to be enabled by the RNING FCAN WARNING INTERRUPT com FCAN INT DISABLE FCAN xxx INT Disable selected interrupts xxx BUSOFF ERROR WAK EUP TX WARNING RX WA RNING FCAN WARNING INTERRUPT FCAN ENABLE FCAN DIS Enable or disable occurrence of warn Y ABLE ing interrupts when enabled the RX and or TX warning interrupts still need to be enabled by
166. E7 one of Set mapping of the physical ADC input UN ANAX ADC ANBx to the sample 7 ADC SET LIST SAMPLE8 one of Set mapping of the physical ADC input vw ANAX ADC ANBx to the sample 8 ADC SET LIST SAMPLE9 one of Set mapping of the physical ADC input 2212 ADC_ANAx ADC_ANBx to the sample 9 ADC_SET_MAX_SPEED_ADCA ADC SPEED Set maximum clock speed of the part xxx 5MHZ 10MHZ 15MHZ ADCA Y 20MHZ DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 14 Freescale Semiconductor Inc Table 5 3 ADC Driver Commands gt lt Description ag 5 iO ADC SET SPEED ADCB ADC SPEED xxx Set maximum clock speed of the part xxx 5MHZ 10MHZ 15MHZ ADCB Y 20MHZ ADC SET POWER UP DELAY UWord16 value 0 63 Set power up delay in Power Control viv Register ADC_SET_SAMPLE_BY_SYNC ADC_SAMPLEx x 0 15 Set converter to delay sample x until a be new sync signal occurs ADC_SET_SAMPLE_BY_SYNC12 ADC_SAMPLEx x 0 19 Set converter to delay sample x until a new sync signal occures ADC_SET_SAMPLE_BY_SYNC2 ADC_SAMPLEx x 16 19 Set converter to delay sample x until a 2 new sync signal ADC_SET_SAMPLE_IMMEDIATEL ADC_SAMPLEx x 0 15 Clear the delay condition and set con Y verter to immediately take the sample viv x after completion of previous sample ADC_SET_SAMPLE_IMMEDIATEL AD
167. EA Bit3 encoder signals from the Input Monitor Regis ter IMR as UWord16 or as decoder sEncSignals structure mem bers ENC GET SCALED POSITION pointer to decoder sEncScale type Calculate and return absolute position as Word32 where the MSB part rep resents the number of revolutions equals to the content of the Revolu tion Register while the LSB part rep resents the portion of the current revolution scaled into the range of a 16bit unsigned data The DEC CALCULATE SCALE COEF command must be executed prior to this command ENC GET SCALED POSITION DI FFERENCE pointer to decoder sEncScale type Calculate and return a relative position difference as Word16 The DEC CALCULATE SCALE COEF command must be executed prior to this command This command reads the content of the Position Difference Counter Register POSD ENC GET TEST COUNT NULL Get the number of quadrature advances to generate during self test operation ENC GET TEST PERIOD NULL Get the number of quadrature advances to generate during self test operation ENC HOME EDGE ENC NEGATIVE ENC POSI TIVE Set the rising or falling edge of the HOME signal to trigger the initializa tion of the Upper and the Lower Posi tion Counter Registers UPOS LPOS DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 69 Table 5 21 ENC Driver Command
168. EFPWM value to which it is forced when viv _CHANNEL_X FORCE_INIT Control 2 Register EFPWMS_SET_FORCE_INIT_PW EFPWM CHANNEL 45 EFP Determine the initial value and the MOUT TO LOW WM CHANNEL 23 EFPWM value to which it is forced when viv CHANNEL X FORCE INIT Control 2 Register EFPWMS SET FORCE INIT SOU EFPWM FORCE XXX Select force initialization source RCE LOCAL FORCE MASTER FORCE LOCAL RELOAD M ASTER_RELOAD LOCAL_S YNC MASTER SYNC EXT SYNC EFPWMS SET FRACTIONAL DEL EFPWM FRAC DELAY X Disable selected fractional delay ew AY DISABLE 1 23 45 POWERUP block EFPWMS SET FRACTIONAL DEL EFPWM FRAC DELAY X Enable selected fractional delay block FX DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 64 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands gt lt Description ag Lre 10O EFPWMS_SET_INDEPENDENT_M NULL Set pair operation to independent 2 ODE EFPWMS_SET_LOAD_MODE EFPWM LOAD xx IMME Select load mode EXE DIATE END CYCLE EFPWMS SET PAIR OPERATION EFPWM XXX COMPLE Set pair operation 213 MENTARY INDEPENDENT EFPWMS SET PRESCALER EFPWM PRESCALER DIV Set reload PWM submodule pres PEE _ 1 2 4 8 16 32 64 128 caler EFPWMS SET PWM FAULT STA EFPWM XXX Set level of output pin PWMA during TEOUT A LOG_0 LOG_1 TRISTATED fault state EFPWMS SE
169. ELAYC successful compare request Description ag LL LL PDB_CLEAR_OVERFLOW NULL Clear the counter overflow interrupt 2 PDB_CNT_OVERFLOW_INT PDB_ENABLE PDB_DISABL Enable disable the counter overflow 2 interrupt PDB_GET_OVERFLOW NULL Get the counter overflow interrupt flag A PDB INIT NULL Initialize the PDB peripheral registers 2 using the appconfig h _INIT values PDB_MODULE PDB_ENABLE PDB_DISABL Enable disable the PDB module E When the module is disabled all Trig Y ger and PreTrigger outputs are low PDB READ COUNT NULL Read and return the PDB Counter reg 2 ister value as UWord16 PDB_READ_CTRLA_REG NULL Read and return the value of the Con 2 trol A register UWord16 PDB_READ_CTRLC_REG NULL Read and return the value of the Con 2 trol register UWord16 PDB READ MCTRL REG NULL Read and return the value of the Mas 2 ter Control register as UWord16 PDB_SELECT_LOAD_MODE PDB_LOAD_IMMEDIATELY Select the behavior of the PDB LOAD AFTER ROLL PDB SET LDOK command Use OVER PDB LOAD IMMEDIATELY to enable the DELAY and MOD regis ters to be loaded immediately after PDB SET LDOK command Use PDB LOAD AFTER ROLL OVER to load registers after calling the PDB SET LDOK command when the counter rolls over in continuous mode or when a trigger signal is received in one shot mode PDB SET CONTINUOUS MODE PDB ENABLE PDB DISABL Set continuous or one shot mode
170. ET MSCAN ON MSCAN OFF Set clear the Remote Transmit Request bit in the message identifier value of the specified Mes sage Buffer MSCANMB SET TBP UWord16 value 0 255 Set the local priority of the associated message buffer structure The local priority is used for the internal prioriti zation process of the CAN and is defined to be highest for the smallest binary number DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 115 5 1 21 On Chip Clock Synthesis OCCS Driver This section describes the DSP56800EX_Quick_Start API for the MC56F2xxx and MC56F84xxx OCCS on chip module The functionality of the OCCS module itself is described in the 56F82XXX Reference Manual MC56F82XXXRM or 56F84XXX Reference Manual MC56F84XXXRM This module provides the 2X system clock frequency to the System Integration Module SIM which generates the various derivative system and peripheral clocks for the chip The on chip clock synthesis module allows product design using several user selectable clock sources including an 8 MHz 400 kHz internal relaxation oscillator a 32 kHz internal RC oscillator 56F84xxx or a 200 kHz internal RC oscillator 56F82xxx an external clock input a 4 MHz to 16 MHz external crystal oscillator and a PLL to run up to a 100 MHz system bus frequency Table 5 47 shows module identifiers for OCCS Driver Table 5 47 Identif
171. Fractional2 Value3 and Fractional3 registers EFPWMS_CENTER_ALIGN_WRIT UWord16 Range 0 to 32767 Set Value2 and E CHANNEL 23 Value3 registers to generate center viv align output signal EFPWMS_CENTER_ALIGN_WRIT UWord16 Range 0 to 32767 Set Value4 and E CHANNEL 45 Value5 registers to generate center align output signal EFPWMS_CLEAR_SUBMODULE _ EFPWM xxx Clear selected interrupt flags note FLAGS RELOAD ERROR RELOAD All parameters are not supported in all COMPARE VALO COMPAR PWM submodules see documenta E VAL1 COMPARE VAL2 C tion VAL3 COMPARE ae _ VALA COMPARE VAL5 CA PTURE A1 CAPTURE AO0 C APTURE B1 CAPTURE B0 CAPTURE X1 CAPTURE X 0 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 57 Table 5 19 EFPWM Driver Commands _CHANNEL_45 representation registers Description ES 3 8 EFPWMS DEBUG OPERATION EFPWM STOP EFPWM RU Set PWM operation during chip PME N debugging EFPWMS CAPTURE DISAB EFPWM FIFO XO EF Disable DMA read requests for the LE FIFO BO EFPW Capture 0 1 0 1 0 1 FIFO M DMA AOJEFPWM the DMA Enable Register FIFO X1 EFPWM DM A FIFO B1 EFPWM _ FIFO A1 EFPWMS DMA CAPTURE ENAB EFPWM DMA FIFO XO EF Enable read requests for the LE FIFO BO EFPW Capture 0
172. Freescale Semiconductor Inc 5 81 Table 5 25 Driver Command Cmd pParam Description 56F82xxx FCAN_CLEAR_RXFIFO_FLAGS FCAN_RXFIFO_OVERFLO W_INT FCAN_RXFIFO_WA RNING_INT FCAN_FRAME S_IN_RXFIFO_INT Clear FIFO interrupts when operating in FIFO mode Note that FIFO mode is not supported by this version of the FCAN driver lt 56F84xxx This table shows the MB specific commands Use the constants or the value returned from FCAN_GET_MB_MODULE as the module identifier The Table 5 26 shows all MB specific commands dedicated for FCAN driver Table 5 26 FCAN driver MB specific commands Description LL LL io Lre FCANMB_GET_ID NULL Parse the ID from the appropriate bits v in given MB The returned value is numerical ID with FCAN ID EXT bit Set for extended frames FCANMB SET ID UWord32 ID value Optionally combined with Y FCAN ID EXT or FCAN ID RTR flags FCANMB SET ID V UWord32 ID value Optionally combined with Y FCAN ID EXT or FCAN ID RTR flags FCANMB SET RTR FCAN ON FCAN OFF Set or clear RTR bit in given MB Use before a frame is transmitted FCANMB_SET_LEN UWord16 frame length value Set data length field of the MB Use 0 8 before frame is transmitted FCANMB SET ID RAW UWord32 ID value in raw reg Set 32bit raw value into the ID register Y ister format of
173. GO AOI INVERT AO Set INPUT D of the Term 0 for 20152 NOTINVERT AOL LOG1 EVENTO SET EVENTO TERM combination of Set all inputs at once of the Term 1 for AOI INPUT n xxx n EVENTO C D xxx viv LOGO INVERT NOTIN VER LOG1 SET EVENTO TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT A of the Term 1 for 2014 NOTINVERT AOL LOG1 EVENTO SET EVENTO TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT B of the Term 1 for sly T_B NOTINVERT AOL LOG1 EVENTO AOI SET EVENTO TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT C of the Term 1 for PB TC NOTINVERT AOI LOG1 EVENTO AOI SET EVENTO TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT D of the Term 1 for iN T D NOTINVERT AOI LOG1 EVENTO AOI SET EVENTO TERM combination of Set all inputs at once of the Term 2 for AOI INPUT n xxx n EVENTO C D xxx viv LOGO INVERT NOTIN VER LOG1 SET EVENTO TERM 2 INPU AOI LOGO AOI INVERT AO Set INPUT_A of the Term 2 for E TA NOTINVERT AOI LOG1 EVENTO AOI SET EVENTO TERM 2 INPU AOI LOGO AOI INVERT AO Set INPUT B of the Term 2 for PN T B NOTINVERT AOI LOG1 EVENTO AOI SET EVENTO TERM 2 INPU AOI LOGO AOI INVERT AO Set INPUT C of the Term 2 for TC NOTINVERT AOI LOG1 EVENTO AOI SET EVENTO TERM 2 INPU AOI LOGO AOI INVERT AO Set INPUT D of the Term 2 for FX T D NOTINVERT AOI LOG1 EVENTO DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 81 Table
174. IAL CODE LIMITATION OF LIABILITY INNO EVENT WILL FREESCALE BE LIABLE WHETHER IN CONTRACT TORT OR OTHERWISE FOR ANY INCIDENTAL SPECIAL INDIRECT CONSEQUENTIAL OR PUNITIVE DAMAGES INCLUDING BUT NOT LIMITED TO DAMAGES FOR ANY LOSS OF USE LOSS OF TIME INCONVENIENCE COMMERCIAL LOSS OR LOST PROFITS SAVINGS OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW COMPLIANCE WITH LAWS EXPORT RESTRICTIONS You must use the Software in accordance with all applicable U S laws regulations and statutes You agree that neither you nor your licensees if any intend to or will directly or indirectly export or transmit the Software to any country in violation of U S export restrictions GOVERNMENT USE Use of the Software and any corresponding documentation if any is provided with RESTRICTED RIGHTS Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph 1 11 of The Rights in Technical Data and Computer Software clause at DFARS 252 227 7013 or subparagraphs c 1 and 2 of the Commercial Computer Software Restricted Rights at 48 CFR 52 227 19 as applicable Manufacturer is Freescale Semiconductor Inc 6501 William Cannon Drive West Austin TX 78735 HIGH RISK ACTIVITIES You acknowledge that the Software is not fault tolerant and is not designed manufactured or intended by Freescale for incorporation into products intended for use or resale in on line control equipment in
175. INPUT xxx Set XBAR B OUTO input A XBAR B SET OUT AOI O A XBAR B INPUT xxx Set XBAR B OUTO input B SET OUT AOI XBAR B INPUT xxx Set XBAR B OUT input B SET OUT AOI XBAR B INPUT xxx Set XBAR B OUT input SET OUT AOI O C XBAR B INPUT xxx Set B 2 input A XBAR B SET OUT AOI O C XBAR B INPUT xxx Set B OUT 2 input A XBAR B SET OUT AOI O D XBAR B INPUT xxx Set B OUTS3 input A XBAR B SET OUT AOI O D XBAR B INPUT xxx Set B OUT3 input B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B Ses G 0 Select Register 0 XBAR B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B p G 1 Select Register 1 XBAR B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B E G2 Select Register 2 XBAR B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B M Select Register 3 XBAR B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B 201152 4 Select Register 4 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 176 Freescale Semiconductor Inc Table 5 64 Driver Commands Description m 5 lt i XBAR B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B PA I G5 Select Register 5 XBAR B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B G6 Select Regis
176. ION one of SYS COPAD xxx Package pin function selection 2 EXTAL CLKIN SYS SET COPAD FUNCTION one of SYS COPAD xxx Package pin function selection 5 EXTAL CLKIN SYS SET C10PAD FUNCTION one of SYS C10PAD xxx Package pin function selection MASK MOSIO XB IN5 MIS Y 00 SYS SET C10PAD FUNCTION one of SYS C10PAD xxx Package pin function selection XB OUT9 MOSIO XB IN5 Y MISOO SYS SET C11PAD FUNCTION one of SYS C11PAD xxx Package pin function selection SCL1 TXD1 CANTX SYS SET C11PAD FUNCTION one of SYS C11PAD xxx Package pin function selection 2 TXD1 SCLO SYS SET C12PAD FUNCTION one of SYS C12PAD xxx Package pin function selection 2 CANRX SDA1 RXD1 SYS SET C12PAD FUNCTION one of SYS C12PAD xxx Package pin function selection 2 SDAO RXD1 SYS SET C13PAD FUNCTION one of SYS C13PAD xxx Package pin function selection 2 1 6 SYS SET C13PAD FUNCTION one of SYS C13PAD xxx Package pin function selection 2 TA3 XB_IN6 EWM_OUTB DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 156 Freescale Semiconductor Inc Table 5 62 SYS Driver Commands x x x amp x X Cmd pParam Description 1 2 5 5 ive Lre SYS SET C14PAD FUNCTION one of SYS C14PAD xxx Package pin function selection 2 SDAO XB OUTA SYS SET C14PAD FUNCTION one of SYS C14PAD xxx Package pin function selection SDAO XB OUT4 PWM FAU Y LT4 SYS SE
177. ION_ACTIVE_ combination of BIT_x Set the selected GPIO pins to be HIGH x 0 1 15 active high by modifying the content of v v the Interrupt Polarity Register GPIO_INT_DETECTION_ACTIVE_L combination of BIT_x Set the selected GPIO pins to be OW 0 1 15 active low by modifying the content of v v the Interrupt Polarity Register GPIO INT DISABLE combination of BIT x Disable an interrupt request generated 0 1 15 by a pin by modifying the By content of the Interrupt Enable Register GPIO_INT_ENABLE combination of BIT_x Enable an interrupt request generated 0 1 15 by a by modifying the AE content of the Interrupt Enable Register GPIO PULLUP DISABLE combination of BIT x Disable pull up on the selected pins by 0 1 15 modifying the content of the Pull Up viv Enable Register GPIO_PULLUP_ENABLE combination of BIT_x Enable pull up on the selected pins by 0 1 15 modifying the content of the Pull Up Enable Register GPIO_READ_DATA NULL Read and return the whole GPIO port by reading the GPIO Data Register GPIO_READ_INT_PENDING_REG NULL Read and return the whole content of Pill ay the Interrupt Pending Register GPIO_READ_RAW_DATA NULL Read and return the logic value of each GPIO pin from the GPIO Raw Data Register even when pins arenot v v in GPIO mode This command reads the DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 8
178. L NULL initialize and configure GPIO ports init gpio configure Interrupt Controller ioctl INTC INTC INIT NULL enable interrupts in archEnableInt while 1 wait while for i 0 1 lt 100 i archDelay Oxffff SR toggle green indicator D8 ioctl GPIO LED G2 GP service COP ioctl COP COP CLEAR COUNTI IO TOGGLI E PIN 11 ED G2 ER NULL GPIO port C interrupt service routine toggles LED Y2 pragma interrupt void gpio_c_isr void UWordl16 irqs ioctl GP toggle LEDs if irqs amp BIN 1 ioctl GPIO LED Y2 IO 1 GPIO READ INT PENDING REG NULL GPIO_TOGGLI E PIN LED Y2 5 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 43 clear interrupt flags ioctl GPIO BTN 1 GPIO CLEAR INT PENDING irqs pragma interrupt off GPIO port interrupt service routine toggles LED R2 x pragma interrupt void gpio_f_isr void UWordl6 irgs ioctl GPIO BTN 0 GPIO READ INT PENDING REG NULL toggle LEDs if irqs amp BIN 0 ioctl GPIO LED R2 GPIO TOGGLE PIN LED R2 clear interrupt flags ioctl GPIO BTN 0 GPIO CLEAR INT PENDING irqs pragma interrupt off Initialize the GPIO ports void init_gpi
179. L Register the specified interrupt as the fast interrupt 0 INTC_SET_FASTINTO_VEC ISR address Set the fast interrupt 0 ISR handler siy address INTC_SET_FASTINT1 NULL Register the specified interrupt as the 21 24 fast interrupt 1 INTC_SET_FASTINT1_VEC ISR address Set the fast interrupt 1 ISR handler viv address INTC_SET_IPL_n interrupt parameter Set the interrupt priority level for given is one of INTC_DISABLED or interrupt The command writes the IPL MB LEVELx 0 1 2 3 bits in the Interrupt Priority Register for the interrupt number n SET n RAW n given interrupt parameter Set one of priority levels Disabled is a two bit IPL value in the Level 0 1 and 2 Note that for some IPR register system interrupts the Level 0 is not viv allowed and the two bit value assigns priority levels DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 102 Freescale Semiconductor Inc 5 1 19 Miscellaneous Control Module Driver The Miscellaneous Control Module MCM provides a myriad of miscellaneous control functions The MCM provides the following features e Program visible information about the configuration and revision of the core and select system peripherals Registers for capturing information on platform bus errors if enabled e Control and configuration of memory resource protection Restriction The MCM is a supervisor only
180. Low byte register This register is using for finish the CRC generator ini v tialization and for writing the data to generate CRC error check code WRITE CRC HIGH REG UWord16 value 0 255 Write the parameter value into the CRC High byte register To complete the CRC generator initialization the 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 38 Freescale Semiconductor Inc Table 5 11 CRC Driver Commands Description ag 55 ive CRC_WRITE_CRC_LOW_REG UWord16 value 0 255 Write the parameter value into the CRC Low byte register This register is using for the CRC generator initializa v tion and for writing the data to gener ate CRC error check code CRC WRITE CRC REG UWord32 Write the CRC Data register A CRC WRITE CRC TRANSPOSE UWord16 Write the CRC Transpose register This register is used to convert data Y from MSb to LSb CRC WRITE CRC TRANSPOSED UWord16 value 0 255 Write the parameter value data in to DATA transpose register transposed data Y are written into CRC low byte WRITE CTRL REG UWord32 Write the CRC Control register A CRC WRITE GPOLY REG UWord32 Write the CRC Polynomial register CRC_WRITE_HIGH_POLYNOMINA UWord16 Write the parameter value into higher L Word of the CRC Polynominal regis Y ter WRITE INIT VALUE UWord16 Initialize the CRC function 4 CRC WRITE
181. MODULE 1 Ew PWM SUBMODULE 2 EFP WM SUBMODULE 3 EFPWM SET SUBO FORCE OUT EFPWM SOURCE XXX Set force out source 23 PWM INV_PWM SWOUT E viv XT EFPWM SET SUBO FORCE OUT EFPWM SOURCE XXX Set force out source 45 PWM INV_PWM SWOUT E viv XT EFPWM SET SUB1 FORCE OUT EFPWM SOURCE XXX Set force out source 23 PWM INV_PWM SWOUT E viv XT EFPWM SET SUB1 FORCE OUT EFPWM SOURCE XXX Set force out source 45 PWM INV_PWM SWOUT E viv XT EFPWM SET SUB2 FORCE OUT EFPWM SOURCE XXX Set force out source 23 PWM INV_PWM SWOUT E viv XT EFPWM SET SUB2 FORCE OUT EFPWM SOURCE XXX Set force out source 45 PWM INV_PWM SWOUT E viv XT EFPWM SET 5 FORCE OUT EFPWM SOURCE XXX Set force out source 23 PWM INV PWM SWOUT E viv XT EFPWM SET 50 3 FORCE OUT EFPWM SOURCE XXX Set force out source 45 PWM INV_PWM SWOUT E viv XT EFPWM TEST FAULT FLAGS EFPWM FAULT 0 1 2 3 Return state of selected fault flags viv DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 55 Table 5 19 EFPWM Driver Commands Description ag Lre EFPWM_TEST_FAULT_PINS EFPWM_FAULT_X 0 1 2 3 Return state of filtered fault pins viv EFPWM TEST FAULTO FLAGS EFPWM FAULT 0 1 2 3 Return state of selecte
182. MP SET OUTPUT ACTIVE HSCMP ENABLE HSCMP _ Enable disable the comparator ouput viv DISABLE pin HSCMP SET OUTPUT PIN HSCMP COUT HSCMP CO The parameter HSCMP COUT sets UTA CMPO to filtered comparator output COUT The HSCMP COUTA viv selects unfiltered comparator output HSCMP SET SAMPLE HSCMP ENABLE HSCMP Enable disable the sample mode at DISABLE the high speed comparator module HSCMP_SET_WINDOWING HSCMP ENABLE HSCMP Enable disable the windowing mode at 2422 DISABLE the high speed comparator output HSCMP_TEST_INT_FLAGS HSCMP_FLAG_RISING_ED Test and returns the value of the GE HSCMP_FLAG_FALLIN selected comparator interrupt flag DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 92 Freescale Semiconductor Inc Table 5 36 Driver Commands Description ag LL LL HSCMP_TEST_OUTPUT NULL Return zero nonzero current compara 2154 tor output state HSCMP_WRITE_FILT_COUNTER HSCMP_FILTER_COUNTE Set the filter counter R x x 0 7 HSCMP WRITE FILT REG UWord16 Write directly to the Filter Period Reg ister The comparator output signal can be filtered by applying a digital counting filter The FPR register con tains the filter sample period value so this command may be used to recon figure the filter in run time DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 93 Fre
183. MSTR Poll function must be called at least once per Tchar time In the FMSTR LONG INTR mode the complete process described above is performed during the SCI or JTAG interrupt There is no need to call the FMSTR Poll function at all and it is actually compiled to an empty function You can still have the function being called in the application main loop to make the code independent on interrupt mode selected Returns None Range Issues None Special Issues None Design Implementation None Example 6 2 FMSTR Poll for FMSTR_Poll DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 13 Freescale Semiconductor Inc This code demonstrates the usage of the FMSTR_Poll API function DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 14 6 6 1 3 FMSTR 15 FreeMASTER interrupt dispatcher Call pragma interrupt void FMSTR_Isr void Arguments None Description Except when the driver is configured for the FMSTR_POLL_DRIVEN mode the FMSTR Isr function must be used as the SCI or JTAG interrupt service routine in the application This function handles the SCI or JTAG communication for the FMSTR SHORT INTR and FMSTR LONG INTR modes Returns None Range Issues None Special Issues None Design Implementation None Example 6 3 FMSTR_Isr define INT VECTOR ADDR 4 FMSTR Isr define INT PRI
184. NAO ANA7 or ANAO ANA7 to DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 16 Freescale Semiconductor Inc Table 5 3 ADC Driver Commands x x xX Description ag 6 Lre ADC_WRITE_CHANNEL_LIST3 ADC_ANAx_Sy x 0 7 Configures mapping of the physical y 8 11 inputs ANAO ANA7 or ANAO ANA7 to 3 5 0 7 samples 8 11 8 11 ADC WRITE CHANNEL LISTA Sy 0 7 Configures mapping of the physical 12 15 inputs ANAO ANA7 or ANAO ANA7 to 2 ADC_ANBx_Sy x 0 7 samples 12 15 y 12 15 ADC_WRITE_CHANNEL_LIST5 ADCx_yyy_Sz x A B Write ADC channel list 5 register yyy TEMPERATURE_SENS Modify the ADC Channel List Register OR ANALOG_INPUT 5 2 16 19 ADC WRITE GAIN CONTROL 1 UWord16 Write the Gain Control Register 1 21 ADC_WRITE_GAIN_CONTROL_2_ UWord16 Write the Gain Control Register 2 ADC_WRITE_GAIN_CONTROL_3_ UWord16 Write the Gain Control Register 3 2 ADC_WRITE_HIGH_LIMITO UWord16 Write High Limit Register for sample 0 v v ADC WRITE HIGH LIMIT1 UWord16 Write High Limit Register for sample 1 v v ADC WRITE HIGH LIMIT10 UWord16 Write High Limit Register for sample 10 ADC_WRITE_HIGH_LIMIT11 UWord16 Write High Limit Register for sample sy 11 ADC_WRITE_HIGH_LIMIT12 UWord16 Write High Limit Register for sample
185. Number Title Number Chapter 4 Developing Software 4 1 4 1 4 2 On chip peripheral 4 5 4 3 On chip drivers interface 4 6 4 3 1 os PAP ME 4 6 4 3 2 4 7 4 3 3 4 8 4 4 Interrupts and Interrupt Service 4 8 4 5 alaia eelt fenni e Ara E EAE A I A AY 4 8 Chapter 5 On chip Drivers 5 1 E AN 5 4 5 1 1 12 bit Cyclic Analog to Digital Converter ADC Driver 5 6 5 1 2 16 bit SAR Analog to Digital Converter 16 5 23 5 1 2 Crossbar AND OR INVERT AOI 5 30 5 1 4 Computer Operating Properly COP 5 35 5 1 5 Cyclic Redundancy Check CRO 5 37 5 1 6 12 bit Digital to Analog Converter DAC 5 40 517 DMA Controller DMA 5 DVE 5 43 5 1 8 Enhanced Flexible Pulse Width Modulator EFPWM 5 48 5 1 9 Enhanced Quadrature Encoder Decoder 5 68 5 1 10 External Watch
186. O EFPWMS_READ_EDGE_COUNTE NULL Return Edge counter value sly R_A EFPWMS_READ_EDGE_COUNTE NULL Return Edge counter value Xe R B EFPWMS READ EDGE COUNTE NULL Return Edge counter value 4x EFPWMS_READ_INIT_REG NULL Return Word16 from the Init Register viv EFPWMS READ VALUE REG 0 NULL Return Word16 from Value Register O v v EFPWMS READ VALUE REG 1 NULL Return Word16 from Value Register 1 v v EFPWMS READ VALUE REG 2 NULL Return Word16 from Value Register 2 v EFPWMS READ VALUE REG 3 NULL Return Word16 from Value Register 3 v v EFPWMS READ VALUE REG 4 NULL Return Word16 from Value Register 4 v v EFPWMS READ VALUE REG 5 NULL Return Word16 from Value Register5 v v EFPWMS SET CAPTURE A 0 EFPWM CAPTURE 0 XXX input capture A 0 edge sensitivity DIS ABLE FALLING_EDGE RISI NG_EDGE ANY_EDGE EFPWMS SET CAPTURE A 1 EFPWM CAPTURE 1 XXX input capture A 1 edge sensitivity DIS viv ABLE FALLING_EDGE RISI NG_EDGE ANY_EDGE EFPWMS SET CAPTURE A FIFO UWord16 Value 0 to 3 824 5 value 0 to 1 _WATERMARK EFPWMS_SET_CAPTURE_A_INP EFPWM_RAW_INPUT EFP Set input capture A source 2512 UT WM_EDGE_COUNTER EFPWMS SET CAPTURE A EFPWM FREE RUNNING Set capture mode sly DE EFPWM_ONE_SHOT EFPWMS SET CAPTURE B 0 EFPWM CAPTURE 0 XXX Set input capture B 0 edge sensitivity DIS viv 5 62 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands
187. O INIT initial value for Fast Interrupt Match register 0 interrupt number 1 80 define INTC 1 INIT initial value for Fast Interrupt Match register 1 interrupt number 1 80 DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 5 Freescale Semiconductor Inc define INTC_FIVAO_INIT optional addr of fast int 0 handler appropriate INT VECTOR ADDR n used if this is not Specified define INTC FIVA1 INIT optional addr of fast int 1 handler appropriate INT VECTOR ADDR n used if this is not Specified Ef 4 3 On chip drivers interface description The DSC56800EX Quick Start includes a set of on chip drivers which are used to initialize to configure and to access the on chip peripherals The on chip drivers provide a C language Application Programming Interface to the peripheral module see Figure 4 5 This interface is common for all input output operations User Application On chip Driver API M Peripheral Module Figure 4 5 User Interface This interface provides the following API statements ioctl to initialize and to access peripheral module read e g to receive data write e g to transmit data The philosophy of all input output operations resides in these three statements commands These commands provide better code portability between the processors from the same family where the base addresses of th
188. O PWM X SUB1 PW M X A B X EFPWM_SUB2_ PW M X A B X EFPWM_SUB3_PW M Masks selected PWM outputs EFPWM_SET_OUTPUTS EFPWM_SUBO_PWM_X_EN ABLE A B X EFPWM_SUBO_PW DISABLE EFPWM_SUB1_PW ENABLE EFPWM_SUB1_PW X DISABLE AIBIX EFPWM SUB2 PW ENABLE JEFPWM SUB2 PW DISABLE JEFPWM SUB3 PW X ENABLE SUB3 PW M X ENABLE A BIX Enable disable selected PWM out puts at selected submodules EFPWM SET OUTPUTS DISABL E EFPWM SUBO PWM X A B X EFPWM_SUB1_PW M_X A B X EFPWM_SUB2_PW M_X A B X EFPWM_SUB3_ PW M Disable selected PWM outputs at selected submodules DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 54 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands Description ag 5 ive EFPWM SET OUTPUTS ENABLE EFPWM SUBO PWM X Enable selected PWM outputs at AJB X EFPWM SUB1 PW selected submodules MX SUB2 PW 1 M_X A B X EFPWM_SUB3_PW M X A B X EFPWM SET CLOCK DISA EFPWM SUBMODULE Set PWM generator clock disable BLE FPWM SUBMODULE 1 viv PWM SUBMODULE 2 EFP WM SUBMODULE 3 EFPWM SET PWM CLOCK ENA EFPWM SUBMODULE O E Set PWM generator clock enable BLE FPWM SUB
189. OCCS_ENABLE OCCS_DIS ABLE Enable disable the clock checking function This command enables clock checking function and resets counters REF_COUNT and TARGET_CNT when parameter is OCCS_ENABLE When clock checking function fin ished bit CHK_ENA is cleared and in counters REF_COUNT and TARGET_CNT are valid values The parameter OCCS_DISABLE stops the clock checking function OCCS_SET_CORE_CLOCK combination UWord16 value 1 64 and OCCS_CLOCK_IN_DIVIDE 1 2 4 8 16 32 64 128 256 Configure the OCCS module to the most frequently used mode when the PLL block provides clock to the DSC core ZCLOCK Source is set to Postscaler output First the command sets the ZCLOCK Source to Prescaler output and turns the lock detector on Then it writes the param value to the PLL Divide by Register and it waits until the PLL is locked Finally it switches the ZCLOCK Source to the Postscaler output OCCS SET DIVIDE BY UWord16 value 0 63 Set the PLL Divide by value This command writes the parameter to the PLL Divide by register Use this com mand only when ZCLOCK Source is set to MSTR clock OCCS SET LORTP UWord16 value 1 15 Set the loss of reference clock trip point The parameter controls the amount of time required for the loss of reference clock interrupt to be gener ated It s recommended to keep the value of LORTP gt 2 OCCS SET POSTSCALER OCCS CLOCK OUT DIVID E BY x 1 2 4 8
190. ODULE 3 EFPWM EDGE ALIGN UPDATE pwm slndependentValues Set PWM Submodule 0 1 and 2 out VALUE REGS INDEP 012 puts in independent mode and set viv LDOK bit afterwards EFPWM EDGE ALIGN UPDATE pwm slndependentValues Set PWM Submodule 0 1 and 3 out VALUE REGS INDEP 013 puts in independent mode and set viv LDOK bit afterwards EFPWM EDGE ALIGN UPDATE pwm slndependentValues Set PWM Submodule 0 1 and 3 out VALUE REGS INDEP 023 puts in independent mode and set LDOK bit afterwards EFPWM FAULT FILTER COUNTE EFPWM SAMPLES X Set number of samples to the input fil 21 42 3 4 5 6 7 8 9 10 ter accepting an input transition EFPWM FAULT FILTER PERIOD UWord16 Value 0 to 255 viv EFPWM FAULT GLITCH STRETC EFPWM_ENABLE EFPWM_ Enable disable Fault glitch stretching PIN H DISABLE EFPWM FAULT INT DISABLE EFPWM FAULT 0 1 2 3 Disable fault interrupt viv EFPWM_FAULT_INT_ENABLE EFPWM FAULT X 0 1 2 3 Enable fault interrupt viv EFPWM FAULTO FILTER COUNT EFPWM SAMPLES X Set number of samples to the input fil v og ER 3 4 5 6 7 8 9 10 ter accepting an input transition DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 49 Table 5 19 EFPWM Driver Commands L_REG Description ag Lre EFPWM_FAULTO_FILTER_PERIO UWord16 Value 0 to 255 P D EFPWM FAULTO GLITCH
191. ORITY LEVEL 47 INTC_LEVEL1 define INT_VECTOR_ADDR_48 FMSTR_Isr define INT PRIORITY LEVEL 48 LEVEL1 define INT VECTOR ADDR 50 FMSTR Isr define INT PRIORITY LEVEL 50 LEVEL1 This appconfig h code shows how the FMSTR Isr is set as 1 TX Empty RX Full and RX Error interrupt service routine in the 56F82748 project DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 15 Freescale Semiconductor Inc 6 6 1 4 FMSTR Recorder FreeMASTER recorder engine Call pragma interrupt called void FMSTR Recorder void Arguments None Description This function takes one sample of variable values being recorded using the FreeMASTER recorder In case the recorder is not active at the moment when FMSTR Recorder 1s called the function returns immediately When the recorder is active the values of variables being recorded are copied to the recorder buffer and the trigger condition is evaluated In case the trigger condition is satisfied the recorder enters the post trigger mode in which it counts the follow up samples FMSTR Recorder function calls and de activates the recorder when required post trigger samples are sampled Typically you call the FMSTR Recorder function in the Timer or PWM interrupt service routine For simple test purposes this function can also be called in the application main loop Returns None Range Issues None Special Issues None Design Implem
192. OUT12 input 2 XBAR_A_SET_OUT_ADCB_TRIGG Set XBAR_A_OUT13 input XBAR_A_SET_OUT_ADCB_TRIGG Set XBAR_A_OUT13 input XBAR_A_SET_OUT_ADCC_TRIGG INPUT Set XBAR_A_OUT14 input 2 SET OUT SAMP INPUT Set XBAR_A_OUT16 input 2 SET OUT SAMP INPUT Set XBAR_A_OUT16 input 2 SET OUT CMPB SAMP XBAR A INPUT xxx Set OUT17 input 2 SET OUT SAMP INPUT Set XBAR_A_OUT17 input m LE A SET OUT CMPC SAMP A INPUT xxx Set 18 input LE DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 167 Table 5 64 Driver Commands Description 5 5 8 SET OUT SAMP XBAR A INPUT xxx Set OUT18 input LE XBAR SET_OUT_CMPD_SAMP XBAR_A_INPUT_xxx Set XBAR_A_OUT19 input 2 SET_OUT_CMPD_SAMP XBAR_A_INPUT_xxx Set XBAR_A_OUT19 input LE XBAR A SET OUT DAC SYNC XBAR A INPUT xxx Set OUT15 input v XBAR A SET OUT DACA SYNC XBAR A INPUT xxx Set OUT15 input v XBAR SET OUT DACB S
193. P Bus clock divided by pres caler value DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 124 Freescale Semiconductor Inc 5 1 23 Power Management Controller PMC Driver This specification details the on chip power management controller module This module contains the core voltage regulators and power monitoring circuitry Its function is to ensure that the chip is operated only within legal voltage ranges and to assist in the orderly shutdown of the chip in the event that the power supply is interrupted It also regulates the internal voltage rails for the core digital and analog logic The Table 5 51 shows module identifiers for PMC Driver Table 5 51 Identifiers for PMC Driver Module identifier 56F82xxx 56F84xxx PMC Y Y Table 5 52 shows all commands dedicated for Driver Table 5 52 PMC Driver Commands Description P BE LL LL PMC_CLEAR_LOW_VOLTAGE_IN combination of PMC_xxx Clear the selected low voltage inter xxx LVI 27V_LEVEL 22V_L rupt flags This command be used EVEL for example in the LVI interrupt service v routine to clear low voltage interrupt flags PMC CLEAR STICKY FLAG combination of Clear the selected sticky low voltage PMC STICKY xxx FLAG flags The flags indicate that supply xxx LV22 LV27 voltage dropped be
194. PLL Divide By register to the value 10 Other bits in the register are not affected DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 18 Freescale Semiconductor Inc 2 5 13 periphBitGrpSet set bit group to given value Call s void periphBitGrpSet UWord16 GroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 15 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpSet macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared This macro uses a single instruction to execute the operation and allows only constants as GroupMask and Mask arguments If the application requires the variable as argument the periphBitGrpSetVar macro must be used instead Example 2 30 periphBitGrpSet macro usage periphBitGrpSet 0 007 10 amp ArchlIO Pll plldb This code sets the lower 7 bits of PLL Divide By register to the value 10 Other bits in the register are not affected but see Caution above 2 5 14 periphBitGrpSetVar set bit group to given value Call s void periphBitGrpSetVar UWord16 GroupMask 16 Mask UWordl16 pAddr Arguments Table 2 16 periphBitSet arg
195. PWM_SUB1_PWM4 5 SOURCE xxx PWM INV PWM SWOUT EXT EFPWM SUBO 2 3 SOURCE xxx PWM INV PWM SWOUT EXT EFPWM SUBO 4 5 SOURCE xxx PWM INV PWM SWOUT EXT Set Force Out mode EFPWM SET FORCE OUT SW SOURCE TO HIGH EFPWM SUBO PWMXX 23145 5081 23 45 EFPWM SUB2 PWMXX 23 45 EFPWM SUB3 PW 23145 Set Force Out software level to high EFPWM_SET_FORCE_OUT_SW SOURCE_TO_LOW EFPWM SUBO PWMXX 2345 EFPWM SUB1 PWMXX 23 45 EFPWM SUB2 PW MXX 23 45 EFPWM SUB3 PW 23145 Set Force Out software level to high EFPWM_SET_LOAD_OK EFPWM SUBMODULE FPWM SUBMODULE 1 EF PWM SUBMODULE 2 WM SUBMODULE 3 Set selected LDOK request EFPWM SET MANUAL FAULT C LEAR EFPWM SET MANUAL FAULTO _ CLEAR EFPWM 0111213 EFPWM FAULT 0 1 213 Set manual fault clearing Set manual fault clearing DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 53 Table 5 19 EFPWM Driver Commands Cmd pParam Description 56F82xxx 56F84xxx EFPWM_SET_MANUAL_FAULT1_ CLEAR EFPWM 0 1 213 Set manual fault clearing lt lt EFPWM_SET_MASK_DISABLE EFPWM SUBO PWM X A B X EFPWM_SUB1_PW M_X A B X EFPWM_SUB2_ PW M_X A B X EFPWM_SUB3_ PW M Set normal PWM outputs EFPWM_SET_MASK_ENABLE EFPWM SUB
196. Polarity Active high Output Mode Push pull Pin 7 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 8 Function GPIO Direction Input PullUp Disable Int Polarity Active high interrupt Disable interrupt Disable e define GPIO F DDR INIT 0x0040U define GPIO PER INI 0x0030U 135 Configuration Monitor PLL State Not locked No PLL check Fault0O Level Low Faultl Level Low Fault2 Level Low Fault3 Level Low FaultO Clearing Manual Faultl Clearing Manual Fault2 Clearing Manual Fault3 Clearing Manual FaultO Safety Mode Normal Faultl Safety Mode Normal Fault2 Safety Mode Normal Fault3 Safety Mode Normal Fault Enable Mode None None None None None Fault Glitch Stretching Enabled DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 12 Fault Filter Period 0 Fault Filter Count 3 Fault 0 Pin Disabl Fault 1 Pin Disabl Fault 2 Pin Disabl Fault 3 Pin Disabl 0 000 Disable Pins by Fault Fau Disable Pins P by Fault Fau Disable Pins P by Fault Fau TO Disable Pins Disable Pins Disable Pins Disable Pins by Fault Fau by Fault PWMA State
197. QT A2 IN XBAR A INPUT xxx Set A OUT51 input v XBAR A SET OUT QT A2 IN XBAR A INPUT xxx Set A input A XBAR A SET OUT QT A3 IN XBAR A INPUT xxx Set A OUT52 input A XBAR A SET OUT QT A3 IN XBAR A INPUT xxx Set OUT37 input A XBAR A SET OUT QT BO IN XBAR A INPUT xxx Set XBAR A OUT34 input v XBAR A SET OUT QT B1 IN XBAR A INPUT xxx Set OUT35 input v XBAR A SET OUT QT B2 IN XBAR A INPUT xxx Set OUTS96 input SET OUT B3 IN XBAR A INPUT xxx Set A OUT37 input A XBAR A SET OUT SCIO RXD XBAR A INPUT xxx Set 138 input A A SET OUT 501 RXD XBAR A INPUT xxx Set A 139 input A XBAR A SET PDB1 TRIGO XBAR A INPUT xxx Set XBAR A OUTA1 input v XBAR A WRITE CROSSBAR CT UWord16 Write the Crossbar A Control Register rs RL 0 0 XBAR A WRITE CROSSBAR CT UWord16 Write the Crossbar A Control Register RL_1 1 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register NS 0 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 172 Freescale Semiconductor Inc Table 5 64 Driver Commands Description ag 515 i XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 22 G 1 1 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select R
198. R B INPUT xxx Set XBAR B OUTS input Y XBAR B SET OUT AOI 2 A XBAR B INPUT xxx Set XBAR B OUTS input Y XBAR B SET OUT AOI 2 B XBAR B INPUT xxx Set B input Y XBAR B SET OUT AOI 2 B XBAR B INPUT xxx Set B input A XBAR B SET OUT AOI 2 C XBAR B INPUT xxx Set OUTI10 input A XBAR B SET OUT AOI 2 C XBAR B INPUT xxx Set OUTI10 input A XBAR B SET OUT AOI 2 D XBAR B INPUT xxx Set B OUT 11 input Y XBAR B SET OUT AOI 2 D XBAR B INPUT xxx Set B OUT 11 input Y XBAR B SET OUT AOI 3 A XBAR B INPUT xxx Set B OUT12 input Y DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 175 Table 5 64 Driver Commands x x Description ag 5 lt SET OUT AOI 3 XBAR B INPUT xxx Set B OUT12 input A XBAR B SET OUT AOI 3 B XBAR B INPUT xxx Set B 13 input A XBAR B SET OUT AOI 3 B XBAR B INPUT xxx Set B OUT13 input B SET OUT AOI 3 C XBAR B INPUT xxx Set 14 input SET OUT AOI 3 C XBAR B INPUT xxx Set 14 input A XBAR B SET OUT AOI 3 D XBAR B INPUT xxx Set OUT 15 input A XBAR B SET OUT AOI 3 D XBAR B INPUT xxx Set OUT 15 input A XBAR B SET OUT AOI O A XBAR B
199. R TSA USERTYPE INNER STRUCT FMSTR TSA MEMBER OUTER STRUCT FMSTR TSA USERTYPE INNER STRUCT FMSTR TSA STRUCT INNER STRUCT FMSTR TSA MEMBER INNER STRUCT aa PMSTR TSA UINT16 FMSTR TSA MEMBER INNER STRUCT bb FMSTR_TSA_UINT32 FMSTR TSA MEMBER INNER STRUCT cc PMSTR TSA SINT16 FMSTR TSA MEMBER INNER STRUCT dd PMSTR TSA SINT32 FMSTR TSA MEMBER INNER STRUCT ee FMSTR_TSA_UINTS8 FMSTR TSA MEMBER INNER STRUCT ff FMSTR TSA 5 8 FMSTR TSA TABLE END This is an example of another TSA table Typically you put one table to each c file where your global or static variables are instantiated FMSTR TSA TABLE BEGIN next table FMSTR TSA RO 502 FMSTR TSA USERTYPE OUTER_STRUCT FMSTR TSA RO VAR si2 FMSTR TSA USERTYPE INNER STRUCT FMSTR TSA TABLE END DSC56800EX Quick Start User s Guide Rev 2 04 2015 TSA 6 33 Freescale Semiconductor Inc This list describes all TSA tables which should be exported to the FreeMASTER application FMSTR TSA TABLE LIST BEGIN FMSTR TSA TABLE first table FMSTR TSA TABLE next table FMSTR TSA TABLE LIST END This function is r
200. RT ADDR LO NULL Get I O short address mode base V CATION REG address as UWord32 SYS READ LSH JTAG ID NULL Return JTAG ID UWord16 viv SYS_READ_MSH_JTAG_ID NULL Return JTAG ID as UWord 16 viv DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 154 Freescale Semiconductor Inc Table 5 62 SYS Driver Commands Description e re SYS_READ_SW_CONTROL_REGO NULL Read and return SIM software control PAP register 0 as UWord16 SYS READ SW CONTROL NULL Read and return SIM software control XE register 1 as UWord16 SYS READ SW CONTROL REG2 NULL Read and return SIM software control sly register 2 as UWord16 SYS READ SW CONTROL REG3 NULL Read and return SIM software control register 3 UWord16 SYS_READ_SW_CONTROL_REG4 NULL Read and return SIM software control register 4 as UWord16 SYS READ SW CONTROL REG5 NULL Read and return SIM software control register 5 as UWord16 SYS READ SW CONTROL REG6 NULL Read and return SIM software control register 6 UWord16 SYS READ SW CONTROL REG7 NULL Read and return SIM software control 2 register 7 UWord16 SYS_RST_FLT SYS_ENABLE SYS_DISABL External Reset Padcell Input Filter Pail E Enable SYS_SELECT_CLKIN SYS_CLKINO SYS_CLKIN1 Determine the GPIO port used for the CLKIN input to the OCC
201. RY_TRIM_TEMP 1 LE SYS Configuration SIM Power Saving Modes Stop enabled Wait enabled OnCE clock to processor core Enabled when core TAP enabled DMA Enable in RUN and WAIT modes DMA enabled in all power modes Enable External Reset Padcell Input Filter No SIM Clock on GPIO Enable CLKO 0 No SIM Clock on GPIO Enable CLKO 1 No SIM HS PERF Peripheral Clk PWM SIM Peripheral Clock Enable GPIO F Yes GPIO E Yes GPIO D No No GPIO No TMR 0 No TMR Al TMR A2 No TMR No SCIO SCI1 QSPIO No QSPI1 No IIC No MSCAN No No B No C No D CYC ADC No CRC No QDC No PITO No PIT1 No DACA DACB No PWMCHO No PWMCH1 No PWMCH2 No PWMCH3 No SIM Modules Enabled in Stop GPIO F No SIM Modules Enabled in Stop GPIO E No SIM Modules Enabled in Stop GPIO D No SIM Modules Enabled in Stop GPIO C No SIM Modules Enabled in Stop GPIO B No SIM Modules Enabled in Stop GPIO A No SIM Modules Enabled in Stop TMR A0 No TMR A1 No TMR A2 No TMR A3 No SCIO No y 5 11 QSPIO QSPI1 IIC MSCAN No No B No No D CYC ADC No CRC No QDC No PITO No PIT1 No DACA DACB No No 1 No PWMCH2 No PWMCH3 Protection of IPS and GPSxx Registers not protected Pro
202. S CLKINO alt1 CLKIN1 GPIOC3 alt3 SYS SELECT MASTER PIT SYS PIT1 SYS PITO Select Master Programmable Interval viv Timer SYS SET 12 POWER MODE SYS NORMAL POWER SY Set Small Regulator 1 2 V Supply S REDUCED POWER Powerdown Control SYS_POWER_MODE_PER MANENT SYS_SET_27_POWER_MODE SYS_NORMAL_POWER SY Set Small Regulator 2 7 V Supply S REDUCED POWER Standby Control SYS_POWER_MODE_PER MANENT SYS_SET_27_POWERDOWN SYS_NORMAL_POWER SY Set Small Regulator 2 7 V Supply S POWERDOWN MODE Standby Control FX SYS POWER MODE PER MANENT DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 155 Table 5 62 SYS Driver Commands x x Description ag 505 Lre SYS SET AOPAD FUNCTION one of SYS AOPAD xxx Package pin function selection 2 _ _ SYS SET AOPAD FUNCTION one of SYS AOPAD xxx Package pin function selection 2 _ _ SYS SET B10PAD FUNCTION one of SYS B10PAD xxx Package pin function selection 2 ANC14 XB 1 8 SYS SET B11PAD FUNCTION one of SYS B11PAD xxx Package pin function selection 2 15 SYS SET B1PAD FUNCTION one of SYS B1PAD Package pin function selection ANB1 CMPB INO DACB SYS SET B9PAD FUNCTION one of SYS B9PAD xxx Package pin function selection 2 ANC13 PADXB IN9 SYS SET COPAD FUNCT
203. SAB LE Enable disable the Quadrature Decoder logic When the Quadrature Decoder logic is bypassed the PHASEA signal is used as a single phase pulse stream and PHASEB is ignored ENC SOFTWARE TRIGGERED NIT NULL Initialize the Upper and the Lower Position Counter Registers UPOS LPOS by the values stored in the Upper and the Lower Initialization Registers WATCHDOG ENC ENABLE ENC DISAB LE Enable disable the watchdog timer to monitor PHASEA and PHASEB inputs changes ENC WRITE CTRL2 REG UWord16 Write to the Control 2 register the parameter value Note an inappropri ate write to register may cause acci dental clear of Write 1 to Clear flags ROIRQ RUIRQ ENC WRITE FILTER UWord16 value 0 255 Setthe filter interval periods in number of IP Bus clock periods ENC WRITE FILTER COUNT SA MPLES COUNT UWord16 value 0 7 Set the number of consecutive sam ples that must agree prior to the input filter accepting an input transition A value of 0x0 represents 3 samples A value of 0x7 represents 10 samples This value affects the input signal latency ENC WRITE INIT STATE Word32 Writes the parameter value to the Lower and the Upper Initialization Registers UINIT LINIT This value represents the initialization number of encoder pulses ENC WRITE LOWER MODULUS REG UWord16 Write the parameter value to the Lower Modulus register DSC5680
204. STATUS2 HLMTI NULL Clear all HILIM status bits for samples 16 19 in the High Limit Status Register v 2 ADC CLEAR STATUS2 LLMTI NULL Clear all LOLIM status bits for sam ples 16 19 in the Low Limit Status Y Register 2 ADC CLEAR STATUS2 ZCI NULL Clear all ZCI status bits for samples 16 19 in the Zero Crossing Status Y Register 2 ADC CLEAR ZERO CROSS STA UWord16 sample number Clear the High Limit Status Register SE TUS ZCS 0 15 ZCSx bit Zero Crossing x flag ADC CLEAR ZERO CROSS STA UWord16 sample number Clear all bits of the ADC zero crossing 2 TUS12 ZCS 0 19 status register 2 ADC CLEAR ZERO CROSS STA UWord16 sample number Clear the Zero Cross Status Register TUS2_ZCS 16 19 ZCSx bit Zero Cross Sample x flag DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 7 Table 5 3 ADC Driver Commands 16 19 Ready Sample 16 19 flag Description ag 55 Lre ADC_DMAEN ADC_CONVERTER_0 ADC_ Enable ADC DMA in the Control Reg PEY CONVERTER_1 ister ADC_END_OF_SCAN_INT ADC ENABLE CONVERTE Enable disable the ADC End of Scan R O ADC DISABLE CONV interrupt this command has no effect ERTER 0 ADC ENABLE C in loop mode ONVERTER_1 ADC_DISAB LE CONVERTER 1 ADC GET LIMIT STATUS HLS UWord16 sample number Read the High Limit Status Register PIN 0 15 HLSx bit High Limit Sample x flag
205. STRET EFPWM ENABLE EFPWM Enable disable Fault glitch stretching XE CH DISABLE EFPWM FAULTO INT DISABLE EFPWM FAULT 0 1 2 3 Disable fault interrupt EFPWM_FAULTO_INT_ENABLE EFPWM_FAULT_X 0 1 2 3 Enable fault interrupt 1 EFPWM_FAULTO_TEST EFPWM Activates simulated fault condition for DISABLE fault 0 Simulated fault to be sent into all of the fault filters EFPWM FAULT1 FILTER COUNT EFPWM SAMPLES X Set number of samples to the input fil well se ER 3 4 5 6 7 8 9 10 ter accepting an input transition EFPWM_FAULT1_FILTER_PERIO UWord16 Value 0 to 255 PY D EFPWM FAULT1 GLITCH STRET EFPWM ENABLE EFPWM Enable disable Fault glitch stretching 20152 DISABLE EFPWM_FAULT1_INT_DISABLE EFPWM_FAULT_X 0 1 2 3 Disable fault interrupt viv EFPWM_FAULT1_INT_ENABLE EFPWM_FAULT_X 0 1 2 3 Enable fault interrupt viv EFPWM_FAULT1_TEST EFPWM ENABLE EFPWM Activates simulated fault condition for DISABLE fault 1 Simulated fault to be sent into viv all of the fault filters EFPWM_INIT NULL Initialization of the peripheral regis ters using appconfig h INIT values EFPWM MONITOR PLL EFPWM ENABLE PERMA Enable disable PLL monitor NENT EFPWM DISABLE viv PERMANENT EFPWM READ DEADTIME SOUR NULL Return value of the Deadtime Source sly Select Register EFPWM_READ_FAULT_CONTROL NULL Return value of the Fault Register PUE REG EFPWM READ FAULT STATUS NULL Return value of the Fa
206. Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc lt freemaster_demo appconfig h 56F800 E Graphical Configuration gt File Edit View Module 3 Target MC56F82748 Generation SYS Clock 50 000 MHz MSTR_OSC source Relaxation oscilator X N 8 M IPBus Clock 50 000 MHz Input frequency Prescaler System clock source Core freq 8 MHz not used v 50MHz PINOUT Package and Pin Out Infor Multiply PLL Div Postscaler VCO freq 7 OCCS On Chip Clock Synthesis 5 23 z 200 MHz COP Computer Operating Properly Startup lock mode F PwM 2X clock HS freq 5 SYS System Support Control Coase v ctor Raw PLL output 100 2 INTC Interrupt Controller Nano Edge freq DMA Controller 200 MHz Quad Timer 3 QT A0 Counter 0 OCCS Interrupts Write Protection 1 QT_Al Counter 1 Loss of lock 0 coarse ISR Name Postscaler amp Clock Source B 1 22 Disable Disabled v Write Protection OFF Counter SEES em PT Periodi c Interrupt Timer Loss of lock 1 Loss of reference timer period Oscillator Configuration a i 1 Periodic Interrupt 0 Wite Protection OFF 5 2 9 G Warning detail Pull Configuration PIT Periodic Interrupt Timer 1 onfiguration Ei v GPIO General P
207. T C15PAD FUNCTION one of SYS C15PAD xxx Package pin function selection 2 SCLO XB_OUT5 SYS SET C15PAD FUNCTION one of SYS C15PAD xxx Package pin function selection XB OUT5 PWM SCLO SYS SET C2PAD FUNCTION one of SYS C2PAD xxx Package pin function selection TXDO TBO XB IN2 CLKOUT Y 0 SYS SET C2PAD FUNCTION one of SYS C2PAD xxx Package pin function selection TXDO XB OUT11 XB IN2 C Y LKOUTO SYS SET C3PAD FUNCTION one of SYS C3PAD xxx Package pin function selection TAO CMPA O RXDO CLKIN Y 1 SYS SET C3PAD FUNCTION one of SYS C3PAD xxx Package pin function selection TAO CMPA O RXDO CLKIN Y 1 SYS SET CAPAD FUNCTION one of SYS CAPAD xxx Package pin function selection TA1 CMPB O XB ING EW Y M OUT B SYS SET CAPAD FUNCTION one of SYS CAPAD xxx Package pin function selection TA1 CMPB O XB IN8 EW Y M OUT B SYS SET C5PAD FUNCTION one of SYS C5PAD xxx Package pin function selection DACO XB IN7 SYS SET C5PAD FUNCTION one of SYS C5PAD xxx Package pin function selection 2 DACA XB_IN7 SYS SET C6PAD FUNCTION one of SYS C6PAD xxx Package pin function selection TA2 XB_IN3 CMPREF SYS SET C6PAD FUNCTION one of SYS C6PAD xxx Package pin function selection TA2 XB_IN3 CMPREF SSO v _B DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 157 Table 5 62 SYS Driver Commands PWMAS XB 5 x x
208. T PWM FAULT STA EFPWM Set level of output pin PWMB during TEOUT B LOG 0 LOG 1 TRISTATED fault state viv EFPWMS_SET_PWM_FAULT_STA EFPWM_XXX Set level of output pin PWMX during TEOUT X LOG 0 LOG 1 TRISTATED fault state viv EFPWMS_SET_PWM_POLARITY_ EFPWM_OUTPUT_X Set output polarity to non inverted e ar HIGH ACTIVE A B X where high is active state EFPWMS_SET_PWM_POLARITY_ EFPWM_OUTPUT_X Set output polarity to inverted where Viv LOW ACTIVE A B X low is active state EFPWMS SET RELOAD FREQUE EFPWM RELOAD OPPOR Set reload period TUNITY_X 1 to 16 EFPWMS SET RELOAD SOURC EFPWM RELOAD XXX Select PWM reload source LOCAL MASTER EFPWMS_SET_SYNC_SOURCE EFPWM XXX Set reload PWM sync source LOCAL SYNC MASTER R JE ELOAD MASTER SYNC EX T SYNC EFPWMS SPLIT DBLPWM EFPWM ENABLE EFPWM Enable disable splitting one pulse on 2 DISABLE PWMA and one on PWMB EFPWMS TEST DEADTIME SAM EFPWM_DEADTIME_0_BIT Return sampled PWMX inputs at Pp PLE BITS EFPWM DEADTIME 1 BIT dealdtime 0 1 EFPWMS TEST PWM INPUTS EFPWM INPUT X A B X Return actual state of selected PWM 18 22 pins DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 65 Table 5 19 EFPWM Driver Commands Description ag 5 ive EFPWMS TEST SUBMODULE FL EFPWM xxx Retu
209. T1 SCLO SDAO TXD1 RXD1 Reserved CMPC_O RXDO GPSn GPIOC3 ripheral Miscellaneous Register 0 ct Register O0 SIM MISCO IPSO GPIOCA GPIOC6 GPIOC13 8 8 12 5 Disabl Disabl CLKINO e e GPIOCO altl DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 29 Freescale Semiconductor Inc SIM Interrupts PITO master Low voltage 2 2V Disabl Low voltage 2 7V Disabl Le Le High voltage 2 2V Disable High voltage 2 7V Disable Enable Voltage Reference Buffer No Bandgap trim 7 Use Factory Trim Value No define SIM PCEO INIT 0x0002U define SIM 1 INIT 0x0802U define SIM PCE2 INIT 0x0000U define SIM PCE3 INIT 0x0000U JE INTC Configuration VE define INTC INIT 0x0000U define INT VECTOR ADDR 47 FMSTR Isr define INT PRIORITY LEVEL 47 INTC LEVE define INT VECTOR ADDR 48 FMSTR Isr define INT PRIORITY LEVEL 48 INTC LEVE define INT VECTOR ADDR 50 FMSTR Isr define INT PRIORITY LEVEL 50 INTC LEVE GPIO_F Configuration Pin 0 Function GPIO Direction Input Pull Int Polarity Active high Pin 1 Function GPIO Direction Input Pull Int Polarity Active high Pin 2 Function GPIO Direction Input Pull Int Polarity Active high
210. T1 TERM 0 INPU AOI LOGO AOI INVERT AO Set INPUT_D the Term 0 for XE T D NOTINVERT AOI LOG1 SET EVENT1 TERM combination of Set all inputs at once of the Term 1 for AOI INPUT n xxx EVENTI C D xxx LOGO INVERT NOTIN VER LOG1 SET EVENT1 TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT A of the Term 1 for PN TA NOTINVERT AOI LOG1 SET EVENT1 TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT B of the Term 1 for NOTINVERT AOI 10091 1 AOI SET EVENT1 TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT C the Term 1 for P TC NOTINVERT AOI LOG1 5 32 Freescale Semiconductor Inc Table 5 7 AOI Driver Commands Description ag 5 iO SET EVENT1 TERM 1 INPU AOI LOGO AOI INVERT AO Set INPUT_D of the Term 1 for PA I T D NOTINVERT AOI LOG1 SET EVENT1 TERM 2 combination of Set all inputs at once of the Term 2 for AOI INPUT n xxx EVENTI C D xxx LOGO INVERT NOTIN VER LOG1 SET EVENT1 TERM 2 INPU AOI LOGO AOI INVERT AO Set INPUT A of the Term 2 for 21 24 10091 1 SET EVENT1 TERM 2 INPU AOI LOGO AOI INVERT AO Set INPUT B of the Term 2 for 21152 NOTINVERT AOI 10091 1
211. URCE FCAN_UNFILTERED_RX Select Wake Up Source FCAN_FILTERED_RX FCAN_SELF_RECEPTION FCAN_ENABLE FCAN_DIS Enable or disable reception of ABLE self transmitted frames FCAN_LOCAL_PRIORITY FCAN_ENABLE FCAN_DIS Enable or disable TX priority to be set v ABLE in individual MBs by using FCANMB_SET_TX_PRIORITY com mand Note that this requires the FCAN_HIGHEST_PRIORITY mode to be set by the FCAN_SET_TX_FIRST_SCHEME command FCAN TX ABORT OPERATION FCAN ENABLE FCAN DIS Enable or disable TX Abort operation Y ABLE FCAN SET SAMPLING FCAN 1SAMP PER Set number of hardware samples per 5 5 PER bit FCAN_SET_PRESCALER UWord 0 255 Set PRES_DIV prescaler divisor FCAN_SET_RJW FCAN_RJW_x x 1 4 Set RJW bit time parameter Y FCAN SET PROP SEG FCAN PROPSEG n Set PROP SEG bit time parameter Y 1 8 or UWord16 value 0 7 FCAN SET PHASE 5 FCAN PSEG n 1 8 or Set PHASE SEG bit time parameter Y UWord16 value 0 7 FCAN SET PHASE SEG2 FCAN PSEG n 1 8 or Set PHASE SEG2 bit time parameter Y UWord16 value 0 7 FCAN UNLOCK ALL MB NULL Unlocks all message boxes by reading Y the free running timer register FCAN GET MAXMB NULL Get maximum number of MB used Y FCAN SET MAXMB UWord16 number 0 15 Set maximum number of MB used Y FCAN READ ERR AND STATUS NULL Read value of error and status register Y error bits are self cleared by reading FCAN CLEAR INT FCAN ESHR1 xxx Clear selected interrupt
212. UT ADC_ Set On Chip Analog Input Alternate 2 NORMAL OPERATION Source DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 11 Table 5 3 ADC Driver Commands x R x Cmd pParam Description ag SET ADCA7 INPUT ADC TEMPERATURE SEN Set On Chip Analog Input Alternate SOR ADC NORMAL OPER Source Y ATION ADC SET ADCB DIVISOR PARA UWord16 or one of Set ADC module ANB clock divisor in LEL MODE ADC_DIVx parallel mode which determines ADC Y conversion speed ADC SET ADCB6 INPUT ADC ANALOG INPUT ADC Set On Chip Analog Input Alternate NORMAL OPERATION Source SET ADCB7 INPUT ADC TEMPERATURE SEN Set On Chip Analog Input Alternate SOR ADC NORMAL OPER Source Y ATION ADC SET ANAO GAIN ADC GAIN x 1 2 4 Selects channel gain for ANAO input viv ADC_SET_ANA1_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANA1 input viv ADC_SET_ANA10_GAIN ADC_GAIN_x x 1 2 4 Selects channel for ANA10 input ADC_SET_ANA16_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANA16 input ADC_SET_ANA17_GAIN ADC_GAIN_x x 1 2 4 Selects channel for ANA17 input ADC_SET_ANA2_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANA2 input S A ADC SET GAIN GAIN 1 2 4 Selects channel gain for input viv ADC SET ANA4 GAIN ADC GAIN x 1 2 4 Selec
213. UT2 GET 10BIT ADDRESS NULL Read and return the 10 bit slave le address GET ADDRESS NULL Read and return the Address 0 127 which is currently active for viv 5 94 Freescale Semiconductor Inc Table 5 38 1 Driver Commands Description e ive GET ADDRESSED AS SLAV NULL Get the addressed as a slave flag P E ARBITRATION LOST NULL Get arbitration lost status viv GET BUS BUSY NULL Get the bus busy status viv GET BUS INT NULL Get the I Bus interrupt flag viv IIC_GET_MASTER_MODE NULL Return non zero if IIC Master mode is PE set GET RANGE SLAVE ADDRE NULL Get the slave address range PE SS RX NULL Get the received acknowledge flag viv IIC_GET_SLAVE_TRANSMIT NULL Get slave read write status IIC_GET_SMBUS_ ADDRESS NULL Read and return the SMBus slave address of the node in the range viv 0 127 as UWord16 GET TRANSFER COMPLETE NULL Get the data transferring status viv IIC_GET_TX_MODE NULL Return non zero if transmit mode is set BUS IIC_ENABLE IIC_DISABLE Enable Disable the module as a sly whole BUS INT ENABLE IIC DISABLE Enable Disable the Interrupt The core receives the interrupt provided if itis enabled in the INTC Interrupt Con PIN troller module and also when inter rupts are
214. UWord16 READ RANGE ADDRESS RE NULL Read and return the IIC Bus Range s de G Address Register as UWord16 IIC_READ_SCL_LOW_TIMEOUT NULL Read and return the SCL low timeout value IIC_READ_SCL_LOW_TIMEOUT_H NULL Read and return the IIC Bus SCL Low IGH_REG Timeout MSByte Register as viv UWord16 READ SCL LOW TIMEOUT L NULL Read and return the IIC Bus SCL Low OW REG Timeout LSByte Register as viv UWord16 READ SMBUS REG NULL Read and return the SMBus 24 22 Control Status UWord16 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 96 Freescale Semiconductor Inc Table 5 38 1 Driver Commands Cmd pParam Description 56F82xxx 56F84xxx IIC_READ_STATUS_REG NULL Read and return the IIC Bus Status Register as UWord16 lt lt REPEAT START NULL Generate a repeated START condition on the bus provided the node is active bus Master otherwise the Arbitration Lost status flag is set SET 10BIT ADDRESS UWord16 value 0 1023 Write to the 10 bit slave address to the Bus Address Register and the upper three bits to the Control Regis ter 2 0 1023 SET ADDRESS UWord16 value 0 127 Set the node slave address The address is used in the slave mode only to detect it is being addressed in an IIC transaction Typically it is not necessary to change the slave
215. UWord16 sample number Read and return the value of ADC 0 19 High Limit Register for sample defined v by parameter ADC_READ_HIGH_LIMIT2 UWord16 sample number Read and return the value of ADC 16 19 High Limit Register for sample defined v by parameter ADC_READ_LOW_LIMIT UWord16 sample number Read and return the value of ADC 0 15 Low Limit Register for sample defined v by parameter ADC READ LOW LIMIT STATUS NULL Read and return values of ADC Low 12 Limit Status registers 1 and 2 ADC READ LOW LIMIT STATUS NULL Read and return the value of Low 3 2 Limit Status Register 2 ADC READ LOW LIMIT12 UWord16 sample number Read and return the value of ADC 0 19 Low Limit Register for sample defined v by parameter ADC READ LOW LIMIT2 UWord16 sample number Read and return the value of ADC 16 19 Low Limit Register for sample defined v by parameter ADC READ OFFSET UWord16 Read and return the value of ADC Off set Register The number of the sam ZI E ple which the offset value belongs to is determined by the parameter ADC READ OFFSET12 UWord16 sample number Read and return the value of ADC Off 0 19 set Register for sample defined by Y Freescale Semiconductor Inc Table 5 3 ADC Driver Commands Description ag iO Lre ADC_READ_OFFSET2 UWord16 sample number Read and return the value of ADC Off 1
216. Word16 Write Value to Value Register 1 viv EFPWMS_WRITE_VALUE_REG_2 Word16 Write Value to Value Register 2 viv DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 66 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands Cmd pParam Description 56F82xxx 56F84xxx lt lt EFPWMS WRITE VALUE REG Word16 Write Value to Value Register 3 lt lt EFPWMS WRITE VALUE REG 4 Word16 Write Value to Value Register 4 EFPWMS WRITE VALUE REG 5 Word16 Write Value to Value Register 5 vorm DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 67 5 1 9 Enhanced Quadrature Encoder Decoder The enhanced quadrature encoder decoder module provides interfacing capability to position speed sensors used in industrial motor control applications It has four input signals PHASEA PHASEB INDEX and HOME This module is used to decode shaft position revolution count and speed The Table 5 20 shows module identifiers for ENC Driver Table 5 20 Identifiers for ENC Driver Module identifier 56F82xxx 56F84xxx ENC v Table 5 21 shows all commands for Driver Table 5 21 ENC Driver Command gt lt gt lt gt lt gt lt Description LL LL iO ENC_CALCULATE_SCALE_COEF pointer to Calculate the scaling coefficients dec
217. Word16 Writes prepared data in to the Soft PM OUT REG ware Controlled Output Register DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 56 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands gt lt gt lt Description re EFPWMS_ACTIVE_CAPTURE_A NULL Actives capture A operation viv EFPWMS_ACTIVE_CAPTURE_B NULL Actives capture B operation viv EFPWMS_ACTIVE_CAPTURE_X NULL Actives capture B operation viv EFPWMS_ACTIVE_FORCE_INIT NULL Active force initialization vw EFPWMS CAPTURE A DISABLE NULL Disable capture A operation viv EFPWMS CAPTURE B DISABLE NULL Disable capture B operation viv EFPWMS_CAPTURE_X_DISABLE NULL Disable capture B operation viv EFPWMS CENTER ALIGN UPDA Word16 in Signed Fractional Range 0 to 1 Set Value2 and Value3 22122 CHANNEL 23 representation registers EFPWMS CENTER ALIGN UPDA Word16 in Signed Fractional Range 0 to 1 Modulo register can be TE CHANNEL 23 FRAC representation maximally 1024 Set Value2 Fractional2 Value3 and Fractional3 registers EFPWMS CENTER ALIGN UPDA Word16 in Signed Fractional Range 0 to 1 Set Value4 and Value5 PET TE CHANNEL 45 representation registers EFPWMS CENTER ALIGN UPDA Word16 in Signed Fractional Range 0 to 1 Modulo register can be TE CHANNEL 45 FRAC representation maximally 1024 Set Value2 212
218. X_Quick_Start tool does not provide any automatic saving restoring of used registers The last instruction of an ISR must be Return from Interrupt instruction This instruction restores the SR and the PC from the stack Both saving restoring registers and using RTI instead of RTS are provided by the compiler directive pragma interrupt pragma interrupt is used when declaring a C function and it instructs the compiler to save all registers used within a C function and to restore those register values upon exiting Also it places an RTI instruction instead of an RTS at the end of the function See Section 2 6 3 2 6 1 4 Interrupt Priority Levels On 56F800EX hybrid microcontroller family each interrupt can be assigned the interrupt priority level IPL It is the number from lowest priority to 3 highest priority When servicing the interrupt until the RTI instruction is executed the other interrupts of the same and lower priority levels are masked DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 34 Freescale Semiconductor Inc temporarily disabled If there is interrupt request of the masked priority level its processing is postponed until the level is unmasked again This model assures that the interrupts of the same level can not nest one to each other On the other hand the higher priority interrupts do nest to the lower priority interrupts 2 6 1 5 Fast Interrupts Up to 2 interrupt sou
219. YNC XBAR A INPUT xxx Set A OUT 14 input Y XBAR SET OUT DMA REQO XBAR A INPUT xxx Set XBAR A OUTO input Y XBAR A SET OUT DMA REQO XBAR A INPUT xxx Set OUTO input v A SET OUT XBAR A INPUT xxx Set XBAR A OUT input v A SET OUT REQ t XBAR A INPUT xxx Set XBAR A OUT input v XBAR A SET OUT DMA REQ2 XBAR A INPUT xxx Set XBAR OUT2 input v XBAR SET OUT DMA REQ2 XBAR A INPUT xxx Set XBAR A OUT2 input Y XBAR SET OUT DMA REQ3 XBAR A INPUT xxx Set XBAR A OUT3 input Y XBAR SET OUT DMA REQ3 XBAR A INPUT xxx Set A OUT3 input Y XBAR SET OUT EWM IN XBAR A INPUT xxx Set A OUTS568 input Y XBAR A SET OUT EWM IN XBAR A INPUT xxx Set A 40 input v XBAR A SET OUT GPIO C 14 XBAR A INPUT xxx Set XBAR A OUTA input v XBAR A SET OUT GPIO C 14 XBAR A INPUT xxx Set A OUTA input 2 SET OUT GPIO C 15 XBAR A INPUT xxx Set XBAR 5 input 2 SET OUT GPIO C 15 XBAR A INPUT xxx Set XBAR A 5 input SET OUT 2 A INPUT xxx Set XBAR A OUT11 input 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 168 Freescale Semiconductor Inc Table 5 64 Driver Commands Description 5 5 8 8 XBAR A SET OUT GPIO C10 F5
220. _MOD E QT FIXED FREQ PWM M ODE QT VARIABLE FREQ PW M MODE QT SET COUNT ONCE QT COUNT REPEATEDLY Select if timer counter counts repeat QT UNTIL COMPARE AN edly or until the compare event and viv D_STOP then it stops QT SET COUNTING UPON SEC QT ENABLE QT DISABLE Enable disable counting timer upon _TRIG receiving a second trigger QT_SET_DEBUG_ACTION QT DEBUG xxx CON Set certain actions in response to the TINUE HALT TMR FORCE chip entering the debug mode OUT_0 HALT_TMR_FORCE OUT 0 QT SET FAULT FUNCTION QT ENABLE QT DISABLE Enable disable the fault function viv QT_SET_INPUT_POLARITY QT NORMAL POLARITY Q Set the polarity of the timer counter PA T INVERTED POLARITY input signal QT SET LOAD CONTROL1 QT NEVER PRELOAD QT Specify the preload event for the Com LOAD ON CMP1 QT LOAD pare Register 1 viv CMP2 QT SET LOAD CONTROL2 QT NEVER PRELOAD QT Specify the preload event for the Com LOAD ON CMP1 QT LOAD pare Register 2 viv CMP2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 139 Table 5 56 Driver Commands Cmd pParam Description 56F82xxx 56F84xxx QT_SET_OUTPUT_MODE QT_SET_WHILE_ACTIVE QT CLEAR ON COMPARE QT SET ON COMPARE QT TOGGLE ON COMPA RE QT TOGGLE USING ALT COMPARE CLEAR ON SECONDA CLEAR COUNTER _ROLLOVER QT GATED WHIL E ACTIVE Set timer counter output
221. _OFFSET4 UWord16 Write Offset Register for sample 4 viv ADC_WRITE_OFFSET5 UWord16 Write Offset Register for sample 5 viv ADC_WRITE_OFFSET6 UWord16 Write Offset Register for sample 6 ADC_WRITE_OFFSET7 UWord16 Write Offset Register for sample 7 viv ADC_WRITE_OFFSET8 UWord16 Write Offset Register for sample 8 viv ADC_WRITE_OFFSET9 UWord16 Write Offset Register for sample 9 viv ADC_WRITE_POWER_CONTROL_ UWord16 Write Power Control Register 2 2 REG ADC WRITE SAMPLE DISABLE UWord16 0 15 or any combi Set the number of samples in scan nation of ADC SAMPLEx sequence viv x 0 15 ADC_WRITE_SAMPLE_DISABLE1 UWord16 0 19 or any combi Set the number of samples in scan 2 nation of ADC_SAMPLEx sequence Y 0 19 ADC_WRITE_SAMPLE_DISABLE2 UWord16 16 19 or any com Set the number of samples in scan bination of ADC_SAMPLEx sequence Y 15 19 ADC WRITE SCAN CONTROL R UWord16 Write Scan Control Register PN EG ADC WRITE SCAN CONTROL R UWord16 Write Scan Control Register 2 2 2 ADC_WRITE_SCAN_HALTED_INT UWord16 Write Scan Halted Interrupt Enable ERRUPT_REG Register ADC_WRITE_SCAN_HALTED_INT UWord16 Write Scan Halted Interrupt Enable 2 ERRUPT_REG2 Register 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 20 Freescale Semiconductor Inc Table 5 3 ADC Driver Commands
222. a 16 ANA 3 CMPA 2 OCCS On Chip C 26 57 cue go 12 A4 ANA4 CMPD INO COP Computer C gui 11 5 KZ SYS System Supp TET 10 CMPD_IN2 TOPO 48 9 ANAT CMPD IN3 V INTC Interrupt Cc 4 DMA Contr GPIO 8014 ANAO CMPB_IN3 C 24 Oxa cLkN QT_A Quad Time GPIO 1 ANA1 CMPB 0 _ 25 gercure 4 QT_A0 Count GPIO ANB2 VERFHB 27 gnam c 5 2 xB_0uT11 xe iN2 Count GPIOB3I ANB3 VREFLB CMPC_INO C 28 coss ayes veeriacusc 7 cro cian scio 3 s 4 1 _ 6 EWM_OUT_B QT A2 Count GPIO de 4 IN1 E 21 18 5 C XB_N7 Count 47 paced be abe 33 31 x8 iN3 REF Periodi 32 Oxs ne sco nae aad B74 ANB7 CMPB_IN2I 17 2 _0 33 XB SPI PIT Periodic 34 XB_ouTs GPIO General Pur GPio JTAG EOnCE Port M 64 35 GPlo cto xB 5 mso xe ours cpio 11 37 M Gpo c11 sci 1 GPIO A GPIO iB 1 38 GPIO C12 C MSCAN GPIO B GPIO 03 2000
223. a flag and an interrupt request if enabled reset to 0x0000 and resume counting The Table 5 49 shows module identifiers for PIT Driver Table 5 49 Identifiers for PIT Driver Module identifier 56 82 56F84xxx PIT O Y Y PIT 1 v The Table 5 50 shows commands dedicated for PIT Driver Table 5 50 PIT Driver Commands Cmd pParam Description 56F82xxx 56F84xxx PIT_CLEAR_ROLLOVER_INT NULL Clear the PIT rollover interrupt flag Typically this command is used in the PIT interrupt service routine to acknowledge the interrupt event lt lt PIT_ENABLE PIT_DISABLE Enable disable the PIT module counter This command has no effect on PIT_1 or PIT_2 modules if these operate in slave mode In the slave mode the PIT module counter is enabled or disabled simultaneously with 0 counter See the PIT_SLAVE_MODE command for more details PIT_INIT NULL Initialize the PIT peripheral registers using the appconfig h _INIT values PIT_INIT NULL Initialize the PIT peripheral registers using the appconfig h _INIT values PIT_READ_COUNTER_REG NULL Read and return the PIT counter regis ter value as UWord16 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 123 Table 5 50 PIT Driver Commands Cmd pParam Description 56F82xxx 56F
224. ale that is 1 altered in any way by you or any third party if the alleged infringement would not have occurred but for such alteration 2 combined with any other products or elements not furnished by Freescale if the alleged infringement would not have occurred but for such combination 3 designed or manufactured in DSC56800EX Quick Start User s Guide Rev 2 04 2015 8 3 Freescale Semiconductor Inc accordance with your designs specifications or instructions if the alleged infringement would not have occurred but for such designs specifications or instructions or 4 designed or manufactured in compliance with standards issued by any public or private standards body if the alleged infringement would not have occurred but for compliance with such standards In no event will Freescale indemnify you or be liable in any way for royalties payable based on a per use basis or any royalty basis other than a reasonable royalty based upon revenue derived by Freescale from your license of the Software THE INDEMNITY PROVIDED IN THIS SECTION IS THE SOLE EXCLUSIVE AND ENTIRE LIABILITY OF FREESCALE AND THE REMEDIES PROVIDED IN THIS SECTION SHALL BE YOUR EXCLUSIVE REMEDIES AGAINST FREESCALE FOR PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION AND IS PROVIDED IN LIEU OF ALL WARRANTIES EXPRESS IMPLIED OR STATUTORY IN REGARD THERETO INCLUDING WITHOUT LIMITATION THE WARRANTY AGAINST INFRINGEMENT SPECIFIED IN THE UNIFORM COMMERC
225. and SIM driver configuration extracted from the appconfig h file 5 Configuration Use Factory Trim Value Yes Enable internal 32 kHz oscillator No Power Down crystal oscillator Yes Core frequency 50 MHz VCO frequency 200 MHz Loss of lock interrupt 0 Disable Loss of lock interrupt 1 Disable Loss of reference clock Interrupt Disable s y define OCCS_CTRL_INIT 0x0081U define OCCS DIVBY INIT 0x2018U define OCCS USE FACTORY TRIM 1 define OCCS_USE_FACTORY_TRIM_TEMP 1 SYS Configuration SIM Power Saving Modes Stop enabled Wait enabled OnCE clock to processor core Enabled when core TAP enabled DMA Enable in RUN and WAIT modes DMA enabled in all power modes Enab External Reset Padcell Input Filter No SIM Clock on GPIO Enable CLKO 0 No DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 28 Yes No No Modul Modul Modul SIM Clock on GPIO Source Continuous Sy Divide by 1 SIM HS PERF Periphe SIM Peripheral Cloc Enable CLKO 1 Yes stem Clock ral Clk PWM k Enable GPIO F Yes GPIO A No OSPIO No QSPI1 CRC No QDC No es Enabl es es SIM ed in Stop Enabled in Stop Enabled in Stop Modules MSCAN CRC No QDC TMR AO No TMR Al No LI
226. ands xx Description ag zou DMA_CH3_SELECT_SOURCE DMA REQUEST Select DMA request which will be 0 15 routed to the DMA channel 3 DMA_INIT NULL Initialization of the DMA peripheral registers using appconfig h INIT val ues Table 5 16 Identifiers for DMA Driver Module identifier 56 82 56F84xxx DMA 0 v DMA 1 _2 v DMA 3 The Table 5 17 incorporates commands where DMA should be used as the device unlike the previous table where DMA is used as the module Table 5 17 DAC_x Driver Commands Description SS LL LL iO CLEAR TRANSACTION DO NULL Clear DMA transaction status bit Use NE in an interrupt service routine to clear viv the DMA interrupt flag and error bits DMA_DISABLE_REQUEST DMA_ENABLE DMA_DISAB If enabled the DMA hardware auto LE matically clears the corresponding Ply DCRn ERQ bit when the byte count register reaches zero DMA_GET_DESTINATION_ADDRE NULL Read and return the destination X SS address used by the DMA channel DMA GET LINK CHANNEL 1 NULL Get the DMA channel assigned as link channel 1 The link channel number cannot be the same as the currently executing channel DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 44 Freescale
227. ane displays the graphical controls which are used to configure the peripheral module e Register Values View Displays immediate register values This bar can be hidden if it is not needed Warning List This side bar displays a list of all configuration conflict warnings DSC56800EX Quick Start User s Guide Rev 2 04 2015 7 3 Freescale Semiconductor Inc lt gt freemaster_demo nfig h 56F800 E iguration gt File Edit View Module gt Target MC56F82748 Global PWM Settings SYS Clock 50 000 MHz Information Panel Fractional PLL check MSTRC MCTRL 0 0001 IPBus Clock 50 000 MHz L PWM A MCTRL2 pO PINOUT Package and Pin Out Information ajf poo PWM_A_MASK 65000 OCCS On Chip Clock Fault configuration DUTEN 040000 COP Computer Operating Properly Fault 0 see XBAR_AFault 1 see AFault 2 see AFault 3 see SYS System Support Control Fault Level Low Low Low Low PWM SWCDUT 100000 ao are Fault Clearing Manual x Manual Manual Manual iene E QT_A Quad Timer A Fault Mode Normal v Nomal v Nomal v Nomal EN i EE 5 2 _ Fault Enable Mode x None R None 7 52 PWM_A_FFILT ox0000 QT A2 Counter 2 Fault Input Filter 8 QTA3 Counter 3 Fault inpu
228. ange the values the user can define the macros CONFIG INTRAM CHECKVALUEI and CONFIG INTRAM CHECKVALUE2 in the appconfig h file ifndef CONFIG_INTRAM_CHECKVALUE1 define CONFIG_INTRAM_CHECKVALUE1 ifndef CONFIG INTRAM CHECKVALUE2 define CONFIG INTRAM CHECKVALUE2 0 5555 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 47 2 7 2 1 4 Linker Command File Symbols While linking the linker replaces any zeros generated by compiler for external symbols with proper values calculated during linking process when the physical addresses of the symbols are known Some values of external symbols can be also specified directly by the directives in the linker command file The following symbols are specified by the LCF and provide physical address of memory segments used in the startup code external constants defined in LCF extern _Lstack_addr extern _Ldata_size ta_ROM_addr ta RAM addr ta2 size extern Lda a a data2 ROM addr a a a extern extern L extern data2_RAM_addr tap_size extern _Ldatap_ROM_addr extern _Ldatap_RAM_addr extern _Lbss_size extern _Lbss_start extern _Lbss2_size extern Lbss2 start extern Lbssp size extern Lbssp start extern Linternal RAM addr extern Linternal RAM size extern Linterrupt vectors addr extern extern
229. are cleared Caution It might seem this macro is the proper way how to set the group of bits to certain value as there are no intermediate invalid values written in the target memory location However it is quite dangerous to use this macro when interrupts may occur between the read and write operations If the interrupt service routine would write the other portion of the target memory location the written value could be overwritten back with its previous state by the write accumulator operation of periphBitGrpSetVar Example 2 40 periphSafeBitGrpSetVar macro usage periphSafeBitGrpSet 0 0002 0x0004 0 00 0 0 0040 amp ArchlO HscmpA scr DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 26 Freescale Semiconductor Inc This code sets the HSCMP A module input hysteresis to 1 rising edge and falling edge interrupt flags are not cleared 2 5 24 periphSafeBitGrpSet32 set bit group to given value and keep value of bit flags which are cleared by write one Call s void periphSafeBitGrpSet UWord32 FlagGroupMask UWord32 GroupMask UWord32 Mask UWord16 pAddr Arguments Table 2 26 periphSafeBitGrpSet arguments FlagGroupMask in Group mask of bit flags which are cleared by write one GroupMask in Group mask Mask in bit mask pAddr in The memory address Description The periphSafeBitGrpSet32 macro sets bit group to given value and keeps value of the bit flags which
230. art User s Guide Rev 2 04 2015 5 162 Freescale Semiconductor Inc Table 5 62 SYS Driver Commands Description e 55 Lre SYS_TEST_RESET_SOURCE any of SYS xxx RESET Get and test source of the previous SW COP COP TOR COP L RESET OR EXTERN POWER ON A viv NY EZPORT COP_WINDO W SYS_WAIT SYS_ENABLE _PERMANEN Enable disable the WAIT instruction T SYS_DISABLE _PERMA SYS WPROTECT CLOCK SETTI SYS ENABLE PERMANEN Write protect PCE SD and PCR NGS 5 5 DISABLE PERMA SYS_WPROTECT_GPIOD SYS_ENABLE _PERMANEN Write protect GPIO_D_PER T SYS_DISABLE _PERMA GPIO_D_PPMODE and GPIO_D_DRIVE SYS_WPROTECT_POWER_MODE SYS_ENABLE _PERMANEN Write protect Power Mode Control T SYS_DISABLE _PERMA viv NENT SYS WPROTECT SIGNALS ROU SYS ENABLE PERMANEN Write protect GPSx TING T SYS_DISABLE _PERMA GPIO_X_PER GPIO_X_PPMODE Big NENT GPIO_X_DRIVE and GIO_X_IFE reg isters SYS WRITE IO SHORT ADDR L UWord32 Set I O short address mode base 22412 _ address SYS_WRITE_SW_CONTROL_REG UWord16 Write SIM software control register 0 Pe 0 SYS WRITE SW CONTROL REG UWord16 Write SIM software control register 1 UN 1 SYS WRITE SW CONTROL REG UWord16 Write SIM software control register 2 EX 2 SYS WRITE SW CONTROL REG UWord16 Write SIM soft
231. ary Initialize value registers Disable DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 17 Freescale Semiconductor Inc Value 0 Disable Valuel Disable Value 2 Disable Value3 Disable Value 4 Disable Value5 Disable Double Switching PWM23 Deadtime count 1 0 Software Controlled Output Logic 0 Logic 0 Force Initialization Enable No Source of FORCE OUTPUT signal Local force CTRL2 FORC Dead Time Source 23 PWM23 Dead Time Source 45 PWM45 PWM45 Initial Value Logic 0 Logic 0 PWMX Initial Value Logic 0 Reload Disable Reload Error Disable 1 3 Value 0 Compare Disable Value 1 Compare Disable Value 2 Compare Disable Value 3 Compare Disable Value 4 Compare Disable Value 5 Compare Disable Capture 0 Disable Capture Al Disable Capture BO Disable Capture Bl Disable Capture Disable Capture 1 Disable Capture A Input select Raw PWMA input Capture B Input select Raw PWMA input Capture X Input select Raw PWMA input One Shot mode enable Disable Disable Disable Edge Counter Enable Disable Disable Disable Edge Compare A Value 0 Edge Compare B Value 0 Edge Compare X Value 0 Capture AO Edge Select Disabled Capture Al Edge Select Disabled Capture BO Edge Select Disabled Capture Bl Edge Select Disabled Capture Edge
232. ate erased to the 0 state programmed Only the erase operation restores bits from 0 to 1 bits cannot be programmed from 0 to a 1 CAUTION A flash memory location must be in the erased state before being programmed Cumulative programming of bits back to back program operations without an intervening erase within a flash memory location is not allowed Re programming of existing Os to 0 is not allowed as this overstresses the device The standard shipping condition for flash memory is erased with security disabled Data loss over time may occur due to degradation of the erased 17 states and or programmed 0 states Therefore it is recommended that each flash block or sector be re erased immediately prior to factory programming to ensure that the full data retention capability is achieved The Table 5 27 shows module identifiers for FTFA Driver Table 5 27 Identifiers for FTFA Driver Module identifier 56F82xxx 56F84xxx FTFL Y Table 5 28 shows all commands dedicated for Driver Table 5 28 FTFA Driver Command Cmd pParam Description 56F82xxx 56F84xxx FTFL_INIT NULL Initialize the FTFL peripheral registers using the appconfig h _ INIT values lt DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 84 Freescale Semiconductor Inc 5 1 13 Flash Memory Module FTFL Driver The driver has only 56F84xxx devices The flash memor
233. ation However it is quite dangerous to use this macro when interrupts may occur between the read and write operations If the interrupt service routine would write the other portion of the target memory location the written value could be overwritten back with its previous state by the write accumulator operation of periphBitGrpSet32 Example 2 38 periphSafeBitSet macro usage periphSafeBitSet32 0 080808000 0x000000080 amp ArchlIO dma reqc Clears the state machine for DMA channel 3 2 5 22 periphSafeBitGrpSet set bit group to given value and keep value of bit flags which are cleared by write one Call s void periphSafeBitGrpSet UWordl16 FlagGroupMask UWordl16 GroupMask UWordl6 Mask 16 pAddr Arguments Table 2 24 periphSafeBitGrpSet arguments FlagGroupMask in Group mask of bit flags which are cleared by write one GroupMask in Group mask Mask in bit mask pAddr in The memory address Description The periphSafeBitGrpSet macro sets bit group to given value and keeps value of the bit flags which are cleared by write one in a peripheral memory location addressed by parameter pAddr The FlagGroupMask specifies all flags which are cleared by write one bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared DSC56800EX Quick Start User s Gui
234. ble Pins Disable Pins Submodule 3 Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins Disable Pins by Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault PWMA Fault State Logic 0 by Fault PWMB Fault State Logic 0 by Fault PWMX Fault State Logic 0 by Fault Fau by Fault Fau by Fault Fau Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault Fau by Fault Fau W 38 Fg 2222222222224 0 0 0 0 0 0 0 0 0 0 0 0 U U U U PREP RPE RPEPEPEEE Cr 75 Cee 2 2 2 2 2 2 2 2 2 2 2 2 070 070 000 0 0 0 0 0 WNHROWNFOWNEFO 5500 DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 13 Freescale Semiconductor Inc s y define MCTR define MCTRL2_INIT define PWM_A_OUTEN_INI as Disable Pins PWMX by Faul Disable Pins PWMX by Faul lt PWMA Faul t PWMB Faul Disable Pins PWMX by Faul L_INIT _0 Configuration lt Faul 0 0 01 0 0000 0 Debug Mode Operation Stop Wait Mode Operation Stop Load Mode Load OK Ye PWM Clock E End cycle 5 nable Yes Clock Source
235. ble the wake up functionin stop mode IIC_TEST_STATUS_ REG combination of IIC_xxx Test IIC Bus Status Register for xxx TRANSFER_COMPLE selected bits TE ADDRESSED_AS_SLAV E BUS_BUSY ARBITRATIO N_LOST SLAVE_TRANSMIT IBUS_INT RX_ACk IIC_TEST_STOP_START_FLAGS combination of Test the state of the start stop detec IIC_xxx_FLAG tion flags viv DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 98 Freescale Semiconductor Inc Table 5 38 1 Driver Commands Description ag 55 Lre IIC_TEST_TIMEOUT_FLAGS combination of xxx Test and return the state of the xxx LOW_TIMEOUT HIGH_ selected timeout flags 5 OUT HIGH_TIMEOUT2 Enable Disable transmitting of the acknowledge signal after a data byte is received matching address byte is always acknowledged By disabling viv an acknowledge signal a receiver informs the transmitting node that it wants to finish the transaction _ _ _ IIC_TRANSMIT IIC_RECEIV Select the direction of data transfers E The Receive Transmit mode selection sly should not be confused with the Mas ter Slave selection IIC_WRITE_ADDRESS2_REG UWord16 value 2 255 Write to the IIC Bus Address Register A 2 WRITE CONTROL REG UWord16 Write the value to IIC Bus Con
236. by the watchdog module COP the same rules as in the previous point apply Again the COP Reset vector is supplied from the full vector table at address 0 0000 interrupt_vectors section The default value of COP Reset vector is Start so the standard power up code is processed The user is able to redefine the COP Reset service routine same way the other interrupt vectors are installed see Section 2 6 2 on page 35 for more details Start assembly routine in startup c file userPreMain function in appconfig c file user s main function in default project it is located in main c gw IN 5 userPostMain function in appconfig c file The following subsections provide a detailed description of all initialization performed before user s main function is called Figure 2 1 Boot Sequence DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 1 Interrupt Vector Table Program Memory void userPreMain 0 0000 Power up Reset 1 and EMI MODE 0 0 0001 Watchdog Reset P 0x0002 EXIBOOT 1 and EMI MODE 0 P 0x0003 asm void Start P 0x0004 basic init P 0x0005 vectors c startup c void userPostMain interrupt vectors section jx FuserPreMain jsr Fmain jsr FuserPostMain debughlt Power up Reset EXTBOOT 0 EXTBOOT 1 and EMI MODE 1 P 0x20000 0 20001 Watchdog Reset appc
237. can Mode Control xxx ONCE_SEQUENTIAL ONCE_SIMULTANEOUS LO OP SEQUENTIAL LOOP SI viv MULTA NEOUS TRIG_SEQUENTIA L TRIG_SIMULTANEOUS ADC SET UNIPOLAR CHANNEL ANAy 222 Enable the Unipolar differential or 01 23 45 67 Fully differential mode according to Y zzz FULLY UNIPOLAR the parameter ADC_SIMULT ADC_ON ADC_OFF Select simultaneous or independent parallel scan mode in the Control Reg v Y ister 2 ADC START NULL ADC CONVERTER 0 Start conversion in software sly ADC_CONVERTER_1 ADC_STOP ADC_ON ADC_OFF ADC_O Set the ADC to normal operation N_CONVERTER_0 ADC_O ADC_ON or to stop mode N CONVERTER 1 ADC OF ADC OFF viv F_CONVERTER_0 ADC_OF 1 ADC SYNC ADC ON ADC OFF ADC O Select the ADC conversion START CONVERTER 0 ADC O source SYNC input ADC ON or CONVERTER 1 ADC OF ADC START command OFF F CONVERTER 0 ADC OF F CONVERTER 1 ADC TEST INT ENABLED ADC END OF SCAN ADC Return non zero if any of interrupts ZERO CROSS ADC LOW _ specified in parameter are enabled LIMIT ADC HIGH LIMIT AD 25152 END SCAN 0 ADC END SC AN CONVERTER 1 ADC WRITE CHANNEL LIST1 Sy 0 7 Configures mapping of the physical 0 3 inputs 7 or ANAO ANA7 to 21 5 0 7 samples 0 3 y 0 3 ADC_WRITE_CHANNEL_LIST2 ADC_ANAx_Sy x 0 7 Configures mapping of the physical y 4 7 inputs A
238. clearbss2 move w R5 clear COP watchdog counter move w D1 X R5 move w 0 1 clear value at r1 dectsta r2 long loop counter DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 55 bne lt loop_clearbss2 end_clearbss2 And again the process is repeated for the Program RAM based variables In the startup code this bss pmem segment is referenced as bssp Note that the move instruction accesses the P program space clear BSSP program RAM segment can t use do and its 16 bit loop counter 1 gt gt _Lbssp_size r2 bssp size tsta l r2 beq end clearbssp skip if size is 0 move l 4 Lbssp start rl dest address move w 0 0 loop clearbssp move w R5 clear COP watchdog counter move w D1 X R5 move w 0 1 clear value at rl dectsta r2 long loop counter bne clearbssp end clearbssp 2 7 2 2 9 Initializing Global Variables The C variables to which are assigned a non zero initial values must be initialized using the data from a non volatile memory Using the directives in the linker command file the initial data are stored in the internal Flash memory The source and destination addresses are calculated by the linker and exported as symbols The P Flash memory is used and the appropriate code is compiled Note that the COP counter is periodically clea
239. configuration bits Depend RMANENT ing on the PERMANENT parameter value the protection acti vated deactivated permanently until next reset or might be changed later OCCS_WPROTECT_PLL_SETTIN OCCS_ENABLE _PERMAN Set the write protection of the GS ENT OCCS DISABLE PE PLL related configuration bits RMANENT Depending on the PERMANENT parameter value the protection may activated deactivated permanently until next reset or might be changed later OCCS_WRITE_CONTROL_REG UWord16 Write the parameter value to the PLL Flt adi Control register OCCS_WRITE_DIVIDE_BY_REG UWord16 Write the parameter value to the PLL viv Divide by register OCCS WRITE OSC CONTROL R UWord16 Write the parameter value to the Oscil e EG lator Control register OCCS WRITE OSC CONTROL2 UWord16 Write the parameter value to the Oscil lator Control 2 register DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 122 Freescale Semiconductor Inc 5 1 22 Periodic Interrupt Timer PIT Driver The programmable interval timer module PIT contains clock select logic a 16 bit up counter a modulo register and a control register The modulo and control registers are read writable The counter is read only The modulo register is loaded with a value to count to and the prescaler is set to determine the counting rate When enabled the counter counts up to the modulo value and set
240. contains the address of the startup code Start routine in the startup c file To install a user s ISR at the xx interrupt vector add the following define in appconfig h define INT_VECTOR_ADDR_xx userISRname The conditional compilation then forces the compiler to use the userISRname ISR instead of the default unhandled_interrupt at the position of the interrupt vector in the interrupt vector table userISRname is the placeholder for the name of interrupt service routine with prototype of void userISRroutine void In your source code you then put the following code pragma interrupt void userISRname void ISR code The range of interrupt vectors which can be installed xx is 1 to 80 Vector 0 is the Hardware Reset vector and always refers to the Start code 2 6 2 1 Assigning Interrupt Priority Levels As described in Section 2 6 1 4 on page 34 each enabled interrupt can be assigned to one interrupt priority level in range from 0 to 3 There are some exceptions from this rule for the particular interrupt sources which has assigned a fixed priority levels Also as there are only two bits four combinations to encode five different states of the interrupt source disabled level 0 level 3 there is always one priority level which cannot be set for any interrupt The 56800EX_Quick_Start tool hides these difficulties and implementation details described above and simplifies the conf
241. crystal oscillator Yes Core frequency 50 MHz VCO frequency 200 MHz Loss of lock interrupt 0 Disable Loss of lock interrupt 1 Disable Loss of reference clock Interrupt Disable DE define OCCS CTRL INIT 0x0081U define OCCS DIVBY INIT 0x2018U define OCCS USE FACTORY TRIM 1 define OCCS_USE_FACTORY_TRIM_TEMP 1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 35 Freescale Semiconductor Inc SYS Configuration SIM Power Saving Modes Stop enabled Wait enabled OnCE clock to processor core Enabled when core TAP enabled DMA Enable in RUN and WAIT modes DMA enabled in all power modes Enab External Reset Padcell Input Filter No SIM Clock on GPIO Enable CLKO 0 No SIM Clock on GPIO Enable CLKO 1 No SIM Peripheral Clock Enable GPIO F Yes GPIO E No GPIO D No GPIO C Yes GPIO B No GPIO A No TMR No TMR Al No TMR A2 No TMR No SCIO 5 1 Yes QSPIO No QSPI1 No IICO No FLEXCAN No CMP A No CMP B No CMP C No CMP D No CYC ADC No CRC No QDC No PITO PIT1 No DACA DACB No PWMCHO No PWMCH1 No PWMCH2 No PWMCH3 No SIM Modules Enabled in Stop GPIO F No SIM Modules Enabled in Stop GPIO E No SIM Modules Enabled in Stop GPIO D No SIM Modules Enabled in Stop GPIO C No SIM Modules Enabled in Stop GPIO B No SIM Modules Enabled in Sto
242. ctly register format FCAN_GET_RX_ERR_COUNT NULL Read RX error counter GET TX ERR COUNT NULL Read TX error counter Y FCAN GET MB MODULE UWord16 with MB index Get pointer to specified MB module Use the return value with FCANMB_ commands FCAN_RXFIFO_OPERATION FCAN_ENABLE FCAN_DIS Enable or disable the Receiver FIFO Y ABLE Beware this option breaks a compati bility with older FlexCAN modules The FIFO mode is not supported by the 56F800EX Quick Start FCAN ID ACCEPTANCE MODE FCAN ONE FULL ID Set FIFO ID filter Acceptance Mode Y FCAN TWO FULL STD ID Note that FIFO mode is not supported S FCAN FOUR PARTIAL by this version of the FCAN driver DS FCAN ALL FRAMES R EJECTED FCAN RXFIFO INT ENABLE FCAN RXFIFO OVERFLO Enable interrupts when operating in Y W INT FCAN RXFIFO WA FIFO mode Note that FIFO mode is RNING INT IFCAN FRAME not supported by this version of the S IN RXFIFO INT FCAN driver FCAN RXFIFO INT DISABLE FCAN RXFIFO OVERFLO Disable interrupts when operating in Y W INT FCAN RXFIFO WA FIFO mode Note that FIFO mode is RNING FRAME not supported by this version of the S IN RXFIFO INT FCAN driver FCAN READ RXFIFO FLAGS FCAN RXFIFO OVERFLO Read and test specified FIFO inter Y W INT FCAN RXFIFO WA rupts when operating in FIFO mode RNING INT IFCAN FRAME Note that FIFO mode is not supported S IN RXFIFO INT by this version of the FCAN driver DSC56800EX Quick Start User s Guide Rev 2 04 2015
243. d fault flags viv EFPWM_TEST_FAULTO_PINS EFPWM_FAULT_X 0 1 2 3 Return state of filtered fault pins viv EFPWM TEST FAULT1 FLAGS EFPWM FAULT 0111213 Return state of selected fault flags EFPWM_TEST_FAULT1_PINS EFPWM_FAULT_X 0 1 2 3 Return state of filtered fault pins viv EFPWM UPDATE MASK BITS IM EFPWM SUBO PWM X Masks selected PWM outputs MEDIATELY AJB X EFPWM SUB1 PW M X SUB2 PW viv M_X A B X EFPWM_SUB3_PW M X A B X EFPWM WRITE DEADTIME SOU UWord16 Writes prepared data in to the Dead viv RCE_REG time Source Select Register EFPWM WRITE FAULT CONTRO UWord16 Writes prepared data in to the Fault L REG Register EFPWM WRITE FAULT STATUS UWord16 Writes prepared data in to the Fault 21 Status Register EFPWM WRITE FAULTO CONTR UWord16 Writes prepared data in to the Fault sly OL_REG Register EFPWM_WRITE_FAULTO_STATUS UWord16 Writes prepared data in to the Fault viv REG Status Register EFPWM WRITE FAULT1 CONTR UWord16 Writes prepared data in to the Fault viv OL REG Register EFPWM WRITE FAULT1 STATUS UWord16 Writes prepared data in to the Fault 22 25 _REG Status Register EFPWM_WRITE_MASK_REG UWord16 Writes prepared data in to the Mask Ly Register EFPWM_WRITE_MASTER_CONT UWord16 Writes prepared data to the Master viv ROL REG Control Register EFPWM WRITE OUTPUT ENABL UWord16 Writes prepared data in to the Output Enable Register EFPWM WRITE SW CONTROL U
244. d instructions mainly as a result of the proper usage of the read modify write instructions These uninterruptible instructions are essential for safety when accessing the control and peripheral registers DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 1 Efficient use of the driver commands The general form of the driver command is the following ioctl peripheral module identifier command command specific parameter Where the Peripheral module identifier parameter is the base address of the peripheral module The predefined symbolic constants like OCCS A INTC ENC etc should be used The Command parameter specifies the action which will be performed on the peripheral module It represents the command name as it is implemented for each on chip driver The Command specific parameter parameter specifies other data required to execute the command Generally speaking it can be a pointer to the structure the NULL value or a variable value depending on the specific command If the required parameter is a variable value users should make use of a constant value if possible because it affects the efficiency of the resulting code The efficiency is illustrated by the following examples ioctl A SET MODULO 0x30ff constant used results in move l 0 145 move w 12543 X RO move w 12543 X 0xf145 while the following code sequence val 3276
245. d returns the result in result variable 2 5 29 2 impysu integer multiply signed 16b x unsigned 16b Call s Word32 impysu Wordl16 sig UWordl16 unsig Arguments Table 2 32 impysu arguments sig in first argument signed unsig in second argument unsigned Description The impysu function multiplies 16 bit signed integer and 16 bit unsigned integer as an and returns the 32 bit signed integer result Returns result of multiplication sig unsig Example 2 47 impysu function usage Wordl6 varl 32768 DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 30 Freescale Semiconductor Inc UWordl6 var2 655350 Word32 result result impysu varl var2 returns 2147450880 This code multiplies variables var and var2 and returns the result in result variable 2 5 29 3 shl2 optimized version of shl intrinsic function Call s Wordl6 8112 416 num 16 shifts Arguments Table 2 33 shl2 arguments num in parameter to be shifted shifts in number of shifts Description The shl2 function performs a multi bit arithmetic shift of the first parameter to the left by the amount specified in the second parameter The result is returned as a 16 bit integer This function is the optimized version of the shl intrinsic function see CodeWarrior Help for more information on shl Returns num parameter shifted shifts times to the left Example 2 48 shl
246. d until a counter reload occurs PDB SET FAULT C LENGTH PDB xxx Select the minimum width number of 2 5 CYCLES A 1 IP bus clock cycles of the input fault PBUS CYCLES when it is recognized as a valid fault condition PDB SET FAULT C POLARITY PDB xxx Select the Fault C polarity INDICATE FAU 22 LT FALSE_INDICATE_FAUL T PDB_SET_INIT_A_VALUE PDB_xxx Set the Trigger A output value which is xxx INIT_FALSE INIT_TRU forced when Fault A is active and E enabled by PDB SET FAULT A command In 2 COMBINED DELAY output mode the specified Trigger output value is also forced whenever the counter is reloaded DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 129 Table 5 54 PDB Driver Command Cmd pParam Description 56F82xxx 56F84xxx PDB SET INIT C VALUE PDB xxx FALSE INIT TRU E Set the Trigger C output value which is forced when Fault C is active and enabled by PDB SET FAULT C COMBINED DELAY CD output mode the specified Trigger C output value is also forced whenever the counter is reloaded PDB SET INPUT TRIGGER PDB TRIG xxx xxx SEL0 SEL1 SEL2 SEL3 SEL4 SEL5 SEL6 SW_TRIG Select the PDB Input trigger source Select one of seven input signals as a trigger The PDB module can also be triggered by software when SW_TRIG Y mode is selected Use the PDB SET SW TRIGGER command PDB SET LDOK NULL L
247. de Rev 2 04 2015 Freescale Semiconductor Inc 1 7 Other hardware requirements Mouse serial RS 232 port for local control network access for remote control 1 2 2 2 2 Target Development Board Requirements To enable the FreeMASTER connection to the target board application follow the instructions provided with the embedded side development tool The recommended and fastest way to start using FreeMASTER is by trying the sample application FreeMASTER software relies on the following items to be provided by the target development board Interface Serial communication port or the JTAG port available on all Freescale EVM boards Data RAM Memory Approximately 160 words of data memory plus the size of the recorder buffer is needed for the full configuration Optionally some features can be disabled to reduce required data memory size Program Flash Memory Required size is approximately 2K words for the full configuration Optionally some features can be removed to reduce required program memory size 1 2 2 2 3 Enabling FreeMASTER Target Application To enable the FreeMASTER operation on the target board application see description and an example in Chapter 6 FreeMASTER Driver 1 2 2 2 4 How to Install The FreeMASTER application is an optional part of the DSC56800EX_Quick_Start environment and must be installed separately e g running the FMASTERSW_v16 exe or later 1 2 3 Build and Run Sample Application Once th
248. de Rev 2 04 2015 Freescale Semiconductor Inc 2 25 This macro uses a single instruction to execute the operation and allows only constants as GroupMask and Mask arguments If the application requires the variable as argument the periphSafeBitGrpSetVar macro must be used instead Example 2 39 periphSafeBitGrpSet macro usage periphSafeBitGrpSet 0 0002 0x0004 0 00 0 0 0040 amp ArchlO HscmpA scr This code sets the HSCMP A module input hysteresis to 1 The rising edge and falling edge interrupt flags are not cleared 2 5 23 periphSafeBitGrpSetVar set bit group to given value and keep value of bit flags which are cleared by write one Call s void periphSafeBitGrpSetVar UWordl6 FlagGroupMask UWordl16 GroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 25 periphSafeBitGrpSeiVar arguments FlagGroupMask in Group mask of bit flags which are cleared by write one GroupMask in Group mask Mask in bit mask pAddr in The memory address Description The periphSafeBitGrpSetVar macro sets bit group to given value and keeps value of the bit flags which are cleared by write one in a peripheral memory location addressed by parameter pAddr The FlagGroupMask specifies all flags which are cleared by write one All bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value
249. dog Monitor EWM 5 75 5101 FIG FCAN DIVET 5 77 5 142 Flash Memory Module Driver rennen d ka Rr or rns 5 84 5 1 18 Flash Memory Module 0 200000 5 85 5 1 14 Flash Memory Controller FMC 5 86 58 1 15 General Purpose Input Output GPIO 5 87 5 1 16 High Speed Comparator HSCMP Driver 5 91 5 1 17 Inter Integrated Circuit IIC Driver 5 94 5 1 18 Interrupt Controller INTC Driver iccccccccssssisssoncnvnsarsonssessssansarieavacssesecoaoncnens 5 101 5 1 19 Miscellaneous Control Module Driver 5 103 5 1 20 Modular Scalable Controller Area Network MSCAN 5 104 5 1 21 On Chip Clock Synthesis OCCS 2 5 116 5 1 22 Periodic Interrupt Timer PIT 22 5 123 5 1 23 Power Management Controller 5 125 5 1 24 Programmable Delay 5 127 5 1 25 Quad Timer OT DIVET Ree rad aiai 5 135 5 1 26 Queued Serial Communication Interface SCI Drive
250. dundant watchdog system External Watchdog Monitor EWM is designed to monitor external circuits and the MCU software flow This provides a back up mechanism to the internal watchdog that resets the MCU s CPU and peripherals The EWM differs from the internal watchdog in that it does not reset the MCU s CPU and peripherals The EWM if allowed to time out provides an independent EWM_ out pin that when asserted resets or places an external circuit into a safe mode The CPU resets the EWM counter that is logically ANDed with an external digital input pin This pin allows an external circuit to influence the reset out signal Table 5 22 shows module identifiers for EWM Driver Table 5 22 Identifiers for EWM Driver Module identifier 56 82 56 84 Y Table 5 23 shows all commands for EWM Driver Y Table 5 23 EWM Driver Commands Description NIES LL LL EWM_CLEAR_COUNTER NULL Clear service the EWM counter both steps are performed EWM_DEVICE_CONFIG combination of EWM_xxx Configure the EWM device The com xxx INPUT_ENABLED EW mand may be used only once for the M_INT_ENABLED EWM_AS next time the reset is needed ERTION_ONE EWM_DEVIC because the register can be writtento v v E ENABLE only once after the CPU reset Modify ing these bits more than once gener ates a
251. e DAC output to be changed after the next update trigger signal which is either SYNC_IN or IP Bus clock DAC_WRITE_MAXVAL UWord16 Write the parameter value into the DAC Maximum Value Register This value is used anytime the DAC is switched to an automatic mode DAC_WRITE_MINVAL UWord16 Write the parameter value into the DAC Minimum Value Register This value is used anytime the DAC is switched to an automatic mode DAC_WRITE_STEP UWord16 Write the parameter value into the DAC STEP Register This value is used anytime the DAC is switched to an automatic mode DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 42 Freescale Semiconductor Inc 5 1 7 DMA Controller DMA Driver The DMA controller module enables fast transfers of data providing an efficient way to move blocks of data with minimal processor interaction The DMA module shown in the following figure has four channels that allow byte word or longword data transfers Each channel has a dedicated source address register SARn destination address register DARn status register DSRn byte count register BCRn and control register DCRn Collectively the combined program visible registers associated with each channel define a transfer control descriptor TCD All transfers are dual address moving data from a source memory location to a destination memory location with the module operating as a 32 bit bus mas
252. e 2 17 archDelay function usage archDelay 1000 DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 10 Freescale Semiconductor Inc 2 5 Macros for peripheral memory access This section describes macros for peripheral memory access The macros are used to read write set clear change the memory mapped on chip peripherals Using these macros offers a greater portability than simply referencing on chip peripherals with direct memory accesses All macros are defined in the periph h header file Required Header File s include types h include periph h 2 5 1 periphMemRead memory read Call s UWordl6 periphMemRead UWordl6 pAddr Arguments Table 2 3 periphMemHRead arguments pAddr in The memory address from which to read a 16 bit word Description The periphMemRead macro reads a 16 bit word from the memory location addressed by parameter pAddr Example 2 18 periphMemRead macro usage UWordl6 RegValue RegValue periphMemRead amp ArchlO TimerD ch0 hold This code reads the content of the timer counter DO Hold Register HOLD 2 5 2 periphMemWrite memory write Call s UWordl6 periphMemWrite UWordl16 Data UWordl16 pAddr Arguments Table 2 4 periphMemWrite arguments Data in The 16 bit data to write to the memory pAddr in The memory address to which to write a 16 bit word DSC56800EX Quick Start User s Guide Rev 2 04 2015 Free
253. e 4 4 DSC56800EX_Quick_Start Variable 9 Clean the project right clicking on the project a choosing Clean command 10 Build the application code by pressing Ctrl B or choosing Project gt Build All command Check if there is zero errors after the application building 11 Run the application by pressing the green arrow Run or choose the Run gt Run command from the menu Select a proper debug interface Upon completing all these actions the project window is displayed The project window contains the predefined file groups as follows ApplicationConfig contains the appconfig h header file SystemConfig contains startup c appconfig c vectors c linker files and debug interface configuration files LinkerFiles contains the target specific linker command files Internal_PFlash_LDM cmd Internal_PFlash_SDM cmd e sre Include contains header files for the driver source files MC56F8xxx Peripheral contains chip specific driver source files System contains arch c and arch h files Support FreeMASTER contains FreeMASTER software support files Now you can start writing your code in the C source file main c and configuring the on chip peripherals into the include file appconfig h either manually or by using the Graphical Configuration Tool GCT See Chapter 7 for GCT usage DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 4 4 2 On chip periphe
254. e B value value 0 to gA 255 EFPWMS_SET_COMPARE_X UWord16 Edge Compare X value value 0 to viv 255 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 63 Table 5 19 EFPWM Driver Commands AY_ENABLE 1 23 45 POWERUP gt lt Description ag 55 iO EFPWMS_SET_COMPLEMENTAR NULL Set pair operation to complementary Viv Y MODE EFPWMS SET DEADTIME 0 UWord16 Deadtime 0 logic value 0 to 2048 Xe Modify Deadtime Count Register 0 EFPWMS SET DEADTIME 1 UWord16 Deadtime 1 logic value 0 to 2048 214 Modify Deadtime Count Register 1 EFPWMS SET DOUBLE SWITCH EFPWM_ENABLE EFPWM_ Enable disable double switching 2152 ING DISABLE mode EFPWMS_SET_EDGE_ALIGN_MO UWord16 Range 0 to 32767 writes modulo DULO_INIT_REG value in to register and Init regis GA rage ter to prepare generating Edge Align output signal EFPWMS_SET_EDGE_COUNTER EFPWM_ENABLE EFPWM_ Enable disable edge counter A _ DISABLE EFPWMS_SET_EDGE_COUNTER EFPWM_ENABLE EFPWM_ Enable disable edge counter B I B DISABLE EFPWMS SET EDGE COUNTER EFPWM ENABLE EFPWM Enable disable edge counter X X DISABLE EFPWMS SET FORCE INIT EFPWM ENABLE EFPWM Enable disable force initialization DISABLE EFPWMS_SET_FORCE_INIT_PW EFPWM CHANNEL 45 EFP Determine the initial value and the MOUT TO HIGH WM CHANNEL 23
255. e DSC56800EX Quick Start tool is installed the user can build and run any released demo application for the TWR DSC modules by opening and building the project and using the CodeWarrior development environment pwm demo is used as an example in this case Two methods can be used to open an example project Import Step 2 amp 3 or drag amp drop Step 4 Step 1 Launch CodeWarrior IDE from the Start gt Programs gt Freescale CodeWarrior menu and open existing or create new Workspace Step 2 Choose File Import command and select General Existing Projects into Workspace and click on Next DSC56800EX Quick Start User s Guide Rev 2 04 2015 1 8 Freescale Semiconductor Inc _ Create new projects from an archive file or directory Select an import source gt General 19 Archive File 5 Existing Projects into Workspace Cj File System E Preferences amp C C A CadeWarrine Figure 1 6 Import Dialog Box Step 3 Select root directory of the example project e g DSCS56800EX_Quick_Start r2 6Nample applicationNMC56F8200TWRNpwm demo The example project might be copied into the CodeWarrior Workspace by ticking Copy project into workspace tick box and click on Finish 2 Import Projects Some projects cannot be imported because they already exist the workspace Select root directory C Freescale DSP56800E_Quick_Start 12 6_al sai
256. e Low Limit Register for sample6 v v ADC WRITE LOW LIMIT7 UWord16 Write Low Limit Register for sample 7 v v ADC WRITE LOW LIMIT8 UWord16 Write Low Limit Register for sample8 v v ADC WRITE LOW LIMIT9 UWord16 Write Low Limit Register for sample 9 v v ADC WRITE OFFSETO UWord16 Write Offset Register for sample 0 viv ADC_WRITE_OFFSET1 UWord16 Write Offset Register for sample 1 viv ADC_WRITE_OFFSET10 UWord16 Write Offset Register for sample 10 viv ADC_WRITE_OFFSET11 UWord16 Write Offset Register for sample 11 viv ADC_WRITE_OFFSET12 UWord16 Write Offset Register for sample 12 viv ADC_WRITE_OFFSET13 UWord16 Write Offset Register for sample 13 viv ADC_WRITE_OFFSET14 UWord16 Write Offset Register for sample 14 viv ADC_WRITE_OFFSET15 UWord16 Write Offset Register for sample 15 viv ADC_WRITE_OFFSET16 UWord16 Write Offset Register for sample 16 A ADC WRITE OFFSET17 UWord16 Write Offset Register for sample 17 A DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 19 Table 5 3 ADC Driver Commands Description ag iO ADC WRITE OFFSET18 UWord16 Write Offset Register for sample 18 4 ADC WRITE OFFSET19 UWord16 Write Offset Register for sample 19 A ADC WRITE OFFSET2 UWord16 Write Offset Register for sample 2 viv ADC WRITE OFFSET3 UWord16 Write Offset Register for sample 3 viv ADC_WRITE
257. e PWM A 3 DISMAPO INIT 0 0000 FE SCI 1 Configuration Baudrate 9601 bps Enable Receiver Enable Enable Transmitter Enable Data word length 8 bits Parity None DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 20 Polarity True polarity Loop mode Disable Function in Wait Mode SCI module enabled in Wait Mode Interrupts RX Full Disable RX Error Disable TX Empty Disable TX Empty Disable Enable RX and TX FIFO Queues Disable RX Active Edge Disable Enable TX DMA Disable Enable RX DMA Disable Hold off entry to stop mode No Rx Idle Interrupt enabled Disable ty define 5 1 5 0 0 2 0 define 5 1 5 0 000 0 define 5 1 5 2 0 00000 define SCI 1 RX BUFFER OKLIMIT 0 000 define SCI 1 BUFFER LOWLIMIT 0x000AU define SCI 1 SCICR3 INIT 0 00000 FMSTR Configuration st define FMSTR COMM INTERFAC define FMSTR LONG INTR define FMSTR SHORT INTR define FMSTR POLL DRIVEN define FMSTR USE define FMSTR USE Ez Fs End of autogenerated code KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RA endif DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 21 Freescale Semiconductor Inc Chapter 5 On chip Drivers One of the DSP56800EX_Quick_Start tool strengths is that it pro
258. e are also set or they are cleared if the corresponding bits in Mask value are cleared This macro uses a single instruction to execute the operation and allows only constants as GroupMask and Mask arguments If the application requires the variable as argument the periphBitGrpSRVar macro must be used instead Example 2 23 periphBitGrpSR macro usage periphBitGrpSR 0x007f 10 amp ArchIO Pll plldb This code sets the lower 7 bits of PLL Divide By register to the value 10 Other bits in the register are not affected 2 5 7 periphBitGrpSRVar set bit group to given value Call s void periphBitGrpSRVar UWordl16 GroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 9 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 14 Freescale Semiconductor Inc Description The periphBitGrpSRVar macro sets the bit group to given value a memory location addressed by parameter pAddr All bits specified by GroupMask are affected These bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared The SR variant uses two non interruptible instructions bfset and bfclr to accomplish the requested operation The bfset first sets the bits in the destination location and bfclr then clears the zero
259. e between the software and the hardware see Figure 1 1 This isolation enables a high degree of portability or architectural and hardware independence for application code This is mainly valid for devices with similar peripheral modules The driver code reuses lead for greater efficiency and performance APPLICATION 7 ON CHIP DRIVERS HARDWARE on chip peripheral modules Figure 1 1 Software Structure 1 1 1 3 Sample Applications The DSC56800EX_Quick_Start tool contains many sample applications that demonstrate how to use on chip drivers and how to implement some user specific tasks These sample examples are kept simple and illustrative and their intention is to minimize the learning curve 1 1 1 4 Graphical Configuration Tool The Graphical Configuration Tool GCT is a graphical user interface GUD designed to provide static chip and on chip peripheral module setting initialization including association of the interrupt vectors with user interrupt service routines The Graphical Configuration Tool is not required in order to use the DSC56800EX_Quick_Start environment 1 it is optional Nevertheless this tool simplifies the configuration of on chip peripheral DSC56800EX Quick Start User s Guide Rev 2 04 2015 1 2 Freescale Semiconductor Inc modules the device itself It also guides the user by supplying lot of useful information and hints It is therefore recommended to u
260. e critical bits are checked by the C preprocessor directive issuing the compile time warning when found in the OMR INIT value 2 7 2 1 3 if OMR INIT amp CM OMR R OMR 3A fwarning Initial OMR value might be invalid for the C project endif if OMR_INIT amp OMR_EX warning CodeWarrior cannot debug projects with OMR EX bit set Other appconfig h Symbols Using the OCCS_ REQUIRED LOCK MODE macro the user specifies in which lock state of the PLL the setup code continues to the rest of the startup code 0x20 default continue when coarse lock mode is reached bit LCKO in PLLSR 0x40 continue when fine lock mode is reached bit LCK1 in PLLSR ifndef OCCS_ define OCCS_ REQUIRED MODI REQUIRED MODI P P 0x20 coarse LCK0 by default fif OCCS REO LOCK MODE 0x40 amp amp OCCS REQUIRED LOCK MOD error OCCS R E 0x20 EQUIRED LOCK MODE must be one of 0x20 coarse or 0x40 1 One of the startup code optional features is to perform the internal data RAM checking The checking algorithm fully described later in Section 2 7 2 2 6 uses two values which writes reads and verifies to check each memory location By default the two values are OXAAAA and 0 5555 If there is any reason to ch
261. e interrupt PMC_xxx_LEVEL sy 1_27 1_22 1 27V LVI_22V PMC_INT_SELECT combination of Enable the selected low voltage inter PMC_xxx_LEVEL rupts XN xxx HVI 27 22VI LVI 27V LVI 22V PMC READ CTRL REG NULL Read and return the value of PMC v a Control register as UWord16 PMC READ STATUS REG NULL Read and return the PMC Status reg ister as UWord16 SET ADC VOLTAGE REF _ PMC ENABLE PMC DISAB Enable disable the voltage reference BUFFER LE buffer that drives the 1 2V bandgap viv reference to the ADC PMC SET BANDGAP TRIM UWord16 value 0 15 Set the trim value of the bandgap ref erence in the regulator Its reset state viv is the mid range PMC TEST FLAG combination of Test the selected flags PMC xxx FLAG ee xxx STICKY_LV27 STICKY LV22 LV 27V LV 22V PMC WRITE CTRL REG UWord16 Write to the PMC Control register viv PMC_WRITE_STATUS_REG UWord16 Write to the PMC Status register Note An inappropriate write to regis v ur 5 126 Freescale Semiconductor Inc 5 1 24 Programmable Delay Block The primary function of the programmable delay block PDB is simply to provide a controllable delay from the PWM SYNC output to the sample trigger input of the programmable gain amplifiers and ADCs as well as a controllable window that is synchronized with PWM pulses for analog comparators to compare the analog signals in a defined window The PDB provides the following features 16 b
262. e of capture DMA DMA disabled Enable DMA Write Requests For alue Registers No Output Trigger 0 Source PWM_OUT_TRIGO Output Trigger 1 Source PWM OUT TRIGI zt define PWM A 1 CTRL INIT 0x0400U define PWM A 1 CTRL2 INIT 0x0206U define 1 INIT INIT OxF 95CU define 1 VAL1_INIT 0x06A3U define 1 VALO INIT 0x0000U define PWM A 1 VAL2 INIT 0x0000U define PWM A 1 VAL3 INIT 0x0000U define A 1 VALA4 INIT 0x0000U define 1 VAL5 INIT 0x0000U define A 1 FRACVAL2 INIT 0x0000U define A 1 FRACVAL3 INIT 0x0000U define A 1 FRACVALA INIT 0x0000U define PWM A 1 FRACVAL5 INIT 0x0000U define 1 DTCNTO INI 0x0000U define 1 DTCNT1 INI 0x0000U define A 1 DISMAPO INIT OxFOOO0U _2 Configuration Debug Mode Operation Stop Wait Mode Operation Stop Load Mode End cycle Load OK No PWM Clock Enable Yes Clock Source PWM_O clock Prescaler 1 1 INIT register 1700 VAL1 register 1699 Fraction FRACVAL1 0 Sync source Master sync 0 Reload source 0 module Reload Frequency Every opportunity Half Cycle Reload Disable Full Cycle Reload Enable PWMA Mask Normal Mask Norma Mask Norma Output Polarity Active High Output Polarity Active High Output Polarity Active High Output enable Enabled Output enable Enabled Output enable Disabled PWMA and PWMB Pair Operation Complement
263. e peripheral modules are different Therefore it is preferred to use ioctl read and write commands instead of the direct access to the peripheral module registers The direct access to the peripheral registers is performed by periphMemWrite periphMemRead and other predefined macros described in Section 2 5 4 3 1 ioctl The ioctl command is used to initialize a peripheral module see Section 4 2 and to access a peripheral module Use of the ioctl command provides a very efficient and easy way to access a peripheral module It increases the code portability and readability and thus decrease the number of bugs in the developed code The general syntax of the ioctl command is as follows DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 6 ioctl peripheral module identifier command command specific parameter or if ioctl command returns a value var ioctl peripheral module identifier command command specific parameter Where e Peripheral module identifier parameter is the base address of the peripheral module Instead of passing the raw base address e g 200 you can use the predefined symbolic constants OCCS QTIMER INTC etc e Command parameter specifies the action which will be performed on the peripheral module The list of all commands available can be found in Chapter 5 On chip Drivers e Command specific parameter parameter specifies other data required to ex
264. e returned value is in the raw format as it is stored in the MB registers so further conversions are needed to obtain a numeric represen tation of the message identifier MSCANMB GET LEN NULL Return the length of the frame data part currently stored in the message buffer as UWord16 value 0 8 MSCANMB_GET_RTR NULL Return a non zero value as UWord16 if the RTR flag is set in the Message Buffer DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 113 Table 5 46 MSCANMB Driver Commands Cmd pParam Description 56F82xxx 56F84xxx MSCANMB_GET_TIMESTAMP NULL Return the time stamp value as UWord16 which was assigned to this message buffer The time stamp is a value of the free running timer counter captured at the time the message was received or transmitted from to the CAN bus The time stamp timer must be enabled in order to generate valid time stamp values MSCANMB_SET_ID 32bit Identifier value con stant Use an OR combina tion of the ID numeric value and the following constants MSCAN ID xxx xxx EXT RTR Assign the CAN message identifier to the specified Message Buffer and clears or sets the Remote Transmit Request flag in the MB The identifier value passed to this ioctl command should contain information about whether it is specified in the standard 11 bit format or extended 29 bit for mat The most signi
265. eared while waiting in the loop move w d4PLLCR TEMP ArchIO Pll pllcr PLL lock detector ON core still on prescaler 11 lock move w 1 R5 clear COP watchdog counter while waiting in the loop move w D1 X R5 brclr OCCS REQUIRED LOCK MODE ArchIO Pll pllsr pll lock test lock LCK1 or LCKO When the PLL is locked the system clock is switched to PLL and the PLLCR is finally initialized with the user defined value As the last the pending PLL interrupts are cleared nop nop move w OCCS PLLCR INIT ArchIO Pll pllcr PLL locked final PLL setup DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 52 Freescale Semiconductor Inc skip_pll_lock move w ArchIO Pll pllsr x0 clear pending clkgen interrupts move w x0 ArchIO Pll pllsr nop If the PLL is not to be enabled the initial value of the PLL Control Register is simply written 1 OCCS PLLCR INIT amp 1 PLL not active move w OCCS PLLCR INIT ArchIO Pll pllcr endif OCCS PLLCR INIT 1 2 7 2 2 6 Internal Memory Checking Checking the internal data RAM is an optional feature of the startup code When the INTXRAM CHECK ENABLED macro is defined in appconfig h this feature is activated The memory checking process consists of tree parts Complete memory fill value OXAAAA amp read compare e Single write read compare for each memory location e Two immediate reads from different
266. ect specific folders which hold the configuration files the project build files and the CodeWarrior private data files The specific board configuration is stored in board h header files placed in MC56F8200TWR MC56F8400TWR directory 3 3 Tools Directory The fools directory contains the Graphical Configuration Tool executable application the needed libraries and the help files 3 4 Src Directory The sre or source directory is intended to hold all source files Its structure is shown in Figure 3 3 The sre directory is further divided into the following subdirectories algorithms optional can contain the distributed algorithms and the user algorithms e 56 8 is the directory specific for each of the supported devices The subdirectory peripheral contains the source code for all on chip peripheral drivers and the system subdirectory contains the device specific source files e include contains the common DSP56800EX Quick Start header files which define APIs and the implementation of generally used macro s support contains other common DSP56800EX Quick Start source files The subdirectory freemaster contains the source files to enable the FreeMASTER operation on the target board application The directory compat is there because of compatibility with older DSP56800E Quick Start releases DSC56800EX Quick Start User s Guide Rev 2 04 2015 3 2 Freescale Semiconductor Inc 3C MC56F82
267. ecute the command Example 4 2 Using ioctl ioctl GPIO B GPIO SET PIN BIT 1 BIT 2 ioctl ADC A ADC START NULL ioctl QTIMER 1 QT CLEAR FLAG QT COMPARE FLAG This example shows a miscellaneous ioctl commands Note the parameters are the first one specifies the peripheral module GPIO B General Purpose Input Output B ADC A Analog to Digital Converter A QTIMER timer counter A1 the second one 15 the command GPIO SET PIN to set pin ADC START to start A D conversion QT CLEAR FLAG to clear flag and the third one is the command specific parameter BIT 1 2 to specify that bits 1 and 2 will be set NULL no parameter is used QT COMPARE FLAG to clear timer compare flag See Chapter 5 On chip Drivers where all ioctl commands and their detailed descriptions can be found Tip To see all available ioctl commands and their parameters from within CodeWarrior IDE just open the appropriate name of driver h include file e g intc h Interrupt Controller driver include file pwm h Pulse Width Modulation driver include file etc and at the beginning of the file there is a list of all implemented ioctl commands 4 3 2 read The read function reads a specified number of words from the SCI or SPI module to an user allocated buffer This function can operate in Blocking mode it waits till end of operation NonBlocking mode it exits from the function im
268. ed code To install CodeWarrior for Microcontrollers V 10 3 it is recommended to use the installation guide attached to the actual version of CodeWarrior for Microcontrollers if available 1 2 2 Install DSC56800EX Quick Start In order for the DSC56800EX Quick Start to integrate itself with the development tools the CodeWarrior tools should be installed prior to the installation of D5C56800EX Quick Start installation see previous section If the DSC56800EX Quick Start tool is installed while CodeWarrior is not present users can only browse the installed software package but will not be able to build download and run the released code However the installation can be simply completed once CodeWarrior is installed see Section 1 2 1 The installation itself consists of copying the required files to the destination hard drive checking the presence of CodeWarrior and creating the shortcut under the Start 2 Programs menu It is recommended to use the default installation directory path c Freescale NOTE Each DSC56800EX Quick Start release is installed in its own new directory named 25 56800 Quick Start rX Y where X Y denotes the release number Thus it enables to maintain the older releases and projects It gives free choice to select the active release To start the installation process perform the following steps 1 Execute DSC56800EX Quick Start rXY exe 2 Follow the DSC56800EX Quick Start software installation instructions o
269. edicated for QT Driver DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 135 Table 5 56 Driver Commands gt lt gt lt x x Cmd pParam Description e e 515 i QT CLEAR COMPARE FLAG combination of Clear the selected timer counter com COMPARE1 FLAG QT pare flags viv COMPARE2_FLAG QT_CLEAR_FLAG combination of Clear the selected timer counter flags QT_xxx_FLAG xxx COM Specify combination of Timer Com PARE OVER pare Flag Timer Overflow Flag v v FLOW INPUT_EDGE VAL TOF Input Edge Flag IEF and Forced OFLAG Value flag VAL QT_CO_CHANNEL_INIT QT_ENABLE QT_DISABLE Enable disable another timer counter in the same Quad Timer module to force the re initialization of this 20112 timer counter when it has encoun tered an active compare event co channel initialization QT_DMA_READ_REQ_CMPLD1 QT_ENABLE QT_DISABLE Enable disable DMA write requests for CMPLD1 whenever data is transferred sell ay out of the CMPLD1 register into the register QT DMA READ REQ CMPLD2 QT ENABLE QT DISABLE Enable DMA write requests for CMPLD2 whenever data is transferred out of the CMPLD2 register into the CNTR or COMP2 registers QT_DMA_WRITE_REQ QT_ENABLE QT_DISABLE Enables DMA read requests for CAPT 2122 when Input Edge Flag gets set QT_EXT_OFLAG_FORCE QT_ENABLE QT_DISABLE Enable disable the external OFLAG force This mea
270. egister G_10 10 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register 2132 G 11 11 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 252 12 12 WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register PE G 13 13 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 241 32 G 14 14 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register 252 G 15 15 WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register Pte G 16 16 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register siy G_17 17 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register G 18 18 WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register viv G_19 19 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register NT G2 2 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register ME G 20 20 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 21 21 XBAR_A_WRITE_CROSSBAR_RE UWord16 Write the Crossbar A Select Register 2 22 22 WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register G 23 23 XBAR A WRITE CROSSBAR RE UWord16 Write the Crossbar A Select Register 2 24 24 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 173 Table 5 64 Driver Commands
271. egistered as a application command handler see main below It gets automatically invoked when the PC FreeMASTER application sends appropriate application command static FMSTR_APPCMD_RESULT myhandler FMSTR_APPCMD_CODE FMSTR_APPCMD_PDATA pData FMSTR SIZE nDataLen the return value is used as the application command result code return FMSTR APPCMD RESULT 0x10 int main void UWordl6 nAppCmdCode initialize SYS and GPIO modules ioctl COP COP INIT NULL ioctl SYS SYS INIT NULL ioctl GPIO GPIO INIT ALL NULL initialize UART ioctl SCI RS232 SCI INIT NULL initialize MSCAN modul alternative FreeMASTER interface ioctl MSCAN MSCAN INIT NULL FreeMASTER initialization FMSTR Init registerring the App Command handler FMSTR_RegisterAppCmdCal1 10 myhandler initialize amp enable interrupts ioctl INTC INTC INIT NULL archEnableInt other initializations var8 10 main application loop while 1 feed the dog ioctl COP CLEAR COUNTER NULL scope variables DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 34 varl6 varl6inc var32 var32inc the application commands not registered with cal
272. eing used To prevent loss of clock to the viv core or the PLL set this bit only if the prescaler clock source has been changed to the crystal oscillator OCCS_LOCK_DETECTOR OCCS ENABLE OCCS DIS Enable disable the lock detector RET ABLE OCCS POWER MODE OCCS HIGH POWER OCC Set the resonator or crystal power sly S LOW POWER mode OCCS READ CLOCK CHECK RE NULL Read and return the result of clock FERENCE checking function for internal refer ence clock as UWord16 OCCS_READ_CLOCK_CHECK_TA NULL Read and return the result of clock RGET checking function for external clockas v v UWord16 OCCS READ CONTROL REG NULL Read and return the content of the TANT DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 118 Freescale Semiconductor Inc Table 5 48 OCCS Driver Commands Cmd pParam Description 56F82xxx 56F84xxx OCCS_READ_DIVIDE_BY_REG NULL Read and return the content of the PLL Divide by register as UWord16 lt lt OCCS_READ_FLAG combination of OCCS_STATUS_ xxx xxx LOCK_LOST_INT1 LO CK_LOST_INTO CLOCK_LO ST LOCK_1 LOCK_0 POWE R_DOWN ZCLOCK CRYSTA L READY Return zero if flag is cleared non zero if flag is set OCCS READ OSC CONTROL R EG NULL Read and return the content of the Oscillator Control register as UWord16 OCCS READ OSC CONTROL2 R EG NULL Read and return the content of the Oscillator Control 2 register as UWord16
273. en the position counter POS rolls over from the MOD value to the INIT value or from Oxffffffff to 2 0x00000000 roll under interrupt request is set when the position counter POS rolls under from the INIT value to the MOD value or from 0x00000000 to ENC_READ_CONTROL_REG NULL Read and return the value of the Con 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 70 Freescale Semiconductor Inc Table 5 21 ENC Driver Command Description ag 5 Lre ENC_READ_CTRL2_REG NULL Read and return the value of the Con 2 trol 2 register UWord16 ENC READ HOLD DATA REGS pointer to decoder sState Read consistent snapshot of values of type the Upper and Lower Position Counter Registers UPOS the Position Difference Counter Register POSD Y and the Revolution Counter Register REV The values are filled to struc ture passed to a parameter ENC READ MONITOR REG NULL Read and return the content of the Input Monitor Register IMR as Y UWord16 ENC READ POSITION pointer to the Read the content of the Upper and the decoder uReg32bit type or Lower Position Counter registers Y to UWord32 UPOS LPOS ENC READ POSITION DIFFERE NULL Read and return the value of the Posi NCE tion Difference Counter register Y POSD as UWord16 ENC_READ_REVOLUTION NULL Read and return the value of the Rev olution Count
274. entation None Example 6 9 FMSTR AppCmdAck switch nAppCmdCode 1 pData FMSTR_GetAppCmdData NULL FMSTR AppCmdAck 0x13 break case 2 This code shows how to finish an Application Command processing DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 21 Freescale Semiconductor Inc 6 6 1 10 FMSTR_AppCmdSetResponseData Set Application Command response data Call void FMSTR_AppCmdSetResponseData FMSTR_ADDR nResultDataAddr FMSTR SIZE nResultDataLen Arguments nResultDataAddr in pointer to data buffer which is to be copied to the Application Command data buffer nResultDataLen in the length of a data to be copied Must not exceed the FMSTR_APPCMD_BUFF_SIZE value Description This function can be used before the Application Command processing is finished when there are any data to be returned back to the PC This function exists as such a feature is enabled by the FreeMASTER protocol However the current version of the FreeMASTER tool does not support the Application Command response data Returns None Range Issues None Special Issues The response data buffer is copied to the Application Command data buffer from where it is accessed in case the host requires it Do not use the FMSTR_GetAppCmdData and the data buffer after the FMSTR_AppCmdSetResponseData is called Design Implementation None Example 6 10 FMSTR GetAppCmdData switch nAppCmdCode case 1
275. entation This function saves and restores all registers used so itis possible to invoke this function from an interrupt service routine safely Example 6 4 FMSTR Recorder pragma interrupt void timer isr FMSTR Recorder This code shows how the FMSTR Recorder function is invoked as a part of Timer interrupt service routine DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 16 6 6 1 5 FMSTR_TriggerRec Force recorder trigger Call void FMSTR_TriggerRec void Arguments None Description This function forces the recorder trigger condition to happen which causes the recorder to be automatically de activated after a post trigger samples are sampled This function can be used in the application when it needs to have the trigger occurrence under its control Returns None Range Issues None Special Issues None Design Implementation None Example 6 5 FMSTR_TriggerRec FMSTR TriggerRec This code shows how the FMSTR TriggerRec function is invoked DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 17 Freescale Semiconductor Inc 6 6 1 6 FMSTR_SetUpRecBuff Set the recorder buffer Call void FMSTR SetUpRecBuff FMSTR ADDR nBuffAddr FMSTR SIZE nBuffSize Arguments nBuffAddr a pointer to the memory which is to be used as a recorder buffer nBuffSize a size of the memory buffer Description This function can only be used
276. er 2 5 16 19 LLSx bit Low Limit Sample x DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 6 Freescale Semiconductor Inc Table 5 3 ADC Driver Commands Description ag 515 ADC_CLEAR_LOW_LIMIT_STATU UWord32 any combination Clear selected bits in the ADC Low 2 512 BITS of ADC_LLSx bits x 0 19 Limit Status Registers 1 and 2 ADC_CLEAR_LOW_LIMIT_STATU UWord16 any combination Clear selected bits in the ADC Low 2 S2 BITS of ADC_LLSx bits x 16 19 Limit Status Register 2 ADC CLEAR STATUS EOSI NULL Clear selected ADC EOSI status in the ADC CONVERTER OJADC Control Register CONVERTER_1 ADC_CLEAR_STATUS_HLMTI NULL Clear all HILIM status bits in the High P m Limit Status Register ADC CLEAR STATUS LLMTI NULL Clear all LOLIM status bits in the Low 21 Limit Status Register ADC CLEAR STATUS 4201 NULL Clear all ZCI status bits in the Zero sg Crossing Status Register ADC CLEAR STATUS12 HLMTI NULL Clear all HILIM status bits for all sam ples 0 19 in the High Limit Status Reg isters 1 and 2 ADC CLEAR STATUS12 LLMTI NULL Clear all LOLIM status bits for all sam ples 0 19 in the Low Limit Status Reg isters 1 and 2 ADC CLEAR STATUS12 ZCI NULL Clear all ZCI status bits for all samples 0 19 in the Zero Crossing Status Reg isters 1 and 2 ADC CLEAR
277. er register REV as Y UWord16 ENC REVOLUTION COUNTER M ENC REV INDEX ENC RE Select the revolution counter REV OD ENABLE V MODULUS source By default REV is controlled based on the count direction and the INDEX pulse REV be controlled using the roll over under detection during modulo counting ENC SET DECODER SIGNAL P ENC POSITIVE ENC NEGA Setthe polarity of the quadrature 2 OLARITY TIVE decoder signal DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 71 Table 5 21 ENC Driver Command Cmd pParam Description 56F82xxx 56F84xxx ENC SET MODULO COUNTING ENC ENABLE ENC DISAB Enable disable the position counters LE UPOS and LPOS to count in a mod ulo fashion using MOD and INIT as the upper and lower bounds of the counting range During modulo count ing when a count up is indicated and the position counter is equal to MOD then the postion counter will be reloaded with the value of INIT When a count down is indicated and the position counter is equal to INIT then the position counter will be reloaded with the value of MOD When clear then the values of MOD and INIT are ignored and the position counter wraps around the 0 value ENC SET POSMATCH OUTPUT POS COMP Select the behavior of the POS ENC REGS READ MATCH output signal The POS MATCH output can be used to trigger a timer channel to record the time stamp Use ENC POS COMP MATCH to
278. ere is just a single buffer to hold the Application Command data the buffer length is FMSTR APPCMD BUFF SIZE bytes In case the data are to be used in the application after the command is processed by the FMSTR AppCmdAck call the user needs to copy the data out to a private buffer Returns Pointer to Application Command data Range Issues None Special Issues None Design Implementation None Example 6 8 FMSTR_GetAppCmdData switch nAppCmdCode 1 pData FMSTR_GetAppCmdData NULL FMSTR AppCmdAck 0x13 break case 2 This code shows how to get the Application Command data when processing the Command DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 20 6 6 1 9 FMSTR AppCmdAck Finish processing of the Application Command Call void FMSTR AppCmdAck FMSTR APPCMD RESULT nResultCode Arguments nResultCode in the result code which is to be returned to the FreeMASTER tool Description This function is used when Application Command processing is finished in the application The nResultCode passed to this function is returned back to the FreeMASTER tool and the driver is re initialized to expect other Application Commands After this function is called and before the next Application Command arrives the return value of the FMSTR GetAppCmd function is FMSTR APPCMDRESULT NOCMD Returns None Range Issues None Special Issues None Design Implem
279. ers for MSCAN 2 0 00 0 0 nennen nenne 5 104 5 44 5 104 5 45 Identifiers for MSCAN Driver 5 113 5 46 MSCANMB Driver 5 5 113 5 47 Identifiers Tor 5 116 DSC56800EX Quick Start User s Guide Rev 2 04 2015 viii Freescale Semiconductor Table Number 5 48 5 49 5 50 5 51 5 52 5 53 5 54 5 55 5 56 5 57 5 58 5 59 5 60 5 61 5 62 5 63 5 64 6 1 6 2 6 3 9 1 Tables Page Title Number OCCS S 5 116 identifiers tor PIT 5 123 PIT Diver Command gt RETE 5 123 Identifiers for PMC DEVE leti 5 125 PMC Driver u PETER rr PES 5 125 Identifiers Tor PDB iki hd rl Xa ek d eR RR RR xe RR i 5 127 PDB Driver EU MEE UR HR OD Hat pa Cr eR 5 127 Identifiers for LATIMER DEBE 5 135 QT Driver rhe addo dtc addetto 5 136 ldentifiers tot DEBE Lao bt ri btt daa ers dieta dad uda d cn E a RR MERE CERE 5 142 22 08 Driver a dedita
280. escale Semiconductor Inc 5 1 17 Inter Integrated Circuit Driver The inter integrated circuit PC I2C or module provides a method of communication between a number of devices The interface is designed to operate up to 100 kbit s with maximum bus loading and timing The device is capable of operating at higher baud rates up to a maximum of clock 20 with reduced bus loading Table 5 37 shows module identifiers for I2C Driver Table 5 37 Identifiers for I2C Driver Module identifier 56 82 56F84xxx I2C 0 Y IC 1 Y Table 5 38 shows all commands dedicated for IICDriver Table 5 38 IIC Driver Commands the slave operation DSC56800EX Quick Start User s Guide Rev 2 04 2015 gt lt gt lt gt lt Description isan LL LL iO CLEAR ARBITRATION LOST NULL Clear arbitration lost flag viv IIC_CLEAR_HIGH_TIMEOUT_FLA NULL Clear the High Timeout flag 2 by writ G2 ing 1 to it CLEAR 1 BUS INT NULL Clear the I Bus interrupt flag A CLEAR LOW TIMEOUT FLAG NULL Clear low timeout flags viv IIC_CLEAR_STOP_START_FLAGS combination of Clear the start stop detection flags xxx FLAG viv xxx STOP START IIC_CLEAR_TIMEOUT_FLAGS combination of IIC_xxx Clear selected timeout flags by writing xxx LOW_TIMEOUT HIGH_ 1 to them viv TIMEO
281. eturn the 8 bit value of the MSCAN Transmit Error Counter Register Y CANTXERR MSCAN GET WINNING ACC FIL NULL Return an index of the acceptance fil TER ter as UWord16 value 0 7 which was 7 hit during reception of a message rently available in the receive buffer DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 105 Table 5 44 MSCAN Driver Commands Description ag 5 NULL Initialize the MSCAN peripheral regis ters using the appconfig h _ INIT val Y ues MSCAN LISTEN ONLY MODE MSCAN ENABLE MSCAN Enable disable the listen only mode in DISABLE which the module does not drive the Y ACK signal MSCAN LOOPBACK MODE MSCAN ENABLE MSCAN _ Enable disable the test loopback 2 DISABLE mode MSCAN_MANUAL_BOFF_RECOV MSCAN ENABLE MSCAN Enable disable the manual bus off 5 ERY DISABLE recovery mode MSCAN READ ABORT ACK NULL Read and return the transmission abort acknowledge flags for those buffers which were not transmitted due to a call of the 2 MSCAN_ABORT_TRANSMIT ioctl command The returned value may be tested for occurrence of MSCAN TXBUFFERx flags MSCAN READ EINT FLAGS NULL Return the Error interrupt flags This command is typically used in the MSCAN error interrupt service routine to retrieve the error interrupt events to be handled The 5 MSCAN_CLEAR_EINT_FLAGS mand can then be used to
282. f the CAN bit timing machine The SJW is specified in the 2 time quanta units and is always at least 1 tq See the CAN standard doc ument for more information MSCAN_SET_TSEG1 UWord16 value 4 16 The Time Segment 1 parameter of the CAN bit timing machine The Time Segment 1 is specified in time quanta gt units and is always at least 1 tq the CAN standard document for more information MSCAN_SET_TSEG2 UWord16 value 2 8 Set the Time Segment 2 parameter of the CAN bit timing machine The Time Segment 2 is specified in time quanta units and is always at least 1 tq See the CAN standard document for more information MSCAN_SLEEP MSCAN_ON MSCAN_OFF Enter ON or leave OFF the sleep state of the MSCAN module MSCAN_SOFT_RESET MSCAN_ON MSCAN_OFF Enter leave the internal soft reset state of the MSCAN module In case of entering the reset state any ongo Y ing transmission or reception is quit and synchronization to the bus is lost MSCAN STOP IN WAIT MSCAN ENABLE MSCAN Enable disable the low power sleep DISABLE mode of the MSCAN module in the Y CPU wait mode MSCAN TEST BUSOFF HOLD NULL Return a non zero value when the MSCAN module is stuck in the bus off state This may happen if manual bus off recovery mode was configured for the MSCAN module The bus off state may be recovered using the MSCAN RECOVER BUSOFF STAT E ioctl command MSCAN TEST RXACT NULL Return a non zero value if the MSCAN module is
283. f the PLL Control Register initial value is defined appconfig h the PLL setup code is executed ifdef OCCS_PLLCR_INIT On the new devices e g 56 82 56 84 all pins are in the GPIO mode after reset including the pins which may be needed as an external clock or crystal source The startup code automatically re configures these pins to the required clock related mode before switching to an external clock The new devices are identified by OCCS version 6 or 7 and SIM version 7 or 8 in the new code NOTE The peripheral module version identifiers are defined in the arch h file for each device purely for an internal use the DSP56800EX Quick Start code The version numbers do not rely to chip or silicon version DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 50 Freescale Semiconductor Inc on new devices som xternal pins may be needed if PLLCR PRESC 1 if defined OCCS VERSION 6 defined OCCS VERSION 7 amp amp defined SIM VERSION 7 defined SIM VERSION 8 amp amp OCCS PLLCR INIT amp 0 4 T first get EXT SEL and CLK MODE values see OSCTL register ifdef OCCS 05 11 INIT define OCCS EXTSEL OCCS OSCTL1 INIT gt gt 10 6 0 1 define OCCS CLKMODE OCCS OSCTL1 INIT gt gt 12 amp 0 1 else define OCCS EXTSEL 1 reset value is 1 define OCCS CLKMODE 1 reset value is 1
284. ficant bit MSB is reserved for this purpose You can use the predefined MSCAN ID EXT constant OR ed with the ID value being passed to the ioctl to set the MSB MSCANMB SET ID RAW UWord32 ID raw value Assign the CAN message identifier to the specified Message Buffer This command behaves in a similar man ner as the MSCANMB SET ID ioctl command except that the passed identifier value must already be in the raw format suitable for writing into the IDR registers of the Message Buffer structure MSCANMB SET ID V 32bit Identifier value vari able Use an OR combina tion of the ID numeric value and the following constants MSCAN ID xxx Assign the message identifier to the specified Message Buffer This command operates in the same way as the MSCANMB_SET_ID com mand except that the MSCANMB_SET_ID_V ioctl com mand is implemented as a function call and it is thus more suitable for passing the 32 bit identifier stored in the caller s variable DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 114 Freescale Semiconductor Inc Table 5 46 MSCANMB Driver Commands Cmd pParam Description 56F82xxx 56F84xxx MSCANMB_SET_LEN UWord16 value 0 8 Set the message length field of the specified message buffer structure Typically the length is set before the message is to be transmitted onto the CAN bus lt 5 S
285. g for GCT might be set g Open Window gt Preferences dialog box h Search for keys and run last in Preferences window 1 Select Run Last Launched External Tool in command menu DSC56800EX Quick Start User s Guide Rev 2 04 2015 1 6 Freescale Semiconductor Inc j Set required binding Run Last Launched External Command Unbind Command Restore Command Name Description Conflicts Figure 1 5 GCT Key Binding k Click on Apply and buttons Now you should be able to execute the Graphical Configuration Tool from the CodeWarrior IDE menu Run gt External Tools gt GCT by clicking on the icon or by pressing the chosen key shortcut Note that the DSC56800EX_Quick_Start project should be open in the Workspace to quickly execute the Graphical Configuration Tool 1 2 2 2 Install FreeMASTER PC Master Software 1 2 2 2 1 System Requirements The FreeMASTER application can run on any computer with Microsoft Windows 98 or later operating system Before installing the Internet Explorer 4 5 5 or higher Operating system Microsoft Windows XP Windows 2000 Windows NT4 with SP6 Windows 98 through Window 7 on the host side Required software Internet Explorer 4 5 5 or higher installed For selected features e g regular expression based parsing Internet Explorer 5 5 or higher is required Hard drive space 108 MB DSC56800EX Quick Start User s Gui
286. ge pin function selection 2 PWMA_FAULT2 SYS SET G5PAD FUNCTION one of SYS G5PAD xxx Package pin function selection 2 PWMA_FAULT3 SYS_SET_G6PAD_FUNCTION one of SYS_G6PAD_xxx Package pin function selection PWMA_FAULT4 TB2 XB_O Y UT8 SYS SET G7PAD FUNCTION one of SYS G7PAD xxx Package pin function selection 2 PWMA_FAULT5 XB_OUT9 SYS SET G8PAD FUNCTION one of SYS G8PAD xxx Package pin function selection 2 0 2 OUT10 SYS SET G9PAD FUNCTION one of SYS G9PAD xxx Package pin function selection PWMA 1 OUT11 Y SYS SET LOW POWER MODE SYS ENABLE SYS DISABL Cause the device to enter exit FX E LPMODE SYS SET POWER MODE SYS NORMAL POWER SY Control the operation mode of the S REDUCED POWER device 21 22 SYS POWER MODE PER MANENT SYS SET PWMAFO INPUT one of SYS PWMAFO xxx SCIO input selection 2 GPIO E8 XB 0 29 SYS SET PWMAF1 INPUT one of SYS PWMAF1 xxx SCIO input selection 2 GPIO_E9 XB_OUT30 SYS_SET_PWMAF2_INPUT one of SYS PWMAF2 xxx SCIO input selection 2 GPIO_G4 XB_OUT31 SYS_SET_PWMAF3_INPUT one of SYS_PWMAF3_ xxx 5010 input selection 2 GPIO_G5 XB_OUT32 SYS SET SCIO INPUT one of SYS SCIO xxx SCIO input selection OUT38 SYS SET 5011 INPUT one of SYS 5011 xxx SCI1 input selection 2 12 9 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 161 Table 5 62 SYS Driver Commands
287. gins the transfer in accor 224152 dance to the values the TCDn DMA_SET_TRANSFER_MODE DMA_SINGLE DMA_CONTI Select single read write transfers per NUOUS request or continuous read write siy transfers until the BCR decrements to zero DMA_WRITE_DCR UWord32 Write the parameter value into chan sly nel n DMA_DCR register DMA_WRITE_DSR_BCR UWord32 Write the parameter value into the sly channel n DMA_DSR_BCR register DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 47 Freescale Semiconductor Inc 5 1 8 Enhanced Flexible Pulse Width Modulator EFPWM Driver The enhanced flexible pulse width modulator EFPWM module contains EFPWM submodules each of which is set up to control a single half bridge power stage Fault channel support is provided PWM module can generate various switching patterns including highly sophisticated waveforms It can be used to control all known motor types and is ideal for controlling different Switched Mode Power Supplies SMPS topologies The Table 5 18 shows module identifiers for EFPWM Driver Table 5 18 Identifiers for EFPWM Driver EFPWMB 50 3 Module identifier 56 82 56F84xxx EFPWMA EFPWMA_SUBO EFPWMA_SUB1 Y EFPWMA SUB2 Y Y EFPWMA SUB3 Y Y EFPWMB Y EFPWMB SUBO Y EFPWMB SUB1 v EFPWMB_SUB2 The Table 5 19 shows commands for EFPWM Driver Table 5 19 EFPWM Driver Commands Cmd pParam Descripti
288. gister which represents the delay between the input PDB trigger and trigger A output Note The write is buffered Writing to this register writes the data into a buffer where it is held depending on the value of LDOK and LDMOD bits The bits are controlled by PDB SELECT LOAD MODE and PDB SET LDOK commands DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 132 Freescale Semiconductor Inc Table 5 54 PDB Driver Command Cmd pParam Description 56F82xxx 56F84xxx PDB_WRITE_DELAYB UWord16 Write the parameter value to the DelayB register which represents the delay between the input PDB trigger and trigger B output Note The write is buffered Writing to this register writes the data into a buffer where it is held depending on the value of LDOK and LDMOD bits The bits are controlled by PDB_SELECT_LOAD_MODE and PDB SET LDOK commands PDB WRITE DELAYC UWord16 Write the parameter value to the DelayC register which represents the delay between the input PDB trigger and trigger C output Note The write is buffered Writing to this register writes the data into a buffer where it is held depending on the value of LDOK and LDMOD bits The bits are con trolled by PDB SELECT LOAD MODE and PDB SET LDOK commands PDB WRITE DELAYD UWord16 Write the parameter value to the DelayD register which represents the delay between the input PDB trigger and trigger D output N
289. gt 5 Commander 22 L eproject EDEN Proc 56800E FSESL 121 P 5 2 apr 16 Project Creation 56800 FSLESL 122 4 F5 New MQX Lite project J Bootloader JSFamily 6 KB 1 6 Pu Import project J CodeWarrior for DS C 112 CodeWarrior for Mic gt iss Import MCU executable file GES F New MCU project items x S software fick to review and install updates Set up Reminder options Figure 1 8 Drag amp Drop CodeWarrior Project File Step 5 Clean the project right clicking on the project a choosing Clean command Step 6 Build the application code by pressing Ctrl B or choosing Project gt Build All command Check if there is zero errors after the application building Step 7 Run the application by pressing the green arrow Run or choose the Run gt Run command from the menu Select proper debug interface for SDM configuration At this point the application is running the LEDs associated to the PWM outputs are flashing and the green LED is blinking periodically The subsequent chapters describe how to create a new application how to use interrupts how to use on chip drivers and other information required to successfully create a new application DSC56800EX Quick Start User s Guide Rev 2 04 2015 1 10 Freescale Semiconductor Inc Chapter 2 Core System Infrastructure The Core System Infrastruc
290. gured For each peripheral module the page displays a status icon which informs the user about what package pins are being used by the module and how they are configured Shared Pins Status Icons No pins are configured for module use click to fix Not all required pins are configured for module use click to fix All required pins are configured for module use v Pins are not shared All pins are hardwired to the module Figure 7 3 Pinout Page Status Icons The page can also be switched to a package view where a top view of the device package is displayed Each package pin on this view is labeled by a function name assigned by pin multiplexer in a current project Clicking on the pin label activates the GPIO control page where a pin multiplexer configuration can be changed DSC56800EX Quick Start User s Guide Rev 2 04 2015 7 5 Freescale Semiconductor Inc freemaster_demo appconfig h 56 800 Graphical Configuration Tool File Edit View Module s t m Target 2748 Block view E SYS Clock 50 000 MHz LQFP64 Package view IPBus Clock 50 000 MHz m 29 43 60 groso janaocmra 713 GPIO 0 0 CMPA P2 _ Power amp Ground 30 44 61 ANAL OMPAO NO 14 1 1 CMPA 0 5 22 zoe 15 A2 2 M1 PINOUT Package Other Supply Ports 23 agu
291. h MSCAN uses an advanced buffer arrangement resulting in predictable real time behavior and simplified application software Table 5 43 and Table 5 45 show module identifiers for MSCAN Driver Table 5 43 Identifiers for MSCAN Driver Module identifier 56 82 56F84xxx MSCAN Y The Table 5 44 shows all commands dedicated for MSCAN Driver Table 5 44 MSCAN Driver Commands x Cmd pParam Description ea LL LL Lre MSCAN_ABORT_TRANSMIT combination of Cancel abort the transmission of the MSCAN_TXBUFFERxxx selected buffers The cancellation is xxx 0 1 2 successful if the message is not already in transmission or if the trans mission is not successful lost arbitra Y tion or error When a message is aborted the associated buffer is marked as empty and is reported in the abort acknowledge register MSCAN AUTO WAKEUP MSCAN ENABLE MSCAN _ Enable disable the automatic wakeup DISABLE MSCAN_CLEAR_EINT_FLAGS combination of Clear the selected error status MSCAN xxx INT change or receiver overrun interrupt 2 xxx STATCHNG OVER flags RUN MSCAN_CLEAR_ERINT_FLAGS combination of Clear the selected wake up status MSCAN xxx INT change receiver overrun receiver full 2 xxx WAKEUP STATCHNG interrupt flags OVERRUN RXFULL DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 104 Freescale Semiconductor Inc
292. he acceptance value The bits set to 1 in the mask are the don t care bits The mask and ID values for the 2x32 mask mode affect all Standard ID bits and all Extended ID bits DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 109 Table 5 44 MSCAN Driver Commands clock frequency of the MSCAN mod ule Description ag 5 re MSCAN SET ACC MASKR 32 1 UWord32 mask value includ Set 32bit acceptance mask 1 for the ing the RTR EX RTR SRR case when using 32 bit mask Y and IDE bits MSCAN SET ACC MASKR 8 0 UWord16 portion of the mask Set 8bit acceptance mask 0 for the value only lower byte case when using 8 bit mask MSCAN SET ACC MODE used with the MSCAN ACC MODE 8X8 parameter The 0 bits in the mask determine which bits are matched with v the acceptance value The bits set to 1 in the mask are the don t care bits The mask and ID values for 8x8 mask mode affect the Standard ID bits 10 3 and or Extended ID bits 28 21 MSCAN SET ACC MASKR 8 1 UWord16 portion of the mask Set 8bit acceptance mask 1 for the 2 value only lower byte case when using 8 bit mask MSCAN_SET_ACC_MASKR_8 2 UWord16 portion of the mask Set 8bit acceptance mask 2 for the 2 value only lower byte case when using 8 bit mask MSCAN SET ACC MASKR 8 3 UWord16 portion of the mask Set 8bit acceptance mas
293. hen initialized to NULL initialize stack move l gt gt _Lstack_addr r0 bftsth 0001 r0 bee lt noinc adda 1 r0 noinc tfra r0 sp move w 0 r1 nop move w rl x sp adda 1 5 2 7 2 2 8 Clearing bss bss pmem and fardata bss Segments The bss is the memory segment containing the global or static C variables to which are not assigned initial values or the initial value is 0 This segment is cleared by the startup code so the global and static C variables are initialized to 0 Note that the COP counter is periodically cleared in all loops below clear BSS segment can t use do and its 16 bit loop counter move l gt gt _Lbss_size r2 bss size tsta l r2 beq lt end_clearbss skip if size is 0 move l gt gt _Lbss_start rl dest address move w 0 x0 loop_clearbss move w R5 clear COP watchdog counter move w D1 X R5 move w 0 rl clear value at r1 dectsta r2 long loop counter bne loop clearbss clearbss The same is done with the bss segment of the fardata section addresses after 0x10000 The full name of segment is fardata bss In the startup code it is referenced as 0552 clear BSS2 segment can t use do and its 16 bit loop counter move l gt gt Lbss2 size r2 bss size tsta l r2 beq end clearbss2 skip if size is 0 move l gt gt Lbss2 start rl dest address move w 0 0 loop
294. hows all commands dedicated for Driver Table 5 3 ADC Driver Commands X X X gt lt Description 53 13 LL LL iO ADC_AUTO_POWERDOWN_MOD ADC_ON ADC_OFF Switch on off ADC Auto Power Down E saving mode in the Power Control viv Register ADC_AUTO_STANDBY_MODE ADC_ON ADC_OFF Enable disable Auto Standby Mode in 214 the Power Control Register ADC CLEAR HIGH LIMIT STATU UWord32 any combination Clear selected bits in the ADC High 512 BITS of ADC_HLSx bits 0 19 Limit Status Registers 1 and 2 ADC CLEAR HIGH LIMIT STATU UWord16 any combination Clear selected bits in the ADC High S2 BITS of ADC_HLSx bits x 16 19 Limit Status Register 2 ADC CLEAR LIMIT STATUS HLS UWord16 sample number Clear the Low Limit Status Register XM 0 15 LLSx bit Low Limit Sample x flag ADC CLEAR LIMIT STATUS LLS UWord16 sample number Clear the High Limit Status Register viv 0 15 HLSx bit High Limit Sample x flag ADC_CLEAR_LIMIT_STATUS12_H UWord16 sample number Clear all bits of the ADC high limit sta 2 15 0 19 tus register 1 and 2 ADC CLEAR LIMIT STATUS12 L UWord16 sample number Clear all bits of the ADC low limit sta 2 15 0 19 tus register 1 and 2 ADC_CLEAR_LIMIT_STATUS2_HL UWord16 sample number Clear the High Limit Status Register 2 5 16 19 HLSx bit High Limit Sample flag ADC_CLEAR_LIMIT_STATUS2_LL UWord16 sample number Clear the Low Limit Status Regist
295. ich enables up to 8 variables to be internally sampled to the on board memory The sam pling can be stopped manually or automatically based on a threshold crossing condition Sampled data buffer is downloaded to the FreeMASTER as a block and data values are displayed in the graph Disabling the recorder feature may save significant amount of code and data memory Default 0 false FMSTR MAX REC VARS integer This constant defines how many variables will it be possible to display in the FreeMASTER Recorder The default value is 8 It makes sense to set this value in the range of 2 8 Values lower than 8 may save some data RAM allocated by the driver 6bytes per variable The current version of the FreeMASTER tool does not support more than 8 variables to be displayed in graph FMSTR REC OWNBUFF numeric When defined non zero the user may must supply zero non zero his own memory to be used as a recorder buffer The recorder buffer is the memory dedicated to the recorder feature and is used to hold sampled variable values As the buffer may be up to 64kB long it may some times be desirable the user allocates the memory him self and do not let the driver to allocate it statically When undefined or set to zero the FreeMASTER driver statically allocates the recorder buffer FMSTR REC BUFF SIZE bytes Default 0 false FMSTR REC BUFF SIZE integer This constant is used when FWMSTR REC OWNBUFF UWord16 is
296. iers for OCCS Driver Module identifier 56 82 56F84xxx OCCS Y Y Table 5 48 shows all commands dedicated for OCCS Driver Table 5 48 OCCS Driver Commands Cmd pParam Description 56F82xxx 56F84xxx OCCS 200KHZ RC OSCILATOR OCCS ENABLE OCCS DIS Enable disable the power down of the OPERATION ABLE 200 kHz internal RC oscillator Note To prevent a loss of clock to the core or the PLL this bit should never be Y asserted while this clock source is selected by the PRECS field in the control register OCCS 32KHZ RC OSCILATOR OCCS ENABLE OCCS DIS Enable disable the power down of the PERATION ABLE 32 kHz internal RC oscillator Note To prevent a loss of clock to the core or the PLL this bit should never be Y asserted while this clock source is selected by the PRECS field in the control register OCCS ADJUST RELAX OSC FR UWord16 value 0 1023 Adjust the internal Relaxation Oscilla EQ tor frequency by changing the size of viv the internal capacitor The reset value is in the middle of the range DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 116 Freescale Semiconductor Inc Table 5 48 5 Driver Commands Description ag 55 Lre OCCS_CLEAR_FLAG combination of Clear the selected flags bits in the OCCS STATUS xxx PLL Status register xx
297. iew e On chip Clock Synthesis OCCS e Computer Operating Properly Watchdog COP e System Integration Module SIM SYS Interrupt controller INTC e DMA Controller DMA e Programmable Delay Block PDB only 56F84xxx devices e Quad Timer Module QT e Periodic Interrupt Timer PIT e General Purpose Input Output GPIO e nter Peripheral Crossbar Switch XBAR e AOI crosbarAND OR INVERT AOI e Pulse Width Modulation A e Pulse Width Modulation B PWMB e Analog to Digital Converter ADC e Digital to Analog Converter DAC DSC56800EX Quick Start User s Guide Rev 2 04 2015 7 1 Freescale Semiconductor Inc High Speed Comparator HSCMP e Queued Serial Communication Interface e Queued Serial Peripheral Interface QSPI Inter integrated Circuit Interface e FlexCAN Module FCAN only 56F84xxx devices e Modular Scalable Controller Area Network MSCAN only 56F82xxx devices e Cyclic Redundancy Check CRC only 56F84xxx devices e Quadrature Encoder Decoder External Watchdog Monitor EWM Flash Memory Module FTFA on 56 82 FTFL on 56 84 Flash Memory Controller FMC 7 1 2 How does it work The Graphical Configuration Tool GCT is a standard Microsoft Windows based application used to graphically edit read and write project s appconfig h file The register initialization values edited by graphical controls can be immediately displayed and or writte
298. iguration of the interrupt priority levels to the maximal extent while keeping the generated code optimal To enable the interrupt servicing and to assign a certain priority level the user defines the macro INT_PRIORITY_LEVEL_xx INTC_LEVELn To explicitly disable the interrupt the user can define the macro as INT PRIORITY LEVEL xx INTC_DISABLED DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 36 Freescale Semiconductor Inc where is the interrupt number from 1 to 110 is the interrupt level from 0 to 3 The interrupt sources configurations are then applied to a processor core by issuing the INTC_INIT ioctl command for example in the main function The C preprocessor and compiler check the validity of the selected priority level early during the compilation and issues compilation errors if invalid combination of interrupt source number and interrupt priority level is requested or if priority level is requested to be set for the source with fixed priority level 2 6 2 2 Installing Fast Interrupts As described in Section 2 6 1 5 on page 35 two interrupt sources can be selected as Fast Interrupts For the fast interrupts the interrupt controller does not fetch the jsr instruction from the vector table and directly loads the program counter PC with address specified in dedicated Fast Interrupt Vector Address FIVA registers In the 56800EX Quick Start t
299. ile the generated clock is stable e initializes the stack pointer SP to the address after any data segments clears the bss segment which holds the uninitialized global and static C variables copies the initial values from Flash memory to initialized global variables data segment The P Flash memory is used to hold the initialization data clears and initializes variables in the fardata bss and fardata data segments clears and initializes variables in the bss pmem and bss data segment program RAM based variables initializes the program RAM based code of the pramcode section When all the initialization is done the functions userPreMain main userPostMain are called 2 1 3 userPreMain The userPreMain function is called before the main application code in the main function The user can add any additional initialization code here The function is located in the appconfig c file 2 1 4 main the User s Application Code The main function is called after all the code described above is executed i e the processor is initialized and the user s pre main code is executed It is the place where the user writes the application code By default the function is located in the file but the file can be renamed by the user 2 1 5 userPostMain The userPostMain function is called after the main application code 1s finished The user can add any additional code he she wishes By default the process
300. in 5 75 5 23 EWM Driver AO 5 75 5 24 Identifiers for FCAN 5 77 5 25 FCAN Driver COMMAND Rr EO pie 5 77 5 26 FCAN driver MB specific commandS 5 82 5 27 identifiers tor TF D QN DIM LR M LM dada ga Fut 5 84 5 28 E prd qi RTT TER 5 84 5 29 5 85 5 30 5 85 5 31 ldentifiers for FMC iius rite M V XR 5 86 5 32 FMC Driver Command od ord ee enna 5 86 5 33 ldentifiers E QUEM RUM 5 87 5 34 GPIO Driver 5 87 5 35 ldentifiers Inr HSCMP DEHUBE DETE 5 91 5 36 HSCMP Driver Commands Less esesuiaxadanakueia tetas adaddduekacxietdaaitap stationed aede 5 91 5 37 ER EUR 5 94 5 38 IIC Driver Um 5 94 5 39 Identifiers for INTC 5 101 5 40 INTC Diver Command i acerbo Dodd xad sre S Map ute a Dir Ltd dr ca tab atc uod 5 101 5 41 Identifiers for MCM a d Ro ird and Dd Rd led 5 103 5 42 MGM Driver Command RETO 5 103 5 43 Identifi
301. in the FreeMASTER protocol which enables the FreeMASTER tool to obtain variable infor mation directly from the embedded application With this feature it is no more necessary for the Free MASTER tool to load and parse the application ELF file It also enables the TSA safety feature Default 0 false FMSTR USE TSA SAFETY numeric zero non zero When defined non zero and TSA is enabled this con stant activates the FreeMASTER memory protection In this mode the driver actively denies any access to memory areas which are not described by any TSA table in the application Also with this feature the variables described by a TSA entries can be declared as Read Write or Read Only for the FreeMASTER tool Default 0 false DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 6 2 FreeMASTER Communication Configuration Items for appconfig h Continued SYMBOL TYPE DESCRIPTION FMSTR_USE_TSA_INROM numeric zero non zero With this constant defined as a non zero value all TSA tables are declared as const i e they are put to const data segment This segment is typically put to Flash memory in DSP56F800EX_Quick_Start applica tions Default 0 false Memory Access FMSTR_USE_READMEM numeric zero non zero When this constant is defined as a non zero value the support for Read Memory feature is implemented It
302. includes the RTR SRR and IDE bits MSCAN_SET_ACC_IDR_16_3 UWord16 portion of the ID Set 16bit acceptance ID 3 The value 2 includes the RTR SRR and IDE bits MSCAN_SET_ACC_IDR_32_0 UWord32 ID acceptance Set 32bit acceptance ID 0 The value value includes the RTR ex RTR SRR and Y IDE bits MSCAN SET IDR 32 1 UWord32 ID acceptance Set 32bit acceptance ID 1 The value value includes the RTR ex RTR SRR and Y IDE bits MSCAN SET IDR 8 0 UWord16 portion of the ID Set 8bit acceptance ID 0 acceptance value lower byte Y only MSCAN SET IDR 8 1 UWord16 portion of the ID Set 8bit acceptance ID 1 acceptance value lower byte Y only MSCAN SET IDR 8 2 UWord16 portion of the ID Set 8bit acceptance ID 2 acceptance value lower byte Y only MSCAN SET IDR 8 3 UWord16 portion of the ID Set 8bit acceptance ID 3 acceptance value lower byte Y only DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 108 Freescale Semiconductor Inc Table 5 44 MSCAN Driver Commands Description ES 3 89 MSCAN SET IDR 8 4 UWord16 portion of the ID Set 8bit acceptance ID 4 acceptance value lower byte Y only MSCAN SET IDR 8 5 UWord16 portion of the ID Set 8bit acceptance ID 5 acceptance value lower byte Y only MSCAN SET IDR 8
303. io File Edit Search Project Run Tools Processor Window Help ri amp iZ U DR i Oae Ej Debu CodeWarrior Projects 53 1 EE Outline 18 p File Name Tx outline is not available File Name E Build Sco QU gt temp My worskpace Standalone C application Search Standalone C application Organize v 1 Ope Burn New folder 1 e d Documents Date modified Type Size F l 1 ApplicationConfig 25 4 2013 13 57 File folder 11 mvfslogs src File folder uti T P 11 SystemConfig File folder entaLogix 3 USA j 18 4 2013 12 25 25 No preview a roject 18 4 2013 12 25 PROJECT File 3KB available Comm d Program Files B sii E main 18 4 2013 12 25 C Source File 2KB 7 Projeq jam E s ReferencedRSESystems 18 4 2013 12 25 XML Document 37 KB ata Fa New E Imp temp Imp totalcmd 17 Imp 5 New project Date modified 18 4 2013 12 25 Date created 25 4 2013 13 57 d PROJECT File Size 214 KB Figure 4 3 Drag amp Drop CodeWarrior Project File NOTE It is recommended to rename the new project directory something other than default names application or Standalone C application to be able to add other new projects later to the same workspace folder This step has to be done either
304. ion 4 2 to find how to initialize on chip peripheral modules using appconfig h file and the respective ioctl xx_INIT command See Section 2 6 2 Configuring Interrupts for information on installing ISRs and defining the interrupt priorities through the appconfig h file DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 9 Freescale Semiconductor Inc Example 4 3 appconfig h from sample application BKK KK KKK KK KK KK AA I I KAA AAA IKK KKK File Name appconfig h Description file for static configuration of the application initial values interrupt vectors k k k k k k k k k k k k k k kk kkk kk kk kkk kkk ifndef APPCONFIG define KR KKK KC KK KO CCCII IGI ke kk File generated by Graphical Configuration Tool Wed 06 Mar 2013 17 23 57 ck ck ck ck ck ck ck ck ck k ck kck ck ck ck ck ck ck ck ck ck ck ck kckck ck k ck kck kck k ck ck ck ck ck ck k ck ck ck ck ck k ck k ck k ck k ck ck ck ck ck ck ck kk ck ck ck kk kk define MC56F82748 define EXTCLK 8000000L define APPCFG_DFLTS_OMITTED 1 define APPCFG_GCT_VERSION 0x02060100L Bs 5 Configuration Use Factory Trim Value Yes Enable internal
305. ion code too This file defines the macros which are used to build the TSA tables in the user code Interrupt Handling The FreeMASTER driver must be configured for one of the three modes of operation differing in the way how the peripheral interrupts are used by the driver Table 6 1 FreeMASTER Driver Interrupt Mode Mode Description Long Interrupt Mode Both the communication interface and the protocol decoder are processed in the SCI or JTAG interrupt The time spent in the interrupt routine depends on the what protocol command is being handled Such a non deterministic behavior may require the application interrupt levels to be balanced with care DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 6 1 FreeMASTER Driver Interrupt Mode Continued Mode Description Short Interrupt Mode The communication is handled in the interrupt while the protocol is decoded and handled only when the function is called The time spent in the interrupt ser vice routine is rather short as the characters are just fetched to or from the buffer One additional communication buffer receiver queue is required to store received characters before they are handled by the protocol state machine Poll driven Mode No interrupt operation Both the communication interface and the protocol are han dled only when the poll function is called Typically this function i
306. ion selection XB INZ PWMA SYS SET F7PAD FUNCTION one of SYS F7PAD xxx Package pin function selection 0 551 B XB Y 3 SYS SET F7PAD FUNCTION one of SYS F7PAD xxx Package pin function selection 2 XB 551 B SYS SET F8PAD FUNCTION one of SYS F8PAD xxx Package pin function selection 2 RXDO TB1 CMPD O SYS SET F8PAD FUNCTION one of SYS F8PAD xxx Package pin function selection OUT10 CMPDO Y PWMA 2X SYS SET F9PAD FUNCTION one of SYS F9PAD xxx Package pin function selection 2 FAULT7 XB_OUT11 SYS SET GOPAD FUNCTION one of SYS GOPAD xxx Package pin function selection 2 XB OUT6 SYS SET G10PAD FUNCTION one of SYS G10PAD xxx Package pin function selection 2 2 IN8 SYS SET G11PAD FUNCTION one of SYS G11PAD xxx Package pin function selection TB3 CLKOUTO MOSI1 SYS SET G1PAD FUNCTION one of SYS G1PAD xxx Package pin function selection 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 160 Freescale Semiconductor Inc Table 5 62 SYS Driver Commands x x Description m 518 Lre SYS SET G2PAD FUNCTION one of SYS G2PAD xxx Package pin function selection 2 XB OUTA SYS SET FUNCTION one of SYS G3PAD xxx Package pin function selection 2 XB_OUT5 SYS_SET_G4PAD_FUNCTION one of SYS_G4PAD_xxx Packa
307. iption ag 55 Lre SYS_CLKOUT_SELECT one of SYS_CLKOUT_xxx Select CLSKOUT source SYSCLK IPB viv CLK HSCLK MSTRCLK SYS DISABLE IN STOP REG2 combination of Disable modules in STOP mode 5222 SYS MOD2 SYS DMA ENABLE DMAEBL RUN MODE DMA Selelct if is enabled in RUN EBL RUN WAIT MODES D WAIT RUN and WAIT or all modes If MAEBL ALL MODES DMA the WP Write protected command is EBL DISABLE AND WP D used seting canot be changed until 21 MAEBL_RUN_MODE_AND the next reset WP DMAEBL_RUN_WAIT_ MODES_AND_WP DMAEBL ALL MODES AND WP SYS ENABLE IN STOP REG2 combination of Enable modules in STOP mode SYS xxx MOD2 SYS FAST MODE SYS ENABLE SYS DISABL Decide if the system will boot in fast E mode core bus 2 1 or normal Y mode SYS GET 12 POWER MODE NULL Return Regulator Control as UWord16 sly value SYS GET 27 POWER MODE NULL Return Regulator Control as UWord16 sly value SYS GET 27 POWERDOWN NULL Return Regulator Control as UWord16 Kw value SYS GET FAST MODE NULL Return UWord16 TRUE Fast mode 2 False Normal mode SYS_GET_LOW_POWER_MODE NULL Return non zero if device is in LPMODE mode SYS_GET_LOW_POWER_MODE NULL Return non zero if device is in VLP SYS GET POWER MODE NULL Get current power mode Returned UWord16 value can be tested for presence of the SYS_REDUCED_POWER SYS POWER MODE PERMANENT flags SYS HS CLOCK DISABLE combination of SYS HS xxx Enable high speed clock
308. is code clears the Index Pulse Interrupt Request flag in the Decoder Control Register DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 21 2 5 17 periphSafeAckByOneVar clear acknowledge bit flags which active high and are cleared by write one Call s void periphSafeAckByOneVar UWord16 GroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 19 periphSafeAckByOneVar arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphSafeAckByOneVar macro clears acknowledges bit flags which are active high and are cleared by write one in a peripheral memory location addressed by parameter pAddr The GroupMask specifies all flags which might be affected by clearing procedure The Mask value specifies flag flags to be cleared Caution TBD Example 2 34 periphSafeAckByOneVar macro usage periphSafeAckByOne 0x8000 0 0100 0 0010 0x0100 amp ArchlO Decoder0 deccr This code clears the Index Pulse Interrupt Request flag in the Decoder Control Register 2 5 18 periphSafeBitClear clear bits and keep value of bit flags which cleared by write one Call s void periphSafeBitClear UWordl6 FlagGroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 20 periphSafeBitClear arguments FlagGroupMask in Group mask of bit flags which are cleared by write one Mask in bit mask pAddr in
309. is the peripheral prefix for example QT INIT for Quad Timer EFPWM INIT for Pulse Width Modulator etc The DSC56800EX Quick Start also enables to dynamically initialize on chip peripherals The dynamic configuration is fully supported by the ioctl commands See Chapter 5 On chip Drivers where all ioctl commands are described Tip If you are editing the configuration file appconfig h manually you can copy the template of all configuration items intended for the appconfig h file from the peripheral module header file name of driver h e g intc h Interrupt Controller driver include file pwm h Pulse Width Modulation driver include file etc See Example 4 1 where this template for interrupt controller extracted from the include file intc h is shown Example 4 1 Configuration items for interrupt controller extract from the driver header file CK ck Ck ck ck Ck Sk KK KKK Ck Ck Sk ck Ck Sk KKK KK ck Ck ck KKK ck ck KKK KR KKK KKK KKK KK KKK KKK KKK ck kk kk ck kk KK KKK KKK KKK KKK Defines for appconfig h FA Kk kk Sk ke kk ko ke kk ke ke ke ke ke e ke x ke x define INT_VECTOR_ADDR_n interrupt handler for interrupt n define INT PRIORITY LEVEL n one of the DISABLED INTC LEVELO INTC LEVEL1 INTC LEVEL2 or LEVEL3 define INTC ICTL INI initial value of INTC Control Register define INTC FIM
310. ister 2 XBAR B READ CROSSBAR REG NULL Read and return the value of the X 3 Crossbar B Select Register 3 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 174 Freescale Semiconductor Inc Table 5 64 Driver Commands Description ag re XBAR_B_READ_CROSSBAR_REG NULL Read and return the value of the PM _4 Crossbar B Select Register 4 XBAR_B_READ_CROSSBAR_REG NULL Read and return the value of the sly 5 Crossbar B Select Register 5 XBAR_B_READ_CROSSBAR_REG NULL Read and return the value of the sly 6 Crossbar B Select Register 6 XBAR_B_READ_CROSSBAR_REG NULL Read and return the value of the F 27 Crossbar Select Register 7 XBAR B SET OUT AOI 1 A XBAR B INPUT xxx Set XBAR B OUTA input A XBAR B SET OUT AOI 1 A XBAR B INPUT xxx Set XBAR B OUTA input A XBAR B SET OUT AOI 1 B XBAR B INPUT xxx Set B OUTS5 input Y XBAR B SET OUT AOI 1 B XBAR B INPUT xxx Set B OUTS5 input Y XBAR B SET OUT AOI 1 C XBAR B INPUT xxx Set B OUTS6 input Y XBAR B SET OUT AOI 1 C XBAR B INPUT xxx Set B OUTS6 input A XBAR B SET OUT AOI 1 D XBAR B INPUT xxx Set B input Y XBAR B SET OUT AOI 1 D XBAR B INPUT xxx Set B input Y XBAR B SET OUT AOI 2 A XBA
311. it resolution with prescaler Positive transition of trigger_in will initiate the counter Supports two trigger_out signals Each has an independently controlled delay from sync_in Trigger outputs can be ORed together to schedule two conversions from one input trigger event Trigger outputs can be used to schedule precise edge placement for a pulsed output This feature is used to generate the control signal for the HSCMP windowing feature see description of High Speed Comparator module and output to a package pin if needed Continuous trigger or single shot mode supported Bypass mode supported Each trigger output is independently enabled The Table 5 53 shows module identifiers for PDB Driver Table 5 53 Identifiers for PDB Driver Module identifier 56F82xxx 56F84xxx PDB_O Y PDB 1 Y The Table 5 54 shows all commands dedicated for PDB Driver Table 5 54 PDB Driver Command Cmd pParam Description 56F82xxx 56F84xxx PDB CLEAR DELAY A FLAG NULL Clear the delay A flag lt PDB CLEAR DELAY B FLAG NULL Clear the delay B flag lt PDB_CLEAR_DELAY_C_FLAG NULL Clear the delay C flag Y PDB CLEAR DELAY D FLAG NULL Clear the delay D flag DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 127 Table 5 54 PDB Driver Command E D
312. iver The high speed comparator HSCMP module provides a circuit for comparing two analog input voltages The comparator circuit is designed to operate across the full range of the supply voltage known as rail to rail operation The Analog ANMUX provides a circuit for selecting an analog input signal from eight channels One signal is provided by the 6 bit digital to analog converter DAC The mux circuit is designed to operate across the full range of the supply voltage The Table 5 35 shows module identifiers for HSCMP Driver Table 5 35 Identifiers for HSCMP Driver Module identifier 56 82 56F84xxx HSCMP_A Y Y HSCMP B Y Y HSCMP C Y Y HSCMP D Y Y Table 5 36 shows all commands dedicated for HSCMP Driver Table 5 36 HSCMP Driver Commands X X X X Cmd pParam Description Xs LL LL HSCMP CLEAR INT FLAGS HSCMP FLAG RISING ED Clear the selected comparator inter GE HSCMP FLAG FALLIN rupt flag G_EDGE HSCMP_DAC Enable disable the 6 bit DAC compar HSCMP ENABLE HSCMP __ ator reference viv DISABLE HSCMP DAC OUT VOLTAGE SE UWord16 value 0 63 Set the VOSEL DAC output voltage vu LECT DACO V in 64 VOSEL 1 HSCMP HARD BLOCK HYSTERE HSCMP HYST LEVEL x Set the programmable hysteresis 21 SIS x 0 1 2 3 level HSCMP_INIT NULL Initialize the HSCMP peripheral regis ters using the appconfig
313. just receiving the CAN mes v sage DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 111 Table 5 44 MSCAN Driver Commands Description ES 3 LL LL 518 MSCAN_TEST_RXFRM NULL Return a non zero value if a CAN frame was received since the MSCAN CLEAR RXFRM ioctl com mand was called last time The y RXFRM flag can not be used to gener ate the CPU interrupt Do not confuse the RXFRM flag with the RXFULL interrupt flag MSCAN TEST SYNCH NULL Return a non zero value if the MSCAN module is synchronized to the CAN bus When synchronized it is able to Y participate in the communication pro cess MSCAN TIMESTAMP TIMER MSCAN ENABLE MSCAN Enable disable the timestamp timer y DISABLE MSCAN TINT DISABLE combination of Disable the selected transmitter buffer MSCAN xxx INT empty interrupts Y 1 2 AL L MSCAN TINT ENABLE combination of Enable the selected transmitter buffer MSCAN xxx INT empty interrupts Y 1 2 AL L MSCAN TRANSMIT combination of Submit the transmit buffer s selected MSCAN TXBUFFERxxx by the parameter value for a transmis 0 1 2 sion onto the CAN bus Once submit ted the buffers are marked as full and 2 should not be accessed by CPU Sub mitted buffer s g
314. k 3 for the 2 value only lower byte case when using 8 bit mask MSCAN SET ACC MASKR 8 4 UWord16 portion of the mask Set 8bit acceptance mask 4 for the E value only lower byte case when using 8 bit mask MSCAN SET ACC MASKR 8 5 UWord16 portion of the mask Set 8bit acceptance mask 5 for the 2 value only lower byte case when using 8 bit mask MSCAN_SET_ACC_MASKR_8 6 UWord16 portion of the mask Set 8bit acceptance mask 6 for the 2 value only lower byte case when using 8 bit mask MSCAN_SET_ACC_MASKR_8_7 UWord16 portion of the mask Set 8bit acceptance mask 7 for the 2 value only lower byte case when using 8 bit mask MSCAN_SET_ACC_MODE 5 Set the receive acceptance filter Xxx 2X32 4X16 8X8 CLOS figuration The ID acceptance filtering 2 is applied any time a new message is received MSCAN_SET_CLOCK_SOURCE MSCAN_IPBUS MSCAN_XT Select the MSCAN clock source 2 MSCAN_SET_PRESCALER UWord16 value 1 64 Set the ratio between the CANCLK signal frequency and the time quanta 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 110 Freescale Semiconductor Inc Table 5 44 MSCAN Driver Commands Cmd pParam Description 56F82xxx 56F84xxx MSCAN SET SAMPLING MSCAN 1SAMP PER BIT Select number of times the line is MSCAN 3SAMPS PER BIT sampled to get the bit value lt MSCAN_SET_SJW UWord16 value 1 4 Set the Synchronization Jump Width SJW parameter o
315. lback handlers can be detected and processed using the API calls below first check if a new command has been received nAppCmdCode FMSTR GetAppCmd when a new command arrives the nAppCmdCode contains the application command code In other case the NOCMD special value is returned if nAppCmdCode FMSTR APPCMDRESULT NOCMD nAppCmdCounter each command may have different processing and different result code The command processing is finished by calling FMSTR AppCmdAck with the result code value switch nAppCmdCode 1 FMSTR_AppCmdAck RESULT var8 break case 2 FMSTR AppCmdAck FMSTR APPCMD RESULT var8 break FMSTR default FMSTR AppCmdAck 0 break This call should be placed in the timer interrupt or anywhere where the recorder sampling should occur FMSTR_Recorder The FreeMASTER poll call must be called in the main application loop to handle the communication interface and protocol In LONG_INTR FreeMASTER interrupt mode all the processing is done during the communication interrupt routine and the FMSTR_Poll is compiled empty FMSTR Poll The FreeMASTER GPIO SCI 1 OCCS and SIM driver configuration extracted from the appconfig h file m OCCS Configuration Use Factory Trim Value Yes Enable internal 32 kHz oscillator No Power Down
316. leared by nibo QURE srwermimrminnadaasanaantenmmmnasansnadeasnnentes 2 27 2 5 29 periphBitChange change selected 2 28 2 5 26 periphBitTest test selected bits 2 28 23 27 periphMemDummyRead memory dummy 2 29 2 5 28 periphMemForcedRead memory force read Never optimized out 2 29 2 5 29 Miscellaneous arr iatis REPERI aped ap dada Era 2 29 2 5 30 MINA 2 32 2 6 2 32 2 6 1 ue NRI REM 2 32 2 6 2 pata Doc qm 2 35 2 6 3 DOREM Capit ua qua Reid CO PET KR DU 2 38 2 7 2 45 2 7 1 2 45 2 7 2 msde manip 2 46 3 Directory Structure 3 1 iso cain ce 3 1 3 2 Sample Applications 3 1 3 3 3 2 3 4 3 2 3 5 94 3 3 3 6 BI MT TT 3 3 DSC56800EX Quick Start User s Guide Rev 2 04 2015 iv Freescale Semiconductor Inc Contents Paragraph Page
317. les for which the DAC output is held unchanged after new data is pre sented to the analog DAC s inputs The number of clock cycles for which DAC output is held unchanged is equal to the value of FILT_CNT DAC_SET_SPEED DAC_LOW_SPEED DAC_HI GH_SPEED Select between speed and power while operating in normal mode Set ting this input low selects high speed mode in which the settling time of the DAC is 1 s faster response but at the expense of higher power con sumption DAC_SET_SYNC_SOURCE DAC IPBUS SOURCE DAC SYNCIN SOURCE Select the DAC trigger signal to be used to trigger an update of the buff ered data to the analog DAC output Restriction Do not set SYNC EN low when DMA EN is set high DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 41 Table 5 13 DAC Driver Commands Cmd pParam Description 56F82xxx 56F84xxx DAC_SET_WATER_MARK_LEVEL DAC_LEVEL_x x 0 2 4 6 Select DAC water mark level When the level of FIFO is less than or equal to this field a DMA request should be sent The FIFO used for DMA support generates a watermark signal depend ing on the value of WTMK_LVL which is used for asserting a DMA request DAC_WRITE_CONTROL_REG UWord16 Write the parameter value into the DAC Control Register DAC_WRITE_DATA UWord16 Write the parameter value into the DAC DATA Register This causes th
318. li Q 2 7 2 2 Startup Source Code The following subsections describe the source code of the Start assembly function asm void Start void 2 7 2 2 1 Initialize Interrupt Vectors Base Address The vector table is located at the beginning of the Program Flash at the beginning of the Program RAM The startup code always updates the Vector Table Base Address VBA to beginning of interrupt vectors section where the Quick Start vector table is located By default this table is always put to the beginning of the Program RAM anyway By defining the ARCH VECTBL ADDR macro in the appconfig h configuration file the VBA may be forced to a custom value relocate vector table properly ifdef ARCH VECTBL ADDR move l ARCH VECTBL ADDR A else move l _Linterrupt_vectors_addr A dif 56 824 MC56F825x 56 84 56 82 asrr l 8 DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 48 Freescale Semiconductor Inc else asrr l 7 A endif initialize Vector Base Address if defined INTC VERSION move w AO ArchIO Intc vba elif defined WINTC VERSION move w AO ArchIO Wintc vba else warning Vector Base Address is not initialized endif 2 7 2 2 2 Clear COP Counter and Keep Clearing Values in Registers On the newer 56F800EX based devices the COP Watchdog counter is enabled after reset so it is necessary to clear
319. low the 2 7V 2 2V VM level Once set those bits remain set until a 1 is written to those bit positions or until a reset occurs PMC GET BANDGAP TRIM NULL Return the trim value 0 15 of the bandgap reference in the regulatoras v v UWord16 PMC_GET_LOW_VOLTAGE combination of Get the low voltage sticky interrupt PMC_xxx_LEVEL flags 22 27 PMC GET NONSTICKY INT SOU combination of Get the low voltage nonsticky inter RCE PMC xxx LEVEL rupts flags 22 27 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 125 Table 5 52 PMC Driver Commands ter might clear Write 1 to Clear LVI SLV27F SLV22F flags DSC56800EX Quick Start User s Guide Rev 2 04 2015 gt lt gt lt Description ME LL LL iO iO PMC GET SMALL 27V REGULAT NULL Return the small regulator 2 7V active OR STATUS flag The small regulator supplies the power to the crystal oscillator relax ation oscillator PLL and duty cycle corrector It can be power down using the SIM s PWR SR27PDN bits PMC_INIT NULL Initialize the PMC peripheral registers using the appconfig h _INIT values PMC_INT_DISABLE combination of Disable the low high voltage interrupt PMC_xxx_LEVEL 1_27 1_22 1 27V LVI_22V PMC_INT_ENABLE combination of Enable the low high voltag
320. ly debugged peripheral drivers examples and interfaces that allow programmers to create their own C application code independent of the core architecture This environment has been developed to complement the existing development environment for Freescale 56F8xxx embedded processors It provides a software infrastructure that allows development of efficient ready to use high level software applications that are fully portable and reusable between different core architectures The maximum portability is achieved for devices with comparable on chip peripheral modules This manual contains information specific only to 5 56800 Quick Start tool as it applies to the Freescale 56F8xxx software development Therefore it is required that users of the DSC56800EX Quick Start tool should be familiar with the 56800E family in general as described in the DSP56800E and DSP56800EX 16 Bit DSP Core Reference Manual DSP56800ERM D MCS56F84XXX Reference Manual MC56F84XXXRM and the 56F82XXX Reference Manual MCS6F82XXXRM before continuing The 56F82xxx and 56F84xxx devices are supported by complete set of hardware development boards Tower modules TWRs Comprehensive information about available tools and documentation can be found on Freescale web pages freescale com Freescale DSC56800EX Quick Start tool is designed for and can be fully integrated with Freescale CodeWarrior development tools Before starting to explore the full feature set of the
321. mand is pending Callback the application registers a callback function which is automatically invoked upon reception of given command The two approaches may be mixed in the application Callback commands do not appear in the polling mechanism In previous DSP56800E Quick Start r2 1 the FreeMASTER driver was completely re written to enable better code portability and memory protection features The former Quick Start versions included similar driver named pc master which is still available for backward compatibility DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 1 Freescale Semiconductor Inc demo pmp FreeMASTER Fere ess File Edit View Scope Project Tools Help eee 41512 gp Fe e or 914 2 Fo 12 l Demo Project gt Demo Scope Demo Recorder 16 32 50000 e f 250004 gt a 8 o 4B 3B d gt 21B 2 0 203 00 203 25 203 50 203 75 204 00 204 25 204 50 204 75 Time sec Ready RS232 COM10 speed 9600 Scope Running Figure 6 1 FreeMASTER Application Window 6 2 Driver Files The driver code be found in the src support freemaster subdirectory of the main install directory The driver is highly configurable and not all of the c files are needed to be compiled in all co
322. mediately and the end of operation can be checked by testing the status word or in Buffered mode characters are copied from the internal circular buffer The syntax of read function call is as follows read peripheral module identifier mode identifier buffer pointer number of words DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 7 Freescale Semiconductor Inc Where e Peripheral_module_identifier parameter is the same as in ioctl i e the base address of the peripheral module which can be either SCI or SPI because only these two peripheral modules can transmit receive data The predefined symbolic constants SCI or SPI can be used Mode identifier parameter specifies the mode of operation which be BLOCKING BLOCKING or BUFFERED e Buffer pointer and number of words parameters specifies the buffer pointer and the number of words which will be read 4 3 3 write The write function writes a specified number of words to the SCI or SPI module from the user allocated buffer This function can operate in Blocking mode it waits for end of operation NonBlocking mode it exits from the function immediately and the end of operation can be checked by testing the status word or in Buffered mode characters are copied into the internal circular buffer The syntax of the write function call is as follows write peripheral module identifier mode identifier buffer pointer number of wo
323. meter value to the ADC Plus Side General Calibration Value 3 Y register ADC16 WRITE 4 REG UWord16 Write the parameter value to the ADC Plus Side General Calibration Value 4 v register ADC16_WRITE_CLPD_REG UWord16 Write the parameter value to the Plus Side General Calibration Value register ADC16_WRITE_CLPS_REG UWord16 Write the parameter value to the Plus Side General Calibration Value register ADC16_WRITE_CV1_REG UWord16 Write the parameter value to the Com pare Value 1 register This register is formatted in the same way as the Result Rn register in different modes of operation for both bit position defini tion and value format using unsigned or sign extended 2 s complement ADC16_WRITE_CV2_REG UWord16 Write the parameter value to the Com pare Value 2 register This register is used only when the compare function is set to one of RANGE modes The relation of CV1 and CV2 register val ues determine whether inside of range or outside of range condition is evaluated ADC16_WRITE_OFS_REG UWord16 Write the parameter value to the Off set register ADC16_WRITE_PLUS_SIDE_GAIN UWord16 Write the parameter value to the _REG Plus Side Gain register ADC16_WRITE_SC1_REG UWord16 Write the parameter value to the Sta tus and Control register 1 This tion clears the conversion complete flag ADC16_WRITE_SC2_REG UWord16 Write the parameter value to the Sta tus and Control register 2
324. miconductor Inc 6 26 6 6 2 Code Listing freemaster demo BKK KK KKK KK KK A ee AAA ko ko ke ko ke k k k kk k k k k k Freescale Semiconductor Inc c Copyright 2013 Freescale Semiconductor Inc ALL RIGHTS RESERVED ck k ck Ck ck k ck k ck k ck kk ck ck ck ck ck ck ck kc ck ck ck k ck k ck kck kck ck ck ck ck ckck ck ck ck kck k ck k ck kck ck ck ck ck ck ckck ck ck ck ck ck ck ck ck k ck kk kk FILE NAME main c DESCRIPTION Simple sample application demonstrating the functionality of FreeMASTER software driver Please s also the freemaster demo2 application which demonstrates use of advanced FreeMASTER features Target side Addressing Memory Access security etc The FreeMASTER driver and the SCI module are configured by GCT TARGET MC56F82xxx device KKK KKK KR KK A I AAR required DSP56F800EX_Quick_Start header include qs h low level driver headers for each module used include intc h Kinclude gpio h include occs h include sci h include sys h Hinclude cop h include freemaster h board specific configuration include board h Test variables will be displayed in the FreeMASTER application
325. n back to the appconfig h file The appconfig h file is included by the application source code and the register initialization values are used in the init functions to physically configure the peripheral module An initialization function exists for each module and it is typically invoked using the ioctl INIT call e g use the SCI1 INIT ioctl command to initialize the SCI module 1 appconfig h Graphical Configuration Tool Application Figure 7 1 GCT Usage The GCT is able to work as a stand alone tool however the integration with the CodeWarrior IDE 10 3 or higher version markedly increases the tool efficiency The integration steps as well as the installation are described in detail in Section 1 2 2 1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 7 2 7 2 Program usage This chapter contains a detailed description of the GCT user interface 7 2 1 GUI Description The GUI is organized as acommon MS Windows application The main window displays the following components see Figure 7 2 below Peripheral Modules Tree The peripheral modules tree enables navigation through the structure of device modules The user switches between different control pages by clicking on tree items Information Pane The upper left part of main application window displays the type of processor used processor system clock and peripheral bus clock Module Settings Pane This p
326. n your screen 3 the installation directory is different than default path it is essential to change DSC56800EX Quick Start path variable in CodeWarrior Development Studio DSC56800EX Quick Start User s Guide Rev 2 04 2015 1 4 Freescale Semiconductor Inc 1 2 2 1 Install Graphical Configuration Graphical Configuration Tool is installed together with the DSC56800EX_Quick_Start environment as part of the Typical installation Graphical configuration tool can also be installed as a selectable component within the Custom installation Graphical Configuration Tool is able to work as stand alone but integration with the CodeWarrior IDE markedly increases the efficiency of this tool The integration is based on the IDE user configurable menus and its interface for external plug ins NOTE External Tool Configurations are set only for the actual Workspace Newly created Workspace requires new configuration setting for GCT integration To integrate the Graphical Configuration Tool with CodeWarrior Workspace perform the following steps a Launch CodeWarrior IDE from the Start gt Programs gt Freescale CodeWarrior menu b Open the External Tools Configurations dialog window using Run gt External Tools gt External Tools Configurations ERU on Create manage and run configurations Run a program New launch configuration 9 Program Figure
327. nction Term register AOI READ BFCRTO012 NULL Return UWord16 value of AOI Bool XN ean Function Term register AOI READ BFCRTO013 NULL Return UWord16 value of AOI Bool ean Function Term register AOI READ BFCRT230 NULL Return UWord16 value of AOI Bool viv ean Function Term register AOI READ BFCRT231 NULL Return UWord16 value of AOI Bool 2127 ean Function Term register AOI_READ_BFCRT232 NULL Return UWord16 value of AOI Bool ean Function Term register AOI READ BFCRT233 NULL Return UWord16 value of AOI Bool 214 ean Function Term register 5 0 combination of Set all inputs at once of the Term 0 for AOI INPUT n xxx EVENTO C D xxx viv LOGO INVERT NOTIN VER LOG1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 30 Freescale Semiconductor Inc Table 5 7 AOI Driver Commands Description ag 516 re AOI SET EVENTO TERM 0 INPU AOI LOGO AOI INVERT AO Set INPUT_A of the Term 0 for 2452 NOTINVERT AOI LOG1 EVENTO AOI SET EVENTO TERM 0 INPU AOI LOGO AOI INVERT AO Set INPUT B of the Term 0 for XE T B NOTINVERT AOI LOG1 EVENTO SET EVENTO TERM 0 INPU AOI LOGO AOI INVERT AO Set INPUT C of the Term 0 for TC NOTINVERT AOI LOG1 EVENTO AOI SET EVENTO TERM 0 INPU AOI LO
328. nd return the value of the _27 Crossbar Select Register 27 READ CROSSBAR REG NULL Read and return the value of the _28 Crossbar Select Register 28 XBAR A READ CROSSBAR REG NULL Read and return the value of the _29 Crossbar Select Register 29 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 166 Freescale Semiconductor Inc Table 5 64 Driver Commands gt lt Description ag re XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 23 Crossbar A Select Register 3 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the sly _4 Crossbar A Select Register 4 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 25 Crossbar A Select Register 5 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the veu _6 Crossbar A Select Register 6 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the viv 27 Crossbar Select Register 7 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 24 32 _8 Crossbar A Select Register 8 XBAR_A_READ_CROSSBAR_REG NULL Read and return the value of the 22 7 29 Crossbar A Select Register 9 XBAR_A_SET_OUT_ADCA_TRIGG XBAR_A_INPUT_xxx Set XBAR_A_OUT12 input 2 A SET OUT ADCA TRIGG INPUT Set
329. ne Description The archEnableInt macro enables all interrupts by clearing bits I1 Bit 9 and IO Bit 8 in the Status Register SR Example 2 3 archEnablelnt macro usage archEnableInt DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 5 2 4 1 2 archEnablelntLvl123 enable interrupt levels 1 2 and 3 Call s void archEnableIntLv1123 void Arguments None Description The archEnableIntLv1123 macro enables interrupts at levels 1 2 and 3 while masking the interrupts at level 0 It is accomplished by clearing bit I1 Bit 9 and setting bit IO Bit 8 in the Status Register SR Example 2 4 archEnablelntLvl123 macro usage archEnableIntLv1123 2 4 1 3 archEnablelntLvl23 enable interrupts levels 2 and 3 Call s void archEnableIntLv123 void Arguments None Description The archEnableIntLvl23 macro enables interrupts at levels 2 and 3 while masking interrupts at levels 0 and 1 It is accomplished by setting bit I1 Bit 9 and clearing 10 Bit 8 in the Status Register SR Example 2 5 archEnablelntLvl23 macro usage archEnableIntLv123 2 4 1 4 archDisablelnt disable interrupts Call s void archDisableInt void Arguments None Description The archDisableInt macro disables all maskable interrupts by setting bits I1 and IO Bits 9 8 in the Status Register SR Example 2 6 archDisablelnt macro usage archDisableInt DSC56800EX Quick
330. nfigurations However all the files may be added to the project as there are conditional compilation statements in the code which assure only the required code gets actually compiled The driver is configured by macro constants defined in the freemaster cfg h file This file is included by all FreeMASTER driver source files and should contain configuration constants which affect how the driver is compiled With the DSP56800EX Quick Start the freemaster cfg h file is rather simple and is not to be modified The actual configuration should be done in the Quick Start s appconfig h file which is included by freemaster cfg h This scenario enables the FreeMASTER driver to be configured graphically using the Graphical Configuration Tool The FreeMASTER driver may also be used without the DSP56800EX Quick Start and thus also without the appconfig h file In this case all the configuration constants should be placed directly to the freemaster_cfg h DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 2 The following files are located in the src support freemaster directory 6 3 freemaster h The main driver header file This is the only file which needs to be included by the application code freemaster cfg h The minimal driver configuration file which further includes the appconfig h file and enables the driver to be configured in Graphical Configuration Tool freemaster cfg h template An
331. nphBitSet E dad dad ddr dd 2 19 Bern SE LO LR ER 2 20 TOT ed 2 21 periphSafeAckByOneVar nnn 2 22 periphSafeBitClear arguments 2 22 p riphSafeBitSet argUMEN S 2 23 periphSafeBitSetVar arguments 2 24 periphSafeBitSet 2 24 periphSafeBitGrpSet arguments 2 25 periphSafeBitGrpSetVar arguments 2 26 periphSafeBitGrpSet arguments 2 27 periphBitChange arguments Lusso suce e ure Run atat dae 2 28 pernphBhi Test SPITS 122i 2 28 periphMemDummyRead arguments 2 29 periphMemForcedRead arguments 2 29 Tay PE EEEE 2 30 vee pe POTE 2 30 cupo Qe dpa S P P 2 31 Ip gas nh ir NN 2 31 Targets or the MC56F82748EVM 2 45 Driver Arguments lt c jarani nannies 5 4 for ADC REEN 5 6 ve kie esti 5 6 5 23 BADUIB Dart onm DD
332. nputs at once of the Term 1 for AOI INPUT n xxx EVENTS C D xxx viv LOGO INVERT NOTIN VER LOG1 SET TERM 2 combination of Set all inputs at once of the Term 2 for AOI INPUT n xxx EVENTS C D xxx viv LOGO INVERT NOTIN VER LOG1 SET TERM 3 combination of Set all inputs at once of the Term 3 for AOI INPUT n xxx EVENTS C D xxx LOGO INVERT NOTIN VER LOG1 AOI WRITE_BFCRT010 UWord16 Write in to Boolean Function Term register AOI WRITE BFCRTO 1 1 UWord16 Write in to AOI Boolean Function se Term register AOI WRITE 012 UWord16 Write in to AOI Boolean Function Term register AOI WRITE_BFCRT013 UWord16 Write in to Boolean Function 22152 Term register AOI WRITE BFCRT230 UWord16 Write in to AOI Boolean Function sly Term register AOI_WRITE_BFCRT231 UWord16 Write in to AOI Boolean Function Term register AOI WRITE BFCRT232 UWord16 Write in to AOI Boolean Function Term register AOI WRITE BFCRT233 UWord16 Write in to AOI Boolean Function 42 42 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 34 Freescale Semiconductor Inc 5 1 4 Computer Operating Properly COP Driver The computer operating properly COP module is used to help software recover from runaway code The COP is a free running down counter that once enabled is designed to generate a reset upon reaching zero
333. ns that the tim ers counters from the same QT mod viv ule set as a master can force the state of this timer counter OFLAG output QT_FORCE_OFLAG QT_ONE QT_ZERO Set clear the OFLAG output using the software triggered FORCE command First this command writes the passed 1 bit value to the VAL bit Then it writes 1 to the FORCE bit what viv causes that the current value of the VAL bit is written to the OFLAG out put Note Use this command if timer is disabled QT_INIT NULL Initialize the QT peripheral registers using the appconfig h _INIT values DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 136 Freescale Semiconductor Inc Table 5 56 Driver Commands Description ag Lre QT_INT_DISABLE QT_xxx_INT xxx COM Disables selected interrupts PARE COMPARE1 COMPA PE RE2 OVER FLOW INPUT_EDGE QT_INT_ENABLE QT_xxx_INT xxx COM Enable selected interrupts PARE COMPARE1 COMPA 214 RE2 OVER FLOW INPUT_EDGE QT_OUTPUT_ON_EXT_PIN QT_ENABLE QT_DISABLE Enable disable the OFLAG output sig nal to be put on the external pin This command sets clears the Output viv Enable OEN bit in the timer counter Status and Control register QT_READ_CAPTURE_REG NULL Read and return the value of the timer counter Capture register as viv UWord16 QT READ CMP STATUS CONTR NULL
334. nstallation The application is also printed below on page 32 6 6 1 12 1 TSA Table Definition The TSA table describes the static or global variables together with their address size type and access protection information In case the TSA described variables are of a structure type the TSA table may also describe this type and enable FreeMASTER user to access individual structure members of the variable The TSA table definition begins with FMSTR TSA TABLE BEGIN macro FMSTR TSA TABLE BEGIN table id Where the table idis any valid C language symbol identifying the table There can be any number of TSA tables in the application provided the table identifiers remain unique After this macro the TSA table entries are placed using one of the macros below FMSTR TSA RW VAR name type read write variable entry FMSTR TSA RO VAR name type read only variable entry FMSTR TSA STRUCT struct name structure type entry FMSTR TSA MEMBER struct name member name type structure member entry The table is finished using the FMSTR TSA TABLE END macro FMSTR TSA TABLE END The TSA entry definition macros accept the following parameter 9 name Variable name The variable must be defined before the TSA table entry references it type Variable or member type Only one of the pre defined type constants may be used as described below e struct name Structure type
335. nt or copyright or misappropriates a trade secret and pay costs and damages finally awarded based upon such suit if you 1 promptly notify Freescale in writing as soon as reasonably practicable after you first become aware of the claim of infringement or misappropriation but in no event later than 15 days of the date on which you first received notice of the claim and 2 at Freescale s request and expense give Freescale sole control of the suit and all requested assistance for defense of the suit Freescale will not be liable for any settlement made without its written consent If the use or sale of any Software component program licensed under this Agreement is enjoined as a result of such suit Freescale at its option and at no expense to you will 1 obtain for you the right to use such program consistent with the license granted in this Agreement for the affected program 2 substitute an equivalent program and extend this indemnity thereto or 3 accept the return of the program and refund the portion of the license fee for such component program less reasonable charge for prior use If an infringement or misappropriation claim related to the Software is alleged prior to completion of delivery Freescale has the right to decline to make further shipments notwithstanding any other provision of this Agreement This indemnity does not extend to any suit based upon any infringement or alleged infringement arising from any program furnished by Freesc
336. o SCIO No SCI1 QSPIO No QSPI1 IICO No FLEXCAN No DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 10 A No B No C D CYC ADC No CRC QDC PITO No No DACA DACB No PWMCHO No PWMCH1 No PWMCH2 No PWMCH3 No Protection of IPS and GPSxx Registers not protected Protection of PCE SD and PCR Registers not protected Protection of GPIO Port D Registers not protected Protection of PWRMODE Registers not protected GPIO Peripheral select registers GPSn ANAO CMPA3 ANB1 CMPB_INO EXTAL TXDO TAO TAL DACA TA2 SSO_B MOSIO SCLKO MOSIO Reserved Reserved TA3 SDAO SCLO PWMA_2B PWMA_2A PWMA_3B PWMA_3A XB_IN6 CLKOUT1 SCLO SDAO TXD1 RXD1 Reserved CMPC O RXDO Internal Peripheral Select Register 0 IPSO GPIOC3 GPIOCA GPIOC6 GPIOC13 GPIOC3 GPIOC8 GPIOF8 GPIOC12 GPIOF5 Miscellaneous Register 0 SIM MISCO Disable Disable CLKINO GPIOCO 141 PITO master PIT1 slave SIM Interrupts Low voltage 2 2V Disable Low voltage 2 7V Disable High voltage 2 2V Disable High voltage 2 7V Disable Enable Voltage Reference Buffer No Bandgap trim 7 Use Factory Trim Value No UA define SIM CLKOSR INIT 0x1020U define SIM PCEO INIT 0x0006U define SIM 1 INIT
337. o void pins are already configured from the device_init this is an example of run time configuration of LEDs outputs ioctl GPIO LED R2 GPIO SETAS GPIO LED R2 LEDS GPIO SETAS GPIO LED Y2 LED 62 Puce ioctl GPIO Ll ioctl GPIO Ll D R2 GPIO SETAS OUTPUT LED R2 DS GPIO SETAS OUTPUT LED Y2 LED G2 E run time configuration of button inputs ioctl GPIO BIN 0 GPIO SETAS GPIO BIN 0 ioctl GPIO 1 GPIO SETAS GPIO BIN 1 ioctl GPIO 0 GPIO 5 5 INPUT 0 ioctl GPIO 1 GPIO SETAS INPUT BTN 1 ioctl GPIO 0 GPIO PULLUP ENABLE 0 ioctl GPIO 1 GPIO PULLUP ENABLE 1 ioctl GPIO BTN 0 GPIO INT ENABLE BTN 0 ioctl GPIO BTN 1 GPIO INT ENABLE 1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 44 Freescale Semiconductor Inc 2 7 Advanced Topics This section describes the implementation details and the system code of each project created from the 56800EX_Quick_Start tool stationery for the 56F82xxx and 56F84xxx hybrid controllers 2 7 1 Project Targets Each created project contains several targets for different hardware configurations of the microcontroller system All targets are briefly described in the following tables Table 2 35 Targets
338. o empty either if transmission is aborted or success fully completed MSCAN_WAIT_SLEEP NULL Wait until sleep mode is entered Y MSCAN WAKEUP FILTER MSCAN ENABLE MSCAN Enable disable the low pass filter on 2 DISABLE the wake up condition DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 112 Freescale Semiconductor Inc Table 5 45 Identifiers for MSCAN Driver Module identifier 56F82xxx 56F84xxx MSCAN_RB v MSCAN TB v The following ioctl commands operate on top of the receive or transmit Message Buffer structures Use the MSCAN_RB or MSCAN_TB module identifiers as the first parameter to all ioctl calls when executing any of these commands Table 5 46 MSCANMB Driver Commands Cmd pParam Description 56F82xxx 56F84xxx MSCANMB_GET_DATAPTR NULL Return the UWord16 pointer to the data part of the message currently stored in the message buffer lt MSCANMB GET ID NULL Return the CAN frame identifier of the message currently stored in the Mes sage Buffer as UWord32 The returned Message Identifier is con verted from a raw form of the MB structure so that it can be treated as a standard 32 bit number The most sig nificant bit MSB of the return value is set for the extended 29 bit identifiers The MSB is cleared for the standard 11 bit identifiers MSCANMB GET ID RAW NULL Return the four IDR registers of MB as UWord32 Th
339. oad the DELAY and MOD registers The effect of this LDOK settings also depends on the LDMOD bit controlled Y by PDB SELECT LOAD MODE PDB SET PRESCALER PDB CLOCK DIVIDER xxx Set the PDB clock prescaler Y 1 2 4 8 16 32 64 128 PDB_SET_SW_TRIGGER NULL Activate the software trigger which triggers a reset and restarts the counter The trigger mode should be first set to SW_TRIG with the 2 PDB SET INPUT TRIGGER com mand Alternatively if TriggerA or TriggerB is bypassed the SW trigger it will propagate immediately PDB SET TRIGGER A BYPASS PDB ENABLE PDB DISABL Bypass the Trigger A Output of the 2 PDB module PDB_SET_TRIGGER_A_DISABLE NULL Disable the PDB Trigger A output Y PDB SET TRIGGER A ENABLE NULL Enable the PDB Trigger A output The PDB Trigger A is generated when i PDB counter value reaches the DELAY A value DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 130 Freescale Semiconductor Inc Table 5 54 PDB Driver Command Description ag PDB_SET_TRIGGER_A_OUTSEL _ Select the triggers output xxx SEPARATED_DELAY_ mode In SEPARATED mode the A_B COMBINED_DELAY_A Trigger A is a function of DELAYA B only and Trigger B is a function of T DELAYB only In COMBINED mode the Trigger A and Trigger B outputs are a function of c
340. oder_sEncScale type needed for correct functionality of the ENC_GET_SCALED_POSITION and the ENC GET SCALED POSITION DIF FERENCE commands This com mand must be executed before using the scaling position commands The EncPulses and RevolutionScale members of the decoder sEncScale structure should be set prior to calling this command EncPulses represents the nominal number of Encoder pulses per revolution and Revolution Scale represents the number of revo lutions to be reflected by the 16 bit register full range RevolutionScale n represents a range 2 ENC DIRECTION COUNTING EN ENC REVERSE ENC NOR Reverse the interpretation of the ABLE MAL quadrature signal It changes the Y direction of count ENC GET COUNT DIRECTION F NULL Get the direction flag of the last count return 0 1 for the down up direction DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 68 Freescale Semiconductor Inc Table 5 21 ENC Driver Command Cmd pParam Description 56F82xxx 56F84xxx ENC GET FILTERED ENCSIGNA LS NULL Read and return the filtered version of HOME INDEX Bit1 PHASEB Bit2 and PHASEA Bit3 encoder signals from the Input Monitor Regis ter IMR as UWord16 or as decoder sEncSignals structure mem bers ENC GET RAW ENCSIGNALS NULL Read and return the raw version of HOME INDEX Bit1 PHASEB Bit2 and PHAS
341. ombined DELAYA and DELAYB PDB SET TRIGGER B BYPASS PDB ENABLE PDB DISABL Bypass the Trigger B Output of the 2 PDB module PDB_SET_TRIGGER_B_DISABLE NULL Disable the PDB Trigger B output Y PDB SET TRIGGER B ENABLE NULL Enable the PDB Trigger B output The PDB Trigger B is generated when PDB counter value reaches the DELAY B value PDB_SET_TRIGGER_C_BYPASS PDB_ENABLE PDB_DISABL Bypass the Trigger C Output of the 2 PDB module PDB_SET_TRIGGER_C_DISABLE NULL Disable the PDB Trigger C output Y PDB SET TRIGGER C ENABLE NULL Enable the PDB Trigger C output The PDB Trigger C is generated when 5 PDB counter value reaches the DELAY C value PDB_SET_TRIGGER_C_OUTSEL PDB_xxx Select the triggers C and D output xxx SEPARATED_DELAY_ mode In SEPARATED mode the C D COMBINED DELAY Trigger C is a function of DELAYC D only and Trigger D is a function of 2 DELAYD only In COMBINED mode the Trigger C and Trigger D outputs are a function of combined DELAYC and DELAYD PDB_SET_TRIGGER_D_BYPASS PDB_ENABLE PDB_DISABL Bypass the Trigger D Output of the PDB module PDB_SET_TRIGGER_D_DISABLE NULL Disable the PDB Trigger D output A PDB SET TRIGGER D ENABLE NULL Enable the PDB Trigger D output The PDB Trigger D is generated when 2 PDB counter value reaches the DELAY D value DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 131 Table 5 54 PDB Driver Command Cmd pParam Description
342. on 56F82xxx 56F84xxx EFPWM_CENTER_ALIGN_UPDAT pwm_sComplementaryValue Set PWM Submodule 0 1 and 2 out E VALUE REGS COMPL 012 s puts in complementary mode and set viv LDOK bit afterwards EFPWM_CENTER_ALIGN_UPDAT pwm_sComplementaryValue Set PWM Submodule 0 1 and 3 out E VALUE REGS COMPL 013 s puts in complementary mode and set viv LDOK bit afterwards DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 48 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands Description ag EFPWM CENTER ALIGN UPDAT pwm sComplementaryValue Set PWM Submodule 0 2 and 3 out E VALUE REGS COMPL 023 s puts in complementary mode and set viv LDOK bit afterwards EFPWM_CLEAR_FAULT_FLAGS EFPWM FAULT X 0 1 2 3 Clear selected fault flags viv EFPWM_CLEAR_FAULT_TEST NULL Clear simulated fault condition viv EFPWM CLEAR FAULTO FLAGS EFPWM FAULT X 0 1 2 3 Clear selected fault flags viv EFPWM CLEAR FAULTO TEST NULL Clear simulated fault condition viv EFPWM_CLEAR_FAULT1_FLAGS EFPWM FAULT X 0 1 2 3 Clear selected fault flags viv EFPWM_CLEAR_FAULT1_TEST NULL Clear simulated fault condition viv EFPWM_CLEAR_LOAD_OK EFPWM SUBMODULE O E Clear selected request FPWM SUBMODULE 1 EF siy PWM_SUBMODULE_2 EFP WM SUBM
343. onally combined with a function call Use when passing a FCAN ID EXT or variable as a parameter FCAN ID RTR flags FCAN SET RXMGMASK RAW UWord32 mask value in raw Set Global RX mask register directly Y register format FCAN SET RX14MASK UWord32 mask value Set MB14 RX mask Logic ones in the Y optionally combined with mask determines bits which are com FCAN ID EXT or pared in ID filtering process Logic FCAN ID RTR flags zeros identify don t care bits FCAN SET RX14MASK V UWord32 mask value Set MB14 RX mask implemented as optionally combined with a function call Use when passing a FCAN ID EXT or variable as a parameter FCAN ID RTR flags UWord32 mask value in raw Y DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 80 Freescale Semiconductor Inc Table 5 25 Driver Command Description ag 55 ive 10O FCAN_SET_RX15MASK UWord32 mask value Set MB15 RX mask Logic ones in the optionally combined with mask determines bits which are com FCAN ID EXT or pared in ID filtering process Logic FCAN ID RTR flags zeros identify don t care bits FCAN SET RX15MASK V UWord32 mask value Set MB15 RX mask implemented as Y optionally combined with a function call Use when passing a FCAN ID EXT or variable as a parameter FCAN ID RTR flags FCAN SET RX15MASK RAW UWord32 mask value in raw Set MB15 RX mask register dire
344. onfig c 0 1 and EMI 1 0 20002 P 0x20003 vectors c boot jump section 2 1 1 Power up Reset The 56800EX core specifies two reset vectors Hardware Reset and COP Watchdog Reset These reset vectors are located at the locations of interrupt vector table at address 0x0000 These vectors identify the address of the program code where the program control is passed to on reset In applications developed with the 56800EX Quick Start tool the default entry point is the assembly routine in the startup c file In the 56800EX Quick Start tool the vector table vectors c is always linked at address 0x0000 for processor configuration The startup code then configures the interrupt controller to use the address 0x0000 as the vector table base address 2 1 2 Start entry point The entry point of all projects developed with the 56800EX Quick Start tool is the Start assembly routine located in the startup c file in project SystemConfig directory This routine performs the following initialization the interrupt controller uses the address 0x0000 as the vector base address sets the OMR register according to the settings in global application configuration file appconfig h DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 2 Freescale Semiconductor Inc initializes the On chip Clock Synthesis OCCS module sets the PLL by values from appconfig h and waits wh
345. onfigure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 14 viv BOTH ADC_ZERO_CROSS_CH15 ADC_ZC_xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 15 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 21 Table 5 3 ADC Driver Commands Description ag 8 ADC ZERO CROSS CH2 ADC 20 xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 2 ADC ZERO CROSS CH3 20 xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 3 viv BOTH ADC ZERO CROSS CH4 ADC 20 xxx DIS Configure zero crossing detection 2 2 5 logic for sample 4 ADC_ZERO_CROSS_CH5 ADC_ZC_ xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 5 viv BOTH ADC_ZERO_CROSS_CH6 ADC_ZC_ xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 6 viv BOTH ADC_ZERO_CROSS_CH7 ADC_ZC_ xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 7 viv BOTH ADC_ZERO_CROSS_CH8 ADC_ZC_xxx xxx DIS Configure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 8 viv BOTH ADC_ZERO_CROSS_CH9 ADC_ZC_ xxx xxx DIS Config
346. ool the fast interrupts are automatically configured by the INTC INIT code if the user defines the macros INTC FIMO INIT xx or INTC_FIM1_INIT xx where xx specifies what interrupt source is to be selected as fast interrupt or 1 By default the address of interrupt service routine defined by INT_VECTOR_ADDR_ xx is then automatically loaded into the FIVA registers during the INTC_ INIT command The preprocessor also verifies the interrupt identified for a fast interrupt is configured to priority level 2 which is required for the proper operation Caution A special Fast Interrupt Return instruction must be used in order to return from the Fast Interrupt service routine If there is another vector address to be used for the fast interrupt processing instead of the default INT VECTOR ADDR the following macros be defined in appconfig h INTC_FIVAO_INIT fastintOISR or INTC 1 INIT fastintlISR where fastintOISR and fastint1I1SR are the placeholders for the fast interrupt service routine names 2 6 2 3 Enabling Interrupts In addition to the interrupt controller peripheral described above the 56800EX core has its own method how to enable and disable the interrupts of certain priority levels So regardless the interrupt setting defined by macros in appconfig h and initialization done by the INTC INIT command there is another step to do to enable interrupt servicing in the application
347. or any stop mode is entered before the calibration sequence completes ADC16 TEST CALIBRATION STA NULL Return a non zero value when the cal RT ibration sequence is in progress and Y zero when is completed ADC16 TEST CONVERSION ACT NULL Return a non zero value when a ADC IVE conversion or hardware averaging is 3 in progress and zero when a conver sion is completed or aborted ADC16 TEST CONVERSION CO NULL Return a non zero value when the MPLETE conversion complete COCO flag is set The COCO flag is cleared when the ADC Status and Control register 1 SC1A is written or when the respec tive ADC Result register Rn is read ADC16 WRITE CFG1 REG UWord16 Write the parameter value to the Con 2 figuration register 1 ADC16_WRITE_CFG2_REG UWord16 Write the parameter value to the Con 2 figuration register 2 ADC16 WRITE CLPO REG UWord16 Write the parameter value to the ADC Plus Side General Calibration Value 0 Y register ADC16 WRITE CLP1 REG UWord16 Write the parameter value to the ADC Plus Side General Calibration Value 1 v register DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 27 Table 5 5 ADC16 Driver Command Description ag LL LL re ADC16_WRITE_CLP2_REG UWord16 Write the parameter value to the ADC Plus Side General Calibration Value 2 Y register ADC16 WRITE CLP3 REG UWord16 Write the para
348. or is halted by debughit instruction here The function is located in the appconfig c file 22 Data Types The 56800EX_Quick_Start tool defines some basic data types to support code portability between different hardware architectures and tools These basic data types which are defined in the C header file types h support International Telecommunication Union ITU generic word types integer fractional and complex data types This is used throughout the interface definitions for the On Chip Drivers Note that in some development environments these data type definitions are located in the prototype h file 1 Generic word types e to represent 8 bit signed character variable value e UWord8 to represent 16 bit unsigned character variable value e Word16 to represent 16 bit signed variable value e UWord16 to represent 16 bit unsigned variable value e Word32 to represent 32 bit signed variable value DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 3 e UWord32 to represent 32 bit unsigned variable value 2 Integer types 1018 to represent 8 bit signed character variable value e 0118 to represent 8 bit unsigned character variable value Int16 to represent 16 bit signed variable value Ulnt16 to represent 16 bit unsigned variable value 101032 to represent 32 bit signed variable value e 01132 to represent 32 bit unsigned variable value 3 Fractional
349. ory location addressed by parameter pAddr Note that this macro can be used in some special purposes e g for clearing the pending flags Example 2 21 periphMemlnvBitSet macro usage periphMemInvBitSet 0x0004 amp ArchlO Sim rststs This code clears the Power On Reset flag in the RSTSTS register 2 5 5 periphBitClear clear selected bits Call s void periphBitClear UWord16 Mask 416 pAddr Arguments Table 2 7 periphBitClear arguments Mask in Bit mask pAddr in The memory address Description The periphBitClear macro clears the selected bits in a memory location addressed by parameter pAddr Example 2 22 periphBitClear macro usage periphBitClear 0xC000 amp ArchIO TimerD ch0O scr This code clears bits 15 and 14 in the timer counter DO Status and Control Register SCR DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 13 2 5 6 periphBitGrpSR set bit group to given value Call s void periphBitGrpSR UWord16 GroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 8 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpSR macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected These bits are either set if the corresponding bits in Mask valu
350. ostic tool Demonstration tool e Education tool The full description can be found in the FreeMASTER User Manual attached to the FreeMASTER tool 1 2 Quick Start This chapter provides the information required to get the 05 56800 Quick Start tool installed and running DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 1 3 1 2 1 CodeWarrior for Microcontrollers CodeWarrior Development Studio V10 3 or later is a complete Integrated Development Environment IDE that provides a highly visual and automated framework to accelerate development of the most complex embedded applications CodeWarrior for Microcontrollers integrates the development tools for the ColdFire ColdFire DSC Kinetis Qorivva PX RS08 S08 and S12Z architectures into a single product based on the Eclipse open development platform Eclipse offers an excellent framework for building software development environments and is a standard framework used by many embedded software vendors As previously mentioned DSC56800EX Quick Start tool is designed for and can be integrated with CodeWarrior for Microcontrollers development tool With CodeWarrior for Microcontrollers tool users can build applications and integrate other software included as part of DSC56800EX Quick Start release Once the software is built CodeWarrior tools allows users to download executable images into the target platform and run or debug the download
351. ote The write is buffered Writing to this register writes the data into a buffer where it is held depending on the value of LDOK and LDMOD bits The bits are con trolled by PDB SELECT LOAD MODE and PDB SET LDOK commands PDB WRITE MCTRL REG UWord16 Write to the Master Control register the parameter value Note an inap propriate write to register may cause accidental clear of Write 1 to Clear flag COF and accidental set of the LDOK bit DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 133 Table 5 54 PDB Driver Command Cmd pParam Description 56F82xxx 56F84xxx PDB_WRITE_MOD UWord16 Write the parameter value to the counter modulo register which pre sents the terminal value of the PDB counter When counter reaches the modulo value it resets to 0x0001 Note The write is buffered Writing to this register writes the data into a buffer where it is held depending on the value of LDOK and LDMOD bits The bits are controlled by PDB_SELECT_LOAD_MODE and PDB SET LDOK commands DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 134 Freescale Semiconductor Inc 5 1 25 Quad Timer QT Driver Each timer module QT contains four identical counter timer groups Each 16 bit counter timer group contains a prescaler a counter a load register a hold register a capture register two compare regi
352. ows module identifiers for FMC Driver Table 5 31 Identifiers for FMC Driver Module identifier 56F82xxx 56F84xxx FMC Y Y Table 5 32 shows all commands dedicated for Driver Table 5 32 FMC Driver Command Cmd pParam Description 56F82xxx 56F84xxx FMC_INIT NULL Initialize the FMC peripheral registers using the appconfig h _ INIT values lt lt DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 86 Freescale Semiconductor Inc 5 1 15 General Purpose Input Output GPIO Driver The general purpose input output GPIO module allows direct read or write access to pin values or the ability to assign a pin to be used as an external interrupt GPIO pins are multiplexed with other peripherals on the package The device s data sheet specifies the assigned GPIO ports and the multiplexed pin package GPIOs are placed on the device in groups of one to sixteen bits called ports and designated as A B C and so on Refer to the device s data sheet for the specific definition of each of the GPIO ports on the chip The Table 5 33 shows module identifiers for GPIO Driver Table 5 33 Identifiers for GPIO Driver Module identifier 56F82xxx 56F84xxx GPIO_A Y Y GPIO B GPIO C GPIO D GPIO E GPIO F lt lt lt lt GPIO_G lt lt lt lt lt The Table 5 34 shows commands dedica
353. p GPIO A No SIM Modules Enabled in Stop TMR A0 No TMR A1 No TMR A2 No TMR A3 No SCIO No SCIT No QSPIO No QSPI1 IICO FLEXCAN No A No B CMP C D CYC ADC No No QDC No PITO No PIT1 DACA DACB No PWMCHO No PWMCH1 No PWMCH2 No PWMCH3 No Protection of IPS and GPSxx Registers not protected Protection of PCE SD and PCR Registers not protected Protection of GPIO Port D Registers not protected Protection of PWRMODE Registers not protected GPIO Peripheral select registers GPSn ANB1 CMPB_INO EXTAL TXDO TAO TAL DACA TA2 SSO_B MOSIO SCLKO MOSIO Reserved Reserved TA3 SDAO SCLO PWMA_2B PWMA_2A PWMA_3B PWMA_3A XB_IN6 CLKOUT1 SCLO SDAO TXD1 RXD1 Reserved CMPC O RXDO Internal Peripheral Select Register 0 IPSO GPIOC3 GPIOCA GPIOC6 GPIOC13 GPIOC3 GPIOC8 GPIOF8 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 36 GPIOC12 GPIOF5 Miscellaneous Register 0 SIM MISCO Disable Disable CLKINO GPIOCO 141 PITO master PIT1 slave SIM Interrupts Low voltage 2
354. phBitGrpSet32 set bit group to given value 2 20 periphSafeAckByOne clear acknowledge bit flags which are active high and are cleared Dy p PTT t 2 21 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor iii Contents Paragraph Page Number Title Number e CN A periphSafeAckByOneVar clear acknowledge bit flags which are active high and are cleared by write OPIB i eise erii iara ndr aao t et rrr tah aea ese 2 22 2 5 18 periphSafeBitClear clear bits and keep value of bit flags which are cleared by 2 22 2 5 19 periphSafeBitSet Set bits and keep value of bit flags which are cleared by E A A T 2 23 2 5 20 periphSafeBitSetVar Set bits and keep value of bit flags which are cleared by A 2 24 2 5 21 periphSafeBitSet32 Set bits and keep value of bit flags which are cleared by fe HO 2 24 2 5 22 periphSafeBitGrpSet set bit group to given value and keep value of bit flags which are cleared by 2 2 1 1 2 25 2 5 23 periphSafeBitGrpSetVar set bit group to given value and keep value of bit flags which are cleared by 444422 2 2 26 2 5 24 periphSafeBitGrpSet32 set bit group to given value and keep value of bit flags which are c
355. ple 2 28 periphBitGrpZS macro usage periphBitGrpZS 0x007f 10 amp ArchIO Pll plldb This code sets the lower 7 bits of PLL Divide By register to the value 10 Other bits in the register are not affected 2 5 12 periphBitGrpZSVar set bit group to given value Call s void periphBitGrpZSVar UWord16 GroupMask UWordl6 Mask UWordl16 pAddr Arguments Table 2 14 periphBitSet arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphBitGrpZSVar macro sets the bit group to a given value in a memory location addressed by parameter pAddr All bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared The ZS variant uses two non interruptible instructions bfclr and bfset to accomplish the requested operation The bfcir first clears all bits in GroupMask bfset then sets the bits there Caution This macro is the optimal way how to set the specified group of bits to given value However it must be kept in mind that during the short time between these two bit operations the target memory location goes through the third state where the bit group contains zeroes Example 2 29 periphBitGrpZSVar macro usage periphBitGrpZSVar 0x007f 10 amp ArchlIO Pll plldb This code sets the lower 7 bits of
356. ple shows the Reload Interrupt Service Routine Note that the CLEAR _ RELOAD FLAG ioctl command is used to clear the Reload Interrupt Flag Bit 5 in the PWM Control Register and that this is the user s responsibility 2 6 2 Configuring Interrupts This section describes the configuration of interrupts using the 56800EX Quick Start tool Interrupt configuration consists of installing the interrupt service routine ISR at the specified interrupt vector enabling the interrupt and setting the interrupt priority level Installing ISRs DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 35 56800EX_Quick_Start tool supports static compile time installation of the ISRs dynamic installation run time is not supported In general static installation of ISRs requires less program memory and has a lower or even no time overhead The static installation of ISRs consists of writing the address of the ISR to the interrupt vector table for given interrupt source at compilation time The interrupt vector table is located in the vectors c file By default all interrupt vectors are initialized with the address of the unhandled_interrupt function in the vectors c file which contains the debughit instruction and provides an alarm to the user that this interrupt was not installed but has occurred which is very useful when debugging One exception to this is the Hardware Reset vector which
357. prior to the project import or using drag amp drop method to add the project to the workspace 5 Rename the project in CodeWarriror Project tab by right clicking the project and select Rename command 6 Ifa different directory path is used the internal variable need to be modified in CodeWarrior preferences Open project properties Project gt Properties 7 Select Resource gt Linked Reources 8 Modify the variable DSP56800_QS_SRC_260 according to the DSC56800EX_Quick_Start installation folder location and click OK DSC56800EX Quick Start User s Guide Rev 2 04 2015 4 3 Freescale Semiconductor Inc type filter text Linked Resources 56F82748_C Application Resource Linked Resources Path Variables Linked Resources Resource Filters Path variables specify locations in the file system including other path variables with the syntax S VAR Builders The locations of linked resources may be specified relative to these path variables C C Build Defined path variables for resource 56F82748 C Application C C General Run Debug Settings C Freescale DSC56800EX_Quick_Start_r2 6 src ECLIPSE HOME C Freescale CW MCU v10 3 56 82 SP 5130205 G ENV Remove PARENT LOC C cc_view rg002c_viewl MC MC406_PMSM_Sensorl 2 PROJECT LOC C temp My_worskpace C_Application gt WORKSPACE LOC C cc_view rg002c_view1 MC MC406_PMSM_Sensorl Figur
358. program changing its flow directly to an ISR Also the status register and the program counter are pushed onto the stack When the user ISR finishes it executes a Return from Interrupt RTI instruction which pops the program counter and the status register from the hardware stack It puts the User Code back into the same state as it was in before execution assuming that the User ISR saved and restored all the registers it had used DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 33 Interrupt Vector Table in Program Memory Interrupt 1 save used registers 2 user code 3 restore registers user code 4 RTI PC and SR saved Return from Interrupt PC and SR restored Figure 2 2 Interrupt Processing Flow 2 6 1 3 ISRs An ISR is a program code that is executed when an interrupt is detected An ISR is responsible for servicing the cause of the interrupt such as reading a sample from a port when it is full or transmitting a sample to a port when it is empty When an interrupt occurs all other interrupts of the same or of a lower priority are disabled from executing until the current ISR finishes executing For this reason an ISR should be as fast as possible to prevent any overflow or under run condition Inside the ISR it is necessary to save and upon servicing the interrupt to restore all used registers including registers from the register bank used by the compiler The 56800E
359. quency v ae Hz value in Hz as UWord32 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 117 Table 5 48 5 Driver Commands PLL Control register as UWord16 Description m 55 Lre OCCS_GET_ZCLOCK_SOURCE NULL Return the same values as OCCS_SET_ZCLOCK_SOURCE parameters other value means synchronizing is in progress OCCS_INIT NULL Initialize the OCCS peripheral regis ters using the appconfig h _ INIT val viv ues OCCS_INIT NULL Initialize the OCCS peripheral regis ters using the appcongig h _ INIT val viv ues OCCS_INT_DISABLE combination of Disable the selected OCCS interrupts OCCS_LOL1_INT OCCS_L 5 LOSS OF CLOCK INT OCCS INT ENABLE combination of Enable the selected OCCS interrupts LOLO INT xxx Note the PLL Interrupt 1 and PLL OCCS LOL1 INT xxx Interrupt O can be enabled in a OCCS LOSS OF CLOCK 1 selected mode only if they were dis abled before It is not possible to xxx ANY_EDGE FALLING_ change the mode of the PLL Interrupt EDGE RISING_EDGE 1 or 0 once it is enabled for example change from any edge to falling edge OCCS INTERNAL RELAX OSC O OCCS ENABLE OCCS DIS Enable disable the Relaxation Oscilla PERATION ABLE OCCS STANDBY tor Power down the relaxation oscilla 80xx only tor if the crystal oscillator is b
360. r 5 142 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor V Contents Paragraph Page Number Title Number 5 1 27 Serial Peripheral Interface 8 5 148 5 1 28 System SY S 5 152 5 1 29 Inter Peripheral Crossbar Switch Driver 5 165 Chapter 6 FreeMASTER Driver 6 1 pm 6 1 6 2 Diver FIE 6 2 6 3 6 3 6 4 New nenns E anana AEN 6 4 6 4 1 Targerside 2005 1 T 6 4 6 4 2 Application Command 6 4 6 5 a Fed D EDO e FERMO ERR EHE HQ REEL 6 4 6 6 72 6 10 6 6 1 DIVEST AP Mese 6 10 6 6 2 Code Listing TITUS CBITIQ 6 27 6 6 3 Code Listing freemaster 2 0 6 32 Chapter 7 Graphical Configuration 7 1 DEDE 7 1 FP Goo p RUN NR T RR ER 7 1 1 12 acis d Road eme 7 2 l2 Proar m 012111 oe AEE EEKE NAAA 7 3 rj 7 3 7 2 2 Application Configuration File 7 9 Chapter 8 License 8 1 Software License
361. r Full flag in the SCI Status Register Return non zero ifthe v v bit is set DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 143 Table 5 58 SCI Driver Commands Description ag Lre SCI_GET_RX_IDLE NULL Test the Receiver Idle flag in the SCI Status Register Return non zero ifthe v v bit is set SCI GET RX NOISE ERROR NULL Test the Noise Error flag in the SCI Status Register Return non zero ifthe v v bit is set SCI GET RX OVERRUN NULL Test the Receiver Overrun flag in the SCI Status Register Return non zero v v if the bit is set SCI GET RX PARITY ERROR NULL Test the Parity Error flag in the SCI Status Register Return non zero ifthe v v bit is set SCI GET STATUS NULL Return SCIO or read write status Es register according to module used SCI GET STATUS REG NULL Read and return the value of SCI Sta viv tus Register 5 GET TX BUFFER FREESPA NULL Return the free space in the transmit CE buffer during the BUFFERED opera tion SCI GET TX EMPTY NULL Test the Transmitter Empty flag in the SCI Status Register Return non zero if the bit is set SCI GET TX IDLE NULL Test the Transmitter Idle flag in the SCI Status Register Return non zero viv if the bit is set SCI INIT NULL Initialize the SCI periheral registers v using the appcongig h INIT values
362. r module use click to fix 2 Pu Not all required pins are configured for module use click to fix is V All required pins are configured for module use PWM A 3 Pu Pins are not shared All pins are hardwired to the module ADC 12 bit Cyclic T 4 ma m 7 4 7 2 1 4 Register View On any of the GCT control pages a Register View bar can be shown to display the immediate register values as they are to be written to the output file For each module all registers bound to graphical controls on the page are displayed When a module configuration is modified the affected registers values are red highlighted in the Register View There is also a possibility to modify the register values directly in the Register View window press Enter to accept a new value causing the graphical controls to be redrawn accordingly However there are often other run time bits in the control registers which are not supposed to be set during an initialization Modifying the register values without paying a high attention to each individual bit or bit field of the register may cause the module settings to be invalid even if the configuration looks good in the GCT The Register View bar can be activated or deactivated by a menu View Register Summary DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 7 6 Help
363. r portion of the target memory location the written value could be overwritten back with its previous state by the write accumulator operation of periphBitGrpSet32 Example 2 32 periphBitGrpSet macro usage periphBitGrpSet32 0x0C0000000 0 040000000 amp ArchIO cre ctrl This code sets the lower TOT bit 30 of CRC Control register Other bits in the register are not affected but see Caution above 2 5 16 periphSafeAckByOne clear acknowledge bit flags which active high and are cleared by write one Call s void periphSafeAckByOne UWord16 GroupMask 16 Mask UWordl16 pAddr Arguments Table 2 18 periphSafeAckByOne arguments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address Description The periphSafeAckByOne macro clears acknowledges bit flags which are active high and are cleared by write one in a peripheral memory location addressed by parameter pAddr The GroupMask specifies all flags which might be affected by clearing procedure The Mask value specifies flag flags to be cleared This macro uses a single instruction to execute the operation and allows only constants as GroupMask and Mask arguments If the application requires the variable as argument the periphSafeAckByOne Var macro must be used instead Example 2 33 periphSafeAckByOne macro usage periphSafeAckByOne 0 8000 0x0100 0x0010 0x0100 amp ArchlO Decoder0 deccr Th
364. ral initialization The DSC56800EX_Quick_Start provides a very effective mechanism on how to initialize statically all on chip peripherals The static configuration of on chip peripherals is provided by the application specific configuration file appconfig h in cooperation with the ioctl driver commands xx_INIT xx is the peripheral prefix used in all ioctl commands These commands are for example INIT for Quad Timer EFPWM INIT for Pulse Width Modulator etc The configuration file appconfig h is used to define the configuration items which determine the configuration of the on chip peripheral Each configuration item corresponds to one register of the respective on chip peripheral The defined configuration items are written to peripheral registers by the ioctl driver commands INIT which are called by the user somewhere in the initialization code of the application The step by step procedure to statically initialize the on chip peripheral using the DSC56800EX Quick Start is the following 1 Define configuration items register values in the configuration file appconfig h You can edit the appconfig h file manually or with the Graphical Configuration Tool GCT For more information on the GCT refer to Chapter 7 Graphical Configuration Tool and predefined names of all configuration items can be found in Chapter 5 On chip Drivers 2 Initialize the selected on chip peripheral by calling the INIT ioctl command xx
365. rces can be declared as Fast Interrupts The Fast Interrupts jump directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first IRQs used as fast interrupts MUST be set to priority level 2 Unexpected results can occur if a fast interrupt vector is set to any other priority Caution A special Fast Interrupt Return instruction frtid must be used in order to return from the Fast Interrupt service routine There are also several limitations in the way how the Fast Interrupt service routine can be coded See the 56800E and 56800EX Reference Manual for more details 2 6 1 6 Clearing Interrupt Flags Each on chip peripheral interrupt source has its own interrupt flag which must be cleared after the interrupt is serviced For each peripheral module the method of clearing the interrupt flag is different As the 56800EX_Quick_Start tool does not add any infrastructure code to the interrupt service routines it also does not clear the interrupt flag inside the ISR See Example 2 50 Example 2 50 Clearing Interrupt Flags inside ISR J E EKK K K A e A KKK He I I AAR AA A ko ko IAA K K K K k k I k k k k k k PWM A Reload Interrupt Service Routine FR A A A A A A A A A A A A A A A I I I I OK pragma interrupt void pwmAReloadISR void ISR code clear Reload interrupt flag ioctl PWM A PWM CLEAR RELOAD FLAG NULL This exam
366. rds Where e Peripheral module identifier parameter is the same as in ioctl i e the base address of the peripheral module which can be either SCI or SPI because only these two peripheral modules can transmit receive data The predefined symbolic constants SCI or SPI can be used Mode identifier parameter specifies the mode of operation which can be BLOCKING NON BLOCKING or BUFFERED e Buffer pointer and number of words parameters specifies the buffer pointer and the number of words which will be transmitted 4 4 interrupts and Interrupt Service Routines Handling interrupts using the DSC56800EX_Quick_Start is described in detail in Section 2 6 This section contains also a practical guide on how to write a user interrupt service routine 4 5 appconfig h file The appconfig h see the full listing in Example 4 3 include file is the application specific configuration file It is used to define configuration items and the addresses of the user interrupt service routines ISRs The defined configuration items are then used by the ioctl commands xx INIT to initialize statically the xx peripheral module e g OCCS INIT to initialize On chip Clock Synthesis module QT INIT to initialize quad timer counter etc The defined addresses of ISRs are used to install the ISR into the desired interrupt vector at compilation time DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 4 8 See Sect
367. red in all loops below copy variable initialization data from pFlash to destination long loop ifdef TARGET INITDATA PFLASH move l gt gt _Ldata_size r2 set data size tsta l r2 beq end prom2xram move l 4 Ldata ROM addr r3 src address xROM data start move l 4 Ldata RAM addr rl1 dest address xRAM data start loop prom2xram move w Cl X R5 clear COP watchdog counter move w D1 X R5 move w r3 x0 fetch value at address r3 move w 0 1 stash value at address rl dectsta r2 bne loop prom2xram end prom2xram Next the initialized program RAM variables those not in bss pmem section and also the program RAM based code from the Quick Start specific pramcode section is initialized using the values from the program Flash in any flash based target do copy pram variable initialization data and ram based code from pFlash storage to destination in program ram ifdef TARGET CODE PFLASH move l 4 Ldatap size r2 set data size DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 56 Freescale Semiconductor Inc n2 beq lt end_prom2pram move l gt gt _Ldatap_ROM_addr r3 src address data start move l gt gt _Ldatap_RAM_addr rl dest address pRAM data start loop prom2pram move w 1 R5 clear COP watchdog counter move w D1 X R5 move w p r3 x0 fetch val
368. register DMA READ REQUEST NULL Get the request pending REQ bit the DMA channel has a transfer remain ing Cleared when the channel is selected DMA READ TRANSACTION DON E NULL Get the DMA transfer completed DONE flag DMA SET AUTO ALIGN DMA ENABLE DMA DISAB LE Set optimized transfers based on the address and size DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 45 WORD gt lt gt lt gt lt Description 55 Lre SET DESTINATION ADDRE UWord32 destination Set the destination address used by 55 address the DMA channel to write data DMA_SET_DESTINATION_ADDRE _ xxx DIS Set the size of the destination data cir SS_MODULO ABLE 16B 32B 64B 128B 25 cular buffer used by the DMA channel 6 512 1 2 4 8 viv 16 32 64 128 25 6 DMA_SET_DESTINATION_INCRE DMA ENABLE DMA DISAB Set destination address increment 22185 after each successful transfer DMA_SET_DESTINATION_ SIZE _ Set the data size of the destination xxx BYTE WORD LONG bus cycle for the DMA channel viv WORD DMA_SET_INTERRUPT_COMPLE DMA_ENABLE DMA_DISAB_ Enable disable interrupt to be gener TED LE ated when completing a transfer orby v v an error condition DMA SET LINK CHANNEL 1 DM
369. river Table 5 61 Identifiers for SYS Driver Module identifier 56F82xxx 56F84xxx SYS SIM v Y Table 5 62 shows all commands dedicated for SYS Driver Table 5 62 SYS Driver Commands CLK 2X BUSCLK DIV4 BU SCLK MSTR OSC ROSC 8 M ROSC_ 32K X X X X Cmd pParam Description LL LL SYS_ADC_REORDERING SYS_ENABLE SYS_DISABL Enable the re ordering of scan control E bits of Cyclic ADC for test channels SYS CLEAR RESET SOURCE any of SYS xxx RESET Acknowledge reset sources and clear SW COP COP TOR COP L selected bits in the Reset Staus Reg OR EXTERN POWER ON A ister viv NY EZPORT COP_WINDO W SYS_CLKODIV_SELECT one of SYS_ xxx Select CLKOUT divide factor DIV1 DIV2 DIV4 DIV8 DIV1 viv 6 DIV32 DIV128 SYS_CLKOUT SYS ENABLE SYS DISABL Enable disable CLKOUT pin X E SYS CLKOUT 1 SYS ENABLE SYS DISABL Enable disable CLKOUT1 pin 221152 SYS CLKOUT 1 SELECT one of SYS CLKOUT 1 xxx Select CLSKOUT 1 source BUS CLK 2X BUSCLK DIV4 BU Y SCLK MSTR OSC ROSC 8 M ROSC 200K SYS CLKOUT 1 SELECT one of SYS CLKOUT 1 xxx Select CLSKOUT 1 source BUS Y DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 152 Freescale Semiconductor Inc Table 5 62 SYS Driver Commands Descr
370. rn state of selected interrupt AGS REGISTER UPDATEJ RELO flags note All parameters are not AD ERROR RELOAD COM supported in all PWM submodules PARE VALO COMPARE VA see documentation L1 COMPARE_VAL2 COMP ARE VAL3 COMPARE VAL 4 COMPARE_VAL5 CAPTU RE A1 CAPTURE AO CAPT URE B1 CAPTURE BO CAP TURE X1 CAPTURE X0 EFPWMS WAIT OPERATION EFPWM STOP EFPWM RU Set PWM operation during the wait mode EFPWMS_WRITE_FAULT_MAPPIN UWord16 Write directly in to the fault Disable G REG Mapping Register EFPWMS WRITE FAULTO MAPPI UWord16 Write directly in to the fault Disable ew NG REG Mapping Register EFPWMS WRITE FAULT1 MAPPI UWord16 Write directly in to the fault Disable sly NG_REG Mapping Register EFPWMS_WRITE_FRAC_VALUE Word16 Write fractional Value to Fractional 22142 _1 Value Register 1 EFPWMS_WRITE_FRAC_VALUE Word16 Write fractional Value to Fractional zu x REG 2 Value Register 2 EFPWMS WRITE FRAC VALUE Word16 Write fractional Value to Fractional PUE REG 3 Value Register 3 EFPWMS WRITE FRAC VALUE 16 Write fractional Value to Fractional sly REG_4 Value Register 4 EFPWMS_WRITE_FRAC_VALUE Word16 Write fractional Value to Fractional 5 Value Register 5 EFPWMS_WRITE_INIT_REG Word16 Write value to the Init Register viv EFPWMS_WRITE_OUTPUT_CONT UWord16 Writes in to Output Control Register ROL_REG EFPWMS WRITE VALUE REG 0 Word16 Write Value to Value Register 0 viv EFPWMS_WRITE_VALUE_REG_1
371. rn value of the callback function is used as the Application Command result code and is returned to FreeMASTER tool Returns Non zero value when the callback function was successfully registered Range Issues None Special Issues None Design Implementation None Example 6 11 FMSTR_RegisterAppCmdCall FMSTR RegisterAppCmdCall 10 HandlerFunction This code shows how to register a callback function for Application Command with code 10 DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 23 Freescale Semiconductor Inc 6 6 1 12 Target side Addressing When the Target side Addressing TSA is enabled in the FreeMASTER driver configuration file by setting the FMSTR USE APPCMD constant non zero the user should define so called TSA tables in his application This section describes macros which need to be used to define the TSA tables There can be any number of TSA tables spread across the application source files There should be always one TSA Table List defined which informs the FreeMASTER driver about TSA tables When there is at least one TSA table and one TSA Table List defined in the application the TSA information should automatically appear in the FreeMASTER symbols list The FreeMASTER user is then able to create FreeMASTER variables based on these symbols The TSA is supported in FreeMASTER version 1 2 37 and higher See the TSA example in the freemaster demo2 sample application in DSP56800EX Quick Start i
372. rs and the voltage reference ADC POWER UP ADC CONVERTER 0 ADC Power up the selected ADC convert sly CONVERTER_1 ers and the voltage reference ADC_READ_ALL_SAMPLES adc_tBuff pointer to results Read the first 16 sample results at a buffer time Sample results are copied to viv user allocated 16 word buffer ADC_READ_ALL_SAMPLES2 adc_tBuff pointer to results Read sample results 16 19 at a time buffer Sample results are copied to user allo v cated 4 word buffer ADC READ GAIN CONTROL 1 R NULL Read and return the value of Gain Control Register 1 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 9 Table 5 3 ADC Driver Commands parameter DSC56800EX Quick Start User s Guide Rev 2 04 2015 Description ag iO Lre ADC_READ_GAIN_CONTROL_2_R NULL Read and return the value of Gain Control Register 2 ADC READ GAIN CONTROL 3 NULL Read and return the value of Gain 2 Control Register 3 ADC_READ_HIGH_LIMIT UWord16 sample number Read and return the value of ADC 0 15 High Limit Register for sample defined v v by parameter ADC_READ_HIGH_LIMIT_STATUS NULL Read and return values of ADC High 12 Limit Status registers 1 and 2 ADC_READ_HIGH_LIMIT_STATUS NULL Read and return the value of High 2 2 Limit Status Register 2 ADC_READ_HIGH_LIMIT12
373. ry is also installed directly into the CodeWarrior development tool if the path to this tool was specified by user e tools contains the Graphical Configuration Tool its configuration files device data sheets and peripheral user manuals which can be opened directly from the GCT e user manuals contains the DSP56800EX Quick Start User s Manual and other documentation 3 2 Sample Applications Directory This directory contains simple application examples to demonstrate usage of the DSP56800EX Quick Start tool as well as the usage of device or on chip peripherals The structure of the sample applications directory is illustrated in Figure 3 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 3 1 D DSC56800EX_Quick_Start_r2 6 J sample_applications 2 MC56F8200TWR 9 O fadc_fmstr_demo 9 _ demo ffreemaster demo2 gpio_demo J iic_demo C3 mscan demo C3Ipwm demo O atimer_demo 3 JIsci demo 5 L3JIsys demo 9JIMC56F8400TWR Figure 3 2 Sample Applications Directory Structure The sample applications reside on the directory corresponding to the target hardware Freescale Tower System boards There are two Tower System boards used in examples e MC56F8200TWR based MC56F82748 device e MCS56F8400TWR based on MC56F84789 device Note the individual application directories are further structured with proj
374. s actually processed by the callback function this function returns FMSTR APPCMDRESULT NOCMD Returns The code of an Application Command which needs to be processed Range Issues None Special Issues None Design Implementation None Example 6 7 FMSTR GetAppCmd check if a new command has been received nAppCmdCode FMSTR GetAppCmd when a new command arrives the nAppCmdCode contains command code In other case the NOCMD special value is returned if nAppCmdCode FMSTR APPCMDRESULT NOCMD each command may have different processing and different result code The command processing is finished by calling FMSTR AppCmdAck with the result code value switch nAppCmdCode case 1 FMSTR AppCmdAck 0x13 break case 2 This code shows how to process the Application Commands for example in the main loop DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 19 Freescale Semiconductor Inc 6 6 1 8 FMSTR_GetAppCmdData Get Application Command data Call FMSTR APPCMD PDATA FMSTR_GetAppCmdData FMSTR_SIZE pDataLen Arguments pDataLen out pointer to a variable which receives the length of the data available in the buffer May be NULL when this information is not needed Description This function can be used to retrieve the Application Command data once the application determines the Application Command is pending see FMTR GetAppCmd function above Th
375. s called from the application main loop 6 4 New Features In addition to the communication support there are two other important new features in the FreeMASTER driver 6 4 1 Target side Addressing One of the new features in the FreeMASTER driver if comparing it with the old master driver is the Target side Addressing capability TSA With this feature the user is able to describe the variables and structure data types directly in the application source code and make this information available for the FreeMASTER tool The tool may then use this information instead of reading it from the application s ELF Dwarf executable file Once the variables are described in TSA tables in the application source code see Section 6 6 1 Driver API below the FreeMASTER driver can also use this information to protect other memory from being accessed by the PC 6 4 2 Application Command Callbacks Another new feature of the FreeMASTER driver is a capability of invoking the user defined callback functions when the Application Command is received The callback function obtains the Application Command number and data as a parameters Callback s return value is used as a Application Command result code In the old driver the Application Command status needed to be periodically tested for example in the application main loop This approach is still possible with the FreeMASTER driver 6 5 Driver Configuration This
376. scale the Freescale logo and Processor Expert are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm All other product or service names are the property of their respective owners All rights reserved 2015 Freescale Semiconductor Inc Document Number DSC56800EXQSUG Rev 2 04 2015 27 freescale Number h m MMMM Au ons Contents Page Title Number Chapter 1 Introduction 9 21 RET DOE 1 1 1 1 1 3 CodeWarrior for Microcontrollers RN T 1 4 Install DSOCSBSOURA 1 4 Build and Run Sample 1 8 Chapter 2 Core System Infrastructure Boot bre ini tux Loo EEA ROSE EE 2 1 acer HIE Od Qd 2 2 ea E EAQUE 2 2 2 3 the Users Application Code iicicseccsscsssesisecicscacsdsesivebonacaesdaananbovabavinn 2 3 USEF OSIN ica leachate acca 2 3 C 2 3 ArchlO Peripheral Register Structures 2 4 Core System s Routines 2 5 Architecture dependent routines 4 4 4
377. scale Semiconductor Inc 2 11 Description periphMemWrite macro writes a 16 bit word parameter Data to the memory addressed by parameter pAddr Example 2 19 periphMemWrite macro usage periphMemWrite 0x1234 UWordl16 0 0 60 periphMemWrite O0xABCD amp ArchlO TimerD ch0 cmpl This code writes 0x1234 to the memory location at address 0 0060 and value OxABCD into the timer counter DO Compare Register 1 2 5 3 periphBitSet set selected bits Call s void periphBitSet UWordl6 Mask UWordl6 pAddr Arguments Table 2 5 periphBitSet arguments Mask in Bit mask pAddr in The memory address Description The periphBitSet macro sets the selected bits ina memory location addressed by parameter pAddr Example 2 20 periphBitSet macro usage periphBitSet 0 000 amp ArchIO TimerD ch0O scr This code sets bits 15 and 14 in the timer counter DO Status and Control Register SCR 2 5 4 periphMemlnvBitSet invert memory content and set selected bits Call s void periphMemInvBitSet UWord16 Mask UWordl6 pAddr Arguments Table 2 6 periphMemInvBitSet arguments Mask in Bit mask DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 12 Freescale Semiconductor Inc Table 2 6 periphMemlnvBitSet arguments pAddr in The memory address Description The periphMemInvBitSet macro reads the memory content inverts its value and sets the selected bits in a mem
378. se the Graphical Configuration Tool 1 1 1 5 FreeMASTER Software The FreeMASTER application is a software tool initially created for developers of Motor Control applications but it may be extended to any other application development This tool allows remote control of an application using a user friendly graphical environment running on a PC It also provides the ability to view some real time application variables in both textual and graphical form Main features Graphical environment e Visual Basic Script or Java Script can be used for control of target board e Easy to understand navigation Connection to target board possible over a network including Internet Demo mode with password protection support e Visualization of real time data in Scope window Acquisition of fast data changes using integrated Recorder Value interpretation using custom defined text messages Built in support for standard variable types integer floating point bit fields e Several built in transformations for real type variables e Automatic variable extraction from CodeWarrior linker output files ELF Remote control of application execution The FreeMASTER tool is not required in order to use the DSC56800EX Quick Start environment i e it is optional Nevertheless FreeMASTER is a versatile tool to be used for multipurpose algorithms and applications It provides a lot of excellent features including Real Time debugging Diagn
379. section describes the FreeMASTER driver configuration constants which can be placed in the appconfig h file or freemaster cfg h file DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 4 Table 6 2 FreeMASTER Communication Configuration Items for appconfig h SYMBOL TYPE DESCRIPTION FMSTR LONG INTR FMSTR SHORT INTR FMSTR POLL DRIVEN numeric zero non zero Exactly one of the three constants must be set to a non zero value Such a macro then affects how the FreeMASTER driver uses interrupts See table Table 6 1 above FMSTR SCI BASE address In case the SCI is to be used as a communication inter numeric face this constant must be defined as a base address of SCI peripheral register space With DSP56800EX Quick Start you can find these constants the processor specific arch h file SCIO BASE 5011 BASE SCI BASE FMSTR USE JTAG numeric When defined as a non zero value the JTAG will be zero non zero used for communication instead of the SCI Default 0 false FMSTR USE JTAG TXFIX numeric zero non zero When non zero the driver implements software workaround of the JTAG TDF status bit problem See more information in the JTAG communication plug in for the FreeMASTER tool Default 0 false FMSTR JTAG BASE address numeric In case the JTAG is to be used as a communication interface this constant may be defined as
380. st the selected bits in SCI Status SCI TRANSMIT DMA REQ NULL Test the TDMA bit if the SCI is cur rently requesting a DMA data transfer v v for transmit data SCI TRANSMITTER SCI ENABLE Enable disable the SCI Transmitter Palle SCI DISABLE SCI TX EMPTY INT SCI ENABLE Enable disable Transmitter Empty aane SCI DISABLE SCI TX INT SCI ENABLE Enable disable Transmitter Idle Inter sy SCI_DISABLE SCI_WAIT NULL Put SCI receiver in sleep mode viv SCI WAKEUP NULL Wake up the SCI receiver viv SCI WAKEUP CONDITION SCI WAKE BY ADDRESS Set SCI wake up mode Bll a SCI WAKE BY IDLE SCI WRITE CANCEL NULL Clear RIEF flag clear TxCounter and disable interrupts in SCIO or SCI1 viv module used SCI WRITE CONTROL REG UWord16 Write to SCI Control Register viv DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 146 Freescale Semiconductor Inc Table 5 58 SCI Driver Commands Description ag LL LL UWord16 Write to SCI Data Register viv SCI_WRITE_DATA DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 147 5 1 27 Serial Peripheral Interface Driver The serial peripheral interface SPI module enables full duplex synchronous serial communication between the chip and peripheral devices including other chips Software can poll the SPI
381. sters two status and control registers and one control register All of the registers except the prescaler are read writable The load register provides the initialization value to the counter when the counter s terminal value has been reached The hold register captures the counter s value when other counters are being read This feature supports the reading of cascaded counters The capture register enables an external signal to take a snap shot of the counter s current value The and COMP2 registers provide the values to which the counter is compared If a match occurs the OFLAG TMR Output signal can be set cleared or toggled At match time an interrupt is generated if enabled and the new compare value is loaded into the or COMP registers from CMPLD1 and CMPLD if enabled The prescaler provides different time bases useful for clocking the counter timer The counter provides the ability to count internal or external events Within a timer module set of four timer counters the input pins are shareable The Table 5 55 shows module identifiers for QTIMER Driver Table 5 55 Identifiers for QTIMER Driver Module identifier 56 82 56 84 QTIMER_AO Y Y QTIMER A1 QTIMER A2 QTIMER Y Y Y QTIMER BO QTIMER B1 QTIMER B2 QTIMER B3 lt lt lt lt lt lt The Table 5 56 shows commands d
382. t glitch stretching Enablec v Fault Input Signal Latency owo Periodic Interrupt Timer PIT 0 Periodic Interrupt Timer 0 PIT 1 Periodic Interrupt Timer 1 GPIO General Purpose Ports 0 DISMAPO OKFFFF PWM_A_0_DISMAP1 OxFFFF PWM_A1_OCTRL 050000 Input signal sampling period 0 filter off 0 pwm clks DFF pwm clks samples required to agree 3 w samples OFF GPIO A General Purpose Port Interrupts PwM 1 DISMAPO FFFF GPIO B General Purpose Port B Faut Pin Faut2Pi Name Priority PWM_A_1_DISMAP1 OxFFFF GPIO C General Purpose I O Port C Fautt1 Faul3Pin Disabled A 2 OCTRL 050000 GPIO D General Purpose I O Port D GPIO E General Purpose Port E GPIO General Purpose I O Port F XBAR Crossbar Switch XBAR A Crossbar Switch XBAR B Crossbar Switch AOI Crosbar AND OR INVERT AOT Ev PWM A Pulse Width Modulator A PWM_A_2 DISMAPO DFFFF PwM A2 018 DFFFF PWMAZOCTRL 000000 PWM_A3DISMAPO DFFFF PwWM A 3DISMAPI JOxFFFF Submodule 0 Disable PWM Pins by Fault Submodule 1 Disable PWM Pins by Fault hosp ox Fault State 0 1 2 3 FaulState 3 PwMA Logicd PwMA Legc PwMB PwMB v PwMX lv iw Logic 0 PwMX
383. t selec Capture X Input selec Raw PWMA input Raw PWMA input input One Shot mode enable Disable Disable Disable Edge Counter Enable Disable Disable Disable Edge Compare A Value 0 Edge Compare B Value 0 Edge Compare X Value 0 Capture Edge Select Disabled Capture Al Edge Select Disabled Capture BO Edge Select Disabled Capture Bl Edge Select Disabled Capture Edge Select Disabled Capture 1 Edge Select Disabled PWMX Double Switching Enable Disable Capture 0 Disable Capture Al Disable Capture BO Disable Capture Bl Disable Capture ns Disable Capture X1 Disable Source of capture DMA DMA disabled Enable DMA Write Requests For alue Registers No Output Trigger 0 Source PWM OUT TRIGO Output Trigger 1 Source OUT TRIGI mA define PWM A 3 CTRL INIT 0x0400U define A 3 CTRL2 INIT 0x2204U define PWM A 3 INIT INIT 0x0000U define A 3 VAL1 INIT 0 0 740 define 3 VALO INIT 0 00000 define 3 VAL2 INIT 0 00000 define 3 VAL3 INIT 0 00000 define 3 VAL4 INIT 0 00000 define 3 VAL5 INIT 0x0000U define A 3 FRACVAL2 INIT 0x0000U define A 3 FRACVAL3 INIT 0x0000U define A 3 14 INIT 0x0000U define PWM A 3 FRACVAL5 INIT 0x0000U defin
384. tart stationery Target MC56F82748 device KCKCKCKCKCKCKCKCkCKCkCkCkCk kk kk kk k k kCk kCk f required DSP56F800E Quick Start header include qs h low level driver headers for each module used include sys h include intc h include gpio h include cop h few Tower Board 56F8200 specific defines three basic LEDs on a single port define GPIO LEDS GPIO E define LED G BIT 0 define LED Y BIT 1 alternate LEDs each may be on a separate port define GPIO LED R2 GPIO F define LED R2 BIT 6 define GPIO LED 2 GPIO define D Y2 BIT 7 define GPIO LED G2 GPIO define D G2 BIT 6 GPIO active low buttons jumper J5 2 3 define GPIO BTN 0 GPIO_F define BIN 0 BIT 7 jumper 94 1 2 define GPIO BTN 1 GPIO C define BTN 1 BIT 2 jumper J5 2 3 define GPIO BTN 0 GPIO define BIN 0 BIT 7 2 Lu 2 DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 42 Freescale Semiconductor Inc local prototypes void init gpio void main function void main void UWordl6 i initialise SYS module ioctl SYS SYS INIT NUI configure COP module ioctl COP COP INIT NUI LL LL configure all GPIO modules ioctl GPIO GPIO INIT AI L
385. tection of PCE SD and PCR Registers not protected Protection of GPIO Port D Registers not protected Protection of PWRMODE Registers not protected GPIO Peripheral select registers GPSn ANB1 CMPB INO EXTAL TXDO TAO 1 2 SSO_B MOSIO SCLKO MOSIO Reserved Reserved TA3 24 y GPIO Yes DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 39 Internal Peripheral Select Register 0 Miscellaneous Register 0 SIM MISCO SIM Interrupts Enable Voltage Reference Buffer No Bandgap trim 7 SDAO SCLO PWMA 2B PWMA 2A PWMA 3B PWMA 3A XB IN6 1 SCLO SDAO TXD1 RXD1 Reserved CMPC_O RXDO 50 Disable Disable CLKINO PITO master Low voltage 2 2V Disable Low voltage 2 7V Disable High voltage 2 2V Disable High voltage 2 7V Disable Use Factory Trim Value No GPIOC3 GPIOC4 GPIOC6 GPIOC13 GPIOC3 GPIOC8 GPIOF8 GPIOC12 GPIOF5 GPIOCO alt1 slave VE define SIM CLKOSR INIT 0 0200 define 51 0 00160 define SIM 1 INI 0 00020 define SIM 2 INI 0 00000 define SIM INI 0 00000 INTC Configuration ri define INIT 0x0000U define INT
386. ted for GPIO Driver Table 5 34 GPIO Driver Commands gt lt Description LL LL GPIO_CLEAR_INT_PENDING combination of BIT_x Clear the selected interrupt request 0 1 15 flags generated by the GPIO by writing ones to the Interrupt Edge Sensitive Register GPIO_CLEAR_PIN combination of BIT_x Clear the selected GPIO pins by x 0 1 15 modifying the content of the Data viv Register GPIO_CLEAR_SW_INT_PENDING combination of BIT_x Disable a software generated interrupt x 0 1 15 request by modifying the content of viv the Interrupt Assert Register GPIO_CLEAR_SW_INT_PENDING combination of BIT_x Disable a software generated interrupt 0 1 15 request by modifying the content of the Interrupt Assert Register DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 87 Table 5 34 GPIO Driver Commands Description ag 55 iO Lre GPIO_GET_INT_PENDING_FLAG combination of BIT_x Read and return the selected interrupt 0 1 15 pending flag s from the Interrupt viv Pending Register GPIO_INIT NULL Initialize the selected GPIO port registers using appconfig h INIT values GPIO_INIT_ALL NULL Initialize all available GPIO ports registers using appconfig h INIT values GPIO_INT_DETECT
387. ter connected to the system bus The programming model is accessed through a 32 bit connection with the slave peripheral bus DMA data transfers may be explicitly initiated by software or by peripheral hardware requests The Table 5 14 and Table 5 16 show module identifiers for DMA Driver Table 5 14 Identifiers for DMA Driver Module identifier 56F82xxx 56F84xxx DMA Y Y Table 5 15 shows commands dedicated for Driver Table 5 15 DMA Driver Commands x x lt x Cmd pParam Description S S3 CHO CLEAR STATE MACHI NULL Clear the state machine for DMA viv NE_CONTROL channel 0 DMA CHO SELECT SOURCE DMA REQUEST xxx Select DMA request which will be Kx 0 15 routed to the DMA channel 0 DMA_CH1_CLEAR_STATE_MACHI NULL Clear the state machine for DMA siy NE_CONTROL channel 1 DMA_CH1_SELECT_SOURCE DMA REQUEST Select DMA request which will be viv xxx 0 15 routed to the DMA channel 1 DMA_CH2_CLEAR_STATE_MACHI NULL Clear the state machine for DMA viv NE_CONTROL channel 2 DMA_CH2_SELECT_SOURCE DMA REQUEST xxx Select DMA request which will be AN 0 15 routed to the DMA channel 2 DMA_CH3_CLEAR_STATE_MACHI NULL Clear the state machine for DMA NE_CONTROL channel 3 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 43 Table 5 15 DMA Driver Comm
388. ter 6 XBAR B WRITE CROSSBAR RE UWord16 Write the Crossbar the Crossbar B 214 G 7 Select Register 7 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 177 Freescale Semiconductor Inc Chapter 6 FreeMASTER Driver 6 1 Introduction The FreeMASTER driver handles a communication between embedded application and the PC running the FreeMASTER tool A communication protocol and the FreeMASTER tool enables real time access to target resources especially C language variables and memory in general FreeMASTER protocol features Read Write Access to any memory location on the target Atomic bit manipulation on target memory bit wise write access Oscilloscope access optimized real time access to variables up to 8 variables Sample rate depends on communication speed Recorder access to fast transient recorder running on board as a part of FreeMASTER driver Sample rate is limited by microcontroller CPU speed only The length of data recorded depends on amount of available memory 64 maximum Application commands high level message delivery from PC to the application FreeMASTER driver features Full FreeMASTER protocol implementation SCI or JTAG as a native communication interface Ability to write protect memory regions or individual variables Ability to deny access to unsafe memory Two ways of how to handle Application Commands Classic the application polls the App Command status to determine any com
389. ter for sample 0 v v ADC WRITE LOW LIMIT1 UWord16 Write Low Limit Register for sample 1 v ADC WRITE LOW LIMIT10 UWord16 Write Low Limit Register for sample 10 ADC_WRITE_LOW_LIMIT11 UWord16 Write Low Limit Register for sample 11 ADC_WRITE_LOW_LIMIT12 UWord16 Write Low Limit Register for sample viv 12 ADC_WRITE_LOW_LIMIT13 UWord16 Write Low Limit Register for sample viv 13 ADC WRITE LOW LIMIT14 UWord16 Write Low Limit Register for sample ell ad 14 ADC WRITE LOW LIMIT15 UWord16 Write Low Limit Register for sample viv 15 ADC_WRITE_LOW_LIMIT16 UWord16 Write Low Limit Register for sample 2 16 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 5 3 ADC Driver Commands x Cmd pParam Description 5 5 8 8 ADC_WRITE_LOW_LIMIT17 UWord16 Write Low Limit Register for sample 2 17 ADC_WRITE_LOW_LIMIT18 UWord16 Write Low Limit Register for sample 2 18 ADC_WRITE_LOW_LIMIT19 UWord16 Low Limit Register for sample ADC WRITE LOW LIMIT2 UWord16 Write Low Limit Register for sample 2 v ADC WRITE LOW UWord16 Write Low Limit Register for sample3 v v ADC WRITE LOW 4 UWord16 Write Low Limit Register for sample 4 v ADC WRITE LOW LIMIT5 UWord16 Write Low Limit Register for sample 5 v v ADC WRITE LOW LIMIT6 UWord16 Writ
390. the FCAN INT ENABLE command FCAN LOOPBACK MODE FCAN ENABLE FCAN DIS Enable or disable test loopback mode Y ABLE FCAN TIMER SYNC MODE FCAN ENABLE FCAN DIS Enable or disable Timer Sync mode Y ABLE In this mode the free running timer is reset each time a message is received in Message Buffer 0 FCAN LISTEN ONLY MODE FCAN ENABLE FCAN DIS ABLE Enable or disable Listen Only mode acknowledge signal is generated Only messages acknowledged by other CAN nodes are received FCAN_SET_TX_FIRST_SCHEME FCAN_HIGHEST_PRIORITY FCAN_LOWEST_MB_NUM BER Set ordering mechanism for Message Y Buffer transmission Either a buffer with highest assigned priority or a buffer with the lowest number is trans FCAN INDIVIDUAL RX MASKING FCAN ENABLE FCAN DIS Enable or disable Individual RX mask Y ABLE FCAN SET CLOCK SOURCE FCAN OSCILATOR CLOCK Set Clock Source for CAN engine Y FCAN PERIPHERAL CLO CK FCAN SUPERVISOR MODE FCAN ENABLE FCAN DIS Enable or disable Supervisor Mode In Y ABLE Supervisor mode certain registers are only accessible when CPU operates in privileged mode DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 78 Freescale Semiconductor Inc Table 5 25 FCAN Driver Command Description ag 10O FCAN_WAKEUP_SO
391. the DSC56800EX_Quick_Start tool how to initialize on chip peripheral modules how to access them in run time by application code and an application configuration by an application specific configuration file appconfig h At this point it is assumed that CodeWarrior for Microcontrollers Development Tools and DSC56800EX Quick Start are successfully installed and running see Section 1 2 1 and Section 1 2 2 if you need information about installation of these tools 4 1 Creating a new project To create a new project based on the DSC56800EX Quick Start project templates stationery two options are available e Standalone C application all essential driver files are located in the project folder e C application driver files are linked to the project from DSC56800EX Quick Start depository Following steps suppose DSC56800EX Quick Start to be installed in a default installation folder cNFreescaleNDSC56800EX Quick Start X Y to link properly driver files when the new project is based on C application template Creating a new project based on QuickStart C application template 1 Launch CodeWarrior IDE from the Start gt Programs gt Freescale CodeWarrior menu and open existing or create new Workspace 2 Choose File gt Import command and select General Existing Projects into Workspace and click on Next B import Sales Select Create new projects from an archive file or directory 1 Select import source gt General
392. the MB FCANMB GET LEN NULL Get data length field of the MB Use Y after a frame is received FCANMB GET ID RAW NULL Get raw 32bit ID register value Use FCANMB_GET_ID command when numerical value is required instead of a raw register value FCANMB_GET_TIMESTAMP NULL Get MB Time Stamp value The time stamp is value of the Free Running Timer captured at the moment of frame reception or transmission DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 82 Freescale Semiconductor Inc Table 5 26 FCAN driver MB specific commands Cmd pParam Description 56F82xxx FCANMB_SET_TX_PRIORITY UWord16 value 0 7 Set MB transmission priority Only applicable when local priority is enabled with FCAN LOCAL PRIORITY command lt 56F84xxx 5 xxx RXVOID RXEMPTY RX FULL TXABORT TXVOID TX ONCE TXRTR TXRAL WAYS Set code field of the MB This com mand controls the reception or trans mission of the MB FCANMB_GET_CODE NULL Get code field of the MB to determine its operation status Compare the value with one of constants FCANMB_REORDER_BYTES NULL Swap bytes in both 32bit data words of the MB This switches data from CPU ordered to bus ordered format and vice versa FCANMB_REORDER_WORDS NULL Swap 16bit words in both 32bit data words of the MB
393. the callback functions are to be registered If this constant is not defined or is zero the support for Application Command callbacks is not compiled in Default 0 Oscilloscope FMSTR USE SCOPE numeric zero non zero When defined non zero this constant enables a sup port for the FreeMASTER Oscilloscope Oscilloscope enables a faster simultaneous access to up to 8 vari ables and is used when the variables are to be dis played in the real time graph If this feature is not enabled the FreeMASTER uses standard memory access commands to access vari ables in graph sequentially Default 0 false FMSTR MAX SCOPE VARS integer This constant defines how many variables will it be possible to display in the FreeMASTER Oscilloscope The default value is 8 It makes sense to set this value in the range of 2 8 Values lower than 8 may save some data RAM allocated by the driver 6bytes per variable The current version of the FreeMASTER tool does not support more than 8 variables to be displayed in graph Recorder DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 6 2 FreeMASTER Communication Configuration Items for appconfig h Continued SYMBOL TYPE DESCRIPTION FMSTR USE RECORDER numeric When defined non zero this constant enables a sup zero non zero port for the FreeMASTER Recorder Recorder is an advanced feature wh
394. the interrupt service routine would write the other portion of the target memory location the written value could be overwritten back with its previous state by the write accumulator operation of periphBitGrpSet Example 2 37 periphSafeBitSetVar macro usage periphSafeBitSetVar 0x0002 0 0004 0 0010 amp ArchIO HscmpA scr This code enables the rising edge HSCMP A module The rising edge and falling edge interrupt flags are not cleared 2 5 24 periphSafeBitSet32 Set bits and keep value of bit flags which are cleared by write one Call s void periphSafeBitSet UWord32 FlagGroupMask UWord32 Mask UWordl16 pAddr Arguments Table 2 23 periphSafeBitSet arguments FlagGroupMask in Group mask of bit flags which are cleared by write one Mask in bit mask DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 24 Freescale Semiconductor Inc Table 2 23 periphSafeBitSet arguments pAddr in The memory address Description The periphSafeBitSet32 macro sets the selected bits and keeps value of the bit flags which are cleared by write one in a peripheral memory location addressed by parameter pAddr The FlagGroupMask specifies all flags which are cleared by write one The Mask value specifies bit bits to be set Caution It might seem this macro is the proper way how to set the group of bits to certain value as there are no intermediate invalid values written in the target memory loc
395. ther application global declarations or macros The GCT parses and re generates the register values part of the file while the other parts are ignored and left untouched In the Quick_Start projects the application configuration file is named appconfig h and resides in the ApplicationConfig project folder subdirectory This file is included by all Quick_Start low level driver source files where a configuration information is required However the GCT can be used independently on the Quick_Start and its low level drivers The GCT is capable of loading and saving the configuration file under any name The configuration file can be logically divided into four parts e Heading is an arbitrary text before the first define statement Typically the heading contains the application or user specific file header or commentary This part is not modified by the GCT The first define is typically a macro used to protect the file from multiple inclusion during compilation i e standard ifndef define sequence General GCT Constants in which the processor type and external crystal clock frequency are specified as macros Module Configuration Sections a block of configuration macro constants generated for each peripheral module This part of the file is terminated with special comment end of auto generated code File Tail is anything what follows the configuration sections The GCT keeps this section unchanged so the
396. this counter periodically during any lengthy operation in the startup code Early in the startup the COP counter 15 initially cleared and the clearing values are preserved in registers The R5 and D1 registers are not changed anywhere in the rest of the startup code and are used to clear the COP without loading the constant values again clear COP watchdog counter keep clearing values in registers C1 D1 R5 moveu w ArchIO Cop copctr R5 move w 0 5555 1 move w OxAAAA D1 move w 1 R5 move w D1 X R5 2 7 2 2 8 Setup the Operation Mode Register OMR The bits in the OMR INIT value are set in the Operating Mode Register setup the OMR bfset OMR INIT omr nop nop 2 7 2 2 4 Other Initialization The MOI register is initialized to 1 to activate linear addressing mode with RO and registers setup the m01 register for linear addressing move w 1 0 moveu w 0 01 The values the Hardware Stack cleared proper debugger behavior clear read out the hardware stack moveu w hws la moveu w hws la nop nop 2 7 2 2 5 Core Clock Setup OCCS The PLL Oscillator Control Register and the Divide By Register are initialized with the appconfig h values if defined The value in the Divide By Register controls the prescaler and postscaler frequency divisors and also multiplication factor of the PLL Note that before the PLLCR register is written the PLL DSC
397. to low at selected sly LTS fault inputs EFPWM_SET_ACTIVE_LOW_FAU EFPWM FAULT X 0 1 2 3 Set active fault level to low at selected TN LTSO fault inputs EFPWM SET ACTIVE LOW FAU EFPWM FAULT 0 1 2 3 Set active fault level to low at selected e LTS1 fault inputs EFPWM SET AUTOMATIC FAUL EFPWM FAULT 0 1 2 3 Set automatic fault clearing siy T_CLEAR EFPWM_SET_AUTOMATIC_FAUL EFPWM_FAULT_X 0 1 2 3 Set automatic fault clearing viv TO_CLEAR EFPWM SET AUTOMATIC FAUL EFPWM FAULT 0 1 2 3 Set automatic fault clearing 2152 T1_CLEAR EFPWM SET CURRENT POLARI EFPWM_SUBMODULE_O E Set PWM23 output as PWM source in TY_TO_PWM23 FPWM_SUBMODULE_1 EF complementary mode PWM SUBMODULE 2 EFP WM SUBMODULE 3 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 51 Table 5 19 EFPWM Driver Commands MODE Description ag 5 ive EFPWM SET CURRENT POLARI EFPWM_SUBMODULE_O E Set PWM45 output as PWM source in TY_TO_PWM45 FPWM_SUBMODULE_1 EF complementary mode EXE PWM SUBMODULE 2 EFP WM SUBMODULE 3 EFPWM SET FAULT FULL CYCL EFPWM FAULT 0 1 2 3 Set re enabling PWM outputs at start E E of a full cycle EFPWM SET FAULT HALF FULL EFPWM FAULT 0 1 2 3 Set re enabling PWM outputs at start Jae CYCLE of a half or full cycle EFPWM SET FAULT NORMAL M EFPWM
398. trol Palle Register 1 WRITE CONTROL2 REG UWord16 value 0 255 Write to the IIC Bus Control Register gt 2 WRITE DATA UWord16 value 0 255 Write the value to the Bus Data Register Typically writing the data PAN register is done in the interrupt ser vice routine WRITE FREQ DIV REG UWord16 value 0 255 Write to the IIC Bus Frequency PM Divider Register WRITE GLITCH FILTER REG UWord16 Write to the IIC bus Programmable V Input Glitch Filter register WRITE RANGE ADDRESS UWord16 Write to the IIC Bus Range Address Register WRITE SCL LOW TIMEOUT UWord16 Set the SCL low timeout This com mand writes directly into the SSLT 21 12 bit fields in the IIC_SLTH register and in the IIC_SLTL register IIC_WRITE_SCL_LOW_TIMEOUT_ UWord16 value 0 255 Write to the IIC Bus SCL Low Timeout 21 HIGH_REG MSByte of Register IIC_WRITE_SCL_LOW_TIMEOUT_ UWord16 value 0 255 Write to the IIC Bus SCL Low Timeout LOW REG LSByte of Register DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 99 Table 5 38 IIC Driver Commands Cmd pParam Description 56F82xxx 56F84xxx IIC_WRITE_SMBUS_REG UWord16 value 0 255 Write to the SMBus Control and Status register Note an inappro priate write to register can clear Write 1 to Clear SLTF SHTF2 flags lt lt DSC56800EX Quick Start User s Guide Rev 2 04
399. ts at PWM LE EFPWMS PWMB FAULTO ENABL EFPWM FAULT 011 213 Enable selected faults at PWM B E EFPWMS PWMB FAULT1 DISAB EFPWM FAULT 0 11213 Disable selected faults at PWM B LE EFPWMS PWMB FAULT1 ENABL EFPWM FAULT 0 11213 Enable selected faults at PWM B E EFPWMS PWMX FAULT DISABL EFPWM FAULT 0 112 3 Disable selected faults at PWM X E EFPWMS PWMX FAULT ENABLE EFPWM FAULT 0 11213 Enable selected faults at PWM Xpin v v EFPWMS PWMX FAULTO DISAB EFPWM FAULT X 0 1 2 3 Disable selected faults at PWM X LE EFPWMS PWMX FAULTO ENABL EFPWM FAULT X 0 1 2 3 Enable selected faults at PWM X pin E EFPWMS PWMX FAULT1 DISAB EFPWM FAULT 0 1 2 3 Disable selected faults at PWM X pin LE EFPWMS PWMX FAULT1 ENABL EFPWM FAULT X 0 1 2 3 Enable selected faults at PWM X pin E EFPWMS READ CAPTURE FI NULL Return value of FIFO counter 22127 FO COUNT DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 60 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands Description ag EFPWMS READ CAPTURE A1 FI NULL Return value of FIFO counter 24152 EFPWMS_READ_CAPTURE_BO_FI NULL Return value of FIFO counter EXE FO COUNT EFPWMS
400. ts channel gain for ANA4 input ADC SET 5 GAIN ADC GAIN x 1 2 4 Selects channel gain for ANAS input viv ADC SET 6 GAIN GAIN x 1 2 4 Selects channel for ANA6 input viv ADC_SET_ANA7_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANA7 input viv ADC SET ANA9 GAIN ADC GAIN x 1 2 4 Selects channel gain for ANA9 input Y ADC SET ANBO GAIN ADC GAIN x 1 2 4 Selects channel gain for ANBO input viv ADC_SET_ANB1_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANB1 input viv ADC_SET_ANB10_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANB10 input ADC_SET_ANB18_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANB18 input DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc Table 5 3 ADC Driver Commands x x x x Cmd pParam Description ag SET ANB19 GAIN ADC GAIN x 1 2 4 Selects channel gain for ANB19 input ADC SET ANB2 GAIN ADC GAIN x 1 2 4 Selects channel gain for ANB2 input viv ADC SET GAIN ADC GAIN x 1 2 4 Selects channel gain for ANB3 input viv ADC_SET_ANB4_ GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANB4 input viv ADC_SET_ANB5_GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for 5 input viv SET 6 GAIN ADC_GAIN_x x 1 2 4 Selects channel gain for ANB6 input viv AD
401. tup code The application configuration header file appconfig h is also included so the startup code is able to configure system modules like OCCS PLL and GPIO include qs h 2 7 2 1 2 Initial Value of Operation Mode Register OMR Although it is not very common the initial value of the Operation Mode Register OMR can be specified in appconfig h using the OMR_ INIT macro The following startup c statements define the default initial OMR value for the cases when the user had not defined the OMR_ INIT in appconfig h ifndef TARGET_OMR_INIT define TARGET INIT 0 endif ifndef OMR_INIT define OMR_INI O TARGET_OMR_INIT endif The default initialization value of the OMR is based on the TARGET OMR INIT value which might be defined in the prefix file LCF within the active compilation target Currently the TARGET OMR INIT is not defined in the prefix file of any target leaving the initial OMR value on 0x0000 DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 46 Freescale Semiconductor Inc The following bits are important for the proper operation of the application CM 0 optional for C application XP 0 enabling separate program and data buses Harvard Architecture 0 rounding off required for C applications SA 0 saturation off required for C applications EX 0 complete X memory space as external required by CodeWarrior debugger Th
402. ture is one of the three main blocks that compose the 56800EX_Quick_Start tool see Section 1 1 1 where the partitioning is described Its purpose is to provide the fundamental infrastructure for the 56800 device operation e g sets the operation mode the interrupt handling the initialization of the global variables CodeWarrior Compiler options It also provides some additional support commonly used macros data types and enables further integration with On chip Drivers 2 1 Boot Sequence The Core System Infrastructure provides the fundamental code which is executed before the user s main function This code provides basic settings needed to initialize the chip settings required by the CodeWarrior Compiler initialization of global variables Finally it passes control to the user s application code the main function NOTE This chapter describes the boot process of the 56F82xxx and 56F84xxx family of microcontrollers For the 56F82xxx and 56F84xxx devices the post reset execution flow may be briefly described as follows also see Figure 2 1 1 After processor reset the execution starts at the Hardware Reset vector in program memory where the 56800EX_Quick_Start tool places its jump to the Start assembly routine The reset vector is located at address 0x0000 and the jump is supplied directly from the first entry of vector table located in the interrupt_vectors section in vectors c file 2 Ifthe chip reset is generated
403. types e Fracl6 to represent 16 bit signed variable value e Frac32 to represent 32 bit signed variable value e CFracl6 to represent 16 bit complex numbers e CFrac32 to represent 32 bit complex numbers 4 Miscellaneous types e bool to represent boolean variable true false 5 Constants rue represents true value false represents false value NULL represents null pointer e PASS represents pass as function result e FAIL represents fail as function result MAX 32 maximum 32 bit signed Word32 value e MIN 32 minimum 32 bit signed Word32 value e MAX 16 maximum 16 bit signed Wordl6 value e MIN 16 minimum 16 bit signed Word16 value 2 3 ArchlO Peripheral Register Structures The global symbol Arch O provides a C interface structure type to all peripheral and core registers mapped in data memory registers are accessed via this structure so there is no need to know and specify the concrete addresses of the registers to write or read This mechanism increases code readability and portability and simplifies access to registers The Arch O is declared in the C header file arch h The ArchIO is of type arch_sIO which is the structure type composed from another structures one for each peripheral module There are two possible approaches how to define and use the ArchIO structure e define ArchIO as the direct numeric address of memory mapped peripheral registers casted to the proper struct
404. ue 0 255 Write the Service register The EWM service mechanism requires the CPU to write two values to the SERV regis v v ter a first data byte of 0xB4 followed by a second data byte of 0x2C DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 76 Freescale Semiconductor Inc 5 1 11 FlexCAN FCAN Driver This driver has only 56F84xxx devices The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2 0B protocol specification A general block diagram is shown in the following figure which describes the main sub blocks implemented in the FlexCAN module including one associated memory for storing Message Buffers Rx Global Mask Registers Rx Individual Mask Registers Rx FIFO and Rx FIFO ID Filters The functions of the sub modules are described in subsequent sections Table 5 24 shows module identifiers for FCAN Driver Table 5 24 Identifiers for FCAN Driver Module identifier 56 82 56F84xxx FCAN Y Table 5 25 shows commands dedicated for FCAN Driver Table 5 25 FCAN Driver Command Description S ME LL LL FCAN INIT NULL Initialize FlexCAN peripheral registers Y using the appconfig h INIT values FCAN MODULE FCAN ENABLE FCAN DIS Enable or disable the FlexCAN mod Y ABLE ule FCAN DOZE MODE FCAN ENABL
405. ue at address r3 move w 0 rl stash value at address rl dectsta r2 bne loop prom2pram end prom2pram fendif 2 7 2 2 10 Calling the main As the last step of the startup code the userPreMain file and the main functions are called The userPreMain can be found in the arch c file and contains architecture and peripheral specific initialization code It is empty in the current implementation In the case the main is prototyped with standard argc and argv arguments the 0 and NULL values are passed as it makes no sense to use them in the embedded application call userPreMain from appconfig c jsr userPreMain call main move w 0 pass parameters to main move w 0 R2 move w 0 R3 jsr main call the user program 2 7 2 2 11 Never Reached Finish Code In case that the main ever returns which would be very uncommon case the userPostMain de initialization code empty from arch c is called and the processor is halted If any of the debugging console I O operations are used in the application the calling of the internal fflush and fflush console functions can be un commented to assure the internal console buffers get flushed call userPostMain from appconfig c jsr userPostMain The fflush calls where removed because they added code growth cases where the user is not using any debugger Users should make these calls at the end of main if they
406. ult Status Reg sly REG ister EFPWM_READ_FAULTO_CONTRO NULL Return value of the Fault Register PAN DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 50 Freescale Semiconductor Inc Table 5 19 EFPWM Driver Commands pParam Description ag Lre EFPWM READ FAULTO STATUS NULL Return value of the Fault Status Reg viv _REG ister EFPWM_READ_FAULT1_CONTRO NULL Return value of the Fault Register L REG EFPWM READ FAULT1 STATUS NULL Return value of the Fault Status Reg _ ister EFPWM_READ_MASK_REG NULL Return value of the Mask Register viv EFPWM READ MASTER CONTR NULL Return value of the Master Control PN OL REG Register EFPWM READ OUTPUT ENABLE NULL Return value of the Output Enable _ Register EFPWM READ SW CONTROL O NULL Return value of the Software Con V Ib UT REG trolled Output Register EFPWM SET ACTIVE HIGH FAU EFPWM FAULT 0 1 2 3 Set active fault level to high at LTS selected fault inputs EFPWM SET ACTIVE HIGH FAU EFPWM_FAULT_X 0 1 2 3 Set active fault level to high at LTSO selected fault inputs EFPWM SET ACTIVE HIGH FAU EFPWM_FAULT_X 0 1 2 3 Set active fault level to high at 24152 LTS1 selected fault inputs EFPWM_SET_ACTIVE_LOW_FAU EFPWM FAULT 0111213 Set active fault level
407. uments GroupMask in Group mask Mask in ones bit mask pAddr in The memory address DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 19 Description The periphBitGrpSetVar macro sets the bit group to a given value a memory location addressed by parameter pAddr All bits specified by GroupMask are affected The bits are either set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits in Mask value are cleared This variant uses the accumulator and read modify write instructions to accomplish the requested operation The memory location is first read to accumulator the and bfset instructions are performed on accumulator and the result value is then written back to memory location Caution It might seem this macro is the proper way how to set the group of bits to certain value as there are no intermediate invalid values written in the target memory location However it is quite dangerous to use this macro when interrupts may occur between the read and write operations If the interrupt service routine would write the other portion of the target memory location the written value could be overwritten back with its previous state by the write accumulator operation of periphBitGrpSetVar Example 2 31 periphBitGrpSetVar macro usage periphBitGrpSetVar 0 007 10 amp ArchIO Pll plldb This code sets the lower 7
408. und set convergent rounding mode Call s void archSetConvRound void Arguments None Description The archSetConvRound macro sets the convergent rounding mode This macro clears the rounding R bit Bit 5 in the Operating Mode Register OMR Example 2 11 archSetConvRound macro usage archSetConvRound 2 4 1 10 archStop stop processing state Call s void archStop void Arguments None Description The archStop macro places the processor into the stop processing state by executing a stop instruction Example 2 12 archStop macro usage archStop 2 4 1 11 archTrap initiate a software interrupt Call s DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 8 Freescale Semiconductor Inc void archTrap void Arguments None Description The archTrap macro initiates a software interrupt by executing a swi instruction Example 2 13 archTrap macro usage archTrap 2 4 1 12 archWait wait processing state Call s void archWait void Arguments None Description The archWait macro places the processor into the wait processing state by executing a wait instruction Example 2 14 archWait macro usage archWait 2 4 1 13 archGetLimitBit get limit bit Call s 16 archGetLimitBit void Arguments None Description The archGetLimitBit inline function returns the status of the limit bit L Bit 6 in the Status Register SR Returns The returned
409. upt priority levels need to be set in GCT and the interrupts have to be enabled in the processor core archEnableInt For FMSTR SHORT INTR or FMSTR POLL DRIVEN modes the FMSTR Poll API function needs to be called periodically in the application For example in the application main loop See Driver API description in the next section for more detail on how to use advanced FreeMASTER features like Application Commands Recorder or TSA 6 6 1 Driver API This section describes the FreeMASTER driver API It can be expected the same API will be used with the new FreeMASTER driver on other Freescale platforms as well The following header files are needed in order to use the FreeMASTER driver Required Header File s include qs h include freemaster h DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 6 10 The next sections describe each driver API function in detail Function arguments for each routine described as in or out 1 in argument means that the parameter value is an input only to the function 2 out argument means that the parameter value is an output only from the function DSC56800EX Quick Start User s Guide Rev 2 04 2015 6 11 Freescale Semiconductor Inc 6 6 1 1 FMSTR_lInit Initializes the FreeMASTER Communication Call void FMSTR_Init void Arguments None Description This function initializes internal variables of the FreeM
410. ure type e define ArchIO as the extern variable while defining its address by a directive in linker command file DSC56800EX Quick Start User s Guide Rev 2 04 2015 2 4 Freescale Semiconductor Inc The second approach is used in the 56800EX Quick Start tool implementation by default Example 2 1 Using the ArchlO structure UWordl16 RegValue RegValue ArchIO TimerD Channel0 HoldReg ArchlO TimerD Channel0 CompareRegl 0 8000 The Example 2 1 reads the timer counter DO Hold Register HOLD and writes to the timer counter DO Compare Register 1 Example 2 2 Using the ArchlO structure UWordl16 RegValue RegValue periphMemRead amp ArchIO TimerD Channel0 HoldReg periphMemWrite 0x8000 amp ArchlO TimerD Channel0 CompareRegl Example 2 2 shows the same operation using the periphMemRead and periphMemWrite macros described later in Section 2 5 2 4 Core System s Routines and Macros This section describes routines macros and intrinsic function redefinition provided by the Core System Infrastructure 2 4 1 Architecture dependent routines This section describes architecture dependent routines and macros which provide interface to the 56800EX core architecture It encapsulates the unique features of the 56800EX architecture into the abstract APIs routines are defined in the arch h header file 2 4 1 1 archEnablelnt enable interrupts Call s void archEnableInt void Arguments No
411. ure zero crossing detection ABLE POS2NEG NEG2POS logic for sample 9 DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 22 Freescale Semiconductor Inc 5 1 2 16 bit Analog to Digital Converter ADC16 The 16 bit analog to digital ADC16 converter is based on the linear successive approximation algorithm with up to 16 bit resolution The ADC16 resolution can be set to 16 bit 12 bit 10 bit and 8 bit modes The results are right justified unsigned format for single ended The converter includes up to 24 single ended external analog inputs The ADC16 provides the following features e Single or continuous conversion which means the automatic return to idle after a single conversion e Configurable sample time and conversion speed power e Conversion complete hardware average complete flag and interrupt e Input clock selectable from up to four sources e Operation in Low Power modes for lower noise e Asynchronous clock source for lower noise operation with option to output the clock e Selectable hardware conversion trigger with hardware channel select e Automatic compare with interrupt for less than greater than or equal to within range or out of range programmable value Temperature sensor e Hardware average function e Selectable voltage reference external or alternate Self Calibration mode The Table 5 4 shows module identifiers for ADC16 Driver Table 5
412. urpose Ports Write Protection OFF GPIO A General Purpose I O Por GPIO B General Purpose I O Por 7 GPIO C General Purpose I O Por Two module pins out of two are not available on any device pin See GPIO C 4 QT A0 Timer Pin 0 is not set to Timer mode in C3 sys To prevent memory read acces error the MSCAN module clock should be enabled t The sianal Cl 111 not availahle an anu device nin See 4 um RU Show warnings even for non included modules NUM 4 Figure 7 6 Warnings View 7 2 1 6 Options dialog The Options dialog Figure 7 7 can be invoked from a File Options menu It contains the following settings for the overall GCT functionality Generate detailed comments check box enables saving of the human readable commentary describing the configuration of each module Preserve user comments check box when checked assures the user comments placed after the individual macro values are not lost when re generating the appconfig h file This option is rarely used as there is typically no need for the user to manually edit any comments in the appconfig h file Generate all register values check box enables saving of all register values of the selected peripheral modules into the appconfig h file When this option is not enabled which is the default state
413. ve edge was seen on the RXD viv input pin SCI RECEIVER INPUT EDGE IN SCI ENABLE Enable disable the Input Edge Inter XE T SCI DISABLE rupt SCI RX ERROR INT SCI ENABLE Enable disable Receive Error Inter sy SCI_DISABLE rupt SCI_RX_FULL_INT SCI_ENABLE Enable disable Receiver Full Interrupt SCI_DISABLE SCI SEND BREAK NULL Send a single break character viv SCI_SEND_XOFF NULL Send the XOFF priority character viv SCI_SEND_XON NULL Send the XON priority character viv DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 145 Table 5 58 SCI Driver Commands Cmd pParam Description 56F82xxx 56F84xxx SCI_SET_BAUDRATE One of the 501 BAUDxx con stants or UWord16 divisor value Configure the SCI Baud Rate Regis ter The BAUD xx baud rate values are defined for the most common clock frequencies lt lt SCI SET FRACTIONAL BAUDRA UWord16 value 0 7 Configure the SCI Fractional Baud Rate divider Provide a value from Oto v v 7 that is divided by 8 STOP IN WAIT SCI ENABLE SCI DISABLE Enable disable the low power STOP mode during the CPU WAIT mode SCI TEST STATUS REG SCI TX EMPTY FLAG SCI TX IDLE FLAG SCI RX FULL FLAG SCI RX IDLE LINE FLAG SCI OVERRUN FLAG SCI NOISE FLAG SCI FRAMING ERROR FL AG SCI PARITY ERROR FLA G SCI RX ACTIVE FLAG SCI LIN SYNC ERROR FL AG Te
414. vides a high degree of architectural and hardware independence for the application code This portability is achieved by the modular design of DSP56800EX Quick Start which in this case isolates all chip specific functionality into a set of defined tested and documented Application Programming Interface API This chapter describes the API for on chip drivers forming the interface between hardware and application software The source code implementation can be found at lt gt src MC56F 8xxx peripheral of the DSP56800EX Quick Start It defines the API by identifying all public interface functions commands and data structures The DSP56800EX Quick Start on chip driver s API is implemented as a low level device driver interface The low level device driver interface was chosen mainly for its efficiency and also because it enables the complete use of the hardware functionality Yet another reason 1 the non standardized approach regarding the usage of most of the on chip peripheral modules The portability of the low level device driver interface is not influenced so much by the lower abstraction level but mainly by the capability of the peripheral module hardware In other words the portability between devices is ensured and involves the same or a very similar implementation of the peripheral module hardware When the peripheral modules on target devices are significantly different the portability is much lower Nevertheless even in this case
415. w 0 Interrupt Disable Int Polarity Active high Output Mode Push pull Pin 6 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int Polarity Active high Output Mode Push pull Pin 7 Function GPIO Direction Output Init Value Low 0 Interrupt Disable Int Polarity Active high Output Mode Push pull SUA define GPIO define GPIO_E DR_INIT 0 00 ER INI 0x0000U D EXP GPIO_F Configuration DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 2 41 Pin 0 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 1 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 2 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 3 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high Pin 4 Function GPIO Direction Input PullUp Disable Interrupt Disable Int Polarity Active high 2 application code file KK IK KK ck ck ck ck ck ko kk File Name main c Description Main application file generated automatically from the d DSP56800EX Quick S
416. ware and derivative works thereof in object machine readable form only as integrated with a development platform from Freescale or other development prototype or production platform utilizing at least one 56800 E processor from Freescale and 5 to sublicense to others the right to use the distributed Software You must prohibit your sublicensees from translating reverse engineering decompiling or disassembling the Software except to the extent applicable law specifically prohibits such restriction If you violate any of the terms or restrictions of this Agreement Freescale may immediately DSC56800EX Quick Start User s Guide Rev 2 04 2015 8 1 Freescale Semiconductor Inc terminate this Agreement require that you stop using and delete all copies of the Software in your possession or control IF SOFTWARE PROVIDED IN OBJECT FORM ONLY Freescale grants to you the non exclusive non transferable right 1 to use the Software exclusively in conjunction with a development platform from Freescale or other development prototype or production platform utilizing at least one 56800 E processor from Freescale Exclusive Use 2 to reproduce the Software as necessary to accomplish the Exclusive Use 3 to distribute the Software only as integrated with a development platform from Freescale or other development prototype or production platform utilizing at least one 56800 E processor from Freescale and 4 to sublicense to others the
417. ware control register 3 PIS 3 SYS WRITE SW CONTROL REG UWord16 Write SIM software control register 4 4 SYS_WRITE_SW_CONTROL_REG UWord16 Write SIM software control register 5 5 SYS_WRITE_SW_CONTROL_REG UWord16 Write SIM software control register 6 2 6 DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 5 163 Table 5 62 SYS Driver Commands Cmd pParam Description 56F82xxx 56F84xxx 7 SYS WRITE SW CONTROL REG UWord16 Write SIM software control register 7 lt DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 164 Freescale Semiconductor Inc 5 1 29 Inter Peripheral Crossbar Switch Driver This module implements array of N input combinational muxes muxes share the same N inputs in the same order but each mux has its own independent select field The intended application of this module is to provide a flexible crossbar switch function that allows any input typically from external GPIO or internal module outputs to be connected to any output typically to external GPIO or internal module inputs under user control This is used to allow user configuration of data paths between internal modules and between internal modules and GPIO The Table 5 63 shows module identifiers for XBAR Driver Table 5 63 Identifiers for XBAR Driver Module identifier 56F82xxx 56F84xxx XBAR_A v XBAR B Y Y
418. x LOCK_LOST_INT1 LO viv CK_LOST_INTO CLOCK_LO ST OCCS CLOCK MONITOR ENABL OCCS ENABLE OCCS DIS Enable disable the clock monitor func PN E ABLE tionality of the XOSC OCCS CLOCK SOURCE TOPWM OCCS RAW PLL OCCS PL Setthe 200MHz clock source to PWM NANO EDGE L DIV2 nano edge The recommended setting is OCCS PLL DIV2 when the PLL 2 output frequency is 400 MHz then the PLL DIV2 Clock is selected as PWM 2X clock OCCS CRYSTAL CLOCK DIV2 OCCS ENABLE OCCS DIS Enable disable the external oscillator ABLE output divider by 2 before use as MSTR OSC Note The CTRL PRECS bit field 2 should not be selecting the external clock source while changing the value of OSC_DIV2 to avoid glitches on the system clock OCCS CRYSTAL OSCILLATOR P OCCS ENABLE OCCS DIS Enable disable the power down of the OWER DOWN ABLE external crystal oscillator Note To prevent a loss of clock to the core or 212 the PLL this bit should never be asserted while this clock source is selected OCCS_DIRECT_CLOCK_MODE OCCS ENABLE OCCS DIS Enable disable the direct clock input ABLE on the XTAL pin Use OCCS ENABLE when the clock source is connected on the XTAL pin Use OCCS DISABLE when the crys tal or the resonator is connected on the EXTAL XTAL pins Note that the OCCS_SELECT_EXT_CLOCK_SOU RCE command needs to be used first to switch clock input to OCCS_CLKIN_OSC OCCS_GET_IPBUS_FREQ UWord32 oscillator frequency Return the IPBus Clock fre
419. y module includes the following accessible memory regions e Program flash memory for vector space and code store e FlexNVM for data store and additional code store e FlexRAM for high endurance data store or traditional RAM Flash memory is ideal for single supply applications permitting in the field erase and reprogramming operations without the need for any external high voltage power sources The flash memory module includes a memory controller that executes commands to modify flash memory contents An erased bit reads 1 and a programmed bit reads 0 The programming operation is unidirectional it can only move bits from the 1 state erased to the 0 state programmed Only the erase operation restores bits from 0 to 1 bits cannot be programmed from a 0 to a 1 CAUTION A flash memory location must be in the erased state before being programmed Cumulative programming of bits back to back program operations without an intervening erase within a flash memory location is not allowed Re programming of existing 08 to 0 is not allowed as this overstresses the device The standard shipping condition for flash memory is erased with security disabled Data loss over time may occur due to degradation of the erased 17 states and or programmed 0 states Therefore it is recommended that each flash block or sector be re erased immediately prior to factory programming to ensure that the full data retention capability is achieved
420. ying the contentof v v the Data Direction Register GPIO SETAS PERIPHERAL combination of BIT x Assign the selected GPIO pins of the 0 1 15 to a peripheral by modifying the E content of the Peripheral Enable Register GPIO SETAS PUSHPULL combination of BIT x Set the output driver of the selected 0 1 15 GPIO pins to push pull mode by sly modifying the content of the Push Pull Mode Register GPIO_SETAS_PUSHPULL combination of BIT_x Set the output driver of the selected 0 1 15 GPIO pins to push pull mode by modifying the content of the Push Pull Mode Register GPIO_SW_INT_ASSERT combination of BIT_x Enable a software generated interrupt 0 1 15 request by modifying the content of the Interrupt Assert Register GPIO_SW_INT_ASSERT combination of BIT_x Enable a software generated interrupt x 0 1 15 request by modifying the content of viv the Interrupt Assert Register GPIO_TEST_INT_PENDING combination of BIT_x Test the selected interrupt pending 0 1 15 flag s from the Interrupt Pending viv Register GPIO_TOGGLE_PIN combination of BIT_x Toggle the selected GPIO pins by x 0 1 15 modifying the content of the Data viv Register GPIO_WRITE_DATA UWord16 Write to the whole port by writing to 2112 the Data Register DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 90 Freescale Semiconductor Inc 5 1 16 High Speed Comparator 5 Dr
421. you not sold Freescale owns the Software and United States copyright laws and international treaty provisions protect the Software Therefore you must treat the Software like any other copyrighted material e g a book or musical recording You may not use or copy the Software for any other purpose than what is described in this Agreement Except as expressly provided herein Freescale does not grant to you any express or implied rights under any Freescale or third party patents copyrights trademarks or trade secrets Additionally you must reproduce and apply any copyright or other proprietary rights notices included on or embedded in the Software to any copies or derivative works made thereof in whole or in part if any SUPPORT Freescale is NOT obligated to provide any support upgrades or new releases of the Software If you wish you may contact Freescale and report problems and provide suggestions regarding the Software Freescale has no obligation whatsoever to respond in any way to such a problem report or suggestion Freescale may make changes to the Software at any time without any obligation to notify or provide updated versions of the Software to you DSC56800EX Quick Start User s Guide Rev 2 04 2015 Freescale Semiconductor Inc 8 2 LIMITED WARRANTY ON MEDIA Freescale warrants that the media on which the Software is recorded will be free from defects in materials and workmanship under normal use for a period of 90 days
422. ze 2 16 Set length of the data word in bits 21 22 Possible value is 2 16 SPI SET TXEMPTY CONDITION SPI WHEN xxx Set how many words in TX FIFO EA or value 0 3 causes the TXEMPTY condition SPI SET WIRED OR MODE SPI NORMAL Set normal or wired OR mode of the 21 SPI OPEN DRAIN SPI pins SPI STOP MODE HOLDOFF SPI ENABLE Enable Stop Mode Holdoff SPI DISABLE TEST SS INPUT NULL Return immediate state of the SS input pin SPI TX EMPTY INT SPI ENABLE Interrupt enable or disable for SPTIE VAN SPI DISABLE DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 150 Freescale Semiconductor Inc Table 5 60 SPI Driver Commands Freescale Semiconductor Inc Description 1 2 Lre SPI_WRITE_CANCEL NULL Cancel non blocking write operation viv SPI WRITE CONTROL REG UWord16 Write to SPI Control Register viv SPI WRITE DATA UWord16 Write data to SPI Data Transmit Reg ister When in MASTER mode it ini viv tiates transmission SPI_WRITE_DATA_DELAY UWord16 0 0x1fff Set inter word delay in the IPbus 42 clocks DSC56800EX Quick Start User s Guide Rev 2 04 2015 5 151 5 1 28 System SYS Driver This section describes the API for on chip system support functions system integration module low voltage detection and external bus interface The Table 5 61 shows module identifiers for SYS D

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