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NT3H1101/NT3H1201 - NXP Semiconductors

1. detail X 0 2 5 5mm scale DIMENSIONS mm are the original dimensions A A A A pq E 2 UNIT max 1 2 3 bp j 0 15 0 95 0 45 0 28 3 1 3 1 mm 11 f oo5 oso 0 25 015 29 29 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION Sarao 03 02 18 Fig 27 Package outline SOT501 1 TSSOP8 NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 60 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 37 Pin description Pin no Symbol Description 1 LA Antenna connection LA 2 VSS GND 3 SCL Serial Clock 12C 4 FD Field detection 5 SDA Serial data 12C 6 VCC VCC in connection external power supply 7 Vout Voltage out energy harvesting 8 LB Antenna connection LB 15 Abbreviations 16 References Table 38 Abbreviati
2. RF address IC Address Byte number sector 3 Dec Hex Dec Hex 0 1 2 3 248 F8h 254 FEh NC_REG LAST_NDEF_BLOCK SRAM _MIRROR WDT_LS _BLOCK 249 F9h WDT_MS I2C_CLOCK_STR NS_REG 00h fixed NT3H1101 1201 Both the session and the configuration bits have the same register except the REG_LOCK bits which are only available in the configuration bits and the NS_REG bits which are only available in the session registers After POR the configuration bits are loaded into the session registers During the communication session the values can be changed but the related effect will only be visible within the communication session for the session registers or after POR for the configuration bits After POR the registers values will be again brought back to the default configuration values All registers and configuration default values access conditions and descriptions are defined in Table 13 and Table 14 Reading and writing the session registers via C can only be done via the READ and WRITE registers operation see Section 9 8 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 22 of 65 NXP Semiconductors NT3H1101 NT3H1201 Table 13 Configuration bytes NTAG 12C Energy harvesting Type 2 Tag with I2C interface Bit Field Acc
3. Symbol Parameter Conditions Min Max Unit l input current LA LB 40 mA Tstg storage temperature 55 125 C Vesp electrostatic discharge voltage 1 2 kV VFD Voltage on the FD pin 3 6 V VSDA Voltage on the SDA line 3 6 V VSCL Voltage on the SCL line 3 6 V 1 Stresses above one or more of the limiting values may cause permanent damage to the device 2 Exposure to limiting values for extended periods may affect device reliability 3 ANSI ESDA JEDEC JS 001 Human body model C 100 pF R 1 5 KQ 13 Characteristics 13 1 Electrical characteristics Table 36 Characteristics Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance LA LB 44 50 56 pF fi input frequency 13 56 MHz Toper operating temperature 40 95 C Energy harvesting characteristics Vout voltage generated at the Vout 3 2 V pin C interface characteristics Vec supply voltage NTAG 2C supplied via Vcc only 1 70 3 6 vV IDD supply current 155 uA EEPROM characteristics tret retention time full operating temperature range 20 year Nendu w write endurance full operating temperature range 500000 l cycle 1 A minimum supply voltage of 1 8 V is required when RF field is present NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 58 of 65 NXP Semiconductors NT
4. NT3H1101 NT3H1201 E BUS NTAG I C Energy harvesting NFC Forum Type 2 Tag with field detection pin and I C interface Rev 3 3 15 July 2015 Product data sheet 265433 COMPANY PUBLIC 1 General description NTAG 12C The entry to the NFC world simple and lowest cost The NTAG I C is the first product of NXP s NTAG family offering both contactless and contact interfaces see Figure 1 In addition to the passive NFC Forum compliant contactless interface the IC features an 12C contact interface which can communicate with a microcontroller if the NTAG I2C is powered from an external power supply An additional externally powered SRAM mapped into the memory allows a fast data transfer between the RF and I C interfaces and vice versa without the write cycle limitations of the EEPROM memory The NTAG 12C product features a configurable field detection pin which provides a trigger to an external device depending on the activities at the RF interface The NTAG I C product can also supply power to external low power devices e g a microcontroller via the embedded energy harvesting circuitry controller NFC enabled device Energy Harvesting Field detection Data Data Energy Energy gt gt aaa 010357 Fig 1 Contactless and contact system NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 2 F
5. The register SRAM_MIRROR_BLOCK see Table 14 indicates the address of the first page of the SRAM buffer In the case where the SRAM mirror is enabled and the READ command is addressing blocks where the SRAM mirror is located the SRAM mirror byte values will be returned instead of the EEPROM byte values Similarly if the tag is not VCC powered the SRAM mirror is disabled and reading out the bytes related to the SRAM mirror position would return the values from the EEPROM In the Pass through mode PTHRU_ON_OFF 1b see Section 8 3 11 the SRAM is mirrored to the fixed address 240 255 for RF access see Section 11 in the first memory sector for NTAG I C 1k and in the second memory sector for NTAG I2C 2k UID serial number The unique 7 byte serial number UID is programmed into the first 7 bytes of memory covering page addresses 00h and 01h see Figure 6 These bytes are programmed and write protected in the production test SNO holds the Manufacturer ID for NXP Semiconductors 04h in accordance with ISO IEC 14443 3 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 16 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface MSB LSB fofofofojo i o fo manufacturer ID for NXP Semiconductors 04h page 0 page 1 page
6. 05 40 10 4 ATQA and SAK responses 40 10 5 GET_VERSION 200005 41 10 6 READS sietett gnre cecatok a ya aia ia 42 10 7 FAST READ 3 ascii wee Se ca eS whee es 43 10 8 WRITE acceso chia ce eG oes oie wag week 45 10 9 SECTOR SELECT 005 46 11 Communication and arbitration between RF and I C interface 05 48 11 1 Non Pass through mode 48 11 1 1 l2C interface accesS 0 000 48 11 1 2 RF interface access 05 48 11 2 SRAM buffer mapping with Memory Mirror enabled 00 cc cece ee eee 49 11 3 Pass through mode 52 11 3 1 SRAM buffer mapping 52 11 3 2 RF to l C Data transfer 55 11 3 3 l2C to RF Data transfer 56 12 Limiting values 00 220eeeeeee 58 13 Characteristics 000000008s 58 13 1 Electrical characteristics 58 14 Package outline 00 200ee eens 59 15 Abbreviations ccc eee eee eee 61 16 References sit sii iain teres ewes 61 17 Revision history 0000000eeeeee 62 18 Legal information 00e eee eens 63 18 1 Data sheet status 00 05 63 18 2 Definitions 0 0 0 0 eee eee 63 18 3 Disclaimers 000 cee eee eee 63 18 4 LicenseS 2 0 ee ees 64 18 5 Trademarks oir saci aisha whe ena werner des 64 19 Contact information 64
7. 10 IDLE State niee e eek ead eae 10 READY 1 state 0 0 2 10 READY 2 state 0 0200 0 11 ACTIVE state 00 000 cease 11 ALT State cesat hed coed arian doer kia aa tae 11 Memory organization 11 Memory map from RF interface 11 Memory map from I C interface 13 EEPROM pies aia e eee heal a a Aa 16 SRAM earet ai wend i a Shand a 16 UlD serial number nnan nn annann 16 Static lock bytes nnana nananana 17 Dynamic Lock Bytes 04 18 Capability Container CC bytes 20 User Memory pageS 04 20 Memory content at delivery 21 NTAG 12C configuration and session FOGISTCLS ee ccnp Becton ag ratua ie Ee Se ee 21 Configurable Field Detection Pin 28 Watchdog timer 20 0 eee 32 Energy harvesting 0005 32 C commands 202 ce eee eee eee 33 Start condition 00000 e eee 33 Stop condition 0 00000e 33 9 3 Soft reset feature 2 6 eee 34 9 4 Acknowledge bit ACK 34 9 5 Data input 0 00 eee eee 34 9 6 Addressing 0 0c eee eee eee 34 9 7 READ and WRITE Operation 35 9 8 WRITE and READ register operation 37 10 RF Command 000000eeeeeeeee 39 10 1 NTAG I2C command overview 39 10 2 TIMING isis ack ete de a EEEE adee ena en 39 10 3 NTAG ACK and NAK
8. 00000000 00001111 result in page 3 read only state 11100001 00010000 01101101 00001111 aaa 012804 Fig 10 CC bytes of NTAG I2C 1k version page 3 Example NTAG I2C 2k version byte fol e2 s default value initialized state CC bytes data 11100001 00010000 11101010 00000000 write command to page 3 CE Bytes 00000000 00000000 00000000 00001111 result in page 3 read only state 11100001 00010000 11101010 00001111 aaa 012805 Fig 11 CC bytes of NTAG I C 2k version The default values of the CC bytes at delivery are defined in Section 8 3 10 8 3 9 User Memory pages Pages 04h to Eth via the RF interface Block 01h to 37h plus the first 8 bytes of block 38h via the 12C interface are the user memory read write areas for NTAG 12C 1k version Pages 04h sector 0 to DFh sector 1 via the RF interface Block 1h to 77h via the 12C interface are the user memory read write areas for NTAG 12C 2k version The default values of the data pages at delivery are defined in Section 8 3 10 NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 20 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 8 3 10 Memory content at delivery 8 3 11 The capability container in page
9. HV voltage error during EEPROM write or erase cycle Needs to be written back via I C to Ob to be cleared 1 EEPROM_WR_BUSY READ READ Ob 1b EEPROM write cycle in progress access to EEPROM disabled Ob EEPROM access possible 0 RF_FIELD_ PRESENT READ READ Ob 1b RF field is detected NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 27 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 8 4 Configurable Field Detection Pin The field detection feature provides the capability to trigger an external device e g uController or switch on the connected circuitry by an external power management unit depending on activities on the RF interface The conditions for the activation of the field detection signal FD_ON can be e The presence of the RF field e The detection of a valid command Start of Communication e The selection of the IC The conditions for the de activation of the field detection signal FD_OFF can be e The absence of the RF field e The detection of the HALT state e The RF interface has read the last part of the NDEF message defined with LAST_NDEF_BLOCK All the various combinations of configurations are described in Table 13 and illust
10. NXP Semiconductors NT3H1101 NT3H1201 NTAG I7C Energy harvesting Type 2 Tag with I2C interface 10 8 WRITE NT3H1101 1201 The WRITE command requires a block address and writes 4 bytes of data into the addressed NTAG I C page The WRITE command is shown in Figure 22 and Table 27 Table 28 shows the required timing NTAG ACK ACK NTAG NAK NAK Ee TNAK 57 us Time out TTimeOut aaa 006990 Fig 22 WRITE command Table 27 WRITE command Name Code Description Length Cmd A2h write one page 1 byte Addr page address 1 byte CRC CRC according to Ref 1 2 bytes Data data 4 bytes NAK see Table 17 see Section 10 3 4 bit Table 28 WRITE timing These times exclude the end of communication of the NFC device Tack nak min Tack nak max TTimeout WRITE n 9l1 TTimeOut 10 ms 1 Refer to Section 10 2 Timing In the initial state of NTAG 12C the following memory pages are valid Addr parameters to the WRITE command e Page address from 02h to E2h E8h and EQh sector 0 for NTAG I C 1k e Page address from 02h to FFh sector 0 from 00h to EOh E8h and EQh sector 1 for NTAG I C 2k e SRAM buffer addresses when Pass through mode is enabled Addressing a memory page beyond the limits above results in a NAK response from NTAG IC Pages that are locked against writing cannot be reprogrammed using any write command The locking mec
11. l ley Pl l ol l l lol lol l ai ad las ja ee aaa 017243 Fig 14 Illustration of the field detection feature when configured for selection of the tag detection NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 31 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 8 5 Watchdog timer In order to allow the I C interface to perform all necessary commands READ WRITE the memory access remains locked to the I C interface until the register 2C_LOCKED is cleared by the host see Table 14 In order however to avoid that the memory stays locked to the I C for a long period of time it is possible to program a watchdog timer to unlock the 12C host from the tag so that the RF reader can access the tag after a period of time of inactivity The host itself will not be notified of this event directly but the NS_REG register is updated accordingly the register bit 12C_LOCKED will be cleared see Table 14 The default value is set to 20 ms 848h but the watch dog timer can be freely set from 0001h 9 43 us up to FFFFh 617 995 ms The timer starts ticking when the communication between the NTAG I C and the I C interface starts In case the communication with the 12C is still going on after the w
12. 150um thickness on film frame carrier electronic fail die bumped marking according to SECS II format Au bumps 1k Bytes memory 50pF input capacitance NT3H1201W0OFUG FFC 8 inch wafer 150um thickness on film frame carrier electronic fail die bumped marking according to SECS II format Au bumps 2k Bytes memory 50pF input capacitance NT3H1101WOFHK XQFN8 Plastic extremely thin quad flat package no leads 8 terminals body 1 6 x SOT902 3 1 6 x 0 6mm 1k bytes memory 50pF input capacitance NT3H1201WOFHK XQFN8 Plastic extremely thin quad flat package no leads 8 terminals body 1 6 x SOT902 3 1 6 x 0 6mm 2k bytes memory 50pF input capacitance NT3H1101WOFTT TSSOP8 Plastic thin shrink small outline package 8 leads body width 3 mm 1k SOT505 1 bytes memory 50pF input capacitance NT3H1201WOFTT TSSOP8 Plastic thin shrink small outline package 8 leads body width 3 mm 2k SOT505 1 bytes memory 50pF input capacitance 5 Marking Table 2 Marking codes Type number Marking code NT3H1201FHK N12 NT3H1101FHK N11 NT3H1101WOFFT 31101 NT3H1201WOFFT 31201 NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 4 of 65 NXP Semiconductors NT3H1101 NT3H1201 6 Block diagram NTAG 12C Energy harvesting Type 2 Tag with I2C interface NT3H1101 1201 Fig 2
13. LOCK PAGE 32 47 LOCK PAGE 16 31 LOCK PAGE 224 225 LOCK PAGE 208 223 LOCK PAGE 192 207 LOCK PAGE 176 191 LOCK PAGE LOCK PAGE 144 159 page 226 E2h BL 16 47 BL 208 225 BL 176 207 BL 144 175 BL 112 143 BL 80 111 BL 48 79 1 aaa 008092 Fig 8 NTAG I C 1k Dynamic lock bytes 0 1 and 2 NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 18 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 240 271 LOCK PAGE 208 239 LOCK PAGE 176 207 LOCK PAGE 144 175 LOCK PAGE 112 143 LOCK PAGE 80 111 LOCK PAGE 48 79 LOCK PAGE 16 47 LOCK PAGE 464 479 LOCK PAGE 432 463 LOCK PAGE 400 431 LOCK PAGE 368 399 LOCK PAGE 336 367 LOCK PAGE 304 335 LOCK PAGE 272 303 Ww 0 lt a x Q O page 224 E0h BL 464 479 BL 400 463 BL 336 399 BL 272 335 BL 208 271 BL 144 207 BL 80 143 BL 16 79 Block Locking BL bits bit 7 6 5 4 3 2 1 aaa 012803 Fig 9 NTAG I C 2k Dynamic lock bytes 0 1 and 2 The default value of the dynamic lock bytes is 00 00 OOh The value of Byte 3 is always 00h when read Reading the 3 bytes for the dynamic lock bytes and the Byte 3 00h from RF interface address E2h sector 0 NTAG 12C 1k or EOh sector 1 NTAG
14. 03h and the page 04h and 05h of NTAG IPC is pre programmed to the initialized state according to the NFC Forum Type 2 Tag specification see Ref 1 as defined in Table 8 NTAG 12C 1k version and Table 9 NTAG 12C 2k version This content is READ only from the RF side and READ amp WRITE from the 2C side The User memory contains an empty NDEF TLV Remark The default content of the data pages from page 05h onwards is not defined at delivery Table 8 Memory content at delivery NTAG I C 1k version Page Address Byte number within page 0 1 2 3 03h Eth 10h 6Dh 00h 04h 03h 00h FEh 00h 05h 00h 00h 00h 00h Table 9 Memory content at delivery NTAG I C 2k version Page Address Byte number within page 0 1 2 3 03h Eth 10h EAh 00h 04h 03h 00h FEh 00h 05h 00h 00h 00h 00h NTAG I2C configuration and session registers NTAG IC functionalities can be configured and read in two separate locations depending if the configurations shall be effective within the communication session session registers or by default after Power On Reset POR configuration bits The configuration registers of pages E8h to EQh sector 0 see Table 10 or 1 see Table 11 depending if it is for NTAG I C 1k or 2k via the RF interface or block 3Ah or 7Ah depending if it is for NTAG 2C 1k or 2k via the I C interface are used to configure the default functionalities of the NTAG I C Those b
15. 1 Oth Serial number Internal READ 2 02h Internal Static lock bytes READ R amp W 3 03h Capability Container CC READ amp WRITE 4 04h ae SRAM memory 16 blocks READ amp WRITE 19 13h 255 FFh User memory READ amp WRITE 223 DFh 224 E0h Dynamic lock bytes 00h R amp W READ 225 Eth 226 E2h 227 E3h 228 E4h Invalid access returns NAK n a 229 E5h 230 E6h 231 E7h 232 E8h Configuration registers see 8 3 11 233 E9h 234 EAh g dis Invalid access returns NAK n a 255 FFh 2 Invalid access returns NAK n a 3 0 00h Invalid access returns NAK n a 248 F8h Session registers see 8 3 11 249 F9h 7 Invalid access returns NAK n a 255 FFh All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 51 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG I7C Energy harvesting Type 2 Tag with I2C interface 11 3 Pass through mode 11 3 1 NT3H1101 1201 PTHRU_ON_OFF 1b see Table 14 enables and indicates Pass through mode To handle large amount of data transfer from one interface to the other NTAG I C offers the Pass through mode where data is transferred via a 64 byte SRAM buffer This buffer offers fast write access and unlimited write endurance as well as an easy handshake mechanism between the two interfaces This buffer is m
16. 12C 2k or from 12C address 38h NTAG I C 1k or 78h NTAG I C 2k will also return a fixed value for the next 12 bytes of 00h Like for the static lock bytes this process of modifying the dynamic lock bytes is irreversible from RF perspective If a bit is set to logic 1 it cannot be changed back to logic 0 From C perspective the bits can be reset to Ob NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 19 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 8 3 8 Capability Container CC bytes The Capability Container CC page 03h is programmed during the IC production according to the NFC Forum Type 2 Tag specification see Ref 1 These bytes may be bit wise modified by a WRITE command from the I C or RF interface Once set to 1b it is only possible to reset it to Ob from C perspective I C address byte 0 and static lock bytes byte 10 and byte 11 are coded in block 0 and may be changed unintentionally See examples for NTAG I C 1k version in Figure 10 and for NTAG I C 2k version in Figure 11 page 3 Example NTAG 12C 1k version byte bo 4 els default value initialized state CC bytes byte 11100001 00010000 01101101 00000000 write command to page 3 CC bytes 00000000 00000000
17. 20 Contents 2 20 0 c eee eee eee eee 65 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2015 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 15 July 2015 265433
18. 255 FFh 1 Invalid access returns NAK n a 2 Invalid access returns NAK n a 3 0 00h Invalid access returns NAK n a 248 F8h P Session registers see 8 3 11 249 F9h Invalid access returns NAK n a 255 FFh NT3H1101 1201 All information provided in this document is subject to legal disclaimers Rev 3 3 15 July 2015 265433 NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC 53 of 65 NXP Semiconductors NT3H1101 NT3H1201 Table 34 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Illustration of the SRAM memory addressing via the RF interface in Pass through mode PTHRU_ON_OFF set to 1b for the NTAG 12C 2k Sector Page address Byte number within a page Access address Dec Hex 1 2 3 conditions 0 0 00h Serial number READ 1 Oth Serial number Internal READ 2 02h Internal Static lock bytes READ R amp W 3 03h Capability Container CC READ amp WRITE 4 04h 19 13h 255 FFh User memory READ amp WRITE 1 0 1 223 DFh 224 E0h Dynamic lock bytes 00h R amp W READ 225 Eth 226 E2h 227 E3h 228 E4h Invalid access returns NAK n a 229 E5h 230 E6h 231 E7h 232 E8h Configuration registers see 8 3 11 233 E9h e 234 EAh Invalid access returns NAK n a 240 FOh ue SRAM 16 pages READ amp WRITE
19. 255 FFh 2 Invalid access returns NAK n a 3 0 00h Invalid access returns NAK n a 248 F8h Session registers see 8 3 11 249 F9h Bee SEE Invalid access returns NAK n a NT3H1101 1201 All information provided in this document is subject to legal disclaimers Rev 3 3 15 July 2015 265433 NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC 54 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 11 3 2 RF to I2C Data transfer If the RF interface is enabled RF_LOCKED 1b and data is written to the terminator block page of the SRAM via the RF interface at the end of the WRITE command bit SRAM_I2C_READY is set to 1b and bit RF_LOCKED is set to 0b automatically and the NTAG I C is locked to the I C interface To signal to the host that data is ready to be read following mechanisms are in place e The host polls reads bit SRAM_I2C_READY from NS_REG see Table 14 to know if data is ready in SRAM e A trigger on the FD pin indicates to the host that data is ready to be read from SRAM This feature can be enabled by programming bits 5 2 FD_OFF FD_ON of the NC_REG appropriately see Table 13 This is illustrated in the Figure 24 If the tag is addressed with the correct I C slave address the I2C_LOCKED bit is automatically set to 1b according to the interface arbitration After a
20. READ from the terminator page of the SRAM bit SRAM_I2C_READY and bit I2C_LOCKED are automatically reset to Ob and the tag returns to the arbitration idle mode where for example further data from the RF interface can be transferred NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 55 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface ON PF field OFF HIGH FD pin LOW 20 LOCKED SC 9 RF_LOCKED O O kel o 1 1 rd 1 ri 1 ip 2 SRAM_120_ READY eooo oo ooo TCC PTHRU_ON_OFF 0b W FD_ON 11b FD_OFF 11b ao ah o SRAM_MIRROR_ON_OFF 0b 9P TBh Oth Z PTHRU_DIR 1b gt t g eeg a g eg le y l e gp Tuy gp p E ISi 18 I Ej po pd i 12h lof Ig 128 188 I l o l2 Ig S los las Pi Event 13s oe 158l pool lol O l SZ ZI 26 PSS esr pil l2 lef l le leg l fe 12 gt l 150o Iz Igel pecl l l SEI uw T l 1 l leE te p 62g ek ie lhea Shee a Wee ea ee j more data available Fig 24 Illustration of the Field detection feature in combination with the Pass through mode for data transfer from RF to I C 11 3 3 C to RF Data transfer If the I C interface is enabled I2C_LOCKED is 1b and
21. Ref 2 2 3 Memory E 1904 bytes freely available with User Read Write area 476 pages with 4 bytes per pages for the NTAG I C 2k version E 888 bytes freely available with User Read Write area 222 pages with 4 bytes per pages for the NTAG I2C 1k version E Field programmable RF read only locking function with static and dynamic lock bits configurable from both 12C and NFC interfaces E 64 bytes SRAM volatile memory without write endurance limitation NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 2 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG I7C Energy harvesting Type 2 Tag with I2C interface E Data retention time of 20 years m Write endurance 500 000 cycles 2 4 12C interface C slave interface supports Standard 100 kHz and Fast up to 400 kHz mode see Ref 3 E 16 bytes one block written in 4 5 ms EEPROM or 0 4 ms SRAM Pass through mode including all overhead m RFID chip can be used as standard 1 C EEPROM 2 5 Security E Manufacturer programmed 7 byte UID for each device E Capability container with one time programmable bits E Field programmable read only locking function per page for first 12 pages and per 16 1k version or 32 2k version pages for the extended memory section 2 6 Key benefits m The Pass through mode allows
22. all 6 bits locked to Ob 1 REG_LOCK_l2C R amp W R amp W Ob Ob Enable writing of the configuration bytes via l C 1b Disable writing of the configuration bytes via l C Once set to 1b cannot be reset to Ob anymore 0 REG_LOCK_RF R amp W R amp W Ob Ob Enable writing of the configuration bytes via RF 1b Disable writing of the configuration bytes via RF Once set to 1b cannot be reset to Ob anymore NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 25 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 14 Session register bytes Bit Field Access Access Default Description via RF via lC values Session register NC_REG 7 I2C_RST_ON_OFF READ R amp W see configuration bytes description PTHRU_ON_OFF READ R amp W 0b 1b enables data transfer via the SRAM buffer Pass through mode 5 FD_OFF READ R amp W 4 3 FD_ON READ R amp W see configuration bytes description 2 1 SRAM_MIRROR_ READ R amp W 0b 1b enables SRAM mirroring ON_OFF 0 PTHRU_DIR READ R amp W see configuration bytes description Session register LAST NDEF_BLOCK 7 0 LAST_NDEF_ READ R amp W see configuration bytes descr
23. fast download and upload of data from RF to 12C and vice versa without the cycling limitation of EEPROM E NDEF message storage up to 1904 bytes 2k version or up to 888 bytes 1k version E The mapping of the SRAM inside the User Memory buffer allows dynamic update of NDEF message content 3 Applications With all its integrated features and functions the NTAG 12C is the ideal solution to enable a contactless communication via an NFC device e g NFC enabled mobile phone to an electronic device for Zero power configuration late customization E Smart customer interaction e g easier after sales service such as firmware update E Advanced pairing for e g WiFi or Blue tooth for dynamic generation of sessions keys Easier product customization and customer experience for the following applications Home automation Home appliances Consumer electronics Healthcare Printers Smart meters NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 3 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 4 Ordering information Table 1 Ordering information Type number Package Name Description Version NT3H1101W0OFUG_ FFC 8 inch wafer
24. from FF interface Memory access from the RF interface is organized in pages of 4 bytes each All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 11 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 4 NTAG I2C 1k memory organization from the RF interface Sector Page address Byte number within a page Access address Dec Hex 0 1 2 3 conditions 0 0 00h Serial number READ 1 Oth Serial number Internal READ 2 02h Internal Static lock bytes READ R amp W 3 03h Capability Container CC READ amp WRITE 4 04h 15 OFh User memory READ amp WRITE 225 Eth 226 E2h Dynamic lock bytes 00h R amp W READ 227 E3h 228 E4h 229 E5h Invalid access returns NAK n a 230 E6h 231 E7h 232 E8h Configuration registers see 8 3 11 233 E9h z 234 EAh e be Invalid access returns NAK n a 255 FFh 1 A as Invalid access returns NAK n a 2 P RF Invalid access returns NAK n a 3 0 00h Invalid access returns NAK n a 248 F8h Session registers see 8 3 11 249 F9h a 2 Invalid access returns NAK n a 255 FFh NT3H1101 1201 All information provided in this document is subject to legal disclai
25. number READ 1 Oth Serial number Internal READ 2 02h Internal Static lock bytes READ R amp W 3 03h Capability Container CC READ amp WRITE 4 04h Ji SRAM memory 16 blocks READ amp WRITE 19 13h User memory READ amp WRITE 225 Eth 226 E2h Dynamic lock bytes 00h R amp W READ 227 E3h 228 E4h 229 E5h Invalid access returns NAK n a 230 E6h 231 E7h 232 E8h l Configuration registers see 8 3 11 233 E9h 234 EAh oe Invalid access returns NAK n a 255 FFh 1 Invalid access returns NAK n a 2 Invalid access returns NAK n a 3 0 00h Invalid access returns NAK n a 248 F8h Session registers see 8 3 11 249 F9h 7 2 Invalid access returns NAK n a 255 FFh NT3H1101 1201 All information provided in this document is subject to legal disclaimers Rev 3 3 15 July 2015 265433 NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC 50 of 65 NXP Semiconductors NT3H1101 NT3H1201 Table 32 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Illustration of the SRAM memory addressing via the RF interface with SRAM_MIRROR_ON_OFF set to 1b and SRAM_MIRROR_BLOCK set to 01h for the NTAG I C 2k Sector Page address Byte number within a page Access address Dec Hex 0 1 2 3 conditions 0 0 00h Serial number READ
26. one block see Table 7 For the READ operation see Figure 16 following a Start condition the bus master host sends the NTAG 12C slave address code SA 7 bits with the Read Write bit RW reset to 0 The NTAG I C acknowledges this A and waits for one address byte MEMA which should correspond to the address of the block of memory SRAM or EEPROM that is intended to be read The NTAG I C responds to a valid address byte with an acknowledge A A Stop condition can be then issued Then the host again issues a start condition followed by the NTAG 12C slave address with the Read Write bit set to 1b When I2C_CLOCK_STR is set to 0b a pause of at least 50 us shall be kept before this start condition The NTAG 12C acknowledges this A and sends the first byte of data read DO The bus master host acknowledges it A and the NTAG 12C will subsequently transmit the following 15 bytes of memory read with an acknowledge from the host after every byte After the last byte of memory data has been transmitted by the NTAG 12C the bus master host will acknowledge it and issue a Stop condition For the WRITE operation see Figure 16 following a Start condition the bus master host sends the NTAG 12C slave address code SA 7 bits with the Read Write bit RW reset to 0 The NTAG 12C acknowledges this A and waits for one address byte MEMA which should correspond to the address of the block of memory SRAM or EEPROM that is intended to be writ
27. situation will trigger a reset of the I2C interface and hence may hamper the communication via the 12C interface Acknowledge bit ACK The acknowledge bit is used to indicate a successful byte transfer The bus transmitter whether it is the bus master or slave device releases Serial Data SDA after sending eight bits of data During the 9th clock pulse period the receiver pulls Serial Data SDA low to acknowledge the receipt of the eight data bits Data input During data input the NTAG 12C samples SDA on the rising edge of SCL For correct device operation SDA must be stable during the rising edge of SCL and the SDA signal must change only when SCL is driven low Addressing To start communication between a bus master and the NTAG I C slave device the bus master must initiate a Start condition Following this initiation the bus master sends the device address The NTAG I C address from 12C consists of a 7 bit device identifier see Table 15 for default value The 8th bit is the Read Write bit RW This bit is set to 1 for Read and 0 for Write operations If a match occurs on the device address the NTAG 12C gives an acknowledgment on SDA during the 9th bit time If the NTAG 12C does not match the device select code it deselects itself from the bus and clear the register 2C_LOCKED see Table 12 Table 15 Default NTAG I C address from I2C Device address R W b7 b6 b5 b4 b3 b2
28. such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof NT3H1101 1201 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for us
29. to EOh and E8h sector 1 for NTAG I C 2k e SRAM buffer address when Pass through mode is enabled Addressing a start memory page beyond the limits above results in a NAK response from NTAG I2C In case a READ command addressing start with a valid memory area but extends over an invalid memory area the content of the invalid memory area will be reported as OOh FAST_READ The FAST_READ command requires a start page address and an end page address and returns all n 4 bytes of the addressed pages For example if the start address is 03h and the end address is 07h then pages 03h 04h 05h 06h and O7h are returned For details on those cases and the command structure refer to Figure 21 and Table 25 Table 26 shows the required timing All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 43 of 65 NXP Semiconductors NT3H1101 NT3H1201 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface i 453 us wl TACK depending on nr of read pages NTAG NAK NAK E TNAK 57 ps Time out TTimeOut aaa 006989 Fig 21 FAST_READ command Table 25 FAST READ command Name Code Description Length Cmd 3Ah read multiple pages 1 byte StartAddr start page address 1 byte EndAddr end page address 1 byte CRC CRC according to
30. to bit 7 GET_VERSION The GET_VERSION command is used to retrieve information about the NTAG family the product version storage size and other product data required to identify the specific NTAG 12C This command is also available on other NTAG products to have a common way of identifying products across platforms and evolution steps The GET_VERSION command has no arguments and returns the version information for the specific NTAG 12C type The command structure is shown in Figure 19 and Table 20 Table 21 shows the required timing NFC device Cmd CRC NTAG ACK CRC 283 us Tack I 868 us a NTAG NAK NAK I TNAK 57 us Time out Timeout aaa 006987 Fig 19 GET_VERSION command Table 20 GET_VERSION command Name Code Description Length Cmd 60h Get product version 1 byte CRC CRC according to Ref 1 2 bytes Data Product version information 8 bytes NAK see Table 17 see Section 10 3 4 bit Table 21 GET_VERSION timing These times exclude the end of communication of the NFC device Tacknak min Tack nak max TTimeout GET_VERSION n 9l1 TTimeout 5 ms 1 Refer to Section 10 2 Timing All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 41 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201
31. which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 18 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of
32. 10 6 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 22 GET_VERSION response for NTAG I C 1k and 2k Byte no Description NTAG I C 1k NTAG C 2k Interpretation 0 fixed Header 00h 00h 1 vendor ID 04h 04h NXP Semiconductors 2 product type 04h 04h NTAG 3 product subtype 05h 05h 50 pF 12C Field detection 4 major product version 02h 02h 2 5 minor product version Oth Oth V1 6 storage size 13h 15h see following information 7 protocol type 03h 03h ISO IEC 14443 3 compliant The most significant 7 bits of the storage size byte are interpreted as an unsigned integer value n As a result it codes the total available user memory size as 2 If the least significant bit is Ob the user memory size is exactly 2 If the least significant bit is 1b the user memory size is between 2 and 2 The user memory for NTAG I C 1k is 888 bytes This memory size is between 512 bytes and 1024 bytes Therefore the most significant 7 bits of the value 13h are interpreted as 9d and the least significant bit is 1b The user memory for NTAG I C 2k is 1904 bytes This memory size is between 1024 bytes and 2048 bytes Therefore the most significant 7 bits of the value 15h are interpreted as 10d and the least significant bit is 1b READ The READ command requires a start page address and returns the 16 bytes of four NTAG I C pages For example if address Addr is 03h then pa
33. 2 byte SAK Prei 7 bytes UID ATQAO ATQA1 lock bytes aaa 012802 Fig 6 UID serial number 8 3 6 Static lock bytes NT3H1101 1201 The bits of byte 2 and byte 3 of page 02h via RF or byte 10 and 11 address Oh via I2C represent the field programmable read only locking mechanism see Figure 7 Each page from 03h CC to OFh can be individually locked by setting the corresponding locking bit Lx to logic 1 to prevent further write access After locking the corresponding page becomes read only memory The three least significant bits of lock byte 0 are the block locking bits Bit 2 controls pages OAh to OFh via RF bit 1 controls pages 04h to 09h via RF and bit 0 controls page 03h CC Once the block locking bits are set the locking configuration for the corresponding memory area is frozen MSB LSB MSB LSB L L L L L BL BL BL L L L L L L L E 7 6 5 4 CC 15 10 9 4 CC 15 14 13 12 11 10 9 8 o2 ee puga lock byte 0 Lx locks page x to read only lock byte 1 BLx blocks further locking for the memory area x aaa 006983 _ Fig 7 Static lock bytes 0 and 1 For example if BL15 10 is set to logic 1 then bits L15 to L10 lock byte 1 bit 7 2 can no longer be changed The static locking and block locking bits are set by the bytes 2 and 3 of the WRITE command to page 02h The contents of the lock bytes are bit wise OR ed and the result then becomes the new content of the lock bytes This process is
34. 3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 14 Package outline XQFN8 plastic extremely thin quad flat package no leads 8 terminals body 1 6 x 1 6 x 0 5 mm SOT902 3 lt D T B JA A terminal 1 index area A E Ai mml oO t detail X Y C A B lem er terminal 1 index area metal area not for soldering m Dimensions scale Unit A Ai b D E e e1 L v w y y1 max 0 5 0 05 0 25 1 65 1 65 0 45 mm nom 0 20 1 60 1 60 0 6 05 0 40 0 1 0 05 0 05 0 05 min 0 00 0 15 1 55 1 55 0 35 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included sot902 3_po References Outline European Issue date version IEC JEDEC JEITA projection SOT902 3 aie MO 255 E 11 08 18 Fig 26 Package outline SOT902 3 XQFN8 NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 59 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface TSSOP8 plastic thin shrink small outline package 8 leads body width 3 mm SOT505 1
35. C 265433 6 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NT3H1101 1201 7 2 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Pin description Table 3 Pin description for XQFN8 and TSSOP8 Pin Symbol Description 1 LA Antenna connection LA 2 VSS GND 3 SCL Serial Clock 12C 4 FD Field detection 5 SDA Serial data 1 C 6 VCC VCC in connection external power supply 7 VOUT Voltage out energy harvesting 8 LB Antenna connection LB NXP recommends leaving the central pad of the XQFN8 package unconnected All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 7 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 8 Functional description 8 1 Block description NTAG IC ICs consist of see details below 2016 bytes of EEPROM memory 64 Bytes of SRAM a PF interface Digital Control Unit DCU Power Management Unit PMU and an I C interface Energy and data are transferred via an antenna consisting of a coil with a few turns which is directly connected to NTAG I C IC e RF interface modulator demodulator rectifier clock regenerator Power On Reset POR voltage regulator Anticollision multiple cards may be selected and managed in s
36. NTAG 12C transits to the HALT state Any other data received when the device is in this state is interpreted as an error Depending on its previous state the NTAG 12C returns to either to the IDLE state or HALT state HALT state HALT and IDLE states constitute the two wait states implemented in the NTAG I C An already processed NTAG I C can be set into the HALT state using the HLTA command In the anticollision phase this state helps the NFC device distinguish between processed tags and tags yet to be selected The NTAG 12C can only exit this state upon execution of the WUPA command Any other data received when the device is in this state is interpreted as an error and NTAG I C state remains unchanged Memory organization The memory map is detailed in Table 4 1k memory and Table 5 2k memory from the RF interface and in Table 6 1k memory and Table 7 2k memory from the 12C interface The SRAM memory is not mapped from the RF interface because in the default settings of the NTAG 12C the Pass through mode is not enabled Please refer to Section 11 for examples of memory map from the RF interface with SRAM mapping The structure of manufacturing data static lock bytes capability container and user memory pages except of the user memory length are compatible with other NTAG products Any memory access which starts at a valid address and extends into an invalid access region will return 00h value in the invalid region Memory map
37. Ob 0 TRANSFER_DIR R amp W R amp W 1b defines the data flow direction for the data transfer Ob From C to RF interface 1b From RF to C interface In case the Pass through mode is not enabled Ob no WRITE access from the RF side NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 23 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 13 _ continuedConfiguration bytes Bit Field Access Access Default Description via RF via PC values Configuration register LAST _NDEF_BLOCK 7 0 LAST_NDEF_BLOCK R amp W R amp W 00h Address of last BLOCK 16bytes of NDEF message from I C addressing An RF read of the last page of the 12C block specified by LAST_NDEF_BLOCK sets the register NDEF_DATA_READ to 1b and triggers FD_OFF if FD_OFF is set to 10b Oth is page 04h first page of the User Memory from RF addressing 02h is page 08h 03h is page OCh 37h is page DCh memory sector 0 last possible page of User memory for NTAG C 1k 77h is page DCh memory sector 1 last page possible of the User Memory for NTAG I C 2k Configuration register SRAM_MIRROR_BLOCK 7 0 SRAM_MIRROR_ R amp W R amp W F8h Address of first BLOCK 16bytes of S
38. POWER MANAGEMENT ENERGY HARVESTING DIGITAL CONTROL UNIT MEMORY RF ARBITER STATUS INTERFACE REGISTERS ANTICOLLISION 12C CONTROL COMMAND INTERPRETER MEMORY INTERFACE EEPROM Block diagram aaa 010358 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 5 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 7 Pinning information 7 1 Pinning 7 1 1 XQFN8 A LB 8 LA J1 7 VOUT A VSS 2 6 VCC scL 3 5 SDA 4 Yo FD Transparent top view side view aaa 010359 1 Dimension A 1 6 mm 2 Dimension B 0 5 mm Fig 3 Pin configuration for XQFN8 7 1 2 TSSOP8 r ST LA i 8 LB VSS 2 7 VOUT B SCL 3 6 VCC FD 4 5 SDA LIT J a A gt i C Transparent top view Side view aaa 017246 1 Dimension A 5 1 mm 2 Dimension B 3 1 mm 3 Dimension C 1 1 mm Fig 4 Pin configuration for TSSOP8 NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLI
39. RAM BLOCK buffer when mirrored into the User memory from lC addressing Oth is page 04h first page of the User Memory from RF addressing 02h is page 08h 03h is page OCh 34h is page DOh memory sector 0 last possible page of User memory for NTAG I C 1k 74h is page DOh memory sector 1 last page possible of the User Memory for NTAG I C 2k Configuration register WDT_LS 7 0 WDT_LS R amp W R amp W 48h Least Significant byte of watchdog time control register NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 24 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 13 _ continuedConfiguration bytes Bit Field Access Access Default Description via RF via PC values Configuration register WDT_MS 7 0 WDT_MS R amp W R amp W 08h Most Significant byte of watchdog time control register When writing WDT_MS byte the content of WDT_MS and WDT_LS gets active for the watchdog timer Configuration register 12C_CLOCK_STR 7 1 RFU READ READ 0 0b reserved for future use all 7 bits locked to Ob I2C_CLOCK_STR R amp W R amp W 1b Enables 1b or disable Ob the I C clock stretching Configuration register REG_LOCK 7 2 RFU READ READ 000000b reserved for future use
40. Ref 1 2 bytes Data data content of the addressed pages n 4 bytes NAK see Table 17 see Section 10 3 4 bit Table 26 FAST_READ timing These times exclude the end of communication of the NFC device Tacknak max Timeout TTimeOut 5 ms Tack nak Min FAST_READ n 9l 1 Refer to Section 10 2 Timing In the initial state of NTAG I2C all memory pages are allowed as StartAddr parameter to the FAST_ READ command e Page address from 00h to E2h and E8h for NTAG I C 1k e Page address from 00h to FFh sector 0 from page 00h to EOh and E8h sector 1 for NTAG I C 2k e SRAM buffer address when Pass through mode is enabled If the start addressed memory page StartAddr is outside of accessible area NTAG 12C replies a NAK In case the FAST_READ command starts with a valid memory area but extends over an invalid memory area the content of the invalid memory area will be reported as OOh The EndAddr parameter must be equal to or higher than the StartAddr Remark The FAST_READ command is able to read out the entire memory of one sector with one command Nevertheless the receive buffer of the NFC device must be able to handle the requested amount of data as no chaining is possible All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 44 of 65
41. YUM Bey z edAy Hunsansey ABsouz O21 DVLN LOC LHELN LOLLHELN SJOJONPUODIWIIS dXN NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface For the READ register operation following a Start condition the bus master host sends the NTAG I C slave address code SA 7 bits with the Read Write bit RW reset to 0 The NTAG 12C acknowledges this A and waits for one address byte MEMA which corresponds to the address of the block of memory with the session register bytes FEh The NTAG 12C responds to the address byte with an acknowledge A Then the bus master host issues a register address REGA which corresponds to the address of the targeted byte inside the block FEh 00h 01h to 07h and then waits for the Stop condition Then the bus master host again issues a start condition followed by the NTAG I C slave address with the Read Write bit set to 1b The NTAG I C acknowledges this A and sends the selected byte of session register data REGDAT within the block FEh The bus master host will acknowledge it and issue a Stop condition For the WRITE register operation following a Start condition the bus master host sends the NTAG I C slave address code SA 7 bits with the Read Write bit RW reset to 0 The NTAG I C acknowledges this A and waits for one address byte MEMA which corresponds to the address of the block of memory within the session register bytes FEh After th
42. age address specified in SRAM_MIRROR_BLOCK byte Table 13 and Table 14 See Table 31 NTAG I C 1k and Table 32 NTAG I C 2k for an illustration of this SRAM memory mapping when SRAM_MIRROR_BLOCK is set to 01h The SRAM buffer will be then available in two locations inside the user memory and at the end of the first or second memory sector respectively NTAG I C 1k or NTAG I C 2k The tag must be VCC powered to make this mode work because without VCC the SRAM will not be accessible via RF powered only When mapping the SRAM buffer to the user memory the user shall be aware that all data written into the SRAM part of the user memory will be lost once the NTAG I C is no longer powered from the I C side as SRAM is a volatile memory NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 49 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 31 Illustration of the SRAM memory addressing via the RF interface with SRAM_MIRROR_ON_OFF set to 1b and SRAM_MIRROR_BLOCK set to 01h for the NTAG I2C 1k Sector Page address Byte number within a page Access address Dec Hex 1 2 3 conditions 0 0 00h Serial
43. aimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 14 of 65 NXP Semiconductors NT3H1101 NT3H1201 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 7 NTAG I2C 2k memory organization from the I C interface Byte number within a block I2C block 0 1 2 3 address 4 5 6 7 Access conditions 8 9 10 11 Dec Hex 12 13 14 15 0 00h 12C adar Serial number R amp W READ Serial number Internal READ Internal Static lock bytes READ R amp W Capability Container CC READ amp WRITE 1 Oth a saN User memory READ amp WRITE 119 77h 120 78h Dynamic lock bytes 00h READ amp WRITE 00h 00h 00h 00h 00h 00h 00h 00h READ 00h 00h 00h 00h 121 79h Invalid access returns NAK n a 122 7Ah Configuration registers see 8 3 11 00h 00h 00h 00h READ 00h 00h 00h 00h 127 7Bh os is Invalid access returns NAK n a 247 F7h 248 F8h Me SRAM memory 64 bytes READ amp WRITE 251 FBh sh Invalid access returns NAK n a 254 FEh Session registers sotii requires READ register command 00h 00h 00h 00h READ 00h 00h 00h 00h Invalid access returns NAK n a Remark The byte 0 of block 0 is always read as 04h Writing to this byte modifies the 1 C address All information pro
44. ame length for FAST READ is up to 9235 bits 1024 data bytes 2 CRC bytes 1024 x 9 2 x 9 1 start bit but here the maximum frame length supported by the NFC device must be taken into account when issuing this command NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 8 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 8 2 1 NT3H1101 1201 NTAG I7C Energy harvesting Type 2 Tag with I2C interface For a multi byte parameter the least significant byte is always transmitted first For example when reading from the memory using the READ command byte 0 from the addressed block is transmitted first followed by bytes 1 to byte 3 out of this block The same sequence continues for the next block and all subsequent blocks Data integrity The following mechanisms are implemented in the contactless communication link between the NFC device and the NTAG I C IC to ensure very reliable data transmission 16 bits CRC per block Parity bits for each byte Bit count checking Bit coding to distinguish between 1 O and no information Channel monitoring protocol sequence and bit stream analysis The commands are initiated by the NFC device and controlled by the Digital Control Unit of the NTAG 12C IC The command response depends on the state of the IC and f
45. and the other as the slave device A data transfer can only be initiated by the bus master which will also provide the serial clock for synchronization The NTAG I C is always a slave in all communications Start condition Start is identified by a falling edge of Serial Data SDA while Serial Clock SCL is stable in the high state A Start condition must precede any data transfer command The NTAG 12C continuously monitors SDA except during a Write cycle and SCL for a Start condition and will not respond unless one is given Stop condition Stop is identified by a rising edge of SDA while SCL is stable and driven high A Stop condition terminates communication between the NTAG 12C and the bus master A Stop condition at the end of a Write command triggers the internal Write cycle All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 33 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 9 3 9 4 9 5 9 6 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Soft reset feature In the case where the 12C interface is constantly powered on NTAG 12C can trigger a reset of the 12C interface via its soft reset feature see Table 13 When this feature is enabled if the microcontroller does not issue a stop condition between two start conditions this
46. apped directly at the end of the sector 0 NTAG I C 1k or sector 1 NTAG 12C 2k of the memory from the RF interface perspective In both cases the principle of access to the SRAM buffer via the RF and I C interface is exactly the same see Section 11 3 2 and Section 11 3 3 The data flow direction must be set with the PTHRU_DIR bit see Table 14 within the current communication session with the session registers in this case it can only be set via the l C interfaces or for the configuration bits after POR in this case both RF and I2C interface can set it This Pass through direction settings avoids locking the memory access during the data transfer from one interface to the SRAM buffer The Pass through mode can only be enabled via I C interface when both interfaces are powered The PTHRU_ON_OFF bit located in the session registers NC_REG see Section 8 3 11 needs to be set to 1b In case one interface powers off the Pass through mode is disabled automatically SRAM buffer mapping In Pass through mode the SRAM is mirrored to pages FOh to FFh sector 0 for the NTAG l2C 1k see Table 33 or sector 1 for the NTAG I C 2k see Table 34 outside the user memory The last page block of the SRAM buffer page 16 is used as the terminator page Once the terminator page block in the respective interfaces is read written the control would be transferred to other interface RF I C see Section 11 3 2 and Section 11 3 3 for more de
47. atchdog timer expires the communication will continue until the communication has completed Then the status register I2C_LOCKED will be immediately cleared In the case where the communication with the I2C interface has completed before the end of the timer and the status register 12C_LOCKED was not cleared by the host it will be cleared at the end of the watchdog timer The watchdog timer is only effective if the VCC pin is powered and will be reset and stopped if the NTAG 12C is not VCC powered or if the register status 12C_LOCKED is set to Ob and RF_LOCKED is set to 1b 8 6 Energy harvesting The NTAG IC provides the capability to supply external low power devices with energy generated from the RF field of a NFC device The voltage and current from the energy harvesting depend on various parameters such as the strength of the RF field the tag antenna size or the distance from the NFC device At room temperature NTAG 12C could provide typically 5 mA at 2 V on the VOUT pin with an NFC Phone Operating NTAG 12C in energy harvesting mode requires a number of precautions e A significant capacitor is needed to guarantee operation during RF communication The total capacitor between VOUT and GND shall be in the range of 150nF to 200 nF e If NTAG I2C also powers the I2C bus then VCC must be connected to VOUT and pull up resistors on the SCL and SDA pins must be sized to control SCL and SDA sink current when those lines are pulled low
48. b1 bO Value 101 oL 10 oM 10 onl 101 1 0 1 Initial values can be changed The 1 C address of the NTAG I C byte 0 block Oh can only be modified by the 12C interface Both interfaces have no READ access to this address and a READ command from the RF or I C interface to this byte will only return 04h manufacturer ID for NXP Semiconductors see Figure 6 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 34 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG I C Energy harvesting Type 2 Tag with I C interface aaa 012811 Stop D15 ti BE EE E y E alee ai ieee ees vy Be D1 D15 R 7 St eer ee ee a I ea Start 7 bits SA and 1 MEMA 12C READ and WRITE operation 9 7 READ and WRITE Operation Write Host Start 7 bits SA and 0 Read Host Start 7 bits SA and 0 D D oO oO a o r D me NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 35 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface The READ and WRITE operation handle always 16 bytes to be read or written
49. by NTAG 2C or the 12C host e If NTAG I C also powers the Field Detect bus then the pull up resistor on the Field Detect line must be sized to control the sink current into the Field Detect pin when NTAG 12C pulls it low The NFC reader device communicating with NTAG 12C shall apply polling cycles including an RF Field Off condition of at least 5 1 ms as defined in NFC Forum Activity specification see Ref 4 chapter 6 Note that increasing the output current on the Vout decreases the RF communication range NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 32 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 9 PC commands NT3H1101 1201 9 1 9 2 For details about 12C interface refer to Ref 3 SCL SDA Start m SDA gt SDA gt Stop Condition Input Change Condition 7 8 9 ACK Start Condition SCL SDA Stop Condition 001aa0231 Fig 15 1 C bus protocol The NTAG I C supports the I2C protocol This protocol is summarized in Figure 15 Any device that sends data onto the bus is defined as a transmitter and any device that reads the data from the bus is defined as a receiver The device that controls the data transfer is known as the bus master
50. d Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 29 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface ON PF field OFF HIGH FD pin LOW o W on Z g FD_ON 01b 15h ol FD_OFF 01b Zz gt t Lo pot pot pot po l l Is I I l l ke l 2l igsi igb dad T l lz0Ol al gl F iso 123 tot amp l gl kel Event ae 5 ae lms ggl pel ol jesl T gt I D gt a c2 I 3 les 1 l o gt Il 3 l I Jeol l ley 2l l ol l l lol lol l ai asd lasd ja ee aaa 017242 Fig 13 Illustration of the field detection feature when configured for first valid start of communication detection NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 30 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface ON PF field OFF HIGH FD pin LOW o W on Z g FD_ON 10b 29h ol FD_OFF 10b Z gt t Lo pot pot pot po l l Is I I l l ke l 2l igsi igb dad T l lz0Ol al gl F iso 123 tot amp l gl kel Event ae 5 ae lms ggl pel ol jesl T gt I D gt a c2 I 3 les 1 l o gt Il 3 l I Jeol
51. data is written to the terminator page of the SRAM via the I C interface at the end of the WRITE command bit SRAM_RF_READY is set to 1b and bit I2C_LOCKED is automatically reset to Ob to set the tag in the arbitration idle state The RF_LOCKED bit is then automatically set to 1b according to the interface arbitration After a READ or FAST_READ command involving the terminator block page of the SRAM bit SRAM_RF_READY and bit RF_LOCKED are automatically reset to Ob allowing the I C interface to further write data into the SRAM buffer To signal to the host that further data is ready to be written the following mechanisms are in place NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 56 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface e The RF interface polls reads the bit SRAM_RF_READY from NS_REG see Table 14 to know if new data has been written by the I C interface in the SRAM e A trigger on the FD pin indicates to the host that data has been read from SRAM by the RF interface This feature can be enabled by programming bits 5 2 FD_OFF FD_ON of the NC_REG appropriately see Table 13 The above mechanism is illustrated in the Figure 25 NS_REG NC_REG ON RF field OFF HIGH FD pi
52. dge ACK Oh NAK for invalid argument i e invalid page address th NAK for parity or CRC error 3h NAK for Arbiter locked to 1 C 7h NAK for EEPROM write error ATQA and SAK responses NTAG 12C replies to a REQA or WUPA command with the ATQA value shown in Table 18 It replies to a Select CL2 command with the SAK value shown in Table 19 The 2 byte ATQA value is transmitted with the least significant byte first 44h Table 18 ATQA response of the NTAG I2C Bit number Sales type Hex value 16 15 14 13 12 11 10 9 8 7 6 5 4 33 NTAG 12C 00 44h 0 0 0 0 0 0 0 0 0 1 0 0 0O 1 0 0 Table 19 SAK response of the NTAG I2C Bit number Sales type Hex value 8 7 6 5 4 3 2 NTAG 12C 00h 0 0 0 0 0 0 0 0 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 40 of 65 NXP Semiconductors NT3H1101 NT3H1201 10 5 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Remark The ATQA coding in bits 7 and 8 indicate the UID size according to ISO IEC 14443 independent from the settings of the UID usage Remark The bit numbering in the ISO IEC 14443 specification starts with LSB bit 1 and not with LSB bit 0 So 1 byte counts bit 1 to bit 8 instead of bit 0
53. e NTAG I2C acknowledge A the bus master host issues a register address REGA which corresponds to the address of the targeted byte inside the block FEh 00h Oth to 07h After acknowledgement A by NTAG IC the bus master host issues a MASK byte that defines exactly which bits shall be modified by a 1b bit value at the corresponding bit position Following the NTAG I C acknowledge A the new register data one byte REGDAT to be written is transmitted by the bus master host The NTAG 2C acknowledges it A and the bus master host issues a stop condition NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 38 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 10 RF Command 10 1 10 2 NT3H1101 1201 NTAG activation follows the ISO IEC 14443 Type A specification After NTAG I2C has been selected it can either be deactivated using the ISO IEC 14443 HALT command or NTAG commands e g READ or WRITE can be performed For more details about the card activation refer to Ref 2 NTAG 12C command overview All available commands for NTAG 12C are shown in Table 16 Table 16 Command overview Timing Command ISO IEC 14443 NFC FORUM Command code
54. e in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage cos
55. eatures and benefits 2 1 Key features E RF interface NFC Forum Type 2 Tag compliant m C interface BH Configurable field detection pin based on open drain implementation that can be triggered upon the following events RF field presence First start of communication Selection of the tag only E 64 byte SRAM buffer for fast transfer of data Pass through mode between the RF and the 12C interfaces located outside the User Memory E Wake up signal at the field detect pin when New data has arrived from one interface Data has been read by the receiving interface Clear arbitration between RF and I C interfaces First come first serve strategy Status flag bits to signal if one interface is busy writing to or reading data from the EEPROM E Energy harvesting functionality to power external devices e g microcontroller m FAST READ command for faster data reading 2 2 RF interface E Contactless transmission of data E NFC Forum Type 2 Tag compliant see Ref 1 E Operating frequency of 13 56 MHz B Data transfer of 106 kbit s E 4 bytes one page written including all overhead in 4 8 ms via EEPROM or 0 8 ms via SRAM Pass through mode E Data integrity of 16 bit CRC parity bit coding bit counting BH Operating distance of up to 100 mm depending on various parameters such as field strength and antenna geometry True anticollision E Unique 7 byte serial number cascade level 2 according to ISO IEC 14443 3 see
56. equence e Command interpreter processes memory access commands supported by the NTAG 12C e EEPROM interface 8 2 RF interface The RF interface is based on the ISO IEC 14443 Type A standard This RF interface is passive and therefore requires to be supplied by an RF field e g NFC enabled device at all times to be able to operate It is not operating even if the NTAG 12C is powered via its contact interface Vcc Data transmission from the RF interface is only happening if RF field from an NFC enabled device is available and adequate commands are sent to retrieve data from the NTAG 12C For both directions of data communication there is one start bit start of communication at the beginning of each frame Each byte is transmitted with an odd parity bit at the end The LSB of the byte with the lowest address of the selected block is transmitted first The maximum length of an NFC device to tag frame used in this product is 82 bits 7 data bytes 2 CRC bytes 7x9 2x9 1 start bit The maximum length of a tag to NFC device frame response to READ command is 163 bits 16 data bytes 2 CRC bytes 16 x 9 2 x 9 1 start bit In addition the proprietary FAST_READ command has a variable response frame length which depends on the start and end address parameters E g when reading the SRAM at once the length of the response is 595 bits 64 data bytes 2 CRC bytes 64x9 2x9 1 start bit The overall maximum supported response fr
57. eral update 20141009 e Section 8 6 Energy harvesting updated e Section 10 5 GET_VERSION updated e Figure 24 and Figure 25 updated NT3H1101_ 1201 v 3 1 Modifications Product data sheet NT3H1101_ 1201 v 3 0 e Section 12 Limiting values and Section 13 Characteristics remark removed 20140806 NT3H1101_ 1201 v 2 3 e Section 8 6 Energy harvesting updated NT3H1101_ 1201 v 3 0 Modifications Product data sheet e Section 16 References updated e Data sheet status changed to Product data sheet 20140708 e Figures updated e General update NT3H1101_ 1201 v 2 3 Modifications NT3H1201_ 1101 v 2 2 Objective data sheet NT3H1101_ 1201 v 2 2 20140306 Objective data sheet NT3H1201_ 1101 v 2 1 Modifications e General updates NT3H1101_ 1201 v 2 1 20131218 Objective data sheet NT3H1201_ 1101 v 2 0 Modifications e Section 4 Ordering information type number corrected NT3H1101_ 1201 v 2 0 20131212 Objective data sheet NT3H1201 v 1 4 Modifications e Additional description for the Field detection functionality for Pass through mode e General update NT3H1201 v 1 4 20130802 Objective data sheet NT3H1201 v 1 3 Modifications e Update for 1k memory version and RF commands NT3H1201 v 1 3 20130613 Objective data sheet Modifications e Pinning
58. ess via RF Access via lC Default values Description Configuration reg ister NC_REG 7 12C_RST_ON_OFF R amp W R amp W Ob enables soft reset through I C repeated start see Section 9 3 6 RFU READ R amp W Ob reserved for future use keep at Ob 5 FD_OFF R amp W R amp W 00b defines the event upon which the signal output on the FD pin is brought up 00b if the field is switched off 01b if the field is switched off or the tag is set to the HALT state 10b if the field is switched off or the last page of the NDEF message has been read defined in LAST_NDEF_BLOCk 11b if FD_ON 11b if the field is switched off or if last data is read by I C in Pass through mode RF gt 12C or last data is written by 1 C in Pass through mode C gt RF 11b if FD_ON 00b or 01b or 10b if the field is switched off See Section 8 4 for more details 3 FD_ON R amp W R amp W 00b defines the event upon which the signal output on the FD pin is brought down 00b if the field is switched on 01b by first valid start of communication SoC 10b by selection of the tag 11b in Pass through mode RF gt I C if the data is ready to be read from the I C interface 11b in Pass through mode C gt RF if the data is read by the RF interface See Section 8 4for more details 1 RFU READ R amp W Ob reserved for future use keep at
59. first part of the UID 3 bytes using the ANTICOLLISION or SELECT commands in cascade level 1 This state is correctly exited after execution of the following command e SELECT command from cascade level 1 the NFC device switches the NTAG 12C into READY2 state where the second part of the UID is resolved All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 10 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 8 2 2 3 8 2 2 4 8 2 2 5 8 3 8 3 1 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface READY 2 state In the READY 2 state the NTAG I2C supports the NFC device in resolving the second part of its UID 4 bytes with the cascade level 2 ANTICOLLISION command This state is usually exited using the cascade level 2 SELECT command Remark The response of the NTAG 12C to the SELECT command is the Select AcKnowledge SAK byte In accordance with ISO IEC 14443 this byte indicates if the anticollision cascade procedure has finished If finished the NTAG I C is now uniquely selected and only this device will communicate with the NFC device even when other contactless devices are present in the NFC device field ACTIVE state All memory operations are operated in the ACTIVE state The ACTIVE state is exited with the HLTA command and upon reception the
60. ges 03h 04h 05h 06h are returned Special conditions apply if the READ command address is near the end of the accessible memory area For details on those cases and the command structure refer to Figure 20 and Table 23 Table 24 shows the required timing T E 368 us ae ACK all 1548 us NTAG NAK nak T Time out TimeOut aaa 006988 Fig 20 READ command All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 42 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 10 7 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 23 READ command Name Code Description Length Cmd 30h read four pages 1 byte Addr start page address 1 byte CRC CRC according to Ref 1 2 bytes Data Data content of the addressed pages 16 bytes NAK see Table 17 see Section 10 3 4 bit Table 24 READ timing These times exclude the end of communication of the NFC device Tacknak Min Tacknak max TTimeout READ n 9l1 TTimeout 5 ms 1 Refer to Section 10 2 Timing In the initial state of NTAG 12C all memory pages are allowed as Addr parameter to the READ command e Page address from 00h to E2h and E8h for NTAG I C 1k e Page address from 00h to FFh sector 0 from page 00h
61. hanisms include static and dynamic lock bits as well as the locking of the configuration pages All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 45 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 10 9 SECTOR SELECT The SECTOR SELECT command consists of two commands packet the first one is the SECTOR SELECT command C2h FFh and CRC Upon an ACK answer from the Tag the second command packet needs to be issued with the related sector address to be accessed and 3 bytes RFU To successfully access to the requested memory sector the tag shall issue a passive ACK which is sending NO REPLY for more than 1ms after the CRC of the second command set The SECTOR SELECT command is shown in Figure 23 and Table 29 Table 30 shows the required timing NFC device SECTOR SELECT packet 1 ACK NTAG 12C ACK 368 us Tack 57 us NTAG 12C NAK NAK L TNAK 57 us Time out TTimeOut SECTOR SELECT packet 2 NFC device no repl Passive AC NTAG 12C ACK no reply Passive ack 537 us gt ms J NTAG IC NAK any reply NAK lt 1ms 57 Us aaa 014051 Fig 23 SECTOR_SELECT command Table 29 SECTOR_SELECT command Name Code Description Length Cmd C2h
62. hexadecimal Request REQA SENS_REQ 26h 7 bit Wake up WUPA ALL_REQ 52h 7 bit Anticollision CL1 Anticollision CL1 SDD_REQ CL1 93h 20h Select CL1 Select CL1 SEL_REQ CL1 93h 70h Anticollision CL2 Anticollision CL2 SDD_REQ CL2 95h 20h Select CL2 Select CL2 SEL_REQ CL2 95h 70h Halt HLTA SLP_REQ 50h 00h GET_VERSION z 60h READ READ 30h FAST_READ 3Ah WRITE WRITE A2h SECTOR_SELECT SECTOR_SELECT C2h 1 Unless otherwise specified all commands use the coding and framing as described in Ref 1 The command and response timing shown in this document are not to scale and values are rounded to 1 us All given command and response times refer to the data frames including start of communication and end of communication They do not include the encoding like the Miller pulses An NFC device data frame contains the start of communication 1 start bit and the end of communication one logic 0 1 bit length of unmodulated carrier An NFC tag data frame contains the start of communication 1 start bit and the end of communication 1 bit length of no subcarrier The minimum command response time is specified according to Ref 1 as an integer n which specifies the NFC device to NFC tag frame delay time The frame delay time from NFC tag to NFC device is at least 87 us The maximum command response time is specified as a time out value Depending on the command the Tacx value specified for command responses defines
63. hts reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 13 of 65 NXP Semiconductors NT3H1101 NT3H1201 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 6 NTAG I2C 1k memory organization from the I C interface Byte number within a block I2C block 0 1 2 3 address 5 6 7 Access conditions 8 9 10 11 Dec Hex 12 13 14 15 0 00h 12C adar Serial number R amp W READ Serial number Internal READ Internal Static lock bytes READ R amp W Capability Container CC READ amp WRITE 1 Oih sai User memory READ amp WRITE 55 37h 56 38h User memory READ amp WRITE User memory READ amp WRITE Dynamic lock bytes 00h READ amp WRITE 00h 00h 00h 00h READ 57 39h Invalid access returns NAK n a 58 3Ah Configuration registers see 8 3 11 00h 00h 00h 00h READ 00h 00h 00h 00h 59 3Bh os su Invalid access returns NAK n a 247 F7h 248 F8h Me SRAM memory 64 bytes READ amp WRITE 251 FBh sh Invalid access returns NAK n a 254 FEh Session registers sotii requires READ register command 00h 00h 00h 00h READ 00h 00h 00h 00h Invalid access returns NAK n a Remark The byte 0 of block 0 is always read as 04h Writing to this byte modifies the 1 C address All information provided in this document is subject to legal discl
64. in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 19 Contact information Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 18 4 Licenses Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication NFC standards ISO IEC 18092 and ISO IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards 18 5 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus log
65. iption BLOCK Session register SRAM_MIRROR_BLOCK 7 0 SRAM_MIRROR_ READ R amp W see configuration bytes description BLOCK Session register WDT_LS 7 0 WDT_LS READ R amp W see configuration bytes description NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 26 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG I7C Energy harvesting Type 2 Tag with I2C interface Table 14 _ continuedSession register bytes Bit Field Access Access Default Description via RF via PC values Session register WDT_MS 7 0 WDT_MS READ R amp W see configuration bytes description Session register I2C_CLOCK_STR 7 1 RFU READ READ reserved for future use all 7 bits locked to Ob 0 I2C_CLOCK_STR READ READ See configuration bytes description Session register NS_REG 7 NDEF_DATA_READ READ READ Ob 1b all data bytes read from the address specified in LAST_NDEF_BLOCK value is reset to Ob when read 6 12C_LOCKED READ R amp W 0b 1b Memory access is locked to the 12C interface 5 RF_LOCKED READ READ 0b 1b Memory access is locked to the RF interface 4 SRAM_Il2C_READY READ READ Ob 1b data is ready in SRAM buffer to be read by 12C 3 SRAM_RF_READY READ READ 0b 1b data is ready in SRAM buffer to be read by RF 2 EEPROM_WR_ERR READ R amp W 0b 1b
66. irreversible from RF perspective If a bit is set to logic 1 it cannot be changed back to logic 0 From C perspective the bits can be reset to Ob by writing bytes 10 and 11 of block 0 I C address is coded in byte 0 of block 0 and may be changed unintentionally The contents of bytes 0 and 1 of page 02h are unaffected by the corresponding data bytes of the WRITE The default value of the static lock bytes is 00 OOh All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 17 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 8 3 7 Dynamic Lock Bytes To lock the pages of NTAG I C starting at page address 10h and onwards the dynamic lock bytes are used The dynamic lock bytes are located at page E2h sector 0 NTAG I2C 1k or address EOh sector 1 NTAG I2C 2k The three lock bytes cover the memory area of 830 data bytes NTAG I2C 1k or 1846 data bytes NTAG 12C 2k The granularity is 16 pages for NTAG 12C 1k see Figure 8 and 32 pages for NTAG I2C 2k see Figure 9 compared to a single page for the first 48 bytes see Figure 7 Remark Set all bits marked with RFUI to 0 when writing to the dynamic lock bytes LOCK PAGE 128 143 LOCK PAGE 112 127 LOCK PAGE 96 111 LOCK PAGE 80 95 LOCK PAGE 64 79 LOCK PAGE 48 63
67. it values are stored in the EEPROM and represent the default settings to be effective after POR Their values can be read amp written by both interfaces when applicable and when not locked by the register lock bits see REG_LOCK in Table 13 Table 10 Configuration registers NTAG I C 1k RF address 12C Address Byte number sector 0 Dec Hex Dec Hex 0 1 2 3 232 E8h 58 3Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_ WDT_LS BLOCK 233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixed NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 21 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 11 Configuration registers NTAG I C 2k RF address 12C Address Byte number sector 1 Dec Hex Dec Hex 0 1 2 3 232 E8h 122 7Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_ WDT_LS BLOCK 233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixed The session registers Pages F8h to F9h sector 3 via the RF interface or block FEh via 12C see Table 12 are used to configure or monitor the values of the current communication session Those bits can only be read via the RF interface but both read and written via the 12C interface Table 12 Session registers NTAG I C 1k and 2k
68. mers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 12 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 5 NTAG I2C 2k memory organization from the RF interface Sector Page address Byte number within a page Access address Dec Hex 0 1 2 3 conditions 0 0 00h Serial number READ 1 Oth Serial number Internal READ 2 02h Internal Static lock bytes READ R amp W 3 03h Capability Container CC READ amp WRITE 4 04h 15 OFh 255 FFh User memory READ amp WRITE 1 0 1 223 DFh 224 EOh Dynamic lock bytes 00h R amp W READ 225 Eth 226 E2h 227 E3h 228 E4h Invalid access returns NAK n a 229 E5h 230 E6h 231 E7h 232 E8h Configuration registers see 8 3 11 233 E9h 234 EAh eet Invalid access returns NAK n a 255 FFh 2 e aa Invalid access returns NAK n a 3 0 00h Invalid access returns NAK n a 248 F8h Session registers see 8 3 11 249 F9h Invalid access returns NAK n a 255 FFh 8 3 2 Memory map from l C interface The memory access of NTAG IC from the IC interface is organized in blocks of 16 bytes each NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rig
69. n LOW l2C_LOCKED fo RF_LOCKED i SRAM_RF_READY RF_FIELD_ PRESENT PTHRU_ON_OFF 0b FD_ON 11b FD_OFF 11b SRAM MIRROR_ON_OFF 0b 2C 7Ch aan PTHRU_DIR 1b t Coot ye oie a ig kee ae 1S leg Iggg loul lp I l let lea 18 Pe Y Igu l 1 o 15s 1223 1S gt lec ig Event 132 las igs EE ISh I 6 180 189 I2 IZ Ig iji lagzi logi y l s 13i jo IXS IZo l i cel 781 pal 1 Juke l Eo I7 l Z I oe ee a d don ices i more data available aaa 017245 Fig 25 Illustration of the Field detection signal feature in combination with Pass through mode for data transfer from I C to RF NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 57 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 12 Limiting values Exceeding the limits of one or more values in reference may cause permanent damage to the device Exposure to limiting values for extended periods may affect device reliability Table 35 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 2IS
70. o is a trademark of NXP Semiconductors N V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 64 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 20 Contents 2 9 1 9 2 General description 0000e00s 1 Features and benefits 00 0eeeee 2 Key features 0 0 00 e eee eee 2 RF interface 000 eee aes 2 MEMON iaasa sarea aaa derek we 2 2C interface 2 2 eee eee eee eee 3 SOCUMIYsc 54 Piece hed eRe Dae tee 3 Key benefits 2 0000000 eee 3 Applications 00 eee eee 3 Ordering information 0 0 0005 4 MarKING viii iia sien diees eee teed Lams 4 Block diagram 00 ces e eee eee 5 Pinning information 0 00ee eee 6 PINNING eigene s pia sodden hae eee 6 XGENG eriei att a o e anaras 6 TSSOP rura ea a E the ak A Sack 6 Pin description 0000055 7 Functional description 0 00eees 8 Block description 20 0008s 8 PF interface 02000 eee eee 8 Data integrity 0 2 eee eee eee 9 RF communication principle
71. ons Acronym Description POR Power On Reset NT3H1101 1201 1 NFC Forum Type 2 Tag Operation V1 2 Technical Specification 2 ISO IEC 14448 Identification cards Contactless integrated circuit cards Proximity cards International Standard 3 l2C bus specification and user manual NXP standard UM10204 4 NFC Forum Activity V1 1 Technical Specification All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 61 of 65 NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface NXP Semiconductors 17 Revision history Table 39 Document ID NT3H1101_ 1201 v 3 3 Modifications Revision history Release date Data sheet status 20150715 e Table 1 Ordering information updated Change notice Supersedes NT3H1101_ 1201 v 3 2 Product data sheet e Capacitor value for energy harvesting corrected e Table 35 Limiting values updated e Table 36 Characteristics updated 20150325 e Table 1 Ordering information updated NT3H1101_ 1201 v 3 2 Modifications Product data sheet NT3H1101_ 1201 v 3 1 e Table 2 Marking codes updated e Section 7 1 Figure 4 added e Section 14 Package outline Figure 27 added e Gen
72. or memory operations also on the access conditions valid for the corresponding page All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 9 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG I7C Energy harvesting Type 2 Tag with I2C interface 8 2 2 RF communication principle 8 2 2 1 8 2 2 2 NT3H1101 1201 m oe REQA NS identification ra and selection procedure wi O 1 ANTICOLLISION HLTA SELECT cascade level 1 AA READY 2 ANTICOLLISION SELECT T cascade level 2 memory operations ACTIVE READ 16 Byte i FAST_READ WRITE SECTOR_SELECT GET_VERSION Y aaa 012797 Fig 5 RF communication principle of NTAG I2C The overall RF communication principle is summarized in Figure 5 IDLE state After a power on reset POR the NTAG I C switches to the IDLE state It only exits this state when a REQA or a WUPA command is received from the NFC device Any other data received while in this state is interpreted as an error and the NTAG I C remains in the IDLE state After a correctly executed HLTA command e g out of the ACTIVE state the default waiting state changes from the IDLE state to the HALT state This state can then only be exited with a WUPA command READY 1 state In the READY 1 state the NFC device resolves the
73. package update NT3H1201 v 1 0 NT3H1201 v 1 0 20130425 Objective data sheet NT3H1101 1201 All information provided in this document is subject to legal disclaimers Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 NXP Semiconductors N V 2015 All rights reserved 62 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 18 Legal information 18 1 Data sheet status Document status I 2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 18 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval
74. plying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 63 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document and as such is not complete exhaustive or legally binding Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products
75. rated in Figure 12 Figure 13 and Figure 14 for all various combination of the filed detection signal configuration The field detection pin can also be used as a handshake mechanism in the Pass through mode to signal to the external microcontroller if e New data are written to SRAM on the RF interface e Data written to SRAM from the microcontroller are read via the RF interface See Section 11 for more information on this handshake mechanism All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 28 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface ON PF field OFF HIGH FD pin LOW o W on Z D FD_ON 00b Oth ol FD_OFF 00b Z gt t Lo pot pot pot po l l Is I I l l ke l 2l igsi igb dad T l lz0Ol al gl F iso 123 tot amp l gl kel Event ae 5 ae ims ggl pel ol jesl T gt I D gt a c2 I 3 les 1 l o gt Il 3 l I Jeol l ley 2l l ol l l lol lol l zi ee lasd jat ee aaa 017239 Fig 12 Illustration of the field detection feature when configured for simple field detection NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserve
76. sector select 1 byte FFh 1 byte CRC CRC according to Ref 1 2 bytes SecNo Memory sector to be selected 1 byte OOh FEh NAK see Table 17 see Section 10 3 4 bit NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 46 of 65 NXP Semiconductors NT3H1101 NT3H1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Table 30 SECTOR_SELECT timing These times exclude the end of communication of the NFC device Tack nak Min Tack nak Max TTimeout SECTOR SELECT n 9l TtimeOut 10 ms 1 Refer to Section 10 2 Timing NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 47 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface 11 Communication and arbitration between RF and l2C interface If both interfaces are powered by their corresponding source only one interface shall have access according to the first come first serve principle In NS_REG the two status bits I2C_LOCKED and RF_LOCKED reflect the status of the NTAG l C memory access and indicate which interface is locking the memory access At power on both bi
77. t to 1b if the tag receives a valid command EEPROM Access Commands on the RF interface If RF_LOCKED 1b the tag is locked to the RF interface and will not respond to any command from the I C interface other than READ register command see Table 14 RF_LOCKED is automatically set to Ob in one of the following conditions e At POR or if the RF field is switched off e Ifthe tag is set to the HALT state with a HALT command on the RF interface e Ifthe memory access command is finished on the RF interface When the RF interface has read the last page of the NDEF message specified in LAST_NDEF_BLOCK see Table 13 and Table 14 the bit NDEF_DATA_READ in the register NS_REG see Table 14 is set to 1b and indicates to the I C interface that for example new NDEF data can be written NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 48 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 NTAG I7C Energy harvesting Type 2 Tag with I2C interface 11 2 SRAM buffer mapping with Memory Mirror enabled With SRAM_MIRROR_ON_OFF 1b the SRAM buffer mirroring is enabled This mode cannot be combined with the Pass through mode see Section 11 3 With the memory mirror enabled the SRAM is now mapped into the user memory from the RF interface perspective using the SRAM mirror lower p
78. tails Accordingly the application can align on the Reader amp Host side to transfer 16 32 48 64 bytes of data in one Pass through step by only using the last blocks page of the SRAM buffer When using FAST_READ to read the SRAM buffer from RF the EndAddr input of the FAST_READ command has to be always set to FFh All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 52 of 65 NXP Semiconductors NT3H1101 NT3H1201 Table 33 NTAG 12C Energy harvesting Type 2 Tag with I2C interface Illustration of the SRAM memory addressing via the RF interface in Pass through mode PTHRU_ON_OFF set to 1b for the NTAG 12C 1k Sector Page address Byte number within a page Access address Dec Hex 1 2 3 conditions 0 0 00h Serial number READ 1 Oth Serial number Internal READ 2 02h Internal Static lock bytes READ R amp W 3 03h Capability Container CC READ amp WRITE 4 04h 15 OFh User memory READ amp WRITE 225 Eth 226 E2h Dynamic lock bytes 00h R amp W READ 227 E3h 228 E4h 229 E5h Invalid access returns NAK n a 230 E6h 231 E7h 232 E8h f i Configuration registers see 8 3 11 233 E9h 234 EAh Invalid access returns NAK n a 240 FOh re SRAM memory 16 pages READ amp WRITE
79. ten The NTAG I C responds to a valid address byte with an acknowledge A and in the case of a WRITE operation the bus master host starts transmitting each 16 bytes DO D15 that shall be written at the specified address with an acknowledge of the NTAG I C after each byte A After the last byte acknowledge from the NTAG I2C the bus master host issues a Stop condition The memory address accessible via the READ and WRITE operations can only correspond to the EEPROM or SRAM respectively 00h to 3Ah or F8h to FBh for NTAG l2C 1k and 00h to 7Ah or F8h to FBh for NTAG I C 2k NT3H1101 1201 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 3 3 15 July 2015 COMPANY PUBLIC 265433 36 of 65 9IT18Nd ANVdNOD J ays Lep jONpoldg eersoc Slog Aine GL ney SJOWUIE OSIP eba 0 JOaIqNs S JUBWINDOP SI UI PEPIAOI UONEUOJU y G9 JO ZE LOZL LOLLHELN pamasa S YBU Ily S LOZ AN S1O ONPUDDIWES XN 9 8 WRITE and READ register operation In order to modify or read the session register bytes see Table 14 NTAG I C requires the WRITE and READ register operation see Figure 17 Host Tag Host Tag Fig 17 Write 7 bits SA and 0 MEMA REGA MASK REGDAT Read 7bisSAand0 MEWA REGA 7s SA and WRITE and READ register operation REGDAT aaa 012812 98 J19 U Oz
80. the NFC device to NFC tag frame delay time It does it for either the 4 bit ACK value specified or for a data frame All timing can be measured according to the ISO IEC 14443 3 frame specification as shown for the Frame Delay Time in Figure 18 For more details refer to Ref 2 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 39 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 10 3 10 4 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface last data bit transmitted by the NFC device first modulation of the NFC TAG FDT n 128 84 fc ie gt a 128 fc 256 fc 128 fc logic 1 end of communication E start of communication S FDT n 128 20 fc ad ae 7 I I isal a ele gt 128 fc 256 fc 128 fc logic 0 end of communication E start of communication S aaa 006986 Fig 18 Frame Delay Time from NFC device to NFC tag Tacx and Tyak Remark Due to the coding of commands the measured timings usually excludes a part of the end of communication Consider this factor when comparing the specified with the measured times NTAG ACK and NAK NTAG uses a 4 bit ACK NAK as shown in Table 17 Table 17 ACK and NAK values Code 4 bit ACK NAK Ah Acknowle
81. ts are 0 setting the arbitration in idle mode In the case arbiter locks to the I C interface an RF reader still can access the session registers If the ISO state machine is in ACTIVE state only the SECTOR SELECT command is allowed But any other command requiring EEPROM access like READ or WRITE is handled as an illegal command and replied to with a special NAK value In the case where the memory access is locked to the RF interface the I C host still can access the NFC register by issuing a Register READ WRITE command All other read or write commands will be replied to with a NACK to the 12C host 11 1 Non Pass through mode PTHRU_ON_OFF 0b see Table 14 indicates non Pass through mode 11 1 1 C interface access If the tag is in the IDLE or HALT state RF state after POR or HALT command and the correct I C slave address of NTAG I C is specified following the START condition the bit I2C_LOCKED will be automatically set to 1b If l2C_ LOCKED 1b the l C interface has access to the tag memory and the tag will respond with a NACK to any memory READ WRITE command on the RF interface other than reading the register bytes command during this time I2C_LOCKED must be either reset to Ob at the end of the 1 C sequence or wait until the end of the watch dog timer 11 1 2 RF interface access The arbitration will allow the RF interface read and write accesses to EEPROM only when I2C_LOCKED is set to Ob RF_LOCKED is automatically se
82. ts or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to ap
83. vided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet COMPANY PUBLIC Rev 3 3 15 July 2015 265433 15 of 65 NXP Semiconductors NT3H1 1 01 NT3H1 201 8 3 3 8 3 4 8 3 5 NT3H1101 1201 NTAG 12C Energy harvesting Type 2 Tag with I2C interface EEPROM The EEPROM is a non volatile memory that stores the 7 byte UID the memory lock conditions IC configuration information and the 1904 bytes user data 888 byte user data in case of the NTAG I2C 1k version SRAM For frequently changing data a volatile memory of 64 bytes with unlimited endurance is built in The 64 bytes are mapped in a similar way as done in the EEPROM i e 64 bytes are seen as 16 pages of 4 bytes The SRAM is only available if the tag is powered via the VCC pin The SRAM is located at the end of the memory space and it is always directly accessible by the 12C host addresses F8h to FBh An RF reader cannot access the SRAM memory in normal mode i e outside the Pass through mode The SRAM is only accessible by the RF reader if the SRAM is mirrored onto the EEPROM memory space With Memory Mirror enabled GSRAM_MIRROR_ON_OFF 1b see Section 11 2 the SRAM can be mirrored in the User Memory page 1 to page 116 see Section 11 2 for access from the RF side The Memory mirror must be enabled once both interfaces are ON as this feature is disabled after each POR

NT3H1101/NT3H1201 - NXP Semiconductors

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