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SOL-20 System Manual

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1. 0 168 12 lav 92 HSfid SO ZNO O 22 ZNI 369 8 dOd 19 ZNH 09 9 38 28 dWO 88 dWO va dWO 68 dWO 88 vHO 8 vHO 98 VHO S8 vHO 28 vHO 08 VHX VHX 3 OV gy VHX 6Y VHX 8 YNY 9v VNV 5 V V YNY YNY LV YNY Ov 12 2 12 Aquenb 9 yey uoisse1dxe 10 uejsuoo 91 Ig lt 3 lt gt lt lt 885 885 885 885 885 885 885 885 875 gns ans ans 8715 ans ans gns ody QQv dV olaj gov Qav AOW AOW AOW AOW 16 36 Q6 26 86 V6 66 86 46 96 56 v6 26 6 15 06 38 ag 28 88 v8 68 88 48 98 S8 ve 58 c8 18 08 Jg 874 92 V2 64 82 TW QW QN 33 33 971 87 VH IN H HH Wa 13 H3 8 aq AOW LH AOW AOW AON AOW AON AOW AOW AOW AOW AOW AOW AOIN AON AOW AOW AOW
2. AG pain o or U9l you should Measure 0 25 V dC higher A significantly lower reading indicates Clock divrder 390 At pin Ll ort UST vou should measure 1 25 V de Or higher A significantly lower reading indicates a Clock 905 At pin 5 of 0104 you should measure 4 or higher A significantly lower reading indicates a problem with 0104 pan 7 of 0104 you should measure 8 V dc or higher A significantly lower reading indicates a problem with 0104 any voltages are incorrect correct the problem before proceeding if correct turn off the power supply and disconnect the power cable Rev B be ash Sol PC Hev A NN NN NN NN NN NN NN NN NN NN NNN NN NN NN NN OOO PROCESSOR TECHJWLOGY CORPORATION IM SINGLE BOARD TERMINAL COMPUTER SS ee ee gt gt gt e gt SICGIION LI Step 17 Install the following resistors in the indicated Locations insert leads LOCATION RI R2 ed R4 JR Ro JE e R6 Leok R7 ds A R8 LAS R9 R10 LLOR REL EESK R16 R17 JE e ELS Leok R30 ds ER 92 ROL LO R92 200 R83 o R84 SOM R99 Leok R86 Leok R87 330 R88 680 Eo T OE R9
3. 13 14 SUBROUTINES Introduction to the SOLOS Machine Language Interface The Machine Language Interface with SOLOS is based on ie A predefined set of pseudo I O ports allowing software compatibility as well as providing an easy means of supporting any I O device Z5 A system defined register usage when interfacing with SOLOS ow A system jump table of entry points First are the pseudo ports Built into SOLOS are four input and four output pseudo ports requests made to a pseudo port are converted internally to a request either to a specific device a puilt in routine or a user written routines All non tape 170 requests made to SOLOS are made with reference to one of the following pseudo ports PSEUDO PORTO FOR SOLOS Pseudo POTE Input Output Keyboard VDM driver 1 Serial port Serial port 2 Parallel Port Parallel Port 3 User written routine User written routine PSEUDO PORTS EOR CUTER Pseudo POLE Input Output Keyboard data from VDM driver parallel port t Dobb Oy bare 04 il Serial port 1 RDA Serial port 1 IBE Status OI porc DIC posb Uy PLE e 2 Parallel port 2 with noc Parallel port 2 with not PXDR PDR Shot us cor pore Ux Dat DI GU On PORC Up DLC l4 24 gt User written routine User written routine SUBROUTINES Second are the defined register usages when interfacing at the machine language level with SO
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5. 50 6 FEN jz DONI elles o Fen lo Arati dele 1 NOGLIUCH iF Mal be E 3 ny EUR ea m TS EIN EMI INDE E wr tere Snitted character The character is shiite three rows 0 at the top of the font acc R4 at the bortom Figure 8 5 6574 Character Generator ROM pattern C and T were stored in the RAM in the proper character positions in the third character row After the first two character rows have been displayed the Scan Counter U40 is reset to a binary count of 15 1111 and the Character and Line Address Multiplexers U30 U32 and U12 call up the in the Display RAM The Scan Counter output specifies line 15 in the Character Generator ROM on RSI through RS4 As previously mentioned this line in the ROM is blank Thus the first scan line of the third character row i19 The ASCIL code for the CO 1000011 is inp t from the Display RAM to address the Character Generator ROM by way of the Dat Latches U26 and U27 This address is applied to ROM inputs A7 through Al A6 through AO in Figures 8 5 and 8 6 The Scan Counter changes to a count of zero wh
6. Zd Od 23 27 62 9 SSeJppe 91 2 YS 100 809 32 6S 94 X 85 263 M 48 el 9G J4O X 6 n SS 3dVl 21 1 vS NO X H 5 5 HO 26 WHOS 20 gt AS LS 80 35 06 371 as dv 8 1 60 56 N 7738 20 as N 00 2 1 3 8t ge We gt 26 6 3791 1195 gE H 8v 9 Lv de 3c Sv de Oc 2 ep x gc g ev 4 184 33 We v Iv 42 33 6c QH 82 6 6 WO Od Ze 8 8 3 93 9 9c Ze W v3 Sc 9 95 5 63 GE 83 v vt 9 1SH 44 IHO 94 Lz ce MSd Sd ooeds 02 LE dO Oot 0 05 df MSd 13 318V II2SV X3H dH 04 S SH 8g 3892 SHOX JHOd 15 80 INV HSNd Odd 1 158 185 39 NI or 815 2 158 80 INS HSfid ino dOd ONY 15 aq IOV TIVO 22 2r 13H ZH 33 33 Q3 83 v3 63 83 93 53 ra 3 03 39 29 40 ea ea 39 99 83 VO 65 89 80
7. di SNOLLISOG SNAM divo BE BES PC RD EPO RE ee RPE EOC oe CHddHRBHHIIHBHH i TL tren 8 19079 4 4 4 4 4 4 4 4 0001 20000 22000 2 0000 20000 290000 0000 ENDS ABORT E 61001 80001 mo 80110 S010 PJOOIO 100 VIII 27 MAE PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON ALII The BLANK input provides window shade blanking which is analogous to pulling a window shade down from the top of the display PRE BLANK is generated in one half of J K flip flop 043 U43 is re set by the TC output of First Screen Position Counter 011 and set by VDISP The output on pin 7 of 011 is generated by the scrolling Circuitry to be discussed later and defines the character row for which the window shade ends It may begin with any character row from zero through 14 The remaining video blanking function concerns the output on pin 14 D flip flop 042 This Signal COMP BLANK 18 composite of HDISP and VDISP Since there 15 two character time delay between Display RAM addressing and the corresponding video output on pin 6 of exclusive OR gate U74 the horizontal and vertical b
8. Audo Tape 2270 KEYBOARD Gos Diagram 096 2 Description Port Decoder IABLES AND ILLUSTRATIONS LETRE 035 amp 036 Outputs and Therr Functions TITLE Clock Generator Timing Example of uppercase character I display Example of lowercase character p display Video Display timing 6574 Character Generator ROM pattern 6575 Character Generator ROM pattern Copy righ 501977 Processor Technology Corporation MET DEN ES AT Eu VIII 14 VLIT 22 MILES ViITIASS VEIT PAGE VETT PAGE VELES VEILL 24 VIII 24 M Ie ALT 0 ART Ip 21 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECCION VILLI Oud INTRODUCTION This section concerns itself with the hardware aspects of the Sol Terminal Computer It Specifically deals with the operation of the power supply and the logic associated with the Sol PC and key board Descriptions of software and the operation of the circuitry contained in the multitude of integrated circuits IC s used in the Sol fall outside the scope of this section In some cases references to other publications or sections in this manual are provided when it is felt that additional information will contribute to a better un derstanding of how Sol operates Should the reader wish to delve further into the operation of a specific IC we suggest th
9. PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES 1 If you see the error immediately the error is to the immediate left of the cursor press the DEL key unshifted to erase the mistake Then make the COLEreECELIOnN Pg If the error is more than one character position to the Lert OL he cursor use cursor COHUtol keys to position the cursor over the mistake Then make the correction Keyboard Restart To perform a keyboard restart press the UPPER CASE and REPEAT keys at the same time This key combination performs the same function as a power on initialization or setting the RST switch to ON Use the keyboard restart to return to SOLOS CONSOL from 1 a program which does not recognize the MODE SELECT key 2 a program that 15 stuck in endless loop 7 9 SOL PERIPHERAL INTERFACING Audio Cassette Recorders Your Sol is capable of controlling one or two recorders The interconnect requirements for one recorder were previously covered in Paragraph 7 41 This Section Since the Sol has only one audio input and one audio output jack however the interconnect requirements for two recorders are somewhat different than for one You will need two Y adapters one to feed the single Sol audio output to the AUXILIARY input of two recorders and the other to feed the MONITOR output of two recorders to the single Sol audio input If you intend to use the Audio In
10. pigtail has a spade lug at its free end and 18 connected to the lug you just attached to the negative terminal of C9 11 17 PROCESSOR TECHNOLOGY CORPORATION SOL POWER SUPPLY SECTION LL o Connect green lead from AC receptacle mounted on fan closure plate to power supply subchassis assembly as shown in drawing on Page X 2 Use the 6 x 1 4 sheet metal screw with which you prethreaded the middle Sol REG heat sink mounting hole in Step 29 Place Oi Screw and drive screw into the middle Sol REG heat sink mounting hole 44 Route black transformer leads along side wall of power supply subchassis out toward the Sol REG heat sink See Figure 2 4 Attach one lead to pin 2 of the commoning block mounted on closure plate nearest the Attach other lead to pin 3 of the other commoning block Step 45 Install cable tie wraps 84 Install one wrap around the wires that connect to Sol REG pads T1 2 3 X2 and X3 as shown in the Detail A Wiring portion of the drawing on Page X 2 Install another wrap around the leads from C9 as shown in Detail B of drawing on Page X 2 Two other wraps are supplied with your kit Use them as appropriate to make your power supply cabling neater Step 46 Using a 6 x 1 4 sheet metal screw attach fan closure plate to power supply subchassis as shown in Drawing No X 2 Step 47 Push on off switch in a
11. If the display circuits are operating correctly Turn monitor and power supply off and disconnect the power cable Remove jumpers from U14 through U21 sockets Bend pin 6 on U42 pin 4 on U49 and pin 5 on 075 back to their normal position arid re install these three IC s in their appropriate sockets CEZA PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER LEL Figure 13 8 Display circuits test pattern with 6575 character generator 025 6574 is the same except graphic control charac ters are displayed 2 4260 22 ICS Locations ULA through 021 Dots on the assembly drawing and board legend indicate the location of pin 1 of each IC CAUTION ULA THROUGH MOS DEVICES RE FER TO CAUTION ON PAGE 111 8 BEFORE YOU INSTALL THESE IC s Step 30 Install the following resistors in the indicated locations Bend leads to fit distance between mounting holes insert leads pull down snug to board solder and CIM LOCATION VALUE ohms COLOR CODE R12 TSK brown green red R18 TO E brown black orange Step 30 continued on Page 111 26 Hev A LEL 29 PROCESSOR TECHNOLOGY CORPORATION IM Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION III LOCATION VALUE ohms COLOR CODE R20 LORK brown green red R31 Trok N Roz LioK 33 Tor E E R34 R35 d S
12. c6 WERE ne 3486555 22 amp 7 Ea gt 255 AM TUM 2 n2 5 ZEE UC EN e S ee _ org oris opvacses ES T LETA a Se T Ea e De c9 1 73 217 t 5 6 Tic dira ae a ET Bee oe eae j ake ee 53 5 55 655 83 04 5 55 4 5 wervelwvews Figure ic RENTEN a cL NU a m LIPS DONE ee ERI DERE NC P COEM ee 242 LATTES MWe Sea tsa LY y ae cA E EE ee Soi PC Rev D Solder Side 1874 eeczisoM COSM ORT cons B64 eoscccocodos o Sol REV E to F The following is a list of changes to bring a Revision E Sol to a Revision F Sol 1 Substitute a 270 ohm 1 4 watt 5 resistor for R21 formerly 470 ohm resistor This change is to increase the drive capability of the serial current loop and was elaborated in CHANGE NOTICE 18 2 Change the value of VR3 from 50K pot to a 100 pot This allows a wider range of variation wh
13. EAPC UO 91L02APC 2o ELPC 7415136 VE MED 74LS20 U24 741504 034 36 E y 395 7415138 C 036 C 0558 Abu Or 24202 C ue 291 7415367 083 741 520 MOS device Refer to CAUTION on Page III 8 Step 48 Test memory and decoder circuits Set Sl switches as specified in Step 38 o Jy Turn on and apply power to Ground pin 1 of U2 You should see the same display showr zn Frouce 3 10 on Page ILI Ol this case ever there should be a vertical flickering movement with an apparent flicker rate of approximately three times per second C Turm Swriteh NO 91 TO The flicker should Stop Step 48 continued on Page III 33 2 EROCESSOR TECLI QDhOGY CORPORATION IM oal PC SINGLE BOARD TERMINAL COMPUTER SC ELON Ir NN NN NN NN NN NN NN NN CN NN ON ON M NNN gt NT ee ee gt eee gt gt gt gt the test fails determine and correct the cause before proceeding with assembly If the 501 passes this test turn monitor and power supply off disconnect power cable set Switch No 1 of Sl 2nd Go on Seep 494 Step 49 Assemble personality module if you have not yet done so See Section IV If you have go to Step 9 in Section IV and complete the personality module assembl
14. 1415174 U12 9 44 99 30 9 51 54 t e deat det 014 741500 ULLS 141574 741500 1442 018 SO s toy ULIS 4051A Co Sr QO de t UZI 1442 Ce 2225 4051A U23 741504 U24 7406 C 029 741530 026 1415174 y MOS devices Refer to CAUTION on Page 3 4 Step 11 Connect 20 conductor ribbon cable between J1 keyboard to J3 on Sol PC so that cable goes left from J3 Step 12 Check keyboard operation Set Sl switches on 501 follows d 4 OFF Nos 55 ON NO 4 OFF ROV B M Sol KEYBOARD Rev A PROCESSOR TECHNOLOGY CORPORATION SECIION M Connect TV monitor to Sol PC With personality module installed apply power to odes Using a CLEAN finger touch key pad 462 MODE SELECT You should get a carriage return and line feed and see a greater than sign on the screen above the cursor NOTE You may have to touch pad 62 several times to obtain the specified display If you are unable to obtain the specified display locate and correct the problem before proceeding if the keyboard is operating correctly turn monitor and DOl Be DOWer OLE 3906000605 20 60ndUCctor ribbon cable at Jl on the keyboard and go on to Step 13 Step 13 Place keyboard assembly carefully over key pads PC board Be sure the three LED s fit in the holes in t
15. Code 574 6575 992 6574 6575 294 6574 6575 STANDARD KEYS Continued E B RETURN Line Line LINE FEED Feed Feed CTRL SHIFT LOCK ca YOM r 09 0 DeletedDelete None None None None UPPER CASE None None SHIFT None None Z Z X X C C See notes at end of this table Page VII 21 PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VLI Table 7 4 Sol Keyboard Assignments Continued HEXADECIMAL CODE CHARACTER GENERATION UNSHIFTED SHIFTED CONTROL Symbol Symbo Symbol Displayed Displayed Displayed Code 6574 6575 Code 6574 6575 Code 6574 6575 lt V AZ lt 5 LOCAL space Bar N 20 PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VI HEXADECIMAL CODE CHARACTER GENERATION UNSHIFTED SH LB TED CONTROL KEY TAN Symbol x Symbol Symbol Code Displayed Displayed donc Displayed AERE 6574 SPEC JOBS LOAD 216 None MODE SELECT 80 None None 80 None None 80 None None T 27 None None oy None None 97 None None E 81 None None 81 None None 24 gt 2
16. The warranty herein extends only to the original purchaser and is not assignable or transferable and shall not apply to any software product which has been repaired by anyone other than Software Technology Corporation or which may have been subject to alterations misuse negligence or accident or any unit which may have had the name altered defaced or removed Uu E This manual describes the use and operation of either tm tm SOLOS os CUTER SOLOS 15 a program designed to be a personality module in a Soi CUTER is program designed to provide much of the power of SOLOS for non 50l user Because aud CUTER nave been designed to be compatible operating systems this manual will refer to SOLOS meaning the SOLOS CUTER operating system The few differences between SOLOS and CUTER will be stated explicitly tm SOLOS CUTER and Sol are trademarks of Processor Technology Corporation SOLOS CUTER User s Manual TABLE OF CONTENTS INTRODUC TION Definition of Terms Quick Command Reference List CONSOLE COMMANDS Console Commands in Brief Console Commands in Detail Execute Command Enter Command Dump Command Terminal Command Custom Command TAPE COMMANDS Tape Commands in Brief Tape Commands in Detail Get a File from Tape into Memory Get then Execute Save a File Catalog a File SET COMMANDS SOLOS Ten Set Commands Set Commands in Detail set Spe
17. gt PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILI done over the Address Bus cursor position and the A enter the Dis play RAM on the Bidirectional Data Bus The CPU is now finished with the transfer and will issue the next activity command When the refresh control circuitry calls up addresses the A from the Display RAM the character generator ROM decodes the ASCII coded A that is input from the Display RAM and generates the A dot pattern see Figure 8 5 and 6 in parallel form The ROM output is serialized into a video signal and combined with a compo site sync signal to provide an Electronic Industries Association EIA composite video signal for display on an external video monitor SDI UART Transfer and Display A data transfer through the SDI UART is similar to a keyboard entry but data can be transferred in either direction Assume the SDI UART wants to transfer an A from a modem to the CPU for display on a video monitor The ASCII code for the A received in serial form from the modem on the serial data input of the SDI connector Jl is fed to the SDI UART In the receiver sec tion of the UART the serial data is converted into parallel form and placed in the UART s output register The UART also sends a received data ready status signal to the CPU on the Internal Data Bus When the program in ROM checks and finds the status signal the program enters the SDI routine and enabl
18. 3 SOLOS CUTER USERS MANUAL Processor Technology Corp Software Technology Corporation 6200 Hollis Si P O Box 5260 Emeryville CA 94608 San Mateo CA 94402 415 652 8080 415 349 8080 0100 t soros USER S MANUAL PROCESSOR TECHNOLOGY CORP SOFTWARE TECHNOLOGY CORP 6200 Hollis Street Ps 0 Box 5200 Emeryville CA 94608 San Mateo CA 94402 ALS 552 000 415 324 9 8 060 1977 Dy Processor Technology Corporation uu R E This copyrighted software product is distributed on an individual sale basis for the personal use of the original purchaser only No license is granted herein to copy duplicate sell or other wise distribute to any other person firm or entity This software product is copyrighted and all rights are reserved SOFTWARE WARRANT Y Software Technology Corporation warrants this Software Product to be free from defects in material and workmanship for a period of three months from the date of original purchase This warranty is made in lieu of any other warranty expressed or implied and is limited to repair or replacement at the option of Software Technology Corporation transportation and handling charges excluded To obtain service under the terms of this warranty the defective part must be returned along with a copy of the original bill of sale to Software Technology Corporation within the warranty period
19. Assembly Tips zo Zr Mechanical Assembly Precautions Required Tools Equipment and Materials Sol REG PC Board Fan Closure Plate Assembly Test Fan Closure Plate Assembly SOL REG Assembly and Test Power Supply Subchassis Assembly and Test B D9 A9 sus GO TIS rS TISS IE IEG A IY ISEA ool POWER SUPPLY Zi ditional PROCESSOR TECHNOLOGY CORPORATION SECTION EL INTRODUCTION The Sol power supply consists of a regulator board plus ad chassis mounted components This section covers assembly and test of the complete power supply 2 2 dag Parts List identifying any parts by sight PARTS AND COMPONENTS 003 Regulator 501 Check all parts and components against the appropriate Tapies Zub Z52 dnd Lf vou have refer to Figure 3 1 on Page III 5 in Secbron ILI of thus gt Power Supply Subchassis In addition to the Sol REG and Components you will need the following parts and components supplied with the Sol Cabinet Chassis Kit Check these parts against the appropriate 6 1 and 6 2 Chassis Darts Rev A Parts List s Tables in Section VI and separate them from the other cabinet Fan Closure Plate Power Supply Subchassis 4 4 4 10 14 14 16 each each each each each each each each
20. Twist the two black wires together except for the last two inches at the commoning block lug end Twist the two green wires together for their full length Twist the two yellow wires together for their full length fup Turse Che INO PLus wines together Tor their JULI Step 26 Connect Sol PC power cable 4 wire cable which connects to J10 on Sol PC to Sol REG Tin ends of cable and solder green lead to pad X9 white lead to pad Xl red lead to pad X7 and white yellow lead to pad X69 Step 27 Connect Sol 20 DC power cable 5 wire to Sol REG Tin ends of cable and solder white lead to pad X4 above red white lead to pad X5 between C5 and FWB2 and yellow white lead to pad X6 left of C5 Step 28 Connect transformer leads to Sol REG Solder green leads to pads Tl and T2 white yellow lead to pad T3 and yellow leads to pads T4 and T5 on Sol REG JUSTO step 29 Prethread the three Sol REG heat sink mounting holes in the power supply subchassis shown in drawing on page X 2 with 6 x 5 16 sheet metal screws Remove screws Le PROCESSOR TECHNOLOGY CORPORATION oou POWER SUPP iY SECTTON TI Step 30 Place 44 lockwashers on two 4 40 x 3 16 binder or pan head screws Insert these screws from the bottom side of the power supply subchassis through the two mounting holes located near the middle of the bottom of the power supply subchassis one on each side Place another 4 lock
21. 3 Eight status outp t lines from the CPU Support Logic Memory and I O devices use status signals to obtain in formation concerning the nature of the CPU cycle DMA devices must generate these signals for DMA transfers 4 Nine processor command and control lines Six of these are output signals from the CPU support logic three of them are input signals to the CPU support logic from memory and I O devices In a DMA transfer the DMA de vice assumes control of these lines 5 Five disable lines Four of these are supplied by a DMA device to disable the tri state drivers on the CPU out puts during DMA transfers The fifth is a derivative of the DBIN output from the CPU and it is used to disable any memory addressed in Page ft Use of this disable is optional with a jumper 6 Two input lines to the CPU support logic which are used for requesting a wait period One is used by memory and I O devices and the other by external devices 7 Six power supply lines which supply power to expansion modules 8 Three clock lines 9 Four special purpose signal lines 10 Thirty one unused lines Definitions for each S 100 Bus dine as used rn the Sol are provided on Pages AVII 3 through AVII 6 in Appendix VII addition to Che S 100 Bus structure Sol uso uses an eight line keyboard input port an eight line parallel input port PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILI an
22. AA lav m 470 1 2 D3 9 e 04 ed ah PROCESSOR TECHNOLOGY CORPORATION 6200 HOLLIS STREET EMERYVILLE CA 94608 415 652 8080 CABLE ADDRESS PROCTEC CN 410 7 77 ESS Ref ECN NO 10059 Processor Technology Processor Technology 7100 Johnson Industrial Drive 415 829 2600 Corporation Pleasanton CA 94566 Cable Address PROCTEC 501 MANUAL CHANGE NOTICE CHANGE NOTICE 11 Refer to Section X Drawing X 19 Sol Audio Tape I O Schematic 0110 a 4046 phase locked loop IC has its VCO center frequency adjusted by VR3 shown as a 50K potentiometer The upper frequency limit of adjust ment is determined by R154 shown as a 100K resistor The lower fre quency limit is determined by the total resistance of VR3 and R154 Due to extreme variations in the specifications of this part among var ious vendors the range of adjustment provided by VR3 and R154 is occa sionally insufficient To correct this problem the value of VR3 has been changed to 100K and the value of R154 has been changed to 47K Parts of these new values have been included in your kit or assembled Sol To insure that the parts are correctly installed if you have a kit and in any case to insure that the manual reflects these changes make the following notes in the manual Item Page No Figure or Step No Changes 1 X 19 Schematic Change VR3 value to 100K 2 Change R154 value to 47
23. Cut the trace leading to pin 1 of 045 on the solder side of the PCB Also on the solder side cut the second trac to the right of 064 Jumper pin 73 of 111 to pin 1 of 045 Jumper from pin 28 of 111 to the feedthrough which formerly led to pin 73 of Jll before the trace was cut Jumper the feedthrough directly below pin 1 of U45 to the feedthrough to the right of 064 pin 3 This fix will allow the Sol to be used with DMA devices Helios II and other DMA devices will not work without this fix Js MWRITE FIX n the solder side of the PCB cut the trace leading to pin 7 of U93 On the solder side cut the trace leading to the feedthrough immediately below pin 1 of U92 DO NOT CUT THE TRACE LEADING TO U92 PIN 11 Connect a jumper from this feedthrough to pin 13 of 0107 On the solder side jumper the feedthrough leading to U94 pin 9 to the trace which formeriy led to U94 pin 7 before the trace cut This fix decodes the MWRITE signal from SOUT and PWR even when a DMA device has disabled the Status Drivers This is especially important to memory boards which require MWRITE and do not decode PWR and SOUT internally and DMA devices such as Helios which do not supply their own MWRITE to the bus Y7 CURRENT LOOP FIX Cut the large trace which leads to R23 and R24 on the solder side of the PCB Connect the now isolated end of R23 to the 412 Volt feedthrough as shown in Figure B 8 CASSETTE RELAY FIX On component side of Sol PCB
24. LES PROCESSOR TECHNOLOGY CORPORATION ood POWER UII SEG ELON Za blek Fan Closure Plate Assembly Refer to Assembly Drawings dn Pages 1 and 2 in Section X Figure 2 1 shows a completed fan closure plate assembly Figure 2 1 Sol 20 fan closure plate assembly Top of plate in foreground ur Mount cooling and to Tam closure plate Insert four 6 32 x X binder or pan head screws from back side of fan closure plate Use the holes positioned in each guandranb of the large circular c to t olip guard over screws on front side of plate Position fan so that air flow will be from front vto Deck sade orf and with its leads next to the rectangular cutouts in the place Place 6 lockwasher on each screw and secure with 6 32 hex DES WARNING FAILURE TO INSTALL FAN GUARD MAY RESULT IN DAMAGE TO THE Sol AND OR PERSONAL TNT ORY J Install power On Off switch 3n Upper rectangular xr ban Closure late Step 2 continued on Page 11 5 ReVB 11 7 PROCESSOR TECHNOLOGY CORPORATION ool POWER SUPPLY SECTION II Rev B Bend four retainer tabs on switch in and position switch with terminals facing front side of fan closure plate Push Switch unit from back side of plate through mounting hole and bend retainer tabs outward if needed to hold switch in place step 3 Install commoning blocks Item 6 on drawing on Page X 1 on fron
25. NOTE Dots on the assembly drawing and PC board indicate the location of pin 1 of each IC IC NO TYPE 028 7415163 or 2515163 031 7415163 or 2515163 U33 7415163 or 2515163 040 7415163 or 2515163 U43 7415109 147 741 610 U49 741 504 Step 24 continued on Page 111 20 III 19 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION III IC NO TYPE 059 741 520 U60 Or 5210502 062 93L16 074 741 586 7415109 087 7406 4049 y 4001 MOS device Refer to CAUTION on Page 111 8 Bee Os Apply power to Sol PC and check display section timing chain operation If you have an oscilloscope use part A of this Steps If you do not use Dare B A Oscilloscope Check Using an oscilloscope check for the waveforms given in Figure 3 5 at the indicated observation points and in the order given The waveforms shown in Figure 3 5 approximate actual waveforms any waveforms are incorrect determine and correct the cause before proceeding with assembly NOTE Irregularities up to 1 volt are accept able on positive portions of waveforms Negative portions however should be relatively flat Volt ohm Meter Check Using the test probe made in Step 16 measure the voltage at pin 12 of 028 You should measure approx imately 1 V dc If you get a significantly lower read
26. OnI EA Typical System Operation Basic Sol system operation 15 as follows The CPU fetches an instruction and in accordance with that instruction issues activity command on the Control Bus outputs a binary code on the Address Bus to identify the memory location or I O device that is to be involved in the activity sends or receives data on the data bus with the selected memory location or I O device and upon completion of the activity issues the next activity command Let s now look at some typical operating sequences Keyboard Data Entry and Display Assume the A and SHIFT keys on the keyboard are pressed The keyboard circuitry converts the key closures into the 7 bit ASCII American Standard Code for Information Interchange code for 1000001 and sends a board data ready status signal to the CPU on the Internal Data Bus The monitor program in ROM repetitively looks for the status Signal When it finds this signal the program enters its keyboard routine and enables the transfer by switching the Data Input Multi plexer to the keyboard bus via the Address Page and I O Port Decoder Following program instructions the CPU addresses the Display RAM on the Address Bus to determine where the next character is to appear on the screen It then stores the ASCII code for the A at the appropriate location in the Display RAM and adds one to the cur Sor position in readiness for the next character Addressing is
27. 1 and Clock_128 neither decoder is selected when 01 is low the time U5 and U6 count During this time false binary signals can appear on the outputs of 05 and 6 The net effect is that only one of the 15 outputs from 017 and 21 will be low and this low advances on each count advance The low outputs of 017 and 21 drive the column lines in the key switch matrix Clocks 1 through 8 are connected to analog multiplexers 019 and U22 Only one channel from input to output is connected at one time Note that Clock 8 and Clock 8 from U6 enable 019 022 re spectively 019 022 the Row Scanner thus scan through the 16 rows in the sequence indicated by the numbers contained within the boxes of the key switch matrix An entire scan of the rows is made before the next column is selected by 017 and 21 We now have 17 U21 driving the column lines and 019 and U22 testing each row line by connecting it to an input to the Capaci tance Key switch KIC Detector These two inputs are normally high at 5 volts Within the switch matrix there is a small capacitance connected between each column and row line that is there is a capa citance associated with each key on the keyboard When a key is de pressed on the keyboard the capacitance associated with that key in creases When the column and row lines associated with that key are selected there is a significant voltage difference between the two and the capacitance charges to
28. After connecting a cassette recorder and video monitor to your Sol you will operate the system in the terminal mode to become familiar with the keyboard and the functions of the video display switches You will then switch to the command mode and perform some of the basic computer operations Xd Monitor and Cassette Recorder Connections The basic Sol system consists of the Sol a video monitor for display e g the Processor Technology PT 872 TV Video Monitor by Panasonic and a cassette recorder for external storage e g the Panasonic Model RQ 413S To connect these three system components you will need the following cables Audio In amp Out Cables two cables of shielded wire fitted with miniature phone plugs at both ends Motor 1 Cable one cable pair such as speaker wire fitted with subminiature phone plugs at both ends An identical cable for Motor 2 is needed if you use two recorders Video Cable one RG59 U coaxial cable fitted with a PL259 UHF male connector on one end and a monitor compatible connector on Cie Connect the basic Sol system as follows refer to Figure 7 1 on Page VII 6 Mud Sol OPERATING PROCEDURES 7 42 Step 1 Step 2 PROCESSOR TECHNOLOGY CORPORATION VLI Remove top and keyboard covers from Plug one end of Audio In Cable into Audio IN jack J7 on Sol rear panel and plug other end into MONITOR or EARPHO
29. C8 to Regulator Board cable to regulator Tin ends without lugs and solder green lead to pad X2 and white lead to pad X3 Rev B Step 22 SOL REG FOr Snort Circuits Check Tor Gonti nuity between FWB1 MDA970 1 mounting screw and the follow Ing porntei The resistance should be greater than 20 ohms in all cases X 2 Q1 Base D3 top lead T2 Q1 Collector D4 top lead 01 right hand lead D3 bottom lead Ol Emitter left hand lead D4 bottom lead Resistance will be initially low due to C4 and C5 but it should increase to greater than 20 ohms after a few seconds Tid PROCESSOR TECHNOLOGY CORPORATION DOL POWER SUPPLY SECTION TI 52159 step 23 Sol REG to one side Power Supply Subchassis Assembly and Test Step 24 Mount transtormer IL for Sol lo S5ol 20 0f power supply subchassis L shaped chassis Position transformer as shown in drawing on Page X 2 and attach it to the subchassis with three 8 32 x 1 2 binder or pan head screws 8 lockwashers and 8 32 hex nuts Insert screws from bottom and outer side of chassis as shown Place lockwasher on each screw and secure loosely with hex nuts Slide former as close as possible to the edge of the chassis and tighten nuts NOTE Only one of the holes in the side wall is used Use the one that lines up with the transformer mounting tab Step 25 Prepare Transformer leads
30. GLOSO On exit Normes retur Carry Flag cleared Error Carry Flag set Error caused by file NOT open 43 UOADING S EXECUTING CUTER Applicable to CUTER only CUTER is available 1 on cassette tape with its own loader which can be loaded at any memory address from 0200 through F400 or 2 ROM at the address C000 In order to load CUTER from cassette tape perform the following steps When CUTER is being used in ROM the procedure is much simpler make sure the sense switches are set according to below prior to executing location 000 A Verify that the hardware is connected and functioning properly Enter the following bootstrap routine into memory beginning at location 0 The following is presented a format similar to that produced by a DUMP command with an address shown every 10 hex bytes 0000 Zl 40 00 45 D SE S0 D3 FA Ey 05 C2 00 E7 OOTUS Os OA OE IE O2 03 EE DD C2 T4 00 EY 0 00 220 0020 FA AS CA 20 00 52 Ga Verify that the above bootstrap is in memory exactly as presented Da Set the sense switches to the address at which CUTER is to be loaded The sense switches will be the hi order byte of the memory address with the lo order byte zero As an example Sense switches set to 34 hex will cause CUTER to be loaded into memory beginning at location 3400 hex For convenience a memory address should be selected that also specifies
31. L of each 10 IC NO TYPE U80 8T97 C QUSE 8T97 NOI substitute Figure CPU ronal Test No 1 display 6574 or 6575 character generator U25 Step 40 Perform Functional Test No 25 JO CPU Ca lt Check that Sl switches are set as specified in Step 38 urn monitor on apply power to 99l PC Momentarily ground pin 1 of U2 and pin 2 of 075 The display shown in Figure 3 10 on Page 111 31 should appear on the monitor the test fails determine and correct the cause bes fore proceeding with assembly If the Sol PC passes this test turn monitor and power ofr disconnect power cable and proceed to Step 41 Rev A 2 0 PROCESSOR TECHNOLOGY CORPORATION IM 501 SINGLE BOARD TERMINAL COMPUTER SC ELON Ir Hev A g gt Step 41 Install the following IC s in the indicated loca tions Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board indicate the location of pin l of each IC TC NOS LYE UGS JT 066 1745233 U78 FAW SASS 12 Jo 9 gt 093 gt 0106 1529 Step 42 Turn monitor on apply power to 501 and perform the test described in Step 40 except ground in S of U75 in Stead of pin 2 You should get the same results If the test fails determine and correct the
32. U22 23 24 76 77 2 Screen fills with random characters and flickers A gt MWRITE not present 046 49 50 107 plus one of the above symptoms 3 Screen fills with random characters and does not flicker A gt CPU not running No PSYNC or DBIN l No 5 5 12 volts 2 Bad CPU 0185 3 No clock to CPU XTAL U77 90 91 92 184 4 Ready line held low U48 63 5 Hold line held high U64 6 INT Interrupt line held high U45 B CPU running PSYNC and DBIN present 1 MWRITE to video section 044 4 Screen clears displays cursor and prompt but also displays an extra character on the Screen or incorrect characters A gt Bad display RAM 014 21 gt Intermittent or floating MWRITE 044 46 49 56 197 5 Screen clears momentarily displays cursor then fills with Flickering nines and nulls as in symptom 1 A gt Bad system RAM 03 1 6 Screen is blank A gt No video output 041 59 74 87 B CPU not running 5 12 or 5 voltage not present gt Reset RST line from keyboard is held low 7 Will not scroll correctly A gt Bad scroll latch or MUX circuitry Ul 2 11 13 38 32 8 Characters on screen are incomplete or broken up A gt Shift register bad 041 9 Cannot enter from keyboard A gt Bad keyboard see section on kybd problems B Keyboard flag logic 053 54 70 71 C gt Bad MUX or MUX decode logic U36 65 66 78 769 18 Keyboard output continously
33. YES CONFIGURATION CHECK 1 Boards in Backplane Seated 2 MEM Cards Addressed Correct 3 Ribbon Cables installed With Correct Polarity v 14 Fuse Installed 5 AC Connected amp Video Connected 6 Ribbon Cable To Helios Cabinet 7 Connected 7 Bootload Personality Module instatled V DELIVER TO CUSTOMER 1 Ribbon Cable Connected With Correct Polarity 2 Fuse Instailed 3 AC Power Connected 4 System Diskette installed Correctly Unit 5 Model 4 PTDOS Configured For 4 Units See Page 1 49 Of PTDOS Monual COMMON SYMPTOMS OF FAILURE IN THE Sol WARNING WHENEVER A PROBLEM OCCURS IT IS ADVISABLE TC FIRST CHECK THE OUTPUTS OF THE POWER SUPPLY This section is designed to aid the technician in the location and isolation of problem areas in the Sol computer It is not intended to be a point to point troubleshooting guide therefore it only identifies ICs by number and not pin numbers 1 The screen fills with alternating nines and nulls screen flickers NOTE THIS CONDITION IS REFERRED TO AS A STACK CRASH AND IS CAUSED BY THE CPU ENCOUNTERING AN ON THE DATA BUS DURING AN INSTRUCTION CYCLE A gt Bad RAM U3 19 B gt Open or short on INT bus NOTE PROBLEMS WITH THE INT BUS CAN SOMETIMES BE CAUSED BY BAD UART S 051 69 gt Bad MUX s or MUX select logic 024 36 47 48 61 65 66 78 79 83 D gt Bad FOUR PHASE WONDER
34. cuit When power is applied 15 starts to charge slowly until it reaches the threshold on pin 6 of U46 a Schmitt trigger By this time the logic and 5 volt supply have stabilized When the thresh old is reached pin 1 of U46 suddenly goes low The resulting output on pin 8 of inverter U92 is initially low and then rapidly goes high This signal is passed through a section of 077 a permanently enabled noninverting tri state driver POC to S 100 Bus pin 99 is also inverted in a section of U45 to become POC The output On pir vor U92 19S also connected to pin Lo OT U63 Thus 9 RESET Or as high to start the CPU in the reset condition when the Sol is initially turned on When POC goes high the RESET flip flop section of 063 is free to clock Assuming PRESET is not active it will change state on the first CLOCK transition The resulting high on pins 10 and 5 of U63 cause pin 7 READY of U63 to go low to place the CPU in the not ready or wait state This state is subsequently removed on the CLOCK transition following the transition which removed the low from 5 of U63 This helps prevent the CPU from starting in crash The HOLD flip flop 064 however is not affected by the Circuit and was clocked to a low on pin 7 well before the RESET and READY signals became active Operation of the POC circuit can also be initiated without turning the power off by a keyboard r
35. each each each each each each L shaped 4 40 x 3 16 Machine Screw 4 40 x 5 16 Machine Screw 4 40 Hex Nut 4 Lockwasher 6 32 x 12 Machine Screw 6 32 Hex Nut 6 Lockwasher 8 32 x Machine Screw 8 32 Hex Nut 8 Lockwasher 6 x M Sheet Metal Screw 6 x 5 16 Sheet Metal Screw 44 Solder Lug 11 Spacer 4 40 Tapped PROCESSOR SO POWER SUPPLY Table 2 1 TECHNOLOGY CORPORALTION SECTION LI Sol Regulator Parts List INTEGRATED CIRCULO gt DIODES amd RECTIFIERS p 715456 912 II FWB2 MDA970 1 1 LRIUGBZ MMCRIOO Z IN4001 03 amp 4 1N4148 D2 Di 02 01 03 SORT TRANSISTORS 2 222227 1 Q2 amp 3 Q1 RESISTORS 3 watt aise 5 watt watt watt watt watt watt watt watt 15 Utd 2300 uid QU tantalum dipped tubular electrolytic electrolytic CABLE ASSEMBLIES 1 Single wire 3 Fuse Holder to Power Switch 3 1 4 C8 to Regulator Board 1 Single wire LOT Power Switch to Commoning Block 1 Two wire Chassis mounted component When identifying IC s you can iqnore prefix and suffix characters in the IC nomenclature since these vary with the manufacturer For example a 1458CP 1458 and 1458 are all 1458 This applies to all Parts Lists in this manual PROCESSOR TECHNOLOGY CORPORATION Sol POW
36. keys on the Sol keyboard and 2 HEXADECIMAL CODE CHARACTER GENERATION which specifies for each key the hexadecimal code generated by the keyboard and the symbol produced by the Sol s character generator The second heading is divided into three major categories UNSHIFTED SHIFTED and CONTROL UNSHIFTED defines the results when operating the keys unshifted lower case SHIFTED provides the same information when they are operated shifted upper case and CONTROL defines the results of control sequences refer to Paragraph 7 7 7 on Page VII 22 Within each of these three categories you will find the hexadecimal code generated and the symbol displayed in response to that code by either of the two possible character generators that can be supplied with your Sol the 6574 and 6575 Some keys move the cursor without displaying a new Character Looking at the entry Page VII 18 and reading across the table we see that i Pressing unshifted would generate the code 77 and either character generator 6574 or 6575 produces a lower case W w Do not actually press the keys at this point Pressing shifted would generate the code 57 and either character generator would produce an upper case W W Pressing CTRL control and W whether shifted unshifted generates the code 17 which causes the 6574 to produce the graphic Symbol Tor the ASCII ond Control character and the 6575 to produ
37. latch five bits of data on D103 7 when PORT OUT FA goes active These bits which supply the indicated outputs control conditions in both the PP and CDI With respect to the PP PIE enables parallel input and PUS selects the parallel device for the transfer The data in these two latches re mains until either a new word is read out or POC goes active Also during PORT OUT FA the keyboard flag is reported DATA READY on pin 3 of J3 is a low going pulse 1 to 10 usec Lm It xs applied Lo pin l3 of d UJ0 Some time after pin 13 of U70 goes low but before 500 nsec 070 is set by 2 and pin 10 goes low This low is buffered through U71 to INTO to indicate the keyboard is ready to send data Reset of U70 occurs witch Or by INJEC The latter occurs when data 15 accepted from the Keyboard The other halt wrth Its OUtpur on prm G latches one bit of status 0104 when OUT F8 is active Its output is applied to pin 5 of one operational amplifier section in U56 to become the SRTS request to send signal on pin 4 of Jl the SUL conmnecb orb The SDI UART centers around UART 051 The UART transmis sion conditions parity word length and stop bits are determined by the settings of 54 1 through 5 Refer to Paragraphs 7 5 8 through 7 5 10 in Section VII for descriptions of the switch settings and their effect on transmission Data destined
38. on the other hand SOLOS buffers the data into 256 byte blocks doing cassette operations only once per 256 transfers BASIC uses byte by byte access for data files Other programs such as editors assemblers or special user written programs can also call the byte by byte routines if a few specific conventions and calling sequences are followed File Header The file header for SOLOS provides specific attributes to a file These attributes consist of a five ASCII character name and a file type File name serves two functions It permits easy human identification of the file and 2 It provides the identification for which SOLOS searches and Ee Tide File type 15 used in SOLOS to prevent certain operations such as automatic XEQ if the file is not of the proper type 19 TEE ADDR 749 SUBROUTINES cont When calling open the register pair HL should point to a memory location that contains the header Following is the layout of a SOLOS file header ASC A five character name with trailing binary zeroes DB Should always be zero DB VEN SEQ File type If Bit 7 1 then this is a data file not executable DW LENGTH Length of file in number of bytes DW FROM Address at which file is to be read to or from which it is to be written DW EXEC Auto execute address ignored for data files 5 3 Space currently used by SOLOS As previously ment
39. six on each side on expan sion chassis side walls for backplane brackets with 6 x 1 4 sheet metal screws Three of these holes on each Side are located near the front edge of the main chassis The remaining three holes on each side are about 1 1 2 to 2 inches behind the front three Leave screws installed Install female coaxial connector the tab that extends out from the lower right front of the expansion chassis Insert connector through tab so threaded end faces left as shown in Drawing X 9 Insert three 4 40 x 5 16 binder or pan head screws from left side of tab through the two front and lower rear mounting holes Place 4 lockwasher on each and secure with 4 40 hex nuts Insert another 4 40 x 5 16 binder or pan head screw through upper rear mounting hole and install 4 40 hex nut Leave this nut loose See Details C and L on Drawing X 8 Install 10 plastic card guides five on each side on inside surface of both side walls of the expansion chassis PROCESSOR TECHNOLOGY CORPORATION ool CABINET CHASSIS SECTION VI These are installed over the ventillation cutout with the gripper fingers pointing towards the backplane board To install simply insert posts on guide into appropriate mounting holes and push in until they snap into place Step 20 Install expansion chassis on main chassis as shown in Drawing X 9 Position expansion chassis with coaxial connector at the front near FWB3
40. the third U90 stage C changes on the seventh clock Ihe counter now stands at 0001 and on the eighth clock the counter flips to 1000 and the count cycle repeats The pattern is thus 1000 1100 1110 1111 0111 0011 0001 090 consequently goes through seven states We have 3 5 stage counter that divides DOT CLOCK by seven to supply a 2 045 output With no jumper installed pin 10 of 091 is pulled high by R105 and 091 operates as a simple inverter for feeding back the output of the third U90 stage In effect we have a three stage coun ter that operates in a similar manner to that described in the pre ceding paragraph It gees through six states 100 110 111 011 001 O00 divide DOL GLOCK by six which produces 2 25960 MHz out put The timing for this option is also shown in Figure 8 1 Let s now put the D to C jumper in The feedback in this case is the NAND combination of the outputs from the second B and third C U90 stages This gives us a 2 5 stage counter that divides DOT CLOCK by five As can be determined from the 2 863 MHz portion of Figure 8 1 the counter has five states with this option and the pattern rss 2005 2019 it OIT Outputs from U90 are applied to the logic comprised of the remaining three sections in 091 This logic and the A to B jumper option permits extracting clock pulses of varying widths and rela tionships to each other from various points within the counter We extract
41. 1001 1 15 409 0 0 0t OOO 100000000 uf 1010 12 100000000 1110000 1038 13 00 0 00 100000000 ASCII code Tor P illuminated dot Figure 8 3 Example of lowercase character p display VILII Z24 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION LON VELI As indicated in Figure 8 4 on Page VIII 27 Subgroup Counter 031 and Group Counter U33 are preset to a count of 3 at the start of each horazonval scan line Uol counts from 3 through 15 charac ter positions and enables U33 for one count 031 then counts 0 through 15 and enables U33 for the second count The sequence con tinues through four more groups of 16 character positions and at Lips point Uz3 is St ate Sixti count da binary 9 Thos puras 14 are high at pins 10 and 11 of 047 031 continues to count from 0 and on the ninth count a binary 8 pin 9 of U47 goes high The re sulting low on output pin 8 of 047 loads three into 031 and 033 and the cycle repeats The U31 U33 cycle from preset is then 13 16 16 16 16 16 and 9 character position counts for total of 102 The QD output pin 11 of 033 15 SCAN_ADV and the QC output on pin 12 is HDISP SCAN_ADV is used to generate horizontal synchro nization signals and HDISP defines the start of the display portion of the horizontal scan line Four outputs from 031 and the two low order outputs of U33 pins 13 and 14 are input to the Character Addre
42. 2884360 03 4 1144001 D2 12 13 14 5 1 14 318 MHz in HC 18 U Case 2 DIP Reed Sigma 191 TE1A15S Kl amp K2 Eg 2 PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL COMPUTER Continued SEG LION ITI rable 53 1 Sd PC Parts List Continued LORS CAPACI TORS 2 6 8 ohm watt 5 1 LO pid dise 2 47 A 8 d 330 DEG disc 225 ohm 4 watt 55 1 470 daise L 100 onm 4 watt 2 3 680 Pia A300D Qul bxc OE ee 2 FOO watts 27 ceramic labeled t 200 ohm watt 5 681 and usually 152 2220 ohm watt 5 blue 1 90 OD 27 6 SOU ALEC 3 470 ohm watt 55 2 SO CIS 2 470 Oh 2 watt 429 2 OL ATA 2 2600 ohm A watt 2 34 ALEC 63 ohm v4 watty 5 12 X Due De A watt 9 vil ard 6 5 6K Onm A 5 250 DEG IO RK Onm A Natty 2 L 4 ufd tantalum dipped Lh 5 watt d usually orange 2 39 Webb D L K sa watt De 5 15 ufd tantalum dipped 3 50 K ohm Potentiometer orange Or 4 100 K onm Watty red 2 150 Ohm Watt 3 1 100 ufd aluminum 2 i gt 4 Watt 5 electrolytic 2 2M ohm 4 watt 2 3 3M ohm watt CONNECTORS Female AMP206584 2 J1 Male 206604 1 J2 3M3492 2002 23 24 Right Angle Edge Connector VIKING J6 J7 28 amp 49 7 pin
43. 3 the output on pin 1 of U56 which Iced to Or approximately 10 volts Tor the oppo site GcOndrtrion pin 2 of rl 15 about 10 volts Thus 056 also inverts and a high or low on pin 2 of 21 represent a binary 1 and 0 respectively Two conditions can override transmitted data a keyboard break BRK or local KBD LOC command For a break command BRK on pin 4 of J3 and pin 4 of NOR gate U55 is low to hold pin 6 of U55 high for the duration of the BRK signal This appears as a Space or high level on pin 2 of Jl A space or break condition re quires that the space level exist for a period longer than the normal length of a character In the case of a KBD LOC command from the keyboard pins 1 and 13 of the other two U55 sections are low Thus data cannot be transmitted to pin 3 of NAND gate U55 and pin 11 of NOR gate U55 is held high to enable tri state driver U37 at pin 15 Data on pin 6 of U55 is consequently looped back by way of U37 and 21 prm 12 038 Data onm LZ or U30 Overrides date riving at pin 13 of 038 local operation therefore data from pin 25 of the UART does not appear at pin 2 of J1 but it is looped back to the receiver input pin 20 of the UART via U37 R21 and U38 Notice that data on pin 25 of the UART will also be looped back if S4 6 is closed half duplex operation But in this case data from the VART rs also fed to pin 2 orf Jl Serial
44. 30 gauge insulated wire Sol REV D to E The following is a complete list of changes necessary to modify a Revision D Sol to a Revision E Sol These changes are illustrated in Figures A amp B for your convenience CLOCK WIDTH FIX On component side of Sol PCB cut the trace between jumpers D and E 090 and U91 of the clock generator the solder side of the PCB connect a jumper from pin E to the feedthrough which leads to U91 pin 5 This brings PHASE 1 into 8080 spec at 140 ns rather than 70 ns without this mod be PHANTOM GLITCH FIX On the solder side of the PCB connect a jumper from U76 pin 4 to the feedthrough immediately below 076 pin 1 This assures the Sol will always power up with 4 PHANTOM cycles GROUND NOISE FIX On the solder side of the PCB jumper 8 of 033 050 068 081 to the ground feedthrough leading to C45 Use 20 gauge insulated solid wire and keep the leads as short as possible The fix shortens the return path to ground from the bus drivers On occasion the present return path can be quite noisy 14 PROTECT FIX On the solder side of the PCB connect a jumper from the ground side of Cli to pin 70 of the 100 bus connector 911 This will ground the PROTECT line which is currently floating Again use 20 gauge insulated solid wire 4 21 5 DMA INTERRUPT UNSCRAMBLE On the component side of the PCB cut the trace leading to pin 73 of 711 5100 connector
45. 50 mv which the negative input pin 2 must exceed in order for the output of 0108 to switch levels positive to negative and the converse Since the feedback loop is regenerative 0108 switches at its maximum rate 0108 switches on each transi tron of the audio signal input It 18 in Chis manner that 9108 pers forms the audio to digital conversion The digital output of U108 is inverted in one section of in verter 0109 and applied to pin 9 of exclusive OR gate 099 which is connected as a buffer without inversion If the output of 0109 is low the output on pin 10 of U99 is also low and the output on pin 4 of another U99 exclusive OR gate is high The voltage across C49 under this condition is minimal When the output of U109 goes high C49 Starts to cherge through Riro until pin 9 ort U99 crosses che threshold of that gate At this point pin 10 of U99 goes high and since the two inputs to the second exclusive OR gate are both high pin 4 of U99 goes low C49 now discharges because pins 9 and 10 of U99 are at the same level so that the circuit can repeat the opera tion on the next high to low transition at pin 4 of U109 R118 C49 and U99 consequently serve as a transition detector that produces a pulse less than one microsecond long for each transition of the out put on pin 4 of U109 regardless of the polarity of the transition Transition pulses from U99 clock doti D oxlrp tlops ULT A transition pulse clocks the top U113 a
46. 6 1 to assemble your Sol cabinet chassis At this point in assembly Table 6 1 should re flect the remaining parts in your Sol kit Note that you may have been supplied extra pieces of some hardware items so do not panic should you have a few pieces of hardware left over after you have com pleted assembling your Sol 20 If you have any difficulty in identi fying individual pieces of hardware refer to Figure 6 1 and 60 2 Table 6 1 lists each part its description quantity and reference designation on the drawing s you will use in assembling the cabinet chassis The assembly drawings in Section X will also prove useful in identifying parts 6 3 ASSEMBLY TIPS 63 5 General 1 Scan Section VI in its entirety before you start to assemble your Sol cabinet chassis 2 IS IMPORTANT that you follow the step by step in structions in the order given when assembling the Sol cabinet Chassis if your assembly is to be done correctly and with minimum effort 3 Assembly steps and component installations are pre ceded by a set of parentheses Check off each installation and step as you complete them This will minimize the chances of omitting a step or component 4 Should you encounter any problem during assembly call on us for help if needed Electrical 1 Use a low wattage soldering iron 25 watts maximum for all soldering 2 Solder neatly and as quickly as possible 3 Use only 60 40 rosin core solder NEVE
47. 680 Monolvuihro or Drsc C44 680 pid Money thie Col 2001 DISE Oo id Monolythic C63 1 utd Disg 64 10 pid Disc Seep ls Install 14 500 MHz crystal location juSt above Col Insert leads and pull down until the case is 17 16 above the front surrace of the board Sold r quickly trim Step 12 Install male Molex connector in location JO POSICION eo the Locking Clip is facing the crystal XTAL insert shorter pins in mounting Holes and solder Step 13 In the jumper area labeled CLK on the assembly drawing between U90 and U91 install Augat pins in mount ing holes A B C D and E Refer to Installing Augat Pins in Appendix IV Using 24 bare wire install a jumper tween the A and B pins and another jumper between the D and E pins Step 14 Install the following IC s in the indicated loca tions Pay careful attention to the proper orientation DO NOT SUBS LLU POR ANY COE THESE G4 NOTE Dots on the assembly drawing and PC board indicate the location of pin 1 of each IC IC NO 071 090 Or 299 175 UAL 74 00 Cy 22 74504 Ul04 0026 or 0 0026 oobder this IC m its location See Loading DIP Devices in Appendix IV Step 15 Connect power to power connector J10 Power and interconnection requirements are as follo
48. 8 Note that pin 1 of this IC is in the upper Gorner 5 step 9 Perform Functional Test No 1 of CPU circuits Set 51 switches as follows Now iL through OFF No ON Dusen monitor and apply power to Sol PC Momentarily ground pin 1 of 02 You Should see a full display 64 characters x 16 lines on the monitor Momentarily ground pin 2 of 075 The display should blank while pin 2 of U75 is grounded When you remove the ground the display shown in Figure 3 9 on Page ILI 29 should appear NOTE The pattern shown in Figure 3 9 delete characters results from all bits of the DIO Bus being high If you do not see the delete characters one or more bits the DTO bus are OW Consult the MCM6575 or MCM6574 pattern as appro priate Section VIII of this manual to determine which bits are low If the test fails determine and correct the cause before proceeding with assembly If the Sol PC passes this test turn monitor and power supply power cable and proceso toO Step 39 Install the following IC s in the indicated loca DIONSS Pay careful attention to the proper orientation Step 39 continued on Page 111 29 LPP PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL coMPUTER SECTION NOTE Dots on the assembly drawing and PC board indicate che
49. CREF CUT B THIS U 29 REF Q O 2 Figure A Ti2V ZI A R29 R27 ae e 2 7 go U28k 051 20 N4148 wae el IN 4148 De lt 12 lt 13 Figure 731011 Page 2 of 2
50. Data output to the PP connector J2 as latched from DIO0 7 by 095 and 096 Data is strobed into these registers on the leading edge of an inverted active PORT_OUT_FD signal on pin 4 of in verter 054 This strobe is also applied to pin 2 of 073 which func tions as a J K flip flop that is clocked by 02 When the 02 goes from low to high 200 to 300 nsec after PORT OUT FD pin 7 of 073 goes low to become POL on pin 17 of J2 This delay allows U95 and 96 to stabilize U73 is reset in the middle of the following PSYNC which means POL is active for the balance of the cycle The outputs of U95 and 96 are tri state outputs that are ena bled by a low on pin 2 In the absence of POE at pin 15 of J2 pin 2 of U95 and 96 are low by virtue of the output pin 8 of inverter 055 Note that the input to U55 is normally pulled up through R63 The POE provision permits tri stating an external bidirectional data bus As discussed in Paragraph 8 5 1 parallel input data on J2 is fed directly to the Data Input Multiplexer see Page X 15 The strobe that indicates the presence of input data PDR on pin 4 of J2 LS applred Lo pins Z2 3 one in UZ2 GG J K EZlsp rflop which is connected as a D flip flop When PDR goes active low pin 7 172 will go high the next low to high transition 2 E toggle the following U72 stage At this point pins 9 and 10 of the second section in 072 go high and low respectively Pi
51. K flip flops U63 and 64 are used to synchronize the READY RESET and HOLD inputs to the CPU All three are connected as D type flip rIlLlops so that their outputs follow their rnputs on the low to high transition of the clock The READY flip flop input on pins 2 and 3 of one section in U63 is either PRDY or XRDY from the 5 100 Bus these are normally pulled high by R34 and R12 respectively S T00 Bus Srdgual XERESEI when e Normally pulled R59 the RESET flip flop the other section of U63 The HOLD flip flop 064 anput 28 P_HOLD normally pulled high by R56 from the 100 Bus Pull up resistors Rol R50 and R53 insure that the high states of these three flip flops are adequate for the CPU MISI PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECTION VIII 2 3 4 5 6 7 8 9 WH 12 5 I DOT CLOCK 1 14 3 MHz U90 PIN2 A i 1 i i 1 1 1 i 1 10 U90 PIN 15 D 8 0 6 5 C USO PIN 2 T B 090 PIN 15 D 6 D B 090 PIN 2 7 USO IS D 2 D B DELAYED 8 C l Qns 2 683 MHz CLOCKS Figure 8 CLOCK GENERATOR TIMING PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECTION VILLI Diode D7 15 and R18 make up the POC power on clear cir
52. MC Factory Service Se ees REINS PE DOI Cop gi ee INS PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTERT SECTION I 1 4 INTRODUCTION This manual supplies the information needed to assemble test and use the Sol PC Single Board Terminal Computer We suggest that you first scan the entire manual before starting assembly Then make sure you have all the parts and components listed in the Parts List Table 3 1 in Section III When assembling the module follow the instructions in the order given Should you encounter any problem during assembly call on us for help if necessary If your completed module does not work pro perly recheck your assembly step by step Most problems stem from poor soldering backward installed components and or installing the wrong component Once you are satisfied that the module is cor rectly assembled feel free to ask for our help 1 2 GENERAL INFORMATION 1 254 Sol PC Description The Sol PC is a single board microcomputer terminal built around an 8080 microprocessor Support circuitry permits full im plementation of every 8080 function It features both parallel and serial communications inter faces a keyboard interface an audio cassette interface a video display generator 1024 8 bit words of system RAM random access memory 1024 8 bit words of display RAM and a plug in personality module with up to 2048 bytes of ROM read only memory stored pro gram an
53. Male Locking Molex Connector J10 Il 3221 50 0506A mates with 410 25 pin 20 pin Header 0 SRHI5 TJIKGI5 J5 Miniature Phone Jack Subminiature Phone Jack J11 orefabricated 100 Edge Connector il ik 2 1 2 2 l 1 Molex type DC Power Cable RevA Ide PROCESSOR TECHNOLOGY CORPORATION 1 SINGLE BOARD TERMINAL COMPUTER SECELON JT Table 3 1 5 1 Parts List Continued MISCELLANEOUS 1 2 29 6 2 2 1 1 2 10 2 4 6 2 1 1 1 Sol PCB Circuit Board length of 24 bare wire DIP Socket 14 DIF lo prn DIP Socket 24 DIP Socket 40 pin DIP Socket Augat Pins on Carrier 6 posxtson 9l 94 DIP POSITION 4552 amp 559 4 foot Length 72 ohm Coaxial Cable Tie Wrap for Coaxial Cable Mounting Bracket 501 1040 Guide A299 4 Lo kwasher internal tooth 4 Insulating Washer 4 40 x Binder Head Screw 4 40 x 7 16 Binder Head Screw 4 40 x 5 8 Binder Head Screw 4 40 Hex Nut solder Manual Personality Module Kit See Section IV for contents DLdq4 PROCESSOR TECHNOLOGY CORPORATION SOLl PC SINGLE BOARD TERMINAL COMPUTER SECTION III Monolythic left and Ceramic Disc Capacitors 5 C 8 C Transistor TO 18 Package Metal Can Transistor TO 92 Package Plastic Mylar Tubular i Capacitor Dipped
54. Mnemonic ON OFF 52 1 SSW LSB Gt a bit 0 10 1 S2 7 LO HI 52 8 5507 MSB data bit 7 LO HI AVII 6 SERIAL I O BAUD RATE SWITCH Schematic Drawing 3 Function Switch No Mnemonic OFF 3 I 75 75 BAUD Do not turn more than 53 2 11 110 BAUD one switch on at a time 53 3 15 150 BAUD 53 4 30 300 BAUD 53 5 60 600 BAUD 53 6 12 1200 BAUD 53 7 24 48 2400 or 4800 normally 2400 if not jumpered K to M 53 8 96 9600 BAUD SERIAL I O CONTROL Schematic Drawing 3 Switch No Mnemonic ON OFF 54 5 Parity odd Parity even if 54 5 on 54 2 WLS 1 Data word length 7bits 6bits on S4 3 WLS 2 Off On Off On Off off On 54 4 585 1 stop bit 2 stop bits 1 5 if 5bits word 54 5 PI Parity No parity S4 6 F H Half duplex Full duplex MEMORY ALLOCATION ON CARD Hexidecimal Address Function 000 7 Personality Module ROM or PROM 2048 words C809 CBFF System RAM 1024 words 00 CFFF Display RAM Memory 1924 characters ON CARD INPUT PORT ALLOCATION Hexidecimal Port Address Function F8 Status Serial Comm channel F9 Serial Communication Channel Data FA Aux Status Cassette tape interface parallel I O keyboard input FB Audio Cassette CUTS Data FC Keyboard Data from J3 FD Parallel Port Data from J2 FE Display Status FF Sense Switch S2 1 thru S2 8 OUTPUT PORTS Hex Port Address Function F8 Control Serial Comm Channel F9 Data Serial Comm Channel FA Control Parallel I O C
55. QOv 58 8 aay lt 8 aay 28 18 08 gt lt lt cooouroz HO1v1nWnoov 32 WY 34 Ty dZ 24 JV AOW 84 vz OV 62 AOW 824 22 TW SZ AOW pz AOW 22 14 AOW 04 vI 39 WT AOW 39 11 09 HI 29 31 89 9 69 81 AOW 89 VH 49 WH AOW 99 TH AOW 69 79 JH 69 c9 OH 19 09 4S 35 as OS 8S VS O3 69 AOW 8S 1002 TO 33 29 ao v g Wg 19 38 og 22 9 XIQGNdddV 4 Ayquenb 14 91 e sanera 1811 uoisseJdxo JO juejsuoo 910 AOW ZS AOW 9S AOW SS 75 68 AOW 29 15 AOW 05 AOW dp AOW ar AOW OP ap AOW VP AOW 6 AOW AON 2 AON 9 AON Sv 77 AON cv AOW 1 AON 9 3AOIN 3 83 3 94 dON 00 TOYLNOD ul Wu Zl 084 dO 20 1319108 1010 JE 4216 VND 32 VV 46 OHOX 83 51119345 1995 63 HIX 63 dO
56. QUANTITY No Designator Lockwasher Internal Tooth H4 16 859 48 Lockwasher Spring 4 8 8 56 Hex Nut 4 40 16 X 8 amp 9 51 Screw Machine metal 6 32 x 1 2 8 X 9 amp 10 40 Screw Self tapping 6 32 x 5 16 1 9 43 Screw Sheetmetal 6 x 1 4 32 X 8 amp 9 45 Lockwasher Internal Tooth 6 8 X 8 amp 10 49 Washer Flat 6 18 X 8 amp 9 56 Screw Machine 10 24 x 3 8 8 X 9 42 Screw Machine 10 24 x 1 2 9 41 Screw Quick Connect Knurled 2 X 10 33 Cable Flat 20 wire i X 10 23 Assembly Keyboard X 10 3 Cable AC Power 3 wire 1 X 10 36 Subassembly Sol Power Supply 1 X 9 1 Subassembly Sol PC 1 X 10 2 Subassembly 2708 9216 Personality Module 1 X 10 8 REV C VI 3 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI A B C SO Washer A Flat Head Wood Screw C Binder or Pan Head Screw B Sheet Metal Screw D Thumb Screw Figure 6 1 Types of screws used in Sol cabinet chassis assembly _ 70 9 00 o 00 Keyboard Bracket Backplane Bracket Right Angle Gusset Bracket Left Gusset Bracket Right Power Supply Subchassis Bracket Figure 6 2 Brackets used in Sol cabinet chassis assembly Rev A VI 4 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION 6 3 2 Electrical continued 4 DO NOT press the tip of the soldering iron on pads or traces when installing components and or attaching leads to a PC board
57. SOLOS ando CUTER 1 5 Ws Address 16 SUBROUTINES 2900 COOL C004 C007 COOA COOD COLO COLS C016 C019 CUTE C022 Label START ENEE RETRN FCLOS RDBYT WIBYI RDBLK WRBLK SOUT AOUT INP AINP Length JUMP TABLE Function This byte allows power on reset of SOLOS It TS DD Tor SOLOS and IE for CUTER Providing an easy means of differentiating the exact operating system in use This lt a Enter SOLOS Enter Enter hinter file Enter file Bx er based at this command here here here here here on a CO CO CO CO CO JMP to the power on reset pornt Lo control ToO mode processor open a tape file close a tape file read a byte from an open tape write a byte to an open tape read one tape block into memory header Enter here to write one tape block from memory based on a header Enter here to output the character in register B to the current system output pseudo port pointing to the byte containing the current system output pseudo port value This is always an LDA Enter here to output the character in register B to the pseudo port specified in mter Here to Obtain Sstatus character from the current system input pseudo port into register byte containing the current system input pseudo port value This
58. Tantalum Electrolytic Capacitor Regulator IC or Power Transistor TO 220 Electrolytic Capacitor vertical mount Metal Film 1 Precision Resistor PLN 142 PIN 17 Nore PIN1 MAY BE INDICATED GOLD BY CORNER Dot ED Bu T OvUTt 2200 Carbon Film Resistor Dual Inline Package DIP IC 5 gold 10 silver 8 14 16 24 or 40 pins Figure 3 1 Identification of components 5 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION III 3 3 ASSEMBLY PRECAUTIONS 3 3 1 Handling MOS Integrated Circuits Many of the IC s used in the Sol PC are MOS devices They can be damaged by static electricity discharge Always handle MOS IC s so that no discharge will flow through the IC Also avoid unneces sary handling and wear cotton rather than synthetic clothing when you do handle these IC s 3 3 2 Soldering IMPORTANT 1 Use a fine tip low wattage iron 25 watts maximum 2 DO NOT use excessive amounts of solder DO solder neatly and as quickly as possible 3 Use only 60 40 rosin core solder NEVER use acid core solder or externally applied fluxes 4 To prevent solder bridges position iron tip so that it doespnot touch adjacent pins and or traces simultaneausly 5 DO NOT press tip of iron pad or trace To do so can cause the pad or trace to lift off the board and permanently damage the board 6 The Sol PC uses circuit boa
59. These are not used in the Sol 10 but they are supplied to the backplane board in the Sol 20 to drive S 100 Bus modules In the case of the Sol 20 the power transformer T2 has an additional 8 volt secondary winding and a third bridge rectifier FWB3 to supply 8 V dc at 8 amps output of FWB3 is filtered by C9 and controlled by bleeder resistor R13 Again this voltage is supplied to the backplane board in the Sol 20 Sol 20 also includes a cooling fan powered by the AC line voltage OD ool PC CIRCUITE DESCRIPTIONS Os Oech CPU and Bus Refer to the CPU and Bus Schematic in Section X Page X 15 A crystal two inverter Sections 1792 and Tour D flrip filops U90 and associated logic make up the Clock Generator The two U92 sections function as a free running oscillator that runs at the crystal frequency of 14 31818 MHz R133 and R134 drive these two sections of U92 into their linear regions and Col and 64 provide the required feedback loop through the crystal 077 a permanently enabled tri state non inverting buffer amplifier fur nishes a high drive capability This fundamental clock frequency is fed directly to the Video Display Generator and to the clock inputs of 090 090 is a four stage register connected as a ring counter that is reset to zero when power is applied to the Sol This reset is accomplished with D8 R104 and C39 Ihe bits contained in the ring counter shift one to the right with every positive goin
60. U99 Also C47 charges through R117 for several usec at which point pin 10 of U98 is brought to the opposite polarity The output from U99 then goes high A series of positive pulses with a pulse width approximately equal to the R117 C47 time constant 10 usec and occuring at every transition of the 2400 Hz signal appears on pain or U99 This circuit thus operates as a frequency doubler in the low speed mode to provide a 4800 Hz clock for Jb Ihe 2400 Hz signal from which the U101 clocks are derived al so produces the 1200 Hz clock signal for 0100 As a result the 1200 Hz signal changes state following a propagation delay after the 2400 Iz signal falls PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON ALII As previously stated the second stage of 0101 is allowed to change state on the positive going transitions of the OUTPUT CLOCK as long as the data out of the synchronizer 15 a 1 The end result is an output on pin 14 of U101 that is one half the clock frequency 1200 Hz and 2400 Hz in the high and low speed modes respectively Assume the data stream out of the UART goes low 0 On the next rising edge of the 1200 Hz signal U100 will reset with Q low and Q high low reset on pin 4 of 0101 enables the first 0101 stage to toggle on the next rising edge of the OUTPUT CLOCK which oc curs 1 2400 second after the synchronizer output falls Remember that OUTPUT CLOCK moves from a low to a high s
61. and heat Sink to board with a 6 32 x 1 2 Nylon screw lockwasher and nut Insert screw from back solder side of board and drive nut finger tight Posrtron FWRI wath lead to the right on heat sink determine how leads must be bent as you did for 01 and bend leads Apply heat sink compound leads lead to right and fasten FWBl and heat sink to PC board with a 4 40 x 5 8 screw lockwasher and nut Insert screw from back solder side of board and drive hut finger tight Position SCR1 IR106B2 or MCR106 2 on heat sink with component nomenclature up and prepare it for installa tion as you did 01 and FWB1 Apply heat sink compound to SCRI the heat sink and both sides of the circular mica insulator Place the mica insulator between the heat sink and SCRI insert leads and fasten SCR1 insulator and heat sink to PC board with a 4 40 x 7 16 screw lockwasher and nut Insert screw from back solder side of board and drive nut finger tight Check alignment of heat sink SCR1 01 and FWB2 and tighten the three mounting screws Solder all leads and trim if required Wipe off excess heat sink compound if necessary NOTE The heat sink may have to be repositioned when you mount the Sol REG on the power supply subchassis This will require that you loosen the mounting screws for SCRI 01 and FWB2 and retighten them after repositioning the heat sink Step zl Connect two wire cable assembly
62. begin program execution at location specified by tape header information addr Note that the TYPE byte determines if the file is of the auto execute type Exemples SET 200 Result The auto execute address of 200 Hex will be written onto the tape header when the next SAVE command is lssued Custom Input Output Commands Ihe next SET commands set address pointers to custom input and out put driver routines when SET I 3 and or SET O 3 are used These custom 1 O drivers must meet the SOLOS I O drivers requirements See the SOLOS software listing for model input routine Set Custom Output Command SET COUT addr This command informs SOLOS software where the user defined output routine specified by addr is located I Vg SET COMMANDS Cont The Custom Output driver requirements are 18 The addr address word in the SET COUT command will equal the starting address of the output routine 2 It is the user s responsibility to save registers prior to any modification of the register D Ihe B register will contain the data passed from SOLOS for Output routine 4 The output routine will end with a RET instruction or equi valent Set Custom Input Command SET CIN addr This command informs SOLOS software where the user defined input routine specified by addr is located The Custom Input driver requirements are Ta The Trader address word xn che SET CIN command will eque che Starting address of
63. cause before proceeding with assembly If the Sol PC passes this test turn monitor and power supply off disconnect power cable and proceed to Step 43 Step 43 Install the following resistors in the indicated locations Bend leads to fit distance between mounting holes insert leads pull down snug to board solder and UD Sm LOCATION VALUE ohms COLOR CODE RLS T ad brown green red R14 5174 RLS La M R6V Look Step 44 Using two 4 40 x 5 8 binder head screws two 4 insulating washers two lockwashers and hex nuts install 30 pin right angle edge connector in location J5 Insert Screws from back solder side of board and place an insu lating washer on each screw on front component side of board Position connector with socket side facing right place over screws and seat pins in mounting holes Then place lockwasher on each screw start nuts and tighten solder prins to board PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL COMPUTERT TON LLI Step 45 Using four 4 40 x 1 4 1 head screws lockwashers and hex nuts install two brackets 501 1040 for personality mod le Xn arsa To E WI 1 brackets Over the mounting holes as shown in Figure 3 11 Insert Screws from front component side of board place lockwasher on each screw on back solder side of board start nuts and tighten ORS E I
64. character blanking switch selectable with S1 3 is accomplished with one NAND gate 060 and one NAND gate in 061 When a control character is present the Data Latch 026 and 027 pins 3 and 15 of U26 are high Assuming the blanking option is se lected S1 3 closed the output of U60 LOAD CLOCK is gated with the control character bits by U61 to clear the video parallel to serial converter 041 041 then loads all zeros instead of the character Video blanking is initiated by the PRE BLANK or COMP BLANK pin 14 of Blank Latch U42 inputs to U59 a three input NOR gate The third input the video output pin 6 of exclusive OR gate 074 15 blanked when any of the two blanking inputs 15 active 1 11 26 AVIdSIO O3GIA 9 8 aniy N33H2 40 NOILYOd Q3MNY 18 33895 30 NOlLMOd 14510 Len S Nid 318VN3 NVOS 341199 EEN Nid BBfl t NIGJONASA re aen 5i Nid SOdA 1V2OLLH3A SH3 10VHVHO Y9 40 SINI 91 Ol NId ONASH o 3A TE Patiala ol Nid N3345S 205 s pez 0 2 H31Nf102 LXIL ini H i x opnluainno OI Nid dSIOA ue 2
65. complement of PKD minus 1 Thus the data active low is strobed into U12 on the first count cycle During the third count it will be strobed again and a high is read in When the key is released a low is strobed in again As a result a high active pulse appears on the output line related to the key that was closed for the duration of the key closure SHIFT and SHIFT LOCK on pins 11 and 10 respectively are applied through U23 inverter stages to NOR gates U13 and 014 These are connected as a cross coupled flip flop An active SHIFT sets this pum oor UL Lo make outpuc prp 6 or prr or Ula high The latter is connected to prr 205 010 512 4 bit ROM 018 is programmed to output the high order four bits of the data Bo UL according to the states pins 15 2 Ine 3138 1461 Ls set to a high on pim if is active As can be seen the shift bit to U18 is high by virtue of the low on pin 6 of U13 and it will remain so until SHIFT again causes U13 14 to change state When output pin 6 of 014 is high pin 12 Of U24 Low to turn light emitting diode LEDI This LED XS located in the SHIFT_LOCK key and indicates the keyboard is ina locked shift condition When UPPER_CASE 15 active pin 7 of 012 goes high to clock D flip flop 015 on pin 3 This flip flop is connected to operate ina toggle mode the UPPER_CASE clock pin 5 of 015 goes to make pin 2 of 018 low The hi
66. cover to rear of main chassis Step 43 Re install fuse and plug power cord into receptacle BE SURE POWER CORD IS NOT PLUGGED INTO 110 V ac OUTLET See CAUTION on Page VI 19 REV B VI 18 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Step 43 continued CAUTION NEVER REMOVE OR INSTALL FUSE WITH POWER ON Step 44 Remove backing from connector identification label and affix it to rear of top cover Position label just above Sol PC connector opening in cover so that J9 is aligned with left most as viewed from rear of Sol subminiature phone jack and J1 is aligned with right most 25 pin female connector Step 45 See Detail on Drawing X 8 Remove backing from serial number label and affix it to rear of top cover Position label to right as viewed from rear of Sol of fan opening in cover Step 46 Affix self stick protective pads to bottom of Sol as shown in Figure 6 8 You have now completed assembly of your Sol Terminal Computer It is ready for use as a stand alone computer CRT terminal Con gratulations on a job well done Proceed now to Section VII to test and learn to operate your Sol C9 IL L 8I Bottom of Sol Protective Pads Front Figure 6 8 Protective foot pad installation REV B VI 19 PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VLI died INTRODUCTION Information in this section will help you to become familiar with
67. displayed A gt Keyboard flag logic 053 54 70 71 11 Will not respond to commands A gt Places question mark on screen in command U29 89 PHASE 1 and 2 timing incorrect B gt Stack crash bad RAM 03 10 12 Will not read cassette tape doesn t give error message Will not respond to CAT command also A gt Bad AGC circuit Q3 4 5 0108 129 B Bad read logic 098 99 190 112 113 119 2 2 gt Bad UART U69 1 Bad data input see A and 2 Bad data output UART 3 Bad status in UART U22 23 24 36 93 94 4 Bad status output D gt Bad clock to UART U85 86 109 lll 112 E gt PLL inoperative 0110 check balow NOTE CHECK VALUES OF ALL DISCRETE COMPONENTS AT 13 Will not read cassette tape gives error message A gt Bad PLL 0110 or PLL not adjusted correctly B gt clock to PLL 011 112 gt Bad UART 069 gt Two Baud Rate Switches at one time 53 14 Will not write to cassette A Bad UART U69 B gt Bad clock to UART 085 86 109 11 112 gt Bad write logic 098 99 100 101 109 NOTE CHECK VALUES OF ALL DISCRETE COMPONENTS AT OUTPUT 15 Motor control of cassette inoperable won t turn off or on A Bad control logic U97 B Bad relay Kl K2 16 Power supply failure A No 45V U2 Ql 2 3 Dl SCRL EWBl NOTE 1 Check reference voltages on U2 NOTE 2 Check values of all discrete components B R
68. entry point address C022 This entry point is used to input one character or status from any pseudo port Register A on entry indicates the desired input pseudo port from 0 to 3 Because this entry point is a combination status get character routine it is the user s responsibility to interpret return flags properly When a character is not available the zero flag will be reset and the character will be placed into register A What this means is that 1f the user wants to wait for a character to be entered simply follow the CALL AINP or SINP with a JZ jump if zero instruction back to the call A combined status get character routine is very important when allowing user written input routines Dy SOLOS Output Entry Poms SOUT entry point address 019 This entry point will set register to the current system out put pseudo port The current system output pseudo port is changed by using the SET O command After setting register A this command proceeds by executing an AOUT next definition 17 18 SUBROUTINES qC eGonts AOUT entry point address This entry point is used to output one character to any pseudo port Register A is assumed to be a binary value from 0 to 3 indicating the desired output pseudo port Register will contain the character to be output On return the PSW and Register are undefined All other registers are as they were on entry SOLOS VDM Display Driver
69. following measurements Volt ohm Meter Check continued on Page 111 16 PROCESSOR TECHNOLOGY CORPORATION ool PC SINGLE BOARD TERMINAL COMPUTER SECTLON ELI CHECK POINT Uda 7 U91 Pin 6 091 Pin 11 0104 7 ULUA Pind SIGNAL OsGcil labor Qutput Clock Divider Output Clock Divider CLOCK 01 Clock 2 Gnd 4V Gnd LAV Gnd 27 Gnd 392 WAVEFORM 14 3 MHz square wave This is not a perfect square wave It in fact more resembles a poor sine wave 70 ns 430 ns ZO TS 230 70 ASO ns 270 ns 50 Clock Cuorcurt waveforms EELSES PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL coMPUTER Sp TION LEL e Test 184148 1 or Disc 1N914 10K ohms 001 ufd Disc Connect to Ground Figure 3 3 Test probe for Steps 16B and 25B NOTE 1 Ihe probe shown in Figure 3 3 can be made using parts supplied with your SOl PC kit Since these parts will be used later in the Sal PC assembly DO NOT shorten the leads or otherwise alter the components Assemble the probe using tack soldering technique NOTE 2 Make sure you have a good ground con nection between the meter probe and SOP CE At pun Lot you should measure or higher A significantly lower reading indicates a
70. ground connection This pad is too small the wire should be run instead to the pad immediately to the right of pad T3 also a ground connection This pad is shown on the legend as pad X 10 NOTE Some legends incorrectly show this pad as a second pad X 5 Make sure that the red white lead goes to the pad labelled X 5 which is between C5 and FWB2 To avoid confusion when you reach this point in the assembly procedures cross out X4 above R8 in Step 27 and write in its place X10 to right of T3 If pad X10 is incorrectly labelled X5 the note should read X5 to right of T3 Also make a note reading See Change Notice 14 CN 14 11 77 page 1 of 1 Ref ECN 10199 Processor Technology Processor Technology 7100 Johnson Industral Drive 415 829 2600 Corporation Pleasanton CA 94566 Cable Address PROCTEC Sol MANUAL CHANGE NOTICE CHANGE NOTICE 15 SUBJECT 2708 Personality Module value change for Rl and R2 If you have a Personality Module using 9216 ROMs ignore this notice The 100 ohm values for 1 and R2 shown in your manual may cause over heating under certain conditions Use 130 ohm 1 2 watt 5 resistors instead which may have been included in your kit To make sure your documentation reflects the improvement note the change in pencil at the following places 1 Section IV Table 4 1 2 Section IV Step 2 3 Section X Drawing X 6 Assembly 4 Section X Drawing X 22 Schematic 731009 1
71. gt 22 A 2442774 52 IN 2 From 122 FKD 24 1 6 77 PROCESSOR TECHNOLOGY CORPORATION 6200 HOLLIS STREET EMERYVILLE 94608 415 652 8080 Sol MANUAL ADDENDUM Sol MANUAL ADDENDUM 3 Dee Cassette Recorders for use with Sol Not all audio cassette recorders are suited for data storage use with the Sol The following models have been tested and ap proved by Processor Technology 1 Panasonic RQ 413AS 25 Realistic CTR 21 Some users have reported unsuccessful results with the Panasonic RQ 309 and the J C Penny Catalog 4851 0018 you should wish to select a different model the following features included on the models above are necessary l An AUX input Although the Sol can be jumpered for low level Microphone level input the procedure is no longer recommended 2 A digital counter The counter is necessary in locating programs on the cassette 3 A tone control The existence of a tone control is one indication of high quality electronics Even though a recorder has the three features there is no guarantee that it will work properly for the purpose Recorders vary greatly in the quality of their electronics If possible test the recorder with a long file before purchasing it in both record SAVE and playback GET or XEQ mode If the recorder is not working properly either you will get an error message or you will find differences between what was recorded an
72. in a read only memory ROM that is plugged into the computer or the Sol random access memory RAM For a description of the CONSOL and SOLOS Personality Modules refer to Section IX in this manual and the SOLOS Users Manual respectively With the SOLOS Personality Module installed the computer is in the command mode when power is applied to the Sol Command mode is a sort of home base from which excursions may be made into other programs An analysis of three levels of programs will make the concept of command mode more understandable At the lowest level of software are the instructions which the 8080 CPU central processing unit the brains of the computer PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES Table l 501 Operating Controls and Ihevr Functions CONTROL FUNCTION ON OFF Switch Connects and disconnects primary power to Sol See Figure 7 1 ROT Restart Permrts manual restart Of Dol Curing power off Useful for test purposes BLANK Switch Determines if control characters are displayed pe OF NOT POLARITY Switch Selects normal white characters on black background Or reverse VIRGO display owlikches 51 5 6 DOWD 7 Permits direct data entry to processor Mie ui eran BAUD RATE Switches Sets operating speed of serial data interface g PS amp PI Switches Selects no parity even pa
73. into the memory location currently EN on the address bus 69 PS PROJECT STATUS not used by Sol PC electronics 70 PROT PROTECT not used by Sol PC electronics 71 RUN RUN used by Sol PC electronics 72 PRDY PROCESSOR READY Memory and I O input to the CPU Board wait circuitry 73 PINT INTERRUPT REQUEST The processor recognizes an interrupt request on this line at the end of the current instruction or while halted If the processor is in the HOLD state or the Interrupt Enable flip flop is reset it will not honor the request 74 PHOLD HOLD Processor command control input signal that requests the processor enter the HOLD state allows an external device to gain control of address and data buses as soon as the processor has completed its use of these buses for the current ________ machine cycle 75 PRESET RESET Processor command control input while activated the content of the program counter is cleared and the instruction register is set to 0 76 PSYNC SYNC Processor command control output provides a signal to indicate the _____ beginning of each machine cycle 77 PWR WRITE Processor command control output used for memory write or I O out put control Data on the data bus is stable while the PWR is active 78 PDBIN DATA BUS IN Processor command control output AVII 5 indicates to external circuits that the data bus is in the input mode S 100 Bus Definitions continued PIN NUMBER SYMBOL NAME
74. it may be used by a program to meet a specific need 7 7 14 REPEAT Key Ihe REPEAT key generates no character and is consequently not displayed Pressing REPEAT shifted or unshifted and another key at the same time causes the other key to repeat at an approximate rate of 15 times per second as long as both keys are held down Pressing REPEAT at the same time as UPPER CASE performs a restart See Section Jae Ol page 1 12 7 7 15 SELECT Key Pressing this key shifted unshifted generates the code 80 and Causes ool to enter che command mode 7 7 16 CLEAR Key Pressing CLEAR shifted or unshifted erases the entire screen and moves the cursor to its home position upper left corner of the Screen VII 24 PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VLI Tel welt Cursor Control HOME CURSOR and Arrows Keys Five keys control basic cursor movement They are HOME CURSOR and the four keys with arrows None are affected by SHIFT status and none are displayed or transmitted Pressing HOME CURSOR moves Lhe Cursor home posrctron the first character position in the upper left corner of the screen To move the cursor up down left or right press the applicable arrow key Each time you press a key the cursor moves one unit in the direction you wish one space horizontally or one line vertically These keys may be used with REPEAT The cursor will not move across any margin of
75. o 0i U23 OCCUTS A low on pin 8 of U25 also resets one half of D flip flop Ull at pin 13 which causes output pin 9 to go low On the rising edge of the inverted 6 usec clock from US the second 011 stage sets and out VIII 42 PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECT LON ALII put pin 5 goes low to clear the first stage The high on output pin 6 1S inverted by NAND gate UIO to supply a low active STROBE on pin 3 QT uli Note that Jl on the keyboard connects to 03 on the Sol PC The next inverted 6 usec clock resets the second 011 stage We thus have a 6 usec strobe pulse following the latching of data into Ul and HZ The complement of KEY minus 1 on output pin 8 of U26 is fed to input pin 10 of NAND gate 016 and translated to high on prn Ou The other input on pin 9 is high at this time since it is driven by the signal which indicates the third count cycle A three input gate U27 thus has high on pin 2 A second input pin 1 is KEY which is active high from the first count cycle of the key clo sure The remaining input on pin 13 rs supplied by pin 11 016 and it is low only when the repeat function is operating 027 15 consequently satisfied and outputs a low on pin 12 This low appears at pin 5 of NOR gate Ul6 Pin 4 of U5 is high CALS pointe by virtue Or low on pin txot ULG which indicates the third count Thus the high on pin 6 of 016 will be stored in the s
76. of R14 do not short to other leads of SCRI or DI Solder the lead to SCRI but not the lead to R2 330 ohms Step 3 Wrap one lead of R13 330 ohms around the same right hand lead of R2 330 ohms with the position of R13 parallel to Dl 1N5231B as shown below Solder the two leads which are wrapped around R2 Step 4 Wrap the leads of D5 1N270 around the anode end opposite banded end of Dl and the loose end of R13 330 ohms Make sure the cathode banded end lead of D5 is connected to R13 not Dl Solder both ends of D5 Step 5 Trim all excess lead lengths check lead dress inspect for possible shorts or solder bridges The parts you have added are shown on the schematic Drawing X 16 with the exception of D5 which may be added by hand Add the underlined words to the second paragraph of Step 30 Section 6 6 3 pan head screws 4 lockwashers and 6 flat washers Place lockwasher then flat washer on screw Add the following item to Hardware in Table 6 1 8 each 6 flat washers Add the following sentence at the end of Section 2 2 1 Refer to the assembly drawing on page Z of Assembly Procedure Change Notice 46 2 REV C as you assemble the regulator CN 6 2 page 1 of 2 REV C Ref ECN 10241 N Cut these traces on the solder side of the PCB and add R13 R14 and C8 as shown IAN Mount Rl approximately 15 from board surface CN 6 2 page 2 of 2 REV C Item Page No Figure or Step No C
77. on power supply subchassis over left rear area of main chassis and lower into place Attach expansion chassis to main chassis using nine 6 x 1 4 sheet metal screws and five 6 flat washers Five screws fitted with 6 flat washers are driven through the bottom of the main chassis into the expansion chassis three are driven through the left side of the main chassis into the expansion chassis and one is driven through the lower left corner of the back side of the main chassis into the expansion chassis Step 21 Attach left end of power supply subchassis bracket to expansion chassis as shown in Drawing X 9 Drive one 6 x 1 4 sheet metal screw through expansion chassis into bracket Step 22 Route coaxial cable from connector on fan closure plate along left side of power supply subchassis to connector on expansion chassis Step 23 Using the 6 x 1 4 sheet metal screw you removed in Step 15 re attach fan closure plate to power supply subchassis Make sure side lip on plate is on right side of expansion chassis side wall See Drawing X 9 Attach fan closure plate to expansion chassis with two 6 x 1 4 sheet metal screws Drive screws through expansion chassis into fan closure plate NOTE If lip on fan closure plate and expansion chassis are not in contact insert one or two 1 2 flat washers as needed between the two surfaces Place washers so screws pass through them Step 25 Connect free end of coaxial cable from connect
78. output latches and the SHIET SHIPYT LOCK UPPER CASE LOCAL flip flops Dt also nar ones STROBE at pin 1 of NAND gate 010 5 SECTION IX SOFTWARE Sol TERMINAL COMPUTER Processor Technology PROCESSOR TECHNOLOGY CORPORATION Sol SOFTWARE SECTION IX CONSOL CONSOL is a 1024 byte program designed to allow the Sol TER MINAL COMPUTER to operate as a standard CRT terminal and to provide access to the essential computer capabilities of the Sol Using CONSOL self test and small diagnostic programs can be entered to system memory and executed This in addition to providing verifica tion of correct system operation helps in finding errors in case of a malfunction In addition CONSOL contains Standardized entry points for all normal I O operations These routines are common with all Sol System Software allowing each personality module in the Sol line to interface with external programs in an almost identical manner A cassette read routine is also resident in the CONSOL mod ule allowing Sol Software to be loaded and run in a system with additional memory Sol System Software as of November 1976 includes BASIC FOCAL a Scientific Calculator and numerous game packages including 8K assembly language version of STARTREK called TREK80 When power is applied to the Sol unit CONSOL initializes the system RAM area clears the screen and enters the terminal mode In this mode the Sol System acts as a standa
79. parameters DNTRODUCTION Gone Only the first two letters of the command expressions must be typed when entering a command expression The underscored letters in the following Quick Command Reference List Quick Command Reference List COMMAND PUNCT ION Console EXEC addr Begin program execution at addr ENTR addr Enter data into memory starting at addr DUMP Dump Memory date adari To addtz TERM portin Cportout Enter Terminal Mode CUST name addr Insert or remove CUSTOM command Tape GET name unit addr Get a tape file into memory SAVE name unit addrl addr2 addr3 Save a file from memory to tape XEQ name unit addr Get then execute a tape file CAT unit Catalog tape files Sig SET S data Screen character rate SEL I BDQIE Input CO SOLOS OUtDpOE POPC CO TOLOS SET N data Number ort NULLS following CRLF SET XEQ addr Auto execute addr TARE Qor 2 0 1200 baud 1 300 baud OET daca Type byte header SET COUT addr Custom output addr SET CIN vadar Custom input addr SET CRC data Allows ignoring of tape CRC Read Errors i INTRODUCTION cont With a Sol or CUTER on a Processor Technology GPM board a power on performs a reset which causes a SOLOS system reset The Sol user may initiate this system reset anytime by simultaneously pressing the upper case and repeat keys A SOLOS system reset enters SOLOS into COMMAND mode When in COMMA
80. power is on Figure 7 7 Connecting Sol SDI to communications modem Vb PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES In Figure 7 8 the Oliver OP80 Manual Paper Tape Reader is used to illustrate a typical PDI interconnect CHANGING THE FUSE Sol is protected with a 3 0 amp Slo Blo fuse housed on the rear panel see Figure 7 1 Page VII 6 To remove the fuse turn 301 Lr drscon ect power cora turn fuse post Cap One quarter turn counterclockwise pull straight out and remove fuse from cap To install a fuse insert fuse in cap push in and turn one quarter turn clockwise J2 Su DL CONNECTOR Rey Rev E TDO LOL LD2 Dp ID4 105 Im POWER SUPPLY 5 de is not available at J2 The use of an external 5 V power supply with its ground connected to Pin 1 of J2 Sol chassis ground 15 recommended Sod PG Board Figure 7 8 Connecting Sol PDI to parallel device de A VIII IABLE FIGURE THEORY OF OPERATION ou INTRODUCTION OZ OVERVIEW ome BLOCK DIAGRAM ANALYSIS 501 8 3 1 Functional Elements And Their 8 3 2 Typical System Operation Keyboard Data Entry and SDI UART Transfer and Display 8 4 POWER SUPPLE DESCRIPTION CIRCUIT DESCRILPIIONS 5955 41 and Bus 8 5 2 Memory and Decoder 8 545 Our put 8 5 4 Display Section
81. raster numerous black lines cutting across the raster and a Stable raster If you cannot obtain these conditions locate and correct the cause before proceeding NOTE For a stable presentation a few moni tors especially modified TV sets may require a higher sync amplitude than that supplied by the Sol PC Ln Such cases increase sync amplitude re d ecrng the value of R90 DO NOT DECREASE BELOW 225 OHMS If the synchronization circuits are operating correctly turn monitor and power supply off disconnect the power cable and go on to Step 27 Step 77 be xobllownng 2575 Sm Che Xmoucabted CLONS Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board indicate the location of pin 1 OF CACA LGs Step 27 continued on Page 111 23 TIIT 22 PROCESSOR TECHNOLOGY CORPORATION IM 501 SINGLE BOARD TERMINAL COMPUTER NO H o DS U2 DOES U13 0297 026 02 9 U30 22 041 042 044 061 089 NNN NNN gt gt gt MOS device CYPE 029 PATON LS 4140295 241212527 MCM6574 TA PAOLO 174151257 4166 PANO LTS 741500 741510 1415367 gt 2 20 Check display GI EQULUS Set 51 switches as follows NOs L turough 22 NO ON Refer to CAUTION SC ELON Ir
82. recorder has only a microphone input re move the I to J jumper you installed in Step 69 and install a jumper 24 bare wire is recommended between the I and H pins Otherwise leave the I to J jumper go to Step 72 Step 72 Install 100 pin edge connector 211 Using two 4 40 x 7 16 binder head screws install 100 pin edge con nector in location Jil center or PC board Seat che pins in the mounting holes Then thread screws from front com ponent side of board into the threaded inserts that are pre installed in the Jll mounting holes Tighten screws and solder pins to board Step 73 Look on the rear of the board on the component side where the Personality Module plugs in for a mark Rev E If your board is marked this way complete this step otherwise ignore this step Connect a jumper of 24 a w g insulated wire between pin 13 of 0107 and the feed Enough pad d acenb Co pam 21 Or Solder check for solder bridges and trim excess wire strands if needed The installed jumper is shown below us J Pin 14 e 0107 0106 Solder side of board shown 12121520 PROCESSOR TECHNOLOGY CORPORATION Sal PC SINGLE BOARD TERMINAL coMPUTER SECON 3 044 For 625 Lane Video The European televisions standard defines a raster of 625 lines at a field rate of 50 Hz The horizontal rate of the U S standard 15 750 Hz 15 maintained Only the number of scan lines on
83. red 7 2 R19 LO brown black black ru R20 oH brown black red 1 1 K Ww R22 3 K orange black red R23 1 brown black red R2 4 1 K Ww 25 brown green red R26 680 blue gray brown 33 K orange orange orange 60 R28 Laok brown green red R29 dI cud e Continued Page 6 PROCESSOR TECHNOLOGY CORPORATION Sol KEYBOARD SECTION V LOCATION VALUE ohms COLOR CODE R30 brown green red 1 baok M M R32 68 blue gray orange R3 brown green red R34 red red red Hev B Step 4 Install Zener diode 1N5221B in its location to the left of R17 Position Dl with its dark band cathode at Ele JDottom Step 5 Install Ol 02 and 09 24274 and Q5 through Qo 2N3640 in their respective locations at the top center of the board The emitter lead closest to flat side of case 1s oriented toward the right of the board and the base is oriented toward the top Insert leads until transistor is approximately 3 16 above surface of circuit board solder and trim Step 6 Install resistor networks RX1 and RX3 2 2K ohms and RX2 and RX4 33K ohms in their respective locations just above the keyboard pads Install each network so that the dot on its package is positioned next to the foil square on the circuit board Recheck values before soldering CAUTION IHESE RESISTOR NETWORKS ARE DELICA
84. return the board to Processor Technology for replacement If the board 18 NOL derectrive proce d to nexe paragraph Rev A ial PROCESSOR TECHNOLOGY CORPORATION ool PC SINGLE BOARD TERMINAL SBECITON Personality Module Assembly Since the personality module is required for testing the Sol PC in the later stages of its assembly we suggest that you assemble the personality module first In your Sol PC assembly will proceed uninterrupted Assembly instructions for the personality module are provided in Section IV of this manual If you wish to wait to assemble the personality module until it is needed go on to Paragraph 3 60 3 25022 SOl PCB Assembly Test Refer to Sol PC assembly drawing X 3 Dur Install wach socket che drcated location with xts end orrented as shown onthe circuit board and assembly drawing Take care not to create solder bridges between the pins and or traces Refer to footnotes at end of this step before installing U105 INSTALLATION TIP Insert socket pins into mounting pads of appropriate location On solder back side of board bend pins at opposite cor ners of socket e g pins 1 and 9 on a 16 socket outward until they are at a 45 angle to the board surface TAIS secures the socket until it is soldered Repeat this procedure with each socket until all are secur
85. that the PSYNC amp 102 Signal om pin oot UJ Torces U70 TO set during the middle of PSYNC refer to CPU and Bus discussion U70 cannot clock until pin 5 is released and this occurs simultaneously withthe low to hlgh transition Of 2 PRDY is thus low immediately after pin 10 of 053 goes low and remains in that state from the mid dle of PSYNC to the first positive going 2 after PSYNC This is the time the CPU tests the status of the ready lines PRDY and XRDY either is low the CPU enters a WAIT state 053 70 and 71 thus guarantees that the CPU enters one WAIT state during cycles in which an input output or memory reference 15 made U35 and 36 the Output and Input Port Decoders respectively decode the higher order eight address bits ADR8 15 All Sol ports have a hexadecimal F 1111 in their high order tour bits cADRIZ2 I5 are 21587 The second hexadecimal digit is also never less than eight This means that ADR11 is always 1 port address These five address bits are thus NAND gated in 023 to provide one of the enables 035 and 36 Note that the ADR14 15 combination is derived from the output on pins 3 and 11 of the U22 exclusive OR logic This is permissible since no I O operations are performed during the first four start up cycles of the CPU The A B and C inputs to U35 and 36 ADR8 9 and 10 respec tively specify the second hexadecimal digit in the port address and are decoded to supply the indica
86. the input routine is the user s responsibility to save registers prior to any modification of the register The input routine combines actually inputting the character along with STATUS The routine returns either a zero flag indicating no character 1s available or the character in Register with a non zero flag The calling program can then take appropriate action based on a zero or non zero condition pel CRE Perot CRC data This command is used to specify whether or not the standard CRC error checking routines are to be used When a value of FF is specified all further tape reads will ignore CRC errors Any value other than FF indicates standard error checking is to be in effect This command is very useful to allow a tape to be read in which would otherwise not be readable When CRC errors are being ignored it must be remembered that the data read in may not be valid Example CRO ER Result CRC error checking will be set to ignore all CRC errors Set Number of NULLS SET N data This command sets the number of nulls binary zeroes to be output following a carriage return linefeed CRLF sequence The value 15 L2 COMMANDS cont initialized to zero but may be set to any number up to FF hex This command is useful when using output devices requiring a delay following a carriage return Example SET N 3 Result Every CRLF issued by SOLOS will be followed by
87. the line prior to pro cessing the characters This is particularly useful when using the ENter command since the input line can be visually scanned and errors corrected prior to the actual entry of input data to memory Included within COINSOL are routines to read standardized cassette tape Software which is recorded with a sixteen byte header that includes NAME LOAD INFORMATION FILE TYPE and execute address CONSOL because of space limitations 15 unable to search fora 1 2 PROCESSOR TECHNOLOGY CORPORATION Sol SOFTWARE SECTION IX program or file by name After receiving the TLoad command CONSOL turns on the cassette player and waits for the next header then uses the header information and loads the file to memory The cas sette recorder must be in play mode and properly connected before executing the TLoad command After loading the data CONSOL returns to the command mode where the EXEC command can be used to execute the just loaded pro gram Also a return can normally be made to the command mode by pressing the MODE SELECT key Space limitations again limited es cape during the header search so if the system locks up in this routine the standard Sol restart must be used To restart the Sol press UPPER CASE and REPEAT keys simultaneously The CUTS cassette interface electronics within the Sol will record or receive data at either of two standard speeds TLoad will accept a parameter to se
88. the long dimension to fit a 4 inline layout 1 Insert pins in the mounting holes from the front component side of board The carrier will hold the pins perpendicu lar to the board 2 Solder all pins from back solder side of board so the solder wicks up to the front side AIV 2 PROCESSOR TECHNOLOGY CORPORATION TM Sol TERMINAL COMPUTER APPENDIX IV 3 Check for solder bridges 4 Remove carrier To install single pins proceed as follows 1 2 3 4 5 Hold board between two objects so that it stands on edge Insert pins in the mounting holes from front component side of board Solder pins from back solder side of board so the solder wicks up to the front side This will hold the pins firm ly in place Insert a component lead into one pin and reheat the solder Using the component lead adjust pin until it is perpendicu lar to board Allow solder to cool while holding the pin as Steady as possible Remove component lead Repeat this procedure with other pins NOTE If cooled solder is mottled or crystal lized a cold joint is indicated and the solder should be reheated Check each installation for cold joints and solder bridges AIV 3 PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER APPENDIX V E gt ANODE 0 1 OUTPUT CATHODE NC i EMITTER COLECTOR INPUT BU gt OUTPUT 8 BASI a Trigger Dis
89. the operation of your Sol Terminal ComputeriM Following brief explanations of the operating controls and the two basic operating modes you will put your Sol through some simple operations This should sufficiently acquaint you with the keyboard and control switches so that you will feel at ease with your Sol In addition you will have performed functional tests of all Sol sections except the parallel data interface Detailed descriptions of the control switches are also provided to allow you to gain greater proficiency in their use For the same reason individual keyboard key descriptions are also given They are intended to be used along with the BASIC 5 and SOLOS Users Manuals or if applicable the CONSOL description in Section IX of thus menus Ihe balance of this section supplies instructions for 1 connecting typical peripheral devices to the serial and parallel data interfaces 21 and 22 2 using audio cassette recorders and 3 changing the fuse d d THE OPERATING CONTROLS Sol operating controls are identified and their functions briefly defined in Table 7 1 on Page VII 2 Unless noted otherwise the location of each control 1s shown on the Sol PC assembly drawing in Section X Page 2 BASIC OPERATING MODES FPES WI Command Mode In this mode Sol operates as a stand alone computer under control of the program software contained in the personality module and additional software that is stored in the Sol stored either
90. to Tl 2 in the 501 20 1 a full wave bridge rectifier is connected across the 8 volt secondary green leads The rectified output is filtered by C8 and applied to the collector of 01 01 a pass transistor is driven by 02 with the two connected as a Darlington pair out put of 01 is connected to R1 which serves as an overload current sensor An overload current approximately 4 amps increases the voltage drop across Rl The difference is amplified in one half of U2 an operational amplifier and the output on pin 7 turns Q3 on xn turn steals current from diverts current from the output on pin 1 of U2 This in effect turns the supply off to reduce the current and voltage Note that the circuit is not a constant current regulator since the current is folded back by R6 and R8 The current is reduced to about 1 amp as the output voltage falls BO zelo Divider nebpwork and RIZ returned to volts senses changes in the output voltage If the output voltage is 5 volts the znput on pin 2 or UZ 18 at zero volts UZ provides a positive output on pin 1 if pin 3 is more positive than pin 2 and a negative output for the opposite condition When the output voltage falls below 5 volts pin 2 of U2 goes more negative than pin 3 This means pin 1 of U2 goes posi tive to supply more current to the base of Ql The resulting in crease in current to the load causes the output voltage to rise unt
91. trans mission rate being governed by BYTE WRITE CLOCK The transmission sequence begins with a start bit a low data zero on the UART s TO output It is followed by eight data bits and two stop bits high on the UART s TO output with the num ber of bits being fixed by the connections to pins 34 through 39 of 169 The data from 069 is applied to the D input of D flip flop 0100 which is clocked at 1200 Hz Consequently the output on pin 1 of 0100 follows the input data on pin 5 after the rising edge of the 1200 Hz clock This output is connected to the reset pin 4 of U101 so when the data out of the UART is high the first section in 0101 is forced to a reset condition this condition the J and inputs to the second stage of U101 are held high which allows the flip flop to change state on the rising edge of the clock The clock for U101 OUTPUT CLOCK is 2400 Hz in the high Speed mode or 4800 Hz in the low speed mode This clock is derived from 2400 Hz in conjunction with the low speed select signal in NAND gate U98 and exclusive OR gate U99 In the high speed mode pins 12 and 13 of U98 are held low thus holding 10 of U9S high As a result the 2400 Hz signal is inverted in 099 to become the clock for 0101 Pins 12 and 13 of U98 are held high however in the low speed mode to enable U98 In this case R117 and C47 provide a delay in the U98 gate When the 2400 Hz signal on pin 2 of U99 changes state so does pin 3 of
92. where the legend reads 5V 21 CO 19 12 This legend designates five pads in a row directly underneath On the back solder side of the board there is a small trace which connects the and 21 pad Cut this trace with a sharp knife or scribe point so there is no longer continuity between these pads Form the clipping from a resistor lead or other small bare wire into a loop and insert this jumper between the 5V pad and the 21 pad Solder and trim the leads Next find the two pads between C2 and R6 with legend 16 under the right pad of the pair On the back Solder side Of the board Gut the trace which connects these pads Step 8 Stop assembly at this point and proceed with Sol PC assembly and test up through Step 48 See Section III Then go on to Step 9 of this procedure Step 9 Plug personality module into Jb on apply power to Sol PC and make the following voltage measurements on the personality module with respect to chassis ground MEASUREMENT POINI VOLTAGE Pin 24 of Ul U2 TO A ue Pin 14 of U3 22 Pate UZ V Pare 22 Ulp UZ Ground Pin 7 of U3 Ground kor 2709091 version only Measure between edge connector pin B14 and pin B15 You should measure more than 1M ohms A reading less than ohms indicates a short C Des PROCESSOR TECHNOLOGY CORPORATION Sol PERSONALITY MODULE SECTION Rev C
93. you feel at home with your Sol The preceding command mode operations used the CPU personality module audio cassette interface ACI and the Sol RAM You have consequently just tested the functions of these sections OPERATING CONTROLS IN DEPTH Unless indicated otherwise the locatron the controls described in this paragraph are shown on the Sol PC assembly drawing in Section X Page X 3 VII L2 PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES deo ON OFF Switch See Figure 7 1 on page VII 6 Push this Swritoh 2n CO Turn your Sol Ona Im the ON position Phe switch remains Locked in its Iin position ITO turn your 9d off push the switch again This releases the locking mechanism and the Wid CO LCS OFF rout POSi CLON Restart RST Switch 5 This switch permits you to restart your Sol without turning the power off You should normally leave it in its OFF or run position Set it to ON and then OFF to initialize the Sol circuitry and reset the CPU bo Zero A manual restart with this switch performs the same function as turning the power on or pressing a keyboard generated restart UPPER CASE key with REPEAT key pao mE Control Character Blanking BLANK S173 oet this Switch to xts ON position you do not want control characters see Table 7 4 on Page VII 18 to be displayed on the Screen In the OFF p
94. 0 IR R96 R K TR R98 10 RIO Leok RLOO LO Doo REO S1 9M R103 Lak REZU 100 REZAL 10 E22 10 R123 ao R124 Dg ER REZ D 39 Riz 101 REZO 325K 10 K amp VR2 20 VALUE ohms watt Bend leads to fit distance between mounting holes down snug CO board solder and trim COLOR CODE brown green red 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 77 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 orange orenge bfrowr violet green black red blsck brown brown green red orange orange green brown green red 44 44 orange orange brown blue gray brown brown green red 44 44 7 7 7 7 brown black orange brown green red brown black orange brown green red orange orange green brown green red brown black yellow 1 orange white orange brown green red orange white orange brown black orange orange orange red brown black orange Potentiometer The leads of R80 and its mounting holes form a snug E id ie Take care when installing this resistor PROCESSOR TECHNOLOGY CORPORATION 50 1 SINGLE BOARD TERMINAL COMPUTER Sp TION LEL SS gt gt NN Step 1
95. 0 Stage is at zero As shown in Figure 8 1 this occurs between the Sixth and tenth CLOCKS or 280 nsec 4 x 70 nsec tor 2 04 MHz Operation For 2 863 MHz it occurs between the fifth and eighth DOT CLOCKS for 210 nsec The section of NAND gate U91 with its out put on pin 11 inverts the output 3 of 091 and introduces slight delay to insure there is no overlap between 1 and 2 With the A to B jumper out pin II of 091 is low only when the second stage B of U90 is at zero At 2 386 MHz this occurs between the fifth and eighth DOT CLOCKS for 210 nsec This configu ration xs used for the 9090A 2 CPU In summary we have two non overlapping pulse trains which represent the 01 and 02 clocks required by the 8080 CPU and the pulse widths of these two clocks vary with frequency as follows FREQUENCY 1 PULSE WIDTH 02 PULSE 24 0745 MHZ 140 nsec 280 nsec 8080A MHZ 70 nsec 210 nsec 80804 2 2 863 MHz 70 nsec 210 nsec 8080A 1 1 and 2 are applied to S 100 Bus pins 25 and 24 respectively through inverters 092 and bus drivers 077 They are also capaci tively coupled to pins 2 and 4 respectively of driver U104 the phase clock conditioner An additional clock called CLOCK is taken from pin 8 of gate 091 It occurs 70 nsec after 02 It is used on the Sol PC and is also made available on S 100 Bus pin 49 as a general 2 04 290 S ronal Ihree J
96. 0 voltage reduction at the primary of Sol T2 If the typical line voltage is over 112 v a c insert the same crimp pin into position 4 on the new commoning block for a 20 voltage reduction Dress all leads and install the tywraps provided to the cabling within the power supply Push the fan closure plate back into position and secure with the three screws which were removed Plug the cable from the keyboard into J3 on the main circuit board J3 is to the right ofa similar jack Place the keyboard back into position and secure with its four Screws and lockwashers Apply power and measure the unregulated supply using the procedure described above to confirm a 10 or 20 reduction Keep the pages of this notice in the Updates section of the Sol Systems Manual Detach the schematic from page 4 and tape it into the blank area on drawing X 14 9 page 3 7 77 9 page 4 NEW TRANSFORMER F 57 NEW COMMONING BLOCK NEW CONNECTION EXISTING Sol T2 EXISTING COMMONING BLOCKS Sol MANUAL CHANGE NOTICE DW technology CHANGE NOTICE 10 Refer to Section X Drawing X 17 Serial Data Interface U A R T block The section of U38 which has its input connected to pin 3 of Jl Serial Loop Current Source may not have enough drive at its input under worst case conditions with the present values of R29 the input pull up resistor and R21 the resi
97. 00 on the Bidirectional Data Bus The CPU can conse quently test the timer status by looking for a high on DIOO This timing allows a 250 msec scroll rate without the need for complex timing routines in the CPU 02 R102 and C37 serve to speed up timer reset Sects Audio Tape I O Refer to Audio Tape I O Schematic in Section X Page X 19 Timing for the Audio Tape I O is derived from the 1200 2400 4800 19 200 and 38 400 Hz signals received from the Baud Rate Gener ator in the Input Output section of Sol The first two are used by the write data synchronizer U100 and the digital to audio converter CULO The remaining three signals are fed to two sections of 0111 a quad multiplexer or select gate All four sections of 0111 are used to select clocks for low speed or high speed operation according to the select inputs pins 9 A and 14 B The states of these two select inputs must be complementary to each other in order to select PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION VELI the high or low speed clocks Specifically must be high and low to select high speed clocks the converse condition selects low speed clocks The select inputs are supplied by SPEED and HI CSOPEBD Ihe output of the second section on pin 11 of 0111 is BYTE WRITE CLOCK 4800 Hz on low speed and 19 2 KHz on high speed The third section outputs a 19 2 KHz high speed or 38 4 KHz low spe
98. 09 5 Tantalum Dipped with Personality program 1 2 24 DIP Socket 1 741508 1 14 pin DIP Socket id ies 1 523 Zener Diode 1 Handle Bracket 501 1045 Or ohm watt 5 Res 2 2 56X1 8 Binder Head 100 ohm watt 5 Res Screw 1 047 ufd Disc Ceramic 3 These are the quantities of parts used in the 2708 1 version 4 2 ASSEMBLY LIPS For the most part the assembly tips given in Paragraph 3 2 of Section III Page III 1 apply to assembling the personality module 4 3 ASSEMBLY PRECAUTIONS For the most part the assembly precautions given in Paragraph 245 Li ectron III Page III 6 apply 4 4 REQUIRED TOOLS EQUIPMENT AND MATERIALS Ihe following tools equipment and materials are recommended for assembling the personality module 14 Needle nose pliers ow 60 40 rosin core solder As Diagonal cutters supplied cr Screwdriver 6 Small amount of 24 4 Soldering 29 watt solid wire 4 5 ORIENTATION Capacitor location C2 will be located in the upper left hand corner of the board when the edge connector 15 positioned at the C PROCESSOR TECHNOLOGY CORPORATION Sol PERSONALITY MODULE SECTION IV left end of the board In this position the component front side of the board is facing up Subsequent position references related to the personality module circuit board assume this orientation A 42 26 ASSEMBLY TEST Circ
99. 129 Sol MANUAL CHANGE NOTICE Processor Bi Technology CHANGE NOTICE 9 Refer to the Sol Systems Manual Section X drawing X 14 The main power transformer Sol T2 supplies power for the 8 V dc unregulated supply which is used by S100 cards plugged into the backplane Distributed regulators on each S100 card reduce this voltage to 5 volts regulated Some Sol T2 transformers supplied with the Sol 20 kits were designed for brown out con ditions even though the A C power line voltage should drop below normal tolerances these transformers can maintain the unregulated supply so that the 5 volt regulators do not drop out of regulation Unfortunately these transformers can pro vide over 11 volts at a normal line voltage of 120 volts If the unregulated supply is lightly loaded by boards in the back plane and the boards in the backplane place heavy demands on their 5 volt regulators the result can be excessive dissipation in the regulators activating their normal thermal shut down circuitry The power supply circuit can be modified with the addition of a bucking transformer which reduces the effective primary voltage at Sol T2 by 10 or 20 thus reducing the un regulated supply by 16 or 20 to eliminate the problem This modification is recommended for all Sols which have the brown out transformers if they are used at a line voltage of 110 120 A schematic of the new circuit is shown below The transformers
100. 1581523 252282928233 Soa LO 5 s gt 1 i j 29 it 1313595 V Frgure 5 10 CPU Functional Test No 2 display 6575 character generator U25 6574 displays 9 09090 etc Bracket Sol 1040 ape gt lt Card Guide SAE1250F 4 40 x Screw Pt Sol P CB M Y lt Lockwasher Hex Nut Figure 3 11 Personality module bracket guide installation Viewed from right ena Of Solder Side Top Edge Board PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTERTM OEC T LON I Hev A Step 46 Attach plastic card guide 250 to each of the brackets installed in Step 45 See Figure 3 11 Insert posts on guides into bracket holes and push in until they snap into place Step 47 Install the following IC s in the indicated loca tions Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board che 1 pin 1 ot each IC NOs TYPE 91LO2APC ZIOZhLPC U4 O9O1LO2APC PANOZ LL pos Ugs 2102L1PC C U6 91LO2APC AOZ Li C6 y 91LO2APC 21 211 Uga 91L02APC INO VAP Ce US 91LO2APC
101. 19 OD6 Output Data bit 6 7 ID6 Input Data bit 6120 OD5 Output Data bit 5 8 ID5 Input Data bit 5 21 OD4 Output Data bit 4 9 104 Input Data bit 4 22 OD3 Output Data bit 3 10 ID3 Input Data bit 3 23 OD2 Output Data bit 2 11 102 Input Data bit 2124 Output Data bit 1 12 101 Input Data bit 1125 ODO Output Data bit 0 13 IDO Input Data bit 0 Pinouts Serial Data Interface SDI used on Processor Tech Sol System Female connector DB25S Jl pin Signal Signal Jl pin Signal Signal name mnemonic name mnemonic 1 CG Chassis Ground 8 CD Carrier Detect 2 TD Transmit Data 11 Current Loop Output 3 RD Receive Data 12 LRI Loop Receiver l 4 RTS Request To Send 13 LR2 Loop Receiver 2 5 CTS Clear To Send 20 DTR Data Terminal Ready 6 DSR Data Set Ready 23 LCS Loop Current Source 7 SG Signal Ground Note l Many pins not specified here are used in EIA RS 232C specification USE THEM WITH CAUTION Note 2 Terminals output on pins 2 4 amp 20 and input on pins 3 5 amp 6 for EIA type hookups Modems and computer mainframes output on pins 3 5 amp 6 and input on pins 2 4 amp 20 Note 3 Current loop hookups are the same for terminals modems mainframes REV A AVII 1 J3 Keyboard Connector between U64 and U65 Sol PC Rev 2 E 10 18 76 pin no Signal name pin no Signal name 1 ground I ground 2 T5v 12 5 3 Kbd Data Ready 13 Restart 4 Break 14 Local 5 Kbd Data 0 15 KBd Data 4 6 Kbd Data 1 16 KBd Data 5
102. 1s always an LDA to the Enter here to obtain Status character from the input pseudo port specified in the register tain the character with the flags set to indicate whether a character is present or NOEs On return register will con SUBROUTINES system Entry Points There are actually only two system entry points within the SOLOS jump table Entry at these points does not require that any register be initialized The first at either label START or INIT is used to perform a complete power on system reset As a part of the system reset the system RAM area data used by SOLOS will be cleared The only reason for entering via START or INIT is that the power on circuitry requires a one byte Instructronm Bo allow various Circu he Orther use of the byte labeled START is to determine if a user program is being executed under SOLOS or is CUTER controlled When under SOLOS this byte will be zero When under CUTER this byte will be non zero The other system entry point RETRN is used to return to SOLOS command mode This entry point does not perform a system Cx SOLOS Input Entry Points SINP entry point address COIF This entry point will set register A to the current system input pseudo port The current system input pseudo port is changed by the SET I command After setting register A this command proceeds by executing an AINP See below AINP
103. 2 None None 22 None None l 9A None None 9A None None 9A None None HOME CURSOR None None SE None None SE None None CLEAR None None None None None None Vertical line between characters indicates dual character key Character generated is displayable and transmittable Return is defined in and Line feed an 727212 code 15 generated or no symbol is displayed vu Lly eee Space Bar Pressing the Space Bar ASCII space code 20 Te de Except for the division symbol key Arithmetic Pad Keys applicable character into the Sol forward slash 7 charac The arithmetic pad is useful for entering large amounts of Fach key in the pad duplicates its corresponding addition key in the pressing one of the pad keys does the same thing as pressing its corresponding key in the numerical data numeric Period decimal point dash minus plus asterisk multiplication and forward slash division typewriter group of keys That is group ter None on page VII 24 shifted or unshifted generates the and moves the cursor one space to the right these keys enter Cie The division symbol key enters a SHIFT does not affect these keys means no type writer PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES SECTION VII 7 7 4 ESCAPE Key Pressing ESCAPE shifted or unshifte
104. 2 low 4 PUS Parallel Unit Select O pin 14 J2 low 5 TBR Tape Baud Rate 300 1200 O 1200 Baud 6 TT2 Tape Transport 2 O run tape 7 TPL Tape Transport 1 O run tape PORT FE SCROLL CONTROL DISPLAY SECTION BIT SIGNAL NAME FUNCTION ACTIVE DIRECTION 3 BDLA Beginning Display Line Absolute 4 bit data nybble address 4 7 FDSP First Displayed Line Screen 4 bit data nybble Position CONNECTOR DESIGNATION Ji Serial data 76 Cassette Tape Audio Out J2 Parallel Data J7 Cassette Tape Audio In J 3 Keyboard J8 Tape Motor 1 J4 Display Expansion J9 Tape Motor 2 J5 ROM Personality Module J1O PC Power Jll S 100 Bus Expansion AVII 8 B C Sol SYSTEM OVERVIEW AND GENERAL THEORY CPU and support circuitry 1 2 3 4 5 6 1 2 3 4 5 Clock generation Status generation Control signal encoding and buffering Data multiplexing and multiplex selection Data buffers Phantom generation and I O decoders Address decoding using the Phantom line Memory decoding page selection I O port decoding and selection Wait state generation System RAM ROM addressing selection Video display 1 2 3 4 5 Clock timing Sync generation Character generation Memory addressing Column and row address generation Audio cassette interface AGC and comparator network Data and transition detection UART Phase Lock Loop circuitry Clock multiplexing Write data logic Input Output c
105. 2 now connects to pin 4 ground instead Or Plin 6 as shown 0 MODULE ESQ Eakins 4 2 Assembly Tips 4 3 Assembly Precautions 4 4 Required Tools Equipment and Materials Zo emt sts 4 6 Assembly Test BOTO Sede 4 6 2 Assembly Test Procedure NC BN BN B NI DNE 2 PROCESSOR TECHNOLOGY CORPORATION Sol PERSONALITY MODULE SECTION IV 4 1 PARTS AND COMPONENTS When ordering your Sol you selected one of two types of Per sonality Modules CONSOL SOLOS The Outer Carton your stamped with the Personality Module type Both use the same PC board marked 2708 assembly 107000 and differ only in the type of ROM s and their programming An alternative PC board marked 5204 and de signed for type 5204 EPROM s is also available but not supplied with this kit Schematic diagram 4 and assembly drawing X20 refer to this alternative board Check all parts against Table 4 1 below If you have difficulty identifying any parts refer to Figure 3 1 on page 111 95 One of two kits using the same PC board 2708 0 or 2708 1 may be sup plied The 2708 0 version uses one 9216 masked ROM which has no window on top of the IC package The 2708 1 version uses two 2708 EPROM s which have windows Table 4 1 PM2708 Personality Module Parts List PM2708 PC Board i Or slaw Capacitor LOr A 9216 ROM or 27
106. 24 x 3 8 is driven through the ex pansion chassis and the two lower rear screws 10 24 x 1 are driven through both the expansion chassis and main chassis Step 3l Install left and right backplane right angle brackets light gauge brackets on expansion chassis side walls Refer to Figure 6 6 on Page VI 15 These two brackets are in stalled just to the front of the card guides and should be positioned as shown in Figure 6 6 Attach each bracket to the chassis with three 6 x 1 4 sheet metal screws USE THE SCREWS YOU USED IN STEP 19 TO PRETHREAD THE HOLES Step 32 See Detail B on Drawing X 8 Install backplane cir cuit board Sol BPB The photograph in Figure 6 7 on Page VI 16 shows the backplane board installed Position Sol BPB with 100 pin male edge connector down and the five female edge connectors facing the card guides The board should rest against the front face of the right angle brackets as shown in Figure 6 6 Adjust position of Sol PC as needed so that you can plug the Sol BPB edge connector into 911 on the Sol PC Align holes on left and right ends of Sol BPB with those in right angle brackets Step 32 continued on Page VI 16 VI 14 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI SOl BPB Right Right Angle Bracket Left Gusset Bracket ue E Expansion Chassis 7 N Front Right Gusset Bracket 6 x sheet metal screw 4 40 x 5 8 b
107. 30 2 1008 dS DANS C 402 72 0105 EOS 4049 Ul1l0O 4046 0111 92 Zo Co MOS device Refer to CAUTION on Page III 8 Step 69 Install Augat pins mountang holes H located to left of C70 Refer to Installing Augat Pins in Appendix IV Using 24 bare wire install a jumper be tween pins I and J I and J Step 70a AGIUSE Using a cable with a male phono jack both ends nect audio output 26 ACI audio input dils App hy Set VR3 fully clockwise CW Measure the DC voltage at pin 13 of U110 and write the measured voltage down Call this Voltage A Set VR3 fully counterclockwise CCW step 70 continued Page 111 39 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER LET Rev Measure the DC voltage at 13 of 110 and write the measured voltage down Call this Voltage B Add Voltages A and B and divide the sum by 2 Call the result Voltage C An example follows Voltage A VR3 full CW 3 45 V dc Voltage B VR3 full CCW A BS 5 25 Voltage 5 25 V de 2 24693 V de Adjust so that the voltage at pin 13 of 0110 equals Voltage C In the preceding example this would be 2 65 95 a otep 71 If your
108. 7 77 11 12 13 14 15 16 17 18 19 20 21 22 23 This lead is from the Sol T2 transformer Separate this lead from the twisted pair back to its origin at the transformer Note that each of the leads to the new transformer has a different color white red black and yellow red Twist together the red and white wires into a twisted pair and route the pair beside Sol T2 through the existing power supply cabling to the two existing commoning blocks Insert the molex crimp pin from the red lead into position 2 of the commoning block nearest the fan from which the other transformer lead was just disconnected Push the crimp pin firmly into place until it clicks Try to pull it out gently to confirm that it is properly seated Insert the crimp pin from the white lead into the position 2 of the commoning block farthest from the fan Insert the crimp pin of the black lead of the new transformer into position 5 of the new commoning block near the bridge rectifier Insert the crimp pin of the red yellow lead of the new trans former into position 1 of the new commoning block Determine the line voltage at which the Sol will typically Operate by a measurement Or averaged series of measurements using an A C voltmeter If the typical line voltage is under 112 v a c insert the crimp pin of the black lead of Sol T2 which was previously detached into position 2 of the new commoning block for a 1
109. 7 Kbd Data 2 17 KBD Data 6 8 Kbd Data 3 18 KBD Data 7 9 5 19 T5v 10 ground 20 ground J4 Display Expansion Connector between U28 29 in no Signal name in no Signal name T ground iT ground 2 12 3 Char addr 4 13 Dot Clock 14 318MHz 4 Character clock 14 Composite sync out 5 Char addr 15 TTL Serial Data Out 6 Char addr l 16 Composite blanking out 7 Char addr 2 17 Sean advance out 8 Char addr 3 18 Char addr 5 9 N C 19 N C 1 0 ground 20 ground J5 Personality Module Edge Connector in no Signal name pin no Signal name B15 Ground B14 5VDC 5VDC B13 Addr 9 T Addr 0 A I Addr 8 2 5 Addr 4 T Addr 7 Addr 3 B10 INT Bus 0 10 2 9 INT Bus 1 A9 R Addr 1 B8 INT Bus 2 AB Addr 5 7 R INT Bus 3 6 B6 INT 4 A6 C4 B5 INT Bus 5 AS c9 B4 Program 0 n P INT Bus 6 B3 Program 1 I INT Bus 7 B2 Program 2 i N 12VDC B1 1 Program 3 Al 12VDC 5 76 Audio Out forCUTS Cassette Interface Mini phone jack at rear panel J7 Audio In forCUTS Cassette Interface Mini phone jack at rear panel J8 Tape Motor Control 1 See output port FA bit 7 Sub mini jack at rear panel J9 Tape Motor Control 2 See output port FA bit 6 Sub mini jack at rear panel Rev A AVII 2 J10 DC Power Connector Sol PC Ground M 5VDC 2 12 VDC Md 12 VDC 12 VDC 5 VDC Ground S 100 Bus Definitio
110. 78 page lof 1 Ref ECN 410231 Processor Technology Processor Technology 7100 Johnson Industrial Drive 415 829 2600 Corporation Pleasanton CA 94566 Cable Address PROCTEC 501 MANUAL CHANGE NOTICE 16 SUBJECT Vectored Interrupt Capability for Sol The Sol Computer and other S100 modules built by Processor Technology do not require use of the vectored interrupt capability which the 8080A microprocessor used in the Sol provides The Sol provides how ever means for implementing vectored interrupt when the interrupt Signal is made available by a circuit board inserted in the 5100 bus on S100 bus pin 96 SINTA If a circuit board in the backplane gener ates interrupts two jumpers shown below should be added to Sol P C to enable the SINTA signal to reach the memory decoder circuit These jumpers may be added after completing the assembly of Sol P C or even after the Sol is completely assembled and tested The jumpers should be made from 24 solid insulated wire not provided The electrical effects of these jumpers may be seen on Drawing X 16 These jumpers may be left in place even if no S100 board generates interrupts 5100 bus pin 96 may float with no interference Step l Strip 1 of insulation from one end of each of two eight inch lengths of wire and insert into pads AC and AB near 058 from the component side of the board Solder and check for solder bridges Step 2 Dress the wires as shown in the drawin
111. 8 Install the following capacitors in the indicated locations Take care to observe the proper value and type for each installation Bend leads outward on solder back side of board solder and trim Refer to NOTE in Step 2 CAUTION REFER TO FOOTNOTE END THIS BEPORE INSTALLING C31 LOCATION VALUE 100 rd Aluminum Electrolytic d urd Disc C34 680 pfd Cisse or Disg yd ura Mylar SOUL Su C36 e urd DISC urd SUID 93 vO Td My iar T pular C54 Urad Desc 528 DOT SEO 238 al ufd DISC rnsbtell ul Wrta 4 lead at Ehe Pop 19 02 2829007 2 3460 its Lloostron below and to the right of 088 The emitter lead closest to tab 1S oriented toward the left of the board and the base 15 oriented toward the bottom Push straight down on transistor until it 1s stopped by the leads Solder and trim Step 20 Install diodes D9 and 010 1N4148 1N914 in their locations below 088 Position 09 with its dark band cathode to the left and 1 with its band to the right Step 21 Install coaxial cable composite video output See Figure 3 4 for details on how to prepare cable Strip away about of the outer insulation to expose shield Unbraid shield gather and twist into a single lead Then strip away the inner conductor insulation leaving abou
112. 9 d3 8927 Unit Separator Vertical Tab Map 0 PROCESSOR TECHNOLOGY CORPORATION SOL OPERATING PROCEDURES DEG LON VLI 7 7 10 LOCAL Key Indicator The LOCAL key internally connects the SDI output to the SDI input and disables serial transmission No character is displayed Pressing LOCAL Shifted or unsbrfuted to turn the indicator on sets Sol for local operation Keyboard entries are not transmitted but they are looped back to the SDI input for display That is Sol 15 not line Pressing LOCAL to turn the light off ends local operation This corresponds to the local line operation of a TTY 7 7 11 RETURN Key Pressing RETURN shifted or unshifted generates the ASCII carriage return character 0D which is not displayed and moves the cursor to the start of the line on which it resided prior to RETURN being depressed This is the same action as a TTY carriage return RETURN also erases all data in the line to the right of the cursor 27 12 LINE FREED Key Pressing LINE FEED shifted or unshifted generates the ASCII line feed character 0A which is not displayed and moves the cursor vertically downward one line This is the same action as a TTY line feed Line feed action does not erase any data in the line to the right of the Cursor 7 7 13 LOAD Key The LOAD key character is displayed but the key is non functional with CONSOL and SOLOS The code generated by this key 15 8C and
113. AOW AOW AOW AOW AOW AOW AOW AOW AOW AOW AOW gs 20 22 vg Wg 38 o g v 35 IDY dS W dS 919 45 3 H H Ayquenb 8 oj yey uoisseJdxe 6 10 AOW AOW AOW AOW AOW AOIN AOW AOW AOW AOW AOW AOW OWO HNI XOQ avd IS HOQ VIS 1 VINO JAW jr Ov gr VP 6t gv LV 9 Sv LP BE 3e Qt 8t 66 86 9E ve ct LE Qc Hc 62 8c IAW HNI XNI IX 1 avd We LAW HOO XNI XViS IX 1 Oud HoQ ava O 1H IAW XVLS IX Le 9c Sc ve cc Lic 02 3 e ai Vi 61 41 91 tL 2 01 30 30 10 20 vO 60 80 40 90 SQ 50 50 LO 00 PROCESSOR TECHNOLOGY CORPORATION TM Sol TERMINAL COMPUTER APPENDIX III STANDARD COLOR CODE FOR RESISTORS AND CAPACITORS SIGNIFICANT FIGURE DECIMAL MULTIPLIER COLOR Black 1 Brown 1 10 100 Red 2 100 200 Orange 3 1 000 300 Yellow 4 10 000 400
114. BE DAMAGED BY STATIC ELECTRICITY DISCHARGE HANDLE THESE 4075 50 THAT NO DISCHARGE FLOWS THROUGH THE 216 AVOID UNNECESSARY HANDLING AND WEAR COTTON RATHER THAN OYNTHETIC CLOTHING WHEN YOU DO HANDLE MOS ps STATIC CHARGE PROBLEMS ARE MUCH WORSE IN LOW HUMIDITY CONDITIONS Sedo cl Circuit Board Check Visually check Sol PCB board for solder bridges shorts between traces broken traces and similar defects Check board to insure that the 5 volt bus 3412 volt bus and 12 volt bus are not shorted to each other or to ground Using an ohmmeter on OHMS X or OHMS X _ 10K scale make the following measurements refer to Sol PC Assembly Drawing 3 to volt Bus Test Measure between positive and neg ative mounting pads for C58 There should be no continuity Meter reads close to infinity ohms 12 volt Bus Test Measure between positive and neg ative mounting pads Tor 059 There should be no CONTINUITY l2 volt Bus Test Measure between positive and neg ative mounting pads for C60 There should be no 5 5I127 312 Volt Bus Test Measure between positive mounting pads for C58 and C59 between positive pad for C58 and negative pad for C60 and between posi tive for C59 and negative pad for C60 You should measure no continuity in any of these measurements If visual inspection reveals any defects or you measure continuity in any of the preceding tests
115. Because the VDM is much more powerful than a standard hardcopy device the built in VDM driver supports many expanded functions The following characters when sent to the VDM driver output pseudo port 0 cause special functions to be performed Hox Pune p 01 Control A SOH Move cursor left wrap mode one position AVL Clear screen position cursor at home 0D Conte CR Clear remainder of line then move cursor to beginning of same line Controls DG Move cursor right wrap mode one position Lr Qontrol w AETB Move cursor up wrap mode one line SUB Move cursor down wrap mode one line The escape key hex code 1B is also a special character to the VDM driver It initiates what is known an escape sequence The escape character is always followed by one or two hexa decimal values bytes which indicate what expanded function is to be performed The following lists the escape sequences and corresponding results Where a third byte must follow the escape this will be represented by 4 indicating that this third byte actually contains a value being passed to the VDM driver Escape sequence 1B 01 Place the cursor onto position tH of the current display line 44 is in the range 00 3F 1B 02 Place the cursor onto line number of the dis play screen is in the range 00 OF with the topmost line being li
116. Connect white wire of C8 cable to negative terminal of C8 and green wire to positive terminal of 202 This cable was soldered to the Sol REG when you assem bled 16 Remove terminal screws place 10 lockwasher on each screw place cable lugs on screws and drive screws tightly into appropriate terminals Step 39 Mount C9 in its mounting ring with its terminal slightly toward C8 and tighten clamping screw See Figure 2 5 otep 40 Prepare R13 39 ohm 2 watt for installation on C9 Solder a 10 lug to each lead of R13 Bend leads of R13 to fit the terminals of C9 RI3 should fit on C9 as shown in Figure 2 94 step 41 Connect Sol 20 DC power cable 5 wire and R13 to 22 Route cable between C8 transformer Remove terminal screws from C9 Place lockwasher terminal screw blue lead of Sol 20 DC cable and one R13 lead on one terminal screw and drive it into the positive terminal 422 Attach lockwasher white cable lead and other R13 lead to negative terminal on C9 in the same manner Tighten Doth capacitor terminals LONCI CAUTION LOOSE CONNECTIONS ON C9 CAN LEAD TO ARC ING AND SUBSEQUENT POWER SUPPLY DAMAGE Step 42 Connect blue pigtail of 1 20 DC cable to positive terminal of FWB3 This pigtail has a spade lug at its free end and is connected to the lug you just attached to the positive terminal oF Connect white pigtail of 501 20 DC cable to negative terminal of FWB3
117. Department and they will be given thorough consideration The three ring binder you are holding is an easel binder The cover 15 hinged from side to side well as down the bind ing so that it may form its own easel stand To use this feature lay the manual open on a table Bend the full width of the manual along the creased hinge until a resistance to further bending is felt Then set the manual up on the table with the bottom of the pages down against the table and the top inclining away from you Tt is supported from falling by the portion of the binder you have bent back In this position your hands are free for building making measurements or troubleshooting The first part of this manual you should read is at the very end the Updates section Integrate this information into your manual before you begin CONTENTS OUTILNE Detailed contents precede each section IV WEE NEJE TEE TX INTRODUCTION and GENERAL INFORMATION oo eU E SM PII Suo pus EMBL anaa bati PERDONA ETEY MObULE AS KEYBOARD ASSEMBEY and TESI CA Bg gt o CO nA LY OPERATING PROCEDURES Clee DE VITRO TY SOFTWARE DRAWINGS APPENDICES gt PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER EIGURE S 6 4 o 9 21 OB Je LIST OF ILLUSTRATIONS TITLE sol 20 fan closure pla
118. EDURES 501 REAR PANEL Left ON OFF SWITCH 2 FUSE AC RECEPTACLE VIDEO Cassette Interface OUTPUT mi Motor Motor Audio Audio 2 COUT 2 1 IC LX C PL259 CONNECTOR RG59 U Cable A Subminiature Phone Plug B Miniature Phone Plug C Monitor compatible Connector Require Seperate Power Source iss Monitor Video Input Video Monitor Cassette Recorder Figure 7 1 Connecting the basic Sol system Aber PROCESSOR TECHNOLOGY CORPORATION 501 OPERATING PROCEDURES VLI 2 apie 5 Lh ie wb ou 3 0 9 LA 222216 97220 REAR OF SOLID BLINK FESTART WHT CHAR CTRL CHAR al Coma A ex FRONT ORE 501 Figure 7 2 Sol control switch settings for terminal mode Step 7 continued OON Switches 62 1 82 OFF BAUD RATE Switches 53 1 8 Lb otbers ORE 300 Baud SDI Switches S4 1 6 OFF selects full duplex operation Sete 2 SCOP buts and mo parity M PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES LT Turn Sol and monitor ons J Step 9 the monitor display raster out of syne black horizontal bar moves slowly down screen numerous black lines cut across raster or both adjust monitor vertical and horizontal hold control
119. ENTR command and returned to command mode addrl addr2 This command displays sequential memory data on the screen starting at location addrl and ending with addr2 Example Result DUMP CO2E C037 COZ EL DB FA EO OL IDB EC CI Dumped the SOLOS keyboard input routine See listing Starting at memory location 2 and ending at memory location C037 II CONSOLE COMMANDS cont Terminal Command TERM oert 0 Avail under only This command causes the Sol system to become a video terminal for connection to an external computer or modem This command begins by automatically setting the 170 pseudo ports to the specitied values An omitted port parameter will be set to 1 Execution then proceeds by sending all Sol keyboard entries except cursor control to the specified Output pseudo port Any input available from the Input pseudo port will be processed by the SOLOS display driver Examples TERM Result Keyboard data will be sent to the serial port and all data from the serial port will appear on the display screen Custom Command CUST name tadar definition removal When a non SOLOS command is entered a separate table of custom commands in RAM will be searched The CUST command is used to enter and remove up to six custom command names from the custom command table Only the first two letters of the name are signi ficant When the name 2 to 5 letters specified by the CU
120. ER SUPPLY SECTION II Table 2 1 Sol Regulator Parts List Continued MISCELLANEOUS Sol REG Circuit Board 1 1 1 1 1 2 1 1 1 1 1 1 2 1 4 3 1 1 2 1 2 3 5 1 Heat Sink 690 220 Heat Sink 203 AP Heat Sink aluminum Package Heat Sink Compound Coax Connector female Video Output Coax Coax Connector Adapter Sleeve Video Output Cable Connector male Video Output Cable AC Receptacle female Fuse Holder SPST Power Switch pushbutton 55 AC Power Cord Commoning Blocks Clamp for C8 Tie Wraps Mica 4 40 4 40 4 40 6 32 6 32 6 32 Insulators x 7 16 screw x 5 8 screw Hex Nut x 1 screw metal x screw Nylon Hex Nut Lockwasher internal tooth Length Solder Chassis mounted component II 3 PROCESSOR TECHNOLOGY CORPORATION Sol POWER SUPPLY SECTION II Table 2 2 Sol 10 Power Supply Parts List The Sol 10 Power Supply Kit includes all Sol REG parts listed in Table 2 1 plus the following components 1 Power Transformer 1 1 Fuse 3 amp Slo Blo F1 Chassis mounted component Table 2 3 Sol 20 Power Supply Parts List The Sol 20 Power Supply Kit includes all Sol REG parts listed in Table 2 1 plus the following components RESISTORS CAPACITORS 1 39 ohm 2 watt 5 1 54 000 ufd electrolytic RECTIFIERS TRANSFORMERS 1 MDA980 1 FWB3 1 Power Transformer T2 MISCELLANEOUS 1 Fan 1 5 wire Cable Assembly 1 Fan
121. ERSONALITY MODULE SECTION LV DAMAGED BY SIATIC EBECITRICITY DISCHARGE HANDLE THESE IC s SO THAT NO DISCHARGE FLOWS THROUGH THE IC AVOID UNNECESSARY HANDEING AND WEAK COTTON RATHER THAN CLOTHING WHEN HANDLING MOS IC s STATIC DISCHARGE PROBLEMS ARE MUCH WORSE IN LOW HUMIDITY CONDITIONS Step 1 Install DIP sockets Install each socket in the indicated location with its end notch oriented as shown on the circuit board and assembly drawing Take care not to create solder bridges between the pins and or traces INSTALLATION TIP Insert Socket pins into Mounting pads ot appropriate Location On back solder side of hoard bend pins at opposite cor ners of socket e g pins 1 and 9 16 socket outward until they are at a 45 angle to the board surface This secures the socket until it is soldered Repeat this procedure with each socket until all are secured to the board Then solder the pins on all sockets LOCATION SOCKET WL 24 pin C 24 pin U3 14 pin Used On 2700 1 vers Ion only Step 2 Install the following resistors in the indicated locations Instal I these resistors parallel with the board Bend leads by using needle nose pliers to grip the resistor lead right next to tlie resistor body and bend the portion of the lead on the other side of the pliers with your finger Ihe bend must he the right distance from the resistor body for the resister to Fi
122. ESSOR TECHNOLOGY CORPORATION Sol PERSONALITY MODULE SECTION IV Hev B If a blinking cursor is present the ENter and DUmp commands should operate as described in Section IX Of thas manual If the ENter and Dump commands do not operate cor bectly Locate Anad Correct the problem pros ceeding If the personality module is operating correctly turn monitor and power off disconnect power cable and video output cable and go on to 50 Section III The personality module can be left plugged in ys KEYBOARD BIMBI Y I RSS ME 9212 Om Seco op D 5 3 Assembly Precautions 5 4 Required Tools Equipment and Materials 265200 Or emt sts uA 5 6 Assembly Test BOTO Sede 5 6 2 Assembly Test Procedure PROCESSOR TECHNOLOGY CORPORATION ool KEYBOARD SECIION M 5 1 PARTS AND COMPONENTS Check all parts and components against the Parts List Table 5 1 If you have difficulty in identifying any parts by Sight refer to Figure 2 1 Page 111 5 in Section ILL of this manuals Fal ASSEMBLY LIPS For the most part the assembly tips given in Paragraph 3 2 of Section III Page III 1 apply to assembling the Sol keyboard In addition be sure your hands are clean before handling the circuit board especially the area containing the keyboard Switch pads 9a ASSEMBLY PREGAUITIONS For the most part the assembly precautions given in Para
123. FUNCTION 79 AO Address Line 0 LSB 80 Al Address Line 1 81 A2 Address Line 2 82 Address Line 6 83 7 Address Line 17 84 A8 Address Line 8 85 A13 Address Line 13 86 A14 Address Line 14 87 All Address Line 11 88 DIO2 Data In Out Line 2 same as pin 41 89 DIO3 Data In Out Line 3 same as pin 42 90 0107 Data In Out Line 7 same as pin 43 91 DIOA Data In Out Line same as pin 38 92 0105 Data In Out Line 5 Same as pin 39 93 0106 Data In Out Line 6 same as pin 40 94 DIOL Data In Out Line 1 same as pin 35 95 0100 Data In Out Line 0 Same as pin 36 96 SINTA INTERRUPT ACKNOWLEDGE Status output signal acknowledges signal for INTERRUPT request 27 SWO WRITE OUT Status output signal indicates that the operation in the current machine cycle will be a WRITE memory or output function 98 SSTACK STACK Status output signal indicates that the address bus holds the pushdown stack address from the Stack Pointer 99 POC POWER ON CLEAR 100 GND GROUND SWITCH FUNCTION DEFINITION Display Ctrl Schematic Drawing 4 Function Switch No Mnemonic ON OFF 61 1 RST Restart to Zero RUN Dwg S1 2 not used 51 3 BLANK Blank Ctrl Characters Display Ctrl Char 51 4 Polarity 51 5 BLINK Blinking cursor Solid or NO cursor S1 6 SOLID Solid cursor Blinking or NO cursor NO cursor if 51 5 and 51 6 are off at same time Both switches should not be on at the same time Drawing 3 Sense Switch Function Switch No
124. Green 5 100 000 500 Blue 6 1 000 000 600 Violet 7 10 000 000 700 Gray 8 100 000 000 800 White 9 1 000 000 000 900 Gold 5 1000 Silver 10 2000 No Color 20 500 Applies to capacitors only 1 TOLERANCE VOLTAGE RATING PROCESSOR TECHNOLOGY CORPORATION TM Sol TERMINAL COMPUTER APPENDIX IV LOADING DIP DUAL IN LINE PACKAGE DEVICES Most DIP devices have their leads spread so that they can not be dropped straight into the board They must be walked in using the following procedure 1 2 3 4 2 3 Orient the device properly Pin 1 is indicated by a small em bossed dot on the top surface of the device at one corner Pins are numbered counterclockwise from pin 1 Insert the pins on one side of the device into their holes on the printed circuit card Do not press the pins all the way in but stop when they are just starting to emerge from the opposite side of the card Exert a sideways pressure on the pins at the other side of the device by pressing against them where they are still wide below the bend Bring this row of pins into alighment with its holes in the printed circuit card and insert them an equal distance until they begin to emerge Press the device straight down until it seats on the points where the pins widen Turn the card over and select two pins at opposite corners of the device Using a fingernail or a pair of long nose pliers push these pins o
125. Guard 1 Clamp for C9 212 1 Fuse amp Slo Blo 2 solder lug internal tooth Chassis mounted component II 4 PROCESSOR TECHNOLOGY CORPORATION ool POWER SUPPLY SECTION II 4522 ASSEMBLY TIPS Electrical For the most part the assembly tips given in Paragraph 3 2 of Section III Page 111 1 apply to assembling the Sol regulator board and power supply In addltron Scan Section 11 completely before you stare to assemble the power supply 2137 Mechanical Ly If you do not have the proper screwdrivers see Para graph 2 5 we recommend that you buy them rather than using a knife point a blade screwdriver on a Phillips screw and other makeshift means Proper screwdrivers minimize the chances of stripping threads disfiguring screw heads and marring decorative surfaces assure correct fit tight assembly sure you use the screws specified in the instructions b Lockwashers are widely used in the power supply assembly so that screws will not loosen when subjected to stress or vibration When a lockwasher is specified do not omit it and make sure you Install wt coOPrectlv 4 Some instructions call for prethreading holes This is done to make assembly easier by giving you maximum working space for installing relatively Nard to drive sheet metal serews you by pass prethreading instructions you will only make subsequent cabinet chassis assembly more difficult To prethread a
126. If any voltages are incorrect locate and correct the cause before proceeding to Step 10 If the voltages are correct turn power off dis connect power cable unplug personality module and GO bo Step 104 Step 10 Install IC s in the sockets numbered Ul through U3 Make sure the dot or notch indicating pin 1 on the IC package is in the correct position as indicated on the PC board component legend and the assembly drawing X 6 Socket 02 is left empty on 2708 0 versions 9216 ROM with no window As shown in the table the 2708 EPROM s have paper labels with the designation shown while 9216 ROM s have the designation printed on the IC package itself IC LABEL EG NO TYPE CONSOL SOLOS U1 2708 54 2105 0 o s NUUS 2 HO Empty 59 version 15 Mie OL DES 9216 SOLOS 290 3 U2 Empty version Cas 0 OS MOS devices See CAUTION on pages IV 2 3 personality module InCo Jo and Con nect Sol PC video output cable to video monitor Refer to CAUTION Page 1117 2272 Section IL Set S1 switches follows 14 tNrough 4i OFF NOs 27 ON No 102 OFF TUL monitor om and apply power to Sol PC With both the CONSOL and SOLOS modules you should ule cursor preceded by a prompt Character tike pes B you AG 568 a Cursor Locate OOPrect the problem before proceeding LV 6 PROC
127. In half duplex operation data transmitted out the SDI 21 is looped back and received by the SDI for subsequent NODIS PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES display the monitor Use this type of operation when your Sol works with an external computer that does not echo data back to the Sol For full duplex operation in the terminal mode set 54 6 to OFF Only received data is displayed in full duplex operation Use full duplex when Sol s transmitted data need not be displayed Note that transmitted data from the Sol if echoed back is displayed as received data NOTE If Baud rate is selected data will not transmitted out of the SDI 7 5 12 Keyboard The keyboard 15 an output device that produces ASCII American Standard Code for Information Interchange encoded It 15 hardwired to an input port on the Sol and is used for data entry ASCII data is interpreted by the Sol as data and or commands as determined by the current system monitor program The monitor program may be in the personality module ALS 8 Sol RAM memory or some memory 0 THE KEYBOARD GENERAL DESCRIPTION The Sol Terminal Computer has ASCII 96 character keyboard Its key arrangment conforms with the QWERTY standard typewriter format As shown in the photo on page X 26 there are also 12 control keys including five basic cursor controls and seven special function keys A 15 key arithmetic pa
128. K 3 X 3 Sol PC Assembly Change VR3 value to LOOK 4 Change R154 value to 47K 5 III 3 Table 3 1 Change Qty 47K resistor to 2 6 Change Qty 50K pot to 2 7 Add 1 100K pot 8 Change Qty 100K resistor to 3 9 III 36 Step 60 Change R154 value to 47K yellow violet orange VR3 100K 10 III 38 Step 70 Add note See Change Notice 11 11 III 7 Section 3 4 Under item 11 Oscilloscope delete optional add with calibrated time base Make the following additional changes in the manual unrelated to the substitution of new values for VR3 and R154 11 III 24 Step 28 After sub step relating to Figure 3 8 add note Adjust and VR2 for centering of the display 12 In last sub step on this page change 049 to 059 CN 11 9 77 Ref No 10129 page l ProcessorTechnology Processor Technology 7100 Johnson Industrial Drive 415 829 2600 Corporation Pleasanton 94566 Cable Address PROCTEC Sol MANUAL CHANGE NOTICE 13 SUBJECT Side Panel Assemblies Superecedes Change Notice 12 The two wooden side panels of the Sol are now supplied as com pletely assembled and finished subassemblies consisting of the walnut and masonite side pieces the tinnerman plastic in serts and 5 8 wood screws presently listed in the Parts List Table 6 1 Section 6 6 2 contains the procedure which was used to assemble the panels The procedure may be useful if it becomes necessary to refinish the walnut piec
129. LI As can be seen Sol s internal memory consists of four con tiguous 1024 byte pages There are two pages CO and C4 hexadecimal or hex of ROM with Page at hex addresses C000 through C3FF and Page at hex addresses C400 through C7FF System RAM Page C8 is at hex addresses C800 through CBFF and Display RAM Page CC is at hex addresses 0 through Ihe six high order bits of the address are decoded in the Address Page and I O Port Decoder to supply the required four memory page selection signals The I O Port Decoder portion of this cir cuit decodes the eight high order address bits to provide outputs that control Data Input Multiplexer switching Data Bus Driver en ablement and I O port selection Ihe video display section consists of the Video Display Gen erator and Display RAM The RAM is a two port memory with the CPU having the higher priority Screen refresh circuitry in the Video Display Generator controls the second port to call up data as needed for conversion by a character generator ROM into video output signals Other circuitry generates horizontal and vertical sync and blanking signals as well as cursor and video polarity options A 1200 Hz signal extracted from dot clock by a divider in the Video Display Generator drives the Baud Rate Generator This generator supplies the receive and transmit clocks for the serial data interface SDI UART and provides ail frequencies required for Baud rates b
130. LOS Whenever a machine program 1s executed by SOLOS via the EXEC or XEQ command or via a custom command the stack pointer and HL registers are predefined by SOLOS gt The stack pointer is set such that the user may perform stacking operations which will use the SOLOS stack The SOLOS stack begins at the end of the SOLOS RAM area and works its way down from there Excessive use Or this stack destroy data Marmtaimed SOLOS wit han Xs RAM area The stack is also prepared so that the user may issue a standard 2xstructrion return control to SOLOS command mode processor The HL register pair 1S initialized to point to the very beginning of SOLOS 15 at this point that the SOLOS jump table begins The user program may then use the address presented in the HL register pair as the beginning of the jump table This address 15 provided for two reasons 1 CUTER may be located at any address in memory providing the means for programs to function with CUTER located at any address and 2 the first byte of the jump table for SOLOS is different from the first byte for CUTER providing an easy means of dis tinguishing between SOLOS and CUTER Third 1s the SOLOS jump table see next page All requests to SOLOS should be made based on this jump table and not to the actual routine addresses as scattered throughout SOLOS By using only this jump table the user can be assured of maintaining compatibility between
131. LOS then resets the buffer file for the next 256 bytes of data Ihe entry point for WRBYT is 010 On entry Register A contarnse Pile or 2 Register B contains the byte of data to be onto On exit Normal return Carry Flag cleared Error Garry Flag Set errors caused Dy 1 file NOT open or file previously used for reading SUBROUTINES Read Byte Routine ROBY The Read Byte routine reads a single byte of data froma buffer file SOLOS fills this buffer as needed per read request Each time SOLOS fills the file buffer reads a DLOGk the CRC character is checked ror data accuracy The entry point for RDBYT 18 2000 On entry Register contains file 1 or 2 On exit Normal return Register A contains data byte Carry and Minus Flags set mean end of file Error return Carry Flag seu Errors causea by 1 file NOT open 2 file previously used for writing 3 CRC character error 4 pressing MODE or Control 8 white actually reading from the tape Close File Routine FCLOS Ihe Close file routine closes the current file and resets the internal parameters for the next open operation It is very important to close the file after all data transfers are completed Failure to do so could result in lost data and prevent further open operations Ihe entry point for FCLOS is On entry contains Eile eb Of 2 Boe
132. M input addr Allows ignoring of tape CRC Read errors SET S 0 FF This command determines character display rate to the screen data 0 Fastest data FF Slowest Input Output Command Parameters The next two SET commands affect SOLOS input and output command parame Set Qut Command SET O port This command selects the output driver routine to which SOLOS routes data Under SOLOS Under CUTER In all cases current output pseudo port Sereen COMMAND mode text is always sent to the display ell output goes to Current pseudo the output from each command is sent to the V SET COMMANDS cont The Output Pseudo ports command parameter values are O Video Display i Qutipub POr 2 Parallel Output Port 3 User Defined by SET COUT command Example DET Q DUMP 0 2 Result Select serial output port Dump 0 2F would displayed but the data would go to the serial oet In Command Set DOSE This command selects the input driver routine to SOLOS 11 future input commands would come from the new selected input pseudo port the Input Pseudo port parameter values sare 0 Keyboard 1 Serial Input Port 2 Parallel Input Port 3 User defined by SET CIN command Example PET Tel Result SOLOS would expect the next command to come from the serial port input routine The Sol keyboard would have no affect except t
133. ND mode SOLOS will do a Carriage Return Line Feed CRLF followed by a prompt gt SOLOS then awaits the entry of a COMMAND A COMMAND is processed upon receipt of a Carriage Return CR Pressing the MODE or Control key while awaiting a COMMAND causes the current COMMAND input line to be ignored and return to COMMAND mode CUTER also resets the current I O pseudo port selections to the system default The MODE or Control key is also used to abort the execution of most commands This use of the MODE or Control key turns off both tape machines if on and returns to COMMAND mode II CONSOLE COMMANDS Console Commands in Brief SOLOS has five console commands They are Command Function EXEC addr Begin program execution at addr ENTR addr DUMP TERM CUST name addr Enter data into memory starting at addr Dump memory Gate addr2 Enter Terminal Mode available under SOLOS only Insert or remove a custom command Console Commands in Detail Execute Command EXEC addr This command begins program execution at memory location specified by addr Example Enter Command ENTR Example Result Dump Command DUMP EXEC 200 addr ENTR 500 Co 00 000 057 Beginning at memory location 500 the follow ing data was entered C3 00 01 The new memory location of 1000 was selected to enter the data 51 The slash terminated the
134. NE jack on recorder Step 3 Plug one end of Audio Out Cable into Audio OUT jack J6 on Sol rear panel and plug other end into AUXILIARY or MICROPHONE jack on recorder The AUXILIARY input is preferred and recommended over the MICROPHONE input NOTE If your recorder has only a microphone jack remove the I to J jumper installed Step 09 in Section III and install Jumper between I and H Step 4 Plug one end of Motor I Cable into Motor I jack J8 on Sol rear panel and plug other end into REMOTE jack on recorder step 5 Connect PL259 UHF connector on Video Cable to video output connector on Sol rear panel and connect other end to yide Monitor rznput connector Step 6 Make sure monitor recorder and Sol power switches are in their OFF position Then connect AC power cord to AC receptacle on Sol rear panel and connect Sol monitor and recorder to appropriate power source Terminal Mode Operation The following procedure assumes your Sol is equipped with a SOLOS personality module step 7 Set Sol control switches as follows see Figure 7 2 onc Page Werde Rol QUE 51 2 spare OFF BLANK Switch 51 3 OFF display control characters POLARITY Switch S1 4 OFF reverse video display OFE Solid curser SOLID Sl 6 ON solid cursor Step 7 continued on Page VII 7 PROCESSOR TECHNOLOGY CORPORATION 501 OPERATING PROC
135. ONNECTOR PINS SO MUCH THAT YOU WILL DAMAGE THE TRACES WHEN PLACING THE CONNECTOR OVER THE EDGE OF THE BOARD While holding the connector and board together place board solder side down on a book or other flat surface that is higher than your work surface so the connector extends fully over the edge That 1s the connector should not rest on the book Reposition connector if needed to align the pins and traces On the component front side of board solder a pair of traces On the component front side of board solder a pair of pins at each end of the connector to their respective traces on the board Then solder the remaining 46 pins on the component side to traces The connector must be perpendicular to the edge of the board If it is not bend the pins you just soldered to obtain the required alignment Then solder the other 50 pins to the traces Step 3 Install the other five 100 pin edge connectors Po Sition connector on front side of board the side without the green solder mask and insert pins solder back side of board the side with the green solder mask solder pins at opposite corners of the connector to hold it in place while making sure the entire connector is seated firmly Then solder the remaining 98 pins Step 4 First check that wire color code in Sol backplane cable assembly 3 5 wire cable conforms with that given be low and in Figure 2 7 Page 11 21 in Section II Then con nect cable to circu
136. PROCESSOR TECHNOLOGY CORPORATION SOl TERMINAL COMPUTERTM ILLUSTRATIONS TABLES FIGURE TITLE PAGE Connecting Sol to two cassette recorders 29 156 Connecting Sol SDI to current loop device such as TTY 7 7 Connecting Sol SDI to communications modem a a a VII 3l 1 8 Connecting Gol to parallel device sr kar s i VEA TABLE TITLE PAGE Zo Sold Parks ww deos ow A we ww Dp SUPPLY Parts EISE s e Ge Sox II 4 25 5020 PONI 2 ow We we e II 4 3 1 Peles Re dE DE 2 4 1 PM2708 Personality Module Parts List 5 1 Keyboard Parts LIS 22 de de 22 oes Cabiner Ciessis Peres DOSE acs 3 8 2 oci Capincet Chassis ox qe Sol Operating Controls end Thelr PUNCU ONS 22 9 MET Baud Rave de d X cx oe Word Length Selection with 54 2 amp 3 we se 59 ERES 7 4 Dol ASS IONES e o s Control Character Symbols Derinitiong al INTRODUCTION and GENERAL INFORMATION le 1 SOLE eC Descent pL ron Receiving Inspection Warrant ENC
137. Pie io 7 BOOMS MCNOS TON duae zoll 2 915927 on 111 8 Remove U42 and bend pin 6 out 450 to its normal position See Figure 3 6 socket Re install 042 with pin 6 out of the Bend desired pin Ont 430 220 vertical Figure 3964 Bending selected pins U42 59 75 U59 shown Remove 059 and bend pin 4 in same manner 042 install 059 with 4 Out the socket Step 28 continued on Page 111 24 111 239 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL coMPUTER OEC LON DII Remove U75 and bend pin 5 in same manner 042 WS with path rour Using 24 wire install the following TEMPORARY jumpers in the sockets for 014 through 021 Double check jumpers after installing for correctness Ti JUMPER U14 12 EO Pin L2 tO 1J16 Pin 22 EO AES Y Pit 12 CO U18 12 EGO U19 S0 U20 Pirim 32 EO U21 422 vec See Figure 3 7 p 1 Figure 3 7 014 through 021 socket jumpers Turn monitor and apply power to Sol PCc Momentarily ground Pin om 2 and puri cer 079 he display shown in Figure 3 8 should appear on the monitor screen If the display circuits do not pass this test determine and correct the cause before proceeding with assembly
138. R use acid core solder or externally applied fluxes REV C VIL PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS PART Circuit Board Cable Assembly Connector Connector Plug Sleeve Chassis Subchassis Bracket Bracket Bracket Bracket Bracket Card Guide Assembly Assembly Cover Cover Cover Label Label Label Label Foot Screw Screw Screw May be packaged under logo cover REV C VI 2 SECTION VI Table 6 1 501 20 Cabinet Chassis Parts List REFERENCE Drawing DESCRIPTION QUANTITY No Designator Sol Backplane l X 8 4 Sol Backplane 3 5 wire 1 X 10 1 PC 100 pin 1 X 8 5 PC 100 pin 5 X 8 6 Coax 75 ohm 1 219 ye Coax Adapter 1 19 9 9 1 X 8 11 Expansion 1 9 12 Connecting Power Supply Subchassis 1 X 9 13 Keyboard Support 2 X 9 14 Backplane Right Angle 2 8 16 Backplane Left Gusset 1 X 8 17 Backplane Right Gusset l 8 18 Plastic 4 10 X 8 34 Left Side Panel 1 X 9 5 Right Side Panel 1 9 6 Keyboard 1 X 10 10 Top 1 X 10 22 Logo Plexiglass l X 10 20 Sol Logo l X 10 21 Fingerwell Black 2 9 28 Connector Identification 1 8 29 Serial Number 1 8 26 Rubber Adhesive 4 cig 6 5 4 40 3 16 2 8 44 Machine 4 40 x 5 16 16 X 8 amp 9 39 Machine 4 40 x 5 8 6 8 38 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Table 6 1 501 20 Cabinet Chassis Parts List Continued REFERENCE Drawing PART DESCRIPTION
139. S CARDBOARD AGAINST SOLDER SIDE OF BACK PLANE BOARD DURING INSTALLATION TO PRE VENT SUCH INJURY See Detail E on Drawing X 8 Attach bracket to backplane board with three 4 40 x 5 8 binder or pan head screws 4 lockwashers and 4 40 hex nuts Insert screws from front Side of bracket through Sol BPB place lockwasher on each screw and secure each with nut Install wider gusset bracket on right side in the same manner as you did the left bracket THE PRECEDING WARN ING ALSO APPLIES TO INSTALLING THIS BRACKET Step 34 Connect Sol 20 DC power cable from power supply subchassis to the Sol BPB power cable you installed in Step 4 Step 35 Check that 501 is in optimum position and tighten the eight screws holding the Sol PC to the expansion main chassis assembly See Step 27 Step 36 Connect Sol PC power cable 4 wire to J10 on Sol PC CAUTION Make sure cable connector mates exactly with J10 Step 37 See Drawing X 10 Position keyboard Sok KBD near its mounting brackets and connect 20 conductor ribbon cable supplied with Sol keyboard between 21 on keyboard and J3 on Sol PC With the cable connected properly the cable will run away from the keys from 21 on the keyboard and towards the keys from J3 on Sol PC Step 38 See Drawing X 10 Attach keyboard to keyboard brackets with two 6 32 x 1 2 binder or pan head screws and 6 lockwashers on each side Place washer on each screw and drive screws loosely into t
140. S don 1493 14 5132 U7 TAGSLIS 1172 90347 9534 95h34 U12 5914 4422572 OF 929129 T9 DIODES ALIGHI gt MVS T LED Iy disc disc disce disc Grse Mylar tubular tantalum dipped PROCESSOR TECHNOLOGY CORPORATION Sol KEYBOARD Y Table 5 1 Sol Keyboard Parts List Continued MISCELLANEOUS L Printed Board DIP 5 14 DIP Socket lo pzn DIP SOCckeL 22 IP 20 pin Header 3 3492 2002 9 3 4 20 conductor Rainbow Cable Assembly 70 501 10 or 85 key 501 20 Keyboard Assembly Plastic Insert 501 10 for Key Pad Torx Screw Similar to 44 by 3 8 sheet metal screws Fiber Spacer Length Solder 5 6 AoORMBLhY TLIESGSIT comm Circuit Board Check Visually inspect circuit board for obvious flaws The design of the board includes numerous unconnected traces and traces that are shorted to each other Doard that the o Vole DUE XS not shorted to ground Using an ohmmeter measure be tween the GND and 5V pads located in the upper left corner of the board There should be no continuity If no visual inspection reveals any defect or you measure continuity between the GND and 5v pads return the board to Processor Technology for replacement If the board is not defective proceed to next paragraph Oe Assembly Test Procedure Refer to keybo
141. SB on S 100 Bus pin 22 is used to disable the address drivers when a DMA device or another CPU takes over the bus 5 1 volt zener diode 011 and a divider network composed of R130 131 and 132 derive 5 V dc from the 12 V dc supply for use by the CPU Diode D12 and the same divider supply 12 V dc to pin 3 of U104 the phase clock conditioner 25092 Memory Decoder Refer to the Memory and Decoder Schematic in Section X Page VIII 14 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON LII The System RAM consists of eight 1K by 1 bit static memory chips U3 through 010 and it is assigned addresses C800 CBFF hex When the CPU wants to write data into memory it addresses the System RAM on ADRO 15 ADRO 4 select the row inside the RAM chips ADR5 9 select the column and ADR10 15 select the page in this case Page C8 hex Page selection enables the eight RAM chips on pin 13 For a read operation MWRITE on S 100 Bus pin 68 is low and the re sulting high on pin 3 WE of the RAM chips keeps them in the read mode Thus data on the Bidirectional Data Bus is read into the PRAM S on their D1 pin 11 inputs MWRITE is high however during the time the CPU wants to write data into memory In this case pin 3 of the RAM s is low to enable them to accept data from the Bidirec tional Data Bus The ROM is also addressed on ADRO 15 as is the System RAM Since there can be two pages however two enable lines
142. ST command is not already in the custom command table a new custom command will be entered into the table having an execute address as specified When the addr is not specified the beginning address of SOLOS will be used When the name specified on the CUST command already exists in the custom command table this table entry will be replaced with an end of table indicator Therefore not only will the specified name be removed but any other custom command names following in the table will also be removed Example CUST BASIC 0 CUST 158 E0600 Result Two new custom commands are now known ALS at JocatIron E090 ana BASIC location 0 III TAPE COMMANDS Tape commands are used to control the tape cassette recorders In these commands unit selection is optional with a default select ing unit 1 When a unit is specified however it must be separated from the file identification name with a slash and without spaces in between e g TARGT 2 Tape Header At the start of each tape file is header information This informa tion includes the following data name name of file 5 ASCII characters less type number is specified by user at time file is created addr starting address of file size number of data bytes in file XEQ addr auto execute address word See Set Commands Section 2 2 Error Messages Cassette error messages are printed in this format ERROR name type addr size Reasons for
143. SUBROUTINES SOLOS provides entry points to Open Read Write and Close tape files Each of these routines requires that certain con ventions be followed to ensure accurate data transfers File Open Routine FOPEN The Open routine sets up certain internal parameters to keep track of data requests This operation should be called only once prior to the first access of the file The File Header information is the same format as in the Block Access mode and 15 used in both reading and writing of files If the Byte Accesses are of the Read type SOLOS will search the tape file until the correct file name is found as specified by the File Header information On the next Read access SOLOS will transfer the first data byte of the file If the Byte Accesses are of the Write type the File Header information will be transferred onto the file The entry point for 18 C007 On entry Register A contains File 1 or 2 same as tape unit L QE 2 Registers H amp L contain address of the File Header 30 exit Normal return All registers are altered and file 1s ready for accesses The Carry Flag 15 set Reason for error file already open Write Byte Routine WRBYT The Write Byte routine writes a single byte of data into a Du urrer files 50105 stores this data until contains 259 bytes It then writes this block onto the tape followed by a CRC character error checking character SO
144. TE HANDLE WITH CARE step 7 Install light emitting diodes LEDI 2 and 3 MV5752 in their respective locations in the lower left corner of the circuit board Insert leads through fiber Spacer position each diode with its cathode lead longer lead and or the lead next to flat edge of LED package at the bottom insert leads into mounting holes in circuit board pull down so that spacer and LED are snug to board solder and trim If fiber spacers are not supplied with your kit LEDs so they sare approximately 3716 above surface of circuit board otep 8 Install 20 pin header in location J1 upper left corner of board Position header so pin 1 is in the lower left corner An arrow on the header points to 1 solder Step 9 Using an ohmmeter measure between GND and 5V pads in upper Left corner of the board You Should measure some resistance Zero resistance indicates a short If qu ired find and correct the problem before proceeding to Step 10 Me PROCESSOR TECHNOLOGY CORPORAL LON 501 KEYBOARD SECTION M lt gt Step L0 Install the following IC s am the indicated Loca tions Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board indicate the location of pin I gue o IG INO Ul TAESLIS U2 JS U3 909 U4 741500 U gt 1493 Cw X Jod U7 Tabor U8 1415174 t Je TALOSTA 010 741500
145. TIONS CABLING CONNECTIONS 76 AUXILIARY Audio input OUT Unit 1 AUXILIARY Input hiel 1 A Shielded Cable Ed A Unit 2 J7 MONITOR Audio Unit 1 N A MONITOR Unit 2 4 B B REMOTE Unit 1 B Soeaker Wire d B REMOTE P Unit 2 A Miniature Phone Plug B Subminiature Phone Plug RL 1000 ohms 174 watt Figure 7 5 Connecting Sol to two cassette recorders 3 Set recorder s tone control s at the top of the range maximum treble 4 set PLAY control s for playback mode gt Grave Sol the or then Execute command as appropriate Refer to your SOLOS Users Manual for instructions on how to use tape commands Te m Serial Data Interface SDI The Sol Serial Data Interface 91 is capable of driving RS 232 device such as a modem or a current loop device such as the ROR SS TEY S3 Baud Rate S4 Parity Word Length Stop Bits and Full Half Duplex are used to select the various serial interface options as described in Paragraphs 7 5 7 through cn this section PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES Set 53 switches to select the Baud rate required by the modem current loop device Standard 8 level TTY s operate at 110 Baud 53 2 ON and all other S3 switches OFF For standard 8 level TTY s and most modems set all S4 switches OFF This select
146. TO do so can cause the pad or trace to lift off the board and per manently damage it 5 The Backplane PC board Sol BPB has plated through holes Solder flow through to the component side of the board can produce solder bridges shorts Check for such bridges after you install each component or wire 6 The Backplane PC board Sol BPB has an integral solder mask a lacquer coating that shields selected areas on the board This mask minimizes the chances of creating solder bridges during assembly 6 3 3 Mechanical 1 If you do not have the proper screwdrivers see Para graph 6 4 we recommend that you buy them rather than using a knife point a blade screwdriver on a Phillips screw and other makeshift means Proper screwdrivers minimize the chances of stripping threads disfiguring screw heads and marring decorative surfaces 2 To assure a correct fit and tight assembly be sure you use the screws specified in the instructions 3 Lockwashers are widely used in the Sol cabinet chassis assembly so that screws will not loosen when subjected to stress or vibration When a lockwasher is specified do not omit it and make sure you install it correctly 4 Some instructions call for prethreading holes This is done to make assembly easier by giving you maximum working space for installing relatively hard to drive sheet metal screws If you by pass prethreading instructions you will only make your cabinet chassis assembly more di
147. This strobe disables the Sequence Detector and causes the Strobe Generator to output repetitive STROBE pulses Column 30 also prevents the Sequence Detector from strobing additional data into the OUtpur Ihe Function Latch and Decoder latches and decodes the Low Order Count from the Row Scanner when the function key column in the Switch Matrix is selected by the Column Scanner It then outputs as appropriate LOCAL RST and BRK to 21 and SHIFT SHIFT LOCK UPPER CASE and CONTROL bits to the Encoding ROM The latter three supply three of the seven address bits to the ROM which specify the high order four KBD bits KBD4 7 All keyboard outputs are supplied to J1 which is connected tO Jo the CIrouit Description Refer to the Keyboard schematic in Section X Page X 23 Keyboard operation is controlled by a 3 usec clock circuit consisting of NAND gate U7 R7 and C7 U7 is connected as a Schmitt trigger inverter with negative feedback through R7 and C7 The out put on pin 11 of U7 a square wave with a 3 usec period is inverted in U4 a NAND gate connected as a simple inverter and applied to the clock input pin 11 of U8 U8 operates in a toggle mode by virtue of feeding 158 Q output on 9 to the D input pin 12 Thus its output state changes on each clock to produce a 6 usec and an in verted 6 usec clock on pins 9 and 8 respectively Each of these outputs is connected to a section of 07 wher
148. Tips and Installing Augat Pins IC Pin Configurations TV Interface Pin outs for Connectors S 100 Bus Definitions Switch Functions and Bit PSS QUEE OY Your Personal Genie Article on Types of software 2 105590014 135 MSd 13S dS 13S 135 135 135 135 135 135 135 Ww oo oO p 5135 15 5 1 4 IIOSV 4531 801100 811011 90 601 ewa used 0901 INV LSNOO Sd gig noa IPY SHO NOILONYLSNI V 39 28 gg va 689 v 28 WHO 98 S8 WHO 3 9 WHO 18 V WHX WHX 1 VHX OV 3 VHX vHX D vux 8y s6e 4 ou 1 uoudeoxe Idaoxe SS8Jppe q 91 spy ZV 9V VNV SV VNV VNV cV LV OV 895 36 885 36 885 06 885 26 885 86 885 885 66 885 86 ans 46 805 96 815 56 805 v6 805 26 875 6 ans 16 875 06 48 38 028 20 88 VB 68 88 28 98
149. U 1 15 7 imm E OCI E loss usa 2s ecd EG oo EE SEG DIDNEL Sore 5 eee A a ccooc cB VE OLE R8 MN 725 aun Ro See SoS 2125 572 130 5 COSTI D 26x woe P E Nets SY 22 42 2 UE ZZD LE Z ZARUS 222 case oa ERPE a 222 a AB SL SSeS E i cg po 221 1 B ZZS nase E jELILDLSLDCIUNCLDCLCMN oe _ L eres Te c 4 2252 287 m y Shifted cravacter The character 15 shifted three rows co R3 at the ton of the font and R11 at the bottom Figure 8 6 6575 Character Generator ROM pattern For the second character position the Character and Line Ad dress Multiplexers call up the T in the Display RAM The resulting ASCII code for a T 1010100 ultimately appears on the address in puts to the Character Generator ROM Since the Scan Counter is still at a count of zero the ROM outputs 1111111 This p
150. UMP 000 COEO Step 31 Press RETURN key Lines of 16 bytes of hexadecimal data will scroll move rapidly up the screen until the last address COEO 15 displayed At this point the display will stop scrolling Mab deed PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES DEC Wit Enter Operation The enter operation is used to enter hexadecimal data from the keyboard into available Sol memory AS an example enter 16 bytes of data starting at address C900 and ending at address C9OF as follows Step 32 Type the ENTER command as follows ENTER C900 7 Step 335 Press RETURN key Ihe monitor should display a colon prompt character at the start of the next line Step 34 Type the following data II 22 33 44 55 66 77 9898 99 00 AA BB CC DD EE FE NOTE The slask X terminates the enter function Step 35 you made a mistake in typing the above line of data refer to Paragraph 7 8 3 on Page VII 25 If you made no mistakes press RETURN key Ihe data entered in Step 34 now resides in locations C900 through C90F in the Sol memory S63 TO Verily thal the dro Indeed enter Sol memory simply give your Sol this DUMP command DUMP C 900 CODE Then press RETURN key The line of data you entered in Step 35 should be displayed on the monitor screen preceded by the Starting address Step 37 Using your SOLOS User s Manual experiment with the other commands until
151. UT Og INPUTS 38 9 OUTPUT DATA INPUTS AV 7 PROCESSOR TECHNOLOGY CORPORATION po APPENDIX V Sol TERMINAL COMPUTER PARALLEL PARALLEL INPUTS DATA LNABLE JATA INP NPUTS SHIFT INPUT OUTPUT POTS i M EUM CLEAR fD 20 404 62 61 CLEAR 10 2D 30 40 DATA ENABLE OUTPUT CLOCK CONTROL 10 20 40 LL 15 6 SERIAL A B D CLOCK CLOCK GND INPUT Te INHIBIT MI NI 10 20 INPUTS OUTPUT CONTROL OUTPUTS CONTROL A DATA i PUTS OUT UT 2G SELECT 7 CLOCK OUTPUT GNO CONTROL SELECT DATA INPUTS 1G 7812 and 7912 Pin 1 Input Pin 2 Output Emitiar Pin 3 Ground Cotlector Heat snk surface connected 3 AV 8 PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER APPENDIX V MEMORY ENABLE OUTPUTS OUT 4 IN 4 SELECT 2 SELECT AV 9 Pinouts Parallel Data Interface PDI as Sept 30 1976 used on Processor Tech Sol System MASTER UNIT Male connector J2 Pin 4 Signal Signal J2 pin Signal Signal name mnemonic mnemonic l CG Chassis Ground 14 US Unit Select 2 SG Signal Ground 15 OE Output Enable 3 IE Input Enable 16 XDR eXternal Device Ready 4 DR Data Ready 17 OL Output Load 5 IAK Input Acknowledge 18 OD7 Output Data bit 7 6 ID7 Input Data bit 7
152. UTS Cassette I O FB Data CUTS audio cassette Interface FC Alarm optional FD Data Parallel output Data channel FE Scroll control Display Section FF not usedin Sol PC REV B AVII 7 STATUS PORT INPUT BIT ASSIGNMENTS PORT F8 STATUS SERIAL COMM CHANNEL BIT SIGNAL NAME FUNCTION ACTIVE DIRECTION 0 SCD Serial Carrier Detect EIA 1 carrier 1 SDSR Serial Data Set Ready EIA link ok 2 SPE Serial Parity Error l error 3 SFE Serial Framing Error l error 4 SOE Serial Overrun Error l error 5 SCTS Serial Clear to Send EIA clear 6 SDR UART Serial Data Ready l ready STBE UART Serial Transmit Buffer Empty l empty PORT FA AUX STATUS CASSETTE TAPE INTERFACE PARALLEL I O KEYBOARD INPUT BIT SIGNAL NAME FUNCTION ACTIVE DIRECTION KDR Keyboard Data Ready 9 ready l PDR Parallel Data Ready ready 2 PXDR Parallel eXternal Device Ready ready 3 TFE Tape Framing Error l error 4 TOE Tape Overrun Error l error 5 not used 6 TDR Tape Data Ready l ready 7 TTBE Tape Transmitter Buffer Empty l empty PORT FE DISPLAY STATUS BIT SIGNAL NAME FUNCTION ACTIVE DIRECTION SOK Scroll sec timeout after f time complete scroll CONTROL PORT OUTPUT BIT ASSIGNMENTS PORT F8 CONTROL SERIAL COMM CHANNEL BIT SIGNAL NAME FUNCTION ACTIVE DIRECTION 4 SRTS Serial Request to Send 1 request PORT FA CONTROL PARALLEL I O CUTS CASSETTE I O BIT SIGNAL NAME FUNCTION ACTIVE DIRECTION 3 PIE Parallel Input Enable l pin 3 J
153. Y _5 35 Install the following IC s in the indicated 1 tions Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board indicate the location of pin 1 of each IC Te ANG TYPE 045 741 504 046 Or D076 048 741 500 550 7415367 054 741504 063 7415109 064 7415109 067 8T97 U68 8T97 076 094 1415367 0107 FASS 6 7 Step 36 Apply power to Sol PC and make the following voltage measurements MEASUREMENT POINT VOLTAGE Pin 11 of 0105 Socket 5 V dc 25v Pin 20 of 0105 Socket T5 V 25 Pin 28 of 0105 Socket 12 V 0 V Pin 1 of U51 Socket to F 520 Pin 2 of Socket 12 V dc 6 V All voltages referenced to ground If any voltages are incorrect locate and correct the cause before going on to Step 37 If voltages are correct turn power supply off dis connect power cable and go to Step 37 Step 37 Install the following IC s in the indicated loca CLONS Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board indicate the location of pin 1 of each IC Step 34 continued on Page 1211 2422 Rev A PROCESSOR TECHNOLOGY CORPORATION IM 501 SINGLE BOARD TERMINAL COMPUTER SECIION ILI IC TYPE C o USD ULO5 8080 8080A or 9080A f MOS device Refer to CAUTION on Page 111
154. a gt 28 45 46 47 48 49 50 51 52 REV SYMBOL PWAIT PINTE A5 A4 A3 Al5 12 9 DIOL DIO DIO4 0105 0106 0102 0103 0107 SM1 SOUT SINP SHLTA CLOCK GND 8V 16V S 100 Bus Definitions continued NAME FUNCTION WAIT Processor command control output sig nal that indicates the processor is in the wait state in response to a low READY signal or a HALT instruc tion INTERRUPT Processor command control output signal ENABLE indicates interrupts are enabled as determined by the contents of the CPU internal interrupt flip flop When the flip flop is set Enable Interrupt instruction interrupts are accepted by the CPU when it is reset Disable Interrupt instruction interrupts are inhibited Address Line 5 Address Line 4 Address Line 3 Address Line 15 MSB Address Line 12 Address Line 9 Data In Out line 1 same as pin 94 Data In Out line 0 same as pin 95 Address Line 10 Data In Out Line 4 same as pin 91 Data In Out Line 5 Same as pin 92 Data In Out Line 6 same as pin 93 Data In Out Line 2 same as pin 88 Data In Out Line 3 same as pin 89 Data In Out Line 7 same as pin 90 MACHINE CYCLE 1 Status output signal that indicates that the processor is in the fetch cycle for the first byte of an instruction OUTPUT Status output signal that indicates the address bus contains the address of an output device and the data bus will cohtain the oupu
155. ally coated with wax during the manufacturing pro cess After inserting leads through mounting holes remove capacitor and clear the holes of any wax Reinsert and install LOCATION VALUE ufd ORIENTATION Ci 15 Tantalum i lead bottom right C2 1 Disc None C3 i Disc None C6 Tantalum lead right Ci 15 Tantalum pedes Step 15 Install 2500 ufd capacitors in locations C4 and Gor Bend leads to fit distance between mounting holes insert leads pull down snug to board solder and trim Be sure cto stall CX with aes bead to the right and C3 with its t lead to the left Step 16 Install 202 and O lt 2NZ222 their locations The emitter lead closest to tab on of 02 18 Oriented toward the left and the lead toward the bottom emitter lead of 03 1S oriented toward the bottom and the base lead toward the right Step 17 Read assembly tip 6 on page 11 5 Apply heat Sink compound to the inside of the small black star shaped cooling install ity with the cylinderreal grip down on Q2 by slipping it down onto the can Be sure heat sink does not touch any other component on the board Step 18 Install bridge rectifier FWB 2 MDAIOI1A its location dt the bottom Of The board Apply heat sink compound per Assembly tip 6 on page 11 5 Position FWB2 with its lead at the top and its lead at the bottom insert leads solder an
156. ally coated with wax during the manufacturing pro cess After inserting leads through mounting holes remove capacitor and clear the holes of any wax Reinsert and install LOCATION VALUE ufd TEPE ORIENTATION 04 7 Ds None 2 122 047 44 2222 52 047 dd me C4 047 amp 4 202159 Ay 4 4 X6 047 id 20 421 047 4 y 047 PROCESSOR TECHISLOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION LOCATION VALUE ORIENTATION C10 XA DISC None i M 5152 M CHE N 0725 M CRS Tantalum lead bottom C16 SOA DISO None F o Check 45 volut bus tO ground shorts Using ohmmeter measure between positive and negative mounting pads for C58 There should be no continuity If there is find and correct the problem before proceeding to Step 4 Step 4 Install the following capacitors in the indicated locations Take care to observe the proper valuel type and 1f applicable for each installation Bend leads outward on solder back side of board solder and trim refer to NOTE in Step 2 LOCATION VALUE ufd TIPE ORIENTATION C19 047 01556 None C20 047 21 O47 C24 O47 2 225 0477 2 M C26 047 A b C35 047 Cas 047 P C40 to Tantalum t lead bottom CAT NOM DISC Non
157. an error message are 1 bad read of file tape error or CRC ERROR 2 MODE or Control key used for escaping while reading a tape file 3 command given to non executable file Tape Commands in Brief SOLOS Mas Cape cobmnandsSe GET name unit addr Get a file from tape to memory SAVE name unit addrl addr2 addr3 cave XEQ name unit addr Get then execute a file CAT unit Catalog of tape files TAPE COMMANDS cont Tape Commands in Detail Get a file from tape GET name unit addr This command transfers the specified or next tape file into memory If a name unit is given this command will search forward on the cassette until that file is found The addr parameter if given specifies the memory location at which the file will be loaded If the addr is omitted the file will be loaded as specified in the header Example GET TARGT 2 Result Gets the program WARM from tape unit 2 into memory specified by the tape file header information Returns to SOLOS command mode Get then Execute XFO This command 1S an extension of the command which gets tape file and executes as specified by the header information The unit and addr are optional and operate the same as with the GET command Example FOCAL Result Gets then executes a program named FOCAL from tape unit 1 save f
158. and Out cables described in Paragraph 7 4 1 in this section miniature phone jack to two miniature phone plug adapters are required Since the recorder outputs are most likely unbalanced we also suggest that you incorporate 1000 ohm resistors in the MONITOR adapter as shown in Figure 7 5 on Page VII 29 7 3 also mllusStreoetes mn Schematic Torm how to Connect wo recorders to your Sol When using two recorders you may read or write to both under program control as well as read one tape while writing on the other If you intend to read one tape while writing on the other however you may have to disconnect the MONITOR plug from the write unit with the need for disconnect being determined by the recorder design The MONITOR disconnect must be made if the recorder has a T0 PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VLI monitor output in the record mode Panasonic RQ 413S and RQ 309DS do for example NOTE 1 Recorders on which the monitor jack is labeled MONITOR usually provide a monitor output in the record mode If the jack is labeled EAR or EARPHONE the recorder does Provide s monrttor output in the record mode NOTE 2 To determine if your recorder provides a monitor output in the record mode install a blank tape plug earphone into monitor jack and microphone into MICROPHONE jack Ser recorder Controls CO record and into microphone while l
159. ange R116 kyot brown green red nS Steep 521 Install the following Capacitors Am the indicated locations Take care to observe the proper value and type for each installation Bend leads outward on solder back side of board solder and trim Refer to NOTE in Step 2 LOCATION VALUE E B C29 SL Disc C30 330 Diese Step 52 Install diodes Dl 1N4148 or 14914 D2 1N4001 and Ds through De 14 or am their locations the area of U39 Position all diodes with their dark band cathode to the right Step 53 Install the following DIP switches in the indi cated locations Take care to observe proper orientation LOCATION ORIENTATION 3 gt Switch No 3t Op 0S3 NOx 454 6 Switch NOs ae step 54 Install 01 2N2907 or 2N3460 an its location be tween 055 056 The emitter lead closest to tab on 1s oriented toward the bottom and the base lead toward the right Push Straight down On transistor until 1t 15 Stopped by the leads Solder and trim Step 55 Using two 4 40 x 7 16 binder head screws hex nuts and lockwashers install 25 1 female connector in location Jl serial I O interface Position connector with socket Side facing right and insert pins into their holes in the circuit board Insert screws fro n back solder s
160. any Wax tO ODSEYrve the proper Value applicable for each installation NOTE solder and trim After inserting leads through and install lke VALUE 047 gal Reinsert TYEE ORIENTATION ufd Tantalum 7 lead top urd Disc None Urdu Mylar M Continued on Page V 5 V 4 remove capacitor and EV Pe PROCESSOR TECHNOLOGY CORPORATION Sal KEYBOARD SECTION LOCATION VALUE LIRE ORIENTATION C4 01 utd DISCE None 2 CS 047 uid i 2 526 2047 utd D C Gd 0022 ura gt 2 470 pid G9 220 pid M CF GLO 220 pfd C y soL B y 2047 wid CIS Ud C14 1 5 Utd Tou em dead Step 3 Install the following resistors in the indicated locations Bend leads to fit distance between mounting holes insert leads pull down snug to board solder and CELM LOCATION VALUE ohms COLOR 1 150 brown green brown R2 1 5 0 Ww R3 1 5 0 Ww R4 68 K blue gray orange 25 560 K green blue yellow AR 33 di orange orange orange R7 1 K brown black red R8 Prok brown green red R9 orange black red RI 0 3 K Ww 11 3 K Ww B 2 3 K Ww 13 brown green red R14 Leok R15 R16 K brown black red R17 390 orange white brown R18 i brown black
161. ard assembly drawing X 7 Rev A M Sol KEYBOARD C LOCATION Cl C2 Cy 208 PROCESSOR TECHNOLOGY CORPORATION CAUTION SOME MOS INTEGRATED CIRCULLS ARE USED ON THE SOL KEY BOARD By RELECIRICITY DISCHARGE MOS IC s SO THAT NO DISCHARGE FLOWS THROUGH TEE IC AVOID UNNECESSARY HANDL ING AND WEAR COTTON RATHER THAN SYNTHE TIC CLOTHING WHEN YOU DO HANDLE MOS STATIC CHARGE PROBLEMS ARE MUCH WORSE IN LOW HUMIDIIY CONDITIONS Step 1 Install DIP sockets IHEY CAN BE DAMAGED HANDLE SECIION M Install each socket in the indicated location with its end notch oriented as shown on the circuit board and assembly drawing create solder bridges betwean the pins and or traces Take care not to Refer to Installation Tip on Page 111 9 in Section III NI NN ATION LOC Ul an U3 U4 th Du U20 U21 a UZS E 918 rough 011 hrough 17126 22 1727 SOCKET Pan pin pan PB pin pin pin pin Step 2 Install the following Capacitors the indicated OC leads pull down snug to board bend leads outward solder back side of board Disc capacitor leads em usnally coated with during che qanufacturrng pro COSS mounting holes Clear the nobles Or
162. at he study the appropriate data sheet for that IC Ihe section begins with an overview of the Sol design A block diagram analysis then provides the reader with an understanding of the relationship between the functional elements of the 501 This analysis sets the stage for detailed descriptions of the cir cuitry that makes up these elements The section concludes with a block diagram analysis and circuit description of the keyboard Oz OVERVIEW The Sol Terminal Computer the name implies is both a terminal and computer is designed around the 5 100 bus structure used in other 8080 microprocessor based computers and incorporates all of the circuitry needed to perform either function In essence Sol combines central processor unit CPU with several 5 100 peri pheral modules memory keyboard input interface including the key board video display output interface plus audio cassette tape parallel and serial input output I O interfaces Sol 20 also in cludes a five slot backplane board for adding other memory and I O modules that are compatible with the S 100 bus An 8080 microprocessor the CPU is the brain of the Sol It controls the functions performed by the other system components obtains fetches instructions stored in memory the program ac cepts inputs data manipulates processes data according to the instructions and communicates outputs the results to the outside world Through oUtput p
163. bchassis as shown in drawing on Page X 2 Position ring over the three mounting holes in the side wall of subchassis so the clamping screw faces the bottom of sub chassis and so it will be accessible from the Sol REG end of the subchassis Insert three 6 32 x binder or pan head screws from outer side of side wall through the mounting holes Place 6 lockwasher on each screw and secure with 6 32 hex nut Figure 2 5 shows an assembled Sol 20 power supply subchassis f E kN Im 4 c d i L Figure 2 5 501 20 power supply subchassis assembly Rear of subchassis at left St p 36 Install Small i415 mounting ing for 059 000 ufd capacitor as shown in drawing on Page X 2 Step 36 continued on Page 11 17 Rev B 11 16 PROCESSOR TECHNOLOGY CORPORATION 501 POWER SUPPLY SECTION ILI T Rev B Position ring over the two mounting holes located between FWB3 and the Sol REG so that the clamping screw 15 positioned between the transformer and FWB3 Insert two 6 32 x 1 2 binder or pan head screws from bottom side of chassis through the mounting holes Place 6 lockwasher on each screw and secure with 6 32 hex nut Refer to Figure 2 4 Route Sol PC power cable between C8 mounting ring and the transformer mount C8 in its mounting ring and tighten clamping screw See Figure 2 4 Step 38
164. be enabled when SED tprn 16 Low rhese Tour bits are PE framing error OR OVenrun SGrror DE date TERE CLPoanSmPLtter regos empty 8 6 KEYBOARD Block Diagram Analysis A simplified block diagram of the keyboard is provided on Page X 25 in Section X The Clock Oscillator produces the basic timing signals for the keyboard and they are distributed as indicated At the heart of the keyboard is a Key Switch Capacitive Matrix which can be viewed as a 16 x 16 X Y matrix with X being the column and Y the row Conceptually a key depression increases the ca pacitance between the X and Y coordinates that uniquely define that key The Column Scanner supplies a pulse train to the X lines in the matrix with only one line being pulsed at any given point in time When a key is depressed to increase the capacitance between the Column Scanner output and a Row Scanner input the X Y coordinates for that key are detected to provide an input to the Sense Circuit The Sense Circuit in turn generates an input to the Sequence Detector when a key closure occurs This detector basically detects key closures and count cycles of the Row Scanner to discriminate against false key signals and insure that valid closures are serviced in order In the absence of key closures the Sequence Detector feeds PKD to the Sense Circuit to increase its threshold This action serves to increase the circ
165. both of which are presettable four bit binary counters Both start at count 3 when pin 8 of NAND gate U47 is low and together they count 102 CHARACTER_CLOCKS to define horizontal timing at 64 usec 102 x 628 nsec 64 usec PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECTION VIII SCAN CHARACTER LINE LINE COLUMN NO ADDRESS ADDRESS NO 1 2 3456 7 8 9 VIDEO INFORMATION BITS 1001001 Ho 1 30666000 000000000 blank T 0000 2 SP dcos 011111000 0001 3 6 93 000100000 0010 4 000 00000 000100000 0011 5 0091000959 000100000 0100 6 000 00000 000100000 OTT 7 oor di oO IND 000100000 0110 8 000 00000 000100000 0111 9 9 09 4 09 09 OO 000100000 1000 10 041144000 1001 ii EOT OET 000000000 blank 1010 12 000000000 blank 1001001 13 6066 0 6 0300 000000000 blank 7 ASCII code for I 2 dot Figure 8 2 Example of uppercase character I display SCAN CHARACTER LINE LINE COLUMN NO ADDRESS ADDRESS NO 12345 67 8 9 VIDEO INFORMATION BITS 1110000 jaa i 9070500 060505070 000000000 blank 7 0000 000000000 blank 0001 3 00 6 000000000 blank 0010 4 0 6 0 0 OO 6 06 000000000 blank 5 101110000 0100 6 oOo00 000 110001000 0101 7 4000 100001000 0110 8 o000 000 100001000 0111 9 O000 000 110001000 1000 10 o 0000 101110000
166. by a port strobe from the Address Page and I O Port Decoder VIII 4 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION TION VILI Output data from the CPU that is channeled through the Paral lel Port PP is latched from the Bidirectional Data Bus by the par allel strobe from the Address Page and I O Port Decoder This data 1s made available at P2 the PP connector Parallel input data PID0 7 on P2 however is fed directly to the Data Input Multi plexer for entry into the CPU As can be seen keyboard data KBDO 7 from 23 is also fed directly to the Data Input Multiplexer The keyboard data ready flag though is input to the CPU on the internal data bus Ihe remaining internal source of data input to the CPU is the Sense Switch Logic with the data being input on the Bidirec tional Data Bus This is an eight switch Dual Inline Package DIP array that lets the CPU read an eight bit word when it issues the sense switch strobe via the Address Page and I O Port Decoder The sense switch data source is available to interact with the user s software CPU Support Logic accepts six control outputs from the CPU status information from the CPU s data bus and control signals from the Control Bus It controls traffic on the data buses by generat ing signals to 1 select the type of internal or external device memory or I O that will have bus access and 2 assure that the de vice properly transfers data with the CPU
167. by the CPU only when it executes an input port FF instruction Otherwise the Sense Switches have no bearing on Sol operation Baud Rate Switches 53 1 through 53 8 The setting of the Baud Rate Switches determines the operating speed of the Serial Data Interface SDI Assuming you have not installed any of the K L and M jumper options you can select any one of eight Baud rates Table 7 2 on page VII 15 defines Baud rate as a OF Go L through CAUTION DO NOT SET MORE THAN ONE 53 SWITCH THE ON POSTETON AT THE TO CAN DAMAGE YOUR Sol Parity PS PL swatches amp 5 With these two switches you can select no parity parity even Parity odd parity for data Nand led through the SDI Set 94 5 To TES ON position Xt you want parity When OFF there will be no parity bit A stop bit immediately follows the data if no parity bit is selected o4 l PS selects even or odd parity if 54 5 15 ON IT otherwise has no affect For even parity set S4 to ON Set S4 1 Or Data Word Length WLS I 2 Switches 54 2 amp 3 Use these two switches to select the number of bits excluding parity in the transmitted word for the SDI You have a choice of 5 6 7 or 8 bits Table 7 3 defines word length as a function of 54 2 and 54925 OCOD Bre Selection SBS S44 Set this switch to ON if you
168. can be identified by looking for markings on the laminations of the transformer on either the top or sides If the marking Sol T2 in large letters is found as in the photos below no modification is necessary If the marking 4 3991 in small letters is found make the modification If any other or no marking is found contact Processor Technology for further information If a voltmeter is used to confirm an PROCESSOR TECHNOLOGY CORPORATION 6200 HOLLIS STREET EMERYVILLE CA 94608 415 652 8080 CN 9 page 1 7 77 overvoltage condition unplug all boards in the backplane dis connect the five pin molex connector which supplies power to the backplane board and make the measurements at the connector between the blue wire 8 V dc and the end white wire ground The following parts are included in the modification kit 1 Triad F 57X 25 2 Volt CT Transformer modified 1 Molex commoning block 07 01 70 1 6 32 by 5 machine screw 1 6 32 hex nut 1 6 lockwasher 5 Tywraps With the covers removed from the Sol and facing the front key board side perform the following modifications 1 Remove the A C line cord and video cable from the rear panel 2 Remove the four screws and lockwashers which hold the keyboard circuit board in place 3 Remove the keyboard from the Sol and detach the interconnecting Cable from J3 on the main circuit board 4 Remove the two 8 32 by 5 screws on the right hand chassis lip be
169. ce a two character mnemonic Ep for that same control character In the following paragraphs each key function is described in terms of its role in the terminal mode only and assumes the control character display option is enabled and the LOCAL indicator light is on Many key functions differ from these descriptions in SOLOS command modes BASIC 5 ALS 8 etc As an aid to learning each key location we suggest that you keep the keyboard photo X 26 in view as you study these functions Alphanumeric Punctuation Symbol Keys These keys enter the applicable character into the Sol PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VIT Table 7 4 Sol Keyboard Assignments HEXADECIMAL CODE CHARACTER GENERATION UNSHIFTED SHIFTED CONTROL Symbol Symbol Symbol Displayed Hex Displayed Displayed 6575 6574 6575 4 6574 6575 STANDARD KEYS ESCAPE None None E H J O Ui DAN 0 0 O Ui A N None None gt f O 4 Mob qd PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VLI Table 7 4 Sol Keyboard Assignments Continued HEXADECIMAL CODE CHARACTER GENERATION UNSHIFTED SHIFTED CONTROL Symbol Symbol Symbol Hex Displayed Hex Displayed Hex Displayed
170. ce subchassis over the right rear corner of main chassis and lower it almost vertically into position Attach sub chassis to main chassis using seven 6 x 1 4 and one 6 x 5 16 sheet metal screws and five 6 flat washers Five 6 x 1 4 screws fitted with 6 flat washers are driven through the bottom of the main chassis into the subchassis The 6 x 5 16 screw is driven through the rear hole in the right side of the main chassis into the subchassis The remaining 6 x 1 4 screws are driven through the main chassis into the subchassis Step 17 Place right side walnut masonite assembly in proper position against right side of main chassis and outline the finger well on the chassis Remove backing from one black finger well label and affix it to the right side of main chassis Position label to cover the finger well outline you Made Be sure label extends beyond all edges of the outline Step 18 Using five 10 24 x 3 8 binder or pan head screws attach right side assembly to main chassis and power supply subchassis as shown in Drawing X 9 Insert screws from inside surface of chassis and drive into the plastic inserts Note that the two front screws are driven through the main chassis the two lower rear screws are driven through both the power supply subchassis and main chassis and the upper rear screw is driven through the power supply subchassis Step 19 Assemble expansion chassis U shaped chassis Prethread 12 mounting holes
171. continuity 16 volt Bus Test Measure between pins 52 and 50 or 100 There should be no continuity 8 16 16 Volt Bus Test Measure between pins 1 or 51 and 2 between pins 1 or 51 and 52 and between pins 2 and 52 There should be no continuity in any of the three measurements VI 8 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI REV If you measure continuity indication of a short in any of the preceding tests check your work for solder bridges If you measure no continuity in any of the tests you have completed the backplane board assembly Set it to one side for later installation in the cabinet chassis NOTE Since the Sol right and left side panels are now supplied as pre assembled units Steps 7 through 12 have been eliminated Sol Assembly Refer to Drawings X 8 through X 10 in Section Figure 6 3 show complete Sol assemblies without covers Step 13 Mount keyboard support bracket heavy gauge right angle brackets to each side of the main chassis as shown in Drawing 9 These are mounted with the narrower side of the bracket at the top Attach each bracket to main chassis with two 6 32 x 5 binder or pan head screws and 6 lockwashers Place lockwasher on Screw insert screw from outer surface of main chassis side wall and drive into the threaded bracket mounting holes Step 14 Attach power supply subchassis bracket short leg T shaped bracket to top front of po
172. coupling ring over plug subassembly and screw it onto plug Rev A 13 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Step 27 Install Sol PC in expansion chassis REV B Position Sol PC on bottom of expansion chassis with J1 J2 and J6 through J9 at the rear Align threaded standoffs on bottom of Sol PC with the oblong holes in the bottom of the main chassis Attach Sol PC board to chassis with two 4 40 x 3 16 and six 4 40 x 5 16 binder or pan head screws eight 6 flat washers and eight 4 spring lockwashers as shown in Detail F on Drawing X 8 in Section X Note that the two shorter screws attach to the same standoffs to which S100 connector 911 is attached Place lockwasher and flat washer on screw in that order and drive screw loosely into standoff from bottom of main chassis Leave all eight screws loose Step 28 Connect Sol PC composite video output cable to ex pansion chassis coaxial connector Step 29 Affix black finger well label to left side of main chassis in same manner as you did the right side See Step 17 SURE LABEL DOES NOT OBSTRUCT COOLING CUTOUT Step 30 Using three 10 24 x 3 8 and two 10 24 x 1 binder or pan head screws attach left side assembly to main chassis as shown in Drawing X 9 Insert screws from inside surface of chassis and drive into plastic inserts Note that the two front screws 10 24 x 3 8 are driven through the main chassis the uppermost screw 10
173. ction III White Yellow IOE E TAREE 12 V dC 12 A Ground 5 V dc 6 V White Figure 2 6 ool PC power connector and voltage measurements Yellow White Red White 12004771 eee 18 to 23 V dc Blue 7777771 18 to 23 V dc White Gnd 1 White Gnd 2 lt 7 5 to 11 V de Pirgure 2H la Sol 20 power connector and voltage measurements Rev B 11 19 JE EE Sr de E Si Pam ompoememis oi Ns 3 3 Assembly Precautions om 3 4 Required Tools Sooo on Due lore ME geste isle XO 2 soldering Power Connection J10 Installing and Removing Integrated D Installing Removing Personalit P ME Use of Clip Leads Equipment and Materials o dii 3 6 Sol PC Assembly Test Procedure W CO CO CO S Cle m Personality Module Assembly Sol PCb Assembly and Test Por 625 me Vadeo MES 5 215 qose qose 7 IEE Ase 9 PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL COMPUTERTM SECTION IIT 22 PARTS AND COMPONENTS Check all parts and components again
174. cut the trace leading to the hot lead of 99 On the solder side connect a 6 8 ohm 1 4 watt 5 resistor between the hot pin of J9 and cathode banded end of 014 Also the solder side cut the trace leading to the hot pin of J8 to the feedthrough isolated by the trace cut This change is adding a series resistance to the cassette drive jack to limit the amount of current drawn by the cassette motor from the reed relays Certain models of cassettes might draw excessive current and burn out the relays without this fix NOTE These changes were elaborated in Issues 2 and 3 of ACCESS April and June of 1977 4 20 i 943 C uf to zZz he tJ L LJ H zZ oo mae X 0 5 Sol PC Rev D Component Side 4 19 Figure A m Lco P ro PST ee hs NE 07 9 eu ce ee SS NERO LAMP EAE 5 Rie NEN e A bo Mies np heat A zd m pa a 5538428 6585860 7 SSB RAG e e HESS e 97 TT Te ee lt 52 qu 2 n RU ZN 93583 AY TA TBARS IS
175. d Page 36 TELS SoL PC SINGLE BOARD TERMINAL COMPUTER Hev A N AN NN NN Y OO OO NN s M To neck the serial C PROCESSOR TECHNOLOGY CORPORATION ne LET proceed as follows set set set set as in previous test Switches all OFF Switches all OFF Switches all OFF except 53 1 ON Set all S4 switches to OFF Connect Sol PC video output cable to monitor turn monr tor on and apply power to 90l PC Set Sol PC to local by depressing LOCAL key on keyboard to turn keyboard indicator light on Data entered from rhe kevbosrd should appear on the Sol PCO Talls this test ocate and correct rhe cause before proceeding If the Sol PC passes this test turn monitor and power supply off disconnect power cable and video output cable and go on bo Step 60 Step 60 Install the following resistors in the indicated locations Bend leads to fit distance between mounting holes insert leads pull down snug to board solder and Erim LOCATION VALUE ohms COLOR CODE 10 brow n black orange R118 LO B b bi RELO 10 K 517272 1 0 brown black green R140 LU 3 brown black orange R141 Lo aK brown green yellow R142 10 K brown black orange R143 1 M brown black green R144 47 K yellow violet orange R145 10 brown black orange R146 LO E 5 M R147 Z M redered greern R148 TOU brown black yel
176. d and the RETURN key must be pressed after a command so that SOLOS can execute the command MODE SELECT excepted Step 12 Set for local operation by pressing LOCAL key to turn indicator light on Set for lower case operation by pressing UPPER CASE Indicator quot OU Step 13 Press each of the alphanumeric punctuation and symbol keys As each is pressed the lower case character in the UNSHIE TED column Of Labbe should appesr On Lhe sereen Read Section 7 7 on page VII 17 to become familiar with Table 7 4 NOTE If the MODE SELECT key is pressed SOLOS will return to the command mode and display a prompt character followed by the cursor In this case return to terminal mode by typing TERM in upper case letters followed by a carriage return Step 14 Press SHIFT LOCK key to return keyboard to shifted operation indicator light will go out and repeat Step 13 Each corresponding upper case character should appear from the SHIFTED column of Table 7 4 Step 15 Use the control sequences given in Table 7 4 on Page VII 18 to generate the indicated control characters Control characters are generated by pressing the CTRL control key and while holding it depressed pressing the desired key given in the first column of the table As the table shows in the last two columns the symbol generated by a control sequence depends on whether a 6574 or 6575 character generator U25 is installed in your Sol lwo exam
177. d available as an option on the Sol 10 is provided as standard equipment on the Sol 20 Operating Features The Sol keyboard features N key rollover That is several keys can be pressed at the same time without loss of characters or commands Key entries however are in the order of actual key closures The keyboard circuitry includes a scanning circuit that prevents simultaneous key operation Keyboard Indicators Three keys SHIFT LOCK UPPER CASE and LOCAL have indicator lights to indicate keyboard terminal status When any of these keys is pressed to turn an indicator light on the light remains on after the key is released to show that the status persists Pressing the key again turns the light out to indicate the change in status Mob qo PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES INDIVIDUAL KEY DESCRIPTIONS The exact function of most keys on the Sol keyboard is determined by the software used e g the personality module Others have predefined functions that are common to the CONSOL and SOLOS Personality Modules Note that Key that generates code can redefined by a program to perform a specific funstion The code generated by each key on the keyboard and the corresponding character or symbol produced by the Sol s character generator U25 are given in Fable 7 4 on Pages VII 19 through VII2Zl Table 7 4 has two main headings 1 KEY which identifies the
178. d generates the ASCII escape character 1B The character is displayed BREAK Key Pressing BREAK shifted or unshifted forces the SDI output line to a space level for as long as the key is depressed No character is displayed Some communications systems use this feature Tagus TAB Key Pressing TAB shifted or unshifted generates the ASCII horizontal tab character 09 The character is displayed qued Control Key CTRL shifted or unshifted is used with alphanumeric punctuation and symbol keys to initiate functions or generate the Characters defined in Table 7 4 Table 7 5 defines the ASCII control characters The characters in Table 7 5 are not always displayed on the video monitor A control sequence e g CTRL plus J which produces ASCII line feed requires that CTRL be pressed first and held down while the other key or keys are pressed in sequence Vee T SHIFT Key and SHIFT LOCK Key Indicator The SHIFT key generates no code and is thus not displayed It 1s interpreted as a direct internal operation and when pressed specifically shifts the keyboard from lower case to upper case and from the lower to upper character on dual character keys as on a typewriter The keyboard remains in upper case as long as SHIFT is held down Pressing SHIFT LOCK turn the indicator light on electronically locks the SHIFT key in the upper case position Again no code is generated and no character is displayed Pressi
179. d 13 13 10 8 dOd 12 MSd 54 83 SQA SO 540 15 15 33 154 43 158 33 158 43 158 15 74 158 39 168 29 Q v C 9 OP 1 153 ViS Q IHS XV1S cl 8 15 20 vc vi 3 015 0 01 dS 66 H ava 62 ava 60 a18noa Le le IX1 IX1 IO JLVIGIWWI ayol WH 84 03 83 OdH 03 OY ZH 82 ZNH 05 13H 62 NUn13HWN peioeye 4822 ejep 19 ue 0 JEU uoissa1dxa 10 1 845 09 de 8l 80 god de HOQ Se Qc Sz Ql 61 HOG 50 12 4 89 33 90 93 33 INV 93 85 39 INS 90 IOV 39 99 WD dO vd ddO O3 Odd 73 22 22 22 ZNO Wd 92 11 2 l 60 DE ve HNI oz HNI ve 21 UNI 20 HNI vO lt 44 1 IAW 3 IAW 9 IAW 90 IAN 3i IAN 9i 30 90 gt lt THOd 63
180. d bus compatibility with all Processor Technology hardware and firmware products Power requirements for the Sol PC are 5 V dc 5 at 2 5 A 12 V dc 5 at 150 mA and 12 V dc 5 at 200 mA Parallel interfacing is eight bits each for input and output plus control handshaking signals and the output bus is tristated TTL for bidirectional interfaces The serial interface circuit in cludes both asynchronous RS 232 and 20 mA current loop provisions 75 to 9600 baud switch selectable Seven level ASCII encoded TTL keyboard interfacing re quires a 2 to 10 usec strobe pulse after data is stable The dual rate 300 or 1200 bps bits per second audio cassette interface is program controlled and self clocking with phase lock loop It includes automatic level control in both the record and playback modes Recording is CUTS Byte standard compatible asynchronously Manchester coded at 1200 2400 Hz or 600 1200 Hz The video display circuitry generates sixteen 64 character lines from data stored in an on card 1024 8 bit word display RAM Alphanumeric and control characters the full 128 upper and lower case plus control ASCII character set are displayed black on white 1 1 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION I or reverse switch selectable Solid video inversion cursors with switch selectable blink are programmable The display output is standard EIA 1 0 to 2 5 V p p with composite negative sync wi
181. d punctuation marks except the comma and semicolon and all lower case characters except the Jj p q and y As shown in Figure 8 3 dot lines five through 13 are available to display characters that normally extend below the base line lower case j p and y plus the comma and semicolon Now that we have a feeling for how characters are formed on the video monitor screen we will move on to the circuit description Refer to Display Section Schematic in Section X Page X 18 The 14 31818 MHz DOT CLOCK which defines the period of one dot 69 8 nsec in a character display matrix controls all timing in the Video Display Generator DOT CLOCK is applied to pin 2 of U28 a four bit binary counter that is preset to count from seven through 4 5 divide CLOCK by nine Two 1 991 MHz outputs are supplied by U28 LOAD CLOCK on pin 11 and CHARACTER CLOCK on pin 12 Pin l l 25 low acLtive pulse or one DOT CLOCK duration Pin 12 18 high for five and low for four DOT CLOCK periods Both the LOAD and ICHARACTER CLOCK low to high transitions occur synchronously on the same DOT CHARACTER CLOCK which defines the period of one character position 628 nsec is inverted in U49 to become CHARACTER CLOCK It performs most of the clocking functions in the Video Display Gen erator and is made available on pin 4 of J4 for use by external graphic display devices CHARACTER CLOCK is in turn divided in U31 and U33
182. d trim Step 19 Install large heat sink Ul and U3 in their loca tions on the bottom left corner of the circuit board 2 POG theo large black heat sink flat side to board over the square foil area in the lower left corner of the PC OU Orient sink so that the two triangular cutouts in the sink are over the two triangles of mounting holes in the board Position Ul 7812 on heat sink and observe how leads must be bent to fit mounting holes Note that the center Tead must be bent down approximately 0 2 inches PROCESSOR TECHNOLOGY CORPORATION 501 POWER oUPPLY SECTION 11 Rev B further from the body than the other two leads Bend leads so that no contact is made with the heat sink when Ul is flat against the sink and its mounting hole 15 aligned with the holes in the sink and PC board Apply heat sink compound per Assembly Tip 6 on page 11 5 Fasten Ul and sink to board using 6 32 x 1 2metal screw lockwasher and nut Insert screw from back solder side of board and drive nut finger tight Position U3 7912 on heat sink determine how leads must be bent as you did for Ul and bend leads Place a rectangular mica insulator over the leads of U3 so that it Tully overs the Side che package Apply heat sink compound to U3 the heat sink and both sides of the mica insulator Bend the two outside leads of U3 slightly in toward the center lead insert Jesds in mo
183. d what was played back Observe the following pointers for best results l Keep the recorder at least a foot away from the Sol or other equipment which can generate magnetic fields The recorder can pick up hum which may generate errors 2 Keep the tape heads cleaned and demagnetized in accordance with the manufacturer s instructions 3 Use high quality brand name tape Cheap tape can wear down the tape heads and give erratic results 4 Bulk erase tapes before using 5 Keep the cassettes in their protective plastic covers in a cool place when not in use Cassettes are vulner able to dirt high temperatures liquids and physical abuse 6 Set the tone control at midrange and set the volume control about 2 3 full volume The Sol has an automatic gain control circuit which compensates for a wide range ef levels but operation in the middle of this range will PROCESSOR TECHNOLOGY CORPORATION 6200 HOLLIS STREET EMERYVILLE CA 94608 415 652 8080 A 3 7 71 A 3 give the most reliable results Experiment to find the best setting of volume and tone controls On some cassette recorders the microphone can be live while recording through the AUX input Deactivate the mike in accordance with the manufacturer s instructions In some cases this can be done by inserting a dummy plug into the microphone jack During recording some recorders present the signal being recorded at the monitor or earphon
184. data from the UART that appears at pin 1 of U56 also drives transistor Ql by way of R45 and R46 to supply the serial cur rent Loop output SCLO on pin Ll Of alls OL supplies 20 ma max Lor sa binary no current ror a binary 0 Pin 23 of 21 connected through R23 to 12 V dc is the serial loop current source 55605 can supply up to 20 ma of current to ground and is used when the external current loop device has no current source Data received from a current loop device enters Sol on pins lc cre us Quum Ene for a Sume 20 Sur rent for 1 This input is rectified by bridge rectifier D3 D6 and applied to a light emitting diode LED in optical isolator U39 As its name implies U39 electrically isolates the current loop circuit from the rest of the Sol This isolation permits a high offset voltage on pins 12 and 13 of 41 For 1 the LED is energized and PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION LON VELI the light is optically coupled to the base of a photo transistor in US9 to the transistor to conducts Conduction translates to a low or mark level at the input pin 13 of U38 Since both the current loop and RS 232 received data SLR1 SLR2 and SRD respectively share the input to U38 both should not be used simultaneously There are five external control signals in the RS 232 section of the SDI UART two are sent to the exte
185. de facing away from the terminal numbers on the block Then gently push lug into appropriate terminal receptacle until it is fully seated Install the 31 4 fuse holder to power switch cable sup plied with your Sol REG kit This Gable female spade lugs at both ends Connect one end to the bottom terminal of the on off switch and the other to the longer male spade lug on the fuse holder Connect the AC receptacle wire closest to the fan to the other fuse holder lug NOTE The green AC receptacle wire will be connected later Connect other AC receptacle wire to terminal 44 on the commoning block furthest away from the fan Connect upper wire of fan cord to terminal 3 of the commoning block closest to fan Connect lower wire of fan cord to terminal 5 of common ing block furthest from fan Put fan closure assembly aside KESS PROCESSOR TECHNOLOGY CORPORATION ool POWER SUPPLY OEC LION LI 2590 asma 501 Assembly and Test Circuit references values and outlines are printed on the component side of the board to assist in assembly 10 501 252 beard for Older shorts between traces broken traces similar detects Lr Visual 12nspection reveals any detects the board to Processor Technology for replacement If the board 15 not defective proceed to next paragraph S
186. do port 3 user written routine verify the following 1 The appropriate user written routine is in memory 11 address of the appropriate I O routine is entered into the CUTER system RAM area The system RAM area begins exactly 2K 800 hex after the beginning of CUTER first word of this area is used to contain the address for the user Input routine The second word will contain the address of the user Output routine Addresses are entered Jp LOT rer J Execute location ZERO The CUTER loader will have properly prepared this location to either transfer control to the CUTER just loaded or to indicate an error while loading CUTER If there was no error CUTLER wrll now oe mmnm conmurol Remember to turn off the cassette machine and remove the CUTER tape K IF your computer halts again this means one of the following errors has occurred Display memory location ONE to determine the error code The error code will be one of the following Error Gode Hex Meaning 00 The specified load address was not within the range 0200 F400 or the tape file loaded was hot CUTER OT A tape read error was detected 02 Ihere was no tape read error but the CRC error checking character was invalid 40 The file was loaded but it was not CUTER 25 REV A APPENDICES AI AII AVI AVII AVIII Deleted 8080 Operating Codes Standard Color Code Loading DIP Devices Soldering
187. e 36 b b E R41 M E M Rog a n E Rol Trok N M b b R53 Tor M E N R54 Ni M M R55 Jd Sc M R56 do b b R57 Tes M gt M R58 orange orange brown R107 O K brown black orange R108 qp K R109 E R110 IW R111 DO E IO lt kh R113 LO K R114 10 ii B RACES doe brown green red Step 31 Install diode D7 1N4148 1N914 in its location between 046 and 047 Position 07 with its dark band cathode at tlie DOttotm Step 32 Install 20 pin header in location J3 keyboard in terconnect between U64 and U65 Position header so pin 1l is in the upper left corner An arrow on the connector points 1 44 Step 33 In the jumper area labeled PHTM the assembly drawing below 064 install Augat pins in mounting holes and Refer to Installing Augat Pins in Appendix IV Using 24 bare wire install a jumper between pins F and G Step 34 In the jumper area labeled RST on the assembly drawing between 076 and 077 install Augat pins in mounting holes N and P Refer to Installing Augat Pins in Appendix IV Using 24 bare wire install a jumper between pins N and 112 525 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION ILL C J
188. e C42 044 bi C45 20 A AS GOG 2 047 di AS C58 1 5 Tantalum DOS top C39 129 Tantalum lead top GOG Tantalum dead top C65 Ay Disc None Step 2 Check 5 volt Dus ground shorts Using an ohmmeter measure between the positive and negative lesds of C58 You should measure at least 100 ohms Less than 100 ohms indicates a short If required find and correct the problem before proceeding to Step 6 NOTE In this and subsequent resistance measurements any value greater than the minimum may normally occur even much higher unless otherwise indicated Step 6 Install the following capacitors in the indicated locations Take care to observe the proper value and type for each installation Bend leads outward on solder back side of board solder and trim Refer to NOTE in Step 2 Step 6 continued on Page 111 12 Hev A TET PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION IIl LOCATION VALUE ufd TYPE ORIENTATION C9 047 DISE None 047 S n 047 P c UNO 047 M o 5222 047 M Cy 5220 047 y 047 v 4220 047 b C46 047 C C Check Tor 5 volt bus to ground shorts Using measure between the positive and negative leads of C58 You should measure some resistance Z
189. e bDoserd and bend tie beads outward oO Secure Chem solder and trim all leads LOCATION VALUE TPE Je GLS Dipped Tantalum 2 Dipped Tantalum Dipped Tantalum Dipped Tantalum 204 7 Disc Ceramic not used on 2708 0 version Check toy shorts Using an ohmmeter on OHMS times 1K or OHMS times 10K scale make the following measurements A typical reading is 1 Megohm A reading less than 10K indicates a short Measure between edge connector pins 2 and A15 Measure between edge connector pins 14 and A15 Measure between edge connector pins Al and A15 If any measurement indicates a short find and correct the problem before proceeding Bev Step 6 Using two 2 50 x 179 binder Dead screws Install IV 4 PROCESSOR TECHNOLOGY CORPORATION Sol PERSONALITY MODUL SECITON IW handle bracket 501 10 45 Position bracket on front com ponent side of board at the right end as shown in Figure 4 2 Align bracket holes with mounting holes in board in Sert screws from back solder side of board and drive into bracket No nuts are needed since the bracket holes are tapped Right End Of PC Board 2 96 3 378 bue SHELL bPigure 4 2 Handle bracket 901 1045 Installation Step 7 If you have a 2708 0 version with the 9216 ROM windowless omit this step If you have the 2708 1 ver sion find the area above the Ul socket
190. e each is AND ed with the 3 usec clock This generates two negative going clocks at pins 8 and 6 of U7 These outputs are called 11 AE PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON ALII 02 respectively This circuit thus generates a symmetrical two phase clock with each phase having a 6 usec period with a 1 5 usec nega tive going pulse 101 advances the cascaded ripple counter U5 and 6 in the Column Scanner circuit U5 06 gates U4 and decoders 017 and 021 Uo divides 101 by two on each advance The output on pin 12 is consequently a square wave with a 12 usec period the output on pin 9 15 a square wave with a 24 usec period and so on to pin 11 which has a 96 usec period The output on pin 11 is then divided by two in 05 to provide 192 384 760 and 1536 usec periods We will call these Clock 1 for the 12 usec period Clock 2 for the 24 usec period Clock 4 for the 48 usec period and so on from Clock 8 16 32 64 and 128 Clocks 16 32 and 64 are applied to the A B and C inputs of binary to decimal decoders U17 021 order for these decoders to yield outputs their D inputs pin 12 must be low U4 is used to enable one or the other of these inputs with Clock 128 being the de termining factor When Clock 128 is low 017 is selected through U4 when 101 is high at pin 4 of 04 U21 is selected when Clock 128 is high and 101 is high at pin 13 of 04 By AND ing
191. e original joint A blob or lump may well be a solder bridge where enough solder has been built upon one conductor to overflow and take on the adjacent conductor Due to capillary action these sol der bridges look very neat but they are a constant source of trouble when boards of a high trace density are bing sol dered Inspect each integrated circuit and component after soldering for bridges 7 To remove solder bridges it is best to use a vacuum solder puller if one is available If not the bridge can be re heated with the iron and the excess solder pulled with the tip along the printed circuit traces until the lump of solder becomes thin enough to break the bridge Braid type solder remover which causes the solder to wick up away from the joint when applied to melted solder may also be used INSTALLING AUGAT PINS Augat pins are normally supplied on carriers e g 8 pin and l6 pin carriers In many cases the PC board layout permits Augat pins to be installed while still attached to the carrier or a portion of the carrier In other cases the pins must be installed singly TO install two or more pins that are still attached to the carrier proceed as follows NOTE It is perfectly alright to appropriately cut a carrier to accommodate the instal lation For example an 8 pin carrier can be cut in half 4 pins each across the short dimension to fit a 4 pin 4 corner layout It may also be cut in half along
192. e output In a system with two cassette recorders this could cause problems if an attempt was made to read from one recorder while the other was writing Since both recorders share the same audio lines the monitor output of the recorder which was recording could interfere with the signal being read from the other recorder If you record more than one file on a tape side SAVE a special file which could be named END to let you know when you have played past the files of interest After recording the last file on a side rewind the tape set the digital counter to zero and issue a CATalog command see SOLOS CUTER User s Manual As each file header is displayed make a note of the read ing on the digital counter the exact name of the file load address and file length Mark the cassette with this information to make file retrieval much easier If you experience a read error use the following procedure to isolate the problem Ls Check for proper settings and make sure you have followed the pointers above Check cables for intermittant connections and shorts Note the exact reading of the digital counter at the time of the error Rewind the tape and try to read the same part of the tape again If the tape reads without errors this time the error was not recorded on the tape If there is a read error at the same point then the error is re corded on the tape Rewind the tape and record a file on the same part of th
193. e tape Read the file If the tape reads without errors then the original read error was generated during the recording process If there is still a read error at the same point then the cassette itself is faulty 7 77 page 2 2 SOl MANUAL ERRATA Sol MANUAL ERRATA NOTICE 3 1 Reference Section X Drawings Drawing X 17 Input Output In the Baud Rate Generator section of this schematic the function of switch S3 7 is incorrectly shown as selecting 2400 4800 Baud and 53 8 is incorrectly shown as selecting only 9600 Baud Change the schematic to show that 3 7 selects 2400 Baud only and that 53 8 selects 9600 4800 Baud Draw a line connecting points L and M to indicate a jumper 2 Reference Section VII page VII 15 Table 7 2 In the Baud Rate column of this table change 4800 to read 9600 Also in the footnote with the triple asterisk change the phrase SDI operates at 9600 Baud to read SDI operates at 4800 Baud ES 3 6 77 mM PROCESSOR TECHNOLOGY CORPORATION 6200 HOLLIS STREET EMERYVILLE CA 94608 415 652 8080 Sol MANUAL ASSEMBLY PROCEDURE CHANGE NOTICE ASSEMBLY PROCEDURE CHANGE NOTICE 6 2 Rev This Change Notice concerns the Sol REG board and applies only to Revision Level B boards A problem was detected in early Sol REG boards in which the crow bar circuit would trigger without adequate cause and short circuit the 5 volt output A circuit change has been made which wil
194. each character row and appears at pins 7 and 10 of Text Counter U62 to enable it to count Thus the Text Counter counts Character Cows It resets itself with its carry output pin 15 through another in verter in U87 with the reset count being determined by the state on prn 10 VDISP of flip flop U435 VDISP rs low the Text Counter resets to a count of 0 if VDISP is high it resets to a count or 12 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILI Assume VDISP is active low which it is during the vertical display portion of the displayable area on the screen Refer to Figure 8 4 U62 is then preset to a count of 0 and will count from through 15 16 character rows The resulting carry output count 15 of the Text Counter causes the U43 VDISP flip flop to toggle It also appears as a low on the load input of the Text Counter The Text Counter is also enabled to reset by virtue of the OVERFLOW_LINE going low after the reset of the Scan Counter Since VDISP is now high the Text Counter is reset to a count of 12 and will count 12 through 15 four character rows The carry output from the Text Counter then causes the U43 VDISP flip flop to toggle and the Text Counter is reset to a count of 0 We can now see that the Text Count er counts 16 character rows when the display is active VDISP is low and four character rows when the display is blanked VDISP is high The total o
195. econd bit location 020 when 02 goes low at pin 20 of U20 When this happens DO2 pin 12 of U20 goes high to indicate the new status OI chis The D02 output is inverted in 010 and applied to input pin 2 of another U26 D flip flop and to the Capacitance Keyswitch Detector as PKD Serves to lower the detector threshold that rs tbe de tector offers less resistance to its input This is positive feed back that allows the detector to discriminate between noise and a key closure Note that two key closures are required before the detector threshold is lowered The inverted D02 output from U20 also appears at the D input prn 2 026 Since this flop is clocked by 1 the prior status of PKD called minus 1 is already present in this latch on output pin 5 If we are on the second count cycle of a key clo sure 5 2s high we are the third count or more it 15 low to inhibit 025 As previously mentioned PKD minus 1 is also con nected to the NOR gate 016 used to feed data to pin 11 of U20 from KE YAEL Baas s When the current KEY signal is released pin 12 of NAND gate 027 and 5 of NAND gate 016 go high The 016 NAND gate that in puts to pin 4 of Ul6 looks at KEY minus 1 on pin 2 and the comple ment or KLPKDumrnus l on pin l pin 1 Xs high for the first one and a halt counts and pin 2 18 high for the first count Upon re lease of KEY therefore pin 3 of 016 i
196. ed timing to input pun CO Ot Up RECOVER CLOCK is produced by a phase locked loop U110 ano ther 0112 binary up counter and the first and fourth sections of 0111 The signal input pin 14 to U110 is supplied from output pin 1 of D flip flop 0113 is a constant frequency regardless of whether one or two transitions are detected in the read data during the count out time 12 counts of the U112 counter with outputs on pins 13 and 14 A phase comparator in U110 compares the signal input to the output of a voltage controlled oscillator VCO in U110 pin 4 By feeding the VCO output through a counter the other half of 0112 before feeding the counter output back to the compare input pin 3 of U110 the circuit acts as a frequency multiplier The output of this circuit remains locked therefore to a multiple of the signal nm pro I4 oT ULLO The output OE JULIO is nominally 1942 KHz The is determined by the signal input which in turn is a function of tape Speed other words the phase lock loop circuit tracks input fre quency variations And it will track such variations within its locking range which is determined by the setting of variable resistor VRS connected to prn 12 0110 For high speed the divide by four output of U112 pin 4 is selected as RECOVER CLOCK For low speed the VCO output of 0110 is selected for RECOVER CLOCK This clock serves a
197. ed of Display Input Output Commands set Out Command oet In Command oet Tape Command Type Command oet Execute Command Custom Input Output Commands UI UIA A J SOLOS CUTER User s Manual TABLE OF CONTENTS Dy SET COMMANDS cont Set CRC Error Checking Command Set Number of NULLS Command SUBROUTINES AS to SOLOS Machine Language Interface PSeuco POrtS LOr DOLOS Ports FOr CUTER Defined Register Usages SOLOS Jump Table Defined Jump Table System Entry Points DOLOS SLNE AINP SOLOS Output Entry Pores SOUT AOUT SOLOS VDM Display Driver Cassette Tape Entry Points to SOLOS File Header Block Access Read Tape Block Routine Write Tape Block Routine Byte Access File Open Routine Write Byte Routine Read Byte Routine Close File Routine LOADING amp EXECUTING CUTER LLL 1 12 727 17 17 18 18 T INTRODUC TION SOLOS is a 2048 byte program that configures the Sol 20 and one or two cassette tape recorders into a powerful stand alone computing system SOLOS takes advantage of the Sol 20 s built in hardware peripherals and the 8080 instruction set to optimize the convenience and power of the inherent computer capabilities of the Sol Outstanding features of SOLOS include STANDARDIZED I O SOFTWARE PROTOCOL which makes all 501 20 I O keyboard display serial paral
198. ed to the board Then solder the unbent pins on all sockets Now straighten the bent pins to their Original position solder LOCATION SOCKET CF UL through 21 Le pin 1224 through 24 14 qun ER 24 pin CE UZO through 551 16 pu JP Use 14 pin C d 2029 None U40 through 43 Lorn U44 through 49 14 pin top MSG 16 pin Co Ul 10 52 16 pin Cob ChEOUgb 53 14 pin 056 cam ones 2 US ch rough Ol 14 pin Continued on Page Rev B T9 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION LXI LOCATION SOCKET UC y 9 9 U69 40 pin o UO through 9 LOPIN U74 14 pin WI pone lh el PE PN 082 None CJ USS led U84 85 Ugo 14 pin 2186 through 20 Hl 14 pin Us through 97 3 95 10 0 T4 C y Urol TG ULOZ 14 pin Cy ULO S None 0104 None ULOS 40 pan 906 L07 Le Dan ULOB o pan UIUS LLA spent Spare locations not used Note that 0105 notch is positioned at the top Step 2 Install the following capacitors in the indicated locations Take care to observe the proper value type and orientation if applicable for each installation Bend leads outward on solder back side oil board solder and CEI NOTE Disc capacitor leads are usu
199. eight line parallel output port an eight line sense switch logic input port and a unidirectional eight line internal data bus The use of a unidirectional input data bus accommodates Sol s internal low drive memory and 1 0 devices that do not meet the heavy drive requirement of the bidirectional data bus The low drive requirement of the internal bus also allows using the tri state abilities of the UART s Universal Asynchronous Receiver Transmitter in the serial and audio cassette I O circuits without additional drivers All CPU data and address lines are buffered through tri state drivers to support a larger array of memory and I O devices than would otherwise be possible with the 8080 output drive capability Data input to the CPU is selected by a four input multiplexer from the Keyboard Port Parallel Port Bidirectional Data Bus and Internal Data Bus The Internal Data Bus is the source of all data input to the CPU from Sol s internal memory the serial interface and the cassette interface The Bidirectional Data Bus is the source of all data fed to memory and I O both internal and external It is also the source of data input to the CPU from eight internal sense switch es as well as from external memory and I O o DEED BLOCK DIAGRAM ANALYSIS Sol BPC Du dao Functional Elements And Their Relationships As can be seen in the Sol block diagram on Page X 24 in Sec tion X timing signals for Sol are derived from a crystal contro
200. eir relation to input selection is as follows both are active high the multiplexers select the Bidirectional Data Bus 2 When the keyboard is called up by the CPU only IPORT IN FC is active low to make MPX ADR A low This selects the Keyboard Data Bus 3 When the parallel port is called up by the CPU only IPORT IN FD is active low to make MPX ADR low This selects the Parallel Input Data Bus 4 When the CPU selects any I O port that uses the Internal Data Bus only SEL z or U4 and 901 2 active Thus both MPX ADR and are low to select the Internal Data Bus Two other conditions defined by PAGE CC on pin 2 and MEM SEL on pin 1 of NAND gate U44 are possible When any of the four memory pages in the Sol are accessed MEM SEL goes high and an inversion in 044 is normally high appears as low MPX ADR A to select the Internal Data Bus Should Page CC the Display RAM be addressed PAGE CC also goes active low to override MEM SEL MPX_ ADR A and _B are consequently high to select the Bidirectional Data Bus These two conditions are required since the ROM and System RAM use the Internal Data Bus and the Display RAM uses the Bidirectional Bus The address outputs of the CPU A0 15 are placed on the Ad dress Bus via tri state drivers U67 68 and 81 These drivers are normally enabled since pin 3 of inverter U49 is pulled high by R36 ADD_D
201. en adjusting the VCO center frequency to account for part variation MID vendors Also change the value of R154 from 190K to 47K To reset this frequency turn Sol on and measure pin 4 of 0110 It should read 14 0 KHz or 71 4 usec This change is advised in CHANGE NOTICE 11 3 If your Sol has a revision B Regulator PCB it may be necessary to perform a mod to the crowbar circuit to enhance its reliability These changes may be found in CHANGE NOTICE 46 2 REV C 4 16 Sol REV F TO G The following are the changes from a Revision F Sol to a Revision G Sol 1 Substitute a 15K 1 4 watt 5 resistor for R29 formerly a 19K resistor Substitute a 279 ohm resistor in place of R21 formerly a 470 ohm resistor Install 1 length of tubing on R29 and bend lead near resistor body to form a 90 degree angle With the PCB legend in the normal reading position connect the angled end of R29 to the left hand lead of R23 470 ohm This connects the resistor to 12 Volts See diagram below for details This change was covered in CHANGE NOTICE 19 and is to increase the drive going into U38 of the serial current loop input BEFORE 5V R23 231 A A tay R2 470 1 2w LA 470 AF IER 12V R25 6 470 R29 LA 191 424 m 77944 15K bw 3 72 pa D3 4 17 Sol REV to REV The following changes bring Revisi
202. eration 15 ready for use with the Sol PC Single Board Terminal Computer Having completed the Sol keyboard power supply Sol PC and person ality module you are now ready to assemble the Sol cabinet chassis Cabinet chassis assembly instructions are provided in Section VI Rev A MES VI Sol CABINET CHASSIS ASSEMBLY 6 6 6 REV A 1 2 3 THELOGUGCION s Parts and Components e Assembly w 25 iw ie ox ve sms Tix Ie E 6 43 2 Blectrica b 6 3 3 M chanrcal Required Tools Equipment and Materials Orientation 2 ww wo 6 5 1 Sol Backplane Board 501 6 5 2 Sol Cabinet Chassis Assembly TOSE e a e 4 4 aw s s 6 6 1 Backplane Board 501 Assembly dq c dU YIN es e x MI L 1 1 VI 1 1 VI 5 gt VI 6 VI 6 VI 6 6 VI 6 VI 6 VI 9 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI 6 1 INTRODUCTION This section covers assembly of the Sol 20 chassis and cabinet The instructions contained herein assume that you have already assem bled the power supply and Sol PC Single Board Terminal Computer including the personality module 6 2 PARTS AND COMPONENTS You will need the parts listed in Table
203. ero resistance ohmmeter indicates a short If required find and correct the problem before proceeding to Step 8 Step 8 Install diodes D8 1N4148 1N914 11 1N5231B and 012 1 4001 in their locations in the area below 090 through U92 Position D8 with its dark band cathode to the right DLL wath bend st the bottom and DIZ with its band at the top NOTE The leads of D12 and its mounting holes are a snug fit Take care when instal ling this diode obep 9 Install the resistors In the Indicated LOns holes insert leads for each installation Side board Bend leads to fit distance between mounting pull down snug to Josrd solder I Puma LOCATION VALUE ohms COLOR CODE 2104 EO brown black orange ROS brown green red R106 Y n REU 100 watt brown black brown RAGS 100 watt 2 S R132 100 watt 330 orange orange brown R134 330 RGS 13506 TO uk brown black orange 4 7 yellow violet black Step 10 Install the following capacitors in the indicated locations Take care to observe the proper value and type Bend leads outward on solder back solder and trim Refer to NOTE in Step 2 115312 PROCESSOR TECHNOLOGY CORPORATION IM Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION III LOCATION VALUE E B Cog 1 HISE 43
204. es otherwise it is no longer necessary Write the following note in the manual on page VI 8 next to the heading for Section 6 6 6 Skip to 6 6 3 To achieve a better grip in the tinnerman plastic inserts in the Side panels the 10 screws which mate with the inserts have been changed from type 8 32 to type 10 24 Document these changes in your manual now by making notes in the manual as indicated below This will save you confusion later during assembly 1 Change Table 6 1 page VI 2 as follows Change 1 Left Side Piece Walnut to 1 Left Side Assy Change 1 Right Side Piece Walnut to 1 Right Side Assy Delete 1 Left Side Piece Masonite Delete 1 Right Side Piece Masonite Change quantity 8 32 x 1 2 Screw Machine from 11 to 3 Change 2 8 32 x 1 Screw Machine to type 10 24 Delete 12 5 8 Screw Wood Delete 10 Tinnerman Plastic Inserts Tapped Add 8 10 24 x 3 8 Screw Machine 2 Change all references in Steps 18 and 30 pages VI 12 and VI 30 from type 8 32 to type 10 24 3 Change items 9 and 10 in Drawing X 10 from 8 32 to 10 24 CN 13 11 77 page 1 of 1 Ref ECN Nos 10166 10197 Processor Technology Processor Technolo 7100 Johnson Industrial Drive 415 829 2600 Corporation 97 Pleasanton 94566 Cable Address PROCTEC Sol MANUAL CHANGE NOTICE 14 Step 27 on page 11 14 calls for the connection of the white wire from the 501 20 DC power cable to pad X4 a
205. es the transfer by switching the Data input Multiplexer to the Internal Data Bus The A enters the CPU on the Internal Data Bus and is sent to the Display RAM on the Bidirectional Data Bus Operations involved in displaying the A are identical to a keyboard entry Now assume the CPU wants to send an A to the SDI UART for transmission The CPU under program control sends the SDI UART status input port strobe via the Address Page and I O Port Decoder to the UART In turn the UART responds with its status on the Inter nal Data Bus Assuming the UART is ready to transmit the CPU places the ASCII code for the A on the Bidirectional Data Bus and sends the SDI UART data output port strobe which loads the Bidirectional Data Bus content into the UART s transmitter section The A is serialized by the UART and sent out the transmitted data pin of Jl 8 4 POWER SUERTE CIRCUIT Refer to the Sol REG and Sol 10 or Sol 20 Power Supply Sche matics in Section X Pages X 12 13 and 14 The Sol power supply consists of the Sol REG regulator and either the Sol 10 or Sol 20 power supply components An 8 V dc un regulated supply in the Sol 20 is the only difference between the two We will therefore describe the complete Sol 10 supply fol lowed by the unregulated 8 V dc supply in the Sol 20 VILEL 6 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION TION VILLI Fused primary power is applied through S5
206. estart signal on pin 13 of J3 or by closing 51 1 if the N P jumper is in In either case C15 is discharged through R58 and then allowed to recharge after KBD RESTART 1s removed or 51 1 is opened POC also resets all stages of D flip flop U76 the phantom Start up to zero Oh initial Start up che CPU four fetch machine cycles refer to Intel 8080 Microcomputer Sys tems User s Manual in accordance with program instructions For each fetch the CPU outputs a DBIN on pin 17 U76 connected as a four stage shift register is clocked by the inverted DBIN signal on pin 3 of NOR gate U46 Thus PHANTOM on 5 100 Bus pin 67 is active low assuming the F to G jumper is in for the first four fetches or machine cycles After the fourth DBIN PHANTOM goes high PHANTOM is used to 1 disable any memory addressed in Page 0 that has Proces sor Technology s exclusive Phantom Disable feature and 2 cause the Sol program memory ROM which normally responds to Page CO hex to respond to Page 00 hex The second function is discussed in Para Graph 93592 2 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILLI The inverted DBIN on pin 3 of U46 is also applied to pin 12 of NOR gate U46 and inverted to appear as PDBIN on S 100 Bus pin 78 This section of 046 also allows DIG1 bus pin 57 to override DBIN is used when an external DMA device replaces the CPU in terms of writin
207. et Write Tape Block Routine WRBLK The entry point for WRBLK is C016 On entry Register A contains unit and speed with the same bit values as specified for RDBLK Registers H amp L contain file header address The file header information will be written onto the specified tape unit followed by the data On exit Normal return Carry Flag is cleared and data has been transferred to tape There are no error returns Byte Access Data stored on or about to be stored on a tape should be considerec a file In a SOLOS file data is stored one byte at a time as a string of bytes along the tape with no assumed meaning or structure It is simply a collection of bytes that can be accessed by someone with responsibility for the intelligence of the data When writing to tape SOLOS records the data in a form that allows the data to be read from the tape later When reading from tape SOLOS provides the management to access each byte sequentially SOLOS also provides start and stop control of two units File opera tions view unit 1 as File 1 and Unit 2 as File 2 Thus data in Unit 1 is associated with File 1 and data in Unit 2 is associated with FILE When using Byte Access two important user management operations are necessary As shown in Figure below the first is to open a file to tell SOLOS you want to access the file The second is to close a file to inform SOLOS you are finished with it Accesses 21 22
208. etween 75 and 9600 It also supplies clock signals to the Cassette Data Interface GDI A UART controls data flow through the Serial Data Interface SDI UART and provides for compatibility between the Sol and a data communications system be it RS 232 standard or a 20 ma current loop device In the transmit mode parallel data on the Bidirectional Data Bus is converted into serial form for transmission Received serial data is converted in the receive mode into parallel form for entry into the CPU on the Internal Data Bus SDI UART status is also reported to the CPU on the Internal Data Bus The SDI UART channel is enabled by the port strobe from the Address Page and I O Port Decoder Circuitry within the GDI derives timing signals from clocks supplied by the Baud Rate Generator The Cassette Data UART func tions to 1 convert parallel data on the Bidirectional Data Bus into serial audio signals for recording on cassette tape and 2 convert serial audio signals from a cassette recorder into parallel data for entry into the CPU from the Internal Data Bus Note that Cassette Data UART status is also reported to the CPU on the Internal Data Bus Again a UART performs the necessary parallel to serial and serial to parallel conversions Other GDI circuitry performs the needed digital to audio and audio to digital conversions and provides the signals that allow motor control for two recorders As with the SDI UART the Cassette Data UART is enabled
209. f 20 character rows represents a full display of 260 scan lines for 60 Hz operation 13 scan lines row x 20 rows 260 scan lines per page Horizontal and vertical synchronization signals are generated by two one shot multivibrators consisting of three two input NOR gates in 0102 Horizontal sync is triggered by SCAN ADVANCE and vertical sync by VDISP Both circuits generate fixed length sync pulses with adjustable starting times C52 determines the length of the horizon tal sync pulse and C53 the length of the vertical sync pulse Ihe starting times with respect to triggering are variable with vari able resistors 1 HORIZ and VR2 VERT to provide continuous adjustment of the display position on the screen An exclusive OR gate in 074 combines the two sync pulses into a composite sync COMP_ SYNC signal Note that the use of the exclusive OR inverts the hor izontal sync pulses when the vertical sync pulse appears Since vertical sync information is extracted in a monitor by an integrating or averaging process this technique maintains horizontal synchro nization during the vertical sync period Two types of blanking are available control character blank ing and video blanking The first blanks control characters and causes cursor information to be displayed in their place Video blank ing forces portions of the video display to a white or black level depending on whether normal or reverse video is selected with S1 4 Control
210. fficult To prethread a hole insert specified screw in the hole and position it as straight as possible While holding the screw in this position drive it into the metal with the proper screwdriver If started straight the screw will continue to go straight into the metal so that the head and sheet metal surfaces are in full contact 5 The diameter of the shank threaded portion of a screw increases in relation to its number For example a 6 32 screw is larger in diameter than a 4 40 screw Also a 8 lockwasher is larger than a 4 lockwasher REV B VI 5 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI 6 4 REQUIRED TOOLS EQUIPMENT AND MATERIALS The following tools equipment and materials are recommended for assembling the Sol cabinet chassis Unless indicated otherwise none of the following items are supplied with your kit l Needle nose pliers 2 Diagonal cutters 3 Screwdriver thin 1 4 blade 4 Screwdriver 2 Phillips 5 Controlled heat soldering iron 25 watt 6 Ohmeter 7 Masking tape 8 Transparent tape 9 Rubber mallet or small hammer 6 5 ORIENTATION Sol Backplane Board 501 When the side without the solder mask no green lacquer is facing you the PC board identification 501 and revision level will be located in the upper left hand corner of the board when the edge connector gold contacts is positioned at the bottom of the board In this position the com
211. four connector and plate mounting holes Place 4 lockwasher on each screw except the upper one which is closest Lo the AC receptacle Secure with 4 40 hex nuts Leave upper nut closest to receptacle loose Step 7 Prepare RG59 U coaxial cable Cut a 13 piece of coaxial cable from that supplied with the 501 Kit Strip away one inch of the outer insulation at both ends to expose shield Unbraid shield at one end and twist it into a single lead Do the same thing at the other end Tin shield lead at each end and solder a 4 lug to each lead Then remove 1 2 of the inner conductor insulation at both ends See Figure 2 2 119 PROCESSOR TECHNOLOGY CORPORATION ool POWER SUPPLY DECT LON LI Rev B Figure 2 2 Coaxial cable preparation Step Connect coaxial cable to coaxial connector in stalled in Step 6 Solder inner conductor on one end to the pin of the connec COT Remove hex nut on upper connector mounting Screw closest LO place coaxial shield on screw and reinstall hex nut Step 9 Connect fan closure plate wiring Install the 3 power switch to commoning block cable supplied with your Sol REG kit Connect the female spade lug end to the upper terminal of the on off switch and the commoning block lug end to the 1 terminal of the commoning block closest to the fan NOTE To install commoning block lugs position lug with its open si
212. g below trim to length strip 1 from the loose ends Insert the wire from pad AB into pad AD and the wire from pad AC to AE Solder and inspect for solder bridges Step 3 Fix the long runs of wire to the board using sili cone compound or tape CN 16 1 78 page of 2 g ejeg 1 4 2 gee o ae gt 27 000 o Li 2 5 19 2227 gt 2 N NNN NN Oo 2 EN by ie 28 1 qc amp 2 4 im I MOT amp lt gt r 1 ay 17 C MC dac pears ANEN yi QUE TR 2 7 e rq epicurei y 1 78 CN 16 page 2 of 2 Sol UPDATE 731011 SUBJECT Optical Isolator U39 Circuit Change To enhance reliability of the optical isolator U39 which couples data from a current loop device to the Sol make the following circuit changes Use the procedure given below after you complete Step 49 in Section III Sol PC Assembly and Test Make a note in your manual after Step 49 to remind you of this change in the assembly procedure Refer to the drawings on the next page while performing
213. g clock transition but the output of the last stage is inverted or flipped before being fed back to the input In a simple four stage flip tail ring counter the contents would Progress Leon Were do 000 SILIO 0011 0001 0000 on the first through eighth clocks respectively The hypothetical counter would go through eight states dividing the clock by eight The Sol counter however is a modified flip tail ring coun ter that can be configured to divide by one of three divisors 5 6 or 7 This is made possible by using two input NAND gate 091 in the feedback path and three jumper options no jumper D to C and D to E to alter the feedback path Let s see how it works VITL 9 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILI Sol is normally configured with the D to E jumper installed to meet the clock requirements of the 8080A CPU With this jumper installed the outputs of the third and fourth 090 stages are applied Lo pins 9 and 10 of 991 Assuming 990 is reset to zero pin 8 of 991 is high and on the first clock pulse the counter contents change to TOUS Refer to 2 045 MHz Clocks portion of Figure 8 1 on Page MEA Dem Pin USI ocannmot change until ithe Ttourth state CLITLI at which time it goes to zero the fifth clock pulse the counter changes to 0111 Again pin 8 of 091 cannot change from zero until one of its inputs changes As shown in Figure 8 1
214. g into and reading from memory The other CPU control sig nals SYNC INTE HLDA WR and WAIT are also fed to the S 100 Bus pins as indicated These as well as DBIN or DIGI1 are placed on the bus through tri state drivers which are enabled by C C DSB on 5 100 Bus pun l9 Note that this signal is normally pulled high R20 The data lines of the CPU DO 7 are bidirectional and are used for several functions One of these is to output status at the start of each cycle which is marked by the SYNC output of the CPU Status on DO 7 is latched in U93 and U106 each of which contains four D flip flops when pin 8 of inverter U45 goes high Status in formation as identified on the schematic is then buffered through tri state drivers 194 and ULOT to the S 100 Bus The status latch strobe on pin 8 of U45 is extracted in the middle of the SYNC pulse by gating PSYNC and 102 in gate 044 DSB 0 02100 Bus pin 18 is used to disable the U94 and U107 buffers when a DMA device or another processor assumes control of the S 100 Bus A second function of DO 7 is to output data from the CPU to the Bidirectional Data Bus Data out of the CPU is placed on this bus through tri state drivers U80 and U81 Note that these drivers are normally enabled unless this bus is in the input mode or an ex ternal device has control or the Dus In the latter case IDO DSB on 5 100 Bus pin 23 would be pulled low to make pin 8 of NOR gate U48 h
215. gh on pin 6 of 015 15 inverted 024 to turn on LED2 LED2 is located in the UPPER CASE key A second clo sure of this key toggles U15 to the opposite condition Now assume the LOCAL key is depressed the output on pin 5 of U12 goes active high to clock the other D flip flop 015 stage at pin 11 This stage also operates as a toggle and output pin 9 goes low to become LOCAL on pin 14 of 21 Again the high on output pin 8 VIII 44 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION TION VILI causes LED3 the LOCAL light to turn on A second closure of the LOCAL key toggles this section of U15 to the opposite condition Note that LOCAL has no affect on keyboard data The other outputs from 012 are BREAK pin 12 CONTROL 6 REPEAT porn 9 BREAK is inverted in U23 to become BRK on prm Rb of Jl CONTROL applred directly to that the control character related the Low Order Dits enters Ul and U2 REPEAT is applied to pins 10 and 11 of NAND gate U27 and pin 13 of NAND gate 016 The input to 027 is gated with UPPER CASE to generate RST pin 13 of 21 This means of course that REPEAT and UPPER CASE must be depressed at the same time to generate RST On pin 13 of 016 REPEAT enables that gate so that 016 trans mits the output on pin 9 of U9 U9 is connected as a two stage shift register whose input pin 2 is ground It is clocked by clock 128 Ion 9 U9 15 init
216. graph 5 9 rn Section ILI Page LII 6 apply to assembling che 501 keyboard 2 4 REQUIRED TOOLS EQUIPMENT AND MATERIALS The following tools equipment and materials are recom mended for assembling the personality module Needle nose pliers Diagonal cutters 35 Screwdriver thin blade 4 Controlled heat soldering iron 25 watt Du 60 40 rosin core solder supplied 3 22 ORIENTATION Light emitting diode location LED3 will be located in the lower left hand corner of the board when locations JI and U4 through 016 are at the top of the board In thin position the component front side of the board is facing up and all horizontal reading legends will read from left to right Subseqeent position refer ences related to the keyboard circuit board assume this orientation PROCESSOR TECHNOLOGY CORPORATION Sol KEYBOARD DEC LEON V Table 5 Sol Keyboard Parts List INTEGRATED CIRCUITS Oo US 21 SAO U20 4051A 019 amp 22 UO dq O14 T5 7141504 U23 7406 024 US TRANSISTORS 6 2N3640 3 221444748 1 Tu ohm watt 155 ohm watt 390 ohm watt ohm watt ohm watt ohm watt ohm watt ohm watt ohm watt GAM S watty ohm resistor ohm resistor Hev A 1 022445 CAPACITORS DIODES ZENER D1 network network 7141530 U29 1442 AULT amp 21 PASI TUI
217. gulator board 29 REQUIRED TOOLS EQUIPMENT AND MATERIALS The following tools equipment and materials are recommended for assembling the Sol regulator board Needle nose pliers Diagonal cutters Sharp knife Screwdriver thin 1 4 blade Screwdriver 2 Phillips Controlled heat soldering iron 25 watt 60 40 rosin core solder supplied Volt ohm meter Ruler CO 1 OTF GO pn IS 226 ORIENTATION Sol REG Board Location C5 2500 ufd capacitor will be located in the lower right hand corner of the circuit board when locations SCRI 1 FWBl are positioned along the top of the board this position the component front side of the board is facing up and the horizontal legends will read from left to right the other legends will read from bottom to top Subsequent position references related to the Sol REG board assume this orientation 21042 Fan Closure Plate The large circular cutout will be located in the upper right quadrant of the plate when the heavy guage doubler plate is facing UP In this position the rectangular cutouts are on the left the front side the plate 15 facing down the side Pacing Up and the small circular cutout 15 at the bottom We suggest you label the two sides 2 AooEMBLY TEST NOTE Instructions chat apply only to the 901 20 are preceded by an asterisk Skip these instructions if you are assembling a Sol lo Rev
218. hanges 13 III 25 Step 28 Add note before Step 29 Do Step 73 p III 39 now 14 III 27 Step 35 Add note to install 093 7415175 and 0106 7415175 15 111 30 Step 41 Delete installation of 093 7415175 and 0106 7415175 16 III 39 Step 71 Add note Mike input not recommended 17 III 28 Step 38 In the third sub step add as in Figure 3 9 In item 10 above you made a note referring you to this Change Notice Instead of the adjustment procedure given in Step 70 on page III 38 use the following procedure Ground the Audio In jack J7 on Sol PC Apply power to Sol PC Using a high impedance probe from an oscilloscope with a cali brated time base a frequency counter is preferred if available monitor the VCO frequency appearing at pin 4 of 0110 type 4046 Adjust VR3 for a measured frequency of 14 0 kHz This is a period 7 1 usec Due to variations in the availability of ICs fromvarious suppliers number of substitutions may be made of equivalent IC types Please make the following changes in the manual on the pages given to reflect these possible substitutions Item Page Nos ICs Main Type Additional Substitutes III 2 III 35 U95 6 74173 8T10 III 2 III 13 U104 AMOO26 0026 0026 xx 0026 III 2 III 28 III 38 051 U69 TMS6011NC 51883 AV 5 1013 TR1602B V 2 V 7 Ul U2 74LS175 25LS175 V 2 V 7 U18 8574 many possible equivalents Rev A CN 11 page 2 9 77 Ref ECN No 10
219. harge Qutput Thrashold Resat Contro Voitaje 8T97 or 74367 Output 3 GND Responsa Control 3 Qutput 2 Response Control 2 Input 2 Output 1 Rasponsa Control 1 Input 1 PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER APPENDIX V 21L02 or 91102 PIN NAMES Ao Ag ADDRESS INPUTS Og DATA OUTPUTS cS CHIP SELECT INPUTS 2 PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER APPENDIX V INPUT RESET PULSES BUFFERED OUTPUTS L EOF K C OD M G H ENABLE A RESET A ENABLE RESET B AV 3 PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER APPENDIX V POWER SAVER SELECT N PROGRAM 6574 or 6575 64 X 64 PROM ARRAY Mol SENSE AMPLIFIERS CONTROL 3STATE LOGIC INPUT OUTPUT BUFFERS H CSp RW OR CS AV 4 PROCESSOR TECHNOLOGY CORPORATION APPENDIX V TM Sol TERMINAL COMPUTER OUTPUTS J Tl 2 OUTPUTS AV 5 PROCESSOR TECHNOLOGY CORPORATION APPENDIX V TM Sol TERMINAL COMPUTER AV 6 PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER APPENDIX V SELECT OUTPUTS DATA INPUT vce 2 2G 2 3 272 2 1 2 0 vo H E ES us Es TPUT LECT 1Y3 1Y2 1Y1 10 SELECT ENABLE 1G INPUT OUTPUTS 74163 or 93L16 QUTPUTS CARRY OUTP
220. he sheet metal Carefully align holes in PC board 18 in all with threaded mounting holes on bottom of keyboard assembly Insert Torx screws from solder back side of board and using a thin blade screwdriver drive into keyboard assembly mounbing holes Drive screws evenly and tighten just enough to hold keyboard assembly in place CAUTION DO NOT OQVERTIIGHIEN THESE SCREWS Step 14 Reconnect Z20 oconductor ribbon Cable to Jl board Step 15 Test keyboard for proper operation Apply power to monitor Sol PC Strike MOdE SELECT key Strike UPPER CASE key Indicator light should come strike UPPER CASE key again Indicator Light should go OTI Strike LOCAL key Indicator light should come on Strike LOCAL key again Indicator Light shoulda go Veg PROCESSOR TECHNOLOGY CORPORATION Sol KEYBOARD SECIION M Step 15 continued Strike SHIFT LOCK key Indicator light should come on Strike either SHIFT key Indicator light should go off Verity operation of all alphanumeric keys you strike each key you should observe the corresponding character on the monitor Should the keyboard fail any of the preceding checks locate and correct the problem before proceeding If the keyboard passes all of the preceding tests congratulations on a job well done At this point you have successfully assembled the Sol keyboard and tested it for proper op
221. hole insert specified screw in the hole and position it as straight as possible While holding the screw in this position drive it into the metal with the proper screwdriver If started straight the screw will continue to go straight into the metal so that the head and sheet metal surfaces are in full contact on The diameter of the shank threaded portion of a screw increases in relation to its number For example a 6 32 screw 15 larger in diameter than a 4 40 screw Also a 8 lockwasher is larger than a 4 lockwasher Os Heat sink compound is supplied with this kit in a small clear plastic package It is a thick white substance which improves transfer between components and their heat sinks To use the compound pierce a small hole near the edge of the top surface of the plastic package using a pin or sharp knife point Squeezing the package will cause a small amount of the compound to ooze out Rev B Ies PROCESSOR TECHNOLOGY CORPORATION ool POWER SUPPLY SECTION II out of the hole which may then be applied with a toothpick or small screwdriver blade spread a thin film of the compound on the mating surfaces of both the heat generating component and the heat Sink surface which it will contact Then assemble as directed 2 4 ASSEMBLY PRECAUTIONS The precautions concerning soldering and the installation and removal of integrated circuits given in Paragraph 3 3 of Section III Page 111 6 also apply to assembling the Sol re
222. hortly before the 1200 Hz signal did The reset on pin 4 of U101 is thus removed slightly after the OUTPUT CLOCK occurred With the J and K inputs to the first 0101 stage high its output will change state on each succeed ing low to high transition of OUTPUT CLOCK Ihe second U101 stage in turn can only toggle on the positive going transition of OUTPUT CLOCK when its J and K inputs are high Since the inputs are high at one half the clock rate by virtue of the first U101 stage the second U101 stage toggles at one fourth the OUTPUT CLOCK rate The two sections of U101 therefore operate as a frequency divider dividing the OUTPUT CLOCK by two when the write data is a 1 and by four when the data is a 0 Thus in the low speed mode four cycles of the 1200 Hz represent a O and eight cycles of 2400 Hz represent a I In the high speed mode one cycle of 1200 Hz rep resents a I and one half cycle of 600 represents a O The output on pin 14 of U101 is applied to one section in U109 which provides sufficient current drive for the divider network Ihis divider and a jumper arrangement allow selecting one of three outputs to be fed to the audio output jack J6 The I to J jumper se lects a 500 mv signal for the auxiliary input to an audio recorder the I to H jumper selects a 50 mv signal for the microphone input to an audio recorder When the CDI is in the read mode data from the recorders enters on J7 This input is fed to the negat
223. hreaded holes in brackets VI 17 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Step 39 See Drawing X 10 Remove protective cover from one side of Plexiglass strip and attach Sol Terminal Computer trim plate to Plexiglass with small pieces of transparent tape Place trim plate with printed side against Plexiglass Step 40 See Drawing X 10 Remove protective cover from other side of Plexiglass and slide it into the channel above the keyboard cutout NOTE A hole is provided in the sheet metal be hind the trim plate This may be used for a power on indicator light if desired Step 41 Refer to Drawing X 10 Install keyboard cover Hook front of cover under front edge of main chassis and lower it over the keyboard A slight adjustment of the keyboard po sition may be needed to obtain a proper fit Position keyboard within cutout in cover if needed and tighten keyboard mounting screws Step 42 Install top cover Be sure power cord is not plugged into 110 V ac outlet and disconnect cord from fan closure plate receptacle Remove fuse holder cap and fuse CAUTION NEVER REMOVE OR INSTALL FUSE WITH POWER ON See Drawing X 10 Hook top cover over back edge of key board cover and lower it down into place over the rear of the main chassis Install the two thumb screws one at the lower left corner and the other to the right of the fan closure plate coaxial connector to attach
224. ially set with output pins 5 and 9 high during the third count cycle by PKD minus 1 This is also the time when U12 outputs data If the key is released U9 clears to a low on pin 9 five count cycles following KEY If the key is held down U9 cannot shift since PKD minus I remains on preset input pins 4 and 10 When REPEAT exists dt prn oot Ulo prn di or Ulo as low to inhibit U25 and U27 at pin 13 This prevents further KEY signals and disables the n key rollover circuitry The low on pin 11 of 016 15 also inverted by open collector inverter U24 to enable the repeat oscillator timer U3 R4 R5 and C3 U3 generates a square wave on pin 3 with a period determined by the RC network This clocks the first stage of D flip flop 011 the STROBE generator 011 produces the previously discussed 6 usec STROBE 011 continues to generate STROBE at the repeat oscillator rate until either the REPEAT or character key is released And with each STROBE of course the data associated with the character key is latched into UL and 92 Eight ASCII coded data bits are output by Ul and U2 to 21 indicated Seven bits 0 6 are used for ASCII characters and the eighth bit 7 15 set only for certain control characters that are recognized by the Sol program These are used for control functions such as MODE SELECT and cursor movement Ihe remaining circuit R32 and C14 initializes the keyboard when power is applied That is it resets the
225. ich specifies scan line RO in the Chara ter Generator ROM As shown in Figures 8 5 and 8 6 the ROM in turn outputs 7 word 100121110 Do through DO respectively B7 through Bl on the schematic Var BROCBOOOER TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECTION VELI 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 130 1110 EH Ed em UR 2 ipo Stewie gt m E EL go CA 2 D Qu De MI 20 Us 08 9 26 DA 20 f Dn 5 2 o 5 Za E saasaa ie 2 m 1 os wu 1 Ts 1 M ET i 2 1 2 27 SEC 2 Pant e a 4 2 p 2 2 2 RS ut LA F gh oe us gan ie ee 25 LESE Do um Ea 22 TUA n n abe sre NER 22222 2 PE Sp W 1224 VS DI S gt
226. ide of board place lockwasher on each screw start nuts and tight en Then solder connector pins to board 111554 PROCESSOR TECHNOLOGY CORPORATION IM 501 SINGLE BOARD TERMINAL COMPUTER SC ELON Ir Rev A Step 5 6 Using two 4 40 x 7 16 binder head screwsl hex nuts and lockwashers install 25 1 male connector in location J2 parallel I O interface Install J2 in the same manner as Your did sl 97 Install Augat pins in mounting Holes L and Refer to Installing Augat Pins in Appendix IV These holes are located between 185 and 086 No juniper will be installed Step 58 Install the following IC s in the indicated loca tions Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board indicate the location of pin 1 of each IC IC NO C U37 1415367 1489A U39 AN2 6 U52 TAGI 00 9 2273025 741500 056 Or gt 2 2927 7406 058 OTIA U72 14 9 0 3 TALS LUJ 084 40299 Uses 4046 4024 095 74173 141 73 U97 JA D 5 MOS device Refer to CAUTION on Page III 8 Solder this IC in its location See Loading DIP Devices in Appendix IV obep 59 Check input output A170 NOTE The parallel I O interface should be tested with the device you will be using Refer to 1 0 Intertacing rn iectoeon Wil Step 59 continue
227. igh the input mode pin 8 of 048 is high because OUT DSB is low Ihis signal is generated by decoding PAGE CC MEM SEL PORT IN FC PORT IN FD INT SEL to produce MPX ADR A and MPX ADR B on pins 3 and 11 respectively of two NOR gates in 048 ADR and MPX ADR are decoded with DBIN on pin 5 of NAND gate 047 The DO 7 bus lines are also used to input data to the CPU Data input to the CPU is multiplexed from four data buses with four 4 1 line multiplexers 065 66 70 and 79 These four buses are the 1 Keyboard Data Bus KDBO 7 2 Parallel Input Data Bus PIDO 7 3 Internal Data Bus 7 and 4 Bidirectional Data Bus These data multiplexers tri state devices with their outputs pulled up by R107 through R114 to a level that satisfies the input requirements of the CPU Their outputs are active only when both their El and E2 pins 1 and 15 are low can be seen this occurs only when DBIN on pin 3 of NOR gate U46 is low that is when the DBIN output of the CPU is active to indicate its data bus 15 in the input mode NAT Me 5 PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION TION VILI Input selection to the multiplexers is done with the A and B inputs to 065 66 78 and 79 These two inputs are driven by MPX_ ADR_A on pin 3 of NOR gate U48 and MPX_ADR_B on pin II of NOR gate U48 There are four possible states for the combination of MPX_ADR_A and _B and th
228. il it stabilizes at 5 volts Should the output voltage rise above 5 volts the circuit operates in a reverse manner to lower the voltage Protection against a serious over voltage condition more than 6 volts is provided by SCRI Dl R2 R13 R14 and C8 Zener diode Dl with a 5 1 zener voltage is connected in series with R13 and R2 When the output voltage exceeds about 6 volts the re sulting voltage drop across R2 triggers SCR1 to short the foldback current to ground Since the overload current circuit is also work ing the current through SCRI is about 1 amp Once the current is removed Circuit to Its normal condition that nS SCRL ODE R13 R14 and C8 serve to slightly desensitize the circuit so that it will not respond to small transient voltage Spikes Bridge rectifier FWB2 connected across the other Tl second ary Supplies 12 and 12 V de The positive output of FWB2 15 111 tered by C5 and regulated by IC regulator Ul The negative output is filtered by C4 and regulated by U3 Shunt diodes D3 and D4 pro tect Ul and U3 against discharge of C6 and C7 when power is turned Note that should the 12 volt supply short to ground the t5 volt supply turns OL by the action or Uz PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILI Unregulated 16 and 16 V dc at 1 amp from the filtered outputs of FWB2 are made available on terminals X6 and X5
229. ile SAVE name unit addrl addr2 addr3 This command transfers program or data onto a tape cassette file name name starting at addrl and ending at addr2 The name of the file becomes part of the tape s header information SET TYPE and SET XEQ commands affect the header information on the tape file The optional addr3 specifies the address if different than addrl to be entered in the tape header Example SAVE CHASE 2 0 Result Saves onto tape unit 2 a program named CHASE starting at location 0000 and ending at location Catalog or files CAT mna This command will start the tape unit specified and list each tape file header information Examples 72 Result SLOPE 10500 9200 HUM 0500 0B00 III TAPE COMMANDS cont Note very useful feature of the CAT command is to apply power to the tape units when needed to rewind tape Depressing the MODE or Control key will remove power from tape unit and return to COMMAND mode TV SET COMMANDS SOLOS has Sag SET SET SET SET SET SET DOEL SET 10 set commands N data XEQ addr TAPE 0 or 1 VEE data COUL addr CIN addr CRG Set Commands In Detail Set Speed of Display TROY ocreen Character rare Lnput port To SOLUS Output oru Lo GOLOS Number of NULLS following CRLF Auto execute addr 021200 baud 1 300 baud Type byte header Custom output addr CUSTO
230. inder or pan head screw 4 lockwasher and 4 40 hex nut Figure 6 6 Backplane board Sol BPB installation Rev A VI 15 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Figure 6 7 Backplane board Sol BPB installation Rear of Sol is at bottom and Sol BPB is to right of power supply subchassis in line with C8 and transformer Step 32 continued REV B See Detail E on Drawing X 8 Attach Sol BPB to brackets with three 4 40 x 5 16 binder or pan head screws 4 lockwashers and 4 40 hex nuts on each side Insert screws from the back side of bracket through Sol BPB place lockwasher on each Screw and secure each with nut Step 33 Install left and right gusset brackets as shown in Figure 6 6 on Page 1 15 Fit narrower gusset bracket on left side so that its flanges are flat against the expansion chassis side wall and the backplane board You may have to bend the flange slightly to obtain a proper fit Attach bracket to expansion chassis side wall with the three 6 x sheet metal screws you used in Step 19 to prethread the holes See WARNING on Page VI 17 Step 33 continued on Page VI 17 VI 16 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI REV C Step 33 continued WARNING IT IS QUITE EASY TO SCRATCH OR CUT YOUR HAND ON THE SOLDER SIDE OF THE BACKPLANE BOARD WHEN DRIVING THESE SCREWS PLACE A SUITABLE PROTECTIVE BARRIER SUCH A
231. ing find and correct the cause before you pro ceed with assembly Turn off power supply and disconnect power connector Step 26 Check synchronization circuits Set all S1 switches to OFF Connect Sol PC video output cable to video monitor SEE CAUTION ON PAGE III 22 BEFORE CONNECTING MONITOR Step 26 continued on Page 111 22 III 20 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION LLI CHECK POINT WAVEFORM 4 V 1292 aZ 250 XS Gnd GDO Pim 64 059 Ping 800 us Gy WASP iio 3 aan LE c 4 us 62 us 0 6 ms U88 Pin 4 mS 23 2 Display section timing waveforms Rev URL UE PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL COMPUTER ELON ILI CAUTION DO CONNECT THE GOLAP VIDEO OULPUT TO A MONITOR OR TV RECEIVER THAT IS NOT EQUIPPED WITH AN ISOLATION TRANSFORMER SEE PAGE AVI 7 IN APPENDIX VI Set VRZ2 VERT HORIZ the Sol PC to their mid range settings Turn monitor on and apply power to the o Goes Cy The display raster will be pulled Using the monitor Vertical Hold you should be able to obtain a slow roll black horizontal bar moves slowly down the screen and a stationary raster Using the monitor Horizontal Hold you should be able to adjust for an out of sync
232. ioned SOLOS uses the name to find the correct data for the file operations Assume you were about to read data from a file named POTTS for example and you had correctly opened the file with a header pointing to that name SOLOS when you first requested a data transfer would read past File 1 and File 2 as shown below and then read data from the POTTS file Beginning position of tape Beginning of file to be read Positron __ 4 Block Access The Block Access method invokes no management by the system Each call to the Read Write routines performs a complete cassette operation Read and Write routines are used by SOLOS for GET and SAVE commands and serve as examples of the calling conventions for RDBLK and WRBLK routines Read Tape Block Routine RDBLK The entry point for RBDBLEK 2013 On entry Register A contains Unit and Speed data with bit 5 speed O for 1200 baud or 1 for 350 baud bit 7 1 Tape 17 bit for Tape 2 and gll other bats 0 SUBROUTINES cont Registers H amp L contain the address of file header iO Registers D amp E contain the address of where the file 1s to be loaded into memory lf TO Oy THiS formation is taken from file header information on tape On exit Normal return Carry Flag is cleared and data has been transferred into memory Error XCULDENHS On errors or user pressing MODE or Control from keyboard the Carry Flag is s
233. ipple 5V FWBl U2 reference voltages gt 12V Ul D3 C5 2 D gt Ripple on 12V C5 FWB2 E gt No 12V 03 D4 C4 FWB2 283 1 2 3 4 6 F gt G gt No A gt B gt C gt D gt E Ripple on 12V C4 FWB2 or 16 Unregulated FWB2 COMMON SYMPTOMS OF FAILURE IN THE I O SECTION data output from TTY section Bad UART 051 Bad strobe to UART U22 23 35 Bad TTY driver logic U55 56 Ql D2 12V missing at 012 or 12V missing at U56 reference voltages Incorrect data out from TTY section A gt gt A gt B gt C gt Two Baud Rate Switches selected at once S3 Bad UART 051 Wrong word length selected S4 data input to TTY section Bad receive logic U38 39 Dl 3 4 5 6 Bad UART 051 Bad strobe to UART U22 23 36 Incorrect data input to TTY section A gt B gt gt No A gt B gt C gt D gt Two Baud Rate Switches selected at once S3 Bad UART 051 Wrong word length selected 54 data output from RS 232 section Bad UART 051 Bad strobe to UART U22 23 35 Bad RS 232 driver logic 055 56 Handshaking signal missing External Incorrect data output from RS 232 section A gt See same symptom for TTY 8 9 19 11 1 A gt B gt lt 2 input data to RS 232 section Bad RS 232 dr
234. ircuitry 1 2 3 4 Serial interface RS 232 C b 29 ma current loop Parallel interface Sense switch operation Handshaking logic and generation b Parallel 1 3 4 6 7 8 9 18 11 12 13 14 15 SET UP PROCEDURES FOR Sol SYSTEM 3 AND 4 Remove covers from Sol Remove all PC boards from Sol backplane Visually inspect interior of Sol checking for loose ICs shipping material broken cables or wires and shipping damage Make sure keyboard cable is connected to the correct connector on the Sol P C J3 Connect video cable to monitor Install AC power cord Configure switches S1 S4 as per the Sol manual to your Specifications Turn Sol power switch on Screen should display a prompt gt and a cursor 2 in the upper left hand corner of the screen NOTE IF Sol DOES NOT PASS STEP 9 DO NOT PROCEED ANY FURTHER UNTIL PROBLEM HAS BEEN CORRECTED Load and run Solt Power down the Sol and install the memory boards Load and run the MEMORY test Power down the Sol and install the format and disk controller boards Install all cables and complete the CONFIGURATION check Run the DOST test NOTE If Helios does not pass Step 15 do not proceed any further until problem has been corrected dl e3 roeilctow BOOTLOEB p rocedure4 SYSTEM 3or4 SYSTEM START BOOT CHECKOUT MEMORY TEST 1 PASS nd
235. is example you will use the BASIC 5 cassette supplied with your Sol Step 19 Set POLARITY S1 4 and BLANK S1 3 Switches as desired Step 20 Replace top and keyboard covers Step 21 Load BASIC 5 cassette in recorder If required fully rewind tape This can be done by disconnecting the REMOTE plug from the recorder and using the REWIND control on the recorder After rewinding reconnect REMOTE plug Step 22 Set the followinDg recorder controls and indicator rt So equipped as indicated Lrsneporb press Volume midrange Tone top of range maximum treble Tape Counter 0 Step 23 Press PLAY control on recorder The tape should not loves Xt does there rs a malfunction rn the remote control Or With the Sol off there should be continuity between the REMOTE plug contacts NO TaS ape Dead Must De Clean TO reliably read a tape or write on tape Step 24 If needed press MODE SELECT key on Sol to enter command mode Remember SOLOS initializes in the command mode while CONSOL initializes in the terminal mode whenever Sol is turned on You should see a prompt character followed by the cursor gt W the left of the screen dee PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES SEC LLON Wit Step 25 Type the XEQ command as follows ABO BASIC Step 26 Press the RETURN key on Sol The cursor should disappea
236. istening with the earphone Lr you hear yoursecr through the earphone your recorder does provide a monitor output in the record mode Write Operations Other than placing the recorder s in the record mode loading the cassette s and making sure that the head s 1S on tape not leader no manual operations are needed to write on tape In the case of two recorders however Unit 1 and 2 must be Specified in the SAVE command in order to select the desired recorder A default selects Unit 1 Refer to your SOLOS Users Manual for instructions on how to use tape commands Read Operations In order to read a specific file on tape you must start the tape at least two seconds ahead of that file This delay allows the Sol audio cassette interface circuitry and the recorder playback electronics to stabilize after power is turned on Since all file searches are in the forward direction the simplest approach is to fully rewind the cassette s before a read operation unless you know that the file of interest is advanced at least two seconds See Paragraph 7 4 3 Step 21 for instructions on how to rewind the tape For a read operation proceed as follows ds Load cassette s as just described 4 If only recorder is used set its volume control at midrange With two recorders set both volume Controls at Cherry high end MLDI A PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES 501 RECORDER CONNEC
237. it board to upper most pads in top right corner Insert wires from solder back side of board green Wed PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI solder mask side and solder on component front side of board If awire is too large for the mounting hole snip off as many individual strands as needed to obtain a fit Connect cable leads as follows CABLE LEAD PAD White Ground fifth hole from right White Ground fourth hole from right Blue 8 V dc third hole from right Red White 16 V de second hole from right Yellow White 16 V first hole from right NOTE Pad orientations given above are as viewed from component front Side of circuit board the side without the green solder mask Step 5 Fill feedthrough holes on right hand side of board REV C with solder Fill only those that are exposed not covered with green lacquer on the solder mask back side Fill these holes from the solder mask side so that no solder protrudes above the back of the board Step 6 Check 8 volt 16 volt and 16 volt buses to in sure they are not shorted to each other or to ground Using an ohmmeter make the following measurements on one of the edge connectors 8 volt Bus Test Measure between pins 1 or 51 and 50 or 100 There should be no continuity meter reads close to infinity ohms 16 volt Bus Test Measure between pins 2 and 50 or 100 There should be no
238. ive input pin 6 of operational amplifier 0108 Ihe first section of U108 is a high gain amplifier with its gain approximately 100 being determined by R142 and R143 The out put from this amplitier 58 coupled to input 2 the following U108 stage and the base of a Darlington pair Q4 and Q5 which pro vides high current gain Current into the base of transistor Q5 causes C67 to dis charge C67 charges through R39 to 5 V dc The voltage on C67 in turn controls the gate of field effect transistor FET Q3 03 func tions as a variable resistor which can be changed by its gate voltage Since Q3 is connected between ground and the input network to the VITI 36 PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION BCT LON VIII first 0108 stage it serves a variable shunt A low gate voltage on Q3 decreases the shunt resistance and the input to U108 Ina like manner a high voltage on C67 results in an increased input to DIU 03 04 and Q5 with their associated circuitry therefore serve as an automatic gain control AGC circuit which limits the in put to the second U108 stage to approximately a positive 2 volt peak signal The second stage of U108 is a comparator with hysteresis that performs the needed audio to digital conversion Feedback resistor R147 in conjunction with R145 establishes the level on the positive input pin 3 of U108 This level be it positive or negative 15 the threshold voltage
239. iver logic U37 38 Bad UART U51 Bad strobe to UART U22 23 36 Incorrect data input to RS 232 section A gt No A gt B gt No A gt B gt see data Bad Bad data Bad Bad same symptom for TTY output from parallel section output latches U95 96 Strobe to latches U35 54 input to parallel section input multiplexers U65 66 78 79 input MUX logic U36 47 48 Bad sense switch operation A gt gt No B C D data drivers 057 58 strobe logic U36 COMMON SYMPTOMS OF FAILURE IN THE Sol KEYBOARD output No 5V Bad Bad Bad Bad Bad 1 output logic Ul 2 28 19 decode logic 020 14 15 25 26 27 key detect circuitry 017 29 21 22 NOTE CHECK FOR SHORTS ON MATRIX clock generation U7 8 KIC circuit No amplification Q2 4 7 No PKD signal Q3 4 010 16 20 26 27 4 Character continually repeated A Strobe line held low 010 11 B Repeat oscillator malfunctioning U3 C3 R4 5 Addressable latch output low 012 Shift shift lock upper case local control break tab keys not functional A Bad addressable latch 012 LED s won t light A Bad LED s Bad driver 024 NOTE All mods involving grounding should be 20 gauge solid insulated wire All mods involving signal paths should be no greater than 26 gauge and no less that
240. l PC 1 Needle nose pliers 2 Diagonal cutters 2 Screwdriver 4 Sharp knife 5 Controlled heat soldering iron 25 watt 6 60 40 rosin core solder supplied 7 Small amount of 24 solid wire 8 Volt ohm meter 9 Video monitor or monochrome TV converted for video input 10 IC test clip optional 11 Oscilloscope optional 3 5 ORIENTATION 501 Location J5 personality plug in module connector will located in the upper right hand area of the circuit board when loca tion J10 power connector is positioned at the bottom of the board In this position the component front side Of the board is facing up and all IC legends U1 through U10 U22 through U24 etc will read from left to right Subsequent position references related to the Sol PCB assume this orientation 3 6 Sol PC ASSEMBLY TEST PROCEDURE The Sol PC is assembled and tested in sections and or cir cuits You will first test the Sol PCB circuit board for shorts solder bridges between the power buses and ground After assembling III 7 PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL COMPUTERT DES ELON TLI the personality module see Section IV the clock and display control circuits are assembled The bus CPU decoder and memory circuits are then assembled followed by the parallel and serial input output 1 0 and audio cassette sections CAUTION THE Sol PC USES MANY MOS INTEGRATED CIRCUITO THEY CAN
241. l be reflected in Revision Level C and above boards to correct the problem Revision Level B boards however require the following modification to correct the problem Parts for this modification are supplied with your kit 1 R2 330 ohms 1 4 watt color code orange orange brown 2 R14 100 ohms 1 4 watt color code brown black brown 3 Dl 1N5231B 4 C8 0 047 uF disc ceramic Assemble these parts as follows 1 Form one lead of R2 R14 and the cathode banded lead of Dl for upright P C insertion as shown 2 Solder C8 in parallel with R2 shown WRAP Q SOLDER CUT S 3 Install and solder R2 C8 R14 and Dl as shown below Install the formed leads into the board with the unformed leads vertical Position R2 C8 so that the body of C8 is parallel to the board edge and oriented away from Cl CN6 2 page 1 Rev B PROCESSOR TECHNOLOGY CORPORATION 6200 HOLLIS STREET EMERYVILLE CA 94608 415 652 8080 SCRI Nome b HERE CI in iv 52218 21 be N SILKSCREEN LEGEND ERE gt Mu 4 H R2 c8 OBLIQUE VIO HERE TOP 4 Bend the top lead of R2 C8 over towards R14 and bend it around the top lead of R14 one eigth inch from the body of R14 Solder and trim the excess lead of R2 C8 only REND t Y i Rz WRAP AND TRIM C8 RIA 50 LE 5 Install R13 between the top leads of and R14 Wrap R13 s leads around R14 and 01 leads Solder all connections at both points and tri
242. lanking signals must be layed an equal amount U42 connected as a two stage shift register functions to shift the blanking into synchronization with the video Since U42 is clocked by LOAD_CLOCK which has a period equal to one character time COMP_BLANK is delayed two character times from the input on pin 4 of 042 COMP_BLANK is active low during nondisplaya ble portions of the video scan to override any video input data on pins I and 2 of NOR gate U59 The display is thus blanked The Display RAM consists of eight 1K x 1 bit RAM random ac cess memory chips U14 through U28 All chips are held permanently enabled by connecting their CE pin 13 inputs to ground Memory ad dressing is provided through two to one multiplexers U30 U32 and U12 which select one of two display address sources 1 an external address on Address Bus bits ADRO 9 and 2 an internal address sup plied by the Subgroup Counter U31 Group Counter U33 and the Beginning Address Counter U1 The function of the address bits associated with each address source is as follows 1 External address bits ADRO 5 specify the character position one of 64 in the character row 2 External address bits ADR6 9 specify the character row position one of 16 on the display screen 3 Internal address bits a total of six outputs from U31 and U33 specify the character position one of 64 in the character row 4 Internal address bits the four outputs from UI
243. le In this example these two characters are to be displayed in the first and second character positions respectively on the third character row of the display screen Remember that the character position and row param eters are contained in the Display RAM since the 7 bit ASCII coded MELI ZS PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECTION VIII oi H 9 s E n OONSNEO 3 z 2 ORG lt B Sw oz 5868 i ese D ana 5 6 lCOOC s 220771 a 22107117 12 EN rud sa E a eusenenr OUBES i ll ssamm s auwusut asanova 2 14 B BN M EE ERT EX wooscce i uan N D A N mOOCO CN 4 NIOCO CE ecdaccae pan j gt 2l 47 2 UIWIMN 25 a O0 acot T oun olala Talola 2114 ziii 5508 5 MADE Ca CICE 1207 22 BO 55 C ES LIII gcc a DOOONERU
244. lect this speed 0 being high speed and 1 being low 1200 and 300 bits per second respectively If no parameter is given CONSOL will default to high speed operation as all standard Processor Technology Sol System Software is recorded at this speed glad EXecute addr The execute command is used to run programs located in ex ternal memory CONSOL branches to the external routine in a manner similar to an 8080 CALL instruction so the program can return to the command mode using a standard 8080 RET instruction if normal stack Operations are used Org BASIC The BAsic command is provided for executing programs whose Starring address 18 0 such ss Sol BASLICS STANDARD I O ROUTINES All Sol System personality modules contain similar I O code for input oubput Operations JCONSOL using LK of memory has rou tines for KEYBOARD and SERIAL PORT input as well as Serial Commu nications Channel and VIDEO DISPLAY OUTPUT Although the same code for SOLOS and SOLED contains expanded functions the I O operations appear almost identical when used with external software SOl BASIC5b for example performs all l O using the jump table of the personality modules Thus without altering BASIC the user may output to either the serial port or to the display screen Provision is also made within BASIC to programatically change to any of the four available Input or Output options CONSOL is of course limited to the two provided IX
245. lel and cassette accessible to external programs from one entry point a standard feature in all future Sol system software products that will require less memory than would normally be used for I O routines SOFTWARE INTERFACE permits user defined routines for custom applications INDUSTRY STANDARD SETTING CASSETTE I 0 CONTROL includes methods for loading and saving programs and commands that execute programs after automatic loading EXCLUSIVE CASSETTE I 0 ROUTINES allow cassette files to be accessed on a byte by byte basis as though each file were a byte by byte device Thus data transfer to and from cassettes appears as normal I O and two cassettes can be used simultaneously to assemble and edit programs NEW DISPLAY CONTROL features found only in expensive video rerminglssmpeludxncg ESCAPE Sequences for Cursor and Character Speed control 19 COMMANDS to access the basic requirements of the 501 20 control cassette tape recorders and set up special conditions SOLOS See the Quick Command Reference List Definition of Terms addr means word address hexadecimal characters 0 FFFF range data means hexadecimal characters 0 FF range file means a collection of data name means any one to five character identification for a file port means a SOLOS pseudoport from 0 to 3 unit means a number of 1 or 2 corresponding to the appropriate tape recorder means optional
246. lel input bit PH pin 14 is tied to ground This effectively adds a low bit or dot following the data and provides one of the spacer dots between characters The second spacer dot is generated by connecting the serial input pin 1 to ground and applying LOAD CLOCK to the load LD pin 15 input to 041 When LOAD CLOCK goes low which it does every ninth DOT CLOCK U41 shifts in one zero A blank oscillator two inverter sections im USS one section in U42 and their associated components comprise the cursor circuit The blink oscillator runs continuously at a rate set by R84 and C36 Its output has a nominal 0 5 sec period If the blink option is selected with S1 5 the blink signal is applied to one input of a gate in U60 The other input to this gate is provided by the blink latch one section in 041 the cursor bit QA out of Data Latch U26 is high D flip flop U42 sets for the time the ROM is active on the character and remains set during the period when video data is shifted out of 041 The output of 042 is gated high through NAND gate U60 when BLINK pin 6 of U88 is low BLINK is held low when the blink option is not selected The output of U60 is in turn gated with the video output of 041 in 074 an exclusive OR gate U 7 4 thus inverts the video if the output of U60 is high and no inversion takes place if the output of U60 is low Ihe video signal inel udring the cursor is gated to prin 9 or another U74 exclusi
247. lled oscillator that produces a dot clock frequency of 14 31818 MHz This frequency four times that of the NTSC color burst provides compatibility with color graphics devices The dot clock is applied directly to the Video Display Generator circuit and divided in the Clock Generator to provide 01 02 and CLOCK CLOCK synchronizes all control inp ts to rhe 9090 1 2 are the nonoverlapping two phase clocks required by the 8080 Memory internal to the Sol is divided between 2K of ROM Read Only Memory 1K of System RAM Random Access Read Write Memory and 1K of Display RAM The ROM permanently stores the instructions that direct the CPU s activities To enhance Sol s versatility this particular memory is on a plug in personality module Thus Sol can be easily optimized for a particular application by plugging in a personality module that contains a software control program designed for the task The CONSOL and SOLOS programs which are described in Section IX are examples of such personality modules Display RAM stores data for display on a video monitor and the System RAM pro vides temporary storage for programs and data All memories are ad dressed on the Address Bus ADRO 15 and except for the Display RAM input data to the CPU on the Internal Data Bus INTO 7 Data entry into both RAM s is done on the Bidirectional Data Bus DIOO 7 Nd PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VI
248. low R149 100 Drowrn blqgok brown EU 470 yellow violet brown RISE OK green blue red ELO OO brown green yellow EROS 100 brown black yellow R154 100 RLS 6 0 watt blue grey gold R156 12 Watt blue grey gold VR3 lt Potentiometer TT 55 6 PROCESSOR TECHNOLOGY CORPORATION IM 501 SINGLE BOARD TERMINAL COMPUTER SECON nr NN ON M gt gt gt NN step 61 Install following capacitors in the indicated locations Take care to observe the proper value and type for each installation Bend leads outward on solder back side of board solder and trim Refer to NOTE in Step 2 CAUTION REFER FOOTNOTE END TALS BEFORE INSTALLING C67 LOCATION VALUE ufd C47 Disc C48 0T C49 001 C50 Od Mylar TObular Cod wi DISE C66 1 1 Tantalum Cos 1 Disc C69 al 5270 001 Nn 5 72 Mylar Tubular 42 2047 Disc GC TA 410 pod Ixsbtall CO7 wilh lead at top right Step 62 Install miniature phone jacks in locations J6 and Located Eo tha Tighe POSICION jack facing right insert pins in mounting holes and solder Step 63 Install subminiature phone Jacks in locations Jo and 9 an Lower tight corner ot board Install 478 aud J9 as you did and JT Step 64 In
249. m excess lead lengths The resulting final configuration is shown below Schematic Diagram 12 of the regulator includes these changes _ CN6 2 2 Rev B ProcessorTechnology Processor Technology 7100 Johnson Industrial Drive 415 829 2600 Corporation Pleasanton CA 94566 Cable Address PROCTEC Sol MANUAL ASSEMBLY PROCEDURE CHANGE NOTICE 6 2 REV C Subjects Crowbar Fix for Sol Rev B Regulator P C Board Flat Washers in Final Cabinet Assembly To enhance the reliability of the crowbar circuit which protects circuitry from overvoltage on the 5 volt supply add the following additional parts supplied with your kit to Sol Reg Use the procedures given below after completing Step 13 of Section II Sol Power Supply Assembly and Test Make a note in your manual after Step 13 to remind you to do the additional steps below Refer to the drawing on the next page as you add the parts to Sol Reg Select the following additional parts from your kit 1 R13 330 ohms 1 4 watt color code orange orange brown 2 R14 100 ohms 1 4 watt color code brown black brown 3 05 1N270 4 C8 047 disc ceramic Step 1 Pass the two leads of under the two leads of R2 330 ohms and bend around the leads of C8 close to the body of the resistor Solder and trim the leads Step 2 Wrap the leads of R14 around the right hand leads of SCR and R2 330 ohms dressing the leads as shown in the drawing Make Sure the leads
250. mode allows the introduction of the second level of software This level includes higher level language programs such as BASIC 5 or FOCAL in which complex application programs may be more easily written These are called higher level languages because they permit the user to write programs ina form much closer to human languages such as English However programs written in these languages must be translated into the more basic machine language before they can be run Besides higher level languages this second level of software includes programs such as the TREK 80 and GAMEPAC video games and the ALS 8 program software package used for developing programs all of which are offered by Processor Technology Corporation Through the facilities of the command mode these second level programs are transferred loaded into memory from cassette tape or other storage media and then executed used These programs may also exist in ROM or EPROM erasable programmable ROM memory which is plugged into the computer to make them instantly available like the SOLOS program All first and second level programs are stored in the computer as binary object code Let us illustrate the concept of the second level of programs with an example BASIC 5 Using the command available in the SOLOS command mode we load the BASIC 5 program into the computer s memory from cassette tape With this command BASIC 5 is ready for use as soon as the tape has stopped m
251. n 9 supplies PIAK on pin 5 of J2 When high PIAK signals the external device that Sol has yet to complete acceptance of the data The state of 10 of U72 is transmitted to of the Internal Data Bus through U71 tri state noninverting buffer U71 is enabled only for the d ratrion or PORT IN FA Status During Lhe came U L s enabled the CPU reads the Internal Data Bus A high INT1 indicates the parallel input data is not ready a low indicates the data is ready Ihe second U72 flip flop is preset by PORT IN FD or POC IN FD is active to read data in from the POC occurs only when Sol is restarted or power is turned on Thus the PP is reset and ready for another transfer at the end of a transfer or when POC 1s active PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION TION VILI PXDR on pin 16 of J2 is supplied by the external device It indicates the device is ready to receive data PXDR is buffered to INT2 and will effect the transfer of data to the Internal Data Bus during the status input to the CPU PXDR 15 analogous to the viously discussed PIAK signal Sense Switches 52 1 through 8 are driven by PORT_IN_FF when lt 15 low Thus the DIO lines connected to closed switches are driven low and those connected to open switches are pulled high U97 a 4 bit D type register and one section of U52 a J K flip flop connected as a D flip flop
252. n the cut off region also but a sufficient positive pulse from 04 will cause Q2 to conduct to give a negative pulse output across RIZ Transistors Ql Q6 Q5 and Q3 represent a second pulse am plifier circuit that is analogous to transistors Q9 Q8 Q7 and Q4 respectively The output of this second amplifier which appears at the collector of Q3 is also connected to the base of the output transistor Q2 An input pulse from either 019 022 will therefore supply an amplified negative pulse to pin 13 of NOR gate 014 The PKD signal through R24 helps to set the threshold at the base of Q4 and Q3 This threshold is normally high when PKD is high So the output from Q7 and Q5 has to overcome a higher threshold at the emitter of 04 and Q3 in order to cause conduction of 04 and Q3 On the second such pulse on the same count address PKD goes low to reduce the threshold at the bases of 04 and Q3 This sensitizes the circuit acting as a positive feedback path and gives an output Thus two consecutive detections of a key stroke are necessary to give an output This feature provides noise immunity since a single noise pulse will not pass through the amplifier The complete key switch matrix is scanned at a very high rate compared to the time it takes to physically press and release a key Thus a key closure will be detected even though the key is not held down for any appreciable time Two sections of NOR gate 014 are connected as a cross c
253. nd out to determine the OFF position Switch mechanically out Wath switeh OFF position connect AC power cord to AC receptacle Then plug power cord into 110 V ac outlet Step 48 Test power supply for proper operation Rev B 4 Make sure on off switch 15 in OFF position Install fuse in fuse holder NEVER INSTALL OR REMOVE FUSE WITH POWER ON Check connector on Sol PC power cable 4 wire to insure it 18 wired as shown in Figure 2 6 Check connector on Sol 20 power cable 5 wire to insure it is wired as shown in Figure 2 7 Turn on off switch ON Measure the voltages at the Sol PC connector at the points indicated in Figure 2 60 The voltages must be as given in Figure 2 6 NOTE Do not take voltage measurements at any other points in the power supply even through they may be more accessible It 2S impor ant that the indicator voltages be available at the connector T5 PROCESSOR TECHNOLOGY CORPORATION ool POWER SUPPLY LON TI Measure the voltages at the 501 20 connector at the points indicated in Figure 2 7 voltages must be within the ranges given in Figure 2 7 See preceding NOTE Gy Che power Supply fails of Lhe preceding tests locate and correct the cause before proceeding If the power supply is operating correctly turn on off switch OFF disconnect power cord set power supply to one side and go on to Se
254. ne OO 1 03 Pass back the current cursor line character posi tion in Registers BC Register B is set to the character position 00 3F and Register C is set to the line position 00 0 1B 04 Pass back the memory address of the current cursor location into Registers BC Cscapoe Sequences Ms SUBROUTINES cont Escape sequence Feuer OH 1B 05 1B 06 1B 07 The third use o Utpub to the VDM at th current cursor position exactly as is regardless of this byte s value No check is made of this character 44 Being a control character it is only placed into the VDM memory as is and the cursor 15 advanced one position 1B 08 The display speed is set to the value Specified The speed ranges from 00 fastest to FF slowest IB SEE This functions the same as escape sequence 01 The cursor is positioned to character position of the current display line F Cassette Tape Entry Points to SOLOS SOLOS contains subroutines to handle data transfer to and from two cassette units Both block by block and byte by byte access are available While performing any tape read the user can return to the present calling software program by pressing the MODE or Conbtrol d ev In block transfers each request results in tape movement and d or um informacion block Do cor From e Locacion D memory SOLOS uses block by block access to provide the tape commands In byte transfers
255. ng SHIFT returns the keyboard to lower case and causes the SHIFT LOCK indicator tTO G0 OU pu UPPER CASE Key Indicator Pressing this key shifted or unshifted to turn the indicator light on activates the upper case keyboard function so that all alphabetic characters entered from the keyboard regardless of SHIFT key status are transmitted as upper case characters Dual character keys however do respond to the SHIFT key With the indicator light on the Sol keyboard essentially simulates a teletype TTY keyboard Pressing UPPER CASE to turn the indicator light off returns the keyboard to normal SHIFT key operation VII 22 PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VLI Table 7 5 Control Character Symbols and Definitions HEXADECIMAL SYMBOL GENERATED BY CODE 6574 Generator 6575 Generator AK BL BS CN CR Dl DEFINITION Acknowledge Bell Backspace Cancel Carriage Return Control 1 Control 2 Device Device Device Control 3 Device Control 4 Delete Data Link Escape End of Transmission Block Escape End of Medium Enquiry End of Transmission End of Text Form Feed File Separator Group Separator Horizontal Tab Line Feed Negative Acknowledge Nuli Record Separator Substitute Start of Heading Shift In Shift Out Start of Text Synchronous Idle MOFllpooeLvea olOscooetm
256. now readily seen that the Baud rate available with S3 8 is 9600 assuming the L M connection is made 153 6 KHz 16 9600 The L M connection is default wired on the Sol PC that is there is a trace between L and M on the circuit board If the L M trace is cut and a jumper is installed between K and M the Baud rate with S3 8 is 4800 76 8 KHz 16 4800 We can thus select any one of eight clock frequencies for the SDI UART with S3 with the highest being determined by the K L and M jumper arrangement Ihe selected clock is applied to both the re ceive and transmit clock inputs pins 17 and 40 respectively of the UART This means of course that the UART always receives and trans mits at the same Baud Rate 20 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION VELI Returning to the SDI UART we see that its transmitter output on pin 25 is applied to pin 5 of U55 a two input NAND gate that is functionally a NOR gate It is normally enabled on pin 4 by pull up resistor R44 A low on pin 5 represents a binary 0 a high sents a binary 1 The inverted output on pin 6 of U55 is again inverted assuming Sol is not operating in Local by the following U55 NAND gate One half of operational amplifier U56 operating open loop converts TTL levels to RS 232 levels 5 to 15 volts Pin 3 of U56 is held at 2 5 V dc by the R47 and R48 divider network When pin 2 is more negative than pin
257. ns PIN NUMBER SYMBOL NAME FUNCTION 8V 8 Volts Unregulated voltage on bus supplied to PC boards and regulated to 5V supplied by Sol 20 supply 2 16V 16 Volts Positive unregulated voltage supplied by Sol 20 power supply 3 XRDY EXTERNAL READY External ready input to CPU ready circuitry 4 VIO Vectored Interrupt Line 0 5 VIL Vectored Interrupt Line 1 6 VI2 Vectored Interrupt Line 2 7 VI3 Vectored Interrupt Line 3 8 VIA Vectored Interrupt Line 4 9 VI5 Vectored Interrupt Line 5 10 VI6 Vectored Interrupt Line 6 11 VI7 Vectored Interrupt Line 7 12 XRDY2 EXTERNAL READY 2 not used by Sol PC 13 to TO BE DEFINED 17 18 STAT DSB STATUS DISABLE Allows the buffers for the 8 TRE status lines to be tri stated 19 C C DSB COMMAND CONTROL Allows the buffers for the 6 DISABLE output command control lines to be tri stated 20 UNPROT UNPROTECT not used by Sol PC electronics 21 SS SINGLE STEP not used by Sol PC 22 ADD DSB ADDRESS DISABLE Allows the buffers for the 16 address lines to be tri stated 23 DO DSB DATA OUT DISABLE Allows the buffers for the 8 data output lines to be tri stated 24 02 PHASE 2 CLOCK 25 01 PHASE 1 CLOCK 26 PHLDA HOLD ACKNOWLEDGE Processor command control output REV A signal that appears in response to the HOLD signal indicates that the data and address bus will go to the high impedance state and processor will enter HOLD state after completion of the current machine cycle AVII 3 PIN NUMBER
258. o simultaneously hit repeat ana Upper case keys LO reset the computer Cassette Tape Parameter Commands The Following SET commands affect the cassette tape parameters Set Tape Command DEI TAPE S SI This command selects one of two standard speeds O 1200 baud high speed 1 300 baud low speed Normally set to 0 10 IV SET COMMANDS cont Set Command DET TYPE data This command sets data values into the type byte in the tape header information when used in conjunction with the SAVE command The type byte data is entered as a hexadecimal value but it will appear on the screen as an ASCII character when displayed by the GET or CAT command Only displayable characters should be used for type values data The most significant bit of the type value determines if the tape file can be executed automatically by an XEQ command 0 Auto execute 1 Not executable Typing of tape files can be very useful in grouping common files Example OEL SYP 47 47 character for GAME FILES Sign Bit 0 auto execute SET TYPE 50 50 P character for PROGRAM FILES Sign Bit 0 auto execute obl TYPE C4 Tp character tor DATA FILES Sign Bit 1 non execute Set Execute Command SET XEQ addr This command sets the auto execute address addr word into the tape header information when used in conjunction with the SAVE command This address word is used by the XEQ command after load ing a tape file to
259. of purchase Also products assembled by the buyer are warranted for a period of 3 months after the date of purchase factory assembled units carry a one year warranty Refer to Appendix I for the complete Statement of Warranty 1 2 4 Replacement Parts Order replacement parts by component nomenclature DM8131 IC or 1N2222 diode for example and or a complete description 680 ohm 1 4 watt 5 carbon resistor for example PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL SECCION I Factory Service In addition to in warranty service Processor Technology also provides factory repair service on out of warranty Processor Technol Before returning the Unit to Us first obtaim our authorization to do so by writing us a letter describing the problem After you receive our authorization to return the unit proceed as follows 1 Write a description of the problem 2 Pack the unit with the description in a container Suitable to the method of shipment 3 Ship prepaid to Processor Technology Corporation 6200 Hollis Street Emeryville CA 94608 Your unit will be repaired as soon as possible after receipt and return shipped to you prepaid Factory service charges will not exceed 20 00 without prior notification and your approval 5 POWER ME som Parco and omens 1 5 m C Open mue
260. on G Sols to Revision H level 1 Change the value of R27 from 470 ohms to 4 7K ohms 2 On the solder side of the PCB cut the trace connecting 039 pin 1 to the cathode of D3 Check with an ohmeter to be sure the cut is complete 3 Wrap one lead of R169 47 ohm resistor around pin 1 of 039 4N26 and wrap the other end around the cathode end of D3 band side of 1N4148 Solder both leads of R16 and check for possible shorts This change was to enhance the reliability of the opto isolator which couples a current loop device to the Sol WW 5 x e CUT O Td U 39 REF S ari 5 3 49 12V A R2 lt 3 SK 12 R27 3 U38 US 20 489A DA IN 4142 4 22 GET EL 5 1 Sol MANUAL ADDENDUM Sol MANUAL ADDENDUM 1 Technology Reference Section X Drawing 23 A block function labelled K T C is shown between U 19 and 022 and 014 This block contains the Capacitive Switch Detector Circuit The parts constituting this circuit are listed and the assembly covered in Section V of this manual The theory of operation is covered in Section VIII At the time of publication of this manual operation of this circuit was proprietary information but has now been released The schematic is shown below Note on the schematic X 23 that this detail is shown here on this page RIZ 12 3K gt 01 4 PIN 15 INA 92 PIN
261. one for Page CO hex and the other for C4 hex are provided The CO and C4 enables are connected to pins and 5 respectively of J5 the sonality Module connector Unlike the RAM the ROM can only read data into the CPU so the previously discussed MWRITE signal is not needed Data out of the ROM is output on the Internal Data Bus on pins A4 and 5 10 of 25 ADR1O 15 are input to the Address Page and Port Decoder 034 3 05 36 and their associated logic U34 Address Page U35 Output Port and U36 Input Port are 3 to 8 line decoders which have three enable inputs Gl G2A and G2B must be high and both G2A and B must be low in order to obtain an active output Let s look at the Address Page Decoder U34 first It must be able to decode four pages and C4 ROM C8 System RAM and CC Display RAM Note that these are the hexadecimal digits of the Six high order address bits ADR10 15 The high order four bits ADR12 15 must be 1100 C hex in all cases by virtue of the U22 exclusive OR logic If they are not the Gl enable 034 is low to disable that decoder Bits 10 and 11 The A and B inputs to U34 are the high order bits of the second hexadecimal digit which must be 00 0 hex O1 4 hex 10 8 hex or 11 12 hex if U34 is to have an active output For CO pin 11 of 934 15 active low Tor pin 10 active for CS 9 is ac tive and for CC pin 7 is active These ou
262. ool SYSTEMS MANUAL fechnology 6200 Hollis Street Emeryville CA 94608 Phone 415 765229050 Copyright 1976 1977 Processor Technology Corporation Prantvng June 21977 Manual No 106000 PREFACE This new edition of the Sol Systems Manual contains many revisions and additions Its release coincides with the release of a new 2708 Personality Module and the Revision E version Or the Tuas beard The new Sol PC Rev E has several improvements resistors have been added which increase the reliability of the cassette motor relays jumper options have been added traces moved to Improve performance Many improvements which had been accumulating as update information have been integrated into the text Section VII Operating Procedures and Appendix 5 IC Pin Configurations are now included A subsection Modification for 625 Line Video has added Li your sS missing Section VIII Theory Operation it will be available soon New divider pages with plastic coated tabs are included to make it easier to flip to frequently referenced sections Much effort has gone towards making this manual complete and accurate The process of updating and revision always continues however and we invite your input If you should find an error or have suggestions for improving any of our documentation please submit your suggestions in writing to our Technical Documentation
263. or on fan closure plate to connector on expansion chassis Solder inner conductor to pin of connector Remove hex nut on upper rear connector mounting screw place lug coaxial Shield and 4 lockwasher on screw in that order and secure with nut REV C VI 12 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Step 26 Install male coaxial connector on free end of co axial cable that is connected to Sol PC the composite video output cable Install connector as follows refer to Figure 6 5 3 4 DEM Se ee 254 Coupling Adapter Braid Plug Subassembly Ring Figure 6 5 Sol PC coaxial cable connector assembly Slide coupling ring and adapter on cable in that order and cut end of cable even Remove one inch of outer insulation Fan braid slightly and fold back over outer insulation as shown Slide adapter fully up under braid and press braid down over adapter body Trim braid so that it does not interfer with adapter threads Remove 3 4 of inner conductor insulation and tin ex posed conductor Slide cable fully into plug subassembly and screw sub assembly on adapter Solder braid to plug subassembly shell through solder holes Use enough heat to create a good bond between braid and shell Solder center conductor to plug contact by filling con tact with solder Cut off excess conductor Slide
264. ort For information on 8080 operation refer to the Intel 8080 Microcomputer Systems User s Manual As shown in the Sol Simplified Block Diagram on Page X 24 in Section X data and control signals travel between the CPU and the rest of the Sol over three buses 1 16 line Address Bus 2 an eight line Bidirectional Data Bus and 3 a 28 line Control Bus which 1s interfaced to the CPU with support logic circuitry Note that the use of a bidirectional data bus permits eight lines to do the work of 16 eight input and eight output These three buses account for the bulk of the S 100 Bus which connects the Sol to expansion memory and I O modules NE op PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECCION VILI the 501 20 the 5 100 Bus structure takes the form five slot backplane board It consists of a printed circuit board with 100 lines 50 on each side and five edge connectors on which like numbered pins are connected from one connector to another Functionally the Sol version of the S 100 Bus is comprised of 1 Sixteen output address lines from the CPU which are input to art external memory and I O Direct memory access DMA devices must generate addresses on these lines for DMA transfers 2 Eight data input output lines that transfer data between external memory and I O devices and the CPU or DMA de vices These eight lines are paralleled with eight other bus lines
265. osition control characters are displayed Video Display POLARITY Switch S1 4 If you want a normal video display white characters on a black DeckOround Ss95 UD swivel uo us ON DOSZULIONS ORF POSICION black characters will be displayed on a white background reverse video FE SEU Cursor Selection BLINK SOLID 51 9456 CAUTION DO NOT SET S1 5 AND S1 6 TO THEIR ON POSITIONS AT THE SAME TIME TO DO SO MAY DAMAGE YOUR Sol wOu wemnt the cursor to St 11 6 to and 1 ON The cursor will blink on and off about two times per second oet ol b5 to OFF and 91 6 to ON 1f you want non blinkrng solo ui sor With both S1 5 and 51 6 in their OFF positions there will be nO Cursor play Sense SSWO 7 Switches 52 1 through 52 8 These eight switches are normally left in the OFF position They are used to manually enter data into the CPU They serve the same function as the front panel sense switches on the Altair 8800 and IMSAL 80807 Nobel PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES o2 1 is the least significant data bit D100 52 6 is the most significant data bit DIO7 To pull a DIO bit low when the program tests SSWO 7 set the switch associated with the bit to ON An open OFF switch pulls the associated DIO bit high when the program tests Sowo T NOTE Ihe configuracion Of 7 56 tested
266. oupled flip flop on 13 of 014 sets output pin 1l of 014 high providing that the low is longer than 1 5 usec which it is when a valid key closure is detected That is because 11 15 applied to pin D 35r 01 effectively prevents switching noise which is short in duration from being interpreted as a key closure The high let s Gall KEY on pin ll or 014 will remain until 01 again goes low about 4 5 usec later VIII 41 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON LII KEY is fed to pin 5 of 8 input NAND gate 025 pin 9 of ROM 020 and pin 1 of NAND gate 027 Let s examine the other inputs to KEY mentioned is fed to pin 9 of 020 which 15 a 256 x 4 bit static ROM Only two bits are used For each possible row column combination there is one storage location in 020 1 and DOl pins 9 and 11 are the input and output respectively of one bit location DI2 and DO2 serve the same functions for the other bit location The row count is applied to A0 4 and the column count is applied to 5 7 to address 020 When a key closure is detected the counts are presented to U20 continuously When the counts change shortly after the failing edge of 1 020 outputs the status of the address that is already stored in the ROM about 1 usec later on pin 10 On the rising edge 1 after the address change the status on pin 10 is latched in one half of D flip flop U26 and
267. oving The control of the computer is now taken over by the BASIC 5 program now in memory and SOLOS is no longer in command All the features of BASIC 5 language are now available to us with a new set of commands and rules the CPU of the computer only understands the machine language of the first level of software the BASIC 5 program must translate the commands and data we enter to this lower level BASIC 5 does this we go While we are using BASIC 5 we still have access to some of the commands and features of SOLOS although they may have a modified form while we are in BASIC 5 We will load and use BASIC 5 later in this section The third level of software consists of programs written using the higher order languages of the second level programs A program written n BASIC S 1S on this third level hrs program only makes sense to the computer while the computer has BASIC 5 in memory control has been transferred to the BASIC 5 program Third level programs written in any high level language are often called applications programs since they are usually written in order to fit a specific application need The ALS 8 Program Development System is another second level program A program to be developed within ALS 8 would then be a third level application program The ALS 8 also includes an Assembler which takes a program written on the third level in assembly language and translates it to object code which the com
268. parallel input and output data is FD hexadecimal and the control port address for the PDI is FA hexadecimal PXDR is available at bit 2 of port FA When this bit 15 set to 0 the external device is ready to receive a byte of data PDR is available at bit I of port FA with O indicating the external device is ready to send a byte of data Parallel Unit Select PUS is controlled by bit 4 of port FA The input and output enable lines are available for tri stating an external two way data bus Use of the three control signals is optional and is unnecessary when only one device is connected to the PDI connector Paragraph 7 9 3 continued on Page 31 Mab PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES 01 ASR33 TTY Sol SDI BARRIER STRIP Right Rear CONNECTOR C Signal Ground 5 6 PRINT MECHANISM ae Current Loop Output CLO 7 Loop Receiver 1 181 Loop Receiver 2 LR2 Current Source LCS CAUTION PINS 1 AND 2 ON TTY BARRIER STRIP CARRY 120 V ac LINE VOLTAGE Figure 7 6 Connecting Sol 501 to current loop device such J1 Sol SDI BELL 103 CONNECTOR _ MODEM Transmitted Data TD 2 Received Data Available at bit 1 of port F8 Terminal mode SOLtware 15005 al does not use taxe and transmits data whether or not the modem is ready Sol is wired so that DTR indicates a ready condition whenever
269. pin 14 of U85 is supplied from the Video Dis play Generator A phase comparator in U85 compares this signal to the output of a voltage controlled oscillator VCO in 085 By feed ing an output from U86 in this case the 1200 Hz output on pin 3 back to the compare input pin 3 of U85 the circuit acts as a fre quency multiplier The output pin 4 of U85 remains locked there fore to a multiple of its input on pin 14 this case we have 128X multiplier to generate 153 6 KHz which is counted down 086 Since U86 is a 7 stage binary counter the first stage output pin TZ 75 0 Ie lt or 5546 KHz Che clock for USO the se cond stage output pin 11 is 38 4 KHz one fourth of 153 6 KHz the third stage output pin 9 is 19 2 KHz one eighth of 153 6 KHz and so on to the seventh stage output pin 3 which is 1 2 KHz 1 128 With the exception of outputs on pins 12 and 9 the outputs of US6 are connected to 53 the Baud Rate Switch The 19 2 KHz out put omn prn 9 is divided Dy LI tn US4 to supply 1745 Hz to 93 2 38 4 KHz on pin 12 can be connected to S3 8 instead of the 153 6 Hz clock by cutting the L M connection and installing a jumper between K and M Let s now translate the frequencies input to 53 into Baud rates The Baud rate of a UART is 1 16 of its clock rate Thus a 1200 Hz clock equates to a 75 Baud transmission rate a 1745 Hz clock equates to a 109 1 110 Baud rate etc It is
270. playable scan line and the number loaded into 022 defines the character row 0 through 15 Uil preset by IVDLSP trom pin 9 U43 This means 011 is forced to its preset condition from the end of the dis played text to the top of the next character row During this time pin o of another U43 J K flip flop is set high to preset Ul If U11 is preset to 0 its TC output on pin 7 is low and pin 6 of U43 is re set to a low This allows Ul to count with each horizontal scan line If Ull is preset to any number other than 0 pin 6 of U43 can not be reset low until 011 reaches zero Assume 011 is preset to two It must count down two character rows before Ul starts count ing During this time pin 7 of U43 PRE_BLANK is low and as pre viously discussed the display is blanked We can now see that the PRE BLANK time often called window shade 15 variable with the number loaded into 11 Therefore scrolling is performed by changing the numbers in U2 and 013 without the need to reposition the text within the Display RAM The remaining circuit in the Display Section consists of transistor 02 one section of 087 89 and 102 088 0102 are con nected as a one shot 250 msec timer that is triggered when OUT FE goes active pin 1 of inverter 087 goes high Thus when data is loaded into 02 and 013 this timer starts Tri state driver U89 which is enabled by PORT IN FE transmits the state of this timer to D1
271. ples CONTROL SEQUENCE 6574 SYMBOL 6575 SYMBOL CTRL and I gt Hr 5 cor 5 x EQ Step 16 Change video display polarity by setting POLARITY Switch SI 4 to ON and observe the effect on the display It should change from black characters on a white background to white Characters oon bDackoroumnd obep l7 Switch from noneblanking cursor to c blinking cursor by SELLING SOLID Swrtchl S160 So OBRF and BLINK Switch 91 5 0 In hat order Should Se a KXeobgDgulsr Sold Cursor That bornes on ng approximately two ties per Second Never put To Blank control characters by Setting BLANK 051 5 to ON Any control characters generated refer to Step should not appear on the screen Up to this point keyboard data has been processed by the CPU transmitted out through the serial channel output looped back BRE PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES to the serial channel input and then displayed on the video monitor You have consequently just tested the CPU serial channel and display section functions am your sol 7 4 3 Command Mode Operation The following operations assume your Sol is equipped with a SOLOS personality module Using the Cassette Recorder The following procedure for loading a program from cassette tape into Sol memory provides a good example of how to use an audio cassette recorder with Sol th
272. ponent front side of the board no solder mask is facing up Subsequent position references re lated to the Sol BPB assume this orientation 06 5 2 Sol Cabinet Chassis Unless specified otherwise all position references e g left right front back bottom and top in the cabinet chassis assembly instructions assume the Sol cabinet is viewed from the front keyboard when it is sitting in its normal position key board up 6 6 ASSEMBLY TEST 6 6 1 Backplane Board 501 Assembly Refer to Detail on Drawing 8 in Section REV VI 6 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI REV Step 1 Visually inspect Sol BPB PC board for obvious flaws such as solder bridges shorts between traces broken traces and similar defects If visual inspection reveals any defects return the board to Processor Technology for replacement If the board passes inspection go on to Step 2 Step 2 Install 100 pin edge connector Item 5 on Drawing X 8 on top edge of PC board This edge has silver not gold contacts NOTE This connector is supplied as a trouble shooting aid It is not critical to normal operation of the 501 20 Position connector on PC board so that its 1 trace is aligned with the 1 trace on the board and push connector fully onto board Bend the connector pins slightly so that both rows of pins are in light contact with the traces on the board DO NOT CLOSE C
273. presented at output pins 9 and 5 About 1 5 usec later the R W signal on pin 20 of U20 goes low and the KEY signal on pin 9 enters the specified location in U20 Note that this KEY is related with the new count address The key stored in 026 represents the preceding address We consequently call the HEY am 26 TREY eens sei o pon db U2 52 The remaining inputs to 025 are 1 2 an inverted 102 on 12 2 a repeat strobe signal on pin 4 supplied by pin 11 of NAND gate 016 which is high without a repeat command 3 minus 1 on pin 6 supplied on pin 3 of U26 which is low if three or more count cycles have occurred since one key closure and 4 the column out put on pin 4 Ort which rS applred pins Ly Zand 2 The last signal drives the column associated with the special function keys on the keyboard SHIFT SHIFT LOCK LOCAL BREAK UPPER CASE REPEAT and CONTROL In order for U25 to output a low on pin 8 therefore we need a current KEY a KEY from the preceding count cycle no repeat function no drive on pin 4 column 30 hexadecimal and we must be on the second count cycle during the current key depression With these conditions satisfied output pin 3 of U25 goes low It is inverted by U10 to a high on pin 11 This signal then clocks the output latches Ul and 2 On this signal the data present on the inputs are latched into Ul and 2 and it remains latched until the next output Om pin
274. produce a small negative going spike at the input to the Capacitance Keyswitch Detector VIII 40 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION VELI This detector GODnSISts Of three tralsrisStors 527208 and Q9 connected as a linear amplifier with negative feedback fol lowed by Q4 and 02 04 and Q2 are large signal amplifiers biased in their cut off region The input to the detector is selectively con nected to 5 V dc by way of the analog multiplexers Ul9 and U22 the row matrix wires and the 33K resistors A key depression causes a negative current pulse through R16 to the base of the input ampli fier transistor Q8 which is biased near cut off The pulse is then amplified by Q8 with inversion to appear as a positive pulse at the input of Q7 07 is an emitter follower circuit which gives a posi tive pulse at its output across R18 at a low impedance This sig nal is coupled back to the input through transistor Q9 a common base amplifier which has its base clamped to 2 5 V dc by zener diode CR4 When the positive pulse appears at the emitter of Q9 it is amplified without inversion and applied to the input of Q8 Since the original input was a negative pulse the positive pulse consti tutes negative feedback The output across R18 a positive pulse is further amplified by pulse amplifier transistor 04 a common base amplifier that is normally biased off The output stage Q2 is bi ased i
275. puter can run The object code version then resides in memory and can be run in another operation For a further discussion of types of software see the article Your Personal Genie in Appendix VIII of this manual Mab beu PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES SECCION VLI Terminal Mode Sol operates as a CRT terminal in this mode capable of sending keyboard data to an output port and displaying data received at the serial input port on an external video monitor via the Sol video display circuitry When Sol is hard wired to another computer or connected to a modem the terminal mode is used for data entry data retrieval anquiry response and monitoring and control applications Capabilities in the terminal mode depend on the personality module used Both CONSOL and SOLOS Personality Modules permit operation as a CRT terminal CONSOL 1 snztializes Sol 2n the terminal mode whenever you turn the power on or initiate a system reset 2 sends keyboard data to the serial data interface SDI only and 3 provides simple stand alone computer capabilities SOLOS on the other hand 1 enters the terminal mode when given the TERM terminal command 2 sends keyboard data to any output port available with the SET 0 set out command and 3 duplicates CONSOL functions while providing additional capabilities GETTING ACQUAINTED WITH Sol One of the best ways to get acquainted with your Sol is to use it
276. r and the tape should advance The display should not change otherwise NOTE With certain cassette recorders or cassettes there may be a misreading of the tape when the splice joining the leader to the tape passes the tape head In this case an ERROR message will appear and the tape will stop To resume tape loading retype the XEQ BASIC command If further difficulty is encountered try datterent Cassette recorder volume Settings Until a reliable setting is found Step 2T the tape loaded Successfully in approximately wo minutes BASIC 5 will display five lines of text ending with SOL BASIC 5 READY py Stee Z5 BAGTC 5 te now ready for uses Refer to your BASTC gt User s Manual Become familiar with both BASIC 5 and the Sol keyboard Try some exercises in BASIC 5 Dump Operation The dump operation displays memory data in hexadecimal on the video monitor can also be used with the appropriate SET command to output memory data to a hard copy device a printer an example dump the first part of the SOLOS personality module C000 through COEO as follows 29 UPPER CASE Kov So that the lnerestor se ON Ir you are still Tm the BASIC 5 command BYE at the beginning of a command line to re enter SOLOS command mode BASIC 5 remains in memory and may be returned to by typing a command line EXEC 0 Step 30 Type the DUMP command as follows D
277. rd CRT terminal sending keyboard data to an output port and displaying received data on the screen The COMMAND KEYS of the keyboard are not transmitted to the output port but are interpreted as direct internal operation keys CURSOR MOVEMENT HOME and CLEAR SCREEN all operate in this manner while MODE SELECT causes an immediate change in the opera tion of the unit When the MODE key is depressed CONSOL issues a prompt charac ter gt and waits for a command line to be input The Sol is now operating as a computer and is ready to accept one of the following commands DUmp Dump memory locations to screen ENter Enter data to memory Execute a program in external memory BAsic Execute a program located at address zero TErminal Return to terminal mode Load program or data from cassette tape MODE Press MODE SELECT key to start new command line PROCESSOR TECHNOLOGY CORPORATION Sol SOFTWARE SECTION IX Sd ud DUmp addr addr Ihe DUmp command displays memory data on the screen in a Hexidecimal representation with all Sol commands the command 15 recognized by the first two characters and up to ten additional char acters can be input without an error being forced Thus DU DUST DUMP DUMPTHESE would all be recognized as being a DUmp command At least one address must follow the command or a error dis planed on the screen If two addresses are input then all values from the first addres
278. rds with plated through holes Solder flow through to the component front side of the board can produce solder bridges Check for such bridges after you install each component 7 The Sol PC circuit boards have integral solder masks lacquer coating that shield selected areas on the boards This mask minimizes the chances of creating solder bridges during assembly DO however check all solder joints for possible bridges 8 Additional pointers on soldering are provided in Appendix IV of this manual 3 3 3 Power Connection J10 NEVER connect the DC power cable to the Sol PC when power supply is energized To do so can damage the Sol PC 3 3 4 Installing and Removing Integrated Circuits NEVER install or remove integrated circuits when power is applied to the Sol PC To do so can damage the IC Installing and Removing Personality Module NEVER install or remove the plug in personality module when power is applied to the Sol PC To do so can damage the module Rev A III 6 PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL COMPUTERTM SECTION III 3 3 6 Use of Clip Leads TARE CARE when using a clip lead to establish a ground con nection when testing the Sol PCB circuit board Make sure that the clip makes contact only with the ground bus on the perimeter of the board 3 4 REQUIRED TOOLS EQUIPMENT AND MATERIALS The following tools equipment and materials are recommended for assembling and testing the So
279. rity or odd parity 54 1 amp 5 Selects number of data DIS inh transmitted 9g us TOF ol tx owe es Determines number of stop bits in transmitted od Data entry mode selection command input and See Figure 7 4 CONECTO l can understand and run All programs must ultimately be reduced to this basic level to be operated on by the computer In the case of the 8080 microprocessor the program is in an object code or machine language since the machine 8080 CPU understands it The SOLOS program contained in the personality module is stored in this machine language form and the computer can therefore run directly from this program Since the SOLOS program 1s contained in permanent ROM which is plugged directly into the computer the SOLOS program is always available and 15 automatically selected whenever the power switch of the Sol is turned on There is also provision for returning at all times to the command mode of SOLOS From the command mode other programs may be brought in for various operations or stored on cassette tape The contents of the computer s memory may be displayed or changed The command mode also performs housekeeping runctrons Such as Setting the rete ac which uote Is Tread from tape Or the rate at which characters are displayed on the video monitor MET qe PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES The command
280. rnal device SRTS and SDTR and three are received from the device SCTS SCD and SDSR SRTS on pin 4 of 41 was discussed earlier SDTR serial data terminal ready is simply tied to 12 V de through R24 This indi cates to the external device that Sol 15 connected to it SCTS serial clear to send SCD Serial carrier detect and SDSR serial data set ready indicate status of the external device They enter Sol on pins 5 8 6 of 21 respectively and all three are active high Following level conversion and inversion in line re ceivers U38 data on these lines is gated through noninverting tri state buffers 037 to the Internal Data Bus when PORT IN F8 is active IN F8 also enables five bits of UART status to be re ported over the Internal Data Bus These are PE FE OE DR and TBRE on pins 13 14 15 19 and 22 respectively of the UART They are de fined as follows EE Parity Error received parity does not compare to that programmed Bit INT2 Framing Error valid stop bit not received when expected Bit QES Overrun Error CPU did not accept data before it was replaced with additional data Bit INT4 DR Data Ready data received by UART is available when requested Bit INT6 TBRE Transmitter Buffer Register Empty UART is ready to accept another word from the Bidirectional Data Bus Bit INT 7 8 5 4 Display Section An understanding of how characters are formed on the video moni
281. rocess continues for the balance of the displayable portion of the video scan line At the end of the horizontal scan line the Scan Counter changes to a binary count of 0001 which specifies scan line in the Character Generator ROM The C and T are again called up from the Display RAM for the first and second character position respec tively The ROM consequently outputs 0100001 and then 0001000 This Sequence continues through scan line R8 when the Scan Counter is at a Count orco X000 co produce the CT rm As discussed earlier the Scan Counter cycles through 13 counts or scan lines For the C and T in our example the Scan Counter has counted ben Lines 15 0 1 Ze Gy dnd Shs The remaining three scan lines are not used in forming the C or T SO On counts 9 10 li of the Scam Counter the Character PROCBSOOE TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECTION VELI Generator ROM automatically outputs all zeros for these two character positions After the last scan line in the third character row the Scan Counter 15 reset to a count of 15 to start the fourth character row The Character Generator ROM output is converted from parallel to serial form in an 8 bit shift register U41 that is clocked by DOT CLOCK For each high bit on the input the serial output pin 13 of 041 is high for one DOT CLOCK period For each low bit OH is low for one DOT CLOCK period Note that paral
282. s done so that the Data latches will output the space code 0100000 to the Character Generator ROM when the latches are reset These latches are reset each time PAGE CC is active by way of 075 a J K connected as aD flip flop and D zlrp rftlop UAZ output pin 6 By outputting the space code on reset the Data Latches insure a blank character position on the screen The Character Generator 025 has seven character ad dress inputs Al through A7 four scan line inputs 851 through RS4 and seven data outputs Bl through B7 It is programmed to generate seven bits dots of character information for the selected scan line of the character row U25 also automatically blanks scan lines that are not a part of the character and shifts the 3 p y comma and semicolon to the fifth through 13th scan lines in the dot matrix refer to Figures 8 2 and 8 3 Page VIII 24 Com plete patterns for the 6574 and 6575 Character Generator ROM s are provided in Figures 8 5 and 8 6 respectively Note that the address bits AO through A6 in Figures 8 4 and 8 5 correspond to the Al through A7 inputs to U25 on the schematic scan lines RO through R8 are specified by the RS1 through RS4 inputs to 025 on the schematic and the data output bits DO through D6 correspond to the Bl through B7 outputs from UZ5 the schematic Let s see how the Character Generator ROM produces a charac ter using an uppercase C and T as an examp
283. s eight data bits bits parity Dirt and full duplex operation for the SDT4 Figures 7 6 and 7 7 show examples of current loop and modem pnbesconu ecbtrous bo the Sol SDL donsnector 94 The ASRS32 LS used to illustrate a current loop interconnect and the Bell 103 modem is used to illustrate a modem interconnect When operating in the terminal mode and full duplex Sol keyboard data is transmitted out on Pin 2 of Jl and date received on Pin 3 of Jl is displayed on the video monitor In the command mode SOLOS set in and out commands can be used to channel output data and input data through the SDI Lo Your sonos Users Manual Tor instructions on how to use the set commands In either mode the LOCAL key directly controls the SDI With the LOCAL indicator light on received data is ignored and keyboard data is not transmitted It is however looped back for display on the video monitor With the LOCAL light off received data is displayed and keyboard data is transmitted but not displayed unless it 15 echoed back Parallel Data Interface PDI The Sol Parallel Data Interface J2 is used to drive parallel devices such as paper tape readers punches and line printers It provides eight output data lines eight input data lines four handshaking signals and three control signals The latter allow up to four devices to share the PDI connector See Appendix VII for J2 pinouts Ihe port address for
284. s for a stable raster Step 10 You should see a prompt character followed by the cursor 2M in Che upper left corner or the screen If you don t adjust VRI and VR2 see Figure 7 3 to move the prompt character and Cursor ono screen With CONSOL only the cursor will appear on the screen NOTE Use VRL horizontal posicion VR2 vertical position to center the display page 16 lines 64 characters line on the screen i 2N2 C 02 R ta Q T hj 3 LJ ui it z TERS 154 35 REM z Vertical FRONT OF Sol VR2 Ve A Left VRI Horizontal all T oa EL TT 1 TTL 11 40 paqure 354 LOCACION Of posrtroning adjustments VRI and VRZ CJ weep It Terminal mode Vv 1 pressing VEPER CASE Key to turn the indicator light on Alphabetic characters are NOW entered Upper case regardless Of SHIFT key Status but duel character keys dO respond XO SHIET 22 TERM and 3 pressing RETURN key If your Sol is equipped with CONSOL it entered terminal mode when you turned the Sol on TERM will appear on the screen as you type and the cursor will disappear when you press the RETURN key So PROCESSOR TECHNOLOGY CORPORATION OPERATING PROCEDURES NOTE All commands must be given in upper case characters order to be recognize
285. s low for the first count On the second count KEY minus I goes low as do pin 6 of 016 and pin 12 0f 120 th next 102 clock the Gata 15 read into U20 Th output on pin 12 of U20 changes to remove PKD which increases the Capacitance Keyswitch Detector threshold for greater noise immunity It also sets minus on pin 5 otf 026 on the third count cycle VIII 43 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION LON VELI following release of KEY On the third cycle the circuit reverts to Les Original State This circuit comprised of 020 026 016 and 017 serves two functions By requiring two events during two consecutive count cy cles before generating a KEY it discriminates against false key clo sures It also insures that multiple key strokes are serviced in or der This is the n key rollover feature That is because the row column addresses are continuously presented to U20 and this circuit s cycle can occur for each possible key closure U20 can thus contain data for all possible key closures and the data will enter Ul and U2 on the KEY generated for each closure as the row column count pro gresses Ihe previously mentioned column 30 output on pin 4 of U17 drives the keyboard control key switches Data for these key clo sures present on pins 1 2 and 3 of addressable latch U12 is latched iiy UIZ during Clock 38 2 when column 30 is driven Pin 13 of U12 is connected to the
286. s read clock for the CDi UART 262 CDI controlb rnvolves IPORT PORT IN PORT OUT TAPE CONTROL 1 and 2 POC power on clear HIGH SPEED HI SPEED The last two were previously explained in the dis cussron or Uli IN FA strobes the CDI UART status DR TBRE OE and FE refer to Page VIII 22 for definitions to the Internal Data Bus INT3 7 PORT IN FB strobes received data on pins 5 12 of U69 to the Internal Data Bus INTO 77 OUT FB loads data from the Bidirectional Data Bus DIOO0 7 into 069 POC simply resets U69 whenever power is applied to the Sol TAPE CONTROL 1 and 2 are used to turn one or two recorder motors on and off An active low TAPE CONTROL 1 energizes Kl to close its contacts and turn recorder 1 on a high de energizes to turn the recorder TAPE CONTROL 2 does the same thing with K2 to cCODLrol another recorder Diodes Dlo 14 which shunt VIII 34 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION VELI respectively prevent damage to the logic circuitry in the Output section due to inductive kickback R155 and 156 are current limiters that keep the relay contacts from welding together When the CDI is in the write mode data is input to the UART U69 under control of PORT OUT FB Upon completion of this strobe the transmit sequence is initiated within the UART with the
287. s to the last will be displayed DUMP 0 EF Up to ten blanks may be inserted between each parameter without forcing an error condition Errors are indicated by a ques tion mark replacing the character where the error occurred For example if the DU command were given without an address the question mark would appear ten spaces to the right of the U Sho ENter addr The ENter command places sequential bytes into memory begin ning at the specified address Data represented as hexadecimal values are input from the keyboard for entry to memory All CONSOL commands except MODE SELECT are executed when the RETURN key is pressed After the ENTER address RETURN sequence the Sol Dis plays a colon prompt character Values are then input one line at a time with each line terminated by a carriage return or linefeed Ihe ENter function itself is terminated with a slash and the Sol goes back to the command mode when the slash is encountered With all command functions of CONSOL input lines are ter minated with a carriage return or line feed If the terminator is a C R CONSOL will erase all characters from the current cursor loca tion to the end of the screen line In this case all valid input should be to the left of the cursor If an error occurred during input the cursor may be moved to the left using the cursor left key and the erroneous characters changed A linefeed would then be used as a terminator since LF does not erase
288. specify the character row position one of 16 on the display screen PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON LII Normally the internal display address is multiplexed to the Display RAM When the CPU or a DMA device requests access PAGE CC active the multiplexers switch to the external address lines ADRO 9 Seven bit ASCII coded data is written into RAM chips 014 through 920 from bits DIO0 6 the Bidirectional Data Bus and the cursor bit DIO7 is written into RAM chip 021 This writing occurs when the write enable WE input to the RAM chips is low This oc curs when the Display RAM is addressed PAGE CC active low and MWRITE on S 100 Bus pin 68 is high The enable is supplied on out put pin 8 of NAND gate U44 Data is read out of the Display RAM when pin 8 of U44 is high Data out of the Display RAM is placed on the Bidirectional Data Bus via tri state drivers U29 and U89 when CC and PDBIN S 100 Bus pin 78 are active 029 and 089 are enabled by a low output on pin 11 of another U44 NAND gate Data out of the Display RAM is also strobed into Data Latches U26 and U27 by LOAD CLOCK Seven outputs from these latches are used to address the Character Generator ROM U25 Note that the output from RAM chip U19 is inverted in exclusive OR gate U74 before being applied to the C input pin 13 of U26 and the complement pin 14 of the QC output of U26 is used in addressing U25 This i
289. ss Multiplexer U30 and U32 which supplies the low order six address bits to the Display RAM U14 through U21 The second address source for the Display RAM is the Address Bus bits ADRO 5 Address source selection is con trolled by the output omn 7 ot D fIlsp rlop Ulos Pin Tf 019065 high when PAGE CC the Display RAM is active and PSYNC amp 102 high which it does in the middle of PSYNC Pin 7 of 075 remains high for the rest of the memory access cycle Ihe preset signal pin 8 of 047 to 031 and U33 is applied to the Scan Counter 040 via inverter 087 040 counts the horizontal scan lines that make up a row of characters and supplies the line number to 025 the Character Generator ROM This ROM is discussed later 040 is preset to a count of 15 for the first scan line in the character It then counts from 0 through 11 On count 11 SCAN ENABLE on pin 8 of U47 is inverted in U87 to disable the Scan Counter decoder comprised of NAND gates 059 and 060 decodes the 13th count count 11 in 040 and SCAN ENABLE to supply a load pulse to pin 9 of U40 This resets U40 to a count of 15 and the cycle re peats Presetting the Scan Counter to a count of 15 permits the Character Generator ROM to provide a blank spacer line between char acter rows since line 15 in the ROM is always blank The output on pin 8 of NAND gate 059 after inversion in 087 becomes the OVERFLOW LINE signal This signal occurs after
290. st the Pages III 2 through 111 4 Table 3 1 Kravis EISE on LGENLLEVING parts Lf Vou Wave am refer to Figure 3 1 on Page 111 5 242 ASSEMBLY TIPS 16 scan Sections and IV in their entirety before you start to assemble your Sol PC kit 2d In assembling your POPC you will following 2 tegrated assembly test procedure Such a procedure is designed to progressively insure that individual circuits and sections in the Sol PC are operating correctly IT IS IMPORTANT THAT YOU FOLLOW THE OIEP BYI SIBEP INSTRUCTIONS JN THE ORDER GIVEN D Assembly steps and component installations are preceded by a set of parentheses Check off each installation and step as you complete them This will minimize the chances of omitting a step or component 4 When installing components make use of the assembly aids that are incorporated on the circuit boards and the assembly drawings These aids are designed to assist you in correctly installing the components a The circuit reference R3 10 and 020 for example for each component is silk screened on the PC boards near the location of its installation Both the circuit reference and value or nomenclature 1 5K and 74H00 for example for each component are included on the assembly drawings near the location dts XUsudcllatron 5 To simplify reading resistor values after installation install resistors so that
291. stall 03 2N4360 its location to the left of C67 205 with its flat side at the bottom Push straight down on transistor until it is stopped by the leads solder and trim CAUTION THe To STATIC SENSITIVE REFER TO CAUTION ON PAGE 8 Step 65 Install Q4 OS 2N2222 xm their locations above and to the lert ot 01068 For both transistors the emitter lead closest to tab on can is oriented toward the left and the base lead toward the right Push straight down on transistor until it is stopped by the leads solder and TEE 9 7 Sol PC SINGLE BOARD TERMINAL COMPUTER PROCESSOR TECHNOLOGY CORPORATION ne LET Step 66 Install diodes 013 and 014 184001 in their loca tions in the lower right corner of the board Position both diodes with their dark band cathode at the bottom Step 67 Install DIP reed relays in locations KL and K2 the right of U113 Be sure to install Kl and K2 with their end notch at the bottom pin 1 in lower right corner These relays are soldered to the board Refer to Loading DIP Devices in Appendix IV 69 Install the following IC s in the andicated loca tions Pay careful attention to the proper orientation NOTE Dots on the assembly drawing and PC board indicate the location of pin 1 of each IC LO NO TYPE 092 gt C 195 1023 C 099 40
292. stor connected to pin 12 of U38 Substitute a 15K 1 4 watt 5 resistor for R29 shown as l0K and a 270 ohm 1 4 watt 5 resistor for R21 shown as 470 ohm These parts are included in the kit Note in the schematics below that R29 is to be returned to 12 instead of 5 When R29 is installed put the 9 length of tubing over the right hand lead Clip this lead l longer than the tubing With the legend on the P C board in normal reading position hook this lead around the left hand lead of R 24 a 1 5K resistor and solder Inspect the solder joint and lead dress for shorts An assembly drawing detail of this modification is shown below Make the following changes in the manual before assembling Sol PC Step Page No Figure No if any Changes l X 17 Schematic Input Output Change R21 value to 270 ohm 2 X 17 Change R29 value to 15 3 X 17 Change R29 return to 12 V 4 X 3 Sol PC Rev E Assembly Change R21 value to 270 ohm 5 3 Change R29 value to 15K 6 3 Change R29 return to 12 V 7 III 3 SOl PC Parts List Add 1 270 ohm 1 4 watt 5 8 III 3 Change Qty 470 ohm 1 4 watt to 2 9 III 3 Change Qty 10K ohm to 31 10 3 Change Qty 15K ohm to 2 il III 33 Step 50 Change R21 270 ohms red violet brown 12 III 33 Change R29 15K ohms brown green orange 13 III 33 Under Step 50 instructions BEFORE 5V add See Change Notice 10 AV 12V 470 1 2 470 470 AF IER H2V R23 lt 23
293. t at the shield end CAUTION WHEN PREPARING AND INSTALLING SHIELD BE SURE BITS OF BRAID DO NOT FALL ONTO BOARD OUCH DEBRIS CAN CREATE HARD TO EIND SHORT CIRCULER D Insert inner conductor in mounting hole P1 left side of board solder and trim gt PROCESSOR TECHNOLOGY CORPORATION Sol PC SINGLE BOARD TERMINAL CoMPUTER SECTION III Shield gt ae 2 p m af Eu e 9 Inner Conductor Outer Insulation 124 Figure 3 4 Coaxial cable preparation Insert twisted shield in mounting hole P2 solder and trim Using the two large holes to the right of VR1 and VR2 tie cable to board with tie wrap see CAUTION below CAUTION AFTER INSTALLATION FINE BITS OF THE BRAID FROM THE SHIELD MAY WORK LOOSE AND FALL ONTO THE BOARD AND CREATE HARD TO FIND SHORT CIRCUITS TO PREVENT THIS COAT ALL EXPOSED BRAID WITH AN ADHESIVE AFTER SOL DERING AND TIEING USE AN ADHESIVE SUCH AS SILICONE CONTACT CEMENT OR FINGERNAIL POLISH DO NOT USE WATER BASE ADHESIVES Step 22 Install 6 position DIP switch in locat n left end of board Position Switch No 1 at the bottom Step 23 Install 20 pin header in location 94 video sion connector between U28 and U29 Position header so pin 1 is in the lower right corner An arrow on the con nector points to pin 1 Step 24 Install the following IC s in the indicated loca tions Pay careful attention to the proper orientation
294. t data when PWB is active INPUT Status output signal that indicates the address bus contains the address of an input device and the input data should be placed on the data bus when PDBIN is active Status output signal that indicates the data bus will be used to read memory data HALT ACKNOWLEDGE Status output signal that acknowledges a HALT instruction MEMORY READ _ CLOCK Inverted output of the 02 CLOCK GROUND 8 Volts Unregulated input to 5 volt regulators supplied by 501 20 power supply Negative unregulated voltage uupplied by Sol 20 power supply 16 Volts AVII 4 S 100 Bus Definitions continued PIN NUMBER SYMBOL NAME FUNCTION 53 SSWI SENSE SWITCH INPUT not used by Sol 54 EXT CLR EXTERNAL CLEAR not used by Sol PC electronics 55 RTC REAL TIME CLOCK not used by Sol PC electronics 56 STSTB STATUS STROBE not used by Sol 57 DIGI DATA INPUT GATE 1 When low forces PDBINS low and forces CPU input multiplexers to the DIO bus During CPU DBIN cycle disables CPU DIO bus drivers 28 FRDY FRONT PANEL READY When low disables MWRITE driver BE DEFINED 65 MREQ MEMORY REQUEST 2 80 signal not used by Sol PC electronics 66 REF REFRESH 2 80 signal not used by 501 electronics 67 PHANTOM PHANTOM DISABLE Output from CPU section used to disable RAM or ROM during power on initialization program execution 68 MWRITE MEMORY WRITE Indicates that the data present on the Data Out Bus is to be written
295. t easily into its two holes Insert the leads into the two holes and from the opposite side of the hoard poll the leads to bring the resistor body down to touch the hoard head the leads outward on the solder back side of the board so the resistors do not slip out of posis Rev C PROCESSOR TECHNOLOGY CORPORATION Sol PERSONALITY MODULE SECTION IV LOCATION VALUE COLOR CODE 100 ohms brown black brown R2 100 ohms brown black brown LOK brown black orange LOK brown black orange R5 LOK brown black orange R6 LOK brown black orange ATO Gn 210870 version Step 3 Install 1N5231B Zener Diodes in locations 21 and 22 if you have the 2708 1 version Form the leads as in Step 2 Insert the diodes so that the white band on the diode is in the position indicated by the legend Bend the leads outward to retain the diodes then solder and trim the leads Step 4 Install the following capacitors in the indica ted locations Take care to observe the proper value type and orientation for each installation On the dipped tantalum capacitors the lead is the one which is closest to the marking on the body of the capacitor Insert this lead in the hole marked on the PC board legend After inserting C5 remove it from the board before soldering to clear wax from the leads and holes After inserting all capacitors pull them close to th
296. t pin 3 which sets Q pin 1 high and 0 2 low to enable binary counter ULlLZ pain 15 Pin 1 is applied to the T input pin 9 of the lower U113 and the circuit remains in this state until one of two things occurs 1 a second transition pulse arrives before U112 reaches count 12 or 2 U112 reaches count 12 second transition pulse arrives before count 12 the bottom U113 stage is set and presents a 1 to the D input pin 9 OT lop his cs clocked Dy the SO output On pin 2 mue UTS as low to pin 12 of 0100 If a transition pulse does not arrive before count 12 the UllS stage o ubputs ud po Input pom 9 of OB Count 12 the C and D outputs of U112 go high to reset U113 by way of U98 at pin 4 As a result the U100 clock goes high as does pin 12 of AGES PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILI 0100 The output pin 12 of 0100 is inverted by 0109 and applied to the receive input pin 20 of the UART output on prn l or ULL whieh occurs at the actual rate of the incoming data is also used by the receive clock cir cuitry to reconstruct the receive clock from the data signal Received data undergoes serial to parallel conversion in the UART and is placed on the 1 8 data outputs of the UART when ROD pin 4 of the UART is low PORT_IN_FB active and onto INTO 7 Four status outputs from the UART can also
297. t side of fan closure plate one on each side of on off switch Position each block with terminal 1 at top and terminal 5 at bottom and attach each block to front side of fan closure plate with two 6 32 X 1 2binder or pan head screws Insert screws from back side of plate place block over screws on front side of plate put 6 lockwasher on each screw and Secure With 6 22 Nex nut Step 4 Install fuse holder in mounting hole located between the two rectangular cutouts in the fan closure plate Insert fuse holder from back side of plate poition large tab at top next to on off switch and secure holder to plate with the large lockwasher and nut supplied with holder Step 5 Install AC Power cord receptacle on fan closure plate Position receptacle on front side of fan closure plate over the rectangular cutout below fuse holder Orient receptacle with green lead at the botton and align the receptacle and closure plate mounting holes Insert two 6 32 x 1 2 binder or pan head screws from back side of plate through each mount ing hole put 6 lockwasher on each screw and secure with 6 32 hex nut Be sure receptacle is properly seated in cut out before tightening to avoid damage Step 6 Install female coaxial connector on fan closure plate Insert connector from front side of plate so that the threaded end projects through to the back side Ihen insert four 4 40 X 5 16 binder or pan head screws from back side of plate through the
298. ta Bus to pin 4 of SDI connector IN FF Permits CPU to read data byte entered from Sense Switches IN FE Places Video Display scroll timer and screen Status on Driuts 0 and l Bidirectional Data Bus BORT IN FD Switches Data Input Multiplexer to input data pins of PP connector and resets PP at end of a transfer to ready it for another IPORT IN FC Switches Data Input Multiplexer to Keyboard Date BUS IN FB Strobes received data in CDI UART to Internal data Bus IN FA Places PP keyboard and CDI UART status on Internal Data Bus IN F9 Strobes received data in SDI UART to Internal Data Bus IN Places SDI UART status on Internal Data Bus VLILI L7 PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION interrupt operation To prevent this SINTA is inverted in 058 to 1 disable U34 on pin 6 and 2 force pin 8 of NAND gate U23 high to dis able 055 sand USS on Dan This feature 15 provided to enable fu ture versions of Sol to operate with a vectored interrupt system 35522 Out our Refer to the Input Output Schematic In Section X Page 17 This section in the Sol has five functional circuits 1 Parallel I O Logic 2 Sense Switch Logic 3 Keyboard Flag Logic 4 SDI UART and 5 Baud Rate Generator The PP uses U95 and 96 4 bit D type registers and their re lated logic
299. te assembly Coaxial Aluminum heat ood ood 20 SOT PO 001 20 cable preparation power power power power sink installation supply subchassis assembly supply subchassis assembly connector and voltage measurements connector and voltage measurements Identification of components Clock circuit waveforms 5 Test probe for Steps 168 25B Coaxial Display Bending selected pins 042 cable preparation section timing waveforms d 39 and T3 014 through U21 socket jumpers Display circuits test pattern CPU Functional Test No CPU Functional Test No Personality module bracket guide RL through R4 Handle bracket 1 display 2 display installation installation 5014104 5 samstallartaon Types of screws used in Sol cabinet chassis assembly Brackets used in Sol cabinet chassis assembly Sol 20 with covers removed Sol 20 with covers removed 501 coaxial cable connector assembly Backplane board Backplane board Sol BPB installation Sol BPB installation Protective foot pad installation Connecting the basic Sol system 501 control switch settings for terminal mode Location Of positioning adjustments 1 and VR2 PAGE LS PLSS Leer LLIS Lo 8215 III TDI 1421 2 21 III 24 119525 13155354 VI 4 VI 4 Med Viel 1 14 Vai ASA VEL 7
300. ted outputs These outputs and their functions are defined in Table 8 1 U36 is enabled to decode when PDBIN and SINP are active that is during an input operation U35 is enabled when SOUT and PWR are active that is during an output operation INT_SEL on pin 8 of inverter 083 15 the remaining signal gen erated by the Input Port Decoder circuit This signal 15 active when either input port F8 9 FA or FB is decoded by U36 Both the address page and input output decoders can be dis abled by SINTA S 100 Bus pin 96 when the AE to AC and AB to AD jumpers are installed SINTA is active high when the CPU is re sponding to an interrupt Should an external device issue addresses during this time any memory response would interfere with the PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SECT LON LII Table 8 1 Port Decoder 035 U36 Outputs and Their Functions OUT FE Loads starting row address and first display line position information from Bidirectional Data Bus into Video Display scroll Circuit IPORT OUT FD Clocks data from Bidirectional Data Bus to output data pins of PP connector IPORT OUT FB Loads data from Bidirectional Data Bus into Cassette Data UART PORT OUT FA Clocks PP and CDI control bits from Bidirectional Data Bus IPORT OUT F9 Loads data from Bidirectional Data Bus into SDI UART PORT OUT F8 Clocks RTS request to send from bit 4 of Bidirectional Da
301. tep 11 Install the following resistors in the indicated locations Bend leads to fit distance between mounting holes insert leads pull down snug to board solder and LE HU LOCATION VALUE ohms COLOR CODE R1 Palle 3 watt none R2 330 5 watt orange orange brown R3 10 K brown black orange RA 1 0 K R5 1 brown black red R6 68 blue gray black 10 K brown black orange R8 1 K brown black red R9 56 K green blue orange R10 10 K brown black orange R11 1690 bronw blue white brown R12 4020 yellow black red brown step 12 Install U2 1458 in its location between C2 and C3 U2 1S positioned with pin 1 in the lower left hand corner and soldered into place See Loading DIP Devices in Appendix IV Step 13 Install diodes 101 1N5231B D2 1N4148 and D4 1N4001 Bend leads to fit distance between mounting holes insert leads pull down snug to board solder and trim BE SURE to position Dl with its cathode dark band to the left D2 and D3 with their cathode at the bottom and D4 with its cathode at the top step 14 Install the following capacitors in the indicated Take care to observe the proper value type and orientation if applicable for each installation Bend leads outward on solder back side of board solder and Crim See NOTE on Page 11 11 Tp PROCESSOR TECHNOLOGY CORPORATION ool POWER SUPPLY SECTION IT Rev B Um NOTE Disc capacitor leads are usu
302. th a nominal bandwidth of 7 MHz It can consequently be used to drive any standard video monitor A monochrome TV converted for video input can also be used See Appendix VI Included on the card are 1024 words of static low power sys tem RAM capable of full speed operation and a plug in personality module which contains the software control program Three personality modules are available for Sol CONSOL allows simple terminal operations plus direct control of the basic computer functions for entering or examining data in any memory location or executing a program stored at a known location in memory SOLED allows advanced terminal operations with CONSOL plus screen file and cassette tape editing transmission operations SOLOS allows full stand alone terminal computer operation 1 2222 Receiving Inspection When your kit arrives examine the shipping container for Signs of possible damage to the contents during transit Then in spect the contents for damage We suggest you save the shipping materials for use in returning the kit to Processor Technology should it become necessary to do so If your Sol PC kit is damaged please write us at once describing the condition so that we can take appropriate action 13233 Warranty Information In brief parts which fail because of defects in materials or workmanship are replaced at no charge for 3 months for kits and one year for assembled products following the date
303. the default I O pseudo ports see below The address Specified must be between 0200 and F400 Remember however that CUTER occupies 2K of memory and uses 1K of RAM beyond Es Ba Make sure that the CUTER tape is rewound and placed into the proper cassette machine The CUTER bootstrap will activate the motor control for tape unit one If your cassette machine motor control is attached as tape unit one you may now place the machine into PLAY mode F Execute location zero the bootstrap This can be accomplished by allowing a Reset to specify an address of Zero At this time be certain that the cassette machine is in PLAY mode and is activated When completed the CUTER loader program will HALT This 1s not an error condition When completed the motor control will also be turned off 24 UE LOADING amp EXECUTING CUTER cont Applicable to CUTER only Hs Via sense switches select the default I O pseudo ports as follows ED d JE x BE 7 654 Ou 0 Where X XXX t matter p which pseudo port from 3 1090 17 binary 15 to be the default input pseudo port pseudo port trom 0 3 00515 binary 15 to be the default Output pseudo port NO LE Whenever CUTER does a full system reset begins execution at its beginning memory address the sense switches will be accessed to determine the default I O pseudo ports L5 If either Input or Output default is to be pseu
304. the color codes or imprints read from left to right and top to bottom as appropriate boards oriented as defined in Paragraph 349 Page 6 Unless specified otherwise install components especially disc capacitors as close as possible to the boards 7 Should you encounter any problem during assembly call on us for help if needed M E PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL COMPUTER SECTION LII Table 3 1 SOl PC Parts Last INTEGRATED CTRCUITS 1 AM0026 DMO026 0104 1 74504 092 1 4126 039 2 7406 057 87 1 8794 058 2 741510 047 61 5 8197 067 68 77 80 81 741920 4023 59 83 2 1458CP or 1558CP 056 108 1 741586 074 1 1489 038 2 56011 051 69 Veg oq 1 MCM6574 or MCM6575 U25 WE o CUL dS 3 7415138 U34 35 36 urb DLE 3 019 30 52 1 4019 0111 1 74166 041 en URR 2 Fats 005 90 1 4027 0101 1 74175 097 3 4029 01 11 84 9 7415175 or 2515175 1 4030 099 1254220 011 42 080 58 166 E ds DAR MUN 4 7415253 065 66 78 79 7 7415367 E 5 8080 8080 9080 0105 XE 8836 or 8 380 046 USES 16 91102 or 2102L1PC 2 41802 or 91802 053 60 05e 2225 4 741504 024 45 49 54 i qU62 TRANSISTORS DIODES 2 2N2222 04 amp 05 9 1 4148 1 914 D1 D3 10 2 2N2907 2N3460 01 amp Q2 1 Gener Diode XDILT 1
305. the following steps Step 1 In Table 3 1 Page III 3 increase quantity of 47 ohm resistor from 2 to 3 reduce quantity of 470 ohm 1 4 watt resistor from 2 to 1 and add one 4 7K ohm 1 4 watt 5 resistor Step 2 In Step 50 Page III 33 change R27 value from 470 ohms to 4 7K ohms color code yellow violet red Step 3 Complete Steps 50 through 58 in Section III Step 4 Install R160 47 ohm resistor color code yellow violet black as follows Wrap one R160 lead around pin 1 of U39 4N26 and the other around the cathode lead banded end of D3 1N4148 dressing the leads as shown in Figure A Solder both R160 leads in place and trim excess lead lengths Inspect for possible shorts or solder bridges es pecially between pins 1 and 2 of U39 On the back solder side of the board the trace that connects pin 1 of U39 to the cathode lead of D3 must be cut Using an Xacto knife or a razor blade make two cuts approximately 1 8 apart cutting across the trace down to the epoxy base Insert blade tip beneath the cut section and gently work it away from the board Be sure the break is free of solder 731011 2 78 Page 1 of 2 Ref ECN 410253 Step 5 On Drawing X 17 in Section X change value of R27 from 470 ohms to 4 7K ohms and add R160 47 ohm resistor between pin 1 of U39 and the cathodes of D3 and D4 Refer to Figure B Step 6 Go on to Step 59 in Section III J
306. the screen is increased The Video Display Generator section may be modified f or the 50 Hz standard by following the additional steps below The effect of the modification is to increase the modulus of the counter U62 to eight during VDISP This results in four extra character lines 52 scan lines between the bottom and top of the display area for a total of 312 scan lines per field and 624 scan lines per frame Ihe field rate should be close enough to 50 Hz to reduce any swim effects to less than 0 1 Hz Some difficulty may be encountered in obtaining centering of the display within the frame This is because the stand off time to VSYNC from the bottom of the display is unchanged from the 60 Hz standard If objectionable increase the value of resistor RIOO which 15 in series with the VPOS CON EOL To convert for 50 Hz perform these additional steps Locate U62 on the component side legend Find pin 5 or this IC the component front side of the board Cut the V shaped trace connecting pin 5 to the near by pad designated AF using a sharp exacto blade or scribe so that there is no continuity between these pads Bend a small piece of bare wire such as resistor clipping into a loop to form a jumper between pad AF and the adjacent pad AG Insert the jumper pull close to the board solder and trim the leads If this modification is made change the schematic X 18 to show that pin 5 of 06
307. the screen with these four keys Tae BASIC OPERATIONS Switching From Terminal To Command Mode switch from terminal to command mode simply press the MODE SELECT key Sol enters the command mode issues a prompt character gt and waits for a command input pes owitching From Command To Terminal Mode To switch from command to terminal mode press UPPER CASE TERM and RETURN in that order Sol enters the terminal mode and all keyboard data will be sent to the SDI output and ail data received including looped back data will appear on the screen TEOR Entering Commands In The Command Mode The various commands for CONSOL and SOLOS are described in Section IX of this manual and the SOLOS Users Manual respectively You can place more than one command on the screen For each command use the arrowed cursor control keys to position the cursor at the start of a new line and begin the new command line with a prompt character gt Js A command is executed when you press the RETURN key and all characters on the line to the left of the cursor are interpreted as the command This means that if more than one command line is on the Screen you can execute any one of them as follows position the cursor with the arrowed cursor control keys to the right of the desired command and press RETURN Should you make a mistake when entering a command there are two ways Lo correct rt Paragraph 7 8 3 continued on Page VII 26
308. to leave Sol through the SDI UART enters the UART its 1 6 inputs from the Bidirectional Data Bus when TBRL pin 23 is low that is when PORT OUT F9 goes active Circuitry within the UART serializes the input data which is in parallel form and outputs it on pin 25 at a rate determined by the clock on pin 40 Ihe binary states at pin 25 are low for a zero and high for a one Assuming eol is not ain local operation Line The output on pin 25 of the is applied to pins 2 and 11 of 41 via two gates in 055 and the other half of 056 0 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION MILI Data that enters Sol through the SDI7UART on pins 35 22 or 22 Of Jl 15 input to the 501 on prn 20 by way of U35 an inverting level converter that converts data levels of up to 25 volts to TTL levels Note that current loop data on prn 12 Or l2 Of Jl asi farst rectified before it is applied to U38 The UART converts this serial data 1070 parallel form and outputs it on ROL thro gh ROS pans 12 through 5 respectively to the Internal Data Bus when ROD pin 4 is low that is when IN F9 goes active The receive transmit clock for the SDI UART is supplied by the Baud Rate Generator 084 085 U86 and their associated circui try U85 is a phase locked loop U86 is a 7 stage binary counter and U84 is connected as a divide by 11 counter The 1200 Hz refer ence signal applied to
309. tor will help you follow operation of the display section The monitor screen can be thought of as a large matrix of small light elements or dots that can be turned on and off this context the overall video presentation consists of light and dark dots VLII 22 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECTION VILI In the Sol the display format is 64 characters maximum per character row with a maximum of 16 rows per frame page Thus up to 1024 characters can be displayed per page A 9x13 columns by lines dot area or character position 15 alloted on the monitor screen for each displayed character see Figures 8 2 and 8 3 on Page VIII 24 Consequently each character row consisting of sixty four 9 x 13 dot areas requires 13 horizontal scan lines To provide spacing between both characters and rows only 12 dot lines and seven dot columns within the 9 x 13 matrix are used for character display Only nine of the available 12 dot lines however are used for any given character Let s take a closer look at how the 9 x 13 dot matrix is used The first seven dot columns are available for all character displays the last two are used to provide a space between characters Ihe first dot line in a character row is always blank to provide a space between character rows As shown in Figure 8 2 the second through tenth dot lines are available for all upper case capital and con trol characters all symbol an
310. tputs are applied to the appropriate memories and also provide the MEM SEL signal on pin 6 of one section in U23 This section is actually a 4 input NAND gate which is functionally the same as a 4 input NOR gate Note that the 922 logic input with ADRI4 and 15 is also con nected to PHANTOM When this signal is active low the output on pins 3 and 11 will be low to disable U34 when ADR12 15 represent a C If Page 0 is addressed however pins 3 and 11 of U22 are high and this coupled with lows on ADR10 13 are decoded by U34 as an active output on pin 11 The ROM will consequently respond to ad dresses in Page 0 and CO hex as long as PHANTOM is active MEE Do PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION SBC TION VILLI The other two enables 034 G2A and G2B are connected to SINP and SOUT These two status signals indicate an input or output operation during the CPU cycle U34 15 therefore disabled during these operations SINP and SOUT are also fed to pins 5 and 6 of NOR gate 053 which detects an input or output operation Its output is inverted by U54 and applied to pin 9 of another 053 NOR gate The other input pin 8 to U53 is MEM SEL So during a memory reference input oper ation or output operation pin 10 of U53 is active to enable the PRDY driver U71 The low on pin 10 of U53 is also clocked by 2 as a Rion prn Jor awd kh Ilsp rtlop that connected as D Tlip flop Note
311. tween the Sol T2 transformer and the keyboard bracket These Screws go into inserts in the wood side panel See the photo below for assembly details 5 Place the new bucking transformer into position over the two holes from which the two 8 32 screws were removed with the two black primary leads down and the three secondary leads up Reinstall the two screws and tighten 6 Locate the 6 sheet metal screw in front of the MDA 980 1 bridge rectifier from the photograph Remove the screw from the bottom of the Sol chassis and insert the 6 32 by 5 from the modification parts in its place 7 Place the new commoning block over the screw and secure with the 46 lockwasher and 6 32 nut 8 Remove the fan closure plate designated part 1 in drawing X 1 from the chassis as follows Remove one screw from the bottom center of the plate which holds the plate to the rear of the chassis Remove two additional screws which go through the expansion back chassis into the lip of the fan closure plate Lift the plate out vertically by rocking back and forth it may be a tight fit 9 Examine the cabling within the power supply Two new wires must pass through this cabling from the area of the new trans former to the two existing commoning blocks beside the fan Cut tywraps as necessary to accomodate the new wires 10 Remove the black lead which is inserted into the number 2 position of the commoning block which is nearest the fan CN 9 page 2
312. two clock signals 1 on 6 1091 and 2 On pin The ability to select the frequency and pulse width for 1 and 02 permits the use of either the 8080A 8080A 1 or 8080A 2 CPU for U105 The A version is the slowest speed unit the A 2 has an intermediate speed and the 1 is the fastest Let s now see how the pulse width of 01 and 02 are determined 1 on pin 6 of NAND gate U91 is low only when its two inputs are high and this happens only when there is 1 in the second and fourth stages of U90 This occurs during the time between the fourth and sixth fundamental clocks for 2 04 MHz operation the fourth and fifth clocks for 2 38 MHz and 2 86 MHz Keeping in mind that the fundamental clock period is 70 nsec it is readily seen that the low frequency pulse train on pin 6 of U91 has a pulse width of 140 nsec and the two higher frequency pulse trains have a pulse width of 70 nsec Refer to Figure 8 1 on Page VIII 11 NEL Ab PROCESSOR TECHNOLOGY CORPORATION Sol THEORY OF OPERATION TION VILI The A to B jumper is installed when the 8080A or 8080A 1 CPU 1s used in the Sol Note that the output 02 on pin 11 of NAND gate 091 is low only when the output on pin 3 of NOR gate 091 is high This section in 091 is actually a two input NAND gate which is func tionally the same as a two input NOR gate Pin 3 of 091 with the A to B jumper in is high when either the second B or third C U9
313. uit Board Check Visually check circuit board for broken traces shorts solder bridges between traces and similar defects Check to Insure that the 5 volt bus F12 volt bus and 12 volt bus are not shorted to each other or to ground Using an ohmmenter make the following mea surements refer to personality module assembly drawing OQQUIOD X C ho Bus Teste On Ul Measure 225 ground and pin 24 5 volts There should be HO COME INUL ys 5 volt Bus Test On Ul U2 measure between pun 12 ground and Pin 2L o Volto WI should NO Continuity 12 volt Bus Test Also on Ul measure between pin 12 ground and the bottom edge connector pin on the component side of the board marked Al Inter bus Test On Ul measure between pins 12 and 21 then between edge connector pin Al and pins 21 then 12 There should be no continuity in any of these measurements If visual inspection reveals any defect or you measure continuity in any of the preceding tests return the CTO Processor Technology replacement the board 15 not defective proceed to next paragraph 4 6 2 Assembly Test Procedure Refer to personality module assembly drawing 6 CAUTION THE MEMORY IC S USED ON THE PERSONALITY MODULE ARE MOS DEVICES THEY CAN BE CAUTION continued Page IV 3 Rev B TN PROCESSOR TECHNOLOGY CORPORATION Sol P
314. uit s noise immunity On valid key clo sures the PKD input is such as to decrease the Sense Circuit s threshold When valid key closures exist the Sequence Detector strobes data into the Output Latch The low order four bits to this latch are supplied by the Row Scanner the high order four bits are 22215520 PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON ALII supplied by the Encoding ROM with the data being determined by in puts from the Column Scanner and Function Latch Decoder This strobe Data Out also enables the Strobe Generator to output STROBE a 6 usec pulse that signals the Sol CPU that the Keyboard is ready to send data Eight bits of keyboard data KBDO through KBD7 are stored in the Output Latch KBDO through KBD6 represent the ASCII code for the character associated with the key closure or closures that initi ated the Data Out strobe from the Sequence Detector 7 is used only for special control characters MODE SELECT CLEAR and cur sor movement that are recognized by the Sol program The data on 7 is input to the Sol CPU when it issues PORT IN FC refer to Paragraph 8 5 2 on Page VIII 14 Ihe Repeat Counter is enabled when the REPEAT key and a char acter key in the Key Switch Capacitive Matrix are pressed at the same time When this occurs Key Out initiated by the character key clo Sure is active and the Repeat Counter generates a periodic Repeat Strobe
315. unt ing holes as you did for Ul and fasten U3 to heat sink and PC board using a 6 32 x 1 2Nylon screw lockwasher and Ht Insert screw from back solder side of board and drive nut finger tight Position heat sink Ul and U3 as needed to obtain cor rect fit and tighten the Ul and U3 mounting screws REMEMBER NO LEADS CAN CONTACT THE SINK Solder ai leads and trim if required pa 07 Install aluminum heat sink SCRI 01 and bridge rectifier EWBI Position aluminum heat sink see Figure 2 3 along top of PC board so that the three holes in one side of the Sink aligned with the SCRI QL and mounting holes in the PC board Bee Nut Y Lockwasher Compound and Mica Insulator gt Heat WILL LIAS LS LL ANS LL 4 Board Sink V ae back Side 4 40 X Screw Left end cross section view Figure 2 3 Aluminum heat sink installation 501 POWER PROCESSOR TECHNOLOGY CORPORATION SUPPLY SECTION 21 Poste OL 11241 woth component nomenclature up Jon heat sink so hole in 01 package is aligned with the holes in sink and PC board Observe how the leads of 01 must be bent down to fit the pads for 01 and bend them accord ingly Apply heat sink compound to 01 the heat sink and both sides of the rectangular mica insulator Place mica insulator between heat sink and 01 insert leads emitter lead to right and fasten 01 insulator
316. utwards until they are bent at a 45 angle to the surface of the card This will secure the device until it is soldered SOLDERING TIPS Use a low wattage iron 25 watts is good Larger irons run the risk of burning the printed circuit board Don t try to use a soldering gun they are too hot Use a small pointed tip and keep it clean Keep a damp piece of sponge by the iron and wipe the tip on it after each use Use 60 40 rosin core solder ONLY DO NOT use acid core sol der or externally applied fluxes Use the smallest diameter solder you can get NOTE DO NOT press the top of the iron on the pad or trace This will cause the trace to lift off of the board which will result in permanent damage In soldering wipe the tip apply a light coating of new solder to it and apply the tip to both parts of the joint that is both the component lead and the printed circuit pad Apply the solder against the lead and pad being heated but not directly to the tip of the iron Thus when the solder 1 PROCESSOR TECHNOLOGY CORPORATION Sol TERMINAL COMPUTER APPENDIX IV melts the rest of the joint will be hot enough for the solder to take i e form a capillary film 5 Apply solder for a second or two then remove the solder and keep the iron tip on the joint The rosin will bubble out Allow about three or four bubbles but don t keep the tip applied for more than ten seconds 6 Solder should follow the contours of th
317. ve OR gate in the absence of any blanking signals at the other two inputs to NOR gate 059 51 4 is open 074 in verts the video signal to produce a reverse black on white display Raw video on pin 8 of 074 is supplied to 15 of J4 Video out on pin 6 of inverter U87 is combined with COMP SYNC on pin 8 of another U87 inverter in a resistive mixer R80 R82 to meet EIA composite video signal standards and coupled to Pl for use by a video monitor This mixer has a 61 ohm output impedance Both Beginning Address Counter Ul and First Screen Position Counter 011 are enabled to advance their counts when 9 of J K flip flop U S ws low which about 0600 nsec rollowrng LINE that is after the Scan Counter 040 is loaded This of course occurs at the end of every scan line in the character row THe Soroll consists Of Ul Scoll Contre hacen U2 and Screen Position Control Latch 013 and their associated cir cuitry Ul and 011 are up and down counters respectively that are pre PROCESSOR TECHNOLOGY CORPORATION ool THEORY OF OPERATION SECT LON LII set to the outputs of latches U2 and 13 U2 latches the starting row address trom DIOU 3 and Ul3 the dara DIO4 7 gt wrinh being the strobe Data DIO4 7 specifies where the first line will be displayed Thus the number loaded into Ul is the address of the first dis
318. want one stop bit transmitted out of the SDI In the OFF position two stop bits are transmitted unless you have selected a five bit word length that case 1 5 stop bits are transmitted PROCESSOR TECHNOLOGY CORPORATION Sol OPERATING PROCEDURES VLI Table 7 2 Baud Rate Selection With Switch S3 BAUD RATE CONEIGURATLONS BAUD RATE SWITCH 53 CONFIGURATION gt on all others OFF _ 856 on all others OFF _ 83 7 ow all others OFF 856 ON all others OFF _ Zo 9530 ON all others ORF OFF S20 ON all others OEF xSet no more than one switch to ON at the same time Rate required by standard 8 level TTY 5 Teletype Machine Assumes K to M Jumper Sol PC 15 not installed With K M jumper in and L M trace on back side of Sol PC cut SDI operates at 9600 Baud when 53 8 is ON and all others OFF NOTE FOR REV D BOARDS With 65 7 ON anad others OFF Baud rate is either 2400 M jumper not installed or 4800 K M jumper in and trace on Dack side or Sol PC Out With 53 8 ON and all others OFF Baud rate 15 9600 5 Table 7 3 Word Length Selection With S4 2 amp 3 WORD LENGTH SWITCH SETTINGS Number of Bits 5 OET 6 y ON 8 ORT T511 I ull Halr Duplex E H Switch 54 6 Set this switch to ON if you want half duplex operation in the terminal mode
319. washer on the screws and drive each screw tightly into a 4 40 x tapped spacer Step 31 Position 501 PC board with top edge over the previously installed spacers Place 4 lockwashers on two 4 40 x 3 16 binder or pan head screws and drive screws t through Sol REG board nto spacers Step 32 Attach heat sink on Sol REG to power supply sub chassis as shown in drawing on Page X 2 At this point use only the two side screws which you used in Step 29 to thread the holes The middle screw will be installed later Place a 6 lockwasher on each screw before driving it through the sink into the subchassis Figure 2 4 shows an assembled 501 10 power supply subchassis Figure 2 4 501 10 power supply subchassis assembly Rear of subchassis at left 33 Install bridge rectifier FWB3 on power supply subchassis Step 35 Continued on Page 11 1065 Rev B dde PROCESSOR TECHNOLOGY CORPORATION Sol POWER SUPPLY EE Position FWB3 MDA980 1 on power supply subchassis as shown drawing on Page X 2 BE SURE NEGATIVE TERMINAL OF FWB3 is next to transformer Insert 6 32 x binder or pan head screw from bottom of subchassis place 6 lockwasher on screw and secure with 6 32 hex nut Step 34 Connect blue transformer wires to unmarked termi nals of FWB3 Step 35 Install Large 287 mounting ring for C9 54 000 ufd capacitor on side wall of power supply su
320. wer supply sub chassis as shown in Drawing X 9 Note that leg of T is closer to side wall of subchassis This leg is for mounting a power on indicator light not supplied In sert 6 x sheet metal screw from right side of side wall and drive into bracket Step 15 To gain access to the rear area of the power sup ply subchassis side wall remove the 6 x 5 16 sheet metal screw that attaches the fan closure plate to the subchassis You should not have to disconnect the transformer black wires or AC receptacle ground green wire leads since they have sufficient slack to permit moving the closure plate out of the way Set screw to one side for use in re installing the fan closure plate VI 9 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Figure 6 3 Figure 6 4 Rev A 501 20 with covers removed Front or keyboard is in foreground power supply is in right rear corner ex pansion chassis with 8KRA Memory installed is to left of power supply The vertical board just behind white connector on left is the backplane board 501 20 with covers removed Rear side of assembly is in foreground and Sol PC is just visible at lower right rear of assembly 8KRA Memory is installed in expansion chassis above Sol PC VI 10 PROCESSOR TECHNOLOGY CORPORATION Sol CABINET CHASSIS SECTION VI Step 16 Install power supply subchassis in main chassis as REV C shown in Drawing X 9 Pla
321. ws Step 15 continued on Page 111 14 PROCESSOR TECHNOLOGY CORPORATION 501 SINGLE BOARD TERMINAL COMPUTER SEC LON LLI CAUTION NEVER CONNECT POWER CABLE TO J10 WITH POWER SUPPLY ENERGIZED CAUTION 2 MAKE SURE POWER CABLE CONNECTOR MATES EXACTLY WITH JLO IHAI 15 PIN I IO PEN TL PIN OZ GIC ANY OTHER MATING RELATIONSHIP WILL BLOW THE DO S C LES NC ___ Suo J10 PIN NO POWER 0000000 Ground 2 He VLG 2 Amax 3andb I 5 3S00mAmagx B wA 5 46 24 4 12Vdc 5 l00mAmax J10 Top View 7 Ground NOTE Though not labeled on the connector J10 pins are designated 1 through 7 reading Lere won step 16 Check clock Circuits If you have an oscilloscope use part A of this step If you do not use part B Oscilloscope Check Using an oscilloscope check for the waveforms given Figure 3 2 on Page 111 15 at the indicated observation points and in the order given The waveforms shown in Figure 3 2 approximate actual waveforms If any waveforms are incorrect determine and correct the cause before pro ceeding with assembly NOTE Irregularities up to 1 volt are accept able on positive portions of waveforms Negative portions however should be relatively flat VolU onm Meter Check Using the test probe shown in Figure 3 3 on Page 111 16 set meter to DC volts and make the
322. y Step 50 Install the following resistors in the indicated locations Bend leads Co fit distance between mounting holes insert reads pull down snug to board solder and trim LOCATION VALUE ohms COLOR CODE 470 yellow violet brown R22 470 watt gt RAS 470 watt gt R24 brown green red RAS TO de brown black orange R26 10 K NN 470 yellow violet brown R28 I0 brown black orange R29 10 K NN R37 LLOR brown green red R39 15 E P gt R39 Sia 2124 green blue red RAO dec de brown green red R42 i R43 fs DK R44 d go S M R45 330 orange orange brown R46 5 OK green blue red R47 LO K brown black orange R48 10 K NN R49 214 brown green red R59 Leok M ROL Ls 2124 R62 Sie Ok green blue red R63 POR Y R64 330 orange orange brown R65 330 NN NN R66 330 W NN R67 330 NN NN R68 330 NN R69 330 W NN NN R70 330 NN 271 330 NN NN Step 50 continued on Page III 34 T4595 PROCESSOR TECHNOLOGY CORPORATION IM Sol PC SINGLE BOARD TERMINAL COMPUTER SECTION III LOCATION VALUE obms COLOR CODE R72 680 blue gray brown R73 680 B 680 R75 680 B 6 680 RII 680 RY Q 680 ER 680 R92 5 6K green blue red R93 brown green red R94 LUC MEE brown black orange R95 du brown green or

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