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Elpida: SDRAM Application Notes

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2. User s Manual E0124N10 59 60 CHAPTER 3 DESIGNING SDRAM CONTROLLER Table 3 1 summarizes Figures 3 5 and 3 6 Table 3 1 Select Signals of Each Operation Mode Operation Mode of SDRAM Refresh Read cycle Write cycle Refresh cycle Mode register set cycle e Read cycle Only read signal always becomes high Write cycle Only write signal always becomes high e Refresh cycle Refresh signal and write signal always become high Mode register set cycle Mode signal and write signal always become high User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 3 Timings between PCI Controller and SDRAM This section explains the timing between the PCI controller and SDRAM 3 3 1 Read cycle of SDRAM Burst read cycle with burst length 4 is used for read cycle Figure 3 7 Read Cycle between PCI Controller and SDRAM T1 T2 13 T4 T5 16 7 19 Tl T T3 FRAME T From bus Start of timing 1 1 AD From bus master ___ From bus master BE IRDY i 1 From bus master TRDY From target Insert Insert Insert Insert i DEVSEL all i I I
3. 63 Figure 3 10 Mode Register Set Cycle between PCI Controller and 64 Figure 3 11 Circuit Diagram and Timings of Select Signal Generation of Each Operation 66 Figure 3 12 Circuit Diagram and Timings of Basic Control Signal Generation 67 Figure 3 13 Circuit Diagram of Basic Select Signal 68 Figure 3 14 Timings of Basic Signal nennen nnne tnn 69 Figure 3 15 Circuit Diagram and Timings of DEVSEL Signal Generation 2 70 Figure 3 16 Circuit Diagram and Timings of TRDY Signal Generation 71 Figure 3 17 Circuit Diagram and Timings of CS Signal 71 Figure 3 18 Circuit Diagram and Timings of RAS Signal Generation 72 Figure 3 19 Circuit Diagram and Timings of CAS Signal Generation 2 72 Figure 3 20 Circuit Diagram and Timings of A11 Signal and A10 Signal 73 Figure 3 21 Timings of Row Column Address Signal Changing 2 74 Figure 3 22 Example of Address Signal Changing nennen 75 Figure 3 23 Circuit Diagram and Timings of WE Signal Generation seen 76 Figure 3 24 Exa
4. 1 DQ 4 4 1 1 The bus master inputs write command at 1 and declares output of data to memory An all bank precharge command CBR auto refresh command and an active command that indicates the next operation are input to SDRAM at T2 T4 and T2 respectively In this case the bus master outputs data but SDRAM does not accept the data For the reason refer to 3 2 2 State diagram of SDRAM controller One turn around cycle and one wait are inserted at T2 and T3 respectively Turn around cycle however is not essentially required in CBR auto refresh cycle This is because CBR auto refresh cycle is multiplexed with the write cycle This method has the advantage that the refresh cycle generation circuit can be simplified On the other hand it has the disadvantage that it takes time to control the refresh cycle because of the insertion of unnecessary waits In terms of the overall data transfer time including the bus master and SDRAM higher speed can be realized by not multiplexing CBR auto refresh cycle and write cycle because of less control over refresh cycle In this case however the method multiplexing CBR auto refresh cycle and write cycle is used to simplify the circuit rather than generating its own refresh cycle timings User s Manual E0124N10 63 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 3 4 Mode register set cycle of SDRA
5. 18 Figure 1 5 B rst Read Gycle iine ela ane Aes in qe c pee Re ode ee ee eagle Glens 19 Figure 1 6 Identical Read Cycle of Conventional DRAM and 5 20 Figure 1 7 Mode Register Set Command sssssessessseseeeeeenne nennen enne nnnm entere nnn entes s enne nnne nnns 22 Figure 1 8 Row Address Strobe and Bank Active Command sse nene 22 Figure 1 9 Precharge Command EEEE DER RARI RARE RR 23 Figure 1 10 Column Address Signal and Read 23 Figure 1 11 Column Address Signal and Write Command sse nennen nennen nnne 24 Figure 1 12 CBR Auto Refresh Command ssssssssseseseeeeeenenen renes enne nennen nene 24 Figure 1 13 Self Refresh Entry 0404440041 10 ener nnne nnn nnnm ennt 25 Figure 1 14 Burst Stop Command 2 te tbe petes ah ae 25 Figure 1 15 NOP Command Eee a eee ad e deter Lied ed i be ete 26 Figure 1 16 Initialization of 44 2 60444 nnns nnns enter innt sentes tenentes nnne 27 Figure 1 17 Writing Mode Register er RE RAM onte Br tetra 28 Fig
6. Sele DX OX 0b 7 1 1 1 1 1 WE 1 1 im POCO EE 1 cedi CLG Cid Liu The bus master inputs a write command at T1 and declares output of data to SDRAM An active command a write command a precharge command and an active command that indicates the next operation are input to SDRAM at T2 4 and T2 respectively A turn around cycle is inserted at T2 and a wait is inserted at T3 Although only bank A is accessed in Figure 3 8 bank B also can be accessed Although this circuit uses precharge auto precharge can also be used without affecting the operation 62 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 3 3 CBR auto refresh cycle of SDRAM CBR auto refresh cycle is used for refresh cycle and it is multiplexed with the timing of the write cycle Figure 3 9 CBR Auto Refresh Cycle between PCI Controller and SDRAM T1 T2 T3 T4 T5 T6 T7 T8 T2 CLK FRAME j D From bus master i AD Data Data Data Dat From bus master C BE From bus master L BE IRDY i i From bus master ee TRDY a eee 1 222 From target 12 Tum Insert DEVSEL From target 1 1 1 1 1 RASH cast 1 E
7. 1 177 178 3 CS signal In Figure 3 17 the CS signal is generated Because BBB signal is used as the CS signal unnecessary clocks are deleted by employing OR logic of the BBB signal and GGG signal Figure 3 17 Circuit Diagram and Timings of CS Signal Generation INPUT a 666 Vc 112 5 ns 150 0 ns 187 5 ns 37 5 ns 75 0 ns 1 Read cycle of SDRAM 9 1 118 11790 1 71 User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 4 RAS signal In Figure 3 18 the RAS signal is generated Because the CS signal is used as the RAS signal unnecessary clocks are deleted by employing OR logic of the CS signal and EEE signal Figure 3 18 Circuit Diagram and Timings of RAS Signal Generation INPUT Vcc INPUT OUTPUT pas Vcc 37 5 ns 75 0 ns 112 5 ns 150 0 ns 187 5 ns 1 1 Read cycle of SDRAM 1 1 1 1 179 110 172 173 174 175 0116 177 178 179 1 5 CAS signal In Figure 3 19 CAS signal is generated Because the CS signal is used as the CAS signal unnecessary clocks are deleted by employing OR logic of the CS signal and DDD signal Figure 3 19 Circuit Diagram and Timings of CAS Signal Generation INPUT Vcc INPUT OUTPUT cas Vcc 37 5 ns 75 0 ns 112 5 ns 150 0 ns Read cycle of SDRAM 1 1 1 1 1
8. I From target RASH Bank Bank Bank A A11 ERU 1 1 1 1 I 1 1 1 GS deu 3 1 I 1 Data Precharge 1 The bus master inputs read command at 1 waits data input from SDRAM An active command a read command a precharge command and an active command that indicates the next operation are input to SDRAM at T2 T4 T10 and 2 respectively A total of four waits are input at T2 T3 T4 and T5 Although only bank A is accessed in Figure 3 7 bank B also can be accessed Although this circuit uses precharge auto precharge can also be used without affecting the operation User s Manual E0124N10 61 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 3 2 Write cycle of SDRAM Burst write cycle with burst length 4 is used for write cycle as well as for read cycle Figure 3 8 Write Cycle between PCI Controller and SDRAM 11 T2 13 14 T5 16 7 T8 T From bus master AD Dat Dat DataN Dat From bus mastery Aout From bus master 7X IRDY From bus master TRDY From target 12 Tur Insert __ DEVSEL oe i i From target cx ee
9. oor oO FS lt lt lt ot SS Onis 0 90 0 0 0000070500 User s Manual E0124N10 postfixed to pin names and signal names indicates active low n Remarkln the diagram Figure 3 Timings of Logic Verification Result 2 1 387 1 275 us 1 3125 us 1 2375 us 825 0 ns 862 5 ns 900 0 ns 937 5 ns 975 0 ns 1 0125 us 1 05 1 0875 us 1 125 us 1 1625 us 787 5 ns APPENDIX A DIAGRAM AND TIMINGS OF ENTIRE CIRCUIT Name gt ad ond 5 S o A duvo E o o oO o 6666 cs lt B gt 8 gt on or Lg OS lt lt lt 22200 User s Manual E0124N10 91
10. forbankA forbankA i forbankA forbankA lt 1 gt lt 2 gt lt 3 gt To output the data in the different bank bank in this case from point 3 using the same control method as in Figure 1 19 input an active command for bank B at point lt 1 gt and input a read command for bank B at point lt 2 gt When controlling different row address signals different row address signals for bank A in this case the data cannot continuously be output The reason is if an active command for bank A with different row address signal at point lt 1 gt is input a read command for bank A cannot be input at point lt 2 gt As described earlier a precharge command is required before an active command is input at point lt 1 gt User s Manual E0124N10 31 CHAPTER 1 SYNCHRONOUS DRAM 1 4 2 Read command and auto precharge Figure 1 20 shows the case that the read cycle is controlled with auto precharge when CAS latency 2 CL 2 burst length 4 BL 4 Figure 1 20 Read Command and Auto Precharge CKE I RAS EE EN 3 10 I 1 1 1 I Auto DQM precharge p M M M ER CL 2 1 1 i I 1 1 ba wc gt n Active Readwith Active command auto command forbankA precharge i forbankA comma
11. I 1 L 1 1 1 I 1 mi i 1 1 1 f 1 1 1 1 1 1 1 1 Active Read Write Read command command i command command forbankA forbankA forbankA forbankA lt gt lt 2 gt lt 3 gt At point lt 2 gt write command is input The write command is input leaving one clock after the last data of the read cycle is output At point lt 1 gt DQ must be set to high impedance state for one clock period in order to avoid bus fight At point lt 3 gt a command that indicates the next operation read command for bank B in Figure 1 24 is input 36 User s Manual 0124 10 CHAPTER 1 SYNCHRONOUS DRAM When changing the bank from bank A to bank B in Figure 1 25 an active command is required between points lt 1 gt and lt 3 gt input of an active command is not required when the bank is not changed An active command for bank can be input trrp after the active command for bank A is input When inputting an active command for bank A at point lt 4 gt a precharge command for bank A is required at point lt 2 gt The other command inputs are the same as for read and write command for the same bank CLK CKE CS RAS CAS WE 11 10 DQM DQ Figure 1 25 Read amp Write Command 2 Active CL 2 1 Read Active command for bank A Precharge
12. eee ciae a Dii at edere DR 61 3 9 2 Write cycle ot SDRAM nir erem retenti dee Ce pact re apte etate dece 62 3 3 3 CBR auto refresh cycle of 0 222044 4 10 0 1 0 nnne nnne nnne rn rene nnne 63 3 3 4 Mode register set cycle of SDRAM 64 3 9 5 tet e rette Ate buste edt cute e ta dense 65 3 4 Examples of Connection Circuit between SDRAM and PCI Bus eese 66 3 41 Basic signals rue ient dd fl coat ptr m ad dett geo ees 66 3 4 2 Read cycle te ee t bo gei 70 3 4 3 Changing control signal noniine c erre dece ee diate Ex o eu a e VERTS 77 op Eun 2 a a a a A E Ea aA A a a aA 78 3 4 5 Refreshicycle EE E T ene 80 3 4 6 Mode register set 82 E aee cR D 84 APPENDIX A DIAGRAM AND TIMINGS OF ENTIRE 88 User s Manual 0124 10 7 LIST OF FIGURES 1 2 Figure No Title Page Figure 1 1 Types of High speed nnne nnne 13 Figure 1 2 Memory Bus Clock Each High speed DRAM Can Support 15 Figure 1 3 Higher speed SDRAM and EDO 16 Figure 1 4 Read Cycles of Conventional DRAM and
13. i D FLIP FLOPS NAND2 SENE 220 OUTPUT INPUT SCLRN 20 74157 OR IRDY gt om SEL t D FLIP FLOPS Bi 2 c OUTPUT 5 B2 OR2 AND2 OUTPUT B3 YA gt OR 4 D OUTPUT B4 GN NA MULTIPLEXER MULTIPLEXER OUTPUT SEL 1 Bi Voc 7474 ADD a2 Yi OR2 74157 B2 2 SEL 1 r 81 OUTPUT 4 2 dGN DFLIP FLOPS x7 MULTIPLEXER S Vec D FLIP FLOPS 4 B4 cMp MULTIPLEXER OUTPUT gt gt OUTPUT OUTPUT gt 7 OUTPUT D FLIP FLOPS gt D FLIP FLOPS ANB D OUTPUT OUTPUT gt OUTPUT gt OUTPUT gt OUTPUT OUTPUT gt In the diagram n postfixed to pin names and signal names indicates active low Memory Read Write FMS2 53 FMS4 AB FMS1 AAA DEVSEL WE RAS CAS CS TRDY EEE GGG HHH BBB A10 11 CCC DDD LINDYID dO V XIaNaddv Figure 2 Timings of Logic Verification Result 1 150 0 ns 187 5 ns 225 0 ns 262 5 ns 300 0 ns 337 5 ns 375 0 ns 412 5 ns 450 0 ns 487 5 ns 525 0 ns 562 5 ns 600 0 ns 637 5 ns 675 0 ns 712 5 ns 750 0 ns 112 5 ns APPENDIX A DIAGRAM AND TIMINGS OF ENTIRE CIRCUIT
14. than memory T1 T2 T4 5 T6 T7 T8 T9 10 1 T2 T4 T5 T6 T7 T8 T1 T2 T3 T4 T5 T6 T7 T8 6 T7 T8 T5 T8 T1 T2 T3 T4 gt 1 C BE2 C BE3 r Read gt Write Refresh r Refresh 69 User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 4 2 Read cycle The read cycle in the circuit example supports only the burst read cycle with burst length 4 1 DEVSEL signal In Figure 3 15 DEVSEL signal is generated The DEVSEL signal is generated by inverting AA signal The DEVSEL signal becomes low at the rising edge of the AAA signal only when memory signal is high and it becomes high when the FRAME signal and IRDY signal are both high Figure 3 15 Circuit Diagram and Timings of DEVSEL Signal Generation 37 5 ns 75 0 ns 112 5 ns 150 0 ns 187 5 ns Read cycle of SDRAM 1 1 1 1 3s gt DEVSEL 70 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 2 TRDY signal In Figure 3 16 the TRDY signal is generated The TRDY signal is generated by latching the OR logic signal of the DEVSEL signal and FFF signal at the rising edge of the DDD signal Figure 3 16 Circuit Diagram and Timings of TRDY Signal Generation INPUT Vcc INPUT OUTPUT Vcc gt 37 5 ns 75 0 ns 112 5 ns 150 0 ns Read Cycle of SDRAM m 9 172 173 4 175 4
15. 27 4 34 Setting of Mode registers ee 28 1 4 Operation Timing of See 30 141 Read command 2 30 1 4 2 Read command and auto precharge 32 1 4 3 Write command and 33 1 4 4 Write command and auto 35 1 4 5 Read command and write 36 1 4 6 Precautions for using access with burst length 1 38 1 4 7 Merits and demerits of auto 39 1 4 8 Temporary stop of clock during data transfer 40 1 4 9 Both bank ping pong Control 42 124 10 CBR auto aio an beri dee mese eee 43 CHAPTER 2 BUS M 44 ANESUIIDXRaeH pcc 44 PGI DUS hunt dei cct 44 2 1 2 Explanation Of Ire DE Lee E 45 2 1 3 Block diagram of PCI bus interface nennen nnne nnne nennen 46 2 1 4 Bus corimand en e tenia eee tee teste 47 2 1 5 Bus drive and turn around 48 2 2 Data Transfer iesu rnnt ep ae na Fi ce LASER Uc uS EY ERR aa RR oa 49 2 2 1 Outline of dat
16. 48 Figure 2 3 Basic Cycle idee ee iai E eee ig etie e ees EC EE ied 49 Figure 2 4 End of Transfer Controlled with Bus 50 Figure 2 5 End of Transfer Controlled with 50 Figure 2 6 Access Latency anie tee eaa aped bae ote deiode Regist givin 51 Figure 2 7 Random Access Cycle iet me tt es rcge aret ep bane eer vete aate ue 52 Figure 2 8 Burst Read Cycle and Burst Write 53 8 User s Manual E0124N10 LIST OF FIGURES 2 2 Figure No Title Page Figure 3 1 Block Diagram of PCI Interface 55 Figure 3 2 Block Diagram of SDRAM 56 Figure 3 3 State Diagram of SDRAM Controller sssssssseseeeeeneenn eene nennen nnn ennt 57 Figure 3 4 Example of Memory Space of PCI eene 58 Figure 3 5 Select Signals of Refresh and Mode Register 59 Figure 3 6 Select Signals of Read Write neret nnet nnne nnne nnns nnne nnns 59 Figure 3 7 Read Cycle between PCI Controller and 61 Figure 3 8 Write Cycle between PCI Controller and 5 62 Figure 3 9 CBR Auto Refresh Cycle between PCI Controller and
17. Active Write 1 command command command command 1 for bank for bank for bank A for bank A lt gt 2 lt 3 gt User s Manual 0124 10 lt 4 gt lt 5 gt Precharge command for bank B 37 CHAPTER 1 SYNCHRONOUS DRAM 1 4 6 Precautions for using access with burst length 1 Figure 1 26 shows the case that the read cycle is controlled with auto precharge when CAS latency 2 CL 2 burst length 1 BL 1 Figure 1 26 Read Command and Auto Precharge 1 1 tro i CS ws puc WER Bank A Bank A A11 A10 NE ae DQM precharge 1 1 CL 2 1 1 1 1 gt 1 1 1 i Read with i Active 1 auto Active command precharge command forbankA command forbankA for bank A lt 1 gt lt 2 gt 9 4 At point 1 an active command is input If a read command is input at point 2 data is output at point 4 Since burst length is 1 a precharge command is automatically input at point 3 In this case the standard value of tras is not observed so that proper operation is not performed Therefore in Figure 1 26 the control tha
18. signal is the inverted signal of CCC signal EEE signal 1 2 frequency division signal of CCC signal 1 8 frequency division of CLK FFF signal is the inverted signal of EEE signal GGG signal Becomes low when FRAMEZ signal and AA signal are both low When FRAME signal and AA signal are both high GGG signal changes at the rising edge of DDD signal HHH signal Signal that employs AND logic of DDD signal and GGG signal Figure 3 12 Circuit Diagram and Timings of Basic Control Signal Generation INPUT OUTPUT Voc 1 CLK m OUTPUT Voc gt OUTPUT gt OUTPUT D FLIP FLOPS OUTPUT OUTPUT gt gt OUTPUT D FLIP FLOPS OUTPUT OUTPUT gt A IRDY INPUT Memory gt INPUT Voc 37 5 ns R ad cy le ITQ Ti T2 T3 01141 T5 T6 T7 T8 T9 T4 oor User s Manual 0124 10 67 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 Command select signal In Figure 3 13 the basic select signal is generated This is the signal to sort commands of various operation modes This is summarized as follows Signal Name Original Signal Logic Verification Result Signal to latch read signal Low only in cycles other than read cycle and memory Signal to latch the
19. DirectRDRAM SynchLink DRAM etc 1 2 3 FPM DRAM Fast Page Mode DRAM FPM DRAM is a DRAM provided with the page mode of higher speed than that of the conventional DRAM Although FPM DRAM executes data input output only once during one cycle of RAS in random access it can continuously execute data input output during one cycle of RAS in the page mode In the page mode the access time of the second data and thereafter becomes faster Other types of DRAM such as NB Nibble Mode and SC Static Column Mode that realize higher speed using specifications different from those of FPM DRAM also exist In 1995 however FPM DRAM represented approximately 90 of all DRAM shipments EDO DRAM Extended Data Out DRAM EDO DRAM is a still faster version of FPM DRAM If the data output read cycle of DRAM is made higher speed the data output time becomes shorter Since EDO DRAM is provided with extended output functions the data output time does not become short even in higher speed Thus wider range for the timing can be allowed in the data output side and as a result a speed higher than that of FPM DRAM can be realized In addition since EDO DRAM and FPM DRAM are compatible DRAM that have packages with the same pin configuration EDO DRAM can easily replace FPM DRAM In the middle of 1996 EDO DRAM represented approximately 50 of all the DRAM shipment SDRAM Synchronous DRAM Specifications different from those of the
20. for bank A lt gt lt 2 gt lt 3 gt The basic controls in write cycle are the same as in read cycle The differences are at points lt 2 gt and lt 3 gt In write cycle data can be input immediately after write command is input at point 2 trcp after point lt 1 gt because all CL 0 At point 3 whichever later of tras after point 1 or the point after the end of data input a precharge command is input User s Manual E0124N10 33 CHAPTER 1 SYNCHRONOUS DRAM To continuously control data with the same row address in the same bank the next data can be input from point lt 3 gt if a read command is input at point lt 3 gt so that the data can continuously be input Figure 1 22 Write Command and Precharge 2 1 nd cepi a DQM i Xxooeeee 1 1 1 1 1 1 1 1 1 Active Write Write Precharge command command command i command forbankA forbankA forbankA i forbankA i lt 1 gt lt 2 gt To input the data in the different bank from point lt 2 gt using the same control method as in Figure 1 22 input active command for bank B at point lt 1 gt 34 User s Manual 0124 10 CHAPTER 1 SYNCHRONOUS DRAM 1 4 4 Write command and auto precharge Figure 1 23 shows the case that the write cyc
21. of the bus to the bus master that has requested the use of the bus User s Manual 0124 10 45 CHAPTER 2 BUS 2 1 3 Block diagram of PCI bus interface There are two types of signals for the control signals of the PCI bus output signal and input signal Taking the case of output signal whether the bus master or the target outputs the signal must be clarified In the same way whether the bus master or the target inputs signal must be clarified in the case of input signal Figure 2 1 Bus Master and Target Bus master Cache memory Local bus Memory controller Local bus PCI bridge PCI board PCI ISA bridge The bus means the PCI bus in this case The bus master arbitrates with devices other than the one using the bus and regularly controls the bus Any device or unit can be the bus master as long as it is capable of arbitrating and controlling the bus In Figure 2 1 major bus master is a bridge etc card can also be the bus master if it is capable of arbitrating with each bridge and regularly controlling the bus The target is a device or unit used by the bus master and it starts operation when directed from the bus master 46 User s Manual E0124N10 2 1 4 Bus command Bus command sets in advance the destination of data transfer in address phase CHAPTER 2 BUS different controls depending on the combination of the four logic levels of C BE C BE3 C BE2 Table 2 2 Bus Command C
22. 1 1 1 1 72 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 6 11 signal and 10 signal Figure 3 20 illustrates the circuit to generate the A11 signal and A10 signal The A11 signal is the address signal of SDRAM to control banks The A10 signal is the address signal of SDRAM to control precharge operations The A11 signal is generated at the rising edge of the AAA signal by latching ADD lower address signal output from the PCI bus controller Because the read write operation in the circuit example uses only precharge the A10 signal is always fixed to low Figure 3 20 Circuit Diagram and Timings of A11 Signal and A10 Signal Generation OUTPUT A10 OUTPUT 11 D FLIP FLOPS m Read of SDRAM tina T9 T10 Ti T2 T T4 T5 T6 T7 T8 9 Ti 12 T3 T4 T5 16 T7 Te T9 1 Read cycle of SDRAM 37 5 ns 75 0 ns 112 5 ns 150 1 Ons 187 5 ns 225 0 ns 262 5 ns 1 User s Manual 0124 10 73 7 74 CHAPTER 3 DESIGNING SDRAM CONTROLLER Changing row column address signal In Figure 3 21 the A B signal is generated This signal is used for changing row address signal and column address signal of SDRAM The A B signal must be changed between the point where row address signal is latched T2 and the point where column address signal is latched T4 The A B signal uses the FFF signal as is Figure 3 21 Timings of Row Column Address Sig
23. PCI bus a versatile high speed bus that does not depend on the performance or type of CPU PCI bus rapidly penetrated the market along with the popularization of Pentium processor The PCI bus is currently the mainstream of high speed busses 44 User s Manual E0124N10 2 1 2 Explanation of pins CHAPTER 2 BUS The following explains typical pins of the PCI bus The descriptions here do not cover all the pins of the PCI bus The bus master arbitrates with other devices and regularly performs controls The target is a device or unit to perform the operation that the bus master directed Table 2 1 Signal Table Signal Description CLK signal Clock Signal to be input to the target This signal is referenced on the bus 33 MHz and 66 MHz are defined in version 2 0 and 2 1 of bus respectively RST Reset Signal to be input to the target This signal initializes all the target RST low from the bus master initializes all the target AD Address signal and data Multiplexed signal of address signal and data Address is a signal to be output to the target and data is a signal input output to from the target Address signal is processed first address phase and data is processed with time difference data phase C BE 3 0 Bus command and byte enable Signal to be input to the target This is a multiplexed signal for bus command and byte enable It controls bus command and byte enable in ad
24. RDRAM is higher than that of any other DRAM Although current RDRAM synchronizes with 400 MHz clock data can be processed at two points the rising edge and the falling edge of a single clock dual edge system as a result equivalent to synchronization with 800 MHz clock is achieved If 400 MHz clock is needed for the memory bus clock of a system the use of RDRAM is effective In this case the trunk of a system can be configured by adopting ASIC and DRAM of the Rambus specification since ASIC with the Rambus specification has already been shipped from semiconductor companies User s Manual E0124N10 15 CHAPTER 1 SYNCHRONOUS DRAM 1 2 Difference between Conventional DRAM and SDRAM 1 2 1 What is SDRAM SDRAM is a type of DRAM which operates in synchronization with input clock This system has been developed from the idea that the synchronization of the system clock and the operating clock of a memory will make it easier to control each other Figure 1 3 Higher speed SDRAM and EDO DRAM Burst cycle time ns Random access time ns Figure 1 3 shows each access time of SDRAM and EDO DRAM respectively Comparing the access time of SDRAM with that of the conventional DRAM the burst access time of SDRAM is much faster than that of the conventional DRAM while there is not much difference in the random access time Since SDRAM and EDO RAM have almost identical basic configuration inside the memory there is no difference in basic access
25. and EDO 20 Table 1 4 Correspondence of Control Signals of Conventional DRAM and SDRAM 21 1 5 eee sin ee ieee 21 e 29 Table 1 7 Setting of CASH Latency a 29 Table 1 8 Merits and Demerits of Each Type of emere 39 251 eme ee A Ee e EEG ee det 45 2 2 ii E RE NM ERREUR EUR LOL eO dad ede 47 Table 3 1 Select Signals of Each Operation 60 10 User s Manual E0124N10 LIST OF TABLES CHAPTER 1 SYNCHRONOUS DRAM This chapter briefly explains major features of synchronous DRAM SDRAM focusing on the differences between synchronous DRAM and the conventional DRAM and methods commonly used for controlling SDRAM to design SDRAM controllers For the details of control methods of the conventional DRAM and SDRAM refer to the User s Manual of each product 1 1 High speed RAM 1 1 1 Types of high speed RAM RAM is roughly divided into two types DRAM Dynamic RAM and SRAM Static RAM The high speed DRAM generally includes EDO DRAM SDRAM and RDRAM The next generation high speed DRAM includes DDR SDRAM
26. and HHH signal and the CS signal CAS signal OR logic of the CS signal and FFF signal WE signal OR logic of the GGG signal and HHH signal Figure 3 27 Circuit Diagram of CBR Auto Refresh Cycle Control Generation INPUT Cc gt INPUT Vcc INPUT INPUT OUTPUT gt INPUT gt WE gt INPUT gt GND MULTIPLEXER Lj 59 901 n RAS OUTPUT CAS User s Manual 0124 10 OUTPUT cs CHAPTER 3 DESIGNING SDRAM CONTROLLER Figure 3 28 Timings of CBR Auto Refresh Cycle Control Refresh cycle write cycle Refresh cycle write cycle of SDRAM To Ti 1731 CTS 1 6 7 178 ITH T2 1751 T7 ITH Precharge command command echarge Refresh command gt Write Refresh gt FRAME gt IRDY gt TRDY gt DEVSEL 81 User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 4 6 Mode register set cycle Figure 3 29 shows the circuit diagram of the mode register set cycle control In this diagram the A side of 74157 is the circuit to control the command for refresh cycle and the B side is the circuit to control the command for mode register set cycle The CS signal RAS signal and CAS signal in the mode register set cycle use the same circuit as in re
27. are of high quality and reliability However users are instructed to contact Elpida Memory s sales office before using the product in aerospace aeronautics nuclear power combustion control transportation traffic safety equipment medical equipment for life support or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury Product usage Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory Inc including the maximum ratings operating supply voltage range heat radiation characteristics installation conditions and other related characteristics Elpida Memory Inc bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions Even within the guaranteed ranges and conditions consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Elpida Memory Inc products does not cause bodily injury fire or other consequential damage due to the operation of the Elpida Memory Inc product Usage environment This product is not designed to be resistant to electromagnetic waves or radiation This product must be used in a non condensing environment If you export the products or technology described i
28. conventional DRAM are used for SDRAM to realize higher speed operation EDO DRAM is provided with extended output functions but it has a problem of operating frequency similarly to FPM DRAM if higher speed is demanded Generally EDO DRAM can be synchronized only up to the clock of approximately 75 MHz SDRAM is capable of operation at higher operating frequency than EDO DRAM is SDRAM however has package pin configuration control signal names and the number of signals different from those of the conventional DRAM since SDRAM performs controls with an interface different from that of the conventional DRAM and the new specifications In the first half of 1997 SDRAM occupied approximately 25 of all the DRAM shipment It is expected that SDRAM will represent more than 50 of DRAM shipments around 1998 and become the most popular high speed DRAM Currently the mainstream of SDRAM synchronizes with the clock of 66 to 100 MHz SDRAM that synchronizes with the clock of 125 to 143 MHz is also to appear in the future User s Manual E0124N10 11 4 5 6 7 8 9 12 CHAPTER 1 SYNCHRONOUS DRAM RDRAM Rambus DRAM RDRAM employs the unique specifications proposed by Rambus Inc Although RDRAM operates in synchronization with the clock of 300 MHz adoption of the dual edge system makes it equivalent to synchronization with the clock of 600 MHz The dual edge system is a system that can perform controls at two points the risi
29. e 1 cycle of CBR auto refresh cycle e 1 cycle of CBR auto refresh cycle e 1 cycle of access cycle other than memory 1 cycle of CBR auto refresh cycle e 1 cycle of mode register set cycle In Figure A 2 0 ns to 750 ns are shown and in Figure A 3 750 ns to 1388 ns are shown User s Manual 0124 10 OLNFcLO3 sasn 68 Figure A 1 Entire Circuit Diagram OUTPUT OUTPUT gt OUTPUT gt gt Voc OUTPUT Vec 7474 OUTPUT gt OUTPUT gt OR2 ON Y D D 1QNb o 2 2aNb es input C BE2 AND2 XOR D FLIP FLOPS AND2 D INPUT AND2 2 C BEO gt D Aa INPUT Refresh gt Ha AND2 Vo 7474 MULTIPLEXER Greer Mode m NPUT 1 GND 1CLRN 10 OUTPUT 5 Vec 1CLK 1QNb 20 aQNb b 1PRN FRAME Vec 2CLRN INPUT H TELE OUTPUT 1
30. is are high a wait is inserted IRDY high indicates that the bus master is requesting a wait from the target TRDY high indicates that the target is requesting a wait from the bus master When both IRDY and TRDY becomes low at the same time while FRAME is low data transfer starts When both IRDY and TRDY become low at the same time while FRAME is high this indicates the last data transfer and idle state must be set afterward Figure 2 3 Basic Cycle Ti T2 13 T4 T5 16 17 T8 719 T12 1 1 i i i From bus master So nue A AMD 21 AD 1 1 I From bus master lt Qaa Paa ______ C BE 1 1 1 From bus master l GER E a a BE i From bus master From target i DEVSEL 1 1 1 1 1 From target A M TL CENE EE E Turn around l Starts data cycle wait Wait Wait Wait Wait transfer transfer i i idle state 1 1 1 1 1 1 1 1 1 Latches Data Data Data Data Last address transfer transfer transfer transfer data Signal and transfer 1 1 1 1 1 1 sets bus command Controls of read cycle and write cycle are performed with command CMD User s Manual 0124 10 49 2 5 2 2
31. low The circuit examples show the concept of operation and not actual operation Use the description only for reference purpose upon designing 341 Basic signals 1 SDRAM operation mode select signal In Figure 3 11 the select signal to request the operation of each operation mode from SDRAM is generated using the circuit shown in Figure 3 6 The memory signal becomes high only when the PCI bus command is either memory read or memory write command Read signal and write signal become high only when the PCI bus command is memory read and when it is memory write respectively Figure 3 11 Circuit Diagram and Timings of Select Signal Generation of Each Operation Mode OUTPUT Memory gt t Write OUTPUT Read cle of SDRAM 1 37 5 ns 75 0 ns 112 5 ns 150 0 ns 187 5 ns 225 1 4 1 1 1 Write cycle of SDRAM 66 User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 2 Basic control signal In Figure 3 12 basic control signals are generated These signals are referenced when generating the command to control SDRAM AAA signal Becomes low at the following rising edge of CLK signal when FRAME signal is high and becomes high when FRAME signal is low BBB signal 1 2 frequency division signal of CLK signal started from low when FRAME and AA signals are low signal 1 2 frequency division signal of BBB signal 1 4 frequency division of
32. low At point lt 2 gt read command RED and column address signal are latched to declare it is a read cycle and data is output a few clocks after In the conventional DRAM this point corresponds to the state that CAS signal is made low after RAS signal becomes low and WE signal is high The time after column address signal is latched until valid data is output is called CAS latency CL 2 in Figure 1 4 and the number of words of the data continuously output is called burst length BL 1 in Figure 1 4 In the conventional DRAM CAS latency corresponds to CAS access time and the burst length corresponds to the number of page mode cycles At point lt 3 gt precharge command PRE is input tras after active command is latched In the conventional DRAM this point corresponds to the state that RAS signal and CAS signal are high 18 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 2 Access time Figure 1 5 Burst Read Cycle SDRAM 15 ns Address pios Data eo T lt DOUTXDOUTXDOUTXDOUT gt 1 1 Conventional DRAM 1 Data Figure 1 5 shows the burst read cycle when burst length 4 Assuming the clock speed of SDRAM is 66 MHz the access time of this SDRAM and that of 60 ns product trac RAS access time 60 ns of EDO DRAM compared the conventional DRAM is not synchronized with 66 2 clock In the case of SDRAM
33. must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function User s Manual E0124N10 3 Rambus RDRAM and the Rambus logo are registered trademarks of Rambus
34. signal because a precharge command is automatically input Considering the circumstances shown above the use of auto precharge is convenient for the control in which the burst length is fixed and an active command is input whenever the burst ends 2 Precharge command In precharge a precharge command can be input at any timing tras after the active command For example the use of precharge is convenient for the control in which the burst length is not fixed but fluctuated depending on the cycle i e burst length 4 in read cycle and burst length 1 in write cycle and for the control which has less chances of changing row address signals User s Manual E0124N10 39 CHAPTER 1 SYNCHRONOUS DRAM 1 4 8 Temporary stop of clock during data transfer Figure 1 27 shows the case that the read cycle is controlled with precharge when CAS latency 2 CL 2 burst length 4 BL 4 Figure 1 28 shows the case that the write cycle is controlled with the same condition as above Figure 1 27 Temporary Stop of Clock in Read Cycle 1 1 tre 1 1 I 1 77 tras 1 tre ea RAS 1 EN 1 1 WE ___ ______ __ 11 1 1 DQM CL 2 1 288 _ __ 1 1 I NEU um m E 1 1 1 1 1 1 1 Active Rea
35. signal that employs AND logic of Low only in mode register set cycle memory signal and mode signal Signal to latch memory signal Low only in cycles other than memory Signal to employ AND logic of 50 signal and Low only in refresh cycle and mode register set FMS2 signal cycle All the FMS signals are high in conditions other than above Figure 3 13 Circuit Diagram of Basic Select Signal Generation FRAME INPUT CLK D FLIP FLOPS Write NUT D OUTPUTS Fuss INPUT Vcc INPUT Voc Refresh gt Mode gt D FLIP FLOPS 68 User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER Figure 3 14 Timings of Basic Signal 225 0 ns 300 0 ns 375 0 ns 450 0 ns 525 0 ns 600 0 ns 675 0 ns 150 0 ns Read cycle 111111111 Write cycle Readoycle 1 275 us 1 125 us 750 0 ns 825 0 ns 900 0 ns 975 0 ns 675 0 ns Mode register set cycle write cycle Access cycle other than Refresh cycle memory write cycle Refresh write cycle write cycle E E D qu uri rn 1 Access cycle other 1 than memo y Mode register set cycle r 1 oth Access cycle
36. the SDRAM and SDRAM controller are configured in the expansion board In this case the expansion board and the PCI controller become the target and the bus master respectively Figure 3 1 Block Diagram of PCI Interface Mother board Bus master Expansion PCI board PCI controller PCI bus PCI expansion SDRAM connector controller When transferring data from the PCI controller to SDRAM the SDRAM controller generates the signal to control SDRAM using the signal output from the PCI controller and input the generated signal to SDRAM User s Manual E0124N10 55 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 2 1 Block diagram of SDRAM controller An SDRAM controller can be divided roughly into five blocks Select circuit Refresh control circuit Address signal data switching circuit Row column address signal switching circuit Control signal generation circuit This User s Manual uses two DRAM products with 16 Mbit x16 bit configuration This is because the PCI bus has a 32 bit bus width and the two SDRAM simultaneously perform identical operations Figure 3 2 Block Diagram of SDRAM Controller PCI slot SDRAM Row column Select Refresh address signal circuit control circuit FRAME IRDY TRDY Control signal generation circuit DEVSEL CLK 1 Select circuit 2 3 56 A circuit to Direct the control signal generation circuit to generate control signals required for read and
37. the other cycles When the PCI bus controller accesses devices other than memory CS signal becomes high When the CS signal becomes high all the control signals also become high because the RAS CAS signal is generated with the OR logic with the CS signal and WE signal is generated with the OR logic with the RAS signal Figure 3 31 Circuit Diagram of Access Cycles Other than Memory OUTPUT cs V GND MULTIPLEXER INPUT Vcc INPUT Vcc INPUT OUTPUT RAS OUTPUT gt CAS Voc User s Manual E0124N10 a OUTPUT WE CHAPTER 3 DESIGNING SDRAM CONTROLLER Figure 3 32 Timings of Access Cycles Other than Memory 0 0 0 0 0 0 0 0 0 0 i User s Manual 0124 10 85 2 3 86 CHAPTER 3 DESIGNING SDRAM CONTROLLER Handling of CKE signal The CKE signal in the circuit example is fixed to high whether accessing SDRAM or not The controls shown below are essentially preferred for the PCI controller Set the signal to high when accessing SDRAM Set the CKE signal to low when accessing memory other than SDRAM and I O equipment This is because setting the CKE signal to low stops the internal clock of SDRAM so that the current consumption of SDRAM can be minimized data cannot be retained only by setting the CKE signal to low To retain data refresh operation is required In addition if the CKE sig
38. 1st access 60 ns 2nd access 75 ns 1st access 60 ns 15 ns 3rd access 90 ns 2nd access 75 ns 15 ns 4th access 105 ns 3rd access 90 ns 15 ns In the case of EDO DRAM 1st access 60 ns 2nd access 85 ns 1st access 60 ns 25 ns 3rd access 110 ns 2nd access 85 ns 25 ns 4th access 135 ns 3rd access 110 ns 25 ns Comparing SDRAM and EDO DRAM SDRAM has the same speed as EDO DRAM does in 1st access but 10 ns faster in 2nd access 20 ns faster in 3rd access and 30 ns faster in 4th access As shown above SDRAM has the same speed as EDO DRAM in 1st access but the longer the burst length the higher the data transfer speed SDRAM has Table 1 3 shows the access time of each SDRAM and EDO DRAM User s Manual 0124 10 19 CHAPTER 1 SYNCHRONOUS DRAM Table 1 3 Access Times of SDRAM and EDO DRAM 143 MHz 125 MHz 100 MHz 60 MHz EDO DRAM trac 60 ns trac 50 ns trac 40 ns Table 1 3 shows only up to burst length 4 but the longer the burst length the larger the difference of performance between SDRAM and EDO DRAM 3 Using the conventional DRAM and SDRAM in the same cycle The following explains an example of using the conventional DRAM and SDRAM in the identical cycle taking the case of read cycle The read cycle of SDRAM in Figure 1 6 shows the case that CAS latency 2 CL 2 burst length 1 BL 1 Figure 1 6 Identic
39. 2 End of data transfer The end of data transfer can be controlled either with bus master or target In neither case data transfer cannot one sidedly be ended The bus master has the final authority and orderly controls the end of data transfer There are several methods to end data transfer This section explains only basic processings 1 When controlled with the bus master When the bus master sets FRAME to high while both IRDY and TRDY are low it indicates that the data phase of the next clock is the last data transfer The bus master notifies the target that the data transfer is ending When both IRDY and TRDY are high data transfer is completed Figure 2 4 End of Transfer Controlled with Bus Master IRDY From bus master TRDY From target Last End of data data transfer transfer From bus master NEM 2 When controlled with the target The target sets STOP to low and requests the bus master to end data transfer Figure 2 5 End of Transfer Controlled with Target CLK FRAME FRAME From bus master From bus master IRDY IRDY From bus master From bus master TRDY TRDY From target From target STOP STOP From target From target Last End of Last End of data data data data transfer transfer transfer transfer After STOP is set to low the bus master immediately sets FRAME to high to end data transfer
40. A11 is used for the bank select signal DQM Input UDQM Input LDQM Input DQM controls I O buffers DQM high and DQM low turn the output buffers off and on respectively x16 bit products are capable of byte control 8 bit control UDQM and LDQM control upper byte and lower byte input buffers respectively DQO to DQn Input Output DQO to DQn are data pins DQn DQ7 and DQ15 in x4 bit products x8 bit products and x16 bit products respectively Vss Power supply Input Vcc and Vss are power supply pins for internal circuits User s Manual E0124N10 21 CHAPTER 1 SYNCHRONOUS DRAM 1 3 2 Commands SDRAM unlike the conventional DRAM performs controls with commands A command refers to a combination of logic levels of control signals The following explains each command 1 Mode register set command Mode register set command sets the mode register before entering the operation mode to set operation method in advance This command is executed with a combination of the logic level of each address signal pin After power on the mode register set command must be executed to set the mode register The mode register retains the data until the setting is made again or the device loses power Figure 1 7 Mode Register Set Command 2 Active command Active command selects a bank with the address signal that controls the selection of bank and latches row address signal of the ba
41. BE1 C BEO Controls Interrupt acknowledge Bus command performs Special cycle read write Reserved 1 Reserved 1 1 0 Memory read Memory write Reserved Reserved Configuration read Configuration write Memory read multiple Dual address cycle Memory read line Memory write and invalidate Of the bus commands shown in Table 2 2 the circuit used in CHAPTER 3 refer to Figure A 1 Entire Circuit Diagram uses memory read and memory write commands This section therefore explains only memory read and memory write commands 1 Memory read command 2 This is a command with which the bus master declares the reading data from a memory mapped in the memory address space Memory write command This is a command with which the bus master declares the writing data in a memory mapped in the memory address space User s Manual 0124 10 47 2 5 2 1 5 drive and turn around cycle All the signals controlled with more than one bus masters requires turn around cycles The turn around cycle is a cycle to set aside a certain interval to avoid the collision of signals when one bus master stops the drive of a device and another bus master starts the drive of that device The shadowed portion in Figure 2 2 indicates turn around cycles Figure 2 2 Turn around Cycle of
42. ELPIDA User s Manual SYNCHRONOUS DRAM Document No E0124N10 Ver 1 0 Previous No M12394EJ2V2ANO0 Date Published May 2001 CP K Elpida Memory Inc 2001 Elpida Memory Inc is a joint venture DRAM company of NEC Corporation and Hitachi Ltd SUMMARY OF CONTENTS CHAPTER 1 SYNCHRONOUS 11 CHAPTER 2 PCI BUS 44 CHAPTER 3 DESIGNING SDRAM CONTROLLER 0 c cccccssssssssssesssesseesseeseesseesseesaesseesenesessaessnessnesseesneueneuenes 54 APPENDIX A DIAGRAM AND TIMINGS OF ENTIRE 20 2 20 40 88 2 User s Manual E0124N10 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices
43. Each Phase FRAME From bus master From bus master O e e BE From bus maste D s IRDY From bus master gi TRDY i From target i i ee d From target 1 1 1 Idle Address phase phase 1 t 1 1 Data phase Idle phase 1 1 IRDY TRDY DEVSEL4 etc require turn around cycles in address phase 2 FRAME and C BE require turn around cycles in idle phase Idle phase is a state where both FRAME and IRDY are high 3 AD changes the direction of input output because the address and data are multiplexed Turn around cycles therefore are required at different phases e When inputting data turn around cycles are required in idle phase and address phase When outputting data turn around cycles are required only in idle phase 48 User s Manual E0124N10 2 5 2 2 Data Transfer 2 2 1 Outline of data transfer Data transfer is started when FRAME is low In read cycle address signal is output and data is input Turn around cycles therefore must be inserted between address signal and data In write cycle turn around cycles are not required because both address signal and data are output When is low and either or both of IRDY or and TRDY
44. Inc Direct Rambus Direct RDRAM RIMM and SO RIMM are trademarks of Rambus Inc Pentium is a trademark of Intel Corporation The information in this document is subject to change without notice Before using this document confirm that this is the latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory Inc Elpida Memory Inc does not assume any liability for infringement of any intellectual property rights including but not limited to patents copyrights and circuit layout licenses of Elpida Memory Inc or third parties by or arising from the use of the products or information listed in this document No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of Elpida Memory Inc or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer Elpida Memory Inc assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information Product applications Elpida Memory Inc makes every attempt to ensure that its products
45. M Mode register set cycle is multiplexed with the timing of the write cycle Figure 3 10 Mode Register Set Cycle between PCI Controller and SDRAM T2 13 714 T5 T6 77 18 T TZ From bus master 1 Dat Dat D D From bus maste From bus master IRDY i From bus master TRDY T i h From target 12 Insert i DEVSEL pee ound wan From target TaT OMEN e coeur OU 1 die cue 1 1 1 I 1 1 1 1 1 CASH wes 1 A11 1 A 1 1 DQ ae ee Ihe ele Sh 1 1 The bus master inputs a write command at T1 and declares output of data to SDRAM An all bank precharge command a mode register set command and an active command that indicates the next operation are input to SDRAM at T2 T4 and T2 respectively In this case the bus master outputs data but SDRAM does not accept the data For the reason refer to 3 2 2 State diagram of SDRAM controller One turn around cycle and one wait are inserted at T2 and T3 respectively Turn around cycle however is not essentially req
46. Once STOP is set to low do set STOP to high until FRAME becomes high 50 User s Manual E0124N10 2 5 2 2 3 Arbitration When there are more than one bus masters they REQ and GNT to orderly perform controls The bus masters request the use of bus by setting REQ to low Do not set REQ to low unless the bus is actually used REQ and GNT are dedicated signals for the bus masters The bus master arbiter which arbitrates the bus sets GNT to low when it judges that one of the bus masters agent etc which are to control given processing can use the bus 2 2 4 Latency Latency is the time after one bus master requests the use of bus until the target inputs outputs the data Figure 2 6 includes three latencies Figure 2 6 Access Latency Bus master Arbiter Arbitration latenc Bus acquisition latenc Target Agent Target latenc 1 Arbitration latency The period when more than one bus masters arbitrates the bus using REQ and GNT The time after one bus master sets REQ to low until the bus master that arbitrates the bus sets GNT to low This is 2 clock period for the bus master with the highest priority 2 Bus acquisition latency The period when the bus masters have to wait until the bus is released The time after one bus is permitted to use the bus until it sets FRAME to low This is 1 clock period 3 Target latency The period
47. QM All banks Mode Active precharge register set command command command The following explains the contents of the mode register taking the case of 16 M SDRAM The mode register set command sets the operation of SDRAM according to the logic level of address AO to A11 signals The mode register has four fields 1 AO to A2 Setting of burst length 2 A3 Setting of wrap type 3 A4 to A6 Setting of CAS latency 4 A7 to A11 Options 1 Setting of burst length Setting of the number of words in which SDRAM continuously inputs outputs data The burst length is selectable as 1 2 4 8 or full page 28 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM Table 1 6 Setting of Burst Length When A3 0 When 1 8 Reserved Reserved Reserved Reserved Reserved Reserved Full page Generally burst length 4 is commonly used Reserved Reserved is set aside for the future extension of specifications All the devices are prohibited to use the reserved 2 Setting of wrap type The setting of the increment order of address signals in burst cycle When 0 the order is sequential and when 1 the order is interleaving The method chosen will depend on the type of DRAM controller used in each system Generally interleaving is commonly used 3 Setting of CAS latency The setting of the latency value after
48. RAM adopts the pipeline system 11 DDR SSRAM Double Data Rate SSRAM DDR 55 is a next generation high speed SRAM While SSRAM adopts the single edge system DDR SSRAM adopts the dual edge system Figure 1 1 Types of High speed RAM Conventional FPM DRAM DRAM EDO bM DRAM gt High speed DRAM Synchronous type DRAM DDR SDRAM RDRAM DirectRDRAM gt Next generation 22 High speed DRAM SynchLink DRAM Graphics Synchronous type Conventional SRAM Synchronous type SRAM Dual Port Graphics Buffer DDR SGRAM DDR SSRAM User s Manual E0124N10 13 CHAPTER 1 SYNCHRONOUS DRAM 1 1 2 Access time of high speed DRAM Access time of DRAM can be divided into the following two types Random access time Access time in which both the row address and the column address different from those of the preceding cycle are accessed e Burst access time Access time in which the same row address and a column address different from that of the preceding cycle are accessed The DRAM that is newly under development and examination has the random access equal to that of the conventional DRAM and only its burst access time is made higher speed As shown in Table 1 1 DRAM EDO DRAM SDRAM and RDRAM have approximately equal random access times but have different burst access times Table 1 1 Random Access Time and Burst Access Time Random Access Time ns Burst Ac
49. RO 1 1 1 1 1 Refresh space 1 1 0 0 0 Mode register space Other space Open space Memory space controlled with PCI master etc User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER Input the address signal ADR31 to ADR29 defined in Figure 3 4 to the circuit in Figure 3 5 to generate the refresh signal and mode signal When the refresh space is selected the refresh signal becomes high and when the mode register space is selected the mode signal becomes high Figure 3 5 Select Signals of Refresh and Mode Register Cycle ADR31 Refresh ADR30 ADR29 ADR31 ADR30 ADR29 Refresh Mode 1 1 1 1 0 Input C BE3 C BE2 C BE1 and C BEO signals to the circuit in Figure 3 6 to generate the read signal and write signal With the memory read command of the PCI bus the read signal becomes high With the memory write command of the PCI bus the write signal becomes high The control of read write cycle uses the logic level of C BE signal output from the PCI bus to generate read and write control signals The selection of memory space according to read write cycle therefore is not required In this case two SDRAMs perform identical operations Figure 3 6 Select Signals of Read Write Cycle Vus 1 C BEO Read 0 0
50. a transfer onica oe cea dee n Ue ee env Canet 49 2 2 2 End of datecttansfer ete aloe e ette crt eoe p vey ER ex e chap Ra RE deus ce 50 2 2 3 AIDItratlori i oni 51 2 2 4 LAtOnCy isch 51 2 2 5 Random a6c6ss 52 2 2 6 Burst access ee ERE E e ERE TEE RE EUER 53 6 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM 54 31 Outline of SDRAM nannan nenn 54 3 2 Outline of Connection between SDRAM and PCI 1 1 11 1 55 3 2 1 Block diagram of SDRAM controller esseeeseseseeeeeeneeneeennneen eene nennen nnne nnns 56 3 2 2 State diagram of SDRAM controller sseesseseseeeeeeeeneeenneennneen nennen nennen nnne nennen 57 3 2 3 Memory space neuere os rre ee pL ah ee ceed a Eo PARTE eed 58 3 3 Timings between PCI Controller and SDRAM eeeeeeeeeeeeenne nnne nnnnnn nn nnnn nnns nini nnne 61 3 3 1 Read cycle of SDRAM Eee Leitern
51. al In Figure 3 24 commands corresponding to various operation modes are changed using the 51 2 3 and 4 signals In the circuit example read write refresh mode register set and accesses other than memory are controlled The command for these operation modes are individually generated changed according to the corresponding operation mode and input from SDRAM controller to SDRAM Figure 3 24 Example of Control Signal Changing Circuit FMS3 74157 Command for cycles other than memory Output Command for read cycle ae FMS1 A side Cycles other FMS2 C 74157 than memory 74157 To SDRAM i B side Read cycle Sutput Command for refresh cycle Command for mode FMS4 register set cycle Aside Refresh cycle B side Mode register set cycle A side Cycle other than read and memory B side Write refresh mode register set cycle Command for write cycle gt A side Refresh mode register set cycle B side Write cycle User s Manual E0124N10 77 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 4 4 Write cycle The write cycle in the circuit example supports only the burst write cycle with burst length 4 Figure 3 25 shows the circuit diagram of burst write cycle control In this diagram the A side of 74157 is the circuit to control the command for read cycle and the B side is the circuit to control the command for write cycle The CS signal RAS sign
52. al CAS signal and WE signal generate commands in write cycle as OR logic of the BBB signal and HHH signal OR logic of the CS signal and EEE signal OR logic of the CS signal and FFF signal and AND logic of the CAS signal and WE signal in read cycle respectively Figure 3 25 Circuit Diagram of Burst Write Cycle Control Generation OUTPUT WE DL DE RAS OUTPUT CAS GND MULTIPLEXER OUTPUT cs 78 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER Figure 3 26 Timings of Burst Write Cycle Control 180 0ns 195 0ns 210 0ns 225 0ns 240 0ns 255 0ns 270 0ns 285 0ns 300 330 0 0 0 0 0 0 0 0 OE AIL Write cycle of SDRAM User s Manual E0124N10 Ons 315 0ns T 79 3 4 5 Refresh cycle cycle 80 CHAPTER 3 DESIGNING SDRAM CONTROLLER The refresh cycle in the circuit example supports only the CBR auto refresh cycle Figure 3 27 shows the circuit diagram of CBR auto refresh cycle control In this diagram the A side of 74157 is the circuit to control the command for refresh cycle and the B side is the circuit to control the command for write The commands for refresh cycle are generated as follows CS signal OR logic of the signal that employs OR logic of the GGG signal and HHH signal and the BBB signal RAS signal OR logic of the signal that employs OR logic of the GGG signal
53. al Read Cycle of Conventional DRAM and SDRAM Command Address Data Conventional DRAM RAS 1 Data 20 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM If a controller that generates the following signals is designed the conventional DRAM and SDRAM can simultaneously be used Table 1 4 Correspondence of Control Signals of Conventional DRAM and SDRAM Figure 1 6 Conventional DRAM RAS signal is active Input active command CAS signal is active Input read command 1 3 Control Method of SDRAM RAS signal is inactive Input precharge command The following explains control methods commonly used taking 16 M SDRAM as an example For the detailed control method of SDRAM refer to the user s manual of SDRAM 1 3 1 Pin functions Pin Name CLK Input Input Output Table 1 5 List of Pin Functions Pin Function CLK is the master clock input pin Control signals of SDRAM are referenced to the CLK rising edge CKE Input CKE determines validity of the next CLK If CKE is high the next CLK rising edge is valid otherwise it is invalid CS Input CS low starts the command input cycle RAS Input CAS Input Input RAS CAS and WE have the same symbols on conventional DRAM but different functions For details refer to 1 3 2 Commands to A11 Input to 11 are address input pins A10 defines the precharge mode
54. cess Time ns FPM DRAM 35 EDO DRAM 20 SDRAM 8 RDRAM 1713 Conventional SRAM Synchronous type SRAM Note Figures in the parentheses show the value of DirectRDRAM The table above shows that the burst access times of high speed DRAM are equal to or faster than the random access times of the conventional SRAM and synchronous type SRAM Therefore it is advisable to keep the control with random access minimum and perform controls with burst access as much as possible when controlling high speed DRAM so that a performance equal or superior to that of the conventional SRAM can be demonstrated 14 User s Manual 0124 10 CHAPTER 1 SYNCHRONOUS DRAM 1 1 3 Relation to system clock Figure 1 2 shows the random access times and burst access times in Table 1 1 converted into frequencies The frequencies are likened to memory bus clocks to illustrate up to which memory bus clock each memory can support The operating frequencies shown here are conversion of the burst access times of DRAM into operating frequencies The operating frequencies of the DDR SDRAM DDR SGRAM and RDRAM however are made half since they adopt the dual edge system Figure 1 2 Memory Bus Clock Each High speed DRAM Can Support DirectRDRAM DDR SDRAM DDR SGRAM 133 266 EDO DRAM FPM DRAM 0 10 30 50 70 100 250 Operating frequency MHz FPM DRAM had been the main stream until 1996 FPM DRAM supports only a memory bus cl
55. d Precharge Active command command i command command forbankA forbankA forbankA forbankA lt gt 2 The internal clock of memory can be stopped by setting CKE signal to low at point lt 1 gt The internal clock of memory stops at point lt 2 gt The latency from CKE signal to the stop of the internal clock of memory is always 1 regardless of the number of CL In Figure 1 27 CLK signal is always input The internal CLK signal of memory however stops for one clock at point lt 2 gt and tras therefore delays for one clock when the external CLK signal is taken as a reference 40 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM In Figure 1 28 the clock is temporarily stopped for two clocks in the write cycle Figure 1 28 Temporary Stop of Clock in Write Cycle 1 1 1 tRC 1 1 ps T T T T T T T T T trop tras i tre 1 1 e CS i i 1 pee 1 1 jii decre E DQM i i i i ni COCEE Q 1 I 1 I I 1 1 1 1 1 Active Write Precharge command command command forbankA forbankA i forbankA lt gt 2 lt 3 gt The c
56. dress phase and data phase of AD respectively FRAME Cycle frame Signal to be input to the target This signal indicates the period in which an access is executed FRAME low indicates the bus is controlling data transfer IRDY Initiator ready Signal to be input to the target This signal becomes low when the bus master is ready for read or write operation It is used simultaneously with TRDY and becomes wait state when either is high and becomes data transfer state when both are low TRDY Target ready Signal to be output from the target This signal becomes low when the target is ready for read or write operation It is used simultaneously with IRDY and becomes wait state when either is high and becomes data transfer state when both are low STOP Stop Signal to be output from the target This signal is output from the target to request the bus master to stop the current transfer DEVSEL Device Select Signal to be output from the target This is a response signal to the signal with which the target directs the bus master to start operation REQ Request dedicated signal for bus master Signal with which a certain bus master requests the use of the bus from the bus master arbiter which arbitrates the bus when there are more than one bus masters GNT Grant dedicated signal for bus master Signal with which the bus master arbiter that arbitrates the bus permits the use
57. e clock operating frequency can be The relationship between CAS latency and the clock operating frequency differs depending on the product See each SDRAM Data Sheet in designing a system Table 1 2 Example of Clock Operating Frequency Corresponding to CAS Latency 125 MHz 100 MHz 8 ns 10 ns 87 MHz 66 MHz 12 ns 15 ns Remark 2 cannot be used in the product of grade 80 and 10 at 125 MHz 100 MHz respectively User s Manual E0124N10 17 CHAPTER 1 SYNCHRONOUS DRAM 6 Selectable burst length BL The selection of burst length is made with the mode register The burst length is a number of words that can continuously be input output in read cycle or write cycle 1 2 3 Basic control method and access time The following explains the actual control method taking the case of read cycle 1 Basic control method Figure 1 4 Read Cycles of Conventional DRAM and SDRAM SDRAM Tn T1 T2 T3 T4 5 6 7 T8 T2 cock LI LILILILILILUL LILI EO TEM 52 DD DD Mess gt 1 4 11 Conventional DRAM M f te CAS I I OE Dig uc 1 2 lt 3 gt At point lt 1 gt active command ACT and low address signal are latched at first so that the start of operation is declared In the conventional DRAM this point corresponds to the state that RAS signal is
58. ed protocol called SynchLink interface SynchLink DRAM aims at operating frequency of 400 MHz Dual Port Graphics Buffer Dual Port Graphics Buffer is a memory dedicated for images and it is configured with two ports serial port and RAM port The serial port performs read out to display unit displaying image and the RAM port mainly performs write in to an image memory drawing Although the RAM port is basically configured with DRAM the operation mode for drawing which is not provided to DRAM is added in order to simplify designing of graphics systems SGRAM Synchronous Graphics RAM SGRAM is a synchronous memory dedicated for images Although SGRAM is basically configured with SDRAM the operation mode for drawing which is not provided to SDRAM is added in order to simplify designing of graphics systems DDR SGRAM Double Data Rate SGRAM DDR SGRAM is a next generation high speed SGRAM While SGRAM adopts the single edge system which performs controls at a single edge of the basic clock DDR SGRAM adopts the dual edge system User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 10 SSRAM Synchronous SRAM SSRAM is a synchronous high speed SRAM There are two types of SSRAM the type that adopts the pipeline system and the type that does not adopt the pipeline system non pipeline system Sometimes the type that adopts the pipeline system is called PBSRAM Pipeline Burst SRAM and the type that does not is called SSRAM SD
59. fresh cycle The WE signal generates the command in the mode register set cycle as OR logic of the CS signal and EEE signal Figure 3 29 Circuit Diagram of Mode Register Set Cycle Control Generation OUTPUT gt OUTPUT RAS OUTPUT CAS GND MULTIPLEXER 82 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER Figure 3 30 Timings of Mode Register Set Cycle Control 1 2375 us gt 1 gt 2 gt Read gt Write gt Refresh oo oo register set cycle write cycle 8 1721 1731 174 11511161 177 User s Manual 0124 10 1 2 83 3 4 7 Other cycles This section excerpts the most important of the handling of SDRAM control signals when PCI bus controller CHAPTER 3 DESIGNING SDRAM CONTROLLER accesses devices other than memory and the operations of SDRAM that have not been explained in the preceding sections and explains their control concept 1 Handling of SDRAM control signal when the bus controller accesses devices other than memory 84 Figure 3 31 shows the diagram of the circuit to control device access cycles other than memory In this diagram the A side of 74157 is the circuit to control the command for access cycles other than memory and the B side is the circuit to control the command for
60. fresh cycle This Users Manual is a preliminary reference Information contained in this Users Manual is subject to change without notice The descriptions concerning PCI bus in this User s Manual show only the concept of operation and not actual operation Use the descriptions only for reference purpose upon designing User s Manual E0124N10 5 5 CHAPTER 1 SYNCHRONOUS 222 nba exams utr eR cs 11 IS uESNDBEILV UE 11 1 1 1 Types of high speed 11 1 1 2 Access time of high speed nnne neret nnne enne nnn 14 1 1 3 Relation to system clock e de RE eR enr 15 1 2 Difference between Conventional DRAM and 5 16 1 24 Whats iaceo 16 1 2 2 Feat res o SDRAM 5 ae du ee fo de 17 1 2 3 Basic control method and access time 18 1 3 Control Method of SDRAM oie Cnm sema 21 1 3 PIM FUNCTIONS 21 1 9 2 ERREUR EDO 22 1 3 3 testem
61. gic levels of control signals Typical commands include active command read or write command precharge command etc The conventional DRAM is also controlled with combinations of logic levels of control signals The conventional DRAM however does not have the concept of command 3 Multiple bank configuration of internal memory circuit The memory chip is separated into several banks so that controls can be performed by the bank For example since the interleave control can be performed to each bank the precharge time is seemingly hidden thus enabling high speed access In the case of SDRAM with 2 bank configuration the control of the bank is set according to the logic level of the highest address signal 4 Adoption of control by the mode register The mode register sets in advance the CAS latency and the burst length etc in the logic level of address signals at a given time for the details refer to 1 3 4 Setting of mode register The mode register retains data until the setting is made again or the device loses power 5 Selectable CAS latency CL CAS latency is the number of clocks from input of a command to output of data The number of clocks can be set with the mode register The value of CAS latency has close relationship with the clock operating frequency The smaller the value of CAS latency the lower the speed of the clock operating frequency must be set to The larger the value of CAS latency the higher the speed of th
62. inues while CKE signal remains low When CKE signal goes to high the self refresh mode is terminated During self refresh mode refresh interval and refresh operation are automatically performed internally so there is no need for external control During certain period of time trc following this command the next command cannot be accepted Figure 1 13 Self Refresh Entry Command CM WE 8 Burst stop command Burst stop command terminates the burst operation whose data is being transferred Although this command is a specification of the industrial standard SDRAM of some companies do not support this command Care should be taken when using this command Figure 1 14 Burst Stop Command User s Manual E0124N10 25 CHAPTER 1 SYNCHRONOUS DRAM 9 NOP command NOP command does not perform any operations No operations are started or terminated by inputting this command Figure 1 15 NOP Command c CH RASH CASH WE 26 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 1 3 3 Initialization SDRAM must be initialized in order to perform proper operation since the state of the circuit inside the SDRAM is unstable immediately after power on SDRAM may not operate properly even during operation guarantee period unless initialization is performed properly To initialize internal circuit precharge must be executed for both the banks using the all banks precharge command etc after 100 ws or longer pause high le
63. is inserted to T7 with the IRDY signal as shown in Figure 3 33 on the other hand extended cycles must be inserted for one cycle immediately after the wait is inserted extended cycle must be inserted for two cycles when the wait is two cycles Self refresh cycle Although refresh cycle is used only in CBR auto refresh cycle use of CBR self refresh cycle is effective when SDRAM is used for portable equipment etc which is driven only with the battery Self refresh requires smaller current than CBR auto refresh does For details refer to individual Data Sheet User s Manual E0124N10 87 APPENDIX A DIAGRAM AND TIMINGS OF ENTIRE CIRCUIT Figure A 1 shows the diagram of entire circuit of the circuit examples Figures A 2 and A 3 show the timings of the logic verification result of this circuit The timing charts of the logic verification result have taken propagation delay in consideration Name in Figures A 2 and A 3 show each signal name and signals shown in parentheses have the following meanings 88 I Input signal O Output signal Operating frequency of 66 MHz is used for the logic verification In Figures 2 and 3 the logic verification is performed with sequence of the following operations e Burst read cycle with burst length 4 Burst write cycle with burst length 4 Burst write cycle with burst length 4 e Burst read cycle with burst length 4 e Burst read cycle with burst length 4
64. ite operations of SDRAM and the operations from devices other than SDRAM such as PCI controllers are described as reverse operations As examples of circuit design of SDRAM controller circuit diagrams are added in the appendix refer to Figure A 1 Entire Circuit Diagram The circuit is used for explanation hereafter The descriptions in this chapter show only the concept of operation and not actual operation Use the descriptions only for reference purpose upon designing 3 1 Outline of SDRAM Controller CPU and SDRAM cannot be connected directly This is because the CPU and SDRAM have different control signal functions and processing methods The CPU is designed to be connected not only to SDRAM but to other memory and I O equipment Therefore a memory controller between the CPU and SDRAM is required in order to connect them Most personal computers are provided with a CPU memory and a chip set A chip set is configured with controllers of various devices and a memory controller is also a part of the chip set Since SDRAM controllers that deal with controls of SDRAM only are explained in this case the circuit examples are configured only with memory controllers 54 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 2 Outline of Connection between SDRAM and PCI Bus Figure 3 1 shows an example of outline of the PCI interface block diagram In this figure an expansion board is connected to the PCI slot on the mother board and
65. le is controlled with auto precharge when burst length 4 BL 4 Figure 1 23 Write Command and Auto Precharge 1 tro CSH L i L i wes Bank A Bank A i A10 i DQM E ee 1 DQ 1 Active Write with command auto for bank A precharge command for bank A Active command forbankA The basic controls in write cycle are the same as in read cycle A precharge command is automatically input inside the memory at the point after the last data of write cycle is input point lt 1 gt User s Manual E0124N10 35 CHAPTER 1 SYNCHRONOUS DRAM 1 4 5 Read command and write command Figures 1 24 and 1 25 show the cases the read cycle and write cycle of the same bank only bank A in Figure 1 24 are continuously executed when CAS latency 2 CL 2 burst length 4 BL 4 Figure 1 24 Read amp Write Command 1 i i i 1 1 1 L Bank A Bank 1 1 1 ABC spo ena 1 1 1 1 1 1 1 1 1 1 Big propc xu 1 1 1 1 1 1 1 I 1 1 1 1 1 1 I 1 DQM 1 1 1 f CL 2 CL 0
66. lock is being stopped at points lt 1 gt and lt 2 gt The precharge command therefore delays for two clocks from the external CLK signal User s Manual E0124N10 41 CHAPTER 1 SYNCHRONOUS DRAM 1 4 9 Both bank ping pong control Figure 1 29 shows the case that the read cycle is continuously and alternately controlled with different banks when CAS latency 2 CL 2 burst length is 4 BL 4 Figure 1 29 Both bank Ping pong Read CKE 1 4 1 1 1 BankB BankB 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DQM 1 1 2 2 oi CXoXoo eeee Active Read Active Read i i command command command command I 1 I 1 forbankA forbankA forbankB for bank B Active commands for different banks can alternately ping pong be input Ensure that the standard value of tras MAX is Satisfied In the case of the write cycle the operations are the same except CL 0 42 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 1 4 10 CBR auto refresh Figure 1 30 shows the case that two CBR auto refresh commands are input consecutively Two CBR commands do not necessarily have to be input con
67. mple of Control Signal Changing Circuit esee 77 Figure 3 25 Circuit Diagram of Burst Write Cycle Control 78 Figure 3 26 Timings of Burst Write Cycle 79 Figure 3 27 Circuit Diagram of CBR Auto Refresh Cycle Control 80 Figure 3 28 Timings of CBR Auto Refresh Cycle 2 nennen nennen 81 Figure 3 29 Circuit Diagram of Mode Register Set Cycle Control Generation sese 82 Figure 3 30 Timings of Mode Register Set Cycle 83 Figure 3 31 Circuit Diagram of Access Cycles Other than 84 Figure 3 32 Timings of Access Cycles Other than 85 Figure 3 33 Waits from ien rp p Hte e LE RR E eter eter 87 Figures A 1 Entire Circuit DIBQEaIm sucer ere rs cct et bere tic nate etre d cv ce at etre caa 89 Figure A 2 Timings of Logic Verification Result 1 89 Figure Timings of Logic Verification Result 2 91 User s Manual E0124N10 9 Table No Title Page Table 1 1 Random Access Time and Burst Access 14 Table 1 2 Example of Clock Operating Frequency Corresponding to CAS Latency 17 Table 1 3 Access Times of SDRAM
68. n this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan Also if you export products technology controlled by U S export control regulations or another country s export control laws or regulations you must follow the necessary procedures in accordance with such laws or regulations If these products technology are sold leased or transferred to a third party or a third party is granted license to use these products that third party must be made aware that they are responsible for compliance with the relevant laws and regulations M02 01 2 User s Manual E0124N10 Readers Purpose Organization Legend Caution INTRODUCTION This User s Manual is intended for user engineers who wish to design and develop application systems using synchronous DRAM SDRAM to support high speed bus clock This User s Manual is designed for users to understand the basic concepts related to connection by introducing connection examples between SDRAM and high speed CPU This User s Manual consists of the following subjects e SDRAM PCI bus Designing of SDRAM controller connection between SDRAM and PCI bus Active low n this User s Manual active low is described with pin names and signal names postfixed with or CAS before RAS CAS before RAS refresh cycle is abbreviated as CBR re
69. nal Changing Signal 37 5 ns 75 0 ns Read cycle of SDRAM User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 8 Example of address signal changing circuit using A B signal The A B signal is connected to the SEL pin of 74157 as shown in Figure 3 22 The address signal output from the PCI bus controller is changed to row column address signal and input to SDRAM Figure 3 22 Example of Address Signal Changing Circuit Address signal of 16 M SDRAM Address signal output from 00 bus controller AD10 ADO1 AD11 02 AD12 ADO3 AD13 GND A B AD04 AD14 AD05 AD15 AD06 AD16 AD07 AD17 GND AD18 9 AD19 GND MULTIPLEXER Address signal generated in Figure 3 20 A10 11 User s Manual 0124 10 75 CHAPTER 3 DESIGNING SDRAM CONTROLLER 9 WE signal In Figure 3 23 the WE signal is generated Because the RAS signal is used as the WE signal unnecessary clocks are deleted by employing OR logic of the RAS signal and AAA signal Figure 3 23 Circuit Diagram and Timings of WE Signal Generation INPUT gt ve INPUT 37 5 ns 75 0 ns 112 Read cycle of SDRAM 5 ns 150 0 5 187 5 5 Active command Read command iPrecharge command Th 76 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 4 3 Changing control sign
70. nal is set to low SDRAM will not operate when noises are generated in control signals CS RAS CAS WE etc so that malfunctions can be prevented In the circuit example however whether accessing SDRAM or not is judged by address signal from the controller In this judging method fixing the CKE signal to high low one clock before the active command is too late in terms of timing Although it is acceptable to insert a wait in order to catch the timing inserting a wait to control the CKE signal is more disadvantageous because it delays data transfer time The CKE signal is fixed to high in this circuit Random access and burst access In the circuit example both read and write cycles are controlled with access with burst length 4 Random access and burst access can coexist to perform controls In this case the following three methods are available Method 1 is the easiest method to control 1 Method to generate the control signal of SDRAM by extending the read random access space and the write random access space in the memory space shown in Figure 3 4 and separating random access and burst access 2 Method to use the controls of the DQM signal and CKE signal 3 Method to make the setting of the mode register again In method 2 only one word of data can be controlled when setting burst length 4 and mode register This method is not recommended because the remaining three words become wait state In method 3 if random acce
71. nd for bank lt 1 gt lt 2 gt lt 3 gt lt 4 gt At point lt 1 gt an active command is input In Figure 1 20 it sets bank At point 2 a read command is input auto precharge in Figure 1 20 At point 3 a precharge command is automatically input inside the memory when the second data from the end of data is output In Figure 1 20 the third data is output for BL 4 At point 4 tnc after point lt 1 gt an active command which indicates the next operation is input For auto precharge an active command is required at point lt 4 gt because a precharge command is automatically set at point 3 When controlling the same row address signals or the same bank at points 1 and 4 active commands are again required to set the same row address signal or the same bank as point 1 at point lt 4 gt 32 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 1 4 3 Write command and precharge Figures 1 21 and 1 22 show the case that the write cycle is controlled with precharge when burst length 4 BL 4 In write cycle all CAS latency 0 CL 0 Figure 1 21 Write Command and Precharge 1 tRC t t t t 1 t 1 CKE treo i e tras tRP 11 DQM Active Write Precharge Active command command i forbankA forbankA forbank A
72. ng edge and the falling edge of one clock While the operating frequency of RDRAM is currently 300 MHz DirectRDRAM aims at 400 MHz DirectRDRAM has the highest operating frequency of all the high speed DRAM DDR SDRAM DirectRDRAM and SynchLink DRAM are next generation high speed DRAM The specifications of these next generation high speed DRAM are under examination in order to be put in practical use between 1998 and 2000 Currently high speed DRAM are gradually unified to SDRAM and these next generation high speed DRAM positioned as the successors of SDRAM DDR SDRAM Double Data Rate SDRAM DDR SDRAM is a synchronous DRAM that realizes high speed data transfer while taking over the specifications of SDRAM as much as possible Although DDR SDRAM does not have complete compatibility with SDRAM DDR SDRAM can be used with simple specification changes of the SDRAM controller since DDR SDRAM has basically the same package pin configuration and the control method as SDRAM While SDRAM adopts the single edge system which performs controls at a single edge of the basic clock DDR SDRAM adopts the dual edge system As for interface DDR SDRAM adopts SSTL interface level in order to realize a speed higher than that of SDRAM DDR SDRAM aims at operating frequency of 100 MHz SynchLink DRAM SynchLink DRAM adopts the dual edge system which performs controls at dual edges of the basic clock As for interface SynchLink DRAM adopts a dedicat
73. nk selected Figure 1 8 Row Address Strobe and Bank Active Command CLK CS RAS i CAS WE 22 User s Manual 0124 10 WE CHAPTER 1 SYNCHRONOUS DRAM 3 Precharge command Precharge command begins precharge operation of the bank selected When 10 is high all the banks are precharged regardless of the status of the address signal that controls the selection of bank When A10 is low only the bank selected by A11 signal is precharged Figure 1 9 Precharge Command CKE CS RAE CAS To 4 Read command Read command begins read operation and latches the column address signal Figure 1 10 Column Address Signal and Read Command CLK H CS RAS WE User s Manual 0124 10 CHAPTER 1 SYNCHRONOUS DRAM 5 Write command Write command begins write operation and latches the column address signal Figure 1 11 Column Address Signal and Write Command 6 CBR auto refresh command CBR auto refresh command executes CBR refresh operation The refresh address signal is automatically generated internally During certain period of time tac following this command any other commands cannot be accepted Figure 1 12 CBR Auto Refresh Command WE 24 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 7 Self refresh entry command Self refresh entry command executes self refresh operation Self refresh operation cont
74. ock of up to 29 MHz In order to support higher memory bus clock controls must be performed inserting waits so that the performance is equal to the control with the clock of 29 MHz To realize high speed access with FPM DRAM performance of the set was improved implementing complicated controls such as interleaving EDO DRAM can improve the performance of a set simply by replacing DRAM Neither SDRAM nor RDRAM have compatibility with EDO DRAM since they have different control methods and interfaces Therefore when performance better than that of EDO DRAM is needed the use of higher speed DRAM such as SDRAM and RDRAM should be considered Figure 1 2 shows that the selection of high speed DRAM is divided at approximately 66 MHz If FPM DRAM are currently used and memory bus clock of higher than 50 to 66 MHz may not be needed in the future it is recommended to use EDO RAM which has the same package pin configuration and interface as those of FPM DRAM instead of SDRAM which has different package pin configuration and interface If the memory bus clock of 100 MHz or higher will definitely be needed in the future it is recommended to use SDRAM Although the technology of FPM DRAM cannot be inherited the use of SDRAM will be advantageous in the future because industrial standardization of SDRAM is progressing and the specification to synchronize with the clock of 143 MHz or higher is under examination In Figure 1 2 the operating frequency of
75. recharge operation in SDRAM Write cycle The write cycle supports burst write cycle with burst length 4 in the same way as read cycle Refresh cycle The refresh cycle supports CBR auto refresh cycle Refresh cycle is controlled once each time a certain period elapses and then miss is performed While SDRAM performs refresh cycle the bus master performs write operation to the address in the refresh space defined in the memory space to be described later The refresh request signals are generated utilizing the change of address signal that occurs when an address in the refresh space is selected The data written during this period is defined as invalid Control must be made with software never to read out this data Mode register set cycle The mode register set cycle performs controls similar to those in the refresh cycle 3 2 3 Memory space Write cycle refresh cycle and mode register set cycle are distinguished according to the memory space Controls with the memory space enables mode register set cycle to be input at any location In addition some SDRAM products with the same capacity but different refresh period can also be supported 58 Figure 3 4 shows an example of memory space In this example the memory space is allocated as follows ADRO to ADR31 are 1 Refresh space ADRO to ADR29 are 0 ADR30 and ADR31 are 1 Mode register space Figure 3 4 Example of Memory Space of PCI Controller ADR31 ADR30 ADR29 AD
76. ress signal input method while the address signal output from the PCI controller does not support this system 5 Control signal generation circuit This is the most important circuit in Figure 3 2 It generates all the control signals of SDRAM For example when the control signal generation circuit receives directions for various controls from the select circuit it immediately generates the control signal to control SDRAM 3 2 2 State diagram of SDRAM controller The following explains using the state diagram the method by which the SDRAM controller controls SDRAM In the circuit example the control with burst length 4 which is the most basic burst length Burst length 1 and burst length 4 can coexist to perform controls When the same row address signal is controlled hit it is not necessary to input the row address miss again In this circuit example however miss is always performed even after a hit Figure 3 3 State Diagram of SDRAM Controller CPU PCI controller Idle state SDRAM Precharge state SDRAM Burst read cycle BL 4 SDRAM Burst write cycle BL 4 SDRAM CBR auto refresh cycle SDRAM Mode register User s Manual E0124N10 57 1 2 3 4 CHAPTER 3 DESIGNING SDRAM CONTROLLER Read cycle The read cycle supports the burst read cycle of burst length 4 After burst read cycle miss must always be performed when controlling p
77. secutively Figure 1 30 CBR Auto Refresh CKE Boe cq eap 4 tlf RAS 1 CAS i Jj Neo peer puppe ec 11 DQM l 0 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1 Allbank CBR auto CBR auto Active precharge refresh refresh command command command command forbankA lt gt lt 2 gt When inputting CBR auto refresh command at point lt 2 gt bank precharge command must be input tre before inputting CBR auto refresh command point lt 1 gt An active command to indicate the next operation can be input tnc after CBR auto refresh command is input User s Manual E0124N10 43 2 5 This chapter provides outline of PCI bus The specifications of PCI bus is subject to change without notice Consult PCI Special Interest Group to acquire the latest specifications of the PCI bus before starting designing work 2 1 Outline of PCI Bus 2 1 4 PCI bus Currently the PCI bus is widely adopted as a high speed I O bus interface The main stream of data transfer time of the PCI bus is 132 Mbytes s and it operates in synchronization with a bus clock of 33 MHz The PCI bus requires a device for the bridge PCI bridge between the local bus and the PCI bus The use of this bridge makes the
78. ss and burst access are performed alternately each setting must be made again This method therefore is not recommended either User s Manual 0124 10 4 5 CHAPTER 3 DESIGNING SDRAM CONTROLLER When the bus master abruptly inserts a wait In the circuit example if the bus master inserts an unexpected wait SDRAM will malfunction When the bus master accesses SDRAM therefore the bus master side must perform controls with the wait number defined in advance In order to support the unexpected wait insertion from the bus master the method to use the CKE signal is easy This is enabled by setting the inverted signal of the IRDY signal as the CKE signal during data transfer cycle Judging how many waits the bus master has inserted the cycle currently being performed must be extended for the number of cycles for which waits are inserted Figure 3 33 Waits from Bus Master Ti T2 13 14 T5 16 7 18 19 T2 TS FRAME 7 From bus master yee From bus master 6 __ From bus master COY IRDY From bus master TRDY From target DEVSEL From target wes E o DE GD A Insert Insert Insert Insert wait wait wait wait For example in the case of read cycle in Figure 3 7 the read cycle is controlled using ten cycles When one wait
79. t delays the read command to point 3 and satisfies the standard value of tras is required In this case a precharge command is automatically set at point lt 4 gt In the case of the write cycle the operations are the same except CL 0 38 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 1 4 7 Merits and demerits of auto precharge Table 1 8 Merits and Demerits of Each Type of Precharge Precharge Method Merits Demerits Auto precharge A precharge command is automatically input if a A precharge command is automatically input precharge command is not input Inputting when tras cannot be observed Figure 1 26 precharge command is not required etc or when a precharge command is not required when accessing the same row address A separate control is needed Precharge A precharge command can be input at any It must be judged whether a precharge timing tras after the active command command is required or not 1 Auto precharge In auto precharge a precharge command is automatically input inside the SDRAM and not required to be input from the external of the memory When tras cannot be observed as shown in Figure 1 26 however the control that delays the auto precharge command is separately required In addition when continuously accessing the same row address signal it is essentially not required to re input an active command In auto precharge it is required to re input an active command of the same row address
80. th 4 in Figure 2 8 The length of the data however must be the same between the device to send the data and the device to receive the data The length of the data is commonly burst length 4 Figure 2 8 Burst Read Cycle and Burst Write Cycle Read cycle Write cycle 1 T1 T2 T3 T4 T5 T6 T7 T1 T2 T3 T4 T5 T6 1 From bus master AD From bus master 1 Erom busitnaster WC s IRDY 1 From bus master From target l DEVSEL a From target Data Data Data Data i transfer transfer transfer transfer input input input input i output output output output 1 1 transfer transfer transfer transfer I 1 1 1 1 End of 1 1 1 1 l 1 Data Data Data Data 1 1 Endof Startof i i read write cycle cycle Start of read cycle Write cycle User s Manual 0124 10 53 CHAPTER 3 DESIGNING SDRAM CONTROLLER This chapter describes the designing of the SDRAM controller to be connected to the PCI bus interface The memory mentioned is specified to SDRAM Centering on SDRAM the outline and points of designing a SDRAM controller that is required to connect the PCI slot and SDRAM Descriptions such as read and write operations mean the read and wr
81. the read command is input until data is output The value of CAS latency depends on the clock operating frequency and the speed grade of SDRAM Table 1 7 Setting of CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved 4 Options Reserved Secured for future extension of specifications All of these addresses must be fixed to low User s Manual 0124 10 29 CHAPTER 1 SYNCHRONOUS DRAM 1 4 Operation Timing of SDRAM The following explains the series of operation of SDRAM using each timing 1 4 4 Read command and precharge Figures 1 18 and 1 19 show the case that the read cycle is controlled with precharge when CAS latency 2 CL 2 burst length 4 BL 4 Figure 1 18 Read Command and Precharge 1 1 1 1 tre 1 1 1 1 pe T T T T T T T j trcp x i o te 1 1 wet AH A10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DQM 2 Z 1 1 1 1 1 1 1 Active Precharge Active command forbankA forbankA i forbankA forbankA lt 1 gt lt 2 gt lt 3 gt lt 4 gt At point lt 1 gt an active command is input When A11 is low the active command controls bank A and when A11 is high it con
82. times such as random access time On the other hand the burst access time of SDRAM is faster than that of the conventional DRAM because SDRAM has adopted technologies such as pipeline system which are different from those of the conventional DRAM In Figure 1 3 there are portions shown with the solid line and that shown with the broken line The portion shown with solid line indicates that the capacity of DRAM is 16 Mbits or more The portion shown with the broken line indicates that the capacity of DRAM is at most 4 Mbits In terms of the burst cycle time EDO DRAM is capable of synchronization with the clock of 13 3 ns 75 MHz This value is considered as the limit of EDO DRAM It is already planned to make SDRAM synchronize with the clock of 7 ns 143 MHz It is also under consideration to make SDRAM synchronize with the clock of 200 MHz or higher in the future The improvement of system performance can be expected in designing a system with fast memory clock of 75 MHz or higher by adopting SDRAM instead of EDO DRAM 16 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM 1 2 2 Features of SDRAM The following explains the features of SDRAM 1 Synchronous operation SDRAM latches each control signal at the rising edge of basic input clock and inputs outputs data in synchronization with the clock signal Controls are made easier by synchronizing the clock with the system memory clock 2 Controls with commands command is a combination of lo
83. trols bank B In Figure 1 18 it sets bank A At point lt 2 gt after point lt 1 gt a read command is input When A10 is low the read command controls precharge and when A10 is high it controls with auto precharge In Figure 1 18 it sets precharge At point lt 3 gt tras after point lt 1 gt or the point where the second data from the last is output In Figure 1 18 whichever later of the points where the third data is output because BL 4 a precharge command is input At point lt 4 gt whichever later of after point 1 or tre after point lt 3 gt an active command which indicates the next operation can be input In Figure 1 18 the active command for bank A is input but the active command for bank B can also be input Note that a precharge command is required at least trp before an active command is input 30 User s Manual E0124N10 CHAPTER 1 SYNCHRONOUS DRAM To continuously output data of the same row address in the same bank the data is output at point lt 3 gt if a read command is input at point lt 2 gt so that the data can continuously be output Figure 1 19 Read Command and Precharge 2 CKE RASE M a wee AT Ac e ee DQM i m CL 2 jj __ 2 jj 4 Active Read Read Precharge i command
84. uired in mode register set command as well as in refresh cycle The mode register set cycle is the same as the write cycle because the mode register set cycle is multiplexed with the write cycle The reason for this is the same as in the case of CBR auto refresh cycle 64 User s Manual E0124N10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 3 5 Initialization cycle As shown in 1 4 3 Write command and precharge SDRAM requires initialization when the power is turned on Initialization of SDRAM can be controlled with software The following shows the procedure of initialization 1 Do not access SDRAM until 100 us from power 2 Select refresh space in the memory space refer to Figure 3 4 twice consecutively and then execute CBR auto refresh cycle twice consecutively Execution of these two operations enables generation of initializing cycle easily with software so that initialization of SDRAM can be executed without an initialization signal generation circuit User s Manual E0124N10 65 CHAPTER 3 DESIGNING SDRAM CONTROLLER 3 4 Examples of Connection Circuit between SDRAM and PCI Bus This section introduces examples of connection circuits between SDRAM and the PCI bus using circuit diagrams and timing charts of the logic verification result The timing charts of the logic verification result have taken propagation delay in consideration and postfixed to pin names and signal names in the diagram indicate active
85. until the target sets TRDY to low for the first data transfer This is 2 clock period in read cycle and a 1 clock period in write cycle User s Manual E0124N10 51 2 5 2 2 5 Random access In read cycle turn around cycles must be inserted between address signals and data inputs in write cycle turn around cycles are not required Compared to write cycle therefore read cycle has more clocks read cycle consists of four clocks while write cycle consists of three clocks Figure 2 7 Random Access Cycle Read cycle Write cycle 1 I 219 18 lt TH FRAME 1 i I 1 1 From bus master L l IN 1 1 1 1 I AD From bus 2 I 1 I 1 I 1 C BE amp From bus master lt 2 1 1 1 1 1 1 1 IRDY From bus master i TRDY From target DEVSEL qur hp From target i cycle cycle 1 I Data transfer 52 User s Manual E0124N10 2 5 2 2 6 Burst access In burst access turn around cycles must be inserted similarly to random access in write cycle turn around cycles are not required Compared to write cycle therefore read cycle has one more clock There is no limitation for the number of burst access burst leng
86. ure 1 18 Read Command and Precharge 1 30 Figure 1 19 Read Command and Precharge 2 31 Figure 1 20 Read Command and Auto Precharge sessssssssssssseeeeeeeneeenneeenne nnne nennen ener 32 Figure 1 21 Write Command and Precharge 1 esses enne nnne nnne neret nennen nennen nene 33 Figure 1 22 Write Command and Precharge nnne nent 34 Figure 1 23 Write Command and Auto 35 Figure 1 24 Read amp Write Command 1 00 4 0 0 0000 0000 nnnm rennes nnns enne 36 Figure 1 25 Read amp Write Command 2 37 Figure 1 26 Read Command and Auto Precharge sessssssssssssseeeeeenee ennemis nennen enne 38 Figure 1 27 Temporary Stop of Clock in Read Cycle 40 Figure 1 28 Temporary Stop of Clock in Write Cycle sessessssseeeeneeeeeeeeeeneeennnee nnne nennen nene 41 Figure 1 29 Both bank Ping pong 42 Figure 1 30 CBR Auto oit ei eee ro ce Ret Dir ets 43 Figure 2 1 Master and Target iui cette Ree ERR ee eR SCR eee FUR n SUR 46 Figure 2 2 Turn around Cycle of Each Phase
87. vel of CKE and CS signals when Vcc gt Vcc after power supply voltage is stabilized After precharge is completed two or more CBR auto refresh must be performed After two or more CBR auto refresh are completed the mode register can be set The mode register set command can be input between the completion of precharge and the execution of CBR auto refresh Figure 1 16 Initialization of SDRAM Voc Voc MIN 3 TET MEE l 1 CS l 1 RAS 1 CAS 5 WES tf 4 A11 A10 1 1 DOM i 100 Allbanks First 2nd Mode Operation longer pause precharge CBR auto auto register set guarantee command refresh refresh command period User s Manual E0124N10 27 CHAPTER 1 SYNCHRONOUS DRAM 1 3 4 Setting of mode register Mode register must be set to specify the operation method of SDRAM The setting must be performed after power on before the actual operation starts Before setting the mode register all banks both banks precharge command must be completed And then the mode register is set using the mode register set command To change the setting the setting must be performed again The resetting of the mode register can be performed even while SDRAM is operating Figure 1 17 Writing Mode Register cup quip eq A10 f 1 1 1 D
88. write operations using the signals generated utilizing the change of address signals from the PCI controller This circuit also defines which SDRAM is to operate when there are more than one SDRAM Refresh control circuit A circuit to generate the signals to control the refresh operation of SDRAM Refresh operation is controlled with software using memory space the details are explained in 3 2 3 Memory space Software selects memory refresh space set in advance in the memory space of the CPU after a certain period of time elapses during refresh period This circuit generates start signal of refresh operation with the change of address signal when the memory refresh space is selected and Direct control signal generation circuit to generate control signals required for refresh operation Address signal data switching circuit This circuit performs the control of separating the multiplexed signal of address and data output from the controller into address signal and data when inputting it to SDRAM This is because SDRAM does not multiplex address signal and data while the PCI bus specification does User s Manual 0124 10 CHAPTER 3 DESIGNING SDRAM CONTROLLER 4 Row column address signal switching circuit This circuit performs the control of separating the address signal output from the PCI controller into row address and column address when inputting it to SDRAM This is because SDRAM adopts address multiplexed system for the add

Elpida: SDRAM Application Notes

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