Hardware Manual
Contents
1. Accessing the Analog World CNS High Speed Digital I O Connector Connector CNB provides 40 digital I O lines along with a 5V pin and ground pins These signals are 3 3V tolerant The signal names reflect the signal names I n the Xilinx UCF file with the device pin out CNB is attached to Bank 1 and supports any of the Spartan 6 I O Standards that use a 3 3V Vcco and no reference voltage This includes LVTTL LVCMOS33 input and output and LVDS 33 input LVDS output is not supported in Bank 1 Table 5 CN8 I O Pin Assignments Ponz nj 4 3 Por pit Porz ni2 Porz np 8 op ops GND Porz np D LPot n 14 18 Por pi5 Porz EL DS o D s Por n 22 21 Ponz np 24 Port n 10 Port p 10 Port2 p 8 29 GND Port2 n 12 82 Port2 n 14 Port2 n 15 GND 40 39 GND Port2 n 16 42 Port2 n 18 L Port2 n 19 4 RTD Embedded Technologies Inc www rtd com 13 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World CN9 Digital UO Connector Connector CN9 provides 24 digital I O lines along with a 5V pin and ground pins All I O have pull up pull down resistors that are controlled by jumper options also shown in the table These signals are 5V tolerant The signal names reflect the signal names in the Xilinx UCF file with the device pin out CN9 is attached to Bank 0 and supports any of the Spartan 6 I O Standards that use a 3 3V Vcco2. Accessing the Analog World 1 Introduction 1 1 Product Overview The FPGA35S6 series of FPGA boards are designed to provide a platform to create any digital I O that is required for your application It interfaces with the PCle bus and features a Xilinx Spartan 6 FPGA with a 27 Mhz oscillator and 1Gb of DDR2 SDRAM The FPGA35S6046 and FPGA35S6101 provide 32 RS 232 422 485 I O 24 5V tolerant I O and 40 3 3V tolerant high speed I O 1 2 Board Features e Xilinx Spartan 6 System level features o XC6SLX45T FPGA35S6046HR 43 661 Logic Cells 2 489 kb of internal RAM e 116 18Kb 2088 Kb Max Block RAM e 401 kB Distributed RAM o XC6SLX100T FPGA35S6101HR 101 261 Logic Cells 5 000 kb of internal RAM e 268 18Kb 4 824 Kb Max Block RAM e 976 kB Distributed RAM o RAM hierarchical memory Each block RAM has two independent ports Programmable Data Width o Integrated Endpoint block for PCI Express o Integrated Memory Controller 1 Gb of DDR2 SDRAM Supports access rates of up to 800Mb s o Dedicated carry logic for high speed arithmetic o Abundant logic resources with increased logic capacity Optional shift register or distributed RAM support Efficient 6 input LUTS UT with dual flip flops o Four dedicated DLLs for advanced clock control Phase shift input clock by 0 90 180 270 Multiply input clock by 2 to 32 Divide input clock by 1 to 32 e Digital UO Connectors o 32 RS 232 422 485 I O Four connect
3. This register reads the inputs of CN13 RS 232 422 485 transceivers B0 com4 rxd B1 com4 cts B2 com4 dsr B3 com4 dcd B7 com4 ri RTD Embedded Technologies Inc www rtd com 32 Accessing the Analog World FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 7 Troubleshooting If you are having problems with your system please try the following initial steps e Simplify the System Remove modules one at a time from your system to see if there is a specific module that is causing a problem Perform you troubleshooting with the least number of modules in the system possible e Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorrectly If problems persist or you have questions about configuring this product contact RTD Embedded Technologies via the following methods Phone 1 814 234 8087 E Mail techsupport grtd com Be sure to check the RTD web site http www rtd com frequently for product updates including newer versions of the board manual and application software RTD Embedded Technologies Inc www rtd com 33 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 8 Additional Information 8 1 PC 104 Specifications A copy of the latest PC 104 specifications can be found on the webpage for the PC 104 Embedded Consortium WWW pc104
4. port2 19 Indicates the direction of each pin 0 input 1 output 6 1 13 R DDR RD DATA READ Reads the data of the DDR2 SRAM at R DDR ADDR location A read is performed by writing address to R DDR ADDR 6 1 14 R DDR WR DATA READ WRITE Writes data in registry to location R DDR ADDR of the DDR2 SRAM 6 1 15 R DDR ADDR READ WRITE Address pointer of the DDR2 SRAM RTD Embedded Technologies Inc www rtd com 28 FPGA35S6046 FPGA35S6101 User s Manual 6 1 16 R DDR STATUS READ This is a status register for the DDR2 memory interface BO Read error B1 Read overflow B2 Read empty B3 Read full B4 Write error Bo Write underrun B6 Write empty B7 Write full B 14 8 Read count B 22 16 Write count B 24 Command full B 25 Command empty B 31 Calibration done 6 1 17 R COM1 OUT READ WRITE This register sets the configuration and outputs of CN10 RS 232 422 485 transceivers B0 com txd B1 com rts B2 com1 dtr B8 Com enable B9 com1_mode0 B10 com model B11 com mode2 B12 com dir B13 com1 dir2 B14 com1 slew B15 com1 term RTD Embedded Technologies Inc www rtd com 29 Accessing the Analog World FPGA35S6046 FPGA35S6101 User s Manual 6 1 18 R COM IN READ This register reads the inputs of CN10 RS 232 422 485 transceivers B0 com1 rxd B1 com1 cts B2 com1 dsr B3 com1 dcd B7 com ri 6 1 19 R COM2 OUT READ WRITE This register se
5. 4 Steps for Installing E 4 IDAN Connections 4 1 Module Handling Precautions sse eee eee eee 4 2 Physical Is MIS EET EET 4 3 Connectors and Jumpers P2 RS 232 422 485 Transceiver Connector P3 Digital UO Connector P4 High Speed Digital I O Connector 4 3 1 Bus Connectors CN1 Top amp CN2 Bottom PCle Connector 4 3 2 Jumpers JP4 JP5 JP6 Pull up Pull down Jumper JP1 Embedded Programmer Enable 4 3 3 Solder Jumper B1 Pull up Voltage 4 4 Steps for Installing e 5 Functional Description 5 2 SGT GE MN 5 3 Eet 5 4 DOR o 50 Ditar esr 5 7 Embedded Digilent USB JTAG Programmer RTD Embedded Technologies Inc www rtd com IV Accessing the Analog World FPGA35S6046 FPGA35S6101 User s Manual 6 Register Address Space 6 1 BARU FPGA Example Register Map 6 1 1 R ID Read 6 1 2 R STATUS Read 6 1 3 R EEPROM Read Write 6 1 4 R_PORT1_IN Read 6 1 5 R_PORT1_OUT Write 6 1 6 R_PORT1_DIR Read Write 6 1 7 R_PORT2L_IN Read 6 1 8 R_PORT2L_OUT Write 6 1 9 R_PORT2L_DIR Read Write 6 1 10 R PORT2H IN Read 6 1 11 R_PORT2H_OUT Write 6 1 12 R PORT2H DIR Read Write 6 1 13 R DDR RD DATA Read 6 1 14 R DDR WR DATA Read Write 6 1 15 R DDR ADDR Read Write 6 1 16 R DDR STATUS Read 6 1 17 R COM1 OUT Read Write 6 1 18 ROM IN Read 6 1 19 R COM2 OUT Read Write 6 1 20 ROM IN Read 6 1 21 R COM3 OUT Read Write 6 1 22 R_C
6. ES GND port1 n 10 Oo CN3 2 CN3 3 on HRP HS HEHEHE HER BLO DO CO OO CO CD GC GO GC GD DO RO RO TROT N52 RO 1 1 YS 1 DOBRO BRO JS gt gt S ma Oy Oe em l N O1 amp Go Ro O O CO N OO O1 B GO RO CO CO CO NJ Od O1 B GO RO CO CO CO N OO AI B G RO CO CO N OO amp Go RO oO Row1 ES Jg 22 Lo 4 PEN NE 3 LE Jg AL ECH E ER NN L LONE EIN 26 NENNEN EN BL O 7 E p 1 ERE NN 83 p EZ NN O E e ERR 130 HEN NEN 10 WE EC Lc EUN PEN 3 NENNEN NEN JL 99 Lo c H JL y 9 SENEC HL 35 EMEN EDEN ER 136 C 16 o I NENNEN NENNEN JL ECH O Al 18 TI 39 OS OS io Z Z Z O J O Oo 39 FPGA35S6046 FPGA35S6101 User s Manual Table 11 P3 Pin Assignments GND CN39 62 Dag CN3 10 Reserved 42 Reevd P4 High Speed Digital I O Connector Connector Part 4 VALCONN HDB 62S Mating Connector VALCONN HDB 62P Accessing the Analog World Connector P4 provides 40 digital I O lines along with a 5V pin and ground pins These signals are 3 3V tolerant The signal names reflect the signal names n the Xilinx UCF file with the device pin out P4 is attached to Bank 1 and supports any of the Spartan 6 I O Standards that use a 3 3V Vcco and no reference volt
7. and no reference voltage This includes LVTTL LVCMOS33 and LVDS 33 input and output Table 6 CN9 I O Pin Assignments o ES ES pott pg port p 4 port1 n 4 24 23 pott nB J 29 saat 33 pott pi 39 pott nfo E 43 pott 10 CRT GND port n 3 CN10 CN11 CN12 CN13 RS 232 422 485 Transceiver Connectors These connectors each provide configurable RS 232 422 485 transceivers The pin configuration and associated FPGA signals are shown in the Table below For other modes and information on how to configure the port see Section 5 6 on page 25 The signal names reflect the signal names in the Xilinx UCF file with the device pin out CN10 is associated with the com signals CN11 with the com2 signals CN12 with the com3 signals and CN13 with the com4 signals These signals are attached to Bank 2 of the FPGA and should be configured as LVCMOS33 Table 7 CN10 CN11 CN12 CN13 I O Pin Assignments com der RX 2 1 com td TX 4 3 com xd RX com cis RX 6 5 com td TX com ri RX com dtr TX BND D 10 9 GND RTD Embedded Technologies Inc www rtd com 14 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 3 3 2 BUS CONNECTORS CN1 Top amp CN2 Bottom PCle Connector The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the
8. n6 sg L J Led bed bed bed Lyd bed bed LJ GJ LJ Led LJ Led Led Led bed Led Led Led T RTD Embedded Technologies Inc uH a EE nu niii 2 nu U7 NE EE Ld c HH 2 III m P l EH ess E nima cniin 2 E EUN MM 23 Cu Cum m e ej ITT nia 2 d H H DI CW nui mnn 9df uu Baa vinnm a UUO23 DU M MAMA CN1 Pann In a EUN ninna Figure 1 Board Dimensions RTD Embedded Technologies Inc www rtd com 11 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 2 2 Connectors and Jumpers CNR High Speed Digital UO CN9 Digital UO ch CNS TEE TEO OPEL ED LP CPE E OTT CET CN10 RS 232 422 485 M RTD Embedded Technologies Inc BH se UZ CN11 RS 232 422 485 ELE JP4 JP5 amp JP6 Pull up Pull down Jumper BEES Sr CN12 RS 232 422 485 E od Ne K d A CN13 RS 232 422 485 CN3 Programming Header Jag mom JP1 Embedded Programmer CN1 amp CN2 PCle Connector Enable B2 on bottom side Figure 2 Board Connections 3 3 1 EXTERNAL I O CONNECTORS CN3 Xilinx JTAG Programming Header Connector CN3 provides a connection to the Xilinx JTAG programming header The pin assignment for CN3 is shown below This connector header mates with the Xilinx OEM programming cable Table 4 CN3 Programming Header RTD Embedded Technologies Inc www rtd com 12 FPGA35S6046 FPGA35S6101 User s Manual
9. the functional block diagram of the FRGA35S6 The various parts of the block diagram are discussed in the following sections 0 CN11 CN12 CN13 PCle x1 igital UO CN9 jh Speed Digital UO CNS I Figure 6 FPGA35S6 Block Diagram 5 2 Oscillator The FPGA35S6 features a 27Mhz oscillator for clock based operations in the FPGA 0 3 EEPROM The FPGA35S6 features a 256 x 16 SPI EEPROM ATMEL AT93C66A For information on the AT93C66A refer to http www atmel com 9 4 DDR2SRAM The FPGA35S6 features a 1Gb DDR2 SRAM MT47H64M16HR 25E This is interface to the Spartan 6 FPGA using Xilinx Memory Interface Generators MIG core The example FPGA code has demonstrated how to use this core in a FPGA design RTD Embedded Technologies Inc www rtd com 24 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 5 5 Digital I O The FPGA3556 digital I O on connector CN9 uses the circuitry shown below to level shift the input voltage from 5V to 3 3V allowing the I O to be 5V tolerant CN4 CN9 Xilinx Spartan 6 URAN ee Figure 7 CN9 Digital I O Circuitry 5 6 RS 232 422 485 Transceivers The RS 232 422 485 transceivers on this board all it to interface with a variety of serial port standards incremental encoders and other devices The transceivers are highly configurable from the FPGA fabric The various modes are show in Table 15 below The modes are selected using the com mode 2 0 signals i
10. FPGA35S6046HR FPGA35S6101HR FPGA Module User s Manual BDM 610010048 Rev A mum um erem F Bu a chu UTI Mlini W RTD Embedded Technologies Inc cw e gt P v D AS SL ree n d HTH TTI RTD Embedded Technologies Inc AS9100 and ISO 9001 Certified RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Ka V asooo lt V 180 8001 JU Accessing the Analog World Revision History Rev A Initial Release Advanced Analog I O Advanced Digital I O aAIO aDIO a2DIO Autonomous SmartCal Catch the Express couModule dspFramework dspModule expressMate ExpressPlatform HiDANplus MIL Value for COTS prices multiPort PlatformBus and PC 104EZ are trademarks and Accessing the Analog World dataModule IDAN HiDAN RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc formerly Real Time Devices Inc PS 2 is a trademark of International Business Machines Inc PCI PCI Express and PCle are trademarks of PCI SIG PC 104 PC 104 Plus PCI 104 PCle 104 PCI 104 Express and 104 are trademarks of the PC 104 Embedded Consortium All other trademarks appearing in this document are the property of their respective owners Failure to follow the instructions found in this manual may result in damage to the product
11. JUMPER B1 Pull up Voltage Solder jumper B1 is used to set the pull up voltage for JP4 JP5 and JP6 Table 14 B1 Pull up Voltage ets Pull up voltage to 3 3V Sets Pull up voltage to 5V RTD Embedded Technologies Inc www rtd com 22 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 44 Steps for Installing Always work at an ESD protected workstation and wear a grounded wrist strap Turn off power to the IDAN system Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busses used by the peripheral cards are connected to the couModule Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack Gently and evenly press the module onto the IDAN system If any boards are to be stacked above this module install them Finish assembling the IDAN stack by installing screws of an appropriate length Attach any necessary cables to the IDAN system Re connect the power cord and apply power to the stack Boot the system and verify that all of the hardware is working properly tO oo Job St n SS qux cx _ r Figure 5 Example IDAN System RTD Embedded Technologies Inc www rtd com 23 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 5 Functional Description 5 1 Block Diagram The Figure below shows
12. OM3_IN Read 6 1 23 R COMA OUT Read Write 6 1 24 R COMA IN Read 7 Troubleshooting 8 Additional Information 8 1 PC 104 Specifications 8 2 PCI and PCI Express Specification 8 3 Serial Port Transceivers H Limited Warranty RTD Embedded Technologies Inc www rtd com Accessing the Analog World FPGA35S6046 FPGA35S6101 User s Manual Table of Figures Figure 1 Board DIMENSIONS MN omm 11 HEEN 12 gie iz gll la le Geen eee cee eee eee eee ee ee ee ee ee 16 Fig re EE 17 Figure 5 Example Eege 23 Fouet FPGA3596 BIOCK el T 24 Faure EC Dota VOC INCUN Y E 25 Table of Tables Table Ordening ODONIS essc E TTD A N N 9 Tade 2 Oporaing e e s 10 Ee Ee Tele Ee 10 IE ie rz gom TEE 12 Table 5 CN8 I O Pin Assignments eee eee e 13 Table ONO Os CT t Ms t RON c P 14 Table 7 CO ev Re v CN13 VO PImASSIOTITIGDIS E 14 Table 8 Pull up Pull down Jumper Te el EE 15 Table 9 B1 Pull up Voltage p M 15 Table 10 P2 Pin ell 18 TALEE O nell 19 Table 12 PA sd sne 20 Table 13 Pull up Pull down Jumper options sss esse eee eee eee 22 Table M B1 Pul up e Le TE P 22 Eelere 25 Table 16 PRGA Example ee MISI EE 27 Accessing the Analog World RTD Embedded Technologies Inc www rtd com vi FPGA35S6046 FPGA35S6101 User s Manual
13. PC 104 Express Specification See PC 104 Specifications on page 34 The FPGA35S6 is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector 3 3 3 JUMPERS JP4 JP5 JP6 Pull up Pull down Jumper JP4 JP5 and JP6 are 3 pin two position jumpers that are used to set pull up or pull downs options on the I O signal lines of CN9 Refer to Table 6 to determine which I O pins are effected by each jumper Table 8 Pull up Pull down Jumper options JO is pulled up to 3 3V or 5V Set by B1 and B2 UO is pulled down to GND I O has no pull up pull down JP1 Embedded Programmer Enable Installing JP1 will attach the embedded programmer to the JTAG chain See Section 5 7 on page 26 for more details 3 3 1 SOLDER JUMPER B1 Pull up Voltage Solder jumper B1 is used to set the pull up voltage for JP4 JP5 and JP6 Table 9 B1 Pull up Voltage ets Pull up voltage to 3 3V Sets Pull up voltage to 5V RTD Embedded Technologies Inc www rtd com 15 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 3 4 Steps for Installing Always work at an ESD protected workstation and wear a grounded wrist strap Turn off power to the PC 104 system or stack Select and install stand offs to properly position the module on the stack Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busse
14. T User Programmable FPGA Module IDAN FPGA35S6046HR PCle 104 Spartan 6 XC6SLX45T User Programmable FPGA Module in IDAN enclosure IDAN FPGA35S6101HR_ PCle 104 Spartan 6 XC6SLX100T User Programmable FPGA Module in IDAN enclosure A Starter Kit is available for any of the options which includes the appropriate programming cable Contact RTD Sales for more information The FPGA35S6 is a general use FPGA module allowing you to design your own FPGA It has support for custom oscillator and larger Xilinx Spartan 6 FPGAs Please contact RTD Embedded Technologies for more information on custom FPGA35S6 products and custom FPGA designs The Intelligent Data Acquisition Node IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged 104 stack This module can also be incorporated in a custom built RTD HIDAN or HiDANplus High Reliability Intelligent Data Acquisition Node Contact RTD sales for more information on our high reliability systems 1 4 Contact Information 1 4 1 SALES SUPPORT For sales inquiries you can contact RTD Embedded Technologies sales via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail sales rtd com 1 4 2 TECHNICAL SUPPORT If you are having problems with you system please try the steps in the Troubleshooting section of this manual For help with this product or any other product made by RTD
15. Technologies Inc www rtd com 18 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World P3 is attached to Bank 0 and support any of the Spartan 6 I O Standards that use a 3 3V Vcco and no reference voltage This includes LVTTL LVCMOS33 and LVDS_33 input and output Connector P3 also provides a connection to the Xilinx JTAG programming header This connector header mates with the Xilinx OEM programming cable through an adapter cable The adapter cable is provided when purchasing the Starter Kit RTD Embedded Technologies Inc www rtd com 19 Table 11 P3 Pin Assignments Row1 Row 2 porti po O port1_n 0 aa F L NENNEN pont p 2 2 porti n 2 porti p 3 NENNEN porti n 3 BEEN _ porti p 4 porti n 4 L GND port p 5 L porti n 5 porti p 6 port n 6 porti p 7 GND port n 7 EE porti p 8 porti n 8 __ porti p 9 C GND N port oi por n 1 H c v RO pori p pori al poti p f poti af poti p poti np portt_p 3 poti nj porti p 4 pori nl GND pori p 5 poti n port p poti al poti p GND poti all poti p porti n B poti p DND port n 9 GND BEEN port1 p 10 mE port p 11 NENNEN port n 11 GND NINE GND Reserved jtag vref
16. age This includes LVTTL LVCMOS33 input and output and LVDS 33 input LVDS output is not supported in Bank 1 oo oo oo No No No No No No No No D NO Sec oO co Co J C On JI OO N z NEN EE p WE p NENEK p p p NEN 6 p NEN NENNEN NEN ES E NEN 9 NEN SS 10 E s n NENNEN MEN 12 12 RTD Embedded Technologies Inc www rtd com Table 12 P4 Pin Assignments co i Port2 oi Port2 ai Port2 p1 Pot n1 Port2 op Port2 n 2 Por2 ol 7 Port2 n 3 Co 10 Port2 p 4 11 Port2_n 4 12 Port2 p 5 13 Port2 n 5 14 Port2 p 6 15 Port2 n 6 16 Port2 p 7 17 Port2 n 7 18 Oo Cl 20 Port2 p 8 21 Port2 n 8 22 Port2 p 9 23 Port2_n 9 24 Port2_p 10 25 Port2 n 10 26 Port2 p 11 27 Port2 n 11 28 29 30 31 32 33 34 co C1 C1 on on qp P D P P P RO A co on iN Z Z Z Z Z Z JJ JJ JJ Port2_p 12 Port2_n 12 Port2 p 13 Port2 n 13 T Co 20 FPGA35S6046 FPGA35S6101 User s Manual Table 12 P4 Pin Assignments Port2 p 14 Port2 n 14 Port2 p 15 Port2 n 15 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x oOo D Z Z JJ Port2 p 16 Port2 n 16 Port2 p 17 Port2 n 17 Port2 p 18 Port2 n 18 Port2 p 19 Port2 n 19 5V C1 D N N Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Re
17. alog World 4 3 Connectors and Jumpers P2 RS 232 422 485 Transceiver Connector Connector Part Adam Tech DE37SD Mating Connector Adam Tech DE37PD Connector P2 provides configurable RS 232 422 485 transceivers The pin configuration and associated FPGA signals are shown in the Table below The signal names reflect the signal names in the Xilinx UCF file with the device pin out For other modes and information on how to configure the port see Section 5 6 on page 25 These signals are attached to Bank 2 of the FPGA and should be configured as LVCMOS33 Table 10 P2 Pin Assignments IDAN P2 Pin Row1 Row2 S 232 Si Com deg com1 der com1 rxd Com rtd Com Yd com1 cts com1 dtr com1 ri Board Pin CN10 1 CN10 2 CN10 3 CN10 4 CN10 5 CN10 6 CN10 7 CN10 8 CN10 9 CN11 1 CN11 2 CN11 3 CN11 4 CN11 5 CN11 6 CN11 7 CN11 8 CN11 9 CN12 1 CN12 2 CN12 3 CN12 4 CN12 5 CN12 6 CN12 7 CN12 8 CN12 9 CN13 1 CN13 2 CN13 3 CN13 4 CN13 5 CN13 6 CN13 7 CN13 8 CN13 9 n c 0 RS 232 Signal comi dcd comi dsr comi md comi rid comi txd comicts comi dr comiri com2 dod com2 dsr com2 md com2 rid com2_txd com2_cts com2 dir com2 r com3 dcd com3 der com md com3 rid com xd com3 cts com3 dir com dd com4 der com4 md com4 rid com txd com4 cts com4 dir ComM
18. described in this manual or other components of the system The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment Contents and specifications within this manual are given without warranty and are subject to change without notice RTD Embedded Technologies Inc shall not be liable for errors or omissions in this manual or for any loss damage or injury in connection with the use of this manual Copyright 2013 by RTD Embedded Technologies Inc All rights reserved RTD Embedded Technologies Inc www rtd com ii FPGA35S6046 FPGA35S6101 User s Manual Table of Contents 1 Introduction 1 1 Breil ege IE N E E 1 2 BOUF EANES 1 3 Ordenng saints 1 4 Contact IOOTITIB VOTIS E 1 4 1 Sales Support 1 4 2 Technical Support 2 Specifications 2 1 Operating SOC ICIS isses tM n pte IER MINER MUNDI 2 2 Electrical Characteristics ssssseennnenn nns 3 Board Connection 3 1 Board Handling Sir ee 3 2 We ere Ee 3 3 Connectors and Jumpers sss eee 3 5 1 External I O Connectors CN3 Xilinx JTAG Programming Header CNB High Speed Digital UO Connector CNS Digital UO Connector CN10 CN11 CN12 CN13 RS 232 422 485 Transceiver Connectors 3 3 2 Bus Connectors CN1 Top amp CN2 Bottom PCle Connector 3 3 3 Jumpers JP4 JP5 JP6 Pull up Pull down Jumper JP1 Embedded Programmer Enable 3 3 1 Solder Jumper B1 Pull up Voltage 3
19. her rights which vary from state to state RTD Embedded Technologies Inc www rtd com 35 FPGA35S6046 FPGA35S6101 User s Manual RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Represents all cpu s pres To 15 we In systems capable of hotp eri as new cpu s are detected E IDANS F rrn d mme Rs method such as ACPI for cpumask t cpu present map _ 1 EXPORT SYMBOL cpu present map ifndef CONFIG SMP Represents all cpu s that v AS9100 V 1S0 9001 Copyright 2013 by RTD Embedded Technologies Inc All rights reserved
20. n the FPGA The Table then shows the FPGA signal associated with each pin of the connector Table 15 Transceiver Configuration eon ded RX DOD com dsr RX DSR _ come RX ee Een TXD1 or o ee LD II com dcd R D com bd TX TXD com txd TX TXD1 com dcd RX Di com txd T SC com txd m qu com rtd TX RTS com dtr T TXD2 com cts RX D2 com dtr m L5 c TXD ae j XD refers PE seo ROS emt gx ms Pom abr 1x o H pep ref T x T8 rs RXD3 com dirt T D Transmitting T TXD enabled T TXD1 enabled T D1 Transmitting U D Receiving U TXD disabled U TXD1 disabled U D1 Receiving com dir2 T TXD2 enabled T D2 Transmitting T U TXD2 disabled U D2 Receiving The other signals that are used to configure the transceivers are below com enable 1 for normal operation 0 for shutdown mode com slew 1 for 250 kbps slew limiting 0 for full speed operation com term 1 to enable receiver termination RS 422 485 modes only 0 to disable termination RTD Embedded Technologies Inc www rtd com 25 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 5 7 Embedded Digilent USB JTAG Programmer This FPGA board includes an embedded Digilent JTAG programming module It connects to the host through the USB connections on the PCle Bus connectors A USB hub is also pro
21. op Output Differential Voltage RS 422 485 mode V Ri 100Q RS 422 2 0 Ri 54Q RS 485 1 5 Vem Driver Common Mode Output Voltage RS 422 485 mode 30 V rS Digital I O 0 55 V Vou Output High Voltage lo f2mACN amp CN9 26 33 V Vo Output Low Voltage lo 12mACN amp CN9 0 04 V 5V Output CN amp CNO IT T mA DDR2 Interface Access Rate 1 250 800 Mbs Note 1 Typical power consumption based on RTD s FPGA example 2 Proving by design not production tested For additionally electrical characteristic of the Spartan 6 I O refer to http www xilinx com RTD Embedded Technologies Inc www rtd com 10 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 3 Board Connection 3 1 Board Handling Precautions To prevent damage due to Electrostatic Discharge ESD keep your board in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware 3 2 Physical Characteristics e Weight Approximately 63 5 g 0 14 Ibs e Dimensions 90 17 mm L x 95 89 mm W 3 550 in L x 3 775 in W 8 550 520 26 zap sle sg sep sp asp 526 556 x sf 5360 sang xng s sf asf
22. org 0 2 PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group WWW pcisig com 0 3 Serial Port Transceivers Detailed information on the Exar SP338 serial port transceivers is available on the Exar website www exar com connectivity transceiver multiprotocol sp338 RTD Embedded Technologies Inc www rtd com 34 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 9 Limited Warranty RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies Inc This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for a Return Material Authorization RMA number This limited warranty does not extend to any products which have been damaged as a result of accident misuse abuse such as use of incorrect input voltages impro
23. ors Each connector can support a single full RS 232 port or two TX RX only ports Up to 1 Mbps in RS 232 mode Up to 20 Mbps in RS 422 485 mode ESD Protected o 245V tolerant Digital I O Selectable pull up pull down per byte Pull up can be 3 3V or 5V ESD Protected Can be used as LVDS Input Output or LVTTL Input Output o AU 3 3V tolerant High Speed UC ESD Protected Can be used as LVDS Input or LVTTL Input Output e Fully supported by Xlinx development system o ISEWebPACK free download from http www xilinx com o ISE Design Suite e Embedded Digilent amp USB JTAG Programmer o Allows programming from the host computer o Compatible with Xilinx tools including iMpact and ChipScope RTD Embedded Technologies Inc www rtd com T FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World e PCI Express Bus o PCle 104 Universal Board Interfaces with Type 1 or Type 2 bus Nore population o Provides 2 5 Gbps in each direction o in band interrupts and messages o Message Signaled Interrupt MSI support RTD Embedded Technologies Inc www rtd com 8 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 1 3 Ordering Information The FPGA35S6 series of FPGA boards is available in the following options Table 1 Ordering Options Part Number Description FPGA35S6046HR PCle 104 Spartan 6 XC6SLX45T User Programmable FPGA Module FPGA35S6101HR PCle 104 Spartan 6 XC6SLX100
24. per or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of God or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims all warranties not stated herein All implied warranties including implied warranties for merchantability and fitness for a particular purpose are limited to the duration of this warranty In the event the product is not free from defects as warranted above the purchaser s sole remedy shall be repair or replacement as provided above Under no circumstances will RTD Embedded Technologies be liable to the purchaser or any user for any damages including any incidental or consequential damages expenses lost profits lost savings or other damages arising out of the use or inability to use the product Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products and some states do not allow limitations on how long an implied warranty lasts so the above limitations or exclusions may not apply to you This warranty gives you specific legal rights and you may also have ot
25. r has the outputs to the EEPROM B0 EEPROM Serial Clock RTD Embedded Technologies Inc www rtd com 2 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World B1 EEPROM Serial Input B2 EEPROM Chip Select 6 14 R_PORT1_IN READ This is the input register for the port1 This reads the current value the I O 6 1 5 R_PORT1_OUT WRITE This is the output register for the port1 The value to be output direction must be set to output 6 1 6 R_PORT1_DIR READ WRITE This is the direction register for port Indicates the direction of each pin 0 input 1 output 6 1 7 R PORT2L IN READ This is the input register for the port low port2 0 port2 15 This reads the current value the I O 6 1 8 R PORT2L OUT WRITE This is the output register for the port low port 0 port2 15 The value to be output direction must be set to output 6 1 9 R PORT2L DIR READ WRITE This is the direction register for port2 low port 0 port2 15 Indicates the direction of each pin 0 input 1 output 6 1 10 R PORT2H IN READ This is the input register for the port high port2 16 port2 19 This reads the current value the I O 6 1 11 R PORT2H OUT WRITE This is the output register for the port high port 16 port2 19 The value to be output direction must be set to output 6 1 12 R PORT2H DIR READ WRITE This is the direction register for port2 high port2 16
26. ri GND hR RO com2 dcd com2_dsr com2_rxd com2_rtd com2 txd com2 cts com2 dtr com2 ri Oo com3_dcd com3_dsr com3_rxd com3_rtd com3_txd coma cts coma dtr com3 ri RO Cc rw com4 dcd com4 dsr com4 rxd com4 rtd com4 Yd com4 cts com4 dtr Com4 ri GND n C Oo 8 mr T me S HE CN10 1 ae CN 102 LEES NM CN10 3 RE ER CN10 4 RENE NN CN10 5 2195 3 CN10 6 4 RES CN 107 123 CN10 8 5 CN10 9 NEN NN CN111 8 CNI12 J5 CN113 7 CN114 26 CN115 8 LI CN116 as CNIIT 9 CNI18 28 CNL 10 E CNI21 J2 CN122 Mo CN123 130 CN124 ae NN CNI25 395 CN12 6 13 f CN127 1382 CN12 8 H CN129 3 CNIS1 HS 1 CN132 We EC CN133 16 CNI34 5 CNI35 EZ EMEN CNI36 E CN137 KE CN138 37 CN139 19 HR 19 P3 Digital UO Connector Connector Part VALCONN HDB 62S Mating Connector VALCONN HDB 62P Connector P3 provides 24 digital I O lines along with a 5V pin and ground pins All I O have pull up pull down resistors that are controlled by jumper options also shown in the table These signals are 5V tolerant The signal names reflect the signal names n the Xilinx UCF file with the device pin out RTD Embedded
27. s used by the peripheral cards are connected to the couModule Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack Gently and evenly press the module onto the PC 104 stack If any boards are to be stacked above this module install them Attach any necessary cables to the PC 104 stack Re connect the power cord and apply power to the stack Boot the system and verify that all of the hardware is working properly oe SS SR Ee eS _ r Figure 3 Example 104 Stack RTD Embedded Technologies Inc www rtd com 16 FPGA35S6046 FPGA35S6101 User s Manual 4 IDAN Connections 4 1 X Module Handling Precautions Accessing the Analog World To prevent damage due to Electrostatic Discharge ESD keep your module in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the module by the aluminum enclosure and do not touch the components or connectors Handle the module in an antistatic environment and use a grounded workbench for testing and handling of your hardware 4 2 Physical Characteristics e Weight Approximately 0 42 Kg 0 92 Ibs e Dimensions 152mm L x 130mm W x 34mm H 5 983 L x 5 117 W x 1 339 H 5 983 A 152mm 5417 130mm Figure 4 IDAN Dimensions RTD Embedded Technologies Inc www rtd com 17 FPGA35S6046 FPGA35S6101 User s Manual Accessing the An
28. served CO co RO Cc Ro 3 LI y ECH BEE E 3 y o 995 EM NEN RN 35 j 956 ml jq 3 Lo 97 106 II 3 y E 5e Eg 38 E M 18 LL o 39 80 E NN NN NEST o 4 Ld e 20 j poe c Li e 21 pue Z O 42 RTD Embedded Technologies Inc www rtd com 21 Accessing the Analog World FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 4 3 1 BUS CONNECTORS CN1 Top amp CN2 Bottom PCle Connector The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the PC 104 Express Specification See PC 104 Specifications on page 34 The FPGA35S6 is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector 4 3 2 JUMPERS JP4 JP5 JP6 Pull up Pull down Jumper JP4 JP5 and JP6 are 3 pin two position jumpers that are used to set pull up or pull downs options on the I O signal lines of CND Refer to Table 11 to determine which I O pins are effected by each jumper Table 13 Pull up Pull down Jumper options JO is pulled up to 3 3V or 5V Set by B1 and B2 UO is pulled down to GND I O has no pull up pull down JP1 Embedded Programmer Enable Installing JP1 will attach the embedded programmer to the JTAG chain See Section 5 7 on page 26 for more details 4 3 3 SOLDER
29. ts the configuration and outputs of CN11 RS 232 422 485 transceivers B0 com2 txd B1 com2 rts B2 com2 dtr B8 com2 enable B9 com2_mode0 B10 com2 model B11 com2 mode2 B12 com2 dir B13 com2 dir2 B14 com2 slew B15 com2 term 6 1 20 R COM IN READ This register reads the inputs of CN11 RS 232 422 485 transceivers B0 com2 rxd B1 com2 cts B2 com2 der B3 com2_dcd B7 com2 ri RTD Embedded Technologies Inc www rtd com 30 Accessing the Analog World FPGA35S6046 FPGA35S6101 User s Manual 6 1 21 R COM3 OUT READ WRITE This register sets the configuration and outputs of CN12 RS 232 422 485 transceivers B0 com3 txd B1 com3 rts B2 com3 dtr B8 com3 enable B9 com3 mode B10 com3 model B11 com3 mode2 B12 com dir B13 com3 dir2 B14 com3 slew B15 com3 term 6 1 22 R COMS IN READ This register reads the inputs of CN12 RS 232 422 485 transceivers B0 com3 rxd B1 com3 cts B2 com3 dsr B3 com3 dcd B7 com3 ri RTD Embedded Technologies Inc www rtd com 31 Accessing the Analog World FPGA35S6046 FPGA35S6101 User s Manual 6 1 23 R COM4 OUT READ WRITE This register sets the configuration and outputs of CN13 RS 232 422 485 transceivers B0 com4 txd B1 com4 rts B2 com4 dtr B8 com4 enable B9 com4 mode B10 com4 mode B11 com4 mode2 B12 com4 dir B13 com4 dir2 B14 com4 slew B15 com4 term 6 1 24 R COM4 IN READ
30. vided for lane repopulation The programming module is compatible with all Xilinx tools including iMpact and ChipScope www xilinx com It is also supported by Digilent s Adept software package www digilentinc com In order to use the embedded programmer JP1 must be installed This attaches the programmer to the JTAG chain CN3 can always be used regardless of whether or not JP1 is installed The embedded programmer has a user string of RTD followed by the serial number of the board This can be used to differentiate the programmers if there are multiple boards in the system RTD Embedded Technologies Inc www rtd com 26 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 6 Register Address Space This is the register address space for the example FPGA that is given with the FRGA35S6 6 1 BARU FPGA Example Register Map Table 16 FPGA Example Register Map Offset 0x3 31 omg OO OOD se 000 RID R_PORT1_OUT R_PORT2L_OUT R_PORT2H_OUT R_PORT2H_DIR R DDR RD DATA R DDR WR DATA R DDR ADDR R CLK 27 2 R COM2 OUT R COMS IN 6 1 1 R ID READ This is a register that identifies the board 0x12345678 is the identification of the example code 6 12 R STATUS READ This is a status register for power good pgood for the power supplies and serial out from the EEPROM B0 EEPROM Serial out B4 1 2V pgood B5 1 8V pgood B6 3 3V pgood 6 1 3 R EEPROM READ WRITE This registe
31. you can contact RTD Embedded Technologies technical support via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail techsupport rtd com RTD Embedded Technologies Inc www rtd com 9 FPGA35S6046 FPGA35S6101 User s Manual Accessing the Analog World 2 Specifications 2 1 Operating Conditions Table 2 Operating Conditions Parameter Test Condition 5V Supply Voltage Ta Operating Temperature o Z o vof je Ts Storage Temperature Z 40 65 C Relative Humidit NonCondnsng LO Telcordia Issue 2 MTBF Mean Time Before Failure 30 C Ground benign controlled 2 2 Electrical Characteristics Table 3 Electrical Characteristics Symbol Parameter IT Test Condition Min Typ Max Unit P PowerConsumpiont Vea SRN 25 w lc L Input Supply Current Active X 50 mA Lil PCle 104 Bus Differential Output Voltage 08 12 V DC Differential TX Impedance 1 80 120 Differential Input Voltage Ir Jos 12V DC Differential RX Impedance 1 1 1 80 120 __ Electrical Idle Detect Threshold TI e pm I Serial Transceivers Vu Input Low Voltage RS232mde 15 12 06 V Rin Input Resistance RS 422 485 mode kO TERM 0 V Vin S 12V RTERM Termination Resistance RS 422 485 mode 100 120 155 O TERM 1 7V Vin lt 12V V
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