BLE121LR - Digi-Key
Contents
1. The DCDC pin P1_7 can only be used for controlling the external soa DCDC The operation of P1_7 must not be altered by SW Bluegiga Technologies Oy Page 6 of 34 2 BLE121LR Product numbering Available products and product codes Product code Description BLE121LR A M256K BLE121LR with an embedded chip antenna and with 256k internal flash Bluegiga Technologies Oy Page 7 of 34 3 Pinout and Terminal Description Figure 1 BLE121LR Pin Number Pin Name Pad Type Description 1 3 14 15 22 31 36 GND GND GND 13 AVDD Supply voltage 23 DVDD Supply voltage 7 Reset Reset Active low reset Internal pull up Table 1 Supply and RF Terminal Descriptions Pin Number Pin Name Pad Type Description mg A e O rr mm Baa 8 PO 3 1 0 Configurable Input Output See Table 4 Peripheral I O Pin Mapping Bluegiga Technologies Oy Page 8 of 34 o y 10 RE w Pos 10 A n Poe 10 A a R 2 Por 10 A w pie yo w E 10 NG a B Pa 10 M U o Ps io E ae 7 pis 10 Ea 19 Po 10 o w Pa 10 More 2 Pa 10 Ba aaa Table 2 Configurable 1 0 Terminals Pin Number Pin Name Pad Type Description 24 SCL 12C clock 25 SDA 12C data 18 DCDC_CNTRL Output om PAPAG el ena Table 3 Non configurable Terminals Bluegiga Technologies Oy Page 9 of 34 PERIPHERAL POP PO AR WAREXML Example FUN2. and obtaining a separate FCC and Industry Canada authorization End Product Labeling The BLE121LR module is labeled with its own FCC ID and IC Certification Number If the FCC ID and IC Certification Number are not visible when the module is installed inside another device then the outside of the device into which the module is installed must also display a label referring to the enclosed module In that case the final end product must be labeled in a visible area with the following Contains Transmitter Module FCC ID QOQBLE121LR Contains Transmitter Module IC 5123A BGTBLE121LR or Contains FCC ID QOQBLE121LR Contains IC 5123A BGTBLE121LR The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or change RF related parameters in the user manual of the end product 10 2 1 FCC et IC Declaration d IC Ce dispositif est conforme aux normes RSS exemptes de licence d Industrie Canada Son fonctionnement est assujetti aux deux conditions suivantes 1 ce dispositif ne doit pas provoquer de perturbation et 2 ce dispositif doit accepter toute perturbation y compris les perturbations qui peuvent entrainer un fonctionnement non desire du dispositif Selon les r glementations d Industrie Canada cet metteur radio ne doit fonctionner qu avec une antenne d une typologie sp cifique et d un gain maximum ou inf rieur approuv pour l metteu
3. lt txpower power 9 gt 3VO supply nue 36 mA lt slow clock enable true gt without DCDC a lt txpower power 9 gt 39 KAP lt slow clock enable false 5 lt txpower power 9 gt Po Transmit lt slow clock enable true gt ka mg With DCDC lt txpower power 9 gt 35 mA lt slow clock enable false 5 lt slow clock enable true gt 28 mA Receive lt slow clock enable false 5 33 mA Power mode 1 lt sleeposc enable true ppm 30 gt 2 7 mA Power mode 2 lt sleeposc enable true ppm 30 gt 1 3 uA Power mode 3 s 0 5 HA Using DCDC reduces transmit power by 2 dB and thus lowers also the peak current drawn by the module To enter PM1 and PM2 sleep oscillator must be enabled in the hardware xml PM3 is not dependent on the sleep clock The module will enter PM3 automatically when there is no activity which would require clock PM3 can be disabled in hardware xml for example lt sleep enable true max modez 2 gt Figure 2 BLE121LR TX peak current as a function of the setting in the HW configuration file RX peak 33 mA TX peak 39 mA slow clock disabled slow clock disabled TX peak 36 mA slow clock enabled RX peak 28 mA slow clock enabled A 1ms div Figure 3 Typical current consumption profile while advertising Bluegiga Technologies Oy Page 13 of 34 BLE121LR TX peak
4. Electrical Characteristics iii 12 4 1 Absolute Maximum Ratings sise 12 4 2 Recommended Operating Conditions sisi 12 43 DE Gharacteristi s iia ii ita iras cts 12 4 4 GUrrentCOnSUMPlO Ni A ee BAG NAE 13 4 4 1 Current Consumption When Using TPS62730 DCDC Converter 14 4 5 RE Characteristics italia bed cts ba ere daang 14 4 6 Range Of BLEFIRA oai a e Buea eel eR te A tds 18 5 Physical Dimensions iii nA 20 6 Power On Reset and Brownout Detector sisi 22 Z DESIGN QUIASINES a A A NA NA 23 7 1 General Design Guidelines bana irradian 23 72 7 Layout Gide LINES AA A A a A AAA aan 23 7 3 BLE121LR A Layout Guide an talento GAD aaa Anang 24 8 Soldering Recommendations iii 26 9 Block diagram isin se RS een im bdo 27 10 Certifications ssh nt ne tr Re at A ER An a el ne es ti 30 10 1 Bluetooth e Ni GRAD an na 30 10 2 KC ALA o se 30 10 24 ACES AAA LANA PANGA BANANA LAB ANA BANGA TATA 31 10 3 BE aaa allas 33 10 4 MIG Wap aN st st vee AG DA eae ee en EA 33 10 5 Anatel Brazil act coat lena necia E 33 10 6 KERO iii a a att 33 11 Contact Information atc atts dao Likha abah ltda 34 Bluegiga Technologies Oy ENT s is BLE121LR Bluetooth Smart Module DESCRIPTION BLE121LR is a Bluetooth Smart Long Range module targeted for Bluetooth Smart applications where the best possible RF performance and range are required At 8 dBm TX power and 98 dBm sensitivity BLE121LR has best in class RF perform
5. Suite 300 Duluth GA 30096 USA Bluegiga Technologies Ltd Phone 852 3972 2186 Bluegiga Technologies Oy Page 34 of 34
6. and if so whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected Each peripheral that connects to the I O pins can choose between two different I O pin locations to ensure flexibility in various applications The sleep timer is an ultra low power timer that uses an external 32 768 kHz crystal oscillator The sleep timer runs continuously in all operating modes except power mode 3 Typical applications of this timer are as a real time counter or as a wake up timer to exit power modes 1 or 2 Timer 1 is a 16 bit timer with timer counter PWM functionality lt has a programmable prescaler a 16 bit period value and five individually programmable counter capture channels each with a 16 bit compare value Each of the counter capture channels can be used as a PWM output or to capture the timing of edges on input signals lt can also be configured in IR generation mode where it counts timer 3 periods and the output is ANDed with the output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction Timer 2 is a 40 bit timer used by the Bluetooth low energy stack It has a 16 bit counter with a configurable timer period and a 24 bit overflow counter that can be used to keep track of the number of periods that have transpired A 40 bit capture register is also used to record the exact time at which a start of frame delimiter is received transmitted or the exact time at which tr
7. current vs HW configuration 40 35 E 30 E E 3 2s 20 15 0 1 2 3 5 6 7 8 9 10 TXP setting in the harware xml Figure 4 BLE121LR TX peak current as a function of hardware xml TXP setting Example lt txpower power 9 bias 5 gt 4 4 1 Current Consumption When Using TPS62730 DCDC Converter TPS62730 DCDC converter provides 20 reduction to the peak current drawn from 3 0V supply and 15 reduction to the peak current drawn from 2 7V supply This is achieved by converting higher power supply down to 2 1V supply with a switching mode regulator The module turns the DCDC on when the processor is active and off by pass mode when the processor is not active Because the TX power of BLE121LR depends on the supply voltage the TX power is reduced when using TPS62730 DCDC converter The reduced TX power in turn reduces the peak current drawn by the module Thus when using TPS62730 with BLE121LR from 3 0V supply the peak current is reduced in total by e 4mA because of lower TX power e 20 because of the switching mode regulator converting from 3 0V down to 2 1V gt Peak current drawn from 3 0V supply in total Max TXP slow clock enabled 36 mA 4 mA 0 8 25 6 mA 4 5 RF Characteristics Rating Min Typ Max Unit Transmit power 8 dBm Transmit power variation within BT band 1 1 8 dB Transmit power variation within the temperature range qna dB Sensitivity Default high gain mode PE
8. practices to avoid any excessive noise coupling to signal lines or supply voltage lines Do not place plastic or any other dielectric material in touch with the antenna Board edge Min 17mm e 3 Min 17mm Figure 23 Recommended layout for BLE121LR A Bluegiga Technologies Oy Page 24 of 34 RANGE of maximum Figure 24 Poor layouts for BLE121LR 120 100 80 60 40 20 25 Amount of GND on the sides of the module mm i Figure 25 Impact of the size of GND plane to the range of BLE121LR Bluegiga Technologies Oy Page 25 of 34 8 Soldering Recommendations BLE121LR is compatible with industrial standard reflow profile for Pb free solders The reflow profile used is dependent on the thermal mass of the entire populated PCB heat transfer efficiency of the oven and particular type of solder paste used Consult the datasheet of particular solder paste for profile configurations Bluegiga Technologies will give following recommendations for soldering the module to ensure reliable solder joint and operation of the module after soldering Since the profile used is process and layout dependent the optimum profile should be studied case by case Thus following recommendation should be taken as a starting point guide Refer to technical documentations of particular solder paste for profile configurations Avoid using more than one flow Reliabili
9. valables et l identification de FCC et le num ro de certification d IC ne pourront pas tre utilis s sur le produit final Dans ces cas l int grateur OEM sera charg d valuer a nouveau le produit final y compris l metteur et d obtenir une autorisation ind pendante de FCC et d Industrie Canada tiquetage du produit final Le module BLE121LR est tiquet avec sa propre identification FCC et son propre numero de certification IC Si l identification FCC et le num ro de certification IC ne sont pas visibles lorsque le module est install l int rieur d un autre dispositif la partie externe du dispositif dans lequel le module est install devra galement pr senter une tiquette faisant r f rence au module inclus Dans ce cas le produit final devra tre tiquet sur une zone visible avec les informations suivantes Contient module metteur identification FCC QOQBLE121LR Contient module metteur IC 5123A BGTBLE121LR ou Contient identification FCC QOQBLE121LR Contient IC 5123A BGTBLE121LR Dans le guide d utilisation du produit final Pint grateur OEM doit s abstenir de fournir des informations Putilisateur final portant sur les proc dures suivre pour installer ou retirer ce module RF ou pour changer les param tres RF Bluegiga Technologies Oy Page 32 of 34 10 3CE BLE121LR has been tested according to the following standards SAFETY e EN 60950 1 2006 A11 2009 A1 2010
10. 21 of 34 6 Power On Reset and Brownout Detector BLE121LR includes a power on reset POR providing correct initialization during device power on It also includes a brownout detector BOD operating on the regulated 1 8 V digital power supply only The BOD protects the memory contents during supply voltage variations which cause the regulated 1 8 V power to drop below the minimum level required by digital logic flash memory and SRAM When power is initially applied the POR and BOD hold the device in the reset state until the supply voltage rises above the power on reset and brownout voltages Bluegiga Technologies Oy Page 22 of 34 7 Design Guidelines 7 1 General Design Guidelines BLE121LR can be used directly with a coin cell battery Due to relatively high internal resistance of a coin cell battery it is recommended to place a 100uF capacitor in parallel with the battery The internal resistance of a coin cell battery is initially in the range of 10 ohms but the resistance increases rapidly as the capacity is used Basically the higher the value of the capacitor the higher is the effective capacity of the battery and thus the longer the life time for the application The minimum value for the capacitor depends on the end application and the maximum transmit power used The leakage current of a 100uF capacitor is in the range of 0 5 uA to 3 UA and generally ceramic capacitors have lower leakage current than tantalum or aluminum electrolytic
11. A12 2011 EMC Art 3 1 a e EN 301 489 1 v 1 9 2 e EN 301 489 17 V2 2 1 o Radiated electric field immunity EN 61000 4 3 2006 o ESD immunity EN 61000 4 2 2009 SPECTRUM Art 3 2 e EN 300 328 V1 8 1 o Equivalent isotropic radiated power o Maximum spectral power density o Occupied channel bandwidth o Transmitter unwanted spurious emissions in the out of band domain o Transmitter unwanted spurious emissions in the spurious domain o Receiver spurious emissions The official DoC is available in www bluegiga com 10 4MIC Japan BLE121LR is certified as a module with type certification number 209 J00111 As a certified module BLE121LR can be integrated to an end product without a need for additional MIC Japan certification of the end product 10 5 Anatel Brazil TBA 10 6KCC Korea BLE121LR has type certification in Korea with certification number MSIP CRM BGT BLE121LR Bluegiga Technologies Oy Page 33 of 34 11 Contact Information Sales Technical support Orders WWW Head Office Finland Postal address Finland Sales Office USA Sales Office Hong Kong salesObluegiga com http www bluegiga com support orders bluegiga com www bluegiga com Phone 358 9 4355 060 Fax 358 9 4355 0660 Sinikalliontie 5A 02630 ESPOO FINLAND P O BOX 120 02631 ESPOO FINLAND Phone 1 770 291 2181 Fax 1 770 291 2183 Bluegiga Technologies Inc 3235 Satellite Boulevard Building 400
12. BLE121LR DATA SHEET Tuesday 09 September 2014 Version 1 2 Copyright O 2000 2014 Bluegiga Technologies All rights reserved Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual Furthermore Bluegiga Technologies reserves the right to alter the hardware software and or specifications detailed here at any time without notice and does not make any commitment to update the information contained here Bluegiga s products are not authorized for use as critical components in life support devices or systems The WRAP is a registered trademark of Bluegiga Technologies The Bluetooth trademark is owned by the Bluetooth SIG Inc USA and is licensed to Bluegiga Technologies All other trademarks listed herein are owned by their respective owners Bluegiga Technologies Oy VERSION HISTORY Version Comment 1 1 First release Standard gain mode option for the receiver added Figure 22 corrected 1 2 Ceritification info updated Footprint and PCB land pattern figures revised Design check list added Layout guide updated Range chapter added Bluegiga Technologies Oy TABLE OF CONTENTS id Design Check iS E A A dr dat ra Pate ANg dde 6 2 BLET21ER Product number test 7 3 Pinout and Terminal Description usines 8 3 1 O O AA a a Ne en 11 3 1 1 VO Gonfigurations 3 it kaa He ec ie NTG NIAN 11 3 1 2 Reserved OS art aunt taht it es RAR M a te tat 11 32 MARTA gee ere 11 4
13. CTION E HN A HE OS TI a USART 0 SPI ara c ss mo mi a See lt usart channel 0 mode spi_master alternate 1 aie mo mi c ss lt usart channel 0 mode spi master alternate 2 ola ata aro ma o 0 UART area lt usart channel 0 mode uart alternate 1 lt usart channel 0 mode uart alternate 2 lt usart channel 1 mode spi_master alternate 1 lt usart channel 1 mode uart alternate 1 lt timer index 1 alternate 1 lt timer index 1 alternate 2 lt timer index 3 alternate 1 OmMmxaxdIm om g O ajaja 57 DCE OE CEE CHE E CETTE lt timer index 3 alternate 2 ma H E E H CN CM mar lt timer index 4 alternate 1 lt timer index 4 alternate 2 Sarees ESPA 1 jopsseL TI 1 15141812 Refer to BLE Configuration Guide for detailed settings SS is the slave select signal when BLE121LR is set as SPI slave When set as SPI master any available I O can be used as chip select signal of BLE121LR NOTE Pins configured as peripheral I O signals do not have pull up down capability Table 4 Peripheral I O Pin Mapping Bluegiga Technologies Oy Page 10 of 34 3 1 1 0 Ports 3 1 1 I O Configurations Each I O port can be configured as an input or output When configured as input each I O port can also be configured with internal pull up pull down or tri
14. R y Bh Oe 9 98 dBm Sensitivity standard gain mode PER dd 30 8 92 dBm Standard gain mode can be set using an API command Please refer to the Bluetooth Smart Software API Reference document Figure 5 BLE121LR RF characteristics Bluegiga Technologies Oy Page 14 of 34 BLE121LR TXP vs temperature 10 9 8 7 E 6 oa 2 5 a Ka 3 2 1 0 1 1 40 20 0 20 40 60 80 Temperature C Figure 6 Typical transmit power as a function of temperature BLE121LR TXP vs supply voltage TXP dBm 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 Supply voltage V Figure 7 BLE121LR transmit power as a function of supply voltage Bluegiga Technologies Oy Page 15 of 34 BLE121LR TXP vs HW configuration TXP dBm E N o N 0 1 2 3 a 5 6 7 8 9 10 Setting in the hardware xml Figure 8 BLE121LR TX power as a function of the setting in the HW configuration file Example lt txpower power 9 bias 5 gt Legend 2400 00 MHz 2440 00 MHz 2480 00 MHz 270deg TANden Figure 9 Radiation pattern of BLE121LR when mounted to a carrier board Bluegiga Technologies Oy Page 16 of 34 Legend 2400 00 MHz 2440 00 MHz 2480 00 MHz Y 7 270deg X 1AMden Figure 10 Radiation pattern of BLE121LR when mounted to a carrier board X E Legend 2400 00 MHz 2440 00 MH2 2480 00 MHz Y y 270deg X 1ANden Figure 11 Radiation p
15. an be implemented by combining BLE121LR Controller Subsystem with the muLLEt Host Host Subsystem with QD ID 34551 10 2FCC and IC This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Any changes or modifications not expressly approved by Bluegiga Technologies could void the user s authority to operate the equipment FCC RF Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment End users must follow the specific operating instructions for satisfying RF exposure compliance This transmitter meets both portable and mobile limits as demonstrated in the RF Exposure Analysis This transmitter must not be co located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi transmitter product procedures IC Statements This device complies with Industry Canada licence exempt RSS standard s Operation is subject to the following two conditions 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Under Industry Canada regulations this radio transmitter may only operate using an antenna of a ty
16. ance and can provide Bluetooth Smart connectivity up to 450 meters BLE121LR integrates all features required for a Bluetooth Smart application Bluetooth radio software stack and GATT based profiles and it can also host end user applications which means no external micro controller is required in size price or power constrained devices BLE121LRBluetooth Smart module also has flexible hardware interfaces to connect to different peripherals or sensors Although BLE121LR Bluetooth Smart Long Range Module is target for applications requiring high RF performance it is still has relatively low power consumption and can be power using a standard 3V coin cell batteries APPLICATIONS Smart home accessories beacon devices Health and fitness sensors Medical sensors iPhone and iPad accessories Security and proximity tags KEY FEATURES e Bluetooth v 4 0 Single Mode Compliant o Master and slave modes o Up to eight connections e Integrated Bluetooth Smart Stack o GAP ATT and GATT o Bluetooth Smart profiles e Best in Class RF Performance o Transmit power 8 dBm o Receiver sensitivity 98 dBm o Range up to 450 meters e Low Current Consumption o Transmit 36 mA 8 dBm o Receive 33 mA 98 dBm o Power mode 3 0 5 UA e Flexible Peripheral Interfaces o UART and SPI o 12C PWM and GPIO o 12 bit ADC e Host Interfaces o UART e Programmable 8051 Processor for Stand alone Operation o Simple Bluegiga BGScript scrip
17. ansmission ends There are two 16 bit timer compare registers and two 24 bit overflow compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts Timer 3 and timer 4 are 8 bit timers with timer counter PWM functionality They have a programmable prescaler an 8 bit period value and one programmable counter channel with an 8 bit compare value Each of the counter channels can be used as PWM output USART 0 and USART 1 are each configurable as either an SPI master slave or a UART They provide double buffering on both RX and TX and hardware flow control and are thus well suited to high throughput full duplex applications Each USART has its own high precision baud rate generator thus leaving the ordinary timers free for other uses When configured as SPI slaves the USARTs sample the input signal using SCK directly instead of using some oversampling scheme and are thus well suited for high data rates The AES encryption decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128 bit keys The AES core also supports ECB CBC CFB OFB CTR and CBC MAC as well as hardware support for CCM The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30 kHz to 4 kHz respectively DC and audio conversions with up to eight input channels I O controller pins are possible The inputs can be selected as single ended or differential The refe
18. attern of BLE121LR when mounted to a carrier board Bluegiga Technologies Oy Page 17 of 34 4 6 Range of BLE121LR ER Sensitivity Attenuation pink Budeet Range ETS CEE 8dBm 98 dBm Front 3 dB 100 dB O 470m 450m PAG 8 d8m 98 dBm Back 7 dB 924 300m 300m CRIE 2 d8m 98 dBm Side 5 dB 9648 370m 340m A nati pagan O 50 aon pe ho 60 o Plane Earth Loss Free Space Loss A int 70 80 Loss dB f 90 Di 100 110 120 10 100 1000 Range m Figure 12 Range of BLE121LR vs BLE121LR when antennas are 1 5m above GND The range of BLE121LR is dependent on the mother board layout height of the antennas above GND and any obstacles within the RF path or near the RF path multipath propagation See Figure 25 how the layout impacts to the range of BLE121LR In an open field the received power is a sum of the line of sight wave and the ground reflected wave Depending on the phase of the ground reflected wave it either amplifies or attenuates the total received power Figure 14 shows how the antenna height from ground impacts to the RF path loss and range in an open field RF power propagates in free space within a virtual pipe which can be defined by so called Fresnel ellipsoid Any obstacles within the area of this pipe will attenuate the RF power and thus decrease the actual range o
19. capacitors Optionally Tl s TPS62730 can be used to reduce the current consumption during TX RX and data processing stages TPS62730 is an ultra low power DC DC converter with by pass mode and will reduce the current consumption during transmission nominally by 20 when using 3V coin cell battery Because unlike with BLE112 and BLE113 the TX power of BLE121LR is dependent on the power supply the DCDC reduces the TX power by 2dB which provides additional saving in the peak current So in total the peak current can be reduced by approximately 30 with the cost of 2 dB lower TX power External DCDC is optional Using TPS62730 reduces peak TX power by 2 dB and peak current by approximately 30 gt i 2V 3V3_MOD u 2 24H 20 130mA 0 430hm iT 2 2uF 10V XSR 8 DV 5 8 1l L 5 3 L L mios O CA 3 TES 1 mao ma 895 A z asg ae Pas SA The module turns the DCDC DIVAS into by pass mode when entering to power modes This is to minimize 5 kia the sleep current consumption 4 cs J i VI 0 47UF 6 3V X5R sa 7 HEADER so 1n PROGRAMMING INTERFACE hoe ea 8 2 Figure 20 Example schematic for BLE121LR with a coin cell battery TPS62730 DCDC converter and an 12C accelerometer 7 2 Layout Guide Lines Use good layout practices to avoid excessive noise coupling to supply vo
20. e hardware peripherals AES core flash controller USARTs timers ADC interface etc can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or XREG address and flash SRAM Each CC2541 contains a unique 48 bit IEEE address that can be used as the public device address for a Bluetooth device Designers are free to use this address or provide their own as described in the Bluetooth specification The interrupt controller services a total of 18 interrupt sources divided into six interrupt groups each of which is associated with one of four interrupt priorities l O and sleep timer interrupt requests are serviced even if the device is in a sleep mode power modes 1 and 2 by bringing the CC2541 back to the active mode The debug interface implements a proprietary two wire serial interface that is used for in circuit debugging Through this debug interface it is possible to erase or program the entire flash memory control which oscillators are enabled stop and start execution of the user program execute instructions on the 8051 core set code breakpoints and single step through instructions in the code Using these techniques it is possible to perform in circuit debugging and external flash programming elegantly The I O controller is responsible for all general purpose I O pins The CPU can configure whether peripheral modules control certain pins or whether they are under software control
21. emories and all peripherals through the SFR bus The memory arbiter has four memory access points access of which can map to one of three physical memories an SRAM flash memory and XREG SFR registers It is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory The SFR bus is a common bus that connects all hardware peripherals to the memory arbiter The SFR bus also provides access to the radio registers in the radio register bank even though these are indeed mapped into XDATA memory space The 8 KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces The SRAM is an ultralow power SRAM that retains its contents even when the digital part is powered off power modes 2 and 3 The 256 KB flash block provides in circuit programmable non volatile program memory for the device and maps into the CODE and XDATA memory spaces Peripherals Writing to the flash block is performed through a flash controller that allows page wise erasure and 4 bytewise programming A versatile five channel DMA controller is available in the system accesses memory using the XDATA memory space and thus has access to all physical memories Each channel trigger priority transfer mode Bluegiga Technologies Oy Page 27 of 34 addressing mode source and destination pointers and transfer count is configured with DMA descriptors that can be located anywhere in memory Many of th
22. ermanently damaged These are not maximum operating conditions The maximum recommended operating conditions are in the Table 7 Rating Min Max Unit 40 85 Storage Temperature C AVDD DVDD 0 3 3 9 V Other Terminal Volatages VSS 0 4 VDD 0 4 V Table 6 Absolute Maximum Ratings 4 2 Recommended Operating Conditions Rating Min Max Unit 40 85 Operationg Temperature Range C AVDD DVDD 2 0 3 6 V Table 7 Recommended Operating Conditions All supply nets must have the same voltage Supply voltage noise should be less than 10mVpp Excessive noise at the supply voltage will reduce the RF performance The supply voltage has an impact on the TX power see Figure 7 4 3 DC Characteristics Parameter Test Conditions Min Typ Max Unit Logic 0 input voltage 0 5 V Logic 1 input voltage DVDD 3V0 2 5 V Logic 0 input current Input equals OV 50 50 nA Logic 1 input current Input equals VDD 50 50 nA O pin pull up and pull down resistors 20 kQ For detailed I O terminal characteristic and timings refer to the CC2541 datasheet available in http www ti com lit ds symlink cc2541 pdf Table 8 DC Characteristic Bluegiga Technologies Oy Page 12 of 34 4 4 Current Consumption Power mode hardware xml Min Typ Max Unit lt txpower power 17 5 lt slow clock enable true gt ai mA Transmit
23. f the link The radius of the pipe can be approximated by R Dx A 12 Where R is the radius D is the distance between the antennas and lambda is the wave length 12 2 cm Bluegiga Technologies Oy Page 18 of 34 Transmitter Receiver Figure 13 RF propagation area between TX and RX Distance m Height m Antennas 0 5m mmm Antennas O 1 0m Antennas 1 5m RF PATH LOSS dB 100 1000 Range 310m Distance m 5 Range 160m Range 470m Figure 14 Impact of module height above GND to RF path loss Bluegiga Technologies Oy Page 19 of 34 5 Physical Dimensions Figure 15 Footprint of BLE121LR top view 8 4 mm 3 9 mm 4 8 mm 14 7 mm 13 7 mm 6 8 mm 13 0 mm Figure 16 Physical dimensions top view 1 9 mm lt Figure 17 Physical dimensions side view Bluegiga Technologies Oy Page 20 of 34 2 00mm 2 95mm 7 50mm sl p y Copper Cleorance 3 45mm Area 0 50mm o 0 90mm 0 90mm 1 55mm Mi 150mm 0 90mm 0 90mm Figure 18 Recommended land pattern for BLE121LR A Recommended PCB Module pads land pattern footprint PCB lands are extended to help visual inspection Center to center 1 5mm PCB land pattern Center to center 1 25mm footprint Figure 19 Module placed on the recommended PCB land pattern Bluegiga Technologies Oy Page
24. ltage traces or sensitive analog signal traces If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emission Bluegiga Technologies Oy Page 23 of 34 from the edges of the PCB Connect all the GND pins directly to a solid GND plane and make sure that there is a low impedance path for the return current following the signal and supply traces all the way from start to the end A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to supply voltage planes and traces and route all the signals on top and bottom layers of the PCB This arrangement will make sure that any return current follows the forward current as close as possible and any loops are minimized Signals GND Power Signals Figure 21 Typical 4 layer PCB construction CC YA KCC D h Overlapping GND layers without Overlapping GND layers with GND stitching vias GND stitching vias shielding the RF energy Figure 22 Use of stitching vias to avoid emissions from the edges of the PCB 7 3 BLE121LR A Layout Guide For optimal performance of the antenna place the module at the edge of the PCB as shown in the Figure 23 Do not place any metal traces components battery etc within the clearance area of the antenna Connect all the GND pins directly to a solid GND plane Place the GND vias as close to the GND pins as possible Use good layout
25. pe and maximum or lesser gain approved for the transmitter by Industry Canada To reduce potential radio interference to other users the antenna type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication OEM Responsibilities to comply with FCC and Industry Canada Regulations The BLE121LR module has been certified for integration into products only by OEM integrators under the following condition e The transmitter module must not be co located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi transmitter product procedures Bluegiga Technologies Oy Page 30 of 34 As long as the condition above is met further transmitter testing will not be required However the OEM integrator is still responsible for testing their end product for any additional compliance requirements required with this module installed for example digital device emissions PC peripheral requirements etc IMPORTANT NOTE In the event that the above condition can not be met for certain configurations or co location with another transmitter then the FCC and Industry Canada authorizations are no longer considered valid and the FCC ID and IC Certification Number can not be used on the final product In these circumstances the OEM integrator will be responsible for re evaluating the end product including the transmitter
26. r par Industrie Canada Pour r duire les ventuelles perturbations radio lectriques nuisibles d autres utilisateurs le type d antenne et son gain doivent tre choisis de mani re ce que la puissance isotrope rayonn e quivalente P LR E n exc de pas les valeurs n cessaires pour obtenir une communication convenable Responsabilit s des OEM quant la conformit avec les r glementations de FCC et d Industrie Canada Les modules BLE121LR ont t certifi s pour entrer dans la fabrication de produits exclusivement r alis s par des int grateurs dans les conditions suivantes Bluegiga Technologies Oy Page 31 of 34 e Le module transmetteur ne doit pas tre install ou utilis en concomitance avec une autre antenne ou un autre transmetteur Tant que ces deux conditions sont r unies il n est pas n cessaire de proc der des tests suppl mentaires sur le transmetteur Cependant l int grateur est responsable des tests effectu s sur le produit final afin de se mettre en conformit avec d ventuelles exigences compl mentaires lorsque le module est install exemple emissions provenant d appareils num riques exigences vis a vis de p riph riques informatiques etc REMARQUE IMPORTANTE En cas dinobservance de ces conditions en ce qui concerne certaines configurations ou l emplacement du dispositif proximit d un autre metteur les autorisations de FCC et d Industrie Canada ne seront plus consid r es
27. rence voltage can be internal AVDD or a single ended or differential external signal The ADC also has a temperature sensor input channel The ADC can automate the process of periodic sampling or conversion over a sequence of channels The IC module provides a digital peripheral connection with two pins and supports both master and slave Bluegiga Technologies Oy Page 28 of 34 operation PC support is compliant with the NXP 12C specification version 2 1 and supports standard mode up to 100 kbps and fast mode up to 400 kbps In addition 7 bit device addressing modes are supported as well as master and slave modes The ultralow power analog comparator enables applications to wake up from PM2 or PM3 based on an analog signal Both inputs are brought out to pins the reference voltage must be provided externally The comparator output is connected to the I O controller interrupt detector and can be treated by the MCU as a regular I O pin interrupt RF front end RF front end includes balun power amplifier low noise amplifier band pass filter and a ceramic chip antenna with matching network Optimal matching combined with effective low pass filter provides extremely low in band spurious emissions and harmonics Bluegiga Technologies Oy Page 29 of 34 10 Certifications BLE121LR is compliant to the following specifications 10 1 Bluetooth BLE121LR is qualified as a Controller Subsystem with QD ID 57409 A Bluetooth End Product c
28. state Pull down or pull up can only be configured to whole port not individual pins Unused I O pins should have defined level and not be floating See the BLE Configuration Guide for more information about the configuration During reset the I O pins are configured as inputs with pull ups Note Pins configured as peripheral I O signals do not have pull up down capability 3 1 2 Reserved l O s The high current driving pins P1_0 and P1_1 are reserved for the internal RF front end control These pins are not exposed in BLE121LR and they can t be used for application purposes P1_7 is also used for the RF front end control but as an output it can be used to control the external DCDC for lowering the peak current drawn from the battery The function of P1_7 can t be altered If external DCD is not used then P1_7 should be left not connected 3 2 UART UART baud rate can be configured up 2 Mbps See the BLE Configuration Guide for more information Following table lists commonly used baud rates for BLE121LR Baud rate bps Error 2400 0 14 4800 0 14 9600 0 14 14 400 0 03 19 200 0 14 28 800 0 03 38 400 0 14 57 600 0 03 76 800 0 14 115 200 0 03 230 400 0 03 Table 5 Commonly used baud rates for BLE121LR Bluegiga Technologies Oy Page 11 of 34 4 Electrical Characteristics 4 1 Absolute Maximum Ratings Note These are absolute maximum ratings beyond which the module can be p
29. ting language for quick application development o Bluegiga Profile Toolkit allowing the quick development of GATT based profiles e Dimensions 14 7 x 13 0 x 1 8 mm e Bluetooth CE FCC IC South Korea and Japan qualified Bluegiga Technologies Oy 1 Design Check List Board edge Min 17mm Make sure that the programing interface P2_ P2_2 reset is available for debugging or FW updates Add test points for testing the current consumption Make sure that all the 10 s are in a known state Make sure that the layout under the antenna is done as instructed Place large capacitor in parallel with the battery to reduce the peak current drawn from the battery awaa non 1 M 2 T NP A u The external DCDC converter A 2 2uH 20 13 D 430hm t Ng Mo e e will reduce the maximum TX els ES 5 Som mn 32 8 power by 72 dB z 3 El i Ng as Hi i ase 5 NG Ket MoDz E i Hs sea Ala ew A Bi apa 2V 3Va MOD ora Ao Y g am nig kale ASE 4 m as as j bee cas o 8 egectanos n sal maaya su 8 la pit ama gas LE rame H T Paros 228 TE A ri a al Nha then nala 3 A 10 Bie 2 sve no 2 Panapaan Te pe mO m2 3 sa GND PROGRAMMING INTERFACE saw me pas 4 4 a we Ale ol ml MMAB451Q 4 L
30. ty of the solder joint and self alignment of the component are dependent on the solder volume Minimum of 150um stencil thickness is recommended Aperture size of the stencil should be 1 1 with the pad size A low residue no clean solder paste should be used due to low mounted height of the component Cetsius A LG F Figure 26 Reference reflow profile pr 4 Bluegiga Technologies Oy Page 26 of 34 9 Block diagram BLE121LR is based on Tl s CC2541 chip Embedded 32 MHz and 32 678 kHz crystals are used for clock generation Matched balun and low pass filter provide optimal radio performance with extremely low spurious emissions ES 32768 2V 3 6V Reset kHz XTAL Pes ee ee A l i cc2541 I I l I 8051 CPU core and memory arbitrator l l Anal IRQ I nalog F 7 DM comparator controller ra o l B Radio arbiter E Radio registers I e Link layer engine 8 SRAM l I Demodulator Modulator l I Chip USART O antenna Frequenc USART 1 y I TIMER 1 Receive synthetisi Transmit l TIMER 2 pal l TIMER 3 l TIMER 4 PA LNA L Figure 27 Simplified block diagram of BLE121LR CPU and Memory The 8051 CPU core is a single cycle 8051 compatible core It has three different memory access buses SFR DATA and CODE XDATA a debug interface and an 18 input extended interrupt unit The memory arbiter is at the heart of the system as it connects the CPU and DMA controller with the physical m
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