CDB48500 USB Evaluation Kit Guide
Contents
1. m ox bay 65 RESET tsm 15 671 MUXED MCLK 2 m MUKED DSP BELKI FTZ COMPATIBLE SNTALVCI25APUR UN 22324223 tev C 1 88 i 2 DSP DAI B c3 5s 2x7 BO soccer DA2 133 TOR BOARDI HoR lt e mss WUXED DSP DAIS TPIB x DSP 31 SPOFZ aen Aoc stt 15 MEE MUXED_DSP_LRCLK2 131 09 050 tam im m GO amp cs6416_LRCLK ADC_SDATAS 31 DSP I 7 csa2448 2 sDOUTS B CONSORTES oam vec H4 3 3VD n DSP 13 GND ous TP20 pe ignore Bg cse FITZ COMPATELE Ten vs 00 509 Ds _DA00 HS0 3 DSP_DAOI HS m2 131 __QRBOARDZ HoR2 gt gt DSP_DA02 HS2 15 31 PoP izenak SEL 8 OSP_DAOS XMTA 370 tess 13 700 OSP_DAO4 HS3 B MUXED DSP LRCLK2 131 C tie 35601 5806 SCLK 120 n RISDA A ii WUXED DSP sCLK2 03 DATA CLOCK SELECTION 151 CSB416 SDOUT 18 50 wH n MUXED DSP DAM i3 Ui2. Shut s 18 JANS 08 JU PREAMP t101 B B 1 E inam l cx Jews aloso lo Jew Sow Tour Tur ov ik I conec pac des den E NK CI s our Tour mo YY Vo Vk EE aE dees Too px eas cas eas E amp Ig be du Lebe smi few Tropa W pow 258283 8 i m loos 2 m CES GS rant JAN B 22 151 CSTE RST E im MANC d ih iuc JANIE i 13 7 IRCUK TE d SCP_MOSI pulled low by pull down Tos des SPDIF RX page O57 50 d 22 57 soours CBE 6s c i psp DAO2 MS2 gt Wm ACRES won E 885588 E desees E wure_covecr 19 osr oaos 1901 3 13 im E 4001 2 13 2n SPI ADDR Ox9E CDB48520 I2C ADDR 0x92 PAT 6000026221 REV 542448 CODEC 1 10 19 06 E 1 0rv Figure 6 Codec 1 CS42448 Schematic caar8zsa 1 50 10 1u
3. eee 4 1 4 1 4 1 4 2 Basic Application Download and System Configuration for PCM Pass through 4 1 4 2 1 System essi nenas 4 2 4 2 2 Changing the Audio Input Source nennen nennen 4 3 4 2 2 1 Audio In via S PDIF 1 nennen nennen snis 4 3 4 2 2 2 Audio In via 8 channel ADC eene 4 3 4 2 2 3 Audio In USB eene nennen tenent 4 4 4 2 2 4 DAI Input of 3485 enne sent nennen nnn nn 4 4 4 2 3 Changing Audio Output Configuration ssssssesseeeeneneennn ens 4 5 4 2 3 1 DAO Output of CS485xx sse entere nnns 4 5 4 2 3 2 542448 DAC Properties sssssssssssseseeeeeeeren nennen 4 6 4 2 4 Changing Serial Control Protocol 12 or SPI sse 4 7 4 2 5 Headphone enne tentes inn ensi nnne rennes 4 8 4 2 6 S PDIF ecce Eee otn inden 4 9 Appendix A Schematics A 1 Introduction RR RR RR L
4. enn A 10 Figure 6 Codec 1 CS42448 5 11 Figure 7 Codec 2 542448 1 12 Figure 8 Codec 1 and Codec 2 Input Filters Schematic A 13 Figure A 9 Output Filters amp Headphone Output ennt enn A 14 Figure 10 Mic Preamp Schematic 1 A 15 Figure A 11 Control Connector and Power Schematic A 16 CDB48500 USB Evaluation Kit Guide v il ERES CIRRUS LOGIC Chapter 1 Introduction to the CRD48500 USB Evaluation Kit 1 1 CDB48500 USB Kit Contents and Requirements 1 1 1 CDB48500 USB Kit Each CDB48500 USB kit comes with the following e CDB48500 Development Board See Figure 1 2 Power Supply 9V 1 67A 100V 240V with AC Power Cord e USB MASTER Digital I O Card See Figure 1 2 USB Cable Board Overlays Identifying the Outputs for CS48520 CS48540 and CS48560 Document Card Explaining How to Get the Latest Board Software 1 1 2 PC Requirements Microsoft Windows XP or Windows 79 Operating System USB 2 0 Support 1 1 3 Software Requirements Cirrus Evaluation Software Package available from your local Cirrus Logic representative 1 1 4 Support Hardwar
5. oO G ETT 5VA ping Shit FOLOCALI FDL CAL FDLOCALI uv 69 amp ws 9 NI Qus FOLOCALI FDLOGALI FBLOCALI bu mo nm ELEC D O 2 Pd assu Ha FDLOCALI FDLDCALI FDLOCALI FDLOCALI R76 TENE WBROS20LTIG E UM m D SPXINMS L Auxiliary H W amp Docs im Bie s 1 1a u Hav REC a Eus T 8 4002 5 o Sko Haei SHUNT 2P 15 29 1025 100 e 1006 VCB 5 u caz 32 h Em e ANE vue NEEE R7B ue ASSY DWG 603 00253 21 R9 066 SCH DWG 600 00253 21 15K pu ces Soto SCREW PHLIPS 4 4OTHR PH 5 16 PMSSS 440 0031 PH E VID BRD mu 8 _ _1 DC Input from 9V to 12V 22005F A PART F E 600 00262 71 REV 1 1 2 EXCHLASASTOH EXCHLASASTOR seer TME CONNECTORS POWER 10 19 06 55 ne Figure A 11 Control Connector and Power Schematic il ERES CIRRUS LOGIC Appendix B Troubleshooting Guide B 1 Intoduction This chapter describes many common problems users may have with the CDB48500 USB possible causes and their solutions B
6. enne nnne B 1 B 1 1 1 Power LEDs are Not illuminated ee m B 1 1 1 2 CDB48500 is Not Recognized by the B 1 1 1 3 Unable to Run a Stereo PCM B 1 Revision HIStOTY seri 5 051405 M DIEI LA 02458555 B 2 iv CDB48500 USB Evaluation Kit Guide CIRRUS LOGIC aii Figures Figure 1 1 CDB48500 USB System Block Diagram sse nennen enne innen nennen 1 2 Figure 1 2 CDB48500 USB Top View 1 3 Figure 2 1 USB MASTER Driver Setup 11 2 2 Figure 2 2 Board Setup Diagram iiec citra cet date A Ea 2 3 Figure 2 3 Found New Hardware Service Window enne nnne nnns 2 4 Figure 2 4 Found New Hardware Wizard Welcome Window 1 2 4 Figure 2 5 Found New Hardware Wizard Finish Window 2 5 Figure 2 6 Microsoft Windows XP WINdOWS db p Sd puni 2 5 Figure 3 1 CDB48500 Block Diagram 3 1 Figure 3 2 Simplified Clock and Data Flow for up to 8 Channel ADC Inputs 3 6 Figure 3 3 Simplified Clock and Data Flow for S PDIF Input
7. nennen 3 7 Figure 3 4 CDB USB Master Card Clocking and Data Flow enne 3 8 Figure 4 1 PCM Pass through Example Application nennen nnns 4 2 Figure 4 2 System Configuration nri ennt nnn enn 4 2 Figure 4 3 Audio In via S PDIF In 4 3 Figure 4 4 Audio In via 8 Channel ADC enne nnn nnn nns 4 4 Figure 4 5 DAI Bevice Properties e bent RAEE ENSA 4 5 Figure 4 6 CDB48500 Digital Audio Output Properties 4 6 Figure 4 7 Codec DAC Properties rennen nnns enn 4 7 Figure 4 8 CDB48500 Comm Mode 1 4 8 Figure 4 9 Remap LEM 4 8 Figure 1 CS48500 System Block Diagram 6 Figure 2 DSP Input Data Multiplexing 7 Figur A 3 9 5 5 iet Ee ER ERRAT Deae near eee eR A 8 Figure 4 Serial Flash Memory Schematic ssssssssssssssssessesenee eene A 9 Figure 5 SPDIF Receiver Schematic enne
8. 1 4 1 2 2 3 CS485xx Family DSP Software 1 4 1 2 2 4 DSP Software Utility Information sseseeeeeennns 1 4 1 2 2 5 Audio CODEC Information nennen 1 4 1 2 2 6 S PDIF Receiver 1 1 4 Chapter 2 Board Setup and Installing the Evaluation Kit Software 2 1 eee 2 1 2 1 1 Installing the Evaluation Kit Software 2 1 2 1 2 Setting up the Evaluation Kit 4 2 3 2 1 3 Connecting Nc 2 4 2 1 4 Running a Stereo PCM Application on 0 48500 0 2 6 2 1 5 Downloading Other eene 2 6 Chapter 3 CDB48500 System Description 3 1 3 1 CDB48500 System Block Descriptions 3 2 3 11 Audio Inputs u c 4 te re t tr ei dece Ere 3 2 3 1 1 1 Analog Line level Inputs 3 2 3 1 1 2 Digital Optical Input 3 2 3 1 1 3 Digital Coaxial Input ennemis 3 2 3 31 14 Microphone InpUt iier Eo tci unie ue tete En 3 2 3 1 2 5 2 2
9. 13 18 0 1 P NI iea osa Seika RED ESI B 13810 DAOO HSO lt 25 tive 1 80 0505 m 24 576MHZ arc 13 71 DSP_DAO5 HS4 DAN B070 200 Tran pen E Marias hag MUxED DSP DAIS 03 0505 osp m 25470 pao RA pen t i aos 07 He 1 DSP DA00 Hs0 3 511 TEM E Qs 1 2 DAOT 3g gt 0 0 351 DAO1_D3 XMTA 53 5 _ t7 M 8IeNDA DA02 D0 HS3 H 57 BE B POTUM 05 DADS NS4 3 7 UEM voor cuo pur pue Mod E m C 31 pur our CURRENT MEASURE y 3 4 DSP L t TOP SIDE at least 3 vias per side 0SP_3V3 ssi 05 DA03 2 3 101 SPDI 380s326 A TSLF 7 m D NR CRORE Vobioz ES ove 3 AFSL wef 003 00103 41002 40 75 1 CURRENT MEASURE POINT C183 0 TOP SDE at least 3 vios per side cise our 16 TOTXIM7PL F T ine 5 ADC_SEL 131 DEFAULT SPI amp 120 ADDR Pen 131 SPOIF 12CH_ADC_SEL 28C3326 A T5L F T PART F 600 002
10. DESCRIPTION 0 48560 7 NPb 5 Block Diagram DRAWN BY wbd pd ENGINEER WBD mE 10 19 06 4 1 11 Figure 1 548500 System Block Diagram Shit 8 25 21607 80 10 v LOZ 140 09 9 V ON BOARD2 HDR2 101 058416 SCLK MUXED DSP SCLK2 CS8416 LRCLK MUXED DSP LRCLK2 CS8416 SDOUT MUXED DSP DAI4 CS42448 2 SDOUT2 SPDIF 12CH SEL J100 SPDIF HDMI SEL 1 J101 HDMI_MCLK MUXED_MCLK HDMI_SCLK HDMI_LRCLK HDMI_SDATA1 MUXED_DSP_SCLK1 HDMI_SDATA2 HDMI_SDATA3 HDMI_SDATA4 MUXED_DSP_DAIO SPDIF 12CH_ADC_SEL J100 CS8415 MCLK MUXED DSP DAI CS8416 LRCLK CSB416_SCLK CS42448_2_SDOUT3 CS42448_1_SDOUT1 MUXED_DSP_DAI2 CS42448 1 SDOUT2 MUXED DSP DAI3 MUXED DSP LRCLK1 DAIS PART 8 600 00262 Z1 REV A SHEET TITLE DSP INPUT DATA MUXING DATE 10 19 06 SHEET 2 11 Figure A 2 DSP Input Data Multiplexing Schematic Shit caar8zsa 1 50 10 Y LOZ 1uBuAdoo LN
11. E MUXED MCLK 2 0 8 8 Use these jumper settings for the clocking z mode and inputs shown in diagram E 2 z YY SDOUT l poa DAO DSP_SCLK SDN DSP_LRCLK DSP DAO 3 0 CS42 448 CS485XX 2 Figure 3 3 Simplified Clock and Data Flow for S PDIF Input Figure 3 3 illustrates the S PDIF clocking architecture used when any S PDIF RX is used as an audio source as described in Section 4 2 2 Changing the Audio Input Source on page 4 3 MCLK recovered from the incoming S PDIF stream is the MCLK for the system The 58416 also generates SCLK and LRCLK for the DAI side of the DSP from the recovered MCLK On the output side the CS485XX slaves to MCLK from CS8416 and masters SCLK and LRCLK for the DAC side of the CS42448 An example of this clocking scheme can be found in pcm cpa ili CIRRUS LOGIC 3 1 11 3 Clock and Data Flow for CDB USB Master Card Source MUXED DAI 4 0 CDB USB MUXED DSP LRCLK1 MASTER CARD MUXED DSP SCLK1 MUXED MCLK DSP SCLK 227 anm DSP_LRCLK a CS42448 CS 48 5XX DSP DAO 3 0 2 m SPDIF OUT Figure 3 4 CDB USB Master Card Clocking and Data Flow Figure 3 4 illustrates the clocking architecture used when IIS USB is used as an audio source as described in Section 4 2 2 Changing the Audio Input Source on page 4 3 MCLK is generated b
12. 250011 2 a 2d 4 3 30 3 3VD 3 3VD 2 SPDIF 12CH ADC SEL ANCZS7APW TSSOPIS 2 our im ROB SPDIF 12cH SEL 31 1 12 Channel ADC to DSP ine ADC SPDIF to DSP S3 32k R45 ZRI 29899 022 8 Channel C WX Sik ie on u n CS48560 CO7 SERAL um s seu Thus ys H n sarin 39 fm 50 2 i 34556111 SCP MOS 35 sce wosi 172 SDATAS v 1353 710 ScP_WOZSDA lt ON BOARD1 HDRI 5 4 tin HOWL io am 31 83 gt Header J102 feeds DAIL5 3 01 1 BSY EE C ADC SPDIF feed DAI 5 3 01 3 ROWCSEL BUF du gua MUXED_MCLK 3 5 7 ORCEOARZ wow2 3 ON BOARD2 HDR2 gt Header 102 feeds DAI 4 43 3vD 43 30 ADC SPDIF feed DAI 4 n Lg uH id LLL 131 LRCLK ADC SOATAE Bu uH TUE E 4 135 671 CS8416 7 Jas 5 eS 1 3 bh i nd ENEA C nE Riet ts gm BEP RESET gt 01 C4244872 50017 mE Cu DIE iHe is A esr thee 20 XU vec Hy 330 3 tno RECS i tj Hoson 21772121 tim DSP DBDA WATCHDOG OUT R146 10K 3 DEFAULT TO I2C BOOT MODE 3 6 1 DSP_DA02 HS2 EER 1 v taen DSP DAOI HS1 CO
13. cns YF AQUT 4B 5 171 aouT2_2 zi BAL 20 1 10K 17 91 wure_copec2 gt 28C5326 A TSL 2 AQUT SA E AQUT2 3 3 ice n D 3 738 wuTE_conece 9503326 A T5L 5 7 co 2 Ul 4 gt 8 q foe 8 02 28 3326 A TSL d 82 aour sa s T D em i 2700p 8 as 2 cra n t _6 gt El Bonyeza 121 lg 21 H Ds 8 gt Sessae utrs rr PART F 600 00262 71 OUTPUT FILTERS amp HP OUT PAE 10 19 06 9 11 Figure A 9 Output Filters amp Headphone Output Schematic Shit caar8zsa 21607 80140 102140 09 mos 45A R06 1 90k PREAMP OUTPUT TO ADC MC PREAMP 63 E 1 1054 INPUT po 1 8 3 5mm stereo BS 2 3 o gt 84 3523 54 2 8 7 043098 6 E ax ad Stak AUT Condenser MIC Reference Av 51 5 dB 8 2 Panasonic WM 61 Max Vin 7 mVpp ADC Vin 0 53 2 65 Vpp 79 E
14. 1 x E iudi 1 SO z pH MEE 2 SPI ADDR Ox9E CDB48520 120 ADDR 0x92 PART 600 00262 21 REV SHEET TNE 0542448 CODEC 2 DATE 10 19 06 SHEET 7o 11 Figure A 7 Codec 2 CS42448 Schematic Shut caar8zsa 1 50 10 Y LOZ 1uBuAdoo ol V CODEC 1 INPUT FILTERS 26 022 RGI 022 RED VERT 288K yc iu Au WV OR Ame e HS m ces me 0 ms cos a 7 5 T ANII 161 ANI_2 161 ED 5 dw VF VF m 430 cs 022 RED VERT ga m AM cm Ant 4 i de thy am RCJ 023 WHT VERT F4 Co ncs 06 p RCI 022 RED VERT AIN1 5 comes from the PREAMP CODEC 2 INPUT FILTERS RCJ 023 WHT VERT Reu 023 WHT VERT RoJ 023 WHT VERT 01 1 0 3 3 01 1 2 se m cuo 006 2700 _5 Ul cut tc YE E RCJ O22 RED VERT E RCJ 022 RED VERT rj RCi 022 RED VERT E304 c aa gt AN a En cur Ex Zio pr cue ELEC AM 8e UI cuz cot 2700p ec dc c 600 00262 71 REV SEET ME INPUT FILTER
15. 4 1 shows the DSP Composer main window for a PCM pass through application on the CDB48500 The blocks shown in the main window of DSP Composer can be selected from the folders in the left hand window pane and then connected together by wires to indicate the processing path as shown The Audio In and Audio Out blocks represent the hardware ports that need to be configured The Audio In block is used to select the S PDIF Input Analog input or USB input that is to be processed It configures the digital audio format for the CS8416 ADC side of CS42448 and the DAI port of the CS485XX The Audio Out block is used to configure the digital audio format for the DAC side of the CS42448 the DAO port of the CS485XX and enables or disables the S PDIF TX output port of the CS485XX DSP Composer CS485XX CDB app_spdif_in File Edit View Mode Tools Windows Help Ba connect gt Audio In Audio Out C713 anal Passthru Passthru Inputs LIR SPDIF_RXP System block Matrix Processing Modules MPM Virtual Processing Modules VPM Post Processing Modules PPM Spanning Modules Graphic Elements amp Blocks Outputs L AOUT 1A R AOUT 1B L RZSPDIF TX Figure 4 1 PCM Pass through Example Application Ss CIRRUS LOGIC 4 2 1 System Block The
16. Audio DSP The CS485xx audio DSP U6 are a family of 32 bit fixed point processors designed specifically for audio applications The CDB48500 allows a designer to evaluate the CS485xx DSPs in many different modes of multi channel input and output The 48 pin footprint on this board is compatible with any 5485 chip Audio input data to the DSP can come from any of the following sources e CS8416 U3 e CS42448 U4 and U5 USB MASTER card Header for external codecs not yet supported Audio output data from the DSP can be sent to the following destinations Both CS42448 s for conversion to Analog Output AOUT 1A AOUT 6B Optical S PDIF Out SPDIF TX this option disables AOUT 4A and AOUT 4B USB MASTER card The CS485XX has many applications stored in internal ROM but a host is still required to configure the application for a particular system The CDB48500 USB allows the PC to act as a host to boot and configure the DSP through the GUI software The 5485 can also be booted from external serial flash for custom applications that are not stored in the DSP s ROM Note The 48 pin footprint on this board is also compatible with the 485 family of DSPs The CDB48500 can support any 5485 chip if the alternate stuffing options shown on the DSP schematic page have been followed CIRRUS LOGIC 3 1 8 CS8416 S PDIF RX The CS8416 U3 is 192 kHz S PDIF receiver with an integrated inpu
17. CUSTOMER AGREES BY SUCH USE TO FULLY INDEMNIFY CIRRUS ITS OFFICERS DIRECTORS EM PLOYEES DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY INCLUDING ATTORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus the Cirrus Logic logo designs and DSP Composer are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trade marks or service marks of their respective owners DTS is a registered trademark of the Digital Theater Systems Inc DTS NEO 6 is a trademark of the Digital Theater Systems Inc It is hereby notified that a third party license from DTS is necessary to distribute software of DTS in any finished end user or ready to use final product SRS Circle Surround and Trusurround are registered trademarks of SRS Labs Inc SRS Focus and Dialog Clarity are trademarks of SRS Labs Inc The CIRCLE SUR ROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs Inc and by Valence Technology Ltd and licensed to Cirrus Logic Inc Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND TECHNOLOGY i e CIRCLE SURROUND LICENSEES must first sign a license to purchase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to and the satisfactory passing of performance verification tests performed by SRS Labs Inc or Valence Technology Ltd E mai
18. DC Power Input Jack 9Vdc to 12 425 CIRRUS LOGIC 1 2 2 Related Documentation The documents described in this section are updated periodically and may be more up to date than the information in this document Check the Cirrus Logic Internet site for the latest updates 1 2 2 1 Additional CDB48500 Evaluation Board Information The following information about the CDB48500 Evaluation Board can be obtained from your Cirrus Logic representative Schematics BOM Artwork and PCB stackup 1 2 2 2 CS485xx Family DSP Hardware Information The following documents are installed with the CS485xx System Development Kit SDK CS485xx Family Data Sheet e CS485xx Hardware Users Manual e CS485xx Errata 1 2 2 3 CS485xx Family DSP Software Information The following document is installed with the CS485xx SDK e AN298 CS485xx Firmware User s Manual 1 2 2 4 DSP Software Utility Information The following document is installed with the CS485xx SDK DSP Composer User s Manual The documents listed above are updated periodically and may be more up to date than the information in this document Check the Cirrus Logic Internet site for the latest updates 1 2 2 5 Audio CODEC Information The following information is located on the www cirrus com Internet site e CS42448 Data Sheet CS42448 Errata 1 2 2 6 S PDIF Receiver Information The following information is located on the www cirrus com Internet site
19. MCLK master audio clock The CS8416 slaves to the CS8416_SCLK and CS8416 LRCLK signals which are used to shift 125 data out of the CS8416 and shift 125 data into the 5485 The CS8416 has 2 different S PDIF inputs available to it One is optical on one is coaxial Refer to Section 4 2 2 1 Audio In via S PDIF on page 4 2 to determine how to configure the board for optical or coaxial input A general purpose output of the CS8416 is used to generate an independent reset signal for the CS42448 audio CODEC Providing a separate reset line for each audio device allows the system to sequence the order in which audio devices come out of reset The USB MASTER drives the serial host control port and 58416 RESET signals on this page The RCA jack for coaxial S PDIF input and optical jack for optical S PDIF input is listed on this page too A 1 1 1 6 Codec 1 CS42448 See Figure 1 6 The CS42448 is a multi channel ADC DAC that is capable of simultaneously supporting up to 6 channels of analog input and 8 channels analog output This is one of the two CODEC The serial host control port SCL CCLK SDA CDOUT AD1 CDIN ADO CS shares clock and data lines with the CS485XX and CS8416 Both CODECS share the CS42448 CS line to this chip and driven only when in SPI mode The pull ups required for the SCL and SDA pins are shared with the other devices on the CDB48500 board CIRRUS LOGIC The CS42448 RST signal is a dedicated reset signal d
20. to Master to indicate that the S PDIF transmitter masters MCLK SCLK and LRCLK as described in Section 3 1 11 2 Clock and Data Flow for S PDIF Input on page 1 7 The Audio In module with S PDIF In as the input source is shown in Fig 4 3 iili EE CIRRUS LOGIC Input source 2 Data format 125 24 bit Figure 4 3 Audio In via S PDIF 4 2 2 2 Audio In via 8 channel ADC To deliver data to the DSP via 8ch ADC drag the Audio In block to the work space and select Analog 8 ch as the Input Source Double click the Audio In block to see the signal flow The device properties of the Analog 8 ch element lets you select if the sampling frequency of the ADC on the 542448 CODEC The Master Slave property must always be set to Master to indicate that the ADC will master SCLK and LRCLK as described in Section 3 1 11 1 Clock and Data Flow for up to 8 Channel ADC inputs on page 1 6 The Audio In module with Analog 8 channel as the input source is shown in Fig 4 4 Enable mic input Input Fs 1 Fs Figure 4 4 Audio In via 8 Channel ADC 4 2 2 3 Audio In via USB This feature is currently not supported Ss CIRRUS LOGIC 4 2 2 4 DAI Input of CS485xx Each of the Audio In Elements listed above are connected to a DAI element This represent the DAI port of the DSP As shown in Fig 4 5 This dialog allows the user to set the following parameters for the CS485xx SCLK
21. 1 1 Solutions to Possible Problems B 1 1 1 Power LEDs are Not illuminated DC power supply is not connected to CDB48500 make sure the DC wall supply is connected to the DC power input jack J25 and the supply is plugged into a wall outlet Power selection headers J17 J18 J19 are set incorrectly if you are using the DC wall supply provided with the CDB48500 USB all jumpers should be in the REG position If you are using an external power supply for any of the system voltages 5V 3 3V 1 8V make sure that the jumper for that voltage has been removed and power is applied to the center pin of the appropriate header B 1 1 2 CDB48500 is Not Recognized by the PC DC power supply is not connected to CDB48500 the CDB48500 is not a USB powered device Make sure the DC wall supply is connected to the DC power input jack J25 and the supply is plugged into a wall outlet CDB48500 USB Drivers not installed before connecting to PC Pull the DC power plug on the CDB48500 Open the device manager on the PC and search for the Opal Kelly device under USB Devices If there is a question mark next to the device right click on it and open Properties Press the Update Driver button and let Windows automatically find the driver Wait 3 seconds and plug DC power supply back in B 1 1 3 Unable to Run a Stereo PCM Application If after unsuccessfully following the instructions in Section 2 1 4 Running a Stereo PCM Ap
22. 255252655585255248 25554 5815 eter 3 2 3 1 2 1 Analog Line level Outputs 1 nennen nnne 3 2 3 1 2 2 Headphone eene ennemis 3 3 3 1 2 3 Optical Digital Output PCM en 3 3 3 1 3 DC Power Inp Ut etre gerente pne PE RR RE Rae 3 3 3 1 4 Control eter etae to Sce Eee ea rre 3 3 3 1 5 On Board Voltage Selection Headers ssssssssssssseeeeeeenn nn 3 3 3 1 6 Audio Input Source Multiplexer Selection 3 4 3 1 7 Cirrus Logic 5485 Audio ener enne nnne nnns 3 4 3 1 8 658416 S PDIF itte eet ot eliza Ged ecd Peta ze o aa eei abides 3 5 3 1 9 CS42448 Audio 3 5 MEMO t 3 5 Clocking 3 5 3 1 11 1 Clock and Data Flow for up to 8 Channel ADC 3 6 3 1 11 2 Clock and Data Flow for S PDIF Input ssss 3 7 3 1 11 3 Clock and Data Flow for CDB USB Master Card Source 3 8 CDB48500 USB Evaluation Kit Guide iii CIRRUS LOGIC CDB48500 Chapter 4 Configuring the CDB48500
23. 48 50 0 0 amp Audio Data Future Development p e e e Figure 1 1 CDB48500 USB System Block Diagram This document will concentrate on the features and basic operation of the CDB48500 USB board Detailed information regarding the operation and programming of the CS485XX DSP is covered by the 5485 data sheet C8485XX Hardware User s Manual and application note AN298 see Section 1 2 2 Related Documentation on page 1 4 for more details The CDB48500 USB is a convenient and easy to operate evaluation platform It has been designed to demonstrate the majority of the CS485XX functions on a small 6 x 6 5 base board These features include PC control of the CS485XX using the DSP Composer graphical user interface Serial control of audio devices on CDB48500 12 9 or SPI protocols Digital audio input of PCM via optical or coaxial S PDIF does not support compressed data input Up to 12 channel analog audio input via the two CS42448 audio codecs Up to 12 channel analog output through the two CS42448 audio codecs Digital audio output of PCM data via optical S PDIF Headphone output jack Multi channel digital audio input via the CDB USB MASTER card not yet supported Separate input and output clocking domains to allow 1FS to 2FS audio processing on the C8485XX Fast boot host controlled master boot HCMB of custom applications from 4 Mbit serial SPI flash device Microphone input with integrated amplifier for Int
24. 62 71 REV A NOTES UNLESS OTHERWISE SPECIFIED SETTE T YNAMICALLY BY DRIVING 3 0 PINS ue SIZE 1 BOOT MODE FOR 485 SELECTED DYN 10 19 06 wes 360 Figure A 3 DSP Schematic Shut caar8zsa 21607 80 10 v LOZ 140 09 ev SPI FLASH ET un E 1 esr LS Er MSG7SDA 3 50 WP s 1 ATASDBOETE SU SOB z molo 433 Sur 555 NORMAL 5 L 3 111 DSP BSY7EE CS C gt g 105 5 i89 r3 gt e A ARES PROGRAM o GST2SLFO404 33 4C S2AE 34 67 11 SCR MSO SDA XS dm HOT usm iw uu 84108 245 Beier 120 EEPROM m nw ENT us sepe E EG sc SDK oh leur Tow ADDRESS 1010 A2 A1 AO CDB48520 12 ADDR OxA2 600 00262 21 REV Seer me SERIAL FLASH 10 19 06 P wn 4o 11 Figure A 4 Serial Flash Memory Schematic Shut caar8zsa 1 50 10 Y LOZ 1uBuAdoo 6 m 9 Soa 2 e lour ehe 28 Ie R TORHUPUE m fene 23 pour SPDIF RX 8AX 5 Note R3
25. Bu doo LEV 542448 pulled high by pull up on CODEC 1 3 SCP CLK Ep 54 6 SCP MSO SDA ANZ 6 CODEC FILT ADE Tes Tew des ELEC Sow our Tio CODEC V Vo DAC Ts lens ELEC oou qw F5VA 64 53 8 52 i Teno cros ese t cles ELEC 134 56 5 SCP MOSI pulled low by pull down on SPDIF RX page E i E 18 E 81 i oono Tiu I pour 82 16 Havo Es AN2 24 81 ROME 1 CSPE RSTO Hast Jamit 00 E AMO ui 15 8 CS8418_LRCLK C SE us 310 pma cs42448 coz tiec 881 AQUIZ 8491 Sur SS 1 200013 0 500013 t 0842448 2 420012 12 l be spoutz 6842448 02 0 131 0540448 2 500011 21204 6481 ym 05 DAOS NSA 2 5 AQUT2 51191 um 08603048 C 43445558 88 E cobtc2 te EB DSP_DAOS AMTA 1 ADUT2 44191
26. C3 close to U3 88416 18016 13671 501361 ao 336 7 33 S AS pooopr H oc Sov 117155 1 cajou 2 lep ossi 22 1 spout 28 m 51 m oPTIcAL expo 25 ts SPDIF_Rx_coAX suck 24 s 25 2 v G 22 honurgu Nm mo ROAST 3 20 20 H2 laxps HZ en ser gt Per H 34 1 00 H wa CSb415 CZ2 E SOFTWARE MODE m 225 M 88416 SDOUT 131 JXTALLOUT 131 CSBHE NT D ScP_WISO SDA 34 COschuk 13 4 8 7 11 SPI ADDR 0x20 122 ADDR 0010 AD2 AD ADO 0 CDB48520 120 ADDR 0 2 JSCP NOSI 13467401 600 00262 71 REV 9 58416 SPDIF RECEIVER 10 19 06 ser 5 11 Figure A 5 SPDIF Receiver Schematic Shut caar8zsa 1 50 10 Y LOZ 1uBuAdoo
27. CDB48500 board is populated with a CS48560 However it is possible to evaluate the CS48520 CS48540 CS48560 CS485AU2B and CS485DV2B on this board When you drag the system block on to the work space a popup menu is displayed as shown in Fig 4 2 This menu lets you choose the target chip that you need to evaluate When you select the target chip place the template of the target chip on the analog connectors The template is a guide that shows which input output channels are valid for the selected chip System Properties Target chip Ref clock freq 24 576 R Core Speed 152 Firmware version V01 Figure 4 2 System Configuration 4 2 2 Changing the Audio Input Source The audio input to the DSP is selected through the Audio In block in DSP Composer The Audio can be delivered to the DSP via the following S PDIF J100 on S PDIF e Analog J100 on 12 _ Analog J100 on 8CH_ADC Analog J100 on 2CH ADC USB IIS Echo Audio 4 2 2 1 Audio In via S PDIF To deliver data to the DSP via S PDIF drag the Audio In block to the work space and select SPDIF as the Input Source Double click the Audio In block to see the signal flow Right Click on SPDIF Rx The device properties of the S PDIF IN element lets you select if the SPDIF input is on SPDIF_RXP Optical In or on SPDIF RXN Coaxial The Input FS depends on input stream and must not be changed The Master Slave property must always be set
28. ER Rr ERR EE 1 5 e qu RP crasse ik Rusa e diei A 1 A 1 1 1 Detailed Schematic Descriptions sess A 1 A 1 1 1 1 CS48500 System Block Diagram See Figure 1 A 1 A 1 1 1 2 DSP Input Data Multiplexing See Figure 2 A 1 A 1 1 1 3 Coyote DSP Core See Figure 3 A 1 A 1 1 1 4 Serial Flash Memory See Figure A 4 A 2 A 1 1 1 5 S PDIF Receiver See Figure 5 A 2 A 1 1 1 6 Codec 1 CS42448 See Figure 6 A 3 A 1 1 1 7 Codec 2 CS42448 See Figure 7 A 3 A 1 1 1 8 Codec 1 and Codec 2 Input Filters See Figure 8 4 A 1 1 1 9 Output Filters amp Headphone Output See Figure A 9 4 A 1 1 1 10 Mic and Pre Amp See Figure 10 A 4 A 1 1 1 11 Control Connector and Power See Figure A 11 4 Appendix B Troubleshooting B 1 Bil INtOdUCUON ss ueni Ie RII RUE Ra EUER B 1 B 1 1 Solutions to Possible Problems
29. IS C5974 1993 F05 Reference Designator J2 or SPDIF_RXP 3 1 1 3 Digital Coaxial Input Note Digital Coaxial Input is PCM only as there is no multi channel decoder present on CDB48500 USB Connector Type RCA Female Maximum Signal Level 3 3V Minimum Signal Level GND 0 7V Reference Designator J31 or SPDIF RXN 3 1 1 4 Microphone Input Absolute Maximum Signal Level 5V Absolute Minimum Signal Level GND 0 7V Full Scale Amplitude 7mVp p Reference Designator J5 The microphone preamplifier shares the AIN1 5 ADC with the AIN3_A RCA jack Only one analog source can be sampled at any given time When the microphone input is selected the AIN3 A audio jack is ignored The default configuration enables the AIN3 A audio jack 3 1 2 Audio Outputs 3 1 2 1 Analog Line level Outputs Connector Type RCA Female Full Scale Amplitude 1 21VRMS e Reference Designators J13 J16 J33 J40 or AOUT 1A AOUT 6B 3 1 2 2 Headphone Output Connector Type 1 8 TRS Female Full Scale Amplitude 3 53 VRMS e Reference Designator 420 or HP OUT CIRRUS LOGIC 3 1 2 3 Optical Digital Output PCM Connector Type Fiber Optic TX for Digital Audio JIS F05 JIS C5974 1993 205 Reference Designator J24 or SPDIF_TX The S PDIF output uses the same data line as AOUT_4A and AOUT_4B When the digital output has been enabled and you have speakers connected to AOUT_4A and AOUT_4B white noise will be heard T
30. LEC 10046 600 00262 21 TE MIC PREAMP mE 10 19 06 BU wer 100 11 Figure A 10 Mic Preamp Schematic Sh caar8zsa 1 50 10 Y LOZ 1uBuAdoo 9160 330 5 R72 R74 576 243 243 h h RED GREEN YELLOW 2 USB BOARD CONNECTOR 45 300 Vib_BRD_1 8VD 3 Ohm placeholders for Series term of USB BR a Res HM 13 os b ba HOWCERCLK ASET sep i im 1 _ 5 5 DMCSDATA 11 34 9571 SCP TEE T HOMISDATAS 31 1541 DSP BSY EE 3 6 20002 HDMLSDATAK 131 5 i M RIDE SPDIF ROWLSEL 31 05080 34 R87 0 E DS 13671 PONT SDATAS A a 2 DSP 50 3 61 677 0 1367 Sraka 0 pAQVASI 38 08 5 ete 38 eet sepa ante vip_eRD_s 3vD Even Odd swap of USB DIO 43 to J11 ms gj ium INo POP The ted B E vn 12 TP z m E 3 E GND TEST POINTS No SPCR STANDOFF 4 40 THR 875L AL NPb roS um e
31. LOGIC Chapter 3 CDB48500 System Description A detailed block diagram of the CDB48500 Customer Development Board is shown in Figure 3 1 The sections that follow provide a detailed description of each block MIC Preamp Up to 12 D Analog Outputs uS MIC In DEM 0 0 l 542448 M Headphone ADC Data ELS ES EM ____________ PU usps Pt USB Clocks Data e m 5 1 12 2 5485 I2C FLASH m gt 5 1 S PDIF ___ DSP RESET gt _ 5 In Figure 3 1 CDB48500 Block Diagram CIRRUS LOGIC 3 1 CDB48500 System Block Descriptions 3 1 1 Audio Inputs 3 1 1 1 Analog Line level Inputs Connector Type RCA Female Absolute Maximum Signal Level 6 5V Absolute Minimum Signal Level GND 0 7V Full Scale Amplitude 2VRMS Reference Designators 4 J6 J10 J12 J26 J30 or AIN1A AIN6B 3 1 1 2 Digital Optical Input Note Digital Optical Input is PCM only as there is no multi channel decoder present on CDB48500 USB e Connector Type Fiber Optic RX for Digital Audio JIS 205 J
32. Polarity LRCLK Polarity Reference Clock Set to the frequency of the crystal driving the CS485XX Y1 This is the reference clock is used to determine the clock dividers needed to derive Fs in ADC only applications If this number changes then all dividers for LRCLK SCLK will change by the same ratio e g 024 576 MHz MCLK 512 1Fs LRCLK 912 288 MHz MCLK 256 1Fs LRCLK DAI Properties SCLK polarity Rising edge LRCLK polarity Channel 0 low DAI clock source DAI2 LRCLK DAI2 SCLK DAI2 clock source Figure 4 5 DAI Device Properties 4 2 3 Changing Audio Output Configuration The audio output section of the CDB48500 is configured through the Audio Out block in DSP Composer 4 2 3 1 DAO Output of CS485xx The digital audio output of the 485 is very flexible making it compatible with a wide variety of audio devices This port can configured using the dialog box shown in Fig 4 6 Right click on the Audio Out block then select Device Properties Right clicking the DAO block and selecting Device Properties produces the DAO Properties dialog il ERES Ss CIRRUS LOGIC Passthru Audio Out input 7 DAO Properties LRELK polarity SCLK polarity Rising edge valid 0401 0402 relationship Dependent MCLK SCLK ratios Automatic v Figure 4 6 CDB48500 Digital Audio Output
33. Properties This dialog allows the user to set the following parameters for the 5485 Audio Output LRCLK polarity Select the phase of LRCLK when the left sample will be shifted out SCLK polarity Select which edge of SCLK for which the output data will be valid e 2 relationship Select independent or unified clock domains for the DAO1 and DAO2 audio output ports MCLK SCLK Ratios Select the ratio of LRCLK to MCLK and LRCLK to SCLK 4 2 3 2 CS42448 DAC Properties The analog output properties are selected through the CODEC DAC Properties dialog box in DSP Composer as shown in Fig 4 7 Right click on the Audio Out block then select Device Properties and select Codec DAC to edit the device properties of the Codec DAC Right clicking on the DAC block does not reveal the device properties of the Codec DAC as the Codec DAC device properties are previously set at the higher level the Audio Out Block il ERES CIRRUS LOGIC Passthru Audio Out a input 7 Audio Out Properties it sclk Irclk master device Codec DAC Data format 125 24 bit Dutput Fs 1 Fs Enable SPDIF output Figure 4 7 Codec DAC Properties This Audio Out dialog allows the user to set the following parameters for the CS42448 DACs Audio Data Format 125 or Left Justified 24 bit Output Sampling Frequency Range Select the Fs range
34. S 10 19 06 PRES ser Bo 11 Figure A 8 Codec 1 and Codec 2 Input Filters Schematic Shit caar8zsa 1 50 10 Y LOZ 1uBuAdoo rv E as aouta 163 AQUTLM E 3 2 6 d 21 ans i 1 257 18 x t 09 1681 cobtci 98c3326 K T5L F 7 1691 1 E c SE no j 5 6 AouTL_3 C 4 AAA 7 26 i E i R55 T t D 8 1 E or 163 cobECI 2505326 A TSL F T 1681 CODECI 2Sc3326 A T8L F T 439 ex EE AQUT_3A E ADUT 38 E t8 aouri s 1 4 a JE i4G E T 8 Tos WE L W i m 168 tes wore copeci Sicss26 A T8L7 T E dam eus YA Tour Saw nec cus coe E cuo 3 tn pour 84 vo suc ase OUTI 28 on cmn RIB amp 100K Mure GND HE 5 Ei 781 wure_cooece ow 8 171 Mi P 2 ELEC RI T E 5
35. T position while connected to the CDB USB MASTER will prevent the board from operating The unpopulated header J3 is also designed for a special mode that brings 12V from the control header but cannot be used when connected to the CDB USB MASTER CIRRUS LOGIC 3 1 6 Audio Input Source Multiplexer Selection Headers The CDB48500 USB includes jumpers to change DSP DAI inputs e Source 0 CDB USB MASTER Board controlled from Software Refer to Section 4 2 2 Changing the Audio Input Source on page 4 3 Source 1 2 Channels from CS8416 and 8 channels from 2 CS42448 short pins 2 and of J100 Source 2 12 Channels from 2 CS42448 codecs short pins 1 and 2 of J100 Reference Designators U1 U2 09 018 and J100 These multiplexers are used to select which audio sources feed the CS485XX DAI pins When the on board sources CS8416 U3 and CS42448 U4 and U5 are being used the CDB USB MASTER data cannot be processed The CDB48500 contains a header to connect DAI pins DAO pins and clocks to external circuitry The DAO and clock pins are DAI 5 3 0 feed from J102 header short pins 1 and on J101 DAI 5 3 0 feed from on board sources short pins 3 and 5 on J101 DAI 4 feed J102 header short pins 2 and 4 on J101 DAI 4 feed from on board sources short pins 4 and 6 on J101 The DAO pins and clocks are paralleled to both the on board devices and J102 J103 headers 3 1 7 Cirrus Logic 485
36. cy policy Can Windows connectto Windows Update to search for software QO Yes this time only QO Yes now and every time connect device 8 notthis time Click Next to continue Figure 2 4 Found New Hardware Wizard Welcome Window 5 Windows will then ask whether to use automatic installation or manual installation Allow Windows to install the software automatically and click Next il A CIRRUS LOGIC Found New Hardware Wizard This wizard helps you install software for Opal Kelly XEM3001v2 If your hardware came with an installation CD x floppy disk insert it now What do you wantthe wizard to do Install the software automatically Recommended C Install from a list or specific location Advanced Click Next to continue lt Back gt Figure 2 5 Found New Hardware Wizard Finish Window 6 Itis possible that during the installation Windows might issue a warning that the drivers have not passed Windows Logo testing Select Continue Anyway Hardware Installation A The software you are installing for this hardware Opal Kelly XEM3001 2 has not passed Windows Logo testing to verify its compatibility with Windows XP me why this testing is important Continuing your installation of this software may impair or destabilize the correct operation of your system either immediately or in the future Microsoft strongly recommends t
37. e CS8416 Data Sheet e CS8416 Errata 1 1 The symbol is used throughout this manual to indicate the end of the text flow in a chapter il ERES CIRRUS LOGIC Chapter 2 Board Setup and Installing the Evaluation Kit Software 2 1 Introduction It is important to install the Evaluation Software BEFORE connecting the USB cable from the PC to the CDB USB MASTER card Failure to install the evaluation software before the initial connection can result in an inability to communicate with the CBD485xx 2 1 1 Installing the Evaluation Kit Software The DSP evaluation software installation will first install the Cirrus Logic DSP evaluation software followed by the USB drivers required to communicate with the CDB USB MASTER 1 Run the latest DSP evaluation software installation executable CS485xx eval kit rc revision number gt exe This executable is supplied by your Cirrus Logic representative At the Welcome screen click Next At the Licensing Agreement window select the I accept the agreement radio button to agree to the terms and then select Next Select the Destination Location window Select the default location C CirrusDSP and click Next Select Start Menu Folder window Select the default location C CirrusDSP and click Next 6 The Ready to Install window indicates the selected destination location and the Start menu folder for confirmation select Install to begin the insta
38. e Requirements Digital or Analog Audio Source e g DVD player PC with a digital audio card device Amplified Speakers for audio playback e g powered PC speakers AVR amp speakers 1 1 5 Cabling Requirements Digital Audio Inputs S PDIF Optical or Coaxial RCA Cables Connect to digital audio card audio analyzer or DVD player Digital Audio Output S PDIF Optical Cable Connect to digital audio card audio analyzer or AVR Analog Audio Inputs RCA Audio Cables Connect CDB48500 line level inputs to analog audio source Analog Audio Outputs RCA Audio Cables Connect CDB48500 line level outputs to powered speakers 1 2 Introducing the CDB48500 USB Customer Development Kit The CDB48500 USB kit is composed of the CDB48500 customer development board and the USB MASTER Control board The CDB48500 provides a practical platform for emulating a typical multi channel audio system application The CDB USB MASTER is a USB control board used to interface the host PC to the CDB48500 board and convert GUI commands into the serial control protocol required for configuring the CS485XX DSP 2 CS42448 codecs and CS8416 S PDIF receiver ICs Figure 1 1 shows the relationship illl mal CIRRUS LOGIC between the PC CS485XX and the CDB USB MASTER LLI Serial Control Interface Reset Signals ort PC Board Control Signals C D B
39. e user to click Finish to exit the Setup wizard 2 1 2 Setting up the Evaluation Kit Boards coBaasao Optical Output on Du E DVD Player UNUSED S Optical Cable a 8 E r1 2 2 E lt lt lt SPDIF RXIN C IAIN 6A e a 5 AIN 5B AIN 4B Analog 5 8 5 8 5 5 5 gt 5 3 AIN 3B 3 3 9 5 8 5 548560 UNUS UNUSED UNUSED SPDIF TX e Cable BE a e Qus J UNUSED AOUT 1B USB 2 0 A Port _ AOUT 2B Powered Speakers Power Cable Optical Output RCA Cables UNUSED Figure 2 2 Board Setup Diagram 1 Place the CDB48500 and the USB MASTER on a static free surface 2 If the boards are not mated connect them together as shown in Fig 2 2 Notice that the USB connector on the USB MASTER and the power connector on the CDB48500 are on the same side 3 Connect the Power Supply as follows A Connect the power supply jack to the CDB48500 board at J25 and the adapter to a wall power socket or power strip B Check that the D3 green 3 3V D2 red 1 8V and D4 orange 5V power indicator LEDs illuminate on the CDB48500 4 Setup Audio Input connection
40. elligent Room Calibration IRC evaluation future Supports all members of the 485 family in the 48 pin LQFP package Note Not all features of the CS485xx are exercised on the CDB48500 1 2 1 Identifying CDB48500 USB Components Figure 1 2 shows the top side of the CDB48500 USB Evaluation Board The accompanying legend identifies the main components of the board caar8zsa 91601 sni 1021468 02 5 1 gt L D L E Legend A CS485XX DSP U6 E 4 Mbit Serial Flash U11 Coaxial S PDIF Input Jacks PCM only J31 M 3 3V Switching Regulator 1 5A U8 Q 5V Selection Header Regulator External J19 U Optical S PDIF Output Jack J24 E 8 4 B CS42448 Audio CODEC 04 C CS42448 Audio CODEC U5 F Headphone jack J20 G 1 8 Microphone Input Jack J5 J Analog Inputs 2 Vrms Max K USB Connector on CDB USB Master P1 N 3 3V Selection Header Regulator 0 1 8V Selection Header Regulator External J17 External J18 R 5V Linear Regulator 1A U7 S Analog Audio Outputs V Power Indicator LEDs W On board External Digital Audio Mux U1 amp U2 U1 amp U2 are on back of PCB Figure 1 2 CDB48500 USB Top View JIDOT SR D CS8416 S PDIF Receiver U3 H Optical S PDIF Input Jacks PCM only J2 L Alternate 12V Jumper J3 P 1 8V Linear Regulator 1A U14 T
41. em amp DAO1 DATAO Left DAO1 DATAD Right DAO1 DATA Left DADO1 DATA Right DAO1 DATA2 Left DAO1 DATA2 Right AMT Left AMT Right DAO2 DATAD Left DAO2 DATAD Right DAO2 DATA Left DAO2 DATA Right paR DAO Remap Figure 4 9 Remap Tab 4 2 6 S PDIF Transmitter The CDB48500 is designed with one S PDIF Transmitter output The content of the S PDIF Transmitter output is controlled by the Remap tab in the System module The 6 SPDIF L is used to select the channel that will be output on the left channel and 7 SPDIF R is used to select the channel that will be output on the right channel The Remap tab is shown in Fig 4 9 il ERES CIRRUS LOGIC Appendix A Schematics A 1 Introduction Updates to the schematics for the CDB48500 Development Board can be can be obtained from your local Cirrus Logic representative as part of a design package including the associated BOM and layout artwork The schematics are provided in Adobe s portable document format PDF and PADS format A 1 1 Schematic Pages The schematics included in this document are the original Revision A schematics of the CDB48500 and reflect the board as it was manufactured Newer schematics may be available which incorporate feature additions or corrections and may not reflect Rev A hardware A 1 1 1 Detailed Schematic Descriptions 1 1 1 1 CS48500 System Block Diagram See Figure 1 1 The CS48560 system block d
42. es with the CS485XX and CS8416 Both CODECS share the CS42448 CS line to this chip and driven only when in SPI mode The pull ups required for the SCL and SDA pins are shared with the other devices on the CDB48500 board The CS42448 RST signal is a dedicated reset signal driven by a general purpose output of the CS8416 The CS42448 is a slave to the MUXED MCLK signal which is the master audio clock for the entire CDB48500 system The CS42448 masters the 58416 SCLK and 58416 LRCLK signals which are used to shift 125 data out of the CS42448 and shift 125 data into the CS485XX when ADC is used as the data input for the DSP The CS42448 slaves to the DSP_SCLK DSP LRCLK signals which are used to shift 125 data out of the CS485XX and shift 125 data into the 542448 The analog inputs and outputs of the 542448 are being used in single ended mode This is evident when looking at the input and output filter circuitry on page 6 of the schematics The transistor connected to MUTEC Q11 provides the current drive necessary to drive all of the mute transistors see page 9 of schematic into saturation Each output of the CS42448 has an output filter that consists of an AC coupling cap 3 3 uF a pull down resistor to prevent the output from floating when not connected to a load a series resistor 470 to provide a voltage drop when the muting transistor is enabled and a mute transistor that will pull the output low when the mute contro
43. essarily the 3 3 V regulator The 3 power jumpers J17 J18 J19 are used to choose between the on board regulators and an external source for 5 V 3 3 V and 1 8 V This is a feature intended only for special applications so these jumpers should be left in the REG position for normal operation The DC input power jumper J3 is used to bring the main 9 to 12VDc supply voltage from the control connector J11 rather than the standard DC input connector J25 This jumper is not populated on the board and is intended only for special applications 3 should not be used in normal operation caar8zsa 21607 80 10 v LOZ 140 09 S V HDMI Clock Data SPI I2C MIC Preamp ADC Data CS42448 x2 DETAIL ON NEXT PAGE SPI FLASH I2C FLASH 5 RESET BRD_RST CS48560 _OUT XTAL S PDIF IN Audio Out S PDIF Data _RST CS42448 ECO REV DESCRIPTION INC BY DATE CHK BY DATE w o 0718 05 HEADPHONE OUT 12x Analog Outputs S PDIF OUT 1 Block Diagram 2 DSP Data Input Muxing Diagram 3 CS4953xx DSP 4 FLASH 5 CS8416 SPDIF RX 6 CS42448 1 ADC and DAC 7 CS42448 2 ADC and DAC 8 Analog Inputs 9 Analog Outputs amp Headphone 10 Preamp 11 Power and Connectors 600 00262 71 REV
44. ge These parameters should be considered when choosing the microphone to be connected to the CDB48500 Too large of a signal on the CS42448 analog input will result in distortion of the sampled signal It is important to note that although the amplifier circuit shown is non inverting the input to U12 B is the same polarity as the output from U12 C the output of an ECM is inherently inverted since it acts as an open collector device Therefore the microphone signal driven to the CS42448 should be considered an inverted signal for processing purposes A 1 1 1 11 Control Connector and Power See Figure 1 11 There is one control connector on the board J11 This 50 pin connector provides pins for the following functions Serial control interface for configuring the DSP codecs and S PDIF RX Resetlines for the DSP and other board devices Pins to provide power to the USB MASTER USB control board Aninterface for delivering audio data to and from the USB board feature not yet available The DC input connector J25 for the CDB48500 can accept 9 to 12 and the power supply should be capable of supplying at least 1 amp of current The 3 voltage regulators on the CDB48500 generate the 1 8V 3 3V and 5V necessary for powering all of the ICs on the board Note that the 5 V and 3 3 V regulators run directly off the DC input supply connected to the CDB48500 while the 1 8 V regulator is dependent upon 3 3 V system power not nec
45. gs for the clocking 5 mode and inputs shown in diagram 9 lt 2 SDOUT I gt DAI DAO DSP SCLK gt SDIN 8 DSP_LRCLK gt lt Analog CS485XX eow 0542448 Inputs 2 S PDIF OUT Figure 3 2 Simplified Clock and Data Flow for up to 8 Channel ADC Inputs The ADC clocking architecture is used when the ADCs are used as the only audio input i e S PDIF is disabled as described in Section 4 2 2 Changing the Audio Input Source on page 4 3 and the audio input source multiplexer U1 U2 is used to select on board audio sources Figure 3 2 illustrates this clocking configuration The jumpers must be set as described above XTAL OUT from the CS485xx is MCLK for the system The CS8416 slaves to this MCLK and generates SCLK and LRCLK for the ADC side of the CS42448 and the DAI side of the DSP On the output side the CS485xx slaves to MCLK from CS8416 and masters SCLK and LRCLK for the DAC side of the CS42448 An example of this clocking scheme can be found in pcm mc 1fs cpa milli o a ES CIRRUS LOGIC 3 1 11 2 Clock and Data Flow for S PDIF Input MUXED DSP LRCLK1 MUXED DSP SCLK1 p B 2 5 6 8 e SPDIF VENT o UN PDIFinput Input baad PLL 5
46. hat you stop this installation now and contact the hardware vendor for software that has passed Windows Logo testing Continue Anyway STOP Installation Figure 2 6 Microsoft Windows XP Message Screen 7 Windows should now locate the correct drivers and complete the installation CIRRUS LOGIC 2 1 4 Running a Stereo PCM Application on CDB48500 USB To run a stereo PCM application follow these steps 1 Launch DSP composer Start Program Cirrus Logic DSP CS485XX DSP Composer In DSP Composer go to File Open and open the appropriate project Press the GO button qe GoM Insert PCM material into the DVD player e g music CD Ifa DVD is being used as the audio source make sure that the DVD Player or other digital audio source is configured to output PCM data 5 Press Play on the DVD player or other digital audio source You should now hear audio from the speakers 2 1 5 Downloading Other Applications Separate project files cpa are provided for other applications such as Dolby Pro Logic Il DTS Neo6 Audistry by Dolby SRS Circle Surround In order to evaluate these please contact your local FAE to ensure the necessary licensing agreements have been completed Please note that the CDB48500 USB does not support multi channel decoding such as Dolby Digital or DTS9 because the C8485XX DSP is only a post processor and does not contain a decoder 88 il A CIRRUS
47. his could damage the speakers 3 1 3 DC Power Input Voltage Range 9 12 Minimum Power 8W supply Connector Type 2mm Female positive center pin Reference Designator J25 3 1 4 Control Header Connector Type 2x25 0 100 inch Shrouded Male Reference Designator J11 This connector is the interface between the CDB48500 and the CDB USB MASTER Control signals clocks data and 3 3V power are passed across this connector 3 1 5 On Board Voltage Selection Headers Connector Type 1x3 0 100 inch Stake Header Reference Designator J17 J19 The CDB48500 USB is designed to operate from a single DC power input The 9V power supply provided with the kit is connected to the DC power input jack J25 and is regulated down to the system voltages 5V 3 3V 1 8V The power selection headers should be set to the REG position when using the DC wall supply This is the default mode of operation and should not need to be changed for most applications It is possible to bypass the regulated power supplies for any of the voltages by removing the jumper from the appropriate power selection header and connecting an external voltage supply to the center pin of that selection header The third configuration for the power selection headers is the EXT position This is a special mode of operation and cannot be used while connected to the CDB USB MASTER control board Placing the power selection headers in the EX
48. hts of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution ad vertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY AUTOMOTIVE SAFETY OR SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PUR POSE WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS
49. iagram shows the various system components A 1 1 1 2 DSP Input Data Multiplexing See Figure 1 2 CS48560 System Block diagram shows the data clock muxing schema Also notice that the multiplexer shown as ADC_SPDIFAHDMI_SEL J11 is inside the FPGA the USB Master Card A 1 1 1 3 Coyote DSP Core See Figure 1 3 The Coyote DSP core is driven by an external crystal circuit This fixed 24 576 MHz clock is buffered and driven out the XTAL_OUT of the CS485XX chip and can be used as the audio MCLK for analog sampling in the CS42448 CODEC The DSP has a dedicated reset line DSP_RESET that must be driven by the host to initialize the CS485XX s communication mode and initiate the first boot sequence This signal is independent of any other reset on the board and can be used to sequence device power up The host communication protocol of the DSP is determined by the state of the HS 4 0 pins at the rising edge of reset When 5 RESET is low the FPGA driver HS 4 0 pin to the communication mode set in Project properties dialog The lines are till reset goes High The serial host control 1 SCP1_MOSI SCP1 MISO SDA SCP1 CS SCP1 IRQ SCP1 BSY is used by the host controller to boot and control the DSP Note that the pull up resistors on the SCP1 and SCP1 BSY pins are required for both SPI and 12 control since these are open drain pins The pull ups on the SCP1 and SCP1_SDA pins are required only for 12C
50. il CIRRUS LOGIC CDB48500 High performance 32 Bit Audio Decoder DSP Family CDB48500 USB USB Evaluation Kit Guide Copyright Cirrus Logic Inc 2014 All Rights Reserved CIRRUS LOGIC http www cirrus co DS784DB2 FEB 14 CDB48500 ss CIRRUS LOGIC Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative To find the one nearest to you go to www cirrus com IMPORTANT NOTICE Preliminary product information describes products that are in production but for which full characterization data is not yet available Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for the use of this information including use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rig
51. l requests for performance specifications and testing rate schedule may be made to csli cense srslabs com SRS Labs Inc and Valence Technology Ltd reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND TECHNOLOGY must carry the Circle Surround logo on the front panel in a manner approved in writing by 585 Labs Inc or Valence Technology Ltd If the Circle Surround logo is printed in users manuals service manuals or advertisements it must appear in a form approved in writing by SRS Labs Inc or Valence Technology Ltd The rear panel of Circle Surround products users manuals service manuals and all advertising must all carry the legends as described in LICENSOR S most current version of the CIRCLE SURROUND Trademark Usage Manual Dolby Dolby Digital the double D symbol ProLogic and Audistry are registered trademarks of Dolby Laboratories Inc Supply of an implementation of Dolby technology does not convey a license nor imply a right under any patent or any other industrial or intellectual property right of Dolby Laboratories to use the implementation in any finished end user or ready to use final product It is hereby notified that a license for such use is required from Dolby Laboratories Intel is a registered trademark of Intel Corporatio
52. l signal is enabled The series resistor is small enough that it does not affect the signal in normal operation assuming a load of at least 10 kO is connected to the analog output of the board The 12 RCA jacks for analog outputs are also shown on this page CIRRUS LOGIC A 1 1 1 8 Codec 1 and Codec 2 Input Filters See Figure 1 8 Each input of the CS42448 has its own input filter that consists of a voltage divider an AC coupling capacitor 10 uF and a anti aliasing capacitor 2700 pF The voltage divider is provided to make the CDB48500 capable of accepting analog signals of up to 2 VRMS The CS42448 analog inputs register full scale for an input amplitude of 1 VRMS The 12 RCA jacks for analog inputs are also shown on this A 1 1 1 9 Output Filters amp Headphone Output See Figure 1 9 A headphone Amp is provided on the AOUT7 and AOUTS of the second CODEC The output of the headphone amp is connected to an 1 8 headphone output The headphone maps to DAO2 D1 on the DSP Refer to section Section 4 2 5 Headphone Output on page 4 8 for more details on the headphone output A 1 1 1 10 Mic and Pre Amp See Figure 1 10 The CDB48500 has a 1 8 microphone input jack to allow direct connection to an encapsulated condenser microphone ECM Because the output of the ECM is so small a pre amplifier is needed to boost the signal to a line level voltage These specifications for the amplifier are noted on the schematic pa
53. late R110 with a 0 ohm resistor There is also a jumper J105 to select Program or Normal Run operation of the SPI flash devices In program mode the CDB USB MASTER card will use the DSP_CS line to control the flash while holding the DSP in reset with the DSP_RST line For program mode jumper pins 2 and 3 on J105 In normal the DSP controls the SPI device In 120 mode no jumper change is required for program or normal mode of EEPROM For normal mode jumper pins 1 and 2 The feature to program flash from the CDB USB MASTER is not yet supported 3 1 11 Audio Clocking Clocking architecture is one of the most important aspects of a digital audio system The input and output clock domains of the DSP must be synchronous when delivering audio data in an isochronous fashion constant bitrate delivery even if the input output domains operate at different frequencies e g 48 kHz input 96 kHz output The CDB48500 can operate in three different clocking modes Each of these modes is explained in the following sections milli A CIRRUS LOGIC 3 1 11 1 Clock and Data Flow for up to 8 Channel ADC inputs MUXED DAI 3 0 MUXED DSP LRCLK1 MUXED DSP 5 1 1 8 8 th e g 8 8 58416 8 7 c 1 spoon p 6 2 w MUXED_MCLK 5 Use these jumper settin
54. ll process which should take less than one minute 7 Afterthe DSP evaluation software is installed the installer will launch the Front Panel Driver Setup Wizard below Click Next to continue the installation Opal Kelly FrontPanel Driver Setup m ES Welcome to the Opal Kelly FrontPanel Driver Setup Wizard This wizard will guide you through the installation of the FrontPanel Driver only package We suggest you uninstall any previous versions of FrontPanel and make sure that FrontPanel is not currently running It is also recommended that you close all other applications before continuing This will make it possible to update relevant system files without having to reboot your computer Click Next to continue Figure 2 1 CDB USB MASTER Driver Setup il A Ss CIRRUS LOGIC 8 The Opal Kelly Licensing Agreement window will appear next Click I Agree to agree to the terms and continue 9 The next window asks the user to choose components for installation By default only one component is available and is pre selected Unified USB Driver Click Next to continue 10 The wizard will then ask the user to choose the install location Select the default location of C Program Files Opal Kelly FrontPanel and click Install This should take only few seconds 11 Click Finish once the wizard has completed installation of the drivers 12 The Cirrus DSP evaluation software will then prompt th
55. n Motorola is a registered trademark and SPI is a trademark of Motorola Inc is a registered trademark of Philips Semiconductor Corp Microsoft Windows and Windows XP are registered trademarks of Microsoft Corporation ii CDB48500 USB Evaluation Kit Guide li CDB48500 Ss CIRRUS LOGIC Contents Contents See Oe ee ee ee te ot Beek he iii aM EUER V Chapter 1 Introduction to the CRD48500 USB Evaluation Kit 1 1 1 1 CDB48500 USB Kit Contents and Requirements 1 1 13121 CDB48500 USB Kit kiirii aneis na a E rat 1 1 1 1 2 PG Requirermehts 1 1 1 1 3 Software Requirements esses enne nenne 1 1 1 1 4 Support Hardware 1 1 1 1 5 Cabling ener nennen 1 1 1 2 Introducing the CDB48500 USB Customer Development 1 1 1 2 1 Identifying CDB48500 USB Components sse 1 2 1 2 2 Related nennen 1 4 1 2 2 1 Additional 48500 Evaluation Board 1 4 1 2 2 2 CS485xx Family DSP Hardware Information
56. operation The DSP has a debug port DBDA DBCK that allows a developer to debug the DSP during normal operation This is a slave port that can be connected to 12C master or it can be simply terminated with pull up resistors The audio input pins of the CS485XX are driven by a multiplexer U1 02 09 018 that chooses between 125 audio from an off board source CDB USB MASTER CARD audio on board S PDIF RX CS8416 and audio CODEC CS42448 as well as changing clock modes This multiplexer defaults to choose the on board audio sources The CDB USB MASTER CARD audio delivery interface is currently under development The input and output audio clocking domains are separated This allows the DSP to accept audio in one Fs and produce output samples at a different sample rate such as 2Fs 4Fs The 5485 is slave only on the input 1 ss CIRRUS LOGIC clock domain MUXED_SCLK MUXED LRCLK On the audio outputs the C8485XX is slave only for the MUXED MCLK master audio clock and master only for DSP_SCLK DSP LRCLK which are used to shift data out of the 5485 The USB MASTER USB board acts as the host controller in the CDB48500 platform and is connected to the CDB48500 via J11 on page 11 of the schematics The CDB USB MASTER drives several DSP interfaces including the serial host control port SCP1 the debug port and DSP RESET The optical jack for S PDIF output is listed on this page too The S PDIF out
57. plication on CDB48500 USB on page 1 5 check to see if the following condition exists S PDIF Source is not connected to SPDIF Connect the audio source to SPDIF or change the S PDIF input to the appropriate connector according to the instructions in Section 4 2 2 Changing the Audio Input Source on page 4 2 il ES CIRRUS LOGIC Revision History Revision Date Changes DB1 September 2006 Initial release DB2 February 2014 Added Windows 7 to list of PC requirements in Section 1 1 2 Updated project file name in Section 2 1 4 Added CS48560 CS485AU2B and CS485DV2B to list of chip IDs in Section 4 2 1 Added audio input sources to Section 4 2 2 Updated Fig 4 8 Updated description of SPP and APP module re mapping in Section 4 2 6
58. put line also goes to the serial data input of U5 Therefore when the S PDIF port is enabled noise will be heard on AOUT 4A and AOUT 4B A 1 1 1 4 Serial Flash Memory See Figure 1 4 The CDB48500 was designed with an Atmel 4 Mbit and SST 4 Mbit serial flash on board However only the SST Flash is connected to the DSP To connect the Atmel part remove R101 and add a 0 Ohm resistor to R110 In addition to serial flash a 512 Kb Serial I2C is also provided Information on programming these devices and booting from them can be found in the AN298MPMF A 1 1 1 5 S PDIF Receiver See Figure 1 5 The CS8416 is a S PDIF receiver capable of supporting sample rates up to 192 kHz The serial host control port SCL CCLK SDA CDOUT AD1 CDIN ADO CS shares clock and data lines with the CS485XX and 542448 The CS8416 CS line is unique to this chip and driven only when SPI mode The pull ups required for the SCL and SDA pins are shared with the other devices on the CDB48500 board The BRD RST signal is a shared reset signal The reference clock for the CS8416 is the XTAL OUT buffered 24 576 MHz crystal output from the CS485XX The CS8416 MCLK signal is the master audio clock for on board audio sources This clock can be either an MCLK recovered from a S PDIF stream or the XTAL_OUT reference depending on the setting of the CS8416 s internal multiplexer The CS8416 is master only for the CS8416 MCLK signal which is one possible source for MUXED
59. riven by a general purpose output of the CS8416 The CS42448 is a slave to the MUXED MCLK signal which is the master audio clock for the entire CDB48500 system The CS42448 masters the CS8416_SCLK and CS8416_LRCLK signals which are used to shift 125 data out of the CS42448 and shift 125 data into the CS485XX when ADC is used as the data input for the DSP The CS42448 slaves to the DSP_SCLK and DSP_LRCLK signals which are used to shift 125 data out of the CS485XX and shift 125 data into the CS42448 The analog inputs and outputs of the CS42448 are being used in single ended mode This is evident when looking at the input and output filter circuitry on page 6 of the schematics AIN5 of the CS42448 has an internal analog multiplexer that can be used to select between single ended inputs on the AIN5 and AIN5 pins This feature is used to share AIN5 between the microphone input and RCA jack 5 The transistor connected to MUTEC Q1 provides the current drive necessary to drive all of the mute transistors see page 9 of schematic into saturation The CDB USB MASTER drives the serial host control port signals on this page A 1 1 1 7 Codec 2 CS42448 See Figure 1 7 The CS42448 is multi channel ADC DAC that is capable of simultaneously supporting up to 6 channels of analog input and 8 channels analog output This is one of the two CODEC The serial host control port SCL CCLK SDA CDOUT AD1 CDIN ADO CS shares clock and data lin
60. s to the CDB48500 as follows A Connect one end of the digital audio S PDIF optical cable to SPDIF on the CDB48500 board CIRRUS LOGIC B Connect the other end of the optical cable to the optical output on the back of a DVD player or other digital audio source 5 Setup Audio Output connections from CDB48500 as follows A The RCA connectors labeled AOUT 1A and AOUT 1B are the left and right analog output channels B Use the RCA audio cables to connect these line level analog outputs to powered speakers 2 1 3 Connecting to a PC Follow these steps to connect to a PC 1 Connect the end of the USB cable to P1 on the USB MASTER USB Digital I O Card 2 Connect the A end of the USB Cable to a USB 2 0 port on a notebook or PC running Win XP 3 Windows should recognize that a new device has been attached and display a notice saying Found New Hardware 1 Found New Hardware Opal Kelly XEM3001v2 Figure 2 3 Found New Hardware Service Window 4 Windows will display the Found New Hardware Wizard below Select the No not at this time radio button so that Windows does not connect to Windows Update for the drivers Click Next Found New Hardware Wizard Welcome to the Found New Hardware Wizard Windows will search for current and updated software by looking on your computer on the hardware installation CD or on the Windows Update Web site with your permission Read our priva
61. t multiplexer The two S PDIF input jacks RXP RXN are connected to the CS8416 Only one of the optical or coaxial S PDIF jacks can be used at a and is automatically selected by the CS8416 When S PDIF audio is being processed the CS8416 must master MCLK for the system see Audio Clocking on page 1 5 for details 3 1 9 CS42448 Audio CODEC The CS42448 U4 and 05 is a high performance multi channel audio CODEC capable of supporting sample rates up to 192 kHz on its 6ADCs and 8 DACs There are two of these devices on the CDB48500 and are used for all analog to digital and digital to analog conversions All analog inputs AIN_1A AIN_6B and all analog outputs AOUT_1A AOUT_6B are connected to the CS42448s The microphone input shares the AIN1_5 ADC with the AIN_3A RCA jack When the microphone is in use the AIN_3A RCA jack is ignored When analog audio is being processed the 24 576 MHz crystal for the CS485XX must master MCLK for the system see Section 3 1 11 for details 3 1 10 Memory The CDB48500 is populated with two 4 Mbit SPI flash devices and one 12C EEPROM Selection from SPI to 12C is changed in Software There are 2 SPI flash footprints U11 U13 on the board for compatibility with both standard 8 pin serial flash pinouts The serial control lines are shared by both footprints and a chip select 0 ohm jumper resistor R101 is populated to make U13 the active device To make U11 the active device remove R101 and popu
62. where 1FS 32 kHz 44 1 kHz or 48 kHz 2Fs 64 kHz 88 2 kHz 96 kHz etc Select CODEC DAC as SCLK and LRCLK Master device S PDIF Enable Checking this box configures DAOS for S PDIF instead of 125 4 2 4 Changing Serial Control Protocol I2C or SPI The CDB48500 is designed to communicate using either 12 or SPI protocols In order to change the communication mode in DSP Composer go to the menu bar and select File gt Properties which brings up the Project Properties dialog shown in Fig 4 8 The Board Comm Mode pull down menu allows the user to select the serial protocol mode The Advanced button of the Project Properties dialog is currently not active mali EE CIRRUS LOGIC User Revision ID 8 4 hex User Build ID 8 bit hex Codebase Sample Rate KHz 48 gt 10 Board boot mode comm mode Siave SPI Multiword commands in snapshot cfg files 7 Use JP 1 customer board control header JP1 board type gt Figure 4 8 CDB48500 Comm Mode CIRRUS LOGIC 4 2 5 Headphone Output The CDB48500 is designed with one Stereo Headphone output The content of the Headphone output is controlled by the Remap tab in the System Block module The left right headphone channels match the setttings for DAO DATA1 Left and Right controls on the Remap tab as shown in Fig 4 9 Syst
63. y the PLL on the USB Master card The PLD on the USB Master Card generates SCLK and LRCLK for the DAI side of the DSP from the MCLK On the output side the CS485xx slaves to MCLK from the USB Master Card and masters SCLK and LRCLK for the DAC side of the CS42448 The CS485XX always masters its output clocks DSP_SCLK DSP_LRCLKk 88 il A CIRRUS LOGIC Chapter 4 Configuring the CDB48500 4 1 Introduction The DSP Composer software is a graphical user interface GUI that is used to program the CS485XX DSP and to configure the CDB48500 With the exception of the power selection and DAI input jumpers the CDB48500 is configured exclusively through software This section provides basic instruction for using the GUI to control the CDB48500 but detailed information can be found in the DSP Composer User s Manual Both the DSP Composer software and the User s Manual for the software package will be provided by your local Cirrus Logic representative 4 2 Basic Application Download and System Configuration for PCM Pass through Follow the instructions in Chapter 1 Board Setup and Installing the Evaluation Kit Software in order to install the USB drivers on your PC and launch DSP Composer the GUI used to control the CDB48500 After following the instructions in Section 2 1 4 Running a Stereo PCM Application on CDB48500 USB on page 1 5 the DSP Composer main window will appear as shown in Fig 4 1 Fig
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