RX family PTP Synchronous Pulse Output Using Firmware
Contents
1. define MODE PORT Default value 0 Specify the kind of clock When this is set to 0 clock is OC por When this is set to 1 clock is OC port BC and TC are not supported in this sample define MS PORTO 1 Default value 0 Select Master or Slave for port0 port1 When this is set to 0 clock is Master When this is set to 1 clock is Slave define SYNC_PORTO 1 Default value 1 Select the delay mechanism P2P or E2E for port0 port1 When this is set to 0 the delay mechanism is P2P When this is set to 1 the delay mechanism is E2E define PLS CHO 1 Default value 0 1st pulse Default value 1 2nd pulse Select the channel of pulse output timer for Ist pulse 2nd pulse Set 0 to 5 Please set the different channel between Ist pulse and 2nd pulse each other define PLS CYCO 1 Default value 400000 1st pulse Default value 100000 2nd pulse Set the pulse period for 1st 2nd pulse in the nanosecond unit Half of this value is set to the pulse setting function R_PTP_Tmr_Set of the PTP driver and the registers TMCYCRm of the EPTPC Please keep in mind the resolution of the pulse period is 50nsec due to STCA clock one In detail please refer to RX64M 71M Group User s manual Sec 36 2 27 define PLS HWO 1 Default value 200000 1st pulse Default value 50000 2nd pulse Set the pulse high width for 1st 2nd pulse in the nanosecond unit Ha2. 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test for the given product Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples Y
3. REN ESAS APPLICATION NOTE R01AN2846EJ0100 RX Family Rev 1 00 July 24 2015 PTP Synchronous Pulse Output Using Firmware Integration Technology Modules Introduction This document explains one of the PTP Firmware Integration Technology module usage examples This example outputs the pulses synchronous with the PTP Precision Time Protocol defined by the IEEE1588 2008 specification 1 Target Device This example supports the following device RX64M Group RX71M Group When using this application note with other Renesas MCUs careful evaluation is recommended after making modifications to comply with the alternate MCU RO1AN2846EJ0100 Rev 1 00 Page 1 of 17 July 24 2015 RENESAS RX Family July 24 2015 PTP Synchronous Pulse Output Contents TT 3 1 1 PIP Synchronous Pulse Output Using FIT Modules 3 12 gt Related documents 2ciiv cccciisis coc cavecsinss a i a senewiea tedden EEES 3 Lei Terms and ADbreviations sivessscdccasacindsvateccarssanitdssaacvanesaasdtesabuvatndnandQinsabevdavbnasdtesvabucatvtaandtdnabeenes 3 E We Ee DEE le 5 er 5 VG Te 6 2 FUNCHONAl INTOFMATLON EEN 7 2 1 Hardware Requirement ss cv c ccees caves ENEE ENEE REENEN See 7 2 2 Hardware Resource Requirement cccccscceceesecceeeeseeceeeeneneeeeeseeeeeeeanaeseeseeeeseeneeaeseeneeeeeeenaaes 7 2 3 Software Requirements 0 ccccccceeceeeeeceeeee cee eeeeaeeeeeeeceaeeesaaeeeeaeeseeeeseaeeesaaeeseeeeseeeeesaeeseeeeeeeeess
4. please refer to the documentation of the each FIT module demo_src main operation and configuration r_elc_rx ELC driver folder sample_main c r_elc_rx_if h ELC driver header file sample_main h STC usr LED control r_elc c ELC driver source file led c led h r_ether_rx Ethernet Driver FIT module sync PTP synchronize operation r_io_rx I O ports driver folder sync c r_io_rx_if h l O ports driver header file sync h SIC r_bsp BSP Board Support Package FIT module r_io c I O ports driver source file r_config configuration setting of FIT modules r_ptp_rx PTP Driver FIT module r_bsp_config h r_bsp_interrupt_config h r_ether_rx_config h r_ptp_rx_config h Figure 1 3 File structure of this example R01AN2846EJ0100 Rev 1 00 Page 6 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output 2 Functional Information This example is developed by the following principles 2 1 Hardware Requirements This driver requires your MCU supports the following feature e EPTPC e PTPEDMAC e ETHERC e EDMAC e ELC e UO Ports 2 2 Hardware Resource Requirements This section details the hardware peripherals that this driver requires Unless explicitly stated these resources must be reserved for the driver and the user cannot use them 2 2 1 ETHERC Channel The example uses the ETHEC CHO or ETHEC CH1 Those resources need
5. Figure 3 7 Jumper setting User need to connect the pulse output pin of the RX64M 71M RSK board to the oscilloscope pin Figure 3 8 indicates the board pins output the pulse Application header_ Pin Header name p29 JA3 E 30 D E Figure 3 8 output pulse observing pins R01AN2846EJ0100 Rev 1 00 Page 14 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output 3 4 Operation Example The operation example applied to two board configuration showed as Figure 3 1 describes following as the typical one 3 4 1 Condition Topology Using one RX71M RSK board Master and one RX64M RSK boards Slave Protocol OC port0 and E2E Synchronous mode The gradient correction which is the functionality of STCA unit was applied mode2 PTP commands interval PTP commands interval was 1sec The intervals of Sync and Delay_Req message were Isec Pulse output timer setting Using channel CHO for Ist pulse PEO CH1 for 2nd pulse PE1 Start time 30 123 456 789 nsec TMSTTRUm 0x00000007 TMSTTRLm 0x037F7915 Pulse specifications Ist pulse PEO 400usec period 200psec width Duty 50 2nd pulse PE1 100usec period 5Ousec width Duty 50 3 4 2 Mechanism The pulse output timer creates the pulse synchronized with PTP continuously connecting timer events to the toggle output of I O ports The period and width of the output pulse are enhanced two times compare to the pulse output ti
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7. The lower 24 bits of default value are set the unique value for this Case of device id 1 sample Default value 0x5000791F port0 Please change this value when users applied to this sample their Default value 0x50007920 port1 system Case of device id 2 Default value 0x50007921 port0 Default value 0x50007922 port1 define IP_ADDR_1 2 Case of device id 0 Default value 0x06070809 port0 Default value 0x16171819 port1 Case of device id 1 Default value 0x26272829 port0 Default value 0x36373839 port1 Case of device id 2 Default value 0x46474849 port0 Default value 0x56575859 port1 Set the IP IPv4 address for portO port1 Please change this value when users applied to this sample their system Set the pulse start time in the nanosecond unit The default value equals to 30 123 456 789 nsec define PULSE_START_H L PULSE_START_H and PULSE_START_L are higher 32bits and Default value 0x00000007 High lower 32bits respectively Default value 0x037F7915 Low This setting is common to 1st and 2nd pulses Please keep in mind those setting value should be after local clock counter initial value 2 8 API Data Structures No specific data structure exists in this sample 2 9 Return Values This section describes return values of the functions of this example Those return values are located in r_elc_rx_if h and r_io_rx_if h as th
8. communication network In general the communication network is specified the Ethernet There are two versions which are IEEE1588 2002 version and IEEE1588 2008 version2 they do not have complete compatibilities each other This document only attributes the IEEE1588 2008 version2 PTP Precision Time Protocol PTP means time synchronize protocol based on the IEEE1588 PTP message The data format which is used in the PTP sequence PTP messages are transmitted in the Ethernet frame Layer2 or UDP packet Layer3 Clock Node Device whose functionality is time synchronization based on the IEEE1588 SG Local clock Synchronize time of the each clock Master Master means the Clock issues the system standard time to other clocks RO1AN2846EJ0100 Rev 1 00 Page 3 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output Slave Slave means the Clock receives and corrects the system standard time to other clocks OC Ordinary Clock OC means the Clock has only one port and one local clock BC Boundary Clock BC means the Clock has more than two ports and common unique local clock Each port has time synchronize function TC Transparent Clock TC means the Clock has more than two ports and corrects the frame propagation delay between ingress and egress ports E2E End to End Synchronize mode in which between a master and multiple Slaves or a Slave P2P Peer to Peer Synchroniz
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10. 7 2 4 Supported TOGIGNAINS kiesto anan aeaa ergeet ege aaa 7 2 5 HO AdS r Files sctssenceccecseccehaandscnadivedctuaundeteneseduidunaddcheduvedcdduagadcceenyedandutehdaewes ia eaaa aaaea 7 2 6 Integer Type isciit cacs ait acatis dali cee denied aati inde antes aided snes baits E EA 8 2 7 Configuration Overnlew cee eeeaaeeeeneecaeeecaaeeeeaee scenes caaeeseaaesgeeeeseeeeeaesseaeeeseeeess 8 28 API Data StruGtures sssrinin dedentessasetuataccsteveadetsad aezanieaeatettadancindeveaietiasdersuieaeauetaavencins 9 Sch Return Valie S aniona aaa a a AE E a aa geed eege AAEE 9 3 Specification of This EXample sirsernsssisesisaesisaieiindn anana aai aaa aiaa a aAa 10 31 Outline gf uer EE 10 3 2 Environment and execution ccccccccceeeeeeeeeceaeeeeeeeeeeeeaaeaeceeeeeseceaaaeseeeeeeesecaeaeceeeeeeeseeseaeeeeess 11 3 3 Board Setting ME 14 3 4 Operation Example sisia ia a aai e aeaa ae aaa Rae Ca EAEEEEEereE 15 A Reference Documents 17 RO1AN2846EJ0100 Rev 1 00 Page 2 of 17 RENESAS RX Family PTP Synchronous Pulse Output 1 Overview This document explains one of the typical usage examples of the PTP driver based on the firmware integration technology FIT This example outputs the two positive and negative PWM Pulse Width Modulation pulses with duty 50 The pulse output nodes are synchronous with the PTP and start the creation of pulses when the time of each nodes coincidence with the specified time set by user Thereafter those no
11. EO 200 5 6 400usec Duty 50 i 400usec period 50usec pulse width 25usec Timer start time coincidents with TMCYCR1 50 000 TMPLSR1 25 000 local clock based on the vous SE gt lt gt LCCVR and TMSTTR j a i Eoi a a i iit vU WU Start fall edge Invert Invert Invert Invert Invert Invert Invert Invert Invert Inveft Low to High eit 50sec eem Ken Eieren i fi d d d i i E Ay WI Pulse output timer 2nd pulse PEO emm Ki 100usec Duty 50 lt 100psec gt Figure 3 10 Synchronous pulse creation Fall edge 3 4 3 Output Pulse Figure 3 11 shows the output pulses in the Sec 3 4 1 conditions when the event signal trigger is rise edge and this time scale is 50sec per unit coordinate The blue line and red line indicate the 2nd pulse and Ist pulse outputted from RX64M RSK board Slave respectively The yellow line and green line indicate the 2nd pulse and Ist pulse outputted from RX71M RSK board Master respectively Please keep your mind those result are depend on the measurement condition and environment Pulses from RX64M RSK board Slave Blue CH3 2nd pulse PE1 Red CH4 1st pulse PEO 50usec Pulses from RX71M RSK board Master Yellow CH1 2nd pulse PE 1 Green CH2 ist pulse PEO i We Figure 3 11 Output pulse example Rise edge 50usec scale unit RO1AN2846EJ0100 Rev 1 00 Page 16 of 17 July 24 2015 RENESAS RX Family PTP Synchrono
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13. SK board 1 RSK board 2 Figure 3 1 Environment two board configuration RO1AN2846EJ0100 Rev 1 00 Page 11 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output Figure 3 2 Figure 3 3 Figure 3 4 and Figure 3 5 show the software flow overview Figure 3 2 describes the initial setting of related peripheral modules such as ETERC EDMAC EPTPC ELC I O Ports and so on Figure 3 3 describes the operation to enable Ether communication including PTP message frame Figure 3 4 describes the operation executed after PTP message receive interrupt occurrence Figure 3 5 describes the operation executed after timer event interrupt occurrence 1 Set PTP configuration structure Set kind of clock delay mechanism E2E or P2P port Master or Slave MAC Address IP address etc 2 Initialize and open Ether driver Initialize ETHERC and EDMAC 3 Initialize I O Ports Set PEO and PE1 to general purpose output 4 Set EPTPC timer event to ELC Connect EPTPC timer event to I O port PEO PE1 toggle output and enable ELC 5 User LED all on pattern LEDO ON LED1 ON LED2 ON LED3 ON 6 SW1 pushed 7 Initialize and open PTP driver Initialize EPTPC and PTP EDMAC 8 Set EPTPC configuration Set EPTPC depends on the PTP configuration structure 9 Set interrupt from ELC Set interrupt indication timer channel edge rise or fall and not auto clear 10 Set and enable timer events Set timer start time pulse period and pul
14. dentity 5 Master changed 6 Update current master port identity Execute R_PTP_SetMPortID function of PTP driver Figure 3 4 3 PTP message receive interrupt z Timer event Interrupt from EPTPC Compare local clock LCCVR to timer start time TMSTTF Time coincidence via ELC Start pulse output From PEO From PE1 1 i 1 1 1 1 1 1 1 1 H 1 1 1 1 SULT SUPA 3 Registered timer event handler 4 Registered CPU_Timer_Ope timer function channel 5 Clear MINT interrupt Set MIEIPR mask if I 6 Disable timer interrupt 7 Clear MINT interrupt a Interrupt from STCA SYNO SYN1 or PRC TC operations Figure 3 5 4 Timer event interrupt RO1AN2846EJ0100 Rev 1 00 Page 13 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output 3 3 Board Setting There are two jumpers setting of the RX64M 71M RSK board depending on the PHY access channel of the configuration option When the product name of the RX64M 71M RSK board is ROK50564MC001BR or ROKSRX71MCO10BR Figure 3 6 indicates their changing And when the product name of the RX71M RSK board is ROK50571MCOOOBR Figure 3 7 indicates their changing depending UNK CH 1 Default setting LINK_CH 0 L 1 ETHERG ETOMDIO or ETiMDIO L 1 ETHERCETOMDC or ET1MDC Figure 3 6 Jumper setting LINK_CH 1 Default setting LINK_CH 0 O n ETHERC ETOMDIO or ETIMDIO ETHER ETOMDC or ETIMDC
15. des continue to output the pulses to the general ports I O Ports via Event Link Controller ELC without CPU operation The period and width of the pulse outputted from each node are corrected based on the synchronous time Users can apply those PWM pulse to their own systems 1 1 PTP Synchronous Pulse Output Using FIT Modules This module is implemented in a project and used as the application example of the PTP Driver FIT Module 1 2 Related documents 1 IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Revision of IEEE Std 1588 2008 Mar 2008 2 RX Family EPTPC Module Using Firmware Integration Technology Rev 1 02 Document No RO1AN1943EJ0102 Dec 31 2014 3 RX Family PTP Timer Synchronous Start Using Firmware Integration Technology Modules Rev 1 02 Document No ROLAN1984EJO102 Dec 31 2014 4 RX Family Ethernet Module Using Firmware Integration Technology Rev 1 02 Document No ROLAN2009EJ0O102 Mar 27 2015 5 RX Family TCP IP for Embedded system M3S T4 Tiny Module Firmware Integration Technology Rev 2 02 Document No R20AN0051EJ0202 Jan 05 2015 6 RX64M Group Renesas Starter Kit User s Manual For CubeSuite Rev 1 00 Document No R20UT2590EG0100 Jun 20 2014 7 RX71M Group Renesas Starter Kit User s Manual Rev 1 00 Document No R20UT3217EG0100 Jan 23 2015 1 3 Terms and Abbreviations e IEEE1588 Specification makes the time synchronization in a
16. e mode in which between the specific two clocks STCA Statistical Time Correction Algorithm Correct offsetFromMaster applied to statistical method to which estimates the tendencies of clock time deviation from the gradient calculated using sampled clock values with worst 10 filter BMC Best Master Clock algorithm BMC algorithm determines the suitable master in the domain and composes of the data set comparison algorithm and the state decision one Data set comparison algorithm decides which port is better as master comparing the feature of each clock State decision algorithm decides the next state of the port as the result of the data set comparison algorithm Time difference between time on the Master and time on the Slave refer to 1 One port of the clock If clock has only one port port equals to clock RO1AN2846EJ0100 Rev 1 00 Page 4 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output 1 4 Hardware Structure The Ethernet peripheral modules of the RX64M 71M group are composed of the EPTPC the PTP Host interface peripheral module PTPEDMAC dual channel Ethernet MAC ones ETHERC CH0 ETHERC CH1 and dual channel Ethernet Host interface ones EDMAC CH0 EDMAC CH1 The EPTPC is divided to PTP Frame Operation CHO part PTP Frame Operation CH1 part Packet Relation Control part and Statistical Time Correction Algorithm part from their functionality EPTPC is also connected to the ge
17. e prototype declarations BEE EE MLC OK 0 No erion EC BINROR General exwor I O Ports driver return value TO OK 0 No erros IO ERROR 1 General error R01AN2846EJ0100 Rev 1 00 Page 9 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output 3 Specification of This Example 3 1 Outline of Functions The function of this example shows Table 3 1 Table 3 1 Function of This Example Item Contents main Main operation of the typical usage example of this sample ReadPTPMsg Read PTP messages If announce message is received update Master port identity led_init Initialize and open user LED led_ctrl Update data to show user LED R_ELC_Init Initialize ELC start ELC R_ELC_Set_Timer_Event Connect EPTPC timer event to IO port PEO PE1 toggle output event R_ELC_Ctr_Timer_Event Enable disable EPTPC timer event H IO oni Initialize IO port PEO PE1 RO1AN2846EJ0100 Rev 1 00 Page 10 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output 3 2 Environment and execution This example needs the Renesas Starter Kit for RX64M hereafter RX64M RSK board 6 or the Renesas Starter Kit for RX71M hereafter RX71M RSK board 7 more than two Master node and Slave node Ethernet Hub hereafter HUB and the Oscilloscope The synchronous pulse output pin of the each RX64M 71M RSK boards connects the in
18. given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed
19. lf of this value is set to the pulse setting function R_PTP_Tmr_Set of the PTP driver and the registers TMPLSRm of the EPTPC Please keep in mind the resolution of the pulse high width is 50nsec due to STCA clock one define TIMER_EDGE Default value 0 Select the rise or fall edge of ELC event signal trigger When this is set to 0 rising edge is selected When this is set to 1 falling edge is selected This setting is common to Ist and 2nd pulses define LINK_CH Default value 0 Specify the Ethernet link channel When this is set to 0 Ethernet CHO is selected When this is set to 1 Ethernet CH1 is selected define MAC _ADDR_1H 2H Default value 0x00007490 Set the Ethernet MAC address upper 16 bits for port0 port1 The lower 16 bits of default value are set the upper 16bits of the Renesas vendor ID 74 90 50 The upper 16 bits of default value are reserved field and should be set 00 00 Please change this value when users applied to this sample their system define MAC _ADDR_1H 2H Case of device id 0 Set the Ethernet MAC address lower 32 bits for portO port1 The upper 8 bits of default value are set the lower 8bits of the RO1AN2846EJ0100 Rev 1 00 July 24 2015 Page 8 of 17 RENESAS RX Family PTP Synchronous Pulse Output Configuration options Default value 0x5000791D port0 Renesas vendor ID 74 90 50 Default value 0x5000791E port1
20. mer original ones Figure 3 9 and Figure 3 10 show the creation mechanism when the event signal trigger is rise and fall edge respectively in this operation example period 200usec pulse width 100s ec Timer start time coincidents 1585 TMCYCRO 200 000 SE Kal 100 000 local clock based on the IEEE1588 LCCVR and TMSTTR Pulse output timer edge High to Low Low to High 1st pulse PEO OU l Dee cl I lt 200p sec 400usec Duty 50 lt 400usec 1 1 b 1 1 1 b 1 1 Start rise Invert rise edge Invert rise edge i i i i 1 1 i 1 1 period 50usec pulse width 25usec Timer start time coincidents with TMCYCR1 50 000 TMPLSR1 25 000 local clock based on the IEEE1588 K gt KS LCCVR and TMSTTR D Co pe D eg D ee ee a D ka aen Start rise Invert Invert Invert Invert Invert Invert Invert Invert Invert Invert edge 2nd pulse PEO Jest 100usec Duty 50 lt 100psec gt i i i Figure 3 9 Synchronous pulse creation Rise edge R01AN2846EJ0100 Rev 1 00 Page 15 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output period 200usec pulse width 100us ec i i 1 D TMCYCRO 200 000 TMPLSRO lt 100 000 1 gt K gt ia Timer start time coincidents with local clock based on the vous LCCVR and TMSTTR Pulse output timer Start fall Invert fall edge Invert fall edge edge High to Low Low to High Ist pulse P
21. neral ports I O ports and motor control timers MTU3 and GPT peripheral modules via ELC peripheral module to output synchronous pulses Figure 1 1 shows the related hardware s block diagram and the green arrows and parts indicate the connection and using parts respectively in this example In detail please refer to RX Family EPTPC Module using Firmware Integration Technology 2 IT Synchronous parts E Using parts in this example 4 A EDMAC CHO Outputs T SE BI 6CH a A 4 Correction PTP Frame PTP Frame ERIS Operation CHO Operation CH1 Local Time Counter ETHERC CHO ETHERC CH1 MII RMII 4 D MII RMII 4 D Figure 1 1 Hardware block diagram 1 5 Software Structure This sample is operations example of the application layer Those operations are to set a PTP configuration such as MAC address IP address the kind of Clock Master or Slave and delay mechanism P2P or E2E to the PTP driver set the pulses parameter such as the specific pulse output start time period and width to the PTP driver set an event link connection between EPTPC and I O ports to the ELC driver set I O ports initial setting to the I O ports driver and control the PTP protocol sequences using the PTP and Ether driver The PTP driver always should be used with Ether drivers 4 TCP IP middle ware does not include in this e
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23. put of the oscilloscope The outline of the execution sequence is following Connect more than two RX64M 71M RSK boards to Hub using Ethernet cables Connect the synchronous pulse output pins of each RSK board to oscilloscope Power on the RX64M 71M RSK board including other devices When the RX64M 71M RSK board finishes Ethernet I O ports and ELC driver initialization and open process the user LED composed of LEDO LED1 LED2 and LED3 shows the all on pattern LEDO ON LED1 ON LED2 ON LED3 ON Push the SW1 switch Each clock RX64M 71M RSK board initializes and open PTP driver with setting the output pulses feature such as start time period and width When each clock starts the synchronization without any error the user LED shows the even pattern LEDO ON LED1 OFF LED2 ON LED3 OFF Fach clock outputs the pulses from I O ports PEO and PE1 via ELC when the local clock counter synchronized of the EPTPC compares matches the timer start time whose field is composed of higher and lower 32 bits of nanosecond order field TMSTTRUm and TMSTTRLm User can observe the synchronous pulses If any error occurred during this operation this example finishes with the odd pattern LEDO OFF LED1 ON LED2 OFF LED3 ON of the user LED 662 The index m indicates pulse output timer channel from 0 to 5 Figure 3 1 shows the environment using two board configuration Oscilloscope RX64M 71M RX64M 71M R
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26. se width and enable timer events 11 Register timer events handler Register PTP driver equipped function CPU_Timer_Ope as the interrupt handler 12 Register PTP message read function Register sample function ReadPTPMsg Complete driver and HW initial setting Figure 3 2 1 Initial setting of related HW 1 Enable PTP Host interface to transfer PTP message Set PTP EDMAC descriptors FIFO configuration software flag etc Set ETHERC promiscuous mode to enable PTP operation 3 Enable EDMAC Host interface to transfer standard Ethernet frame Set EDMAC descriptors FIFO configuration software flag etc 4 Start synchronization Slave and master start the synchronization using the PTP messages 5 User LED even pattern LEDO ON LED1 OFF LED2 ON LED3 OFF Wait interrupt 6 Infinite Timer event from EPTPC loop PTP message receiving event from PTP EDMAC Slave only Figure 3 3 2 Enable Ether communication RO1AN2846EJ0100 Rev 1 00 Page 12 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output PTP message receiving event interrupt from PTP EDMAC 1 Read PTP message by one frame Execute R_PTPIF_Read function of PTP driver Check Ether frame type field is OxB or not 2 Announce message Clock ID high clock ID low and port number fields 4 Get current master port identity Execute R_PTP_GetMPortID function of PTP driver Compare sourcePortldentity and current master port i
27. to the Ethernet MAC operations 2 2 2 EDMAC Channel The example uses the EDMAC CH0 or EDMAC CH1 Those resources need to the CPU Host interface of standard Ethernet frame operations 2 2 3 ELC The example uses the ELC to connect events between EPTPC and I O ports This resource needs to output the pulses synchronously 2 2 4 I O Ports The example uses the I O ports for the synchronous PWM output Please do not modify the settings or try to use the peripheral during driver operations 2 3 Software Requirements This example is dependent upon the following packages e r bsp e r ptp rx e r ether_rx e r elc_rx e riorx 2 4 Supported Toolchains This example is tested and works with the following toolchain e Renesas RX Toolchain v2 01 00 2 5 Header Files Each functions call are accessed by including a single file sample_main h sync h led h r_elc_rx_if h r_io_rx_if h which is supplied with this driver s project code RO1AN2846EJ0100 Rev 1 00 Page 7 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output 2 6 Integer Types This project uses ANSI C99 These types are defined in stdint h 2 7 Configuration Overview The configuration options in this example are specified in sample_main h The option names and setting values are listed in the table below Configuration options define DEVICE_ID Default value 0 Set the device id number of the demo
28. us Pulse Output 4 Reference Documents User s Manual Hardware RX64M Group User s Manual Hardware Rev 1 00 RO1UH0377EJ RX71M Group User s Manual Hardware Rev 1 00 RO1UH0493EJ The latest version can be downloaded from the Renesas Electronics website User s Manual Software RX Family RXv2 Instruction Set Architecture User s Manual Hardware Rev 1 00 RO1US0071EJ The latest version can be downloaded from the Renesas Electronics website Technical Update Technical News The latest information can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics website http www renesas com Inquiries http www renesas com contact RO1AN2846EJ0100 Rev 1 00 Page 17 of 17 July 24 2015 RENESAS RX Family Application Note REVISION HISTORY PTP Synchronous Pulse Output Using Firmware Integration Technology Modules Description Summary Date Jul 24 2015 First edition issued All trademarks and registered trademarks are the property of their respective owners General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accordance with the directions
29. xample Therefore user needs to implement TCP IP middle ware ex M3S T4 Tiny the RX Family 5 when this example applied to the TCP IP system Figure 1 2 shows the software structure of this sample This example supports only OC not support BC and TC RO1AN2846EJ0100 Rev 1 00 Page 5 of 17 July 24 2015 RENESAS RX Family PTP Synchronous Pulse Output This Sample PTP Synchronous Pulse Output Using FIT Modules PTP configuration MAC address IP address Master slave P2P E2E PWM pulses parameter start time period width ELC connection UO ports initial setting PTP protocol sequence ctrl Application TCP IP Not use PTP UDP IP Not use Ether Driver CHO Ether Driver CH1 PTP Driver ELC Driver UO ports Driver Event link set Port initial Connect EPTPC settin Driver event to I O port toggle output JUUUUUL ZC EDMAC CH1 Zeen VO ports gt JUUN mut 4 A D 4 D i Hardware EPTPC M D D ETHERC CHO ETHERC CH1 4 MII RMII 4 Ak MII RMII PWM pulses Figure 1 2 Software structure of this sample 1 6 File Structure This sample codes are stored in the demo_src and lower hierarchical folders ELC and I O ports drivers are stored each driver folders respectively Figure 1 3 shows the file structure of this sample As for other FIT based modules include the PTP driver FIT module
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