^2 Accessory 68E
Contents
1. 24 inputs and 24 outputs low power all optically isolated 12 24 inputs and 24 outputs high power all optically isolated 14 48 bits TTL level VO ACC 65E Sourcing 24 inputs 24 outputs self protecting all optically isolated 250mA outputs ACC 66E 48 optically isolated self protecting sourcing inputs ACC 67E 48 optically isolated self protecting sourcing outputs 250mA outputs ACC 68E Sinking 24 inputs and 24 outputs self protecting all optically isolated The inputs to the ACC 68E board have an activation range from 12V to 24V Due to the self protecting circuitry the inputs can only be configured as sinking inputs Although self protecting there are still limits to power supplied to the inputs of the ACC 68E The limiting voltages are Vr 57 volts input to the VO and the V 33 volts input to the I O These limitations are due to the protective circuitry including the MMBZ33VALT 1 Zener diodes The output drivers are organized in a set of three 8 bit groups The output chip used for the sinking configuration is the ULN2803 Each open collector output line can sink up to 100mA when pulled up to a voltage level between 12 and 24 volts external pull up resistors are not supplied Introduction 1 Accessory 68E HARDWARE SETUP The ACC 68E uses expansion port memory locations defined by the type of PMAC 3U Turbo or MACRO Station it is dire2. dbe Ge 33 DB15 STYLE CONNECTOR J1 TOP INPUTS 1 THROUGH 12 33 Table of Contents i Accessory 68E JL Top Connector MEER 33 DB15 STYLE CONNECTOR J2 TOP INPUTS 12 THROUGH 24 ese se ee ee ee es ee 000000000000 34 J2 GORROC OF RE eet aid ed ese ses 34 DB15 STYLE CONNECTOR J1 BOTTOM OUTPUTS 1 THROUGH 12 35 JI Bottom OOE O 35 DB15 STYLE CONNECTOR 12 BOTTOM OUTPUTS 12 THROUGH 24 ee ees ese 35 J2 Bottom 222 22 20 7 000000000 ee ee ee ee S er e eer 35 ii Table of Contents Accessory 68E INTRODUCTION The UMAC Accessory 68E is a general purpose input output board to the UMAC Turbo or UMAC MACRO systems Both the inputs and outputs of this board are to be configure as Sinking signals ONLY ACC 68E provides 24 lines of self protected optically isolated inputs and 24 lines of self protected optically isolated outputs The actual I O Reads are carried out using M variables which will be described later ACC 68E is one of the series of 3U rack I O accessories designed to transfer data through the UMAC BUS UBUS Other boards in the family of the UMAC I O Accessory products include the following ACC 9E 48 optically isolated inputs 10 48 optically isolated outputs low power
3. 1 gt 0 198 5409807 10 Disable PLC10 Close 26 countdown countdown timer for Turbo Ultralite timer for Ultralite countdown timer for non turbo PMAC 2 second delay to ensure MACRO Stal set control wril word for ACC 68 te 07 into 58807 50 msec delay set control write 5 into 59807 word for ACC 66E 750 msec delay tion is powered up properly GI control word control word Setting Up Control Word for MACRO IO Accessory 68E LEGACY MACRO SYSTEMS The legacy systems are defined as MACRO CPU with the following part numbers 602804 100 602804 101 602804 102 602804 103 602804 104 These systems do not have the extended addressing of the newer model MACRO CPU s 602804 105 through 602804 109 The addressing scheme for the legacy MACRO systems is listed below The ACC 9E ACC 10E ACC 11E and ACC 12E will have the following table E1 E4 Gate Transfer Jumpers TENE 8800 or SFFEO 8840 or SFFE8 8880 or SFFFO The ACC 68E ACC 66E and ACC 67E are not direct replacements for ACC 9E ACC 10E and ACC 11E IO cards The reason self protected IO is not a direct replacement is because of the addressing scheme The older IO cards used the LOW MIDDLE and HIGH bytes of a base address and the MACRO I variables would read consecutive IO cards in this manner The self protected I
4. 59 5 ACC 57E 16 Feedback 16 B ACC 58E Devices Chip Select Addresses Chip UMAC Turbo MACRO UMAC Turbo MACRO Select Type A Card Type Card 10 078C00 SFFEO or 8800 078C00 079C00 8800 9800 07ACO00 507 00 A800 B800 12 078D00 FFE8 or 58840 078D00 079D00 8840 9840 07AD00 07BD00 A840 B840 14 078E00 FFFO or 8880 078E00 079E00 8880 9880 07AE00 07EC00 5 880 5 880 16 5078 00 588 0 078F00 079F00 88C0 98C0 507 0 07BF00 5 8 0 5 8 0 Hardware Setup 5 Accessory 68E Addressing Conflicts When just using only the type A UMAC cards or using only the type B UMAC cards in an application the user does not have to worry about potential addressing conflicts other than making sure the individual cards are set to the addresses as specified in the manual If the user has both type A and type B UMAC cards in their rack they should be aware of the possible addressing conflicts If the customer is using the Type A card on a particular Chip Select 510 CS12 CS14 or CS16 then they cannot use a Type B card with the same Chip Select address unless the Type B card is a general IO type If the Type B card is a general IO type then the Type B card will be the low byte card at the Chip Select address and the Type A card s will be setup at as the middle byte and high byte addresses Type A and Type B Example 1 ACC 11E and A
5. 20 21 22 23 7042 gt B SLtop PLC This PLC will abort all motion programs and kill the bus E stop is depressed 7024 Y 7025 Y M7026 Y M7027 Y M7028 Y M7029 Y M7030 Y M7031 Y M7032 Y M7033 Y M7034 Y M7035 Y M7036 Y M7037 Y 7038 Y 7039 Y 7040 Y 7041 Y 7043 Y 7044 Y 7045 Y 7046 Y 7047 Y When 078C03 0 1 078C03 1 1 078C03 2 1 078C03 3 1 078C03 4 1 078C03 5 1 078C03 6 1 078C03 7 1 078C04 0 1 5078 04 5078 04 5078 04 5078 04 5078 04 5078 04 5078 04 OU DU N H p ret ret re p po po 078C05 0 1 078C05 1 1 078C05 2 1 078C05 3 1 078C05 4 1 078C05 5 1 078C05 6 1 078C05 7 1 allowing 5 seconds for proper bus voltage P7000 used M7000 used M8000 used I5111 used OPEN PLC 5 CLEAR IF 7000 1 and 7000 0 CMD A 15111 500 8388608 110 WHILE ENDWHILE CMD 1511120 K 8000 0 7000 1 Endif IF M7000 0 and P7000 1 8000 1 5111 5000 8388608 110 WHILE ENDWHILE 1511120 T as a Latch variable Emergency Stop Input as Main Contact for main AC for as count down timer from 9 Input Inpu Input Inpu Inpu Input Inpu Inpu Input Inpu Inpu Input Inpu Inpu Inpu Inpu Input Inpu Inpu Input Inpu Inpu Input
6. 078 078 078 PLC to 078E 078E 078E 078E 078E 078E 078E 078E C00 0 C01 0 C02 0 C03 0 C04 0 C05 0 06 0 C07 0 07 0 8 OPEN PLC 1 CLI EAR initialize read write I O Bits 0 7 are read write Bits 8 15 are read write Bits 16 23 are read write Bits 24 31 are read write Bits 32 39 are read write Bits 40 47 are read write 21 0 21 0 21 0 ROJO register bits bits bits bits bits bits 0 7 port A ICO 8 15 port A ICO 16 23 port A ICO 0 7 port B ICQ 8 15 port B ICO 16 23 port B ICO selected control register 21 0 21 0 21 0 21 0 71 0 bits bits bits bits bits bits 0 7 port 8 15 port 16 23 port 0 7 port 8 15 port 16 23 port B register selected control register 21 0 UZO 21 0 21 0 T 0 21 0 register bits bits bits bits bits bits 0 7 port A IC2 8 15 port A IC2 16 23 port A IC2 0 7 port B IC2 8 15 port B IC2 16 23 port B IC2 selected control register control ole ode da control for T8000 0 8 for 578000 0 8 for S7BE00 0 28 word word word KKK bits 79C05 0 8 7800508 79C05 AA 2007 507 define bits 0 23 as inputs and bits 24 47 as outputs ACC 68E M2015 3F define bits 0 23 and 24 47 as inputs ACC 66E 2023 500 defin
7. 2 Setup Register 2_ Setup Register 3 Base 6 Register Selected Data Register Setup n a In a typical application non zero combined values of Bits 6 and 7 are used only for initial configuration of the IC These values are used to access the setup registers at the other addresses After the configuration is finished zeros are written to both Bits 6 and 7 so the data registers at the other registers can be accessed Control Word Setup Example You need to set up the control words for the IO card at power up To accomplish this task a simple PLC could be written to set up the control word properly For this example we will be setting up one ACC 68E ICO 24in 24out one ACC66E 48 inputs and one ACC 67E IC2 48 outputs Using Acc 68E with UMAC Turbo 9 Accessory 68E Control Word for ACC 68E 2007 gt 5078 07 0 8 Hex 0 0 Binary Bit 71615 413121110 Register M2000 Y M2001 Y 2002 gt 5078 2003 gt 5078 2004 gt 5078 2005 gt 5078 2006 gt 5078 2007 gt 5078 5078 5078 M2008 Y M2009 Y M2010 Y M2011 Y M2012 Y M2013 Y M2014 Y M2015 Y 078 078 078 078 078 078 078 078 M2016 Y M2017 Y M2018 Y M2019 Y M2020 Y M2021 Y M2022 gt Y M2023 gt Y M2007 Y M2015 Ys M2023 Y
8. Control Register CS10 CS12 CS14 CS16 Description SW1 1 ON SW1 1 OFF SW1 1 ON SW1 1 OFF SW1 2 SW1 2 ON SW1 2 OFF SW1 2 OFF 5078 00 0 8 Y DOO 0 8 Y E00 0 8 5078 00 0 8 I O bits 0 7 Z Z 5078 01 0 8 Y D01 0 8 Y E01 0 8 5078 01 0 8 I O bits 8 15 5078 02 0 8 5078002 0 8 Y E02 0 8 5078 02 0 8 bits 16 23 ea t 5078 03 0 8 Y 0 8 Y E03 0 8 5078 03 0 8 I O bits 24 31 z z 5078 04 0 8 Y 0 8 Y E04 0 8 5078 04 0 8 I O bits 32 39 22 5078 05 0 8 Y 0 8 Y E05 0 8 Y 078F05 0 8 I O bits 40 47 1 5078C07 0 8 Tas 0 8 Yt E07 0 8 1 078F07 0 8 Control Word 5079 00 0 8 Y 079D00 0 8 5079 00 0 8 Y S079F00 0 8 bits 0 7 E Z 5079 01 0 8 Y 5079D01 0 8 5079 01 0 8 8079 01 0 8 I O bits 8 15 v 5079c02 0 8 Y 079D02 0 8 5079 02 0 8 5079 02 0 8 bits 16 23 e 5079 03 0 8 5079003 0 8 5079 03 0 8 5079 03 0 8 I O bits 24 31 gt Y 079C04 0 8 5079004 0 8 5079 04 0 8 5079 04 0 8 bits 32 39 22 Y 079C05 0 8 5079005 0 8 5079 05 0 8 Y 079F05 0 8 I O bits 40 47 5079C07 0 8 Y 9079D07 0 9 1 5079E07 0 8 5079 07 0 8 Control Word Y 07AC00 0 8 Y 07AD00 0 8 507 00 0 8 507 00 0 8 I O bits 0 7 Y 07AC01 0 8 Y S07AD01 0 8 507 01 0 8 Y 07AF01 0 8 I O bits 8 15 v 5072c02 0 8 507 002 0 8 Y S07AE02 0 8 Y SO7AF02 0 8 bits 16 23 507 03 0 8 Y 507AD03 0 8 Y S07AE03 0 8 Y SO
9. a BOTTOM 1 J2 3 L Y H jo EI DELTA TAU AT TREO 24 IN 24 OUT ACC 68E DB15 Option VS E af i HI Qu d 24 IN 24 OUT i x 1 puc top 2 A Ha 25 m HERE B B 5 5 B E Pom P1 Sr lp ds m TB1 3 S pus Ins mn vb ms E E aa ms 5 na TD da i J2 BOTTOM J1 _ eseooc DE 00445 Hardware Setup 3 Accessory 68E Address Select DIP Switch S1 The switch one S1 settings will allow the user to select the starting address location for the first IO gate on the ACC 68E The following two tables show the dip switch settings for both the TURBO PMAC 3U and the MAC RO Station TURBO PMAC 3U Switch Settings CHIP 3U Turbo SWITCH SW1 POSITION SELECT PMAC 6 5 4 3 2 1 Address Y 78C00 03 CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CS10 Y 79C00 03 CLOSE CLOSE CLOSE OPEN CLOSE CLOSE Y 7AC00 03 CLOSE CLOSE OPEN CLOSE CLOSE CLOSE Y 7BC00 03 CLOSE CLOSE OPEN OPEN CLOSE CLOSE Y 78D00 03 CLOSE CLOSE CLOSE CLOSE CLOSE OPEN
10. 2 1 0 value o o ojojojo o ojo o o o r r ojo MS0 975 000 50 1975 54 Enable VO Node 2 alone 50 975 5 Enable I O Nodes 2 amp 3 50 975 54 Enable I O Nodes 2 3 amp 6 50 975 5 Enable I O Nodes 2 3 6 amp 7 50 975 54 Enable I O Nodes 2 3 6 7 amp 10 50 975 5 Enable I O Nodes 2 3 6 7 10 amp 11 54 975 540 Enable I O Node 6 alone 54 975 5 0 Enable 1 Nodes 6 amp 7 58 975 5400 Enable I O Node 10 alone 58 975 5 00 Enable I O Nodes 10 amp 11 MACRO VO Software Settings 15 Accessory 68E MI69 and MI70 specify the registers used 16 bit I O transfers between MACRO node interface registers and I O registers on the MACRO Station I O accessory board They are used only if MI19 is greater than 0 Note The examples for the setup of MI69 and MI70 require MACRO firmware 1 16 and above MI69 and MI70 are 48 bit variables represented as 12 hexadecimal digits The first 6 digits specify the number and address of 48 bit 3 x 16 real time MACRO node register sets to be used The second 6 digits specify the number and address of 16 bit I O sets on the MACRO Station I O accessory board to be used The individual digits are specified as follows 1 0 1 2 3 Number of MACRO nodes to use 0 disables this should also match the number of 48 bit I O sets you intend to use see Digit 7 COA1 Node 2 C0
11. 823 gt 0010 0 15 824 gt 0010 0 16 825 gt 0010 0 17 826 gt 0010 0 18 827 gt 0010 0 19 828 gt 0010 0 20 829 gt 0010 0 21 830 gt 0010 0 22 M831 gt Y 0010F0 23 Reading and Writing to Node Addresses M832 gt X 0010F 1 8 M833 gt X 0010F 1 9 M834 gt X 0010F 1 10 M835 gt X 0010F 1 11 M836 gt X 0010F 1 12 M837 gt X 0010F 1 13 M838 gt X 0010F 1 14 M839 gt X 0010F 1 15 M840 gt X 0010F 1 16 M841 gt X 0010F 1 17 M842 gt X 0010F 1 18 M843 gt X 0010F 1 19 M844 gt X 0010F 1 20 M845 gt X 0010F 1 21 M846 gt X 0010F 1 22 M847 gt X 0010F 1 23 21 Accessory 68E IO word 4 IO Word 5 IO Word Z6 M900 Y 0010F1 8 901 gt 0010 1 9 902 gt 0010 1 10 M903 gt Y 0010F 1 11 M904 gt Y 0010F 1 12 M905 gt Y 0010F 1 13 M906 gt Y 0010F 1 14 M907 gt Y 0010F 1 15 M908 gt Y 0010F 1 16 M909 gt Y 0010F 1 17 M910 gt Y 0010F 1 18 M911 gt Y 0010F 1 19 M912 gt Y 0010F 1 20 M913 gt Y 0010F 1 21 M914 gt Y 0010F 1 22 M915 gt Y 0010F 1 23 M916 gt X 0010F2 8 M917 gt X 0010F2 9 M918 gt X 0010F2 10 M919 gt X 0010F 2 11 M920 gt X 0010F2 12 M129 gt X 0010F2 13 M922 gt X 0010F2 14 M923 gt X 0010F2 15 M924 gt X 0010F2 16 M925 gt X 0010F2 17 M926 gt X 0010F2 18 M927 gt X 0010F2 19 M928 gt X 0010F2 20 129 gt 0010 2 21 930 gt 0010 2 22 931 gt 0010 2 23 M932
12. Y A840 Y 9A847 0 8 MI198 40A847 Y B840 5 8 5 847 0 8 198 540 847 Y 8880 Y 8887 0 8 MI198 408887 Y 9880 59887 0 8 198 5409887 Y A880 Y SA887 0 8 MI198 40A887 Y B880 SFFFO 5 887 0 8 1198 5408887 Y 88C0 Y 88C7 0 8 198 54088 7 Y 98C0 Y 98C7 0 8 198 54098 7 Y A8CO 5 8 7 0 8 MI198 40A8C7 Y B8C0 Y B8C7 0 8 MI198 40B8C7 for legacy systems Setting Up Control Word for MACRO IO 25 Accessory 68E Once we have the control word defined to MI198 we can write to the individual bytes associated with the IO gate and make them either read only or read write default Byte 0 Byte 1 Byte 2 Byte 3 Byte4 Byte 5 58800 0 8 58801 0 8 58802 0 8 58803 0 8 58804 0 8 58805 0 8 59800 0 8 59801 0 8 59802 0 8 59803 0 8 59804 0 8 59805 0 8 Example MACRO Station has 68 24in 24out and ACC 66E 48 set to base addresses 8800 and 9800 respectively mer 15111 tdefine Ti define Timerl M70 M70 X 50700 0 24 8 Open PLC 10 Clear Timer1 2000 8388608 110 While Timer1 gt 0 Endwhile CMD MS0 MI 50 11 99 507 Timer1 50 8388608 1 1 gt 0 While 198 408807 10 Endwhile CMDYMSO MI 50 11 99 53 Timer1 50 8388608 1 Endwhile While Tin
13. gt Y 0010F2 8 M933 gt Y 0010F2 9 934 gt 0010 2 10 935 gt 0010 2 11 936 gt 0010 2 12 937 gt 0010 2 13 938 gt 0010 2 14 939 gt 0010 2 15 940 gt 0010 2 16 941 gt 0010 2 17 942 gt 0010 2 18 943 gt 0010 2 19 944 gt 0010 2 20 945 gt 0010 2 21 946 gt 0010 2 22 947 gt 0010 2 23 Example 1 48 inputs 48 outputs using 1x24 bit transfers For this example the inputs and outputs are not sharing the same Node Transfer Address C0A0 C0A4 COAS8 COAC Each of the node transfer addresses be defined as 24 bit addresses Ultralite Axis Turbo Ultralite Axi 1996 0FB3FF 16841 0FB3FF Enable nodes 0 1 2 3 4 5 6 7 8 9 12 amp 13 at PMAC Ultralite 970 gt 0 0 0 24 M970 gt X 78420 0 24 IO word 1 24 bit word node2 971 gt 0 4 0 24 971 gt 78424 0 24 word 2 24 bit word node 3 972 gt 0 8 0 24 972 gt 578428 0 24 IO word 3 24 bit word node 6 IM973 gt X COAC 0 24 M973 gt X 7842C 0 24 IO word 1 24 bit word node 7 0 IM 1003 gt Y 0771 0 24 1003 gt 80010 1 0 24 mirror word 2 1010 gt 50772 0 24 M1010 gt X 0010F2 0 24 Old Input mirror word 2 1011 gt 80772 0 24 1 1011 gt 80010 2 0 24 Old Input mirror word 3 MSO MI71 20C0A0218800 MS0 MI975 CC 1000 gt 80770 0 24 M1000 gt X 0010F0 0 24 Input mirror
14. gt Y 771 21 M914 gt Y 771 22 915 gt 9771 23 20 M816 gt Y 770 8 M817 gt Y 770 9 M818 gt Y 770 10 M819 gt Y 770 11 M820 gt Y 770 12 M829 gt Y 770 13 822 gt 770 14 M823 gt Y 770 15 M824 gt Y 770 16 M825 gt Y 770 17 M826 gt Y 770 18 M827 gt Y 770 19 M828 gt Y 770 20 M829 gt Y 770 21 M830 gt Y 770 22 M831 gt Y 770 23 M916 gt X 772 8 M917 gt X 772 9 918 gt 772 10 M919 gt X 772 11 M920 gt X 772 12 M129 gt X 772 13 922 gt 772 14 M923 gt X 772 15 924 gt 772 16 925 gt 772 17 926 gt 772 18 927 gt 772 19 928 gt 772 20 129 gt 772 21 930 gt 772 22 931 gt 772 23 832 gt 771 8 833 gt 771 9 834 gt 771 10 835 gt 771 11 836 gt 771 12 837 gt 771 13 838 gt 771 14 839 gt 771 15 840 gt 771 16 841 gt 771 17 842 gt 771 18 843 gt 771 19 844 gt 771 20 845 gt 771 21 846 gt 771 22 847 gt 771 23 M932 gt Y 772 8 M933 gt Y 772 9 M934 gt Y 772 10 935 gt 772 11 M936 gt Y 772 12 M937 gt Y 772 13 938 gt 772 14 939 gt 772 15 M940 gt Y 772 16 M941 gt Y 772 17 M942 gt Y 772 18 M943 gt Y 772 19 M944 gt Y 772 20 M945 gt Y 772 21 M946 gt Y 772 22 M947 gt Y 772 23 Reading and Writing to Node Addresses Accessory 68E PMAC2 TURBO Ultralite
15. 29 I 29 984 gt 578426 8 16 1000 gt 50010 0 8 16 1001 gt 50010 0 8 16 m ss M1005 gt Y 0010F2 8 16 M1010 gt X 0010F3 8 16 M1011 gt Y 0010F3 8 16 M1012 gt X 0010F4 8 16 8800 sets up macro to transfer data for ACC 68E 66E enable node 2 and 3 for VO sets interrupt period for data transfer save to macro station reset macro station to enable IF M1000 M1010 OR M1001 M1011 M1010 M1000 Reading and Writing to Node Addresses new input mirror equal to actual input word new input mirror equal to actual input word new input mirror equal to actual input word if inputs change process outputs old input mirror equal to new input mirror 23 Accessory 68E ENDIF CLOSE 24 M1011 M1001 M983 M1003 M984 1004 M985 M1005 old input mirror equal to new input mirror Set outputs based on inputs or program logic Output word equals Output Mirror Word Output word equals Output Mirror Word Output word equals Output Mirror Word Reading and Writing to Node Addresses Accessory 68E SETTING UP CONTROL WORD FOR MACRO IO The Delta Tau IO gate array used on the UMAC IO accessories has the ability to allow any of the 48 bits be used as an input read or an output write To protect the inputs to be read only the user can define the individual bits as read only on a byte by byte basis This accomplished by writing to the control word of the IO
16. 6 X 078428 7 X 8078429 X 07842A 5078428 Example If the user wanted to read the inputs from the MACRO Station of the first 24 bit I O node address of node 2 X C0A0 then he she could point an M variable to the Ultralite or TURBO Ultralite VO node registers to monitor the inputs M980 X C0A0 0 24 Ultralite node2 address 1980 gt 5078420 0 24 TURBO Ultralite MACRO ICO node 2 address These M variable definitions M980 or M1980 could then be used to monitor the inputs for either the Ultralite or TURBO Ultralite respectively 14 MACRO Station VO Transfer Accessory 68E MACRO SOFTWARE SETTINGS The MACRO Station I O can be configured as either an input or an output The hardware connected to the MACRO I O boards determines whether or not the addresses defined are inputs or outputs Each I O node has 72 bits of data to be transferred automatically to the Ultralite As stated previously there are three methods of transfer 3x16 bit 1x24 bit or 72 bit transfer There are several variables at the MACRO Station and PMAC2 Ultralite that enable the I O data transfer Once these variables are set to the appropriate values the user can then process the data like a normal PMAC or PMAC2 The variables to be modified at the MACRO Station are MI69 70 or MI71 To read multiple extended address UMAC IO cards efficiently a new function was added to MACRO firmware 1 16 to read consecutive extended add
17. CS12 Y 79D00 03 CLOSE CLOSE CLOSE OPEN CLOSE OPEN Y 7AD00 03 CLOSE CLOSE OPEN CLOSE CLOSE OPEN Y 7BD00 03 CLOSE CLOSE OPEN OPEN CLOSE OPEN Y 78E00 03 CLOSE CLOSE CLOSE CLOSE OPEN CLOSE CS14 Y 79E00 03 CLOSE CLOSE CLOSE OPEN OPEN CLOSE Y 7AE00 03 CLOSE CLOSE OPEN CLOSE OPEN CLOSE Y 7BE00 03 CLOSE CLOSE OPEN OPEN OPEN CLOSE Y 78F00 03 CLOSE CLOSE CLOSE CLOSE OPEN OPEN CS16 Y 79F00 03 CLOSE CLOSE CLOSE OPEN OPEN OPEN Y 7AF00 03 CLOSE CLOSE OPEN CLOSE OPEN OPEN Y 7BF00 03 CLOSE CLOSE OPEN OPEN OPEN OPEN MACRO Station Switch Settings CHIP 3U Turbo PMAC SWITCH SW1 POSITION SELECT Address 6 5 4 3 2 1 Y 8800 CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CS10 Y 9800 CLOSE CLOSE CLOSE OPEN CLOSE CLOSE Y A800 CLOSE CLOSE OPEN CLOSE CLOSE CLOSE Y B800 FFEO CLOSE CLOSE OPEN OPEN CLOSE CLOSE Y 8840 CLOSE CLOSE CLOSE CLOSE CLOSE OPEN CS12 Y 9840 CLOSE CLOSE CLOSE OPEN CLOSE OPEN Y A840 CLOSE CLOSE OPEN CLOSE CLOSE OPEN Y B840 FFE8 CLOSE CLOSE OPEN OPEN CLOSE OPEN Y 8880 CLOSE CLOSE CLOSE CLOSE OPEN CLOSE CS14 Y 9880 CLOSE CLOSE CLOSE OPEN OPEN CLOSE Y A880 CLOSE CLOSE OPEN CLOSE OPEN CLOSE Y B880 FFFO CLOSE CLOSE OPEN OPEN OPEN CLOSE 588 0 CLOSE CLOSE CLOSE CLOSE OPEN OPEN CS16 598 0 CLOSE CLOSE CLOSE OPEN OPEN OPEN Y A8CO CLOSE CLOSE OPEN CLOSE OPEN OPEN Y B8CO CLOSE CLOSE OPEN OPEN OPEN OPEN The default
18. gate Each IO gate has eight 8 bit words IO word 0 IO bits 0 7 IO word 1 O bits 8 15 IO word 2 O bits 16 23 IO word 3 O bits 24 31 IO word 4 O bits 32 39 IO word 5 O bits 40 47 IO word 6 Data Word IO word 7 Control Word IO words 0 through 5 contain the actual IO data IO word 7 is the control word that allows us to turn any of the IO words into read only bits The lower 6 bits of the Control Word are used to tell the IO gate whether or not the data in the six IO word bytes are read only or read write registers For example if the user wanted to make IO word 0 IO word 1 and IO word 2 bits 0 23 read only they would have to set the IO control word equal to 7 binary 000111 As of MACRO firmware release 1 16 there are no MI variables to support direct access to the IO control words An easy method can be used to write directly to the control word of the IO gate using MI198 MI199 place the register you want to read or write to into MI198 and the read or write to that value using 1199 This will usually be done in a one time read PLC at power up Base Address from Control Word MII98 Setting SWI Setting Location Y 8800 58807 0 8 MI198 408807 Y 9800 Y 9807 0 8 MI198 409807 Y A800 Y SA807 0 8 MI198 40A807 Y B800 0 5 807 0 8 MI198 40B807 Y 8840 58847 0 8 MI198 408847 Y 9840 59847 0 8 MI198 409847
19. word 1 1002 gt 80771 0 24 1002 gt 80010 1 0 24 Output mirror word 1 1 a IM1001 gt Y 0770 0 24 M1001 gt Y 0010F0 0 24 Input mirror word 2 sets up macro to transfer data for 68 and 66E enable node 2 3 6 and 7 for VO at MACRO Station 50 119 4 sets interrupt period for data transfer MSSAVEO save to macro station MS 0 reset macro station to enable OPEN PLC1 CLEAR 1000 970 1001 971 new input mirror equal to actual input word new input mirror equal to actual input word IF M1000 M1010 OR M1001 M1011 if inputs change process outputs 22 Reading and Writing to Node Addresses Accessory 68E M1010 M1000 M1011 M1001 M973 M1002 M974 M1003 ENDIF CLOSE old input mirror equal to new input mirror old input mirror equal to new input mirror Set outputs based on inputs or program logic Output word equals Output Mirror Word Output word equals Output Mirror Word Example 2 48 inputs 48 outputs using 3x16 bit transfers For this example the inputs and outputs are not sharing the same Node Transfer Address C0A1 C0A2 C0A3 COAS COA6 and COA7 Each of the node transfer addresses can be defined as 16 bit addresses MS0 MI697 20C0A131 MS0 MI975 C 50 119 4 MSSAVEO MS 0 OPEN PLC1 CLEAR 1000 980 1001 981 1002 982 M1003 gt Y 0771 8 16 Turbo Ultralite 8 Axis 16841 0FB33F M981 gt X 78422 8 16 I
20. 18 Reading and Writing to Node Addresses Accessory 68E Active Nodes for Compact MACRO I O Station example Node s Gate Addresses Node Transfer Addresses 8800 SCOAI SCOA2 8C0A3 96 Bit 2 3 8800 C0A1 C0A2 C0A3 9800 C0A5 C0A6 COA7 144 Bit C0OA1 C0A2 C0A3 C0A5 C0A6 COA7 C0A9 COAA SCOAB The data in this application will transfer 48 bits of data per node as specified by MI69 These memory locations could be utilized by pointing an M variable to the node locations In your PLC program these M variables would be considered the actual input words and actual output words or a combination of the two 8 inputs 8 outputs for 16 bit read write To efficiently read and write to these memory locations Delta Tau suggests using image input words to read the actual input words and then write to the actual output word if the inputs have changed states The following block diagram shows the typical logic for PMAC s inputs and outputs input mirror lt input word yes in mirror old in mirror no old input mirror input word Process Inputs Build Output Word Perform Desired Actions output word out mirror d END For this application we are using six 16 bit data transfers and will use the following M Variable definitions in our application Reading and Writing to Node Addresses 19 Accessory 68E PMAC2 Ultralite Example
21. 7AF03 0 8 bits 24 31 gt m 5074 04 0 8 507 004 0 8 Y S07AE04 0 8 Y SO7AF04 0 8 T O bits 32 39 GE Y 07AC05 0 8 Y 07AD05 0 8 507 05 0 8 507 05 0 8 I O bits 40 47 Y 5072007 0 8 0 8 Y 50TAEQT 0 9 Y 507A8F07 0 8 Control Word Y 078C00 0 8 Y 07BD00 0 8 507 00 0 8 507 00 0 8 I O bits 0 7 E E 507 01 0 8 507 001 0 8 507 01 0 8 507 01 0 8 bits 8 15 507 02 0 8 507 002 0 8 507 02 0 8 507 02 0 8 I O bits 16 23 507 03 0 8 507 003 0 8 507 03 0 8 507 03 0 8 bits 24 31 m m Y 07BC04 0 8 507 004 0 8 507 04 0 8 Y 07BF04 0 8 I O bits 32 39 2 507 05 0 8 507 005 0 8 507 05 0 8 Y 07BF05 0 8 I O bits 40 47 3 5079007 0 8 Y 9078DQ07 0 59 1Y 9078E07 0 8 Y 5078F07 0 8 Control Word Note SW1 5 and SW1 6 must be set to ON The control register at address Base 7 permits the configuration of the IOGATE IC to a variety of applications The control register consists of 8 write read back bits Bits 0 7 The control register consists of two sections Direction Control and Register Select The direction control allows setting input bytes to be read only One of the advantages of the IOGATE IC is the ability to define the bits as inputs or outputs This control mechanism Using Acc 68E with UMAC Turbo Accessory 68E allows you to ensure the inputs will always be read properly Our traditi
22. A5 Node 3 MACRO Station X Address of MACRO I O node first C0A9 Node 6 COAD Node 7 of three 16 bit registers COBI Node 10 COB5 Node 11 7 0 1 2 3 Number of 16 bit I O sets to use 1x16 2x16 3x16 0 disables 1 Set to 1 for 14 ACC 68E 66 ACC 67E consectutive address read Base 1000 2000 9 12 8800 8840 MACRO Station Y Base Address of ACC 14E ACC 8880 88CO 68E ACC 66E ACC 67E When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output and pulls the output low Example 1 48 bit I O transfer using node 2 with IO card base address of 8800 MS0 MI69 10C0A1318800 2 96 bit I O transfer using nodes 2 and 3 with IO card base address of 8800 and 9800 MS0 MI69 20C0A1318800 3 288 bit I O transfer using nodes 2 3 6 7 10 and 11 using 6 IO cards Setup using 144 bit transfer with MI69 and 144 bit transfer with MI70 The first three IO cards are addressed at 8800 9800 and A800 The second three IO cards are addressed at 8840 9840 and A840 MS0 MI69 30C0A1318800 MS0 MI70 30C0AD318840 16 MACRO VO Software Settings Acces
23. Accessory 68E DELTA TAU Data Systems Inc NEW IDEAS IN MOTION Single Source Machine Control Power Flexibility Ease of Use 21314 Lassen Street Chatsworth CA 91311 Tel 818 998 2095 Fax 818 998 7807 www deltatau com Accessory 68E Table of Contents INTRODUCTION ccc N OE EE EE OE 1 HARDWARE SETUP ede see 2 LAYOUT DIAGRAM EE t HE E Ed ER OE OE EE Re EE ERES Ce 3 ADDRESS SELECT SWITCH 1 se ee ee ee es ee ee ee se ee ee ee ee nennen enne nnne RR Re Re ee 4 TURBO PMAC 30 Switch Settings cossis anran eene enne A E nnne nennt 4 MACRO Station Switch Settings 4 JUMPERS EE E Ee 5 HARDWARE ADDRESS IMITATIONS ei Se 5 Addressing Conflicts EE OE EN nde N 6 and Example 1 ACC 11E and 6 6 A Example 2 and 68 0 0 9 6 USING ACC 68E WITH 8 UMAC TURBO MEMORY MAPPING FOR 68 8 CONTROL REGISTER cccsccsccccecsessseceeececsessnseeecceeceeseuaeseescecsesuaseesececeesuaeseeecesseua
24. CC 36E If the user has an ACC 11E and ACC 36E the user cannot allow both cards to use the same Chip Select because the data from both cards will be overwritten by the other card The solution to this problem is to make sure you do not address both cards to the same chip select Type A and Type B Example 2 ACC 11E and ACC 68E For this example the user could allow the two cards to share the same chip select because the ACC 68E is a general purpose IO Type B card The only restriction in doing so is that the ACC 68E must be considered the low byte addressed card and the ACC 11E must be jumpered to either the middle or high bytes jumper E6A E6H 6 Hardware Setup Accessory 68E Hardware Setup Accessory 68E USING ACC 68E WITH UMAC TURBO For the UMAC Turbo the ACC 68E can be used for either general purpose I O or as latched inputs The registers used for general I O use are 8 bit registers and you will define three 8 bit registers for each 24 bit I O port UMAC Turbo Memory Mapping for 68 The Delta Tau I O Gate used on the ACC 68E is an 8 bit processor and therefore the memory mapping to the I O bits is processed as 8 bit words at the Turbo UMAC Using this simple scheme the user could process up to 768 48x16 bits of data for general purpose I O
25. Example M Variable Definitions 980 gt 78421 8 16 word 1 1 16 bit word node2 981 gt 78422 8 16 word 2 2 16 bit word node 2 982 gt 78423 8 16 IO word 3 34 16 bit word node 2 983 gt 78425 8 16 word 1 1 16 bit word node 3 M984 gt X 78426 8 16 IO word 2 2 16 bit word node 3 M985 gt X 78427 8 16 IO word 3 34 16 bit word node 3 1000 gt 0010 0 8 16 mirror word 1 M1001 gt Y 0010F0 8 16 Input mirror word 2 M1002 gt X 0010F 1 8 16 Input mirror word 3 M1003 gt Y 0010F 1 8 16 Output mirror word 1 M1004 gt X 0010F2 8 16 Output mirror word 2 M1005 gt Y 0010F2 8 16 Output mirror word 3 M1010 gt X 0010F3 8 16 Old Image mirror word 1 M1011 gt Y 0010F3 8 16 Old Image mirror word 2 1012 gt 0010 4 8 16 Old Image mirror word 3 IO word 71 IO Word 2 IO Word 3 800 gt 0010 0 8 801 gt 0010 0 9 802 gt 0010 0 10 803 gt 0010 0 11 804 gt 0010 0 12 805 gt 0010 0 13 806 gt 0010 0 14 807 gt 0010 0 15 808 gt 0010 0 16 809 gt 0010 0 17 810 gt 0010 0 18 811 gt 0010 0 19 812 gt 0010 0 20 813 gt 0010 0 21 814 gt 0010 0 22 815 gt 0010 0 23 816 gt 0010 0 8 M817 gt Y 0010F0 9 818 gt 0010 0 10 819 gt 0010 0 11 820 gt 0010 0 12 829 gt 0010 0 13 822 gt 0010 0 14
26. G 3x16 BIT TRANSFERS 2 404004 4 eke ee ee 23 SETTING UP CONTROL WORD FOR MACRO 1O eee se ee eese 25 LEGACY MACRO SYSTEMS ss esse sesse se Ge aoo ee e voe see sees ee oog eed e ee ed Ge gee ee eg uve Even 27 EI E4 VO Gate Transfer Jumper iis se ee se ese ee ee se ee Ge ee Ge ee GR ee GR Ge ee ee Ge eke Ge ee GR ee ek Ge ek ee ee 27 MACRO VO ACCESSORY CONNECTORS ee eeee eese enne es ss se ees se ee Ge Ge ee Ge Ge ee Ge ee Ge AG ee ee 29 PI UBUS 06 PINHEADER ii Ee ee Ge ER Ee Se Ee neg ee Eg ee INR Gee Ge GE bee ER Ee 29 6 P 30 IBI Top 12 Pin Terminal Block 5 ies Ee a oe e aa eins totae b QURE e AS era eue bl ese es das 30 182 12 Pin Terminal BloCk a ia a asi cesis cte daniele cta UV a ERR Eee UE 30 TB3 Top 3 Pin Terminal Block e e e 30 IBI Bottom 12 Pin Terminal Block vids tener rhe ER oe Se 31 182 Bottom 12 Pin Terminal Block ic Wigs te ets wines eshte SU web RE cepe 31 TB3 Bottom 3 Pin Terminal Block se GR Ge ek Ge ee 31 15 CONNECTOR 5522 FN o URN EE
27. Inpu E Stop button lt ctrl gt command Bus Voltage emergancy stop condition global motion program abort 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 n OU i voltage to in pulled after 101 7500 msec delay for deceleration kill all axes turn off BUS voltage latch input enable BUS volatge 759000 msec delay for bus voltage Using Acc 68E with UMAC Turbo 11 Accessory 68E CMD A 7000 0 Endif close loop for all servos latch input 12 Using Acc 68E with UMAC Turbo Accessory 68E MACRO STATION TRANSFER A fundamental understanding of the MACRO Station I O transfer is needed to set up the MACRO VO family of accessories The MACRO station typically will have up to eight axis nodes 0 1 4 5 8 9 12 and 13 and up to six I O transfer nodes 2 3 6 7 10 and 11 There are two types of I O transfers allowed to send the information to the Ultralite from the MACRO Station 48 bit transfer and 24 bit transfer The PMAC2 Ultralite and the MACRO Station enable the user to transfer 72 bits per VO node For a multi Master system 432 bits 6x72 of data may be transferred for each Master Ultralite in the ring If only one Master is used in the ring node 14 could be used for I O transfer which would give us 504 bits 7x72 of I O transfer data For all MACRO Station I O accessories the information
28. M Variable Definitions M980 gt X C0A1 8 16 word 1 1 16 bit word node2 M981 X C0A2 8 16 word 2 2 16 bit word node 2 M982 gt X C0A3 8 16 word 3 34 16 bit word node 2 M983 gt X C0A5 8 16 word 1 1 16 bit word node 3 M984 gt X C0A6 8 16 word 2 2 16 bit word node 3 M985 gt X C0A7 8 16 IO word 3 34 16 bit word node 3 1000 gt 0770 8 16 M1001 gt Y 0770 8 16 M1002 gt X 0771 8 16 M1003 gt Y 0771 8 16 M1004 gt X 0772 8 16 M1005 gt Y 0772 8 16 M1010 gt X 0773 8 16 M1011 gt Y 0773 8 16 M1012 gt X 0774 8 16 IO word 1 IO Word 2 IO Word 3 Input mirror word 1 Input mirror word 2 Input mirror word 3 Output mirror word 1 Output mirror word 2 Output mirror word 3 Old Image mirror word 1 Old Image mirror word 2 Old Image mirror word 3 M800 gt X 770 8 M801 gt X 770 9 802 gt 770 10 803 gt 770 11 804 gt 770 12 M805 gt X 770 13 M806 gt X 770 14 M807 gt X 770 15 808 gt 770 16 809 gt 770 17 M810 2X 770 18 811 gt 770 19 812 gt 770 20 813 gt 770 21 814 gt 770 22 M815 2X 770 23 IO word 4 IO Word 5 IO Word 6 M900 gt Y 771 8 M901 gt Y 771 9 M902 gt Y 771 10 M903 gt Y 771 11 M904 gt Y 771 12 M905 gt Y 771 13 M906 gt Y 771 14 M907 gt Y 771 15 M908 gt Y 771 16 M909 gt Y 771 17 M910 gt Y 771 18 M911 gt Y 771 19 M912 gt Y 771 20 M913
29. O cards are addressed from the LOW bytes only Because of this the MACRO I variables MI69 MI70 and MI71 were modified to read up to three consecutive base address cards in MACRO firmware version 1 16 Chip Select MACRO Address DIP SWITCH SW1 POSITION 6 5 4 3 2 1 CS 10 FFEO OPEN OPEN OPEN OPEN CLOSE CLOSE CS 12 FFE8 OPEN OPEN OPEN OPEN CLOSE OPEN CS 14 FFFO OPEN OPEN OPEN OPEN OPEN CLOSE CS 16 Cannot Use OPEN OPEN OPEN OPEN OPEN OPEN To use the new IO cards with the older firmware systems the user can use each of the IO transfer variables MI69 MI70 MI71 to transfer 48 bits each The main problem is that the older systems did not have the new extended addressing and the user can only use three IO cards per MACRO station e For systems with only one IO card the user will not have to change anything If any of these New IO cards are used with the ACC 9E ACC 10E ACC 11E or ACC 12E then the user should address the New IO card as the first card LOW byte in addressing scheme Legacy MACRO Systems 27 Accessory 68E 28 Legacy MACRO Systems Accessory 68E MACRO ACCESSORY CONNECTORS C32 00000000000000000000000000000000 P1 UBUS 96 B32 OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOIBI A321OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO AM PIN HEADER 55 BS Pi 7 1 5 0 2 2 2 2 2 2 S 2 2 2 2 2 ANALOG 2 F
30. ctly communicating to These memory locations are typically used with other Delta Tau 3U 1 accessories such as ACC 9E 10 ACC 12E 65 ACC66E ACC 67E ACC 68E 28 16 bit A D Converter Inputs up to four per card ACC 53E SSI Encoder Inputs of these accessories have settings which tell them where the information is to be processed at either the PMAC 3U Turbo or the MACRO Station 3U Turbo PMAC Memory Locations MACRO Station Memory Locations 078C00 079C00 8800 9800 07AC00 07BC00 A800 B800 078D00 079D00 8840 9840 07AD00 07BD00 A840 B840 078E00 079E00 58880 59880 07AE00 07 00 A880 B880 078F00 079F00 88C0 98C0 07AF00 07BF00 A8C0 B8C0 The ACC 68E has a set of dip switches telling it where to process its data Once the information is at these locations we can process the binary word in the encoder conversion table to use for servo loop closure Proper setting of the dip switches ensures all of the UBUS IO boards used in the application do not interfere with each other Hardware Setup Accessory 68E Layout Diagram ACC 68E Terminal Block Option e ress ae 33 BS Ed OO B DELTA TAU 24 J2 H TOP n m m m H m H m l m P1 H 1 2 TB1 m a m 4 m
31. e bits 0 23 and 24 47 as outputs ACC 67E DIS CLOSE 10 Using Acc 68E with UMAC Turbo Accessory 68E Accessory 68E M Variables for UMAC Turbo The following 15 a list of suggested M variables for the default Jumper settings is provided You may assign any M variables to these addresses You may make these M variable definitions and use them as general purpose I O for their PLC s or motion programs M701 M701 M701 M701 0 gt 7021 gt the motors when out the motors will servo to actual position 7000 Y 7001 Y M7002 Y M7003 Y M7004 Y M7005 Y M7006 Y M7007 Y M7008 Y M7009 Y 5078 01 1 gt 2 gt 3 Y 7014 Y J015 2Y 7016 Y 7017 Y 7018 Y 7019 Y 7020 Y 078C02 5 1 7022 Y 7023 Y 078C00 0 1 078C00 1 1 078C00 2 1 078C00 3 1 078C00 4 1 078C00 5 1 078C00 6 1 078C00 7 1 5078 01 5078 01 p pore rere 5078 01 5078 01 5078 01 5078 01 5078 01 5078 02 0 1 5078 02 1 1 5078 02 2 1 5078 02 3 1 5078 02 4 1 pig rd 79 1 0 1 1 1 2 L 3 3 1 4 Ls 1 6 p 078C02 6 1 078C02 7 1 Sample Inpu Inpu Input Inpu Inpu Input Inpu Inpu Input Inpu Inpu Input Inpu Inpu Inpu Inpu Input Inpu Inpu Input Inpu Inpu Input Inpu N HO HOU BU N HO
32. erminal block provides the inputs 13 24 for the ACC 68E I O Card Output Output Output o o sel H3 E E TB3 Bottom 3 Pin Terminal Block Top View Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking 2 1 Symbol EET OGND Reference voltage 24 uv This terminal block can be used to provide the input reference for the ACC 68E for the 24 outputs MACRO VO Accessory Connectors 3l Accessory 68E 32 MACRO VO Accessory Connectors Accessory 68E DB15 CONNECTOR OPTION DB15 Style Connector J1 Top Inputs 1 through 12 J1 Top Connector Front View 00000000 OOOOOOO 15 Pin Notes NO pct sg mo mw sn Sinking o Sinking Sinking DNI EE EE EE REFI Reference Voltage for Inputs 24V for Sinking 1 8 2 22 Mm BY LI PD 9 16 Sinking 10 Sinking 1 mos Sinking Sinking i Sinking i Sinking 15 REF3 Reference Reference Voltage for Inputs 24V for Sinking 17 24 DB15 Connector Option 33 Accessory 68E DB15 Style Connector J2 Top Inputs 12 through 24 J2 Top Connector Mm BY LI NTR Pin Notes Sinking Sinking Sinking Sinking Sinking mr pa np 3 inn REFI Reference Voltage for Inputs 24V for Sinking 1 8 Front View 00000000 OOOOOOO 15 9 16 5 Sinking Sinking Sink
33. ing 12 Sinking Sinking i Sinkine 15 REF3 Reference Reference Voltage for Inputs 24V for Sinking 17 24 34 DB15 Connector Option Accessory 68E DB15 Style Connector J1 Bottom Outputs 1 through 12 Front View ODOOOOOO Pin Notes Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking O424V Voltage 12 24V J1 Bottom Connector oo ND NY BY WwW NMI Re DR LI PD o CA DB15 Style Connector J2 Bottom Outputs 12 through 24 Front View BO OOOOOOO J2 Bottom Connector OOOOOOO 15 Pin Notes ouri Sinking our out operis ining Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking O424V Voltage 12 24V Ol Cl ALD NY BY WwW NI Ph Lol PD DB15 Connector Option 35
34. is transferred to or from the accessory I O Gate to the MACRO Station CPU Gate 2B Information from the MACRO Station Gate 2B Is then read or written directly to the MACRO IC on the Ultralite Once the information is at the Ultralite it can be used in the users application motion programs or PLC programs o 7 0 8 JG Ultralite MACRO Station MACRO IC Gate 2B Iu P UN VO Accessory Gate Ss Each I O board has jumper and software settings to select the I O transfer memory locations at both the VO transfer Gate and the MACRO transfer addresses These jumpers and software settings are discussed in this manual MACRO Station VO Node Transfer Addresses Node 16 bit upper 16 bits Transfer Addresses X COA1 X COA2 X C0A3 X C0AS X C0A6 X C0A7 s xscms XSCM XSCMAXSCUB X COAC X COAD X COAD X COAE X COBO X C0B1 X COB2 X COB3 X C0B4 X C0B5 X C0B6 X C0B7 Ultralite I O Node Addresses Node 24 bit Transfer Addresses Node 16 bit upper 16 bits Transfer Addresses X C0A0 X C0A1 X C0A2 X C0A3 X C0A4 X C0A5 X C0A6 X C0A7 6 5 0 8 X C0A9 X COAA X COAB X C0AC X COAD X COAD X COAE MACRO Station VO Transfer 13 Accessory 68E X COBO X COBI X COB2 X COB3 0 4 8 0 5 X COB6 X COB7 PMAC2 TURBO Ultralite 1 Node Addresses MACR Node 24 bit Node 16 bit upper 16 bits O IC Node Transfer Addresses Transfer Addresses Node acos
35. node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output and pulls the output low Example 1 48 bit I O transfer using nodes 2 and 3 with IO card base address of 8800 MS0 MI71 10C0A01218800 2 96 bit I O transfer using nodes 2 3 6 and 7 with IO card base address of 8800 and 9800 MS0 MI71 20C0A0218800 3 144 bit I O transfer using nodes 2 3 6 7 10 and 11 using three IO cards at base address 8800 9800 and A800 MS0 MI71 30C0A0218800 MACRO VO Software Settings 17 Accessory 68E READING AND WRITING TO NODE ADDRESSES Delta Tau recommends that you read and write to the node address as complete words If the node address is 24 bits wide or 16 bits wide read or write to the M Variable assigned to that address Example Ultralite TURBO Ultralite 970 gt 0 0 0 24 M970 gt X 78420 0 24 M980 gt X C0A 1 8 16 M980 gt X 78421 8 16 M981 gt X C0A2 8 16 M981 gt X 78422 8 16 M982 gt X C0A3 8 16 M982 gt X 78423 8 16 M1000 gt X 0770 0 24 M1000 gt X 0010F0 0 24 image word M1001 gt X 0771 8 16 M1001 gt X 0010F0 8 16 image word For Outputs M970 F00011 sets bits 0 4 20 21 22 amp 23 M980 8101 sets bits 0 8 amp 23 M970 M 1000 sets M970 equal to M1000 M980 M1001 sets M980 equal to M1001 For Input
36. onal I O accessories always define the inputs and outputs by hardware The register select bits allow you to define the input or output bytes inversion control or the latching input features Direction Control Bits Bits 0 to 5 ofthe control register simply control the direction of the I O for the matching numbered data register That is Bit n controls the direction of the I O at Base A value of 0 in the control bit the default permits a write operation to the data register enabling the output function for each line in the register Enabling the output function does not prevent the use of any or all of the lines as inputs as long as the outputs are off non conducting value of 1 in the control bit does not permit a write operation to the data register disabling the output reserving the register for inputs Example A value of 1 in Bit 3 disables the write function into the data register at address Base 3 ensuring that lines 1024 IO31 can always be used as inputs Register Select Control Bits Bits 6 and 7 of the control register together select which of 4 possible registers can be accessed at each of the addresses Base 0 through Base 5 They also select which of 2 possible registers can be selected at Base 6 The following table explains how these bits select registers Bit7 Bit6 Combined Value Base 0 to Base 5 Register Selected DataRegister 2 1 1
37. or more details about the JEXP please see the UBUS Specification Document D BS1 SEL BAG 3 0 1 1 1 1 1 1 1 1 1 8 3 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 9 0 195 MACRO VO Accessory Connectors 29 Accessory 68E VO Terminals TB1 12 Terminal Block pt Top View M Pin mo 1 2 02 is 05 m Input NOT 08 m NO Input This terminal block provides the inputs 1 12 for the ACC 68E I O Card TB2 Top 12 Pin Terminal Block Top View Pin Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking This terminal block provides the inputs 13 24 for the ACC 68E I O Card Symbol c 101 i li Mn BB Ww i This connector can be used to provide the input reference for the ACC 68E I O Card for the 24 inputs 30 MACRO VO Accessory Connectors Accessory 68E TB1 Bottom 12 Pin Terminal Block epee Top View Pin Notes Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking Sinking 12 Sinking This terminal block provide the inputs 1 12 for the ACC 68E I O Card ELI 10 eee TB2 Bottom 12 Pin Terminal Block 6 OUTI7 8 0019 9 0270 Output This t
38. resses The previous method supported the low middle high byte addressing of the Type A IO cards see Hardware Address Limitations section controls the data transfer period on a Compact MACRO Station between the MACRO node interface registers and the I O registers as specified by station MI variables MI20 through MI71 If is set to 0 this data transfer is disabled If MI19 is greater than 0 its value sets the period in Phase clock cycles the same as MACRO communications cycles at which the transfer is done MI975 permits the enabling of MACRO VO nodes the Compact MACRO Station MI975 is a 16 bit value bits 0 to 15 with bit n controlling the enabling of MACRO node n If the bit is set to 0 the node is disabled if the bit 15 set to 1 the node 15 enabled The I O nodes on the Compact MACRO Station are nodes 2 3 6 7 10 and 11 which be enabled by MI975 bits of these numbers Only bits 2 3 6 7 10 and 11 of MI975 should ever be set to 1 MI975 15 used at the power on reset of the Compact MACRO Station in combination with rotary switch SW 1 and 1976 to determine which MACRO nodes are to be enabled The net result can be read in Station variable MI996 To get a value of MI975 to take effect the value must be saved MSSAVE node and the Station reset MS node Example Set MI975 to enable nodes 2 and 3 MS0 1975 Set Number MACRO IO nodes to be enabled _ ps 14 13 12 11 10 98 7 6 5
39. s M1000 M970 sets M1000 equal to M970 M1001 M980 sets M1001 equal to M980 If using the 48 bit read write method it would be ideal if the inputs and outputs were used in multiples of 16 Example 48 inputs 32 inputs 16 outputs 16 inputs 32 outputs or 48 output see Example 2 If the 16 bit word is to be split 8 in and 8 out then we would read the word at the beginning of the PLC and write the word at the end of the PLC However instead of writing the value of the inputs to the output word you must write zeros to all input bits of this in out word This is because writing a value of 1 to a MACRO I O register makes that I O bit an output only bit The best method to ensure proper input reads is to write directly to the control word of the IO gate array to set the input words as read only see Setting Up Control Word for MACRO IO section Example Setup System Configuration 8 axis PWM System w 96 bit 1 0 48 inputs amp 48 outputs ACC 68E amp ACC 68E PMAC Ultralite Setup 1996 activates nodes 1 2 3 4 5 8 9 12 and 13 at Ultralite TURBO PMAC Ultralite Setup 16841 FB33F activates nodes 1 2 3 4 5 8 9 12 and 13 at Turbo Ultralite Macro Station Definitions MSO MI69 20C0A1318800 sets up macro to transfer data for IO cards MS0 MI975 C enable node 2 and 3 for VO 50 119 4 sets interrupt period for data transfer MSSAVEO save to macro station MS 0 reset macro station to enable
40. setting is ALL CLOSED position Hardware Setup Accessory 68E Jumpers Please refer to the layout diagram of ACC 68E for the location of the jumpers on the board E Point Jumpers Jumper Config Description Settings Default El 1 2 Turbo PMAC MACRO Jump 1 2 for Turbo 3U CPU and MACRO CPU 1 2 Select Jump 2 3 for legacy MACRO CPU before 6 00 E2 1 2 Sample Clock Select 1 2 servo clock 1 2 2 3 phase clock for legacy MACRO Stations part number 602804 100 thru 602804 104 Hardware Address Limitations Some of the older UMAC IO accessories might create a hardware address limitation relative to the newer series of UMAC high speed IO cards The ACC 66E would be considered a newer high speed IO card The new IO cards have four addresses per chip select CS10 CS12 CS14 and CS16 This enables these cards to have up to 16 different addresses The ACC 9E ACC 10 ACC 11E and ACC 12E all have one address per chip select but also have the low byte middle byte and high byte type of addressing scheme and allows for a maximum of twelve of these IO cards UMAC Card Types UMAC Number of Category Maximum Card CARD Addresses of cards Type ACC 9E ACC 10E 4 General IO 12 A 12 65 66 16 General IO 16 B ACC 67E ACC 68E 14 ACC 28E ACC 36E 16 ADC and DAC 16 B
41. sory 68E specifies the registers used in 24 bit I O transfers between MACRO I O node interface registers and I O registers on the MACRO Station I O accessory board It is used only if is greater than 0 Note The examples for the setup of MI71 require MACRO firmware 1 16 and above is a 48 bit variable represented as 12 hexadecimal digits The first 6 digits specify the number and address of 48 bit real time MACRO node register sets to be used The second 6 digits specify the number and address of 48 bit I O sets on the MACRO Station VO accessory board to be used The individual digits are specified as follows 1 0 1 2 3 Number of MACRO I O nodes to use times 2 0 disables this should also match the number of 48 bit I O sets you intend to use see Digit 7 COAO Node 2 COA4 Node 3 MACRO Station X Address of MACRO I O node first COAS Node 6 COAC Node 7 of three 16 bit registers COBO Node 10 COB4 Node 11 7 0 1 2 Number of 24 bit I O sets to use 1x24 2x24 0 disables 1 Set to 1 for 14 ACC 68E 66 67 consectutive address read Base 1000 2000 9 12 8800 8840 MACRO Station Y Base Address of ACC 14E ACC 8880 88CO 68E ACC 66E ACC 67E When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output
42. ssecececeesenssaeeseeseenseeaeeeees 8 Direction Control Bits ee 9 Register Select Control Bits ME RE RE OE 9 Control Word Setup Example 9 ACCESSORY 68E I O M VARIABLES FOR UMAC TURBO ee esse esse ee ee ee se een ee ee ee ee 11 MACRO STATION TRANSFER 22 o vo ru VN p Ges E 13 MACRO Station I O Node Transfer Addresses eee eene ener 13 2 Ultralite VO Node Addresses esee e ee eee nentes ener tete enses eese nenne 13 PMAC2 TURBO Ultralite VO Node Addresses ee ee ee ee ener enne nennen 14 MACRO VO SOFTWARE 15 READING AND WRITING TO NODE 585 8 2 4 oe ei se sese se Ge sese ense ee 18 Example shes 18 Example Setup RE N ACH xe Cd 18 Active Nodes for Compact MACRO I O Station example 19 PMAC2 ULTRALITE EXAMPLE M VARIABLE DEFINITIONS se se se ee ee ee ee ee ee ee nennen ee ee ee ee ee ee nns 20 PMAC2 TURBO ULTRALITE EXAMPLE M VARIABLE DEFINITIONS eise ees ee ee se ee ee ee ee ee ee ee ee ee ee ee ee ee 21 EXAMPLE 1 48 INPUTS 48 OUTPUTS USING 1x24 BIT TRANSFERS ese ee esse see se ee ee ee ee ee ee ee ee ee ee ee ee ee tenens 22 EXAMPLE 2 48 INPUTS 48 OUTPUTS USIN
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