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USER`S MANUAL

1. 1283 ASI TP 8 0 ANNUHI 100 2 0 513 2 1 lt 8511 1 Bing 6 0 953290 Qno 9 542 Schematic page 7 of 9 A 9 XVME 542 Manual SCHEMATIC 542 9 M 9 4 20MA DRIVER 4 20MA DRIVER 4 20MA DRIVER J29 B CHANNEL 5 J25 8 CHANNEL 7 CHANNELS 4 7 QUT CHANNEL 4 12 BIT DAC 8 A S ss 1 8 8 41 55 8 5 EN 5 5 t a 8 5 5 V V t 0008 2 48 5 9555 3 x 5 8 XVME 542 Schematic page 8 of 9 A 10 XVME 542 Manual SCHEMATIC 542 XUCOm ss DC DC POWER SPARES D 2 2 38 388 84888 PL 2 T 00 2 5228 f C 7 0 2 UUO 0000 0 Un ee w 0 T LJ m 8 x ES 0 3 p UC E z C gt gt 8 5 ES oe 2 a vt me ON ON gem MM ES 58 58 801 39 40 55 55 55 55 Ss 55 55 58 58 LON 0 LO CH 2 HI CH13 LO X lg x z so Sm
2. 3 A A RY REED RE Sc RR DS 3 aaa ES gt 28 2 5 2 2 5 898858 8 8 m 5 2 ES 5 T z e De De oL 22 c DA 9 DS eO gt zl rj ej x x aeeeaqss E Hae 555 Ogata i SERES i 2 n ied ag IDE OSSA 00000000 00000000 QO OOOQOO 9277909 pressesy Hance 2 tt 0 ng c 1 11 11 Eo og d og gd og d Exe EXE 7 256665 a cia 55555555 55555555 eee ee Seria Seams Sissi e oocooooo Coo coooo COO Oo OOo oco ooo e XVME 542 Schematic page 3 of 9 5 XVME 542 Manual 725428 001 5 XUME 542 x SADE 48126 6 CIMUXEN 0 7 NUT enl TT hp E Fa ob E 08855 8 8 wee 5 ME ac AME or D ANALOG INPUT MUXING CONTINUED 72770163636 3656 22 222 5 7557575 355555 7373737 55555555 Bes XVME 542 Schematic page 4 of 9 725428 001 SCHEMATIC 542 1 pu ith YC OM ss 129
3. SELECT THE NUMBER OF CHANNELS YOU WISH TO SCAN 8 16 32 64 AND WRITE THIS BYTE 2 BITS VALID WITH BIT 7 A 1 TO AUTOSCAN CONTROL REGISTER BASE 111H READ DATA 16 BITS FROM ANY SCANNED CHANNEL 0 63 IN REGISTERS BASE 200H BASE 27FH 3 3 542 Random Channel Mode Flow Chart In random channel mode a control byte written to the low byte of the gain channel register that specifies a channel automatically starts a conversion on that channel INITIALIZE BOARD SEE BOARD INITIALIZATION FLOW CHART SELECT RANDOM CHANNEL MODE BY WRITING 02H TO A D MODE REGISTER BASE 180H DETERMINE WHICH CHANNEL YOU WISH TO CONVERT ON 0 63 AND WRITE THIS BYTE 6 BITS VALID TO THE GAIN CHANNEL REGISTER LOW BASE 185H POLL OR BE INTERRUPTED ON END OF CONVERSION SEE END OF CONVERSION FLOW CHARTS READ A D REGISTER BASE 186H RECEIVE VALID DATA Chapter 3 Programming External Trigger Mode Flow Chart In external trigger mode the rising edge of a low going externally triggered pulse on pin 50 of JK 1 referenced to power ground pin 49 of JK1 J65IN initiates conversion Note J65 must be IN to use this mode See Chapter 2 for information on jumper settings 1 INITIALIZE BOARD 1 SEE BOARD INITIALIZATION FLOW CHART SELECT EXTERNAL TRIGGER MODE BY WRITING 03H TO A D MODE REGISTER BASE 180H DETERMINE WHICH CHANNEL YOU
4. 2 ae E 22 kd eie mm mm ale 4 44 SED rm om 328 ga OU UO OU UU gO 00 OU 09 OU UQ UU Q 3 0 05 60 55 38 Se FS 25 zo GB zm use D sa oan TT OTT WT Va Wa 8 8 8 8 8 88 8 MM EE EXE ro mE Mx lt lt Dx Lnd 25 88 RR 55 39 55 55 55 55 55 55 FP FP BB BB RB BB BB BB BB BB 1 XVME 542 Schematic page 9 of 9 Index A A D calibration potentiometers 4 1 A D conversion modes autoscanning 3 19 external trigger mode 3 19 programming gain 3 19 random channel 3 19 sequential channel 3 19 single channel 3 19 A D conversions 3 21 A D mode register 3 18 A D offset and gain adjustment 4 3 A D register 3 21 A D status control register 3 20 analog input features 1 1 specifications 1 3 analog output 3 8 features 1 1 specifications 1 4 analog to digital conversion options 2 4 input calibration grounding 2 6 input conversion format 2 4 input gain range options 2 5 input voltage 2 5 assembly drawing A 2 autoscan control register 3 17 autoscanning mode 3 19 B base addressing 3 10 bipolar offset adjustment 4 6 block diagram 1 2 A 1 board initialization 3 2 board overview 1 1 calibration 4 1 A D potentiometers 4 1 input 4 2 output 4 5 card cag
5. 22 277 4l fe ee 6 2 HH lin ee NENNEN 54 J55 2 356 6 2 STRAPPRBLE MULTIPLIER JUFER BLOCK 1 57 458 359 wa 4 90 C42 8 wv 2 v a La amp STAGE 2 OIFF MULT i GAIN RAM CHART STAGE 1 PROGRAMMABLE GAIN AMPLIFIER PROGRAMMABLE GAIN AMPLIFIER SECTION 2y 1 4 gt CETTE EE 888 5 05 Sg geom 2953 288 cen mp ng gt 2 2 eoume gt 5 lt 006 1 1 88 5 5 5 55 amp E XVME 542 Schematic 5 of 9 A 7 2 5 3 0 JILUN3H2S XVME 542 Manual JNAS QUO Sor 194303 9190 0 9 43125450 818057080 ASnB Qu C 21 4 0 N3XNWO 7 100994 H 0 0200 Q 851 538300 Q 44IQ NIS C CG 0 UW lt 11 0 08 5 1 1 1 XVME 542 Schematic 6 of 9 8 2bS 3WNX JILUW3H2S XVME 542 Manual R 2 4 zi 2 3l x JL 6 S 6 21001 B l3NNUHJ 061 y 103038 oret AGT or de GDOG 193433
6. gt 00 U D cg dn MALIS 25 lt 252 89 022 E son Bs 5 3 Be s 288 208 5 55 E amp eo e on a XVME 542 Manual ee 1 TN RCC mu E 08 SB amp E we Zo Xo i 5 085 4 18 0388 8 S 0 0000 QE 5 53 5 3 000 0 0 O 0000000 0 Q x E ek EN EN 8 es 83 w g Zo ZE 6g undi aon 88 o bebe dene w By iE 121 PRSS FRIL LED S BUS amp DRC CONTROL joja 2 25 PF VO 09 aj 10 Sal E 3 SA B m SCREEN Ble 2E EL B 0000 02 d 00000 8 zo 20202584 S EB 9 22 s 518648 Elali 5 5 85 mw x 8 D 5 Dan a woo a 4 XVME 542 Schematic page 2 of 9 XVME 542 Manual SCHEMATIC 542 8 2 i 2 x 8 1 T a EM 5 5 8 E 0 v Q 4648 3640 4648 4640 28771 INPUT CONFIGURATION 5 818 2 e 8 E N 5 2 M iiim g 5 gt c ie Sh Oye
7. Precision voltage source capable of supplying 1 22 mV 4 30 uV Inputs can be calibrated in either single ended or differential configuration Calibration begins by offset nulling the instrumentation amplifier with channel 0 selected and its inputs grounded Chapter 4 Calibration Programmable Gain Offset Adjustment Perform the following steps to adjust the programmable gain offset for single ended unipolar operation Remove any connectors at JK1 2 Ground input channel 0 by setting jumper J66 to B 3 Measure and record the output voltage of gain amp 039 pin 6 using the Fluke 8860 DMM 4 Next measure the voltage of gain amp U37 pin 6 Adjust R76 so the output voltage of U37 pin 6 matches the output voltage of U39 pin 6 6 Reset jumper J66 to A for the rest of the calibration A D Offset and Gain Adjustment With the previous networks nulled it is necessary to perform continuous conversion on channel 0 Channel 0 must be set for the lowest programmable gain G 1 bits 6 and 7 of the gain channel register must be set to 0 There are two types of input calibration zero 0 5 LSB and full scale FS 1 5 LSB Conversion results should be display on a CRT in hex format for verification Both must be performed on the XVME 542 as described below Zero Calibration The table below provides information necessary to perform a zero calibration 5 LSB Binary Voltage Analog Adjust POT Transition Encoding Mod
8. You can program each analog input channel gain for one of three ranges as shown below Jumper 1 2 5 10 4 8 20 40 10 20 50 100 Jumper Settings Input Gain Range 2 5 XVME 542 Manual Input Calibration Grounding Options Use jumpers J66 and J67 to ground channel 0 in single ended or differential mode for programmable gain offset adjustment Single ended Ground Differential Ground Jumper Settings Input Calibration Grounding If you do not want to ground channel 0 jumpers J66 and J67 should be set to A In external trigger mode set J65 IN to pick up digital ground for external trigger signals returned on top or bottom pin 49 If external trigger mode is not used remove J65 Digital to Analog Conversion Options 2 6 The XVME 542 offers six jumper configurable output configurations e 0 5V e 0 10 V e 25 e 45V e 10V 4 20 mA The table below indicates the jumper settings to achieve the desired configuration Jumper Settings D A Output Configurations continued Continued from previous page 3 5 Chapter 2 Installation Once you ve configured the module for unipolar or bipolar mode you can configure the D A format for complementary offset binary complementary straight binary COB or complementary two s complement CTC 1B 19 18 16 158 Jumper Settings D A Format 2 7 XVME 542 Manual
9. All Xycom XVME I O modules conform to the Xycom VMEbus Standard I O Architecture This architecture is intended to make the programming of all Xycom VMEbus I O modules simple and consistent The following features apply to the operation of the AIO module e Module Address Space All XVME modules are controlled by writing to addresses within the 64 Kbyte short I O address space or the upper 64 Kbyte FFXX XXh of VMEbus standard address space A module can be configured to occupy any one of 64 available 1 Kbyte blocks within the address space The 1 Kbyte block occupied by the module known as the I O interface block contains all of the module s programming registers module identification data and I O registers Within the I O interface block the address offsets are standardized so that users can find the same registers and data at the same address offsets across the entire Xycom XVME product line e Module Identification The AIO has ID information which provides the module name model number manufacturer and revision level information at a location that is consistent with other Xycom I O modules e Status Control Register This register is always located at address module base 81h and the lower two bits are standard from module to module Chapter 1 XVME 542 Overview Specifications Specifications for the XVME 542 are detailed in the following tables Characteristic Specification Number of channels Single ended 64
10. Even Odd Base 00h Undefined Module Identification Oth 3Eh 3Fh 40h Reserved 41h 7Eh 7Fh 1 Status Control Register 81h 82h Undefined 83h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h Reserved 99h E6h E7h Channels 0 7 EAh 1 100h 101h NM o 102h Programmable Timer Interrupt 103h Vector Register 21 1 108 109 110h 111h 112h 113h 180h 181h 1822h Endof Conversion Vector Register 183h 184h 185h 186h 187h 188h 189h 200h 201h 202h 203h 204h Channels 2 62 A D Scan Channels 2 62 A D Scan 205h 27Ch 27Dh 27Eh 27Fh XVME 542 Memory Map 3 11 542 Any location within the 5427 1 Kbyte I O interface block can be accessed by adding the module base address to the address of the specific location within the I O interface block referred to as the I O interface block offset For example the D A status control register is located at address 81h within the I O interface block If the module base address is set at 1000h then the status control register would be accessible at address 108 1h Module Base Interface Block D A Status Control Register Address Offset 1000h 0811 10818 For memory mapped CPU modules the short I O address space is memory mapped to begin at a specific address For such modules the I O interface block offset is an offset from the start of this memory mapped short I O a
11. iU Definition Channel 0 Vout NC Analog GND NC Channel Vout Analog GND Channel 2 Vout NC Analog GND NC Channel 3 Vout Channel 0 IOU Channel 0 IOU Channel IOU Channel IOU Channel 2 IOU Channel 2 IOU Channel 3 Channel 3 IOU Dual Connector 2nd Half Pin Definition Channel 4 Vout NC Analog GND NC Channel 5 Vout Analog GND Channel 6 Vout NC Analog GND NC Channel 7 Vout Channel 4 IOU Channel 4 IOU Channel 5 IOU Channel 5 IOU Channel 6 IOU Channel 6 IOU Channel 7 IOU Channel 7 IOU Chapter 2 Installation Card Cage Installation Caution Do not attempt to install or remove any boards without first turning off power to the bus and all related external power supplies Prior to installing a module determine and verify all relevant jumper configurations Check the jumper configuration with the diagram and lists in the manual Xycom VMEbus modules can accommodate typical VMEbus backplane construction The following illustration depicts a standard VMEbus chassis and a typical backplane configuration There two rows of backplane connectors depicted the and the P2 backplane RESOURCE GUIDE SLOT SOLDER SIDE Musto CPU P1 BACKPLANE COMPONENT SIDE AX Siri TM a Ta 2 2 ST MUU B
12. upon which of the six A D modes the board is operating 1 Conversion initiated 0 No conversion initiated Reserved This bit is used to perform an analog input section software reset A software reset stops a conversion in process and clears any end of conversion interrupts It also clears the interrupt pending flag bit 2 resets the gain channel register base 184h and disables scanning by clearing the scan control bit bit 7 of base 11 1h 1 Starts the software reset process 0 Stops the reset When the associated jumpers and switches are set this bit generates end of A D conversion VMEbus interrupts 1 Enables end of A D conversion VMEbus interrupts 0 Disables end of A D conversion VMEbus interrupts This bit is an interrupt pending flag 1 0 To clear this bit you must cause a new A D conversion perform backplane or software reset read the converted input data from the low order data byte or select autoscanning mode End of conversion has occurred End of conversion has not occurred Bits 1 0 LSB Reserved End of Conversion Vector Register base 183h 3 20 This register stores the vector used for end of A D conversion interrupts Chapter 3 Programming A D Gain Channel Register base 184h This 16 bit register initiates A D conversions when you write the desired channel to the lower byte while in random channel mode This register is also used to program a gain factor for input
13. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Single Ended Configuration Channel 24 Analog GND Channel 25 Channel 17 Analog GND Channel 18 Channel 26 Analog GND Channel 27 Channel 19 Analog GND Channel 20 Channel 28 Analog GND Channel 29 Channel 21 Analog GND Channel 22 Channel 30 Analog GND Channel 31 Channel 23 Analog GND Power GND External trigger Differential Configuration Channel 8 high Analog GND Channel 9 high Channel 9 low Analog GND Channel 10 low Channel 10 high Analog GND Channel 11 high Channel 11 low Analog GND Channel 12 low Channel 12 high Analog GND Channel 13 high Channel 13 low Analog GND Channel 14 low Channel 14 high Analog GND Channel 15 high Channel 15 low Analog GND Power GND External trigger JKI Pinouts continued from previous page top 50 pin connector DN gt re TO 0 Nn 8 Single Ended Configuration Channel 32 Channel 40 Analog GND Channel 41 Channel 33 Analog GND Channel 34 Channel 42 Analog GND Channel 43 Channel 35 Analog GND Channel 36 Channel 44 Analog GND Channel 45 Channel 37 Analog GND Channel 38 Channel 46 Analog GND Channel 47 Channel 39 Analog GND Channel 48 Differential Configuration Channel 16 low Channel 16 high Analog GND Channel 17 high Channel 17 lo
14. Differential 32 Pseudo differential 64 Accuracy Resolution 16 bits Single channel mode 003 FSR All other modes 006 FSR Speed Conversion time 16 bits Settling time Throughput Single channel mode Autoscanning mode All other modes A D full scale voltage ranges G 1 Unipolar 0 5 V 0 10 V Bipolar 5 V 10 Programmable Gain Range 1 1 2 5 or 10 Range 2 4 8 20 or 40 Range 3 10 20 50 or 100 Maximum input voltage Power on 44 Power off 30 V Power requirements Voltage outputs 5 V 5 1 8 A typical with voltage outputs at full scale Current Outputs 5 V 5 2 75 A typical with current outputs at full scale Analog Input Specifications XVME 542 Manual Characteristic Specification Number of channels Bo Accuracy Resolution Overall error Differential linearity Voltage output characteristics Ranges Settling time Output current Offset temperature coefficient Gain temperature coefficient Current Loop Characteristics Range Compliance voltage Settling time Load resistance range Offset temperature coefficient Gain temperature coefficient 0 5 V 0 10 V 2 5 V 4 usec 5 mA maximum 10 ppm C 20 ppm C 4 20 mA non isolated 2 min 10 5 max 80 usec 50 525 ohms 30 ppm C 50 ppm C Digital Input Coding OBN CTC Analog Output Specifications Chapter 1 XVME 542 Overview Characteristic Specification Temperature Oper
15. External Connectors The XVME 542 uses standard VMEbus connectors for P1 and P2 96 pin DIN P2 is Jumper resets the DAC When is set the four digital to analog converters are loaded with Os at reset or power up When J4B is set they are loaded with Is used for extra 5 V and GND connections only JK1 Connector A dual 50 pin ribbon connector with latches containing 100 pins is used for the analog input section Pinouts are shown in the following tables JKI Pinouts bottom 50 pin connector gt N PWN RK 0 Ut Single Ended Configuration Channel 0 Channel 8 Analog GND Channel 9 Channel 1 Analog GND Channel 2 Channel 10 Analog GND Channel 11 Channel 3 Analog GND Channel 4 Channel 12 Analog GND Channel 13 Channel 5 Analog GND Channel 6 Channel 14 Analog GND Channel 15 Channel 7 Analog GND Channel 16 Channel 0 low Channel 0 high Analog GND Channel 1 high Channel 1 low Analog GND Channel 2 low Channel 2 high Analog GND Channel 3 high Channel 3 low Analog GND Channel 4 low Channel 4 high Analog GND Channel 5 high Channel 5 low Analog GND Channel 6 low Channel 6 high Analog GND Channel 7 high Channel 7 low Analog GND Channel 8 low Pinouts continued on following page Differential Configuration 26 27 28 29 30 31 32 33
16. bipolar 4 6 unipolar 4 5 operational diagram 1 2 output calibration 4 5 pinouts bottom 2 8 top 2 9 JK2 2 10 potentiometers A D calibration 4 1 locations on board 2 2 programmable gain offset adjustment 4 3 programmable timer interrupt vector register 3 17 programming gain mode 3 19 R random channel mode 3 19 registers A D gain channel 3 21 A D mode 3 18 A D scan 3 21 A D status control 3 20 autoscan control 3 17 D A channel 3 15 D A update 3 16 D A status control 3 14 end of conversion vector 3 20 interrupt timer 3 16 programmable timer interrupt vector 3 17 requirements system 2 1 5 schematics A 3 settings jumper 2 4 switch 2 3 sequential channel mode 3 7 3 19 single channel mode 3 6 3 19 S continued single ended input options 2 5 specifications analog input 1 3 analog output 1 4 environmental 1 5 standard I O architecture 1 2 switches interrupt level select 2 4 locations on board 2 2 settings 2 3 SW 1 2 3 SYSFAIL 2 4 system requirements 2 1 U unipolar offset adjustment 4 5 V VMEbus chassis 2 11 voltage input options 2 5 2 zero calibration 4 3
17. channels by writing to the higher byte while in programming gain mode Use bits 8 and 9 to first select the gain as shown in the table below Gain Channel Register Jumper Selected Gain Bit 9 Bit 8 Range 1 Range 2 Range 3 Ug qm s m 1 7 2 110 7 0 109 Once the gain has been selected write to the lower byte with the desired channel to program Writing to the lower byte programs the gain for that channel You may also write a word at a time to simultaneously select the gain and the desired channel to program A D Scan Registers base 200h 3FEh While in autoscanning mode these registers are used to store A D readings Each register keeps an updated reading of the specified channel A D Conversions Following are some general steps for configuring the XVME 542 to convert analog inputs to digital data 1 Configure jumpers and switches refer to Chapter 2 for the desired interrupt level input type differential single ended or pseudo differential and bipolar or unipolar input voltage range input gain range and input binary data format 2 Program the gain RAM by setting programming gain mode then writing to the gain channel register base 184h 3 Perform calibration see Chapter 4 4 Select one of the five A D conversion modes by writing to the A D mode register base 180h 5 Initiate the A D conversion process 3 21 Chapter 4 Calibration Calibration facilities have b
18. 000004544 3 20 A D Gain Channel Register base 184 2 3 21 A D Scan Gain Registers base 200h 3 21 A D E 3 21 XVME 542 Manual Chapter 4 ceri 441 Input Calibration iss eee e Het ene I 4 2 Programmable Gain Offset eene ennemis 4 3 A D Offset and Gain Adjustment sss enne enne nnne trennen 4 3 Output Calibration etie ie Sad AE aA ni GN RII nee e SP VIN Re UR 4 5 Unipolar Offset Adjustment oes Rae e eet s as d idi 4 5 Bipolar Offset 4 6 Appendix Schematics and 4222220 1 Chapter 1 XVME 542 Overview Product Features The 542 is a powerful VMEbus compatible analog input output AIO module It is capable of performing analog to digital A D conversions with a 16 bit resolution and digital to analog D A conversions with a 12 bit resolution The module can be configured to provide 64 single ended 32 differential or 64 pseudo differential analog input channels with three ranges of programmable gain and six modes of operati
19. Acromag 9 THE LEADER IN INDUSTRIAL 1 XVME 542 6U 64 32 Channel Analog Input 8 Channel Analog Output Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 974B Xycom Revision Record Revision Description A Manual Released B Manual Updated RADIO 98105 Trademark Information Brand or product names are registered trademarks of their respective owners Windows is a registered trademark of Microsoft Corp in the United States and other countries Copyright Information This document is copyrighted by Xycom Incorporated Xycom and shall not be reproduced or copied without expressed written authorization from Xycom The information contained within this document is subject to change without notice Xycom does not guarantee the accuracy of the information and makes no commitment to keeping it up to date xycom Technical Publication Department 750 North Maple Road Saline MI 48176 1292 313 429 4971 313 429 1010 fax Table of Contents Chapter 1 XVME 542 Overview 1 1 Product Features esie Cg Or e rp OE Deen d 1 1 Operational Description ede e ec ie etie eic eee ier eee ipei k 1 2 Xycom Standard I O Arc
20. Adjust the corresponding gain potentiometer until the output is 1 LSB less than the nominal full scale 4 5 XVME 542 Manual Steps 2 3 and 5 may also be executed with the channels configured for current output In this case the channel offset potentiometer is adjusted for an output of 4 mA or 1 000 V 30 across a 250 Ohm 0 1 resistor returned to ground on connector JK2 and the gain potentiometer should be adjusted for an output of 20 mA or 5 000 V Note Make certain that the resistor used does not change value due to self heating Bipolar Offset Adjustment Perform the following steps for bipolar offset adjustment 1 Set jumpers to the desired bipolar range 2 Turn all bits off load binary zeros to the output channel being calibrated 3 Adjust the bipolar potentiometer that corresponds to the channel being calibrated until the output reads FS 2 5 5 0 10 0 4 Turn all bits on load FFFh to the output channel being calibrated Adjust the gain potentiometer until the output reads 1 LSB less than FS 225 V 100 V 4 6 Appendix Schematics and Diagrams Channels 0 3 Out Channels 4 7 Out Channels 0 31 In Channels 32 63 In Multiplexers Input Gain Prog Gain Ram Ctrl Sampling A D Serial Shift Register 1 Autosca Conversion and mode Control Logic Sa is ets a ge sat AE tsa a Ram X
21. OARD BN GUIDE SLOT P2 BACKPLANE VMEbus Chassis 2 11 XVME 542 Manual Perform the following steps to install a board in the card cage 1 Make sure the card cage slot that you are going to use is clear and accessible 2 Center the board on the plastic guides in the slot so that the handle on the front panel is toward the bottom of the card cage 3 Push the card slowly toward the rear of the chassis until the connectors are fully engaged and properly seated Note It should not be necessary to use excess force to engage the connectors If the board does not properly connect with the backplane remove the module and inspect all connectors and guide slots for possible damage or obstructions 4 Once the board is properly seated tighten the two machine screws at the top and bottom of the front panel 2 12 Chapter 3 Programming This chapter provides the information required to program the XVME 542 for analog input and output signal conversions This information includes the following e Flow charts providing quick start information e Module address map showing programming locations e Base addressing and the module I O interface block A D conversion modes e D A conversion principles Flow Charts The following flow charts provide information on initializing the XVME 542 board using A D conversion modes and analog outputs and detecting the end of a conversion The flow charts assume that hardw
22. TED Chapter 3 Programming End of Conversion Flow Charts 1 Polling method START IS BIT 7 OF A D STATUS CONTROL REGISTER BASE 181H SET CONVERSION IN PROCESS CONTINUE 2 Interrupt vector method START END OF CONVERSION CAUSES 542 564 TO INTERRUPT THE VMEbus AND PROVIDE INTER RUPT VECTOR CORRESPONDING TO USERS 542 564 INTERRUPT SERVICE ROUTINE ISR ISR RUNS CONTINUE NOTE INTERRUPT VECTOR MUST BE LOADED AND INTERRUPTS ENABLED SEE BOARD INITIALIZATION FLOW CHART 542 Module Base Addressing 3 10 The 542 is designed to be addressed within either the VMEbus defined 64 Kbyte short I O address space or the upper 64 Kbytes of the standard address space FF0000h FFFC00h Because each I O module connected to the bus must have a unique base address the addressing scheme for Xycom XVME I O modules is configurable When the XVME 542 is installed in a system it will occupy a 1 Kbyte block of address space also referred to as the I O block The base address decoding scheme for the XVME 542 positions the starting address of each board on a 1 Kbyte boundary Thus there are 64 possible base addresses 1 Kbyte boundaries for the XVME 542 within either the short I O address space or the upper 64 Kbytes of standard address space Refer to Chapter 2 for a list of base addresses and their corresponding SW 1 bit locations Chapter 3 Programming
23. TIALIZE BOARD SEE BOARD INITIALIZATION FLOW CHART SELECT SEQUENTIAL BASE 180H YOU WISH TO START CONVERSION ON 0 63 AND WRITE THIS BYTE 6 BITS VALID TO THE GAIN CHANNEL REGISTER LOW BASE 185H READ A D REGISTER BASE 186H TO INITIATE A CONVERSION NOTE FIRST READ WILL NOT HAVE VALID DATA POLL OR BE INTERRUPTED ON END OF CONVERSION SEE END OF CONVERSION FLOW CHARTS READ A D REGISTER BASE 186 TO RECEIVE VALID DATA AND START A CONVERSION ON NEXT CHANNEL CHANNEL MODE BY WRITING 1 A D MODE REGISTER DETERMINE WHICH CHANNEL CHANNEL NUMBER IS AUTOMATICALLY INCREMENTED N N 1 3 7 542 Analog Output Flow Chart 3 8 START TOGGLE BIT 4 OF D A STATUS CONTROL REGISTER BASE 81H TO RESET OUTPUTS DO YOU REQUIRE SIMUL TANEOUS UPDATE OF ANALOG OUTPUTS YES RESET BIT 5 IN D A STATUS SET BIT 5 IN D A STATUS CONTROL REGISTER CONTROL REGISTER BASE 81H TO ENABLE BASE 81H TO ENABLE TRANSPARENT MODE SIMULTANEOUS UPDATE MODE WRITE DATA 12 BITS VALID TO CHANNEL 0 7 REGISTERS BASE 88H BASE 97H WRITE DATA 12 BITS VALID TO CHANNEL 0 7 REGISTERS BASE 88H BASE 97H WRITE A BYTE TO D A UPDATE REGISTER BASE WITH BITS SET CORRESPONDING TO CHANNELS THAT ARE TO BE SIMULTANEOUSLY UPDA
24. WISH TO CONVERT ON IN RESPONSE TO EXTERNAL TRIGGER 0 63 AND WRITE THIS BYTE 6 BITS VALID TO THE GAIN CHANNEL REGISTER LOW BASE 185 EXTERNAL TRIGGER OCCURS POLL OR BE INTERRUPTED ON END OF CONVERSION SEE END OF CONVERSION FLOW CHARTS READ A D REGISTER BASE 186H TO RECEIVE VALID DATA REPEAT 3 5 542 Single Channel Mode Flow Chart In single channel mode the module automatically starts another conversion on the specified channel after the low order A D register base 187h has been read 3 6 INITIALIZE BOARD SEE BOARD INITIALIZATION FLOW CHART SELECT SINGLE CHANNEL MODE BY WRITING 00H TO A D MODE REGISTER 180H DETERMINE WHICH CHANNEL YOU WISH TO CONVERT ON 0 63 AND WRITE THIS BYTE 6 BITS VALID TO THE GAIN CHANNEL REGISTER LOW BASE 185H READ A D REGISTER BASE 186H TO INITIATE A CONVERSION NOTE FIRST READ WILL NOT HAVE VALID DATA POLL OR BE INTERRUPTED ON END OF CONVERSION SEE END OF CONVERSION FLOW CHARTS READ A D REGISTER BASE 186H TO RECEIVE VALID DATA AND START ANOTHER CONVERSION ON SAME CHANNEL Sequential Channel Mode Flow Chart Chapter 3 Programming In sequential channel mode the module automatically increments the channel number by one and initiates a conversion on the next channel previous channel 1 after the low byte A D register base 187h has been read 1 INI
25. ank if single digit Minor functional revision level with trailing blank if single digit Manufacturer dependent Reserved information reserved for Reserved future use Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Identification Data The module has been designed so that it is only necessary to use odd backplane addresses to access the ID data Thus each of the 32 bytes of ASCII data have been assigned to the first 32 odd I O interface block bytes that is odd bytes 1h 3Fh ID information can be accessed by addressing the module base offset by the specific address for the character s needed For example if the base address of the board is jumpered to 1000h and if you wish to access the module model number 1 interface block locations 11h 13h 15h 17h 19h 1Bh and 1Dh individually add the offset addresses to the base addresses to read the hex encoded ASCII value at each location Thus in this example the ASCII values that make up the module model number are found sequentially at locations 1011h 1013h 1015h 1017h 1019h 101Bh and 101Dh 3 13 542 D A Status Control Register base 81h This 8 bit register is used to e Select the operating mode for the D A channels e Reset the module e Control the red and green LEDs used on the module Below is a description of the bits in this register Bit 7 MSB Reserved Bit 6 Reserved Bi
26. are jumpers have been set See Chapter 2 for information on setting jumpers Note Register information begins on page 3 14 3 1 542 Board Initialization Flow Chart This flow chart describes the steps necessary to initialize the XVME 542 START TOGGLE BIT 4 OF A D STATUS CONTROL REGISTER BASE 181H TO RESET A D CONVERTER WILL YOU BE USING END OF CONVERSION INTERRUPTS WRITE INTERRUPT VECTOR 8 BITS TO EOC VECTOR REGISTER BASE 183H ENABLE INTERRUPTS BY SETTING BIT 3 OF A D STATUS CONTROL REGISTER BASE 181H SELECT PROGRAMMING GAIN MODE BY WRITING 05H TO A D MODE REGISTER BASE 180 WRITE DESIRED GAIN TO GAIN CHANNEL REGISTER LOW BASE 184H SELECT CHANNEL BY WRITING CHANNEL NUMBER TO GAIN CHANNEL REGISTER HIGH BASE 185H ARE ALL CHANNEL GAINS PROGRAMMED CONTINUE End of conversion interrupts will not work if board is used in autoscanning mode Chapter 3 Programming Autoscanning Mode Flow Chart In autoscanning mode continuous conversions are performed on 8 16 32 or 64 channels and the results of each channel are stored in 16 bit registers starting at offset base 200h for channel 0 to base 27Fh for channel 63 I INITIALIZE BOARD SEE BOARD INITIALIZATION FLOW CHART SELECT AUTOSCANNING MODE BY WRITING 04H TO A D MODE REGISTER BASE 180H
27. ate up to 8 D A channels simultaneously when the D A status control register is set to simultaneous mode bit 5 is set to 1 Writing to the D A channel latches the data into the D A data register To update the D A channel s output you must write a 1 to the channel update register s corresponding to the D A channel register s you want to update This starts the conversion process This register is cleared on power SYSRESET or a D A software reset For example if you specify bipolar unsigned straight binary mode with a jumper selected output voltage range of 10 and you want to set channel 0 to 10 V channel 3 to 0 V and channel 7 to 10 V perform the following steps 1 Set bit 5 in the D A status control register base 81h to 1 This selects simultaneous update mode Write 0000h to the channel 0 D A registers base 881 891 Write 800h to the channel 3 D A registers 8Eh 8Fh Write OFFFh to the channel 7 D A registers base 96h 97h To update the outputs of channels 0 3 and 7 write base 89h to register base E9h This byte has a bit pattern corresponding to the channels to be updated Channel 0 will then update to 10 V channel 3 will update to 0 V and channel 7 will update to 10 V UE IP Interrupt Timer Register base 101h The 8 bit interrupt timer register generates VMEbus interrupts with configurable delay times It has the following bit definitions Bit 7 MSB Depending on jumpe
28. ating 0 to 65 C 32 to 149 F Non operating 40 to 85 C 40 to 185 F Altitude Operating Sea level to 10 000 ft 3048 m Non operating Sea level to 50 000 ft 15240 m Vibration Operating 5 to 2000 Hz 015 peak to peak displacement 2 5 g acceleration maximum Non operating 5 to 2000 Hz 030 peak to peak displacement 5 0 g acceleration maximum Shock Operating 30 g peak acceleration 11 msec duration Non operating 50 g peak acceleration 11 msec duration VMEbus Compliance A24 16 D16 DTB slave AM CODES 29 2D 39 3D BGXIN hardwired to BGXOUT Conforms to Xycom Standard I O Architecture I 1 7 STAT Programmable Vector Environmental Specifications Chapter 2 Installation System Requirements To operate correctly the XVME 542 AIO must be properly installed in a VMEbus backplane Following are the minimum system requirements for module operation e host processor installed in the same backplane and a properly installed controller subsystem or e host processor module that incorporates an on board controller subsystem Relevant Components Prior to installing the analog input output module you must configure several jumper switch options The configuration of the jumpers and switches is dependent upon which of the module operational capabilities are required for a given application The switches are used to set VMEbus related options The jumper options can be divided into three categories e VME
29. bus related options e Analog to digital conversion options Digital to analog conversion options The figure on the following page illustrates the jumpers switches connectors and potentiometers located on the XVME 542 2 1 XVME 542 Manual 581 XVME 542 Jumpers Switches Connectors and Potentiometers Chapter 2 Installation Switch Settings The XVME 542 has two switches an eight position addressing switch and a three position interrupt level select switch Switch SW 1 Addressing switch SW 1 is used to e Select the address on a 1 Kbyte boundary in the VMEbus short I O or FEXXXXh in the VMEbus standard address space e Select supervisory only or both supervisory and non privileged accesses e Choose between the short I O or FEXXXXh in the standard address space The table below describes the switch bits and their functions Setting Address bit A10 Open Closed Address bit 11 Open Closed Address bit A12 Open Closed 5 Address bit 13 Open Closed Address bit A15 Open Closed Supervisory non Open supervisory privileged Closed supervisory amp non privileged Standard short I O Open standard access Closed short I O access Switch SW 1 Bit Settings Address bit 14 Open Closed 2 3 542 Interrupt Level Select Switch SW 2 This three position switch selects which VMEbus interrupt level the XVME 542 uses to generate a periodic inte
30. ddress space For example if the short address space of a CPU module starts at F90000h and if the base address of the AIO is set at 1000h the actual module base address would be F91000h Interface Block This section describes the programming locations in the XVME 542 I O interface block Note Reading from or writing to undefined I O interface block locations may make application software incompatible with future XVME modules Module Identification Data The Xycom module identification scheme provides a unique method of registering module specific information in an ASCII encoded format ID data is provided as 32 ASCII encoded characters consisting of the board type manufacturer identification module model number number of 1 Kbyte blocks occupied by the module and module functional revision level This information can be read by the system processor on power up to verify the system configuration and operational status The table on the following page defines the identification information locations 3 12 Chapter 3 Programming Offset Relative to Contents ASCII Encoding Description a Module Base ID PROM identifier always VMEID five characters Manufacturer s ID always XYC for Xycom modules three characters Module Model Number three characters four trailing blanks Number of 1 Kbyte blocks of I O space occupied by this module one character Major functional revision level with leading bl
31. de In single channel mode the module automatically starts another conversion on the specified channel after the low byte of the A D register base 187h has been read An added feature of the single channel mode is that it offers faster conversions than the other modes 10 usec as opposed to 26 usec in sequential random channel and external trigger modes and 18 usec autoscanning mode Sequential Channel Mode In sequential channel mode the module automatically increments the channel number by one and initiates a conversion on the next channel previous channel 1 after the low byte of the A D register base 187h has been read You can force a conversion in this mode without incrementing the channel number by writing a 1 to bit 7 of the status control register base 181h Random Channel Mode In random channel mode a control byte written to the low byte of the gain channel register base 184h that specifies a channel number automatically starts a conversion on the specified channel External Trigger Mode External trigger mode allows the rising edge of a low going externally triggered pulse on pin 50 of JK 1 referenced to power ground pin 49 of JK1 J65IN to initiate a conversion Autoscanning Mode Autoscanning mode performs continuous conversions on 8 16 32 or 64 channels and stores the results of each channel in its own 16 bit register starting at offset base 200h for channel 0 to base 27Fh for chan
32. e Range Voltage In Points Unipolar 0 5 V 04 mV 0000h 0001h straight binary 0 10 V 08 mV 0000h 0001h R69 R69 Bipolar 4 R69 8000h 8001h offset binary 69 8000h 8001h R69 8000h 8001h Bipolar R69 0000h 0001h two s 69 0000h 0001h complement 69 0000h 0001h A D Zero Calibration Points To perform a zero calibration 1 Apply the 5 LSB analog voltage in for binary encoding mode and the voltage range chosen to channel 0 2 Adjust the zero calibration and the POT until the display reading toggles between the zero calibration and transition point values 4 3 XVME 542 Manual For example t o perform a zero calibration on an XVME 542 configured for bipolar offset binary 10 V range operation e Apply 15 mV to channel 0 Adjust R69 until the display reading toggles between 0000h and 0001h Full Scale Calibration The table below provides information necessary to perform a full scale calibration FS 1 5 LSB Encoding Mode Range Voltage In Points 0 5 4 99988 70 FFFEh FFFFh straight binary 0 10 V 9 99977 V 70 FFFEh FFFFh Unipolar Bipolar Bipolar two s complement R R 4 2 49988 V R70 FFFEh FFFFh offset binary 4 99977 V R FFFEh FFFFh 9 99954 V R FFFEh FFFFh R 4 R 70 70 2 49988 V 70 7FFEh 7FFFh 4 99977 V 70 7FFEh 7FFFh 9 99954 V R70 7FFEh 7FFFh A D Full Scale Calibration Points To perform a full scale calibration 1 Apply
33. e installation 2 11 chassis VMEbus 2 11 connectors external 2 8 JK1 2 8 JK2 2 10 locations on board 2 2 conversions A D 3 21 D D A channel registers 3 15 D A channel update registers 3 16 D A format 2 7 D A status control register 3 14 differential input options digital to analog conversion options 2 6 E end of conversion 3 9 end of conversion vector register 3 20 external trigger mode 3 19 environmental specifications 1 5 external connectors 2 8 F features analog input 1 1 analog output 1 1 flow charts analog outputs 3 8 board initialization 3 2 end of conversion 3 9 sequential channel mode 3 7 single channel mode 3 6 full scale calibration 4 4 H host processor 2 1 T O interface block 3 12 input calibration 4 2 input calibration grounding options 2 6 input conversion format options 2 4 input gain range options 2 5 input voltage options 2 5 installation into card cage 2 11 interrupt timer register 3 16 J jumpers locations on board 2 2 settings input channels 2 5 input voltage 2 5 input gain range 2 5 input calibration grounding 2 6 D A output configuration 2 6 542 memory map 3 11 modes autoscanning 3 19 external trigger mode 3 19 programming gain 3 19 random channel 3 19 sequential channel 3 19 single channel 3 19 module base addressing 3 10 module identification data 3 12 offset adjustment
34. een provided on the AIO module for both analog input and analog output circuits The module is calibrated in the 10 V A D input voltage range and the 0 10 V D A output voltage range before it leaves the factory However if the module is configured to operate in ranges other than these it is recommended that the calibration be checked and adjusted As a general rule the input output circuitry should be recalibrated whenever voltage range jumpers and voltage current select jumpers are changed Type of Adjustment R69 Offset for A D convertor a R76 Programmable gain amp offset A D Calibration Potentiometers The calibration procedure is divided into two parts input circuit calibration and output circuit calibration Input circuit calibration entails offset nulling the instrumentation amplifier and offset adjusting and gain adjusting the A D converter Output calibration entails offset and gain adjustment for each output channel in either unipolar or bipolar modes 4 1 XVME 542 Manual The table below defines the potentiometers for both A D and D A calibrations Resistor Number Type of Adjustment RIO R26 R33 R40 R45 R52 R57 R64 R20 R27 R34 R41 R46 R53 R58 R65 R21 R28 R35 R42 R47 R54 R59 R66 Calibration Potentiometers Input Calibration You will need the following equipment to perform an input calibration Five digit volt meter capable of reading 30 Small flat bladed screw driver
35. hart eene enne enne ener 3 2 Autoscanning Mode Flow Chart ener enne entren nennen 3 3 Random Channel Mode Flow ete detecte HIR Sb dte eects 3 4 External Trigger Mode Flow Chart case em e ec 3 5 Single Channel Mode Flow Chart sese ener enne 3 6 Sequential Channel Mode Flow Chart sese enne nennen enne 3 7 Analog Output Flow Chatter eid Ri eti 3 8 End of Conversion Flow Charts rre D te ep e e Rin 3 9 Module Base Addressing e eR a a 3 10 Blocks 3 12 Module Identification sedet RADI 3 12 D A Status Control Register 81h cenieni iniri iiie s RE TERE 3 14 D A Channel Registers base 88 97 1 27 111000000000000000000000000000000000000000000000004 4 3 15 D A Update Register Channels 0 7 base E9h sss enne nnns 3 16 Interrupt Timer Register base F TOTB eee cte iie He ie A 3 16 Programmable Timer Interrupt Vector Register base 103h sss 3 17 Autoscan Control Register base 111 ener 3 17 A D Mode Register 1806 enne enne 3 18 A D Status Control Register base t 181Th ace 3 20 End of Conversion Vector Register base 183 01 0 014 000000000000000000000000000000
36. he red LED turns on The power up or reset state for status bits is 00 D A Channel Registers base 88h 97h Each output channel 8 total has its own word address starting at locations 88h and 89h for channel 0 and ending at locations 96h and 97h for channel 7 Each channel can be written as a byte or word The even byte contains data bits 8 11 and the odd byte contains data bits 0 7 The D A converters are double buffered which means the DAC register can be written to without affecting the output of the D A converter When you write to a D A channel both RAM and the actual DAC register gets written During a read only the RAM is read Since the D A RAMs used for reading DAC registers power up with unknown data they must be initialized before they can be read correctly This is also true for any reset conditions or a software reset since the RAM data remains the same after the reset while the DAC registers are reset Note When reading a D A channel the information read contains the data in the D A register and not necessarily the actual output of the D A channel 3 15 XVME 542 Manual D A Update Register Channels 0 7 base Note When the module is in transparent mode update registers serve no purpose In this mode individual channels are updated with a write to the lower byte of the D A channel and only the channel written to is updated The D A channel update registers upd
37. hitecture cccesccesccsseesseeseeeseeeeceeseesecesecesececseecesecaecaecsaecaeesaeeeaeeeeeseeeseresreneeeeenaees 1 2 Specifications d stie eei o edi It menie iii teh ote ata e Rs 1 3 Chapter 2 Installation cecinere cree tenete tuned ue eta na eL Rund unc 2 1 a RR RAT DR ee 2 1 Relevant Components 5 nee eec ae e RU RET Ue teeta re e ree TREES 2 1 SWitch Settings esto reet tate e i e As 2 3 SW TEC eser I S LEO ILU LL cant LT Re 2 3 Interrupt Level Select Swatch SW 2 xxt ne fee tie t Rt bd ie ORE e SERIE URS 2 4 Jumper Settings ree tede ede eere ee tee e ce re a eee 2 4 SYSEAIUT c o FEE ER ore noe par ue Tee eR DR EE PRESE 2 4 Analog to Digital Conversion nennen rennen 2 4 Digital to Analog Conversion Options sess 2 6 External Connectors ccs deiecti b ro TER b ERO D e i eT E rp Heo a n e ener dde 2 8 IK T Connector ig P at a DE b EO E REO MORE 2 8 2 10 Gard Cage Installation te Ra CHR Re Ride det etie 2 11 Chapter 3 Programming eter nerunt 3 1 Flow Charts c read e ego gere on rq engan ripe ie 3 1 Board Initialization Flow C
38. nel 63 When autoscanning mode is selected and bit 7 of the autoscan control register is set to 1 conversions are initiated and stored End of A D conversion interrupts cannot be used with this mode and will not generate interrupts However the programmable interrupt timer is available Programming Gain Mode After power up or system reset use this mode to initialize the XVME 542 s on board gain RAM to provide each input channel with an associated gain factor from the jumper selectable range set at installation Once an input channel is initialized the associated gain factor is automatically applied when an A D conversion occurs on that channel To program the gain RAM first select programming gain mode Once this mode is set you can write the gain for each channel to the high byte of the gain channel register base 184h Refer to the A D Gain Channel Register section later in this chapter for more information on programming the gain RAM 3 19 XVME 542 Manual A D Status Control Register base 181h This 8 bit register is used to monitor the status of A D channels enable and disable interrupts and reset the module The bits in this register are defined below Bit 7 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 This bit acts as a busy flag to show when an A D conversion 18 in progress 1 A D conversion in process 0 No conversion in process This bit initiates a conversion The length of the conversion is dependent
39. on The analog output can provide up to eight analog output channels with two modes of operation XVME 542 analog input features include e 64 single ended 32 differential or 64 pseudo differential 16 bit analog input channels e Unipolar 0 5 V 0 10 V or bipolar 5 V 1 0 V operation e Programmable gains of 1 2 5 10 4 8 20 40 or 10 20 50 100 e 16 bit conversion e 6 operating modes e Single channel conversion Sequential channel conversion e Random channel conversion e External trigger conversion e Autoscanning conversion Programming gain e 10 usec acquisition and conversion time e 16 usec settling time Analog output features include 8 analog output channels with 12 bit resolution e 4 20 mA 0 5 V 0 10 V 2 5 5 and 4 e 5 output drive for voltage output 10 V operation e Transparent and simultaneous update operating modes e D A latch readback capability e Analog ground reference for current return 1 1 542 Operational Description The following figure shows the operational diagram of the XVME 542 AIO module Channels 4 7 Out 4 20mA Driver 4 20 Driver X DACs 4 7 Programmable Interrupt Timer VMEbus Interface VME Bus gt XVME 542 Operational Block Diagram Xycom Standard I O Architecture
40. r and switch settings this bit enables or disables periodic VMEbus interrupts 1 Enables periodic interrupts 0 Disables periodic interrupts Bit 6 This period select bit selects the time interval for a one bit change in delay bits 1 Delay bit time interval is 131 072 msec 0 Delay bit time interval is 8 192 msec Bits 5 3 Reserved Bits 2 0 LSB These period multiplier bits select a timeout period for the interrupt timer The resolution for each bit is determined by the delay set bit 3 16 Chapter 3 Programming The table below defines the interrupt timeout periods Period Multiplier Period Select Interrupt Timeout Period Bits Bit ooi 0 o olo o un e 37me osom 0 10 0 mooo 01 ooi olo n in Interrupt Timeout Periods Programmable Timer Interrupt Vector Register base 103h This read write register holds the vector to be driven on the VMEbus when the interrupt generated by the interrupt timer is acknowledged This register clears on power up Autoscan Control Register base 111h Continuous conversions are performed on 8 16 32 or 64 channels when autoscanning mode is selected that is base 180h is set to 4 The results of each channel are stored in 16 bit register using dual ported RAM starting at offset 200h channel 0 and ending at 2Fh channel 63 In this mode end of A D con
41. rrupt or an interrupt at the end of a conversion The time period is determined by the interrupt timer register base 101h Open Open Closed f6 Interrupt Level Switch Settings Jumper Settings This section defines the XVME 542 jumper settings Note must always be set to for proper operation SYSFAIL The position of jumper J3 determines whether the XVME 542 can assert a SYSFAIL When J3 is set to A the SYSFAIL driver is disabled when it is set to B the SYSFAIL driver is enabled and the module asserts SYSFAIL when the red fail LED is on J3A is the factory shipped configuration Analog to Digital Conversion Options Following are the jumper settings for analog to digital conversions Input Conversion Format Options Jumper J62 sets the conversion of analog information to straight binary or two s complement binary format J62A sets straight binary format J62B sets two s complement binary format Chapter 2 Installation Differential Single ended Input Options Use jumpers J2 and J64 to configure the analog input channels for 64 single ended 64 pseudo differential or 32 differential input channels Single ended Pseudo differential Differential Jumper Settings Input Channels Input Voltage Options Jumpers J53 J60 J61 and J63 configure the module for one of four input voltage ranges J53 J60 J61 J63 Jumper Settings Input Voltage Input Gain Range Options
42. t 5 This bit determines the mode in which the D A converters are operating 1 Simultaneous update mode 0 Transparent mode In transparent mode each analog output channel or DAC is updated individually when the lower byte of the desired DAC is written to Byte or word transfers are allowed If all 12 bits are written at once then that DAC s register along with the output of the DAC gets updated Each channel has its own word location In simultaneous channel update mode the individual DAC registers are written to both high and low bytes with no update to the DAC output Updating the channel or channels is accomplished by writing to location E9h with the desired channels to update In simultaneous channel update mode any combination of the 8 channels may be updated at once Bit 4 This bit performs a software reset to the D A section A software reset occurs when this bit is toggled to 1 then 0 This resets all DAC outputs and clears the D A update register Bits 3 2 Reserved Bits 1 0 LSB These bits control the green and red LEDs 1 Turns red LED 0 Turns on green LED Refer to the table on the following page for more information on bits 1 and 0 3 14 Chapter 3 Programming Status Bits LEDs 1 0 Green Red SYSFAIL Status tested 9 11 or 1 on Or Module undergoing rest Note Whenever bit 0 is 0 the VMEbus SYSFAIL signal is asserted and t
43. the to channel 2 Adjust the analog voltage in for binary encoding mode and the voltage range chosen 0 full scale calibration and the POT until the display reading toggles between the full scale calibration and transition point values For example t offset binary d perform a full scale calibration on an XVME 542 configured for bipolar 10 V range operation e Apply 9 99954 V to channel 0 e Adjust R70 until the display reading toggles between FFFEh and FFFFh Chapter 4 Calibration Output Calibration You need the following equipment to perform an output calibration Five digit volt meter capable of reading 30 uV e Small flat bladed screw driver Output calibration entails voltage offset and gain adjustments for each channel in both unipolar and bipolar configurations The following table shows which potentiometers relate to which output channels R66 859 RAT R46 R35 Ra R33 Output Offset Adjustment Potentiometers Unipolar Offset Adjustment Perform the following steps to adjust the unipolar offset Set jumpers to the desired unipolar range Turn all bits off load binary zeros to the channel being calibrated Make sure the channel is jumpered for voltage output J39 J42 ses cpu Oba eo Adjust the unipolar potentiometer that corresponds to the channel being calibrated until the output reads 0 0000 volts 30 uV Turn all bits on FFFh to the channels being calibrated en
44. version interrupts cannot be used however the programmable interrupt timer is still available This register clears on power up or sysreset Bit 7 can also be cleared by an A D section software reset 3 17 XVME 542 Manual The bits in this register are defined below Bit 7 MSB Bits 6 2 This bit enables or disables the autoscan control register It is cleared on power up SYSRESET or A D software reset 1 Autoscanning enabled 0 Autoscanning disabled Reserved Bits 1 0 LSB These bits defined in the table below are used to select the channels to be scanned These bits are cleared on power SYSRESET Scan Select Bits Channels Scanned o J n ves Hh o A D Mode Register base 180h This 8 bit register determines the operating mode for the analog inputs used on the module The bits are defined below Bits 15 MSB 11 Reserved 3 18 Bit 10 Bit 9 Bit 8 LSB Mode bit 2 Mode bit 1 Mode bit 0 The mode bits determine the operating mode for analog inputs One of six modes can be selected as defined in the table below Mode Bits Bit2 A D Conversion Mode o 0 0 j Singlechanel 0 0 Sequenialchannel o i o Random channe o fi i Bxemiwger 1 o o i o i Programming gain Chapter 3 Programming The A D conversion modes are described below Single Channel Mo
45. w Analog GND Channel 18 low Channel 18 high Analog GND Channel 19 high Channel 19 low Analog GND Channel 20 low Channel 20 high Analog GND Channel 21 high Channel 21 low Analog GND Channel 22 low Channel 22 high Analog GND Channel 23 high Channel 23 low Analog GND Channel 24 low 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Single ended Configuration Channel 56 Analog GND Channel 57 Channel 49 Analog GND Channel 50 Channel 58 Analog GND Channel 59 Channel 51 Analog GND Channel 52 Channel 60 Analog GND Channel 61 Channel 53 Analog GND Channel 54 Channel 62 Analog GND Channel 63 Channel 55 Analog GND Power GND External Trigger Chapter 2 Installation Differential Configuration Channel 24 high Analog GND Channel 25 high Channel 25 low Analog GND Channel 26 low Channel 26 high Analog GND Channel 27 high Channel 27 low Analog GND Channel 28 low Channel 28 high Analog GND Channel 29 high Channel 29 low Analog GND Channel 30 low Channel 30 high Analog GND Channel 31 high Channel 31 low Analog GND Power GND External Trigger XVME 542 Manual JK2 Connector A dual 34 pin ribbon connector with latches containing 68 pins is used for the analog output section The pinouts for this connector are shown in the following table JK2 Pinouts upper and lower Dual Connector 1st Half Pin
46. ycom Standard rogrammable VO Module Buffer Interrupt Interface Timer VMEbus Interface XVME 542 Block Diagram XVME 542 Manual XVME 542 Assembly Drawing A 2 15 00 15 900 AGND 8 255 C54 447 448 449 2 2 1 2 0 81343 81344 8 8 J45 a 8 J22 n 8 J38 8181 39 81813740 Psa 1333 a 8 Jz4 4 81813355 430 81813156 Dres 8181427 81814128 a 8 J29 8 J350 1 e 2 18 a 8 J 19 a 8 J Dis Des XVME 542 Manual f 3 e ROAR e i S on tes 2 2 cs Hals 28 5 AEN ceno 22 88 cuz as 2 BE 8 51185655 Q 00 i 0 gt T 7 x5 ERMEE EELT SI N STANDARD ADDRESS GI SPUR BUTH 5 ___ 35 _ 35 Tn ER 53955858 3 8 5 Kis 2 UME INTERFACE CIRCUITRY E 8 B 8 2 e gt 28 8 San oh z5 zx z 264 5 28 04 Ss os a Q ee aw Lun aas ue T 25 8 LO Bor gt

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