Active Optical Cable Assembly
Contents
1. Byte Bit s Description Value Meaning 128 7 0 Identifier 0Dh 129 1 6 Extended Identifier Values Power Class 0 Power Class 1 Module 130 7 0 Connector 23h AOC has no optical connector 140 7 0 Nominal BR Part Specific 142 7 0 Cable Length SM fiber in km 0 143 7 0 Cable Length fiber in 2 m Increments 0 144 7 0 Cable Length OM2 fiber in 1 m Increments 0 145 7 0 Cable Length OM1 fiber in 1 m Increments 0 146 7 0 Link Length Units of 1 m Part Specific 147 4 Transmitter Technology 0 Pass 850 nm VCSEL 148 163 Vendor Name Samtec Inc 164 3 0 Extended Module Codes InfiniBand Data Rates Part Specific 165 167 Vendor OUI 04C880h 168 183 Vendor Part Number Part Specific 184 185 Vendor Revision 0 186 7 0 Wavelength fiber 42h Wavelength 850 nm 187 7 0 Wavelength fiber 68h Wavelength 850 nm 188 7 0 Wavelength Tolerance OFh Wavelength Tolerance 20 nm 189 7 0 Wavelength Tolerance AO0h Wavelength Tolerance 20 nm 190 7 0 Max Case Temp 70 Max Temp Case 70 C 191 7 0 Check Sum Part Specific 193 0 RX Output Amplitude Programming 0 Not Implemented 194 3 RX Squelch Disable Implemented 0 Not Implemented 194 2 RX Output Disable Capable 1 RX Output Disable Capable 194 1 TX Squelch Disable Implemented 0 Not Implemented 194 0 TX Squelch Implemented 0 Not Implemented 195 7 Memory Page 02 Provided 1 Memory Provided 195 6 Memory Page 01 Provided 0 Not Implemented 195 4 TX Disable Implemented also disables serial output 1 TX2. This is invisible to the end user who just reads and writes to the 12 as if it were an actual EEPROM according to the standard SFF Memory Map The processor will take care of fetching and writing the data internally from to the correct physical location Instructions for modifying the EEPROM map can be found at www samtec com Samlec INITIALIZATION PROCEDURE SFF Memory Map The structure of the SFF Memory Map as defined by SFF 8436 rev 3 8 is shown in Figure 3 For historical reasons the SFF Memory Map is somewhat contrived It is divided into lower and upper memory The lower memory is a block or page of 128 bytes and its bytes address are numbered 0 to 127 The upper memory is itself divided in four pages numbered page 0 to page 3 Each page is also 128 bytes long block but with byte addresses numbered 128 255 for each page All QSFP AOCs are hard wired at I C device address AOh The lower page is accessed by using the AOh address as the device address and the 0 to 127 address as the byte address Upper pages are accessed by first writing the desired page number at byte in address 127 Page Select Byte Any subsequent byte read or write request in the address range 128 255 will be done from to the page that has been specified in the Page Select Byte Samtec AOCs do not use Page 02 Figure 5 Structure of the SFF Memory Map from the SFF specification 2 wire serial address 1010000x Ah Page
3. QSFPO Series Active Optical Cables AOCs are 4 channel bidirectional optical assemblies for QSFP applications and are designed to meet the requirements of modern optical based interconnects Each AOC offers 4 independent transmit and receive channels carrying 850 nm signals across standard multi mode fibers Two different series are available providing an aggregate bandwidth of up to 40 Gbps QSFPO 40G Series or 56 Gbps QSFPO 56G Series The electrical interface is a standard QSFP 38 contact edge type connector and is electrically compliant with the SFl and PPI interface supporting InfiniBand Ethernet Fibre Channel and other protocols The connector is hot pluggable and provides 12 serial access via an on board microcontroller Figure 1 QSFP Active Optical Cable Assembly INTRODUCTION Applications The QSFP AOC comes pre tested and can be used as a direct replacement for traditional copper cables but with the added benefit of a lighter weight and smaller diameter solution for cable lengths from 1 to 100 m It can also be used to replace a pair of transceivers proving equivalent performance at a lower cost The QSFPO 40G Series AOC complies with the standard for InfiniBand QDR and Ethernet 40 GbE 40 Gigabit Ethernet applications and is listed on the InfiniBand Trade Association s Approved Integrator s List for lengths from 1 to 100 m The QSFPO 56G Series AOC provides the same capabili
4. EMI Immunity Variation of IEC 61000 4 3 10 V m 80 1000 Mz IEC 60825 1 amendment 2 CFR 21 section 1040 Class 1 Laser Eye Safety RoHS 6 6 directive 2002 95 EC Rons Compliance amendment 4054 2005 747 EC Complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No 50 dated June 24 2007 Manufacturing Location Samtec 520 Park East Blvd New Albany IN 47150 Caution Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure Ordering Information QSFP Active Optical Cable XXX 07 Product Category _____ D9 9 Speed 4 x 100 lanes 40G 4 x 14G lanes 56G Type Length in meters 0 5 to 100 0 500 mm to 100 m See www samtec com QSFPO 40G www samtec com QSFPO 56G MTP or Duplex LC end terminations also available Call Samtec Samlec TECHNICAL INFORMATION Definitions This document uses the following conditions All voltages are referred to GND unless otherwise specifically noted Currents are defined positive out of the pin Reference Documents SFF 8436 QSFP Specifications Document SFF 8431 SFP Specifications Document InfiniBand Architecture Release 1 3 IEEE802 3ba Amendment 4 Media Access Control Parameters Physical Layers and Management Parameters for 40 Gbps and 100 Gbps
5. 1 1 8 LVTLL I ModSelL Module Select 3 9 LVTLL I ResetL Module Reset 3 10 Vcc Rx 3 3 V Power Supply Receiver 2 2 11 LVCMOS I O SCL Two Wire Serial Interface Clock 3 12 LVCMOS I O SDA Two Wire Serial Interface Data 3 13 GND Ground 1 1 14 CML O Rx3p Receiver Non Inverted Data Output 3 15 CML O Rx3n Receiver Inverted Data Output 3 16 GND Ground 1 1 17 CML O Rxip Receiver Non Inverted Data Output 3 18 CML O Rxin Receiver Inverted Data Output 3 19 GND Ground 1 1 20 GND Ground 1 1 21 CML O Rx2n Receiver Inverted Data Output 3 22 CML 0 Rx2p Receiver Non Inverted Data Output 3 23 GND Ground 1 1 24 CML O Rx4n Receiver Inverted Data Output 3 25 CML 0 Rx4p Receiver Non Inverted Data Output 3 26 GND Ground 1 1 27 LVTLL O ModPrsL Module Present 3 28 LVTLL O Intl Interrupt 3 29 Vcc Tx 3 3 V Power Supply Transmitter 2 2 30 Vccl 3 3 V Power Supply 2 2 31 LVTLL I LPMode Low Power Mode 3 32 GND Ground 1 1 33 CML I Tx8p Transmitter Non Inverted Data Input 3 34 CML I Tx8n Transmitter Inverted Data Input 3 35 GND Ground 1 1 36 CML I Txip Transmitter Non Inverted Data Input 3 37 CML I Txin Transmitter Inverted Data Input 3 38 GND Ground 1 1 Vote 1 GND is the symbol for signal and supply power common for the optical engine All are common within the optical engine and all module voltages are referenced to this potential unless otherwise noted Connect these directly to the host board signal com mon ground plane Vote 2 Vcc Rx V
6. module and channel digital diagnostic parameters are provided for monitoring Transceiver Temperature Transceiver Supply Voltage The microcontroller will generate an Interrupt Flag by asserting the IntL signal when an operational fault occurs The host can identify the source of the interrupt by reading the appropriate registers through the Two Wire interface The following Interrupt Flags are provided Rx LOS Provided for each channel which indicates that the optical power input into the receiver has dropped below a minimum allowed value Tx Fault Provided for each channel which indicates that a fault condition relating to either the laser or one of the optical modulators has occurred Transceiver Temperature High and Low Alarm and High and Low Warning Transceiver Supply Voltage High and Low Alarm and High and Low Warning SPECIFICATIONS Common Electrical Characteristics The maximum operating and storage conditions are shown in Table 1 Any stress beyond these maximum ratings may result in permanent damage to the device Table 1 Absolute Maximum Rating CC1 Storage Temperature Range m C 40 85 Powered Case Temperature C 0 70 Heat sink temperature Operating Humidity RH 5 90 Noncondensing Supply Voltage Range V V 0 5 4 0 Specifications listed in this documentation are only guaranteed when the QSFP AOC is operated under the recommended operating
7. 02 INITIALIZATION PROCEDURE Below is a summary description of the memory pages For more details see pages 18 19 of this product specification Lower memory Page 00 bytes 0 127 contains status interrupt and monitoring information Page 00 bytes 128 255 contains standardized Read Only information for the end user The data is physically mapped to the microprocessor internal EEPROM bytes 128 255 Page 01 bytes 128 255 is optional and not supported in the Samtec AOC Page 02 bytes 128 255 is available for the user to store and read his own data Page 03 bytes 128 255 contains module thresholds channel thresholds and masks and optional channel controls Page 00 Lower Memory Many of the lower memory bytes are optional or not applicable to an AOC implementation Table 13 lists the bytes and corresponding features supported in our implementation Full details about the bit fields and usage can be found in the SFF 8436 specification Table 13 Supported Page 00 Lower Memory Fields e Read Only Page 00 Byte Description Default Value BORA Notes 0 Identifier 00 RO 2 Status Flat or Paged Memory 0 RO 3 Interrupt Flags LOS RO 1 4 Interrupt Flags Tx Fault RO 6 Interrupt Flags Temp Alarm RO 7 Interrupt Flags Voltage Alarm RO 22 Module Monitors Temperature 8 RO 23 Module Monitors Temperature LSB RO 26 Modul
8. Common Mode Voltage mV 15 RMS Differential Input Return Loss Shou dB See Note 1 50 MHz to 14 1 GHz Common Mode Input Return Loss dB 2 Common Mode to Differential Reflection Soon Reflected Differential to Mode Conversion Seon 08 10 Total Jitter TJ Ul 0 28 Data Dependent Jitter DDJ Ul 0 1 Data Dependent Pulse Width Shrinkage DDPWS Ul 0 11 J2 Jitter Tolerance J2 Ul 0 19 JQ Jitter Tolerance J9 Ul 0 34 Eye Mask See Note 3 Hit ratio 5 x 10 Notes for Table 6 1 Maximum is defined by the formula 0 05 lt 1 lt 56 12 171 7 is defined by the formula 16 3f 3 The worst case electrical input is defined by the eye mask LL 2 Maximum Spe Voltage mV 95 0 95 0 69 Normalized Time UI sam ec SPECIFICATIONS Table 7 QSFPO 56G Series Electrical Output Specification Specifications Symbol Unit Min Max Notes Data Rate per Channel Gbps 1 14 2 Termination Mismatch at 1MHz AZ 15 Output AC Common Mode Voltage mV 20 RMS Single ended Output Voltage Tolerance v 03 38 Differential Output Amplitude in Squelched State mV 50 Peak to peak differential e mV 50 225 Range 0 ifferential Unsigne Output Voltage 100 350 Range 1 150 450 Range 2 Common Mode Output Reflection Coefficient Sc dB See Note 1 Differential Output S Parameter Sono dB See Table 6 Note 2 50 MHz to 15 GHz Common Mode to Different
9. Disable Implemented 195 3 TX Fault Reporting Implemented 1 TX Fault Reporting Implemented 195 1 LOS and Reporting Implemented 0 Not Implemented 196 211 All Vendor Serial Number Part Specific 212 217 Date Code Part Specific 218 219 Lot Code 0 Optional Value 00 223 Check Sum Part Specific 224 255 Vendor Specific Information FF000110 INITIALIZATION PROCEDURE Notes to Page 00 Implementation Please see Table 15 for further clarification of our implementation of Page 00 fields Table 14 Notes to the Memory Map Implementation Address Type of Parameter Name Notes Page Byte Interrupt Flag 00 3 Tx_LOS Not Provided Interrupt Flag 00 9 10 L Rx Power Alarm Not Provided Channel Monitoring 00 34 41 Rx Input Power Rx Input Power is Not Supported Channel Monitoring 00 42 49 Tx Bias Tx Bias Monitoring is Not Supported Channel Mask 00 100 7 4 M Tx LOS Tx LOS is Not Supported Optional Channel Controls 03 241 3 0 Tx SQ Disable Tx Squelch is Not Supported Page 02 Page 02 bytes 128 255 are provided for end customer s own use The fields are initialized to 0 at the factory Page 03 Table 16 Supported Page 03 Fields Page 03 Byte Description Default Value Read Only Read Write 128 Temp High Alarm MSB RO 129 Temp High Alarm LSB RO 130 Temp Low Alarm MSB oc RO 131 Temp Low Alarm LSB RO 132 Temp Hig
10. IFICATIONS Control Status and Monitor Interface Table 11 and Table 12 provide the specifications of the control status and monitoring interface Table 11 1 0 Timing for Control Status and Monitoring Specifications Symbol Unit Min Max Notes Eur Time from power on hot plug or rising edge of Initialization Time 3 ms 2000 reset until the module is fully functional crei fiiit esr TR team de 25 A reset is generated by a low level longer than the minimum reset pulse time present on the ResetL pin Time from power on until module responds to data Serial Bus Hardware Ready ET ms 2000 transmission over the Two Wire serial bus Monitor Data Ready t ma 2000 Time from power on to data not ready bit 0 of Time DATA Byte 2 de asserted and IntL asserted Time from rising edge on the ResetL pin until the Reset Assert Ue hee MS i module is fully functional Time from occurrence of condition triggering IntL IntL Assert Time e 200 mil Visi Wal Time from operation of associated flag until IntL De assert Time bean US 500 Vout IntL Voh This includes de assert times for Rx 7 LOS Tx Fault and other flag bits Time from Rx LOS state to Rx LOS bit set Rx LOS Assert Time haies ms 100 value 1b and IntL asserted Tx Fault Assert Time Ie 200 Ting ue BUE si Flag Assert Time lacus Ms 200 Tag ES valve Trand rt deserit Mesk Asser Time Ms 100 Time from mo
11. L pin is used to toggle control of different modules the assert and de assert times must be taken into account to prevent communication conflicts e LPMode The LPMode pin is used by the host to set the maximum power consumption by the module This is intended to protect hosts that are not designed to cool higher power modules that draw more than 1 5 W Since the power consumption of a QSFP AOC is 0 8 W maximum this pin is not used and the module is always in a low power state e ResetL The AOC can be reset to its default settings by pulling this control pin to a low level for a period longer than the minimum pulse length of the Two Wire serial interface While in this reset state the host should disregard all status bits ModPrsL ModPrsL is used to indicate to the host that the connector is popu lated by the AOC In the absence of an AOC this is pulled up to the host Vcc When the AOC is inserted it completes the path to ground through a resistor on the host and pulls ModPrsL to a low state IntL This control pin is used to indicate a possible module operation fault or a status critical to the host system The IntL pin is an open collector output and must be pulled to the host Vcc voltage on the host board When pulled low by the AOC the alarm is active and the AOC will identify the source of the interrupt using the Two Wire serial interface SPECIFICATIONS In addition there is an industry standard Two Wire serial
12. LE FOR ANY DIRECT INCIDENTAL CONSEQUENTIAL INDIRECT OR PUNITIVE DAMAGES ARISING OUT OF YOUR ACCESS USE OR INABILITY TO ACCESS OR USE THIS PUBLICATION OR ANY ERRORS OR OMISSIONS IN ITS CONTENT Copyright 2014 Samtec Inc TABLE OF CONTENTS INTRODUCTION Product Features cnc ER HEUS 4 Applications sese 5 FUNCTIONAL DESCRIPTION Transmitter Block sss 6 RecelVer BlOCK 7 Management Interface sss 7 SPECIFICATIONS Common Electrical Characteristics ssene 8 High Speed Electrical Characteristics QSFPO 40G Series 10 High Speed Electrical Characteristics QSFPO 56G Series 12 Optical Characteristics sese Interfaces Two Wire Serial Interface Control Status and Monitor Interface INITIALIZATION PROCEDURE Memory Map Introduction EEPROM Virtual Addressing 18 SFF Memory Page 00 Lower Memory Page 00 Upper Memory Notes to Page 00 Implementation Page 02 Page 03 Output Voltage and Pre emphasis Settings 23 INTERFACE 24 MECHANICAL CHARACTERISTICS Connector DIMENSIONS 2 22 25 TECHNICAL INFORMATION Regulatory and Compliance Ordering Information Definitions LISTED FILE NO E357212 I T E INTRODUCTION Product Features
13. Operation Notice This document is made available subject to Samtec General Terms and Conditions available at www samtec com and contains information about a product which is currently under final development The information contained in this document is based on design targets simulation results or early prototype test results Characteristics data and other specifications are subject to change without notice Therefore the reader is cautioned that this datasheet is preliminary The reader is advised to obtain the most recent datasheet before considering any purchase or use for design considerations Warning Samtec products are not intended for use in life support applications and any such use without written consent is therefore prohibited AL For more information visit www samtec com active optics or contact Samtec s Optical Group at optics samtec com All designs specifications and components are preliminary and subject to change without notice SUDDEN SERVICE JANUARY 2014
14. Samlec Active Optical Cable Assembly USER S MANUAL SAMTEC OPTICAL GROUP COVERING JANUARY 2014 QSFPO Series COPYRIGHTS TRADEMARKS AND PATENTS Terms of Use Disclaimer Patents Product names used herein are trademarks of their respective owners All information and material in this publication are property of Samtec Inc All related rights are reserved Samtec Inc does not authorize customers to make copies of the content for any use Use of this publication is limited to viewing the pages for evaluation or purchase No permission is granted to the user to copy print distribute transmit display in public or modify the contents of this document in any way The information in this publication may change without notice All materials published here are As Is and without implied or express warranties Samtec Inc does not warrant that this publication will be without error or that defects will be corrected Samtec Inc makes every effort to present our customers an excellent and useful publication but we do not warrant or represent the use of the material here in terms of their accuracy reliability or otherwise Therefore you agree that all access and use of this publication s content is at your own risk Patents pending on technologies used within this product NEITHER SAMTEC INC NOR ANY PARTY INVOLVED IN CREATING PRODUCING OR DELIVERING THIS PUBLICATION SHALL BE LIAB
15. TION PROCEDURE Memory Map Introduction EEPROM Virtual Addressing The SFF 8436 specification calls for a list of cable parameters to be readable through an I C interface commonly referred as the EEPROM parameters When the first standard revision was written all the parameters were static and were stored in an on board EEPROM As revisions evolved some of the fields became dynamic such as temperature or optical power readings while others such as interrupts and alarms became Read Write R W As a result an EEPROM based implementation does not suffice anymore although the term is still used to refer to the Memory Map We will refer to this as the SFF Memory Map Consequently the Samtec current implementation although referred to as an EEPROM map does not use an actual direct EEPROM read or write Instead each l C read or write request is interpreted by the embedded microprocessor in the optical engine The microprocessor then reads or stores data which could come from or go to different sources The processor s own internal EEPROM The processor s static dynamic RAM or register memory Sensors or internal chipset readings Internal processor calculations or registers An important consequence is that EEPROM byte addresses used 0 requests are virtual they will not always correspond to the physical address in the processor internal EEPROM or might not have a physical EEPROM location at all
16. al differential input impedance of 100Q AC coupling capacitors are located on the optical engine board and therefore are not required on the host board An LVTTL compatible Two Wire Serial I C interface is provided for module control and diagnostics Status alarm and fault information are available via the TWS interface To reduce the need for polling a hardware interrupt signal is provided to inform hosts of an assertion of an alarm Loss of Signal LOS and Transmitter Tx fault FUNCTIONAL DESCRIPTION Receiver Block The optical receiver portion of the engine incorporates a 4 channel PIN photodiode array a 4 channel TIA array a 4 channel output buffer diagnostic monitors control and bias blocks The Receiver Output Buffer provides CML compatible differential outputs for the high speed electrical interface presenting nominal single ended output impedances of 50Q to AC ground and 100Q differentially that should be differentially terminated with 100Q Again AC coupling capacitors are located on the optical engine and are therefore not required on the host board Management Interface The internal optical engine provides digital diagnostics and control monitor functions as specified in SFF 8436 A microcontroller which can be accessed through the Two Wire interface monitors and reports this information The functionality of the Two Wire interface is specified in the SFF 8436 specification The following
17. cc1 and Vcc Tx are the receiver and transmitter power supplies and shall be applied concurrently Requirements defined for the host side of the Host Edge Card Connector are listed in Table 18 The connector pins are each rated for a maximum current of 500 mA Samlec INTERFACE GND 1 37 TX1 na 2 E 2 3 35 GND GND 4 34 TX3 5 33 TX3 6 32 GND 30 Voci g ResetL 9 29 VecTx VCCRX 10 28 IntL rm sa 11 27 ModPrst g SDA 12 GNO G GND 13 25 RX4 m 24 R3 15 23 GND 16 22 7 Hu Rx2 RX1 18 m GND 19 Top Side Bottom Side Viewed from Top Viewed from Bottom Figure 5 Edge Card Connector Pinout Connector Dimensions OVERALL LENGTH CABLE LENGTH 47 00 1 85 5 i E OI DOO E M co 67 45 2 66 Pm 722 8 50 _44 138 43 5 45 ____________ 335 HE Ee Figure 6 Connector Dimensions TECHNICAL INFORMATION Regulatory and Compliance Table 19 Regulatory and Compliance JEDEC Human Body Model HBM Electrostatic Discharge ESD ATTY JEDEC Machine Model MM TBD JESD22 A115 A Electrostatic Discharge ESD Variation of IEC 61000 4 2 15 kV to Module Case Electromagnetic FCC part 15 CENELEC EN55022 TBD Interference EMI CISPR 22A VCCI class 1
18. conditions listed in Table 2 Table 2 Recommended Operating Conditions Operating Case Temperature a C 0 70 sink temperature Power Supply Voltage Ms V 3 15 3 45 DC Common Mode Voltage Vow V 0 3 6 Per Channel Data Rate 40G series Gbps 1 10 5 Per Channel Data Rate 56G series Gbps 1 14 1 sam ec SPECIFICATIONS In addition to the recommended operating conditions the power supply requirements are shown in Table 3 Table 3 Power Supply Requirements Power Supply Voltage Ves V 3 15 3 45 Power Supply Current ba mA 240 typical Power Consumption W 1 0 0 8 W typical Power Supply Noise mV 50 1 kHz to frequency of operation including Ripple measured at Vcc host The QSFP specification recommends the use of a host board power supply filter to reduce power supply noise The recommended power supply filter is shown in Figure 3 mel _ Vos Tx 2 host 33 vo nm Voc Rx T a 0 1 uf a uk 010 0 GND 1uH AA Vect LLL 1 uF GNO re QSFP Module Figure 3 QSFP Filtering Scheme SPECIFICATIONS High Speed Electrical Characteristics QSFPO 40G Series The electrical requirements for input signal into the QSFPO 40G Series are defined for the transmit side in Table 4 With inputs into the AOC that meet these requ
19. e 7 associated Time from mask bit cleared value 0b until associated IntlL operation resumes Time from change of state of Application or Rate Select ms 100 until transmitter or receiver bandwidth is in conformance with appropriate specification Time from P Down bit set value 1b until module Mask De assert Time tore mask MS 100 Application or Rate t Select Change Time RATE SEL Power Over ride or Power Set Assert Time loeo MS 100 power consumption enters Power Level Power Over ride or t E 300 Time from P Down bit cleared value 0b until the Power Set De assert Time FF Poown module is fully functional Note 1 Measured from falling clock edge after stop bit of write transaction Note 2 Power is defined as the instant when supply voltages reach and remain at or above the minimum level specified in Table 3 Note 3 Fully functional is defined as IntL asserted due to data not ready bit bit 0 Byte 2 de asserted The module should also meet electrical specifications Note 4 Measured from falling edge after stop bit of read transaction Table 12 1 0 Timing for Squelch Specifications Symbol Unit Min Max Time from loss of Rx input signal until the squelched output condition is reached Time from resumption of Rx input signals until normal Rx output condition is reached Rx Squelch Assert Time tON_RXSQ Rx Squelch De assert Time tOFF_RXSQ INITIALIZA
20. e Monitors Supply Voltage MSB RO 27 Module Monitors Supply Voltage LSB RO 86 Control Transmitter Disable R W 93 Low Power Control R W 2 100 Interrupt Masks Tx LOS Mask 0 R W 101 Interrupt Masks Tx Fault Mask 0 R W 103 Interrupt Masks Temperature Fault Mask 0 R W 104 Interrupt Masks Voltage Fault Mask 0 R W 119 Password Change Entry Data R W 3 120 Password Change Entry Data R W 3 121 Password Change Entry Data R W 3 122 Password Change Entry Data R W 3 123 Password Entry Area R W 3 124 Password Entry Area R W 3 125 Password Entry Area R W 3 126 Password Entry Area R W 3 Page Select Byte R W 1 Rx only Tx LOS not supported 20 2The engine always runs in low power mode writing to this register has no effect 3 User settable password protection of page 02 not supported INITIALIZATION PROCEDURE Page 00 Upper Memory The values for the Page 00 Upper Memory bytes are shown Table 14 Default factory programmed values for InfiniBand are shown Some of the fields will need to be adjusted by the customer at manufacturing time Values can be uploaded using our software tool For details please contact optics samtec com Please contact Samtec for alternate default configurations Table 14 Page 00 Upper Memory Fields factory default InfiniBand
21. h Warning MSB 70 RO 133 Temp High Warning LSB RO 134 Temp Low Warning MSB 5C RO 135 Temp Low Warning LSB RO 144 Vcc High Alarm MSB RO 0 oo 3 465 V 145 Vcc High Alarm LSB RO 146 Vcc Low Alarm MSB RO 147 Vcc Low Alarm LSB cdd RO 14 Vcc High Warning MSB RO 8 CC ig arning 5 33825 V 149 Vcc High Warning LSB RO 1 i R 50 Vcc Low Warning MSB 32175 V 0 151 Vcc Low Warning LSB RO 176 Rx Power High Alarm MSB RO 177 Rx Power High Alarm LSB RO FDR Voltage Select FDR Voltage Select Squelch Disable Rx Output Disable Note Bytes 238 and 239 are only writeable for QSFPO 56G Series variants 22 INITIALIZATION PROCEDURE Output Voltage and Pre emphasis Settings The Rx output amplitude swing and pre emphasis settings are factory adjustable Four output voltage amplitude settings are available 0 mV Rx channel permanently disabled 317 mV 422 mV e 739 mV factory default Four pre emphasis settings are available e 0 mV factory default 125 mV 175 mV 325 mV These settings will change the quality of the electrical output In addition changing these settings also affect the power consumption of the optical engine as shown on Table 17 Reducing voltage and pre emphasis results in the lowest power consumption available while larger voltage and pre emphasis might be used in special non standard applications to overcome poor electrical traces or provide more design margin at the expense of power cons
22. ial Reflection Soc See Table 6 Note 2 Output Transition Time Tr Tf ps 17 20 to 80 Total Jitter TJ Ul 0 7 J2 Jitter Ul 0 44 J9 Jitter Ul 0 69 Eye Mask See Note 2 Hit ratio 2 5 x 105 Notes for Table 7 1 Maximum 5 is defined by the formulas O01 lt f lt 41 12 2 F 111 lt 1 lt 15 2 2 The InfiniBand Architecture Release 1 3 introduces the concept of user selectable output voltage to enable interworking with linear and limiting PHYs By default a QSFPO 56G Series cable will power up with a voltage output range of 1 This can be changed to produce a higher or lower output voltage swing by changing Bytes 238 and 239 within Page 03 of the memory map For further information please refer to the aforementioned standard The voltage mask is dependent on the Selected Voltage Range Normalized Time UI SPECIFICATIONS Optical Characteristics QSFP Active Optical Cables are also available as half cable assemblies Half cables with MTP connectors are available for applications that require connection to existing infrastructure Breakout cables with four Duplex LC connectors are available for connecting a QSFP port to SFP or XFP transceivers Table 8 QSFPO 40G Series Optical Performance Specifications Unit Min Notes Center Wavelength nm 840 860 Defined as the standard RMS Spectral Width 065 deviation of the spectrum RIN OMA dB Hz 128 286 At 19 um Encircled Flu
23. interface scaled for 3 3 volt LVTTL It is implemented as a slave device Signal and timing characteristics are further defined below Two Wire Serial Interface Table 10 and Figure 4 show the Two Wire timing specifications as defined by SFF 8436 Table 10 Optical Engine Two Wire Timing Specifications Parameter Symbol Unit Min Typ Max Conditions Clock Frequency KHz 0 400 0 Clock Pulse Width Low loy ys 1 3 Clock Pulse Width High m ys 0 6 m Bus Free Before New t us 20 Between STOP ransmission Can Start eur and START START Hold Time tigi us 0 6 START Setup Time lr ys 0 6 Data in Hold Time bon us 0 Data in Setup Time lins ys 0 1 Input Rise Time 400 kHz Las ns 300 From V 0 15 to V 0 15 Input Fall Time 400 kHz ban ns 300 From V 0 15 to Vi 0 15 STOP Setup Time tuso us 0 6 Setup time on the select lines ModSelL Setup Time HOST_select_setup ms 2 before start of a host initiated serial bus sequence Delay from completion of a serial ModSelL Hold Time Host_select_hold us 10 bus sequence to changes of mod ule select status Delay from a host de asserting ModSelL at any point in a bus sequence to the module releasing SCL and SDA Figure 4 Two Wire Timing Diagram per SFF 8436 START HIGH Abort Sequence ists sila Deselect abort ms 2 RESTART STOP START t sam ec SPEC
24. irements the output parameters shown in Table 5 are guaranteed Table 4 QSFPO 40G Series Electrical Input Requirements Specifications Symbol Unit Min Max Notes Data Rate per Channel Gbps 1 10 5 Differential Input Amplitude Won mV 150 1600 Peak to peak differential Single ended Voltage Tolerance V 0 3 3 8 AC Common Mode Voltage mV 15 5 Differential Input S Parameter Spit dB See Note 1 10 MHz to 11 1 GHz Pereca pitte antat comman Soon dB 10 10MHzto 11 1 GHz Total Jitter TJ 0 28 Data Dependent Jitter DDJ Ul 0 1 Data Dependent Pulse Width Shrinkage DDPWS Ul 0 055 Uncorrelated Jitter UJ Ulkus 0 023 J2 Jitter Tolerance J2 Ul 0 17 J9 Jitter Tolerance J9 Ul 0 29 Eye Mask See Note 2 Hit ratio 5 x 10 Notes for Table 4 1 Maximum 5 is defined by the formulas 0 1 f 4 11 124 2 f 4 11 f 11 1 63 131089 2 The worst case electrical input is defined by the eye mask Normalized Time Ul sam ec SPECIFICATIONS Table 5 QSFPO 40G Series Electrical Output Specification Specifications Unit Data Rate per Channel Gbps 1 10 5 Termination Mismatch at 1 MHz AZ 15 Output AC Common Mode Voltage mV 7 5 RMS Single ended Output Voltage Tolerance v 03 38 Differential Output Amplitude Voo mV 310 750 Peak to peak differential Differential Output Amplitude in i 2 a Squelched State
25. mV 50 Peak to peak differential Differential Unsigned Amplitude 0 1 0 6 Common Mode Output RetlachoniGoaniiclent So dB See Note 1 10 MHz to 11 1 GHz Differential Output S Parameter Soo dB See Note 2 10 MHz to 11 1 GHz Output Transition Time Tr Tf ps 28 20 to 80 Total Jitter Td Ul 0 7 Deterministic Jitter DJ Ul 0 4 J2 Jitter Ul 0 42 J9 Jitter Ul 0 65 Eye Mask See Note 3 Hit ratio 5 x 105 Eye Mask See Note 3 Hit ratio 1 x 10 Notes for Table 5 1 Maximum S is defined by the formulas 0 1 f 2 5 251 3 2 Maximum S is defined by the formulas 0 1 lt lt 4 11 124 2 f 411 lt lt 11 1 6 3 131080 3 Two eye masks are specified but are considered to be identical due to the differences in the hit ratio Eye Mask for Hot Ratio k for Hot Ratio 75 1x10 SPECIFICATIONS High Speed Electrical Characteristics QSFPO 56G Series The electrical requirements for input signal into the QSFPO 56G Series are defined for the transmit side in Table 6 With inputs into the AOC that meet these requirements the output parameters shown in Table 7 are guaranteed Table 6 QSFPO 56G Series Electrical Input Requirements Specifications Symbol Unit Min Max Notes Data Rate per Channel Gbps 1 14 2 Differential Input Amplitude Vi mV 250 1600 Peak to peak differential Single ended Voltage Tolerance V 0 3 3 8 AC
26. ties as the QSFPO 40G Series but provides a higher data rate and the ability to reconfigure the output voltage amplitude It complies with the InfiniBand FDR standard and is listed on the InfiniBand Trade Association s Approved Integrator s List for lengths from 1 to 100 m FUNCTIONAL DESCRIPTION The QSFP AOC has a miniature optical engine embedded into each end of the cable assembly The engines interconnect 4 independent transmit receive lanes An on board microcontroller provides control diagnostic and monitoring for the cable functions as well as the external 12 serial communication interface A functional block diagram of the engine is shown in Figure 2 The transmitter section consists of a 4 channel VCSEL Vertical Cavity Surface Emitting Laser array a 4 channel input buffer and laser driver The receiver section consists of a 4 channel PIN photodiode array a 4 channel TIA array and a 4 channel output buffer x4 Laser Driver VCSEL Array SCL SDA Electrical ModSelL interface Optical interface Microcontroller LPMode ModPrsL ResetL PIN Diode Array Figure 2 Transceiver Functional Block Diagram Transmitter Block The optical transmit portion of the engine incorporates a 4 channel VCSEL array a 4 channel input buffer and laser driver diagnostic monitors control and bias blocks The transmit input buffer provides CML compatible differential inputs presenting a nomin
27. umption All QSFP AOC cables will default on power up to the 739 mV 0 mV settings As per the InfiniBand FDR specification the memory map can be used to change the output settings of the QSFPO 56G Series Changing the output to Range 0 will result in a drop in power consumption whereas changing to Range 2 will increase the power consumption Table 17 Typical Power Consumption vs Rx Settings Typical Power Voltage Swing Setting mV Pre emphasis Setting mV Consumption mW Notes 317 0 590 317 125 740 317 175 TIO 317 325 850 422 0 620 56G Range 0 422 125 770 422 175 800 422 325 890 739 0 710 Default Setting 739 860 56G Range 2 739 890 739 980 INTERFACE Electrical Figure 5 shows the contact numbering for the assembly connector The diagram shows the module from the bottom view There are 38 pins intended for high speed low speed signals power and ground connections These pins are described in Table 18 Table 18 Edge Connector Pin Descriptions Pin Logic Symbol Description Plug Sequence Note 1 GND Ground 1 1 2 CML I Tx2n Transmitter Inverted Data Input 3 3 CML I Tx2p Transmitter Non Inverted Data Input 3 4 GND Ground 1 1 5 CML I Tx4n Transmitter Inverted Data Input 3 6 CML I Tx4p Transmitter Non Inverted Data Input 3 T GND Ground
28. x 230 At 4 5 um Average Power of an Off Transmitter dBm 30 Electrical connector to Fiber Length m 0 1 100 optical connector Average Launch Power per Lane dBm 5 0 1 2 Extinction Ratio dB 3 Average Receive Power dBm 9 9 1 Receiver Sensitivity in OMA dBm 11 1 Table 9 QSFPO 56G Series Optical Performance Specifications Unit Min Notes Center Wavelength nm 840 860 Defined as the standard RMS Spectral Width Do 0 65 deviation of the spectrum RIN OMA dB Hz 128 286 At 19 Encircled Flux 230 At 4 5 um Average Power of an Off Transmitter dBm 30 Electrical connector to Fiber Length m 0 1 100 optical connector Average Launch Power per Lane dBm 5 0 1 2 Extinction Ratio dB 3 Average Receive Power Receiver Sensitivity in OMA Sam ec SPECIFICATIONS Interfaces Control Interface As described in the QSFP standard the electrical interface has the following low speed signals for control and status ModSelL LPMode ResetL ModPrsL IntL Their operation is described below ModSelL The ModSelL signal allows multiple QSFP modules to be on a standard I C Serial control bus By default this pin is held low by the host In this state the module will respond to the l C interface When the ModSelL pin is pulled high by the host the module will not respond to or acknowledge any 1 C query or command Care must be taken to ensure that the ModSel
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