Freescale Semiconductor
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1. sivan vivan zomi3 Lvod vonva vod zonva peod era Laod inva Bvod zsNvv Od LSNWE cgod S vi zgod zNva pe e dew reuxoqur O I zemod E 1408 aeg zaos 2 Uppy bzaos 2 1908 PPY 8905 PPY 640 PIdOS 2 149 1 8515 aia perm perm 5 EE asang PIE 8559 EE zd N 995 OYI I ee THA OdMI iet zl euonara fa SSS oss EREEEEFE Sao Saas OL 6 8 2 9 S SSSOdNW E E t4 5 5 E 4 nara Honana s IL LHOI iHonar 8 p x Qn 5 SE Figure 3 MPC555 Pinout Diagram MPC555 Product Brief For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features 4 Supporting Documentation List This list contains references to currently available and planned documentation 5 MPC555 User s Manual MPC555UM AD RCPU Reference Manual RCPURM AD Board Strategies for Ensuring Optimum Frequency Synthesizer Performance AN1282 D Using the MIOS on the MPC555 Evaluation Board AN1778 D Exception Table Relocation and Multi Processor Address Mapping in the Embedded MPC5XX Family AN1821 D Non Volatile Memory Technology Ove2. guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly a
3. 2 2 freescale semiconductor Block Diagram Freescale Semiconductor Inc e Extensive system development support On chip watchpoints and breakpoints Program flow tracking BDM on chip emulation development interface 1 1 Block Diagram Figure 1 is a block diagram of the MPC555 E bus USIU a 256 Kbytes 192 Kbytes Flash Flash Burst Interface U bus RCPU 16 Kbytes 10 Kbytes SRAM SRAM m i gt 120 L bus UIMB QADC QADC QSMCM TouCAN IMB3 i y TPU3 rtt gt TPU3 TouCAN MIOS1 Figure 1 MPC555 Block Diagram 1 2 Key Features The MPC555 key features are explained in the following sections 1 2 1 Four Bank Memory Controller e Works with SRAM EPROM Flash EEPROM and other peripherals e Byte write enables e 32 bit address decodes with bit masks MPC555 Product Brief For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features 1 2 2 U Bus System Interface Unit USIU Clock synthesizer Power management Reset controller MPC555 decrementer and time base Real time clock register Periodic interrupt timer Hardware bus monitor and software watchdog timer Interrupt con
4. C555 Product Brief For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features 1 2 10 Two CAN 2 0B Controller Modules TouCAN Each TouCAN provides these features e Full implementation of CAN protocol specification version 2 0A and 2 0B e Each module has 16 receive transmit message buffers of 0 to 8 bytes data length e Global mask register for message buffers 0 to 13 e Independent mask registers for message buffers 14 and 15 e Programmable transmit first scheme lowest ID or lowest buffer number e 16 bit free running timer for message time stamping e Low power sleep mode with programmable wake up on bus activity e Programmable I O modes e Maskable interrupts e Independent of the transmission medium external transceiver is assumed e Open network architecture e Multimaster concept e High immunity to EMI Short latency time for high priority messages Low power sleep mode with programmable wakeup on bus activity 1 2 11 Queued Serial Multi Channel Module QSMCM e Queued serial peripheral interface QSPI Provides full duplex communication port for peripheral expansion or interprocessor communication Up to 32 preprogrammed transfers reducing overhead 160 byte queue buffer Programmable transfer length from 8 to 16 bits inclusive Synchronous interface with baud rate of up to system clock divided by 4 Four programmable peripheral select pins support up
5. Product Brief MPC555PB D Rev 3 2 2003 MPC555 Product Brief Freescale Semiconductor Inc This document provides an overview of the MPC555 microcontroller including a block diagram showing the major modular components and sections that list the major features The MPC555 member of the Freescale MPC500 RISC Microcontroller family Table 1 MPC555 Features 1 Device Flash Code Compression MPC555 448 Kbytes Code compression not supported Introduction The MPC555 device offers the following features PowerPC core with floating point unit 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM 448 Kbytes Flash EEPROM with 5 V programming 5 V system Serial system queued serial multi channel module QSMCM dual CAN 2 0B controller modules TouCANTM 50 channel timer system dual time processor units TPU3 modular I O system MIOS1 32 analog inputs dual queued analog to digital converters QADC64 Submicron HCMOS CDR1 technology 272 pin plastic ball grid array PBGA packaging 40 MHz operation 40 C to 125 C with dual supply 3 3 V 5 V 55 C to 125 C for the suffix A device 32 bit architecture PowerPC ISA architecture compliant Core performance measured at 52 7 Kbyte Dhrystones v2 1 40 MHz Fully static low power operation Integrated double precision floating point unit Precise exception model Freescale Semiconductor Inc 2004 All rights reserved e
6. SRAM ControlA 8 bytes 0x38 0008 SRAM ControlB 8 bytes 0x38 0010 Reserved 485 98 Kbytes Ox3F 9800 SRAM 10 Kbytes Ox3F C000 SRAMB Ox3F FFFF 16 Kbytes USIU Control Registers 1 Kbyte FLASH Module A 64 bytes FLASH Module B 64 bytes Reserved for USIU IMB3 Address Space DPTRAM Control 12 bytes Reserved 8180 bytes DPTRAM 6 Kbytes QSMCM 4 Kbytes MIOS1 4 Kbytes TouCAN A 1 Kbyte TouCAN B 1 Kbyte Reserved 1920 bytes UIMB Registers 128 bytes Figure 2 MPC555 Internal Memory Map MPC555 Product Brief For More Information On This Product Go to www freescale com Ox2F C000 Ox2F C800 Ox2F C840 Ox2F C880 0x30 0000 0x30 2000 0x30 4000 0x30 4400 0x30 4800 0x30 4C00 0x30 5000 0x30 6000 0x30 7080 0x30 7480 0x30 7884 0x30 7F80 0x30 7FFF Freescale Semiconductor Inc Key Features MPC555 Pinout Diagram Figure 3 shows the pinout for the MPC555 3 Z OT UorSIoA aomod E ELON ZLOldW 90ldN amp Levan BDHDBEHE ES elvan 6L 8L ZOldN 23 OLON IMMAN OMA m s Zd S pem seeq L6 0t 6 3 35 5 L661 ASQWSAON TZ eBexped y jo do e si jnould ayy 9joN Od 69NVg EM vod seNva pesod Pre oevan vod eswva vod esuva badd erva vod
7. ny claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part lt freescale semiconductor MPC555PB D For More Information On This Product Go to www freescale com
8. ool Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or
9. rammable channels and pins Each channel has an event register consisting of a 16 bit capture register a 16 bit compare register and a 16 bit comparator Nine pre programmed timer functions are available Any channel can perform any time function Each timer function can be assigned to more than one channel Two timer count registers with programmable prescalers Each channel can be synchronized to one or both counters Selectable channel priority levels 5 V tolerant inputs outputs e 6 Kbyte dual port TPU RAM DPTRAM is shared by the two modules for TPU microcode 1 2 8 18 Channel Modular I O System MIOS1 e Ten double action submodules DASM e Eight dedicated PWM sub modules PWMSM e Two 16 bit modulus counter submodules MCSM e Two parallel port submodules PIOSM e 5 V tolerant inputs outputs 1 2 9 Two Queued Analog to Digital Converter Modules QADC64 Each QADC provides e Up to 16 analog input channels using internal multiplexing e Up to 41 total input channels using internal and external multiplexing e 10 bit A D converter with internal sample hold e Typical conversion time of 10 us 100 000 samples per second e Two conversion command queues of variable length e Automated queue modes initiated by External edge trigger level gate Software command e 64 result registers e Output data that is right or left justified signed or unsigned e 5 V reference and range 4 MP
10. rview AN1837 D Designing Expansion Boards for the Freescale EVB555 ETAS ES200 AN2001 D MPC555 Interrupts AN2109 D EMC Guidelines for MPC500 Based Automotive Powertrain Systems AN2127 D Nexus Standard Specification non Freescale document Nexus Web Site http www nexus5001 org IEEE 1149 1 Specification non Freescale document Revision History Table 2 Revision History Revision Number Substantive Changes Date of Release 2 Existing Document September 2001 2 1 Added temperature range for suffix A device 11 December 2002 3 Updated template and formats 11 February 2003 MPC555 Product Brief For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features THIS PAGE INTENTIONALLY LEFT BLANK MPC555 Product Brief 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features THIS PAGE INTENTIONALLY LEFT BLANK 10 MPC555 Product Brief For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features THIS PAGE INTENTIONALLY LEFT BLANK MPC555 Product Brief 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma Sch
11. to 16 devices Wrap around mode allows continuous sampling for efficient interfacing to serial peripherals e g serial A D converters I O latches etc Two serial communications interfaces SCI Each SCI offers these features UART mode provides NRZ format and half or full duplex interface 16 register receive buffer and 16 register transmit buffer SCII only Advanced error detection and optional parity generation and detection Word length programmable as 8 or 9 bits Separate transmitter and receiver enable bits and double buffering of data Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or a new address byte is received External source clock for baud generation Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs allowing realization of a low speed serial protocol MPC555 Product Brief 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features 2 MPC555 Address Map The internal memory map is shown in Figure 2 0x00 0000 CMF Flash A 256 Kbytes 0x04 0000 CMF Flash B 192 Kbytes 0x06 FFFF 0x07 0000 Reserved for Flash 2 6 Mbytes 16 Kbytes Ox2F BFFF Ox2F C000 USIU amp Flash Control Ox2F FFFF Dee 0x30 0000 UIMB Interface amp Modules 32 Kbytes 0x30 7FFF 0x30 8000 Reserved for IMB3 480 Kbytes 0x37 FFFF 0x38 0000
12. troller that supports up to eight external and eight internal interrupts IEEE 1149 1 JTAG test access port External bus interface 24 address pins 32 data pins Supports multiple master designs Four beat transfer bursts two clock minimum bus transactions Supports 5V inputs provides 3 3 V outputs 1 2 3 Flexible Memory Protection Unit Four instruction regions and four data regions 4 Kbyte to 16 Mbyte region size support Default attributes available in one global entry Attribute support for speculative accesses 1 2 4 448 Kbyte Flash EEPROM Memory One 256 Kbyte and one 192 Kbyte module Page read mode Block 32 Kbyte erasable External 4 75 V to 5 25 V program and erase power supply 1 2 5 26 Kbytes of Static RAM One 16 Kbyte and one 10 Kbyte module Fast one clock access Keep alive power Soft defect detection SDD 1 2 6 General Purpose I O Support Address 24 and data 32 pins can be used for general purpose I O in single chip mode Nine general purpose I O pins in MIOS1 unit Many peripheral pins can be used for general purpose I O when not used for primary function 5 V tolerant inputs outputs MPC555 Product Brief 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Key Features 1 2 7 Two Time Processor Units TPU3 e Each TPU3 module provides these features A dedicated micro engine operates independently of the RCPU 16 independent prog
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