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ATmega8(L)

1. Voc Device 1 Device 2 SLAVE MASTER Device 3 Device n R1 R2 TRANSMITTER RECEIVER SDA SCL To initiate the Slave Transmitter mode TWAR and TWCR must be initialized as follows TWAR TWA6 TWA5 TWAA TWA3 TWA2 TWA1 TWAO TWGCE value Device s Own Slave Address The upper seven bits are the address to which the Two wire Serial Interface will respond when addressed by a Master If the LSB is set the TWI will respond to the general call address 0x00 otherwise it will ignore the general call address TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI The TWEA bit must be written to one to enable the acknowledgement of the device s own slave address or the general call address TWSTA and TWSTO must be written to zero When TWAR and TWCR have been initialized the TWI waits until it is addressed by its own slave address or the general call address if enabled followed by the data direction bit If the direction bit is 1 read the TWI will operate in ST mode otherwise SR mode is entered After its own slave address and the write bit have been received the TWINT Flag is set and a valid status code can be read from TWSR The status code is used to determine the appropriate software action The appropriate action to be taken for each status
2. Power save Supply Current Figure 134 Power save Supply Current vs Voc Watchdog Timer Disabled POWER SAVE SUPPLY CURRENT vs Vcc WATCHDOG TIMER DISABLED 25 25 C 20 15 lcc UA 10 2 5 3 3 5 4 4 5 5 5 5 Voc V AMEL 257 2486R AVR 07 07 AMEL Standby Supply Current Figure 135 Standby Supply Current vs Voc 455 kHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Voc 455 kHz RESONATOR WATCHDOG TIMER DISABLED lcc uA A o Vcc V Figure 136 Standby Supply Current vs Vcc 1 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Vcc 1 MHz RESONATOR WATCHDOG TIMER DISABLED lcc uA Voc V 28 ATmega8 L mmm 2486R AVR 07 07 f 11 C025 Figure 137 Standby Supply Current vs Vcc 2 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Vcc 2 MHz RESONATOR WATCHDOG TIMER DISABLED 90 80 70 60 z 50 E 8 40 30 20 10 0 2 5 3 3 5 4 4 5 5 5 5 Voc V Figure 138 Standby Supply Current vs Vcc 2 MHz Xtal Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Vcc 2 MHz XTAL WATCHDOG TIMER DISABLED 90 80 70 60 50 Icc uA 40 30 20 10 2 5 3 3 5 4 4 5 5 5 5 Voc V
3. clk clk 8 cre TOP 1 TOP BOTTOM BOTTOM 1 OCRn TOP OCFn nes ATmega8 L m A megae8 L 8 bit Timer Counter Register Description Timer Counter Control Register TCCR2 BN i 6 2 3 2 1 0 Tecra Read Write W RW RW R W R W RW RW R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 FOC2 Force Output Compare The FOC2 bit is only active when the WGM bits specify a non PWM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCR2 is written when operating in PWM mode When writing a logical one to the FOC2 bit an immediate Compare Match is forced on the waveform generation unit The OC2 output is changed according to its COM21 0 bits setting Note that the FOC2 bit is implemented as a strobe Therefore it is the value present in the COM21 0 bits that determines the effect of the forced compare A FOC2 strobe will not generate any interrupt nor will it clear the timer in CTC mode using OCR2 as TOP The FOC2 bit is always read as zero Bit 6 3 WGM21 0 Waveform Generation Mode These bits control the counting sequence of the counter the source for the maximum TOP counter value and what type of waveform generation to be used Modes of oper ation supported by the Timer Counter unit are Normal mode Clear Timer on Compare Match CTC mode and tw
4. TCNTn MAX 1 MAX BOTTOM BOTTOM 1 TOVn AMEL n 2486R AVR 07 07 8 bit Timer Counter Register Description Timer Counter Control Register TCCRO Timer Counter Register TCNTO Timer Counter Interrupt Mask Register TIMSK AMEL Bit 7 6 5 4 3 2 1 0 Cee 69 T 699 recm Read Write R R R R R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 2 0 CS02 0 Clock Select The three clock select bits select the clock source to be used by the Timer Counter Table 34 Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source Timer Counter stopped 0 0 1 cIk o No prescaling 0 1 0 clk 9 8 From prescaler 0 1 1 clkyo 64 From prescaler 1 0 0 clkyo 256 From prescaler 1 0 1 clk o 1024 From prescaler 1 1 0 External clock source on TO pin Clock on falling edge 1 1 1 External clock source on TO pin Clock on rising edge If external pin modes are used for the Timer CounterO transitions on the TO pin will clock the counter even if the pin is configured as an output This feature allows software control of the counting Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Timer Counter Register gives direct access both for read and write operations to the Timer Counter unit 8 bit counter Bit 7 6 5 4 3 2 1 0 oct T oz nore ocr ones Tor rors tsk Read Write R
5. Voc V Figure 156 O Pin Input Threshold Voltage vs Vcc Vi I O Pin Read as 0 l O PIN INPUT THRESHOLD VOLTAGE vs Voc VIL IO PIN READ AS 0 40 C m 25 C p 85 C E _ nd 2 1 a o 9 E E 0 5 0 2 5 3 3 5 4 4 5 5 5 5 Vcc V xs ATmega8 L memm 2486R AVR 07 07 AT 11 C025 Figure 157 O Pin Input Hysteresis vs Voc 1 0 PIN INPUT HYSTERESIS vs Vcc 0 7 0 6 85 C 40 C a 0 5 25 C a 0 4 o E gt IT o3 Q 0 2 0 1 0 2 5 3 8 5 4 4 5 5 5 5 Voc V Figure 158 Reset Pin as I O Input Threshold Voltage vs Vcc Vi I O Pin Read as 4 j RESET PIN AS I O INPUT THRESHOLD VOLTAGE vs Vec VIH RESET PIN READ AS 1 40 C 85 C 25 C ke o o ie E Vcc V AMEL 269 2486R AVR 07 07 AMEL Figure 159 Reset Pin as I O Input Threshold Voltage vs Voc Vi I O Pin Read as 0 RESET PIN AS I O INPUT THRESHOLD VOLTAGE vs Vcc VIL RESET PIN READ AS 0 Threshold V Voc V Figure 160 Reset Pin as I O Pin Hysteresis vs Voc RESET PIN AS I O PIN HYSTERESIS vs Vcc Input Hysteresis V Voc V 270 ATmega8 L mmm 2486R AVR 07 07 Figure 161 Reset Input Threshold Voltage vs Voc Vi Reset Pin Read as 1
6. 0 2 5 3 3 5 4 45 5 5 5 Figure 186 Watchdog Timer Current vs Voc WATCHDOG TIMER CURRENT vs Vcc Icc UA AMEL 283 AMEL Figure 187 Analog Comparator Current vs Vec ANALOG COMPARATOR CURRENT vs Voc 100 85 C 25 C 80 40 C 70 60 50 8 i 40 30 20 10 0 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 188 Programming Current vs Voc PROGRAMMING CURRENT vs Vcc 7 40 C 6 25 C 5 85 C T4 8 3 2 1 0 2 5 3 3 5 4 4 5 5 5 5 Vcc V 284 ATmegae8 L EEEeye gt yxyee 2486R AVR 07 07 f mega8 L Current Consumption in Reset and Reset Pulsewidth 2486R AVR 07 07 Figure 189 Reset Supply Current vs Voc 0 1 1 0 MHz Excluding Current Through The Reset Pull up RESET SUPPLY CURRENT vs Voc 0 1 1 MHz EXCLUDING CURRENT THROUGH THE RESET PULL UP 4 5 5V 35 3 5 0V 4 5V 25 T 4 0V E 2 8 3 3V 3 0V 2 7V 0 5 0 0 0 1 0 2 0 8 04 0 5 0 6 07 0 8 0 9 1 Frequency MHz Figure 190 Reset Supply Current vs Vcc 1 20 MHz Excluding Current Through The Reset Pull up RESET SUPPLY CURRENT vs Vcc 1 20 MHz EXCLUDING CURRENT THROUGH THE RESET PULL UP 25 5 5V 20 5 0V 4 5V _ 15 lt x E 8 10 3 3V 5 3 0V 2 7V 0 0 2 4 6
7. Address Name Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 0x21 TWSR Tws7 TWS6 TWS5 Tws4 TWS3 TWPS1 TWPSO 173 0x00 0x20 TWBR Two wire Serial Interface Bit Rate Register 171 Notes 1 Refer to the USART description for details on how to access UBRRH and UCSRC 2 For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written 3 Some of the Status Flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will operate on all bits in the I O Register writing a one back into any flag read as set thus clearing the flag The CBI and SBI instructions work with registers 0x00 to Ox1F only 288 ATmegae8 L Ct __ 2486R AVR 07 07 X A megae8 L Instruction Set Summary 2486R AVR 07 07 EE Sj Mnemonics Operands Description Operation Flags Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd Rr Add two Registers Rd Rd Rr Z C N V H 1 ADC Rd Rr Add with Carry two Registers Rd Rd Rr C Z C N V H ADIW Rdl K Add Immediate to Word Rdh Rdl Rdh Rdl K Z C N V S 2 SUB Rd Rr Subtract two Registers Rd Rd Rr Z C N V H 1 SUBI Rd
8. Symbol Parameter Condition Min Typ Max Units xad ue rese 14 23 V Voltage rising Vpot Power on Reset Threshold 1 8 2 3 V Voltage falling Vast RESET Pin Threshold Voltage 0 2 0 9 Voc Minimum pulse width on ast RESET Pin meo Ms Brown out Reset Threshold BODLEVEL 1 2 4 2 6 2 9 V 2 V EPI MNA BODLEVEL 0 37 40 45 Minimum low voltage period for BODLEVEL 1 2 us t 7 BOD Brown out Detection BODLEVEL 0 2 us Vuyst Brown out Detector hysteresis 130 mV Notes 1 The Power on Reset will not work unless the supply voltage has been below Vpor falling Vgor may be below nominal minimum operating voltage for some devices For devices where this is the case the device is tested down to Vec Vgor during the production test This guarantees that a Brown out Reset will occur before Vo drops to a voltage where correct operation of the microcontroller is no longer guaranteed The test is performed using BODLEVEL 1 for ATnega8L and BODLEVEL 0 for ATmega8 BODLEVEL 1 is not applicable for ATmega8 ATlmega8 L memm 2486R AVR 07 07 f 11 C023 Power on Reset A Power on Reset POR pulse is generated by an On chip detection circuit The detec tion level is defined in Table 15 The POR is activated whenever Vo is below the detection level The POR circuit can be used to trigger the Start up Reset as well as to detect a failure in supply voltage A Power on Reset POR
9. ess 300 2486F 07 02 to Rev 2486G 09 02 eese 300 2486E 06 02 to Rev 2486F 07 02 sess 300 2486D 03 02 to Rev 2486E 00 02 sess 300 2486C 03 02 to Rev 2486D 03 02 esses 300 2486B 12 01 to Rev 2486C 03 02 esee 301 AIMEL aaa Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Fax 33 1 30 60 71 11 Product Contact Sales Contact www atmel com contacts Web Site Technical Support www atmel com avr Q atmel com Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE
10. CLT Clear T in SREG T lt 0 T 1 SEH Set Half Carry Flag in SREG Hei H 1 CLH Clear Half Carry Flag in SREG He0 H 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR timer None 1 AMEL 291 2486R AVR 07 07 AMEL Ordering Information Speed MHz Power Supply Ordering Code Package Operation Range ATmega8L 8AC 32A Commercial ATmega8L 8PC 28P3 0 C to 70 C ATmega8L 8MC 32M1 A ATmega sL 8Al 32A 8 2 7 5 5 ATmega8L 8AU 32A ATmega8L 8PI 28P3 Industrial ATmega8L 8PU 28P3 40 C to 85 C ATmega8L 8MI 32M1 A ATmega8L 8MU 32M1 A ATmega8 16AC 32A Commercial ATmega8 16PC 28P3 0 C to 70 C ATmega8 16MC 32M1 A ATmegas 16Al 32A 16 4 5 5 5 ATmega8 16AU2 32A ATmega8 16Pl 28P3 Industrial ATmega8 16PU 28P3 40 C to 85 C ATmega8 16MI 32M1 A ATmega8 16MU 32M1 A Notes 1 This device can also be supplied in wafer form Please contact your local Atmel sales office for detailed ordering information and minimum quantities 2 Pb free packaging alternative complies to the European Directive for Restriction of Hazardous Substances RoHS direc tive Also Halide free and fully Green Package Type 32A 32 lead Thin 1 0 mm Plastic Quad Flat Package TQFP 28P3 28 lead 0 300 Wide Plastic Dual Inline Package PDIP 32M1 A 32 pad 5 x 5 x 1 0 body Lead P
11. 132 DS ELT E ta M IIT MM DE E C MIR 133 jui 133 Clock Generatio sssini en 134 Fram Formals ineeie niaaa aereis ae AA Ra ekee aed 137 USART Initialization 2 5 itin aenea a cune 138 Data Transmission The USART Transmitter sssseeeeseeese 140 Data Reception The USART Receiver sssssseeeeeeeeenee nen 143 Asynchronous Data Reception ssssesssseseeeemeeen memes 147 Multi processor Communication Mode sssseseeeeneeeeennn 151 Accessing UBRRH UCSRC Registers esssssseeseeeerenees 152 USART Register Description sssssesesseseseeeeeeenneennenn nnns 153 Examples of Baud Rate Setting 159 Two wire Serial Interface ceo eee eese ee rennen 163 aur 163 Two wire Serial Interface Bus Definition sssseeseeeeee 163 Data Transfer and Frame Format sssseeseeeeeneenn menn 164 Multi master Bus Systems Arbitration and Synchronization 167 Overview of the TWI Module sssssseseseeeeeeeenenneen nennen nnne nnne 169 TWI Register Description 171 BETIDRUIAPUUE 174 Transmission Modes einen creen sereni cente an se ca Coa cR e nae 178 Multi master Systems and Arbitration seses
12. B oue m COMMON DIMENSIONS 0 15 REF Unit of Measure mm C RM eee ua Des SYMBOL MIN NOM MAX A 4 5724 A1 34 798 8 255 7 493 0 533 1 397 eB Note 1 Dimensions D and E1 do not include mold Flash or Protrusion Mold Flash or Protrusion shall not exceed 0 25 mm 0 010 1 143 3 429 m 0 356 10 160 2 540 TYP 09 28 01 TITLE DRAWING NO REV IMEL 2325 Orchard Parkway 28P3 28 lead 0 300 7 62 mm Wide Plastic Dual AIMEL San Jose CA 95131 Inline Package PDIP 24 ATmega8s L 2486R AVR 07 07 m f 1 C023 32M1 A SIDE VIEW TOP VIEW COMMON DIMENSIONS Unit of Measure mm MIN 0 80 NOM 0 90 MAX 1 00 0 02 0 05 0 65 1 00 0 20 REF 0 23 0 30 5 00 5 10 4 75 4 80 3 10 3 25 5 00 5 10 4 75 4 80 BOTTOM VIEW 3 10 3 25 0 50 BSC 0 40 0 50 Note JEDEC Standard MO 220 Fig 2 Anvil Singulation VHHD 2 TITLE AMEL 2325 Orchard Parkway 32M1 A 32 pad 5 x 5 x 1 0 mm Body Lead Pitch 0 50 mm San Jose CA 95131 5 10 mm Exposed Pad Micro Lead Frame Package MLF AMEL 2486R AVR 07 07 5 25 06 DRAWING NO REV 295 Erratas ATmega8 Rev D tol AMEL T
13. 2 i z z B 3 i4 iva 5 End RWW 5 End RWW E Start NRWW Ei Start NRWW o o 2 Application Flash Section 2 Application Flash Section 3 2 End Application n End Application E ENS Start Boot Loader z oot Loader Flash Section 8 Boot Loader Flash Section Start Boot Loader 8 s Flashend a Flashend o o z zZ Program Memory Program Memory BOOTSZ 01 BOOTSZ 00 0000 0000 c c Sg 9 9 o o o o 7 2 Application Flash Section E Application flash Section z o S iS z o o c Oo o o 5 End RWW S End RWW End Application 9 Start NRWW 5 Start NRWW Start Boot Loader o o 2 Application Flash Section o End Application 2 Stait Boot Loader Boot Loader Flash Section z Boot Loader Flash Section 9 c c Flashend Flashend o o z z Note 1 The parameters in the figure are given in Table 82 on page 220 If no Boot Loader capability is needed the entire Flash is available for application code The Boot Loader has two separate sets of Boot Lock Bits which can be set indepen dently This gives the user a unique flexibility to select different levels of protection The user can select e To protect the entire Flash from a software update by the MCU e To protect only the Boot Loader Flash section from a software update by the MCU e To protect only the Application Flash section from a software update by the MCU Allow software update in the entire Flash See Table 78 and Table 79 for
14. 2486R AVR 07 07 AT 11 C025 Output Compare Units 2486R AVR 07 07 ICF1 must be cleared by software writing a logical one to the I O bit location For measuring frequency only the clearing of the ICF1 Flag is not required if an interrupt handler is used The 16 bit comparator continuously compares TCNT1 with the Output Compare Regis ter OCR1x If TCNT equals OCR1x the comparator signals a match A match will set the Output Compare Flag OCF1x at the next timer clock cycle If enabled OCIE1x 1 the Output Compare Flag generates an Output Compare interrupt The OCF1x Flag is automatically cleared when the interrupt is executed Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I O bit location The waveform generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode WGM13 0 bits and Compare Output mode COM1x1 0 bits The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation See Modes of Operation on page 88 A special feature of Output Compare unit A allows it to define the Timer Counter TOP value i e counter resolution In addition to the counter resolution the TOP value defines the period time for waveforms generated by the waveform generator Figure 35 shows a block diagram of the Output Compare unit Th
15. 6 9 6 7 6 5 60 40 20 0 20 40 60 80 100 Temperature C AMEL 275 2486R AVR 07 07 Figure 17 8 5 8 3 8 1 7 9 7 7 7 5 Fro MHz 7 3 74 6 9 6 7 6 5 AMEL 1 Calibrated 8 MHz RC Oscillator Frequency vs Voc CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs Vcc 40 C 25 C 85 C 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 172 Calibrated 8 MHz RC Oscillator Frequency vs Osccal Value 276 CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 96 112 128 144 192 208 224 240 OSCCAL VALUE 32 48 64 80 160 176 ATmega8 L memm 2486R AVR 07 07 A mega8 L Figure 173 Calibrated 4 MHz RC Oscillator Frequency vs Temperature CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 4 2 5 5V 4 1 4 0V 4 RN 3 9 z 2 7V g uw 38 3 7 3 6 3 5 60 40 20 0 20 40 60 80 Temperature C Figure 174 Calibrated 4 MHz RC Oscillator Frequency vs Voc CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs Voc 100 4 2 40 C 4 1 25 C 4 85 C N 3 9 I z o i 38 3 7 3 6 3 5 2 5 3 3 5 4 4 5 5 55 Vcc V 277 AMEL 2486R AVR 07 07 278 ATmega8 L AMEL Figure 175 Calibrated 4 MHz RC Oscillator Frequency vs Osccal Value CALIBRATED 4MHz RC OSC
16. Note 1 See About Code Examples on page 8 The receive function example reads all the I O Registers into the Register File before any computation is done This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible AMEL 145 2486R AVR 07 07 Receive Compete Flag and Interrupt Receiver Error Flags AMEL The USART Receiver has one flag that indicates the Receiver state The Receive Complete RXC Flag indicates if there are unread data present in the receive buffer This flag is one when unread data exist in the receive buffer and zero when the receive buffer is empty i e does not contain any unread data If the Receiver is disabled RXEN 0 the receive buffer will be flushed and consequently the RXC bit will become zero When the Receive Complete Interrupt Enable RXCIE in UCSRB is set the USART Receive Complete Interrupt will be executed as long as the RXC Flag is set provided that global interrupts are enabled When interrupt driven data reception is used the receive complete routine must read the received data from UDR in order to clear the RXC Flag otherwise a new interrupt will occur once the interrupt routine terminates The USART Receiver has three error flags Frame Error FE Data OverRun DOR and Parity Error PE All can be accessed by reading UCSRA Common for the error flags is that they are located in the receive buffe
17. T9 we Read Write R W R W R W R W R W R W R R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 OCIE2 Timer Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I bit in the Status Register is set one the Timer Counter2 Compare Match interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer Counter2 occurs i e when the OCF2 bit is set in the Timer Counter Interrupt Flag Register TIFR e Bit 6 TOIE2 Timer Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I bit in the Status Register is set one the Timer Counter2 Overflow interrupt is enabled The corresponding interrupt is executed if an overflow in Timer Counter2 occurs i e when the TOV2 bit is set in the Timer Counter Interrupt Flag Register TIFR Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 ENTE TOVO TIFR Read Write R W R W R W R W R W R W R R W Initial Value 0 0 0 0 0 0 0 0 e Bit 7 OCF2 Output Compare Flag 2 The OCF2 bit is set one when a Compare Match occurs between the Timer Counter2 and the data in OCR2 Output Compare Register2 OCF2 is cleared by hardware when executing the corresponding interrupt Handling Vector Alternatively OCF2 is cleared by writing a logic one to the flag When the I bit in SREG OCIE2 Timer Counter2 Com pare Match Interrupt Enable and OCF2 are set one the Timer Counter2 Compare Match Interrupt is execu
18. TOVn Interrupt Flag Set Yy M Y Y Y TCNTn Y yoy Y Y Y OCn COMn1 0 2 OCn m COMn1 0 3 Period 1 pl 2 k 3 The Timer Counter Overflow Flag TOV2 is set each time the counter reaches BOT TOM The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value In phase correct PWM mode the compare unit allows generation of PWM waveforms on the OC2 pin Setting the COM21 0 bits to 2 will produce a non inverted PWM An inverted PWM output can be generated by setting the COM21 0 to 3 see Table 45 on page 118 The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output The PWM waveform is generated by clearing or setting the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments and setting or clearing the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements The PWM frequency for the output when using phase correct PWM can be calculated by the following equation _ fako focnPCPWM T N 510 The N variable represents the prescale factor 1 8 32 64 128 256 or 1024 The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode If the OCR2 is set equal to BOTTOM the output will be continuously low and if set eq
19. RESET INPUT THRESHOLD VOLTAGE vs Vcc VIH RESET PIN READ AS 1 2 5 3 40 C 25 C 85 C S15 E o E 7 o E o 0 5 0 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 162 Reset Input Threshold Voltage vs Vcc Vi Reset Pin Read as 0 RESET INPUT THRESHOLD VOLTAGE vs Voc VIL RESET PIN READ AS 0 85 C 25 C 40 C Threshold V Voc V AIMEL 271 2486R AVR 07 07 ur AMEL Figure 163 Reset Input Pin Hysteresis vs Vcc RESET INPUT PIN HYSTERESIS vs Vcc 0 8 o o o m Input Hysteresis V 0 2 Voc V Bod Thresholds and Analog Figure 164 BOD Thresholds vs Temperature BOD Level is 4 0V Comparator Offset BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 4 0V Threshold V 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C 72 ATmega8 L mmm 2486R AVR 07 07 X f mega8 L Figure 165 BOD Thresholds vs Temperature BOD Level is 2 7v BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 2 7V 2 8 27 Rising Vcc Zz 2 26 7 o Ez L L L LL dL aL ee S a Falling Vcc 25 24 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Figure 166 Bandgap Voltage vs Voc BANDGAP VOLTAGE vs Vec 1 815 1 31 40
20. e Bit6 WCOL Write COLlision Flag The WCOL bit is set if the SPI Data Register SPDR is written during a data transfer The WCOL bit and the SPIF bit are cleared by first reading the SPI Status Register with WCOL set and then accessing the SPI Data Register Bit 5 1 Res Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero Bit 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed SCK Frequency will be doubled when the SPI is in Master mode see Table 50 This means that the minimum SCK period will be 2 CPU clock periods When the SPI is configured as Slave the SPI is only guaran teed to work at f 4 or lower The SPI interface on the ATmega8 is also used for Program memory and EEPROM downloading or uploading See page 237 for Serial Programming and verification Bit 7 6 5 4 3 2 1 0 Cass SPOR Read Write R W R W R W R W R W R W R W R W Initial Value X X X X X X X X Undefined The SPI Data Register is a Read Write Register used for data transfer between the Reg ister File and the SPI Shift Register Writing to the register initiates data transmission Reading the register causes the Shift Register Receive buffer to be read AMEL 131 AMEL Data Modes There are four combinations of SCK phase and polarity with respect to serial data 132 which are determined by control bits CPHA and CPOL The SPI data transfer formats are shown in Figure 59
21. 1 or can be programmed 0 to obtain the additional features listed in Table 86 The Lock Bits can only be erased to 1 with the Chip Erase command Table 85 Lock Bit Byte Lock Bit Byte Bit No Description Default Value 7 1 unprogrammed 6 1 unprogrammed BLB12 5 Boot lock bit 1 unprogrammed BLB11 4 Boot lock bit 1 unprogrammed BLBO2 3 Boot lock bit 1 unprogrammed BLBO1 2 Boot lock bit 1 unprogrammed LB2 1 Lock bit 1 unprogrammed LB1 0 Lock bit 1 unprogrammed Note 1 1 means unprogrammed 0 means programmed Table 86 Lock Bit Protection Modes LB Mode Memory Lock Bits LB2 LB1 Protection Type 1 1 1 No memory lock features enabled Further programming of the Flash and EEPROM is disabled in Parallel and Serial Programming mode The Fuse Bits are locked in both Serial and Parallel Programming mode Further programming and verification of the Flash and EEPROM is disabled in parallel and Serial Programming mode The Fuse Bits are locked in both Serial and Parallel Programming modes BLBO Mode BLBO2 BLBO1 No restrictions for SPM or LPM accessing the Application section SPM is not allowed to write to the Application section SPM is not allowed to write to the Application section and LPM executing from the Boot Loader section is not allowed to read from the Application section If
22. 2486R AVR 07 07 to 3 See Table 38 on page 98 The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output DDR OC1x The PWM waveform is generated by setting or clearing the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments and clearing or setting the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation foko focnxPFCPWM 2 N TOP The N variable represents the prescaler divider 1 8 64 256 or 1024 The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non inverted PWM mode For inverted PWM the output will have the opposite logic values If OCR1A is used to define the TOP value WGM13 0 9 and COM1A1 0 1 the OC1A output will toggle with a 50 duty cycle The Timer Counter is a synchronous design and the timer clock clk is therefore shown as a clock enable signal in the following figures The figures include information on when Interrupt Flags are set and when the OCR1x Register is updated with the OCR1x buffer value only for modes utilizing double buffering Fig
23. AMEL s Unconnected pins Alternate Port Functions AMEL If some pins are unused it is recommended to ensure that these pins have a defined level Even though most of the digital inputs are disabled in the deep sleep modes as described above floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled Reset Active mode and Idle mode The simplest method to ensure a defined level of an unused pin is to enable the internal pull up In this case the pull up will be disabled during reset If low power consumption during reset is important it is recommended to use an external pull up or pull down Connecting unused pins directly to Vec or GND is not recommended since this may cause excessive currents if the pin is accidentally configured as an output Most port pins have alternate functions in addition to being general digital I Os Figure 25 shows how the port pin control signals from the simplified Figure 22 can be overrid den by alternate functions The overriding signals may not be present in all port pins but the figure serves as a generic description applicable to all port pins in the AVR micro controller family Figure 25 Alternate Port Functions PUOExn PUOVxn o C PUD DDOExn DDOVxn WDx PVOExn PVOVxn e El m lt a SYNCHRONIZER KS es gt K D PINxn L L an O Pa clk yo Ea Dixn AlOxn PUOExn Pxn PUL
24. For the ATmega8 the signature bytes are 1 0x000 Ox1E indicates manufactured by Atmel 2 0x001 0x93 indicates 8KB Flash memory 3 0x002 0x07 indicates ATmega8 device The ATmega8 stores four different calibration values for the internal RC Oscillator These bytes resides in the signature row High byte of the addresses 0x0000 0x0001 0x0002 and 0x0003 for 1 2 4 and 8 Mhz respectively During Reset the 1 MHz value is automatically loaded into the OSCCAL Register If other frequencies are used the calibration value has to be loaded manually see Oscillator Calibration Register OSC CAL on page 31 for details Table 89 No of Words in a Page and no of Pages in the Flash FlashSize Page Size PCWORD No of Pages PCPAGE PCMSB 4K words 8K bytes 32 words PC 4 0 128 PC 11 5 11 Table 90 No of Words in a Page and no of Pages in the EEPROM EEPROM Size PCWORD No ofPages PCPAGE EEAMSB 512 bytes 4 bytes EEA 1 0 128 EEA 8 2 8 AMEL 225 Parallel Programming Parameters Pin Mapping and Commands Signal Names AMEL This section describes how to parallel program and verify Flash Program memory EEPROM Data memory Memory Lock Bits and Fuse Bits in the ATmega8 Pulses are assumed to be at least 250 ns unless otherwise noted In this section some pins of the ATmega8 are referenced by signal names describing their functionality during parallel programming see Figure 104 and Ta
25. In order to prevent unintentional EEPROM writes a specific write procedure must be fol lowed Refer to the description of the EEPROM Control Register for details on this When the EEPROM is read the CPU is halted for four clock cycles before the next instruction is executed When the EEPROM is written the CPU is halted for two clock cycles before the next instruction is executed AMEL i The EEPROM Address Register EEARH and EEARL The EEPROM Data Register EEDR The EEPROM Control Register EECR AMEL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write R R R R R R R R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 X X X X X X X X e Bits 15 9 Res Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero Bits 8 0 EEAR8 0 EEPROM Address The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space The EEPROM data bytes are addressed lin early between 0 and 511 The initial value of EEAR is undefined A proper value must be written before the EEPROM may be accessed Bit 7 6 5 4 3 2 1 0 E EDR Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bits 7 0 EEDRT 0 EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register For the EEPROM read oper ation the EEDR contains the data read o
26. Ss SCK CPOL 0 SCK CPOL 1 MISO Data Input MOSI Data Output Figure 117 SPI interface timing requirements Slave Mode SCK CPOL 0 SCK CPOL 1 MOSI Data Input MISO Data Output 2486R AVR 07 07 AMEL 247 ADC Characteristics Table 103 ADC Characteristics AMEL Symbol Parameter Condition Min Typ Max Units Resolution Single Ended Conversion 10 Bits Single Ended Conversion Absolute accuracy Vier 4V Voc 4V S LSB Including INL DNL ADC clock 200 kHz Quantization Error Gain Single Ended Conversion and Offset Error Vaer 4V Voc 4V 3 LSB ADC clock 1 MHz Single Ended Conversion VREF 4V Vec 4V Integral Non linearity INL ADC clock 200 kHz 0 75 LSB Single Ended Conversion Differential Non linearity Vrer 4V Voc 4V DNL ADC clock 200 kHz 0 5 LSB Gain Error Single Ended Conversion 1 LSB VREF 4V Vec 4V ADC clock 200 kHz Offset Error Single Ended Conversion 1 LSB Vner 4V Vec 4V ADC clock 200 kHz Conversion Time Free Running Conversion 13 260 us Clock Frequency 50 1000 kHz AVcc Analog Supply Voltage Voc 0 30 Vcc 0 39 V VREF Reference Voltage 2 0 AVcc V Vin Input voltage GND VREF V Input bandwidth 38 5 kHz Vint Internal Voltage Reference 2 3 2 56 2 7 V Rner Reference Input Resistance 32 kQ Rain Analog Input Resistance 55 100 M
27. 1 Mbps 2 Mbps 1 152 Mbps 2 304 Mbps 1 25 Mbps 2 5 Mbps 1 UBRR 0 Error 0 0 162 ATmega8 L memm 2486R AVR 07 07 w Armega8 L Two wire Serial Interface Features Simple Yet Powerful and Flexible Communication Interface only two Bus Lines Needed Both Master and Slave Operation Supported Device can Operate as Transmitter or Receiver 7 bit Address Space Allows up to 128 Different Slave Addresses Multi master Arbitration Support Up to 400 kHz Data Transfer Speed Slew rate Limited Output Drivers Noise Suppression Circuitry Rejects Spikes on Bus Lines Fully Programmable Slave Address with General Call Support Address Recognition Causes Wake up When AVR is in Sleep Mode Two wire Serial Interface The Two wire Serial Interface TWI is ideally suited for typical microcontroller applica Bus Definition tions The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi directional bus lines one for clock SCL and one for data SDA The only external hardware needed to implement the bus is a single pull up resistor for each of the TWI bus lines All devices connected to the bus have individual addresses and mechanisms for resolving bus contention are inherent in the TWI protocol Figure 68 TWI Bus Interconnection Voc Device 1 Device 2 Device 3 Device n R1 R2 SDA SCL q gt TWI Terminology The f
28. 4 1 ms Fast rising power or BOD enabled 01 1K CK 65 ms Slowly rising power 10 32K CK 65 ms Stable frequency at start up 11 Reserved Note 1 These options should only be used if frequency stability at start up is not important for the application 28 ATmega8 L mmm 2486R AVR 07 07 X f mega8 L External RC Oscillator 2486R AVR 07 07 For timing insensitive applications the external RC configuration shown in Figure 12 can be used The frequency is roughly estimated by the equation f 1 3RC C should be at least 22 pF By programming the CKOPT Fuse the user can enable an internal 36 pF capacitor between XTAL1 and GND thereby removing the need for an external capacitor Figure 12 External RC Configuration Voc A R NC JXTAL2 XTAL1 Gas GND The Oscillator can operate in four different modes each optimized for a specific fre quency range The operating mode is selected by the fuses CKSEL3 0 as shown in Table 7 Table 7 External RC Oscillator Operating Modes CKSEL3 0 Frequency Range MHz 0101 0 1 0 9 0110 0 9 3 0 0111 3 0 8 0 1000 8 0 12 0 When this Oscillator is selected start up times are determined by the SUT Fuses as shown in Table 8 Table 8 Start up Times for the External RC Oscillator Clock Selection Start up Time from Additional Delay Power down and
29. 78 X BO states in slave mode gor n Any number of data bytes From master to slave DATA A and their associated acknowledge bits From slave to master This number contained in TWSR corresponds to a defined state of the Two Wire Serial Bus The prescaler bits are zero or masked to zero Slave Receiver Mode In the Slave Receiver mode a number of data bytes are received from a Master Trans 184 mitter see Figure 82 All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero Figure 82 Data transfer in Slave Receiver mode cc Device 1 Device 2 g SLAVE MASTER Device 3 Device n R1 R2 RECEIVER TRANSMITTER SDA SCL To initiate the Slave Receiver mode TWAR and TWCR must be initialized as follows TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWAO TWGCE value Device s Own Slave Address ATmega8 L mmx 2486R AVR 07 07 A megae8 L 2486R AVR 07 07 The upper 7 bits are the address to which the Two wire Serial Interface will respond when addressed by a Master If the LSB is set the TWI will respond to the general call address 0x00 otherwise it will ignore the general call address TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI The TWEA bit must be written to one to enable the
30. The double buffered Output Compare Registers OCR1A B are compared with the Timer Counter value at all time The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin OC1A B See Output Compare Units on page 85 The Compare Match event will also AMEL 2486R AVR 07 07 AMEL set the Compare Match Flag OCF1A B which can be used to generate an Output Compare interrupt request The Input Capture Register can capture the Timer Counter value at a given external edge triggered event on either the Input Capture Pin ICP1 or on the Analog Compar ator pins see Analog Comparator on page 193 The Input Capture unit includes a digital filtering unit Noise Canceler for reducing the chance of capturing noise spikes The TOP value or maximum Timer Counter value can in some modes of operation be defined by either the OCR1A Register the ICR1 Register or by a set of fixed values When using OCR1A as TOP value in a PWM mode the OCR1A Register can not be used for generating a PWM output However the TOP value will in this case be double buffered allowing the TOP value to be changed in run time If a fixed TOP value is required the ICR1 Register can be used as an alternative freeing the OCR1A to be used as PWM output Definitions The following definitions are used extensively throughout the document Table 35 Definitions BOTTOM T
31. Asynchronous Operation of the Timer Counter Asynchronous Status Register ASSR 2486R AVR 07 07 Bit 2 0 CS22 0 Clock Select The three clock select bits select the clock source to be used by the Timer Counter see Table 46 Table 46 Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source Timer Counter stopped 0 0 1 ClKrog No prescaling 0 1 0 ClKy55 8 From prescaler 0 1 1 Clkr54 32 From prescaler 1 0 0 ClKkr55 64 From prescaler 1 0 1 Clkr54 128 From prescaler 1 1 0 ClKy54 256 From prescaler 1 1 1 Clky54 1024 From prescaler Bit 7 6 5 4 3 2 1 0 TCNT2 7 0 TCNT2 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Timer Counter Register gives direct access both for read and write operations to the Timer Counter unit 8 bit counter Writing to the TCNT2 Register blocks removes the Compare Match on the following timer clock Modifying the counter TCNT2 while the counter is running introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register Bit 7 6 5 4 3 2 1 0 OCR2 7 0 OCR2 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register contains an 8 bit value that is continuously compared with the counter value TCNT2 A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC2 pin Bit 7 6 5 4 3
32. E 1 305 85 E 25 a S o 1 3 oO a 1 295 1 29 2 5 8 8 5 4 4 5 5 5 5 Vcc V AMEL 273 2486R AVR 07 07 AMEL Figure 167 Analog Comparator Offset Voltage vs Common Mode Voltage Vgc 5V ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Voc 5V 0 003 0 002 0 001 o 0 001 85 0 002 0 003 Comparator Offset Voltage V 25 0 004 0 005 40 0 006 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 Common Mode Voltage V Figure 168 Analog Comparator Offset Voltage vs Common Mode Voltage Vec 2 7V ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Vcc 2 7V 0 003 0 002 0 001 0 001 85 0 002 25 Comparator Offset Voltage V 0 003 0 004 40 0 005 0 0 5 1 1 5 2 2 5 3 Common Mode Voltage V 24 ATlmega8 L memm ATmega8 L Internal Oscillator Speed Figure 169 Watchdog Oscillator Frequency vs Voc WATCHDOG OSCILLATOR FREQUENCY vs Vcc 1260 40 C 1240 25 C 85 C 1220 1200 E 1180 o c 1160 1140 1120 1100 ee oo po pL Ll 2 5 3 3 5 4 4 5 5 5 5 Voc V Figure 170 Calibrated 8 MHz RC Oscillator Frequency vs Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 8 5 5 5V 8 3 8 1 4 0V 7 9 7 7 7 5 2 7V Fro MHz 7 3 74
33. Figure 70 START REPEATED START and STOP conditions START STOP START REPEATED START STOP All address packets transmitted on the TWI bus are 9 bits long consisting of 7 address bits one READ WRITE control bit and an acknowledge bit If the READ WRITE bit is set a read operation is to be performed otherwise a write operation should be per formed When a Slave recognizes that it is being addressed it should acknowledge by pulling SDA low in the ninth SCL ACK cycle If the addressed Slave is busy or for some other reason can not service the Master s request the SDA line should be left high in the ACK clock cycle The Master can then transmit a STOP condition or a REPEATED START condition to initiate a new transmission An address packet consist ing of a slave address and a READ or a WRITE bit is called SLA R or SLA W respectively The MSB of the address byte is transmitted first Slave addresses can freely be allo cated by the designer but the address 0000 000 is reserved for a general call When a general call is issued all slaves should respond by pulling the SDA line low in the ACK cycle A general call is used when a Master wishes to transmit the same mes sage to several slaves in the system When the general call address followed by a Write bit is transmitted on the bus all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle The following data packets will then be received by all the
34. SLAW Load SLA_W into TWDR Register out TWDR r16 TWCR 1 TWINT 1 lt lt TWEN Clear TWINT bit in TWCR to start ldi r16 1 lt lt TWINT 1 lt lt TWEN transmission of address out TWCR r16 4 wait2 while TWCR amp 1 TWINT Wait for TWINT Flag set This in r16 TWCR indicates that the SLA W has been sbrs r16 TWINT transmitted and ACK NACK has i been received rjmp wait2 5 in r16 TWSR if TWSR amp OxF8 Check value of TWI Status andi r16 OxF8 MT SLA ACK Register Mask prescaler bits If cpi r16 MT SLA ACK ERROR status different from MT SLA ACK go to ERROR brne ERROR ldi r16 DATA TWDR DATA Load DATA into TWDR Register out TWDR r16 TWCR 1 lt lt TWINT 1 TWEN Clear TWINT bit in TWCR to start ldi r16 1 lt lt TWINT 1 TWEN transmission of data out TWCR r16 6 wait3 while TWCR amp 1 lt lt TWINT Wait for TWINT Flag set This in r16 TWCR indicates that the DATA has been sbrs r16 TWINT transmitted and ACK NACK has been received rjmp wait3 7 in r16 TWSR if TWSR amp OxF8 Check value of TWI Status andi r16 OxF8 MT DATA ACK Register Mask prescaler bits If cpi r16 MT DATA ACK ERROR status different from MT DATA ACK go to ERROR brne ERROR ldi r16 1 lt lt TWINT 1 lt lt TWEN TWCR 1 lt lt TWINT 1 lt lt TWEN Transmit STOP condition 1 lt lt TWSTO 1 lt lt TWSTO out TWCR r16 AMEL 177 2486R AVR 07 0
35. TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM 8 bit OxOOFF BOTTOM TOP 6 0 1 1 0 Fast PWM 9 bit OxO1FF BOTTOM TOP 7 0 1 1 1 Fast PWM 10 bit Ox03FF BOTTOM TOP 8 1 0 0 0 PWM Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 Reserved 14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP 15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP Note 1 The CTC1 and PWM11 0 bit definition names are obsolete Use the WGM12 0 definitions However the functionality and location of these bits are compatible with previous versions of the timer 2486R AVR 07 07 AMEL 99 Timer Counter 1 Control Register B TCCR1B AMEL Bit 7 6 5 4 3 2 1 0 ccr T icEsr wowrs wowiz csz T Gsm 69m Tceme Read Write R W R W R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 ICNC1 Input Capture Noise Canceler Setting this bit to one activates the Input Capture Noise Canceler When the noise can celer is activated the input from the Input Capture Pin ICP1 is filtered The filter function requires four successive equal valued samples of the ICP1 pin for changing its output The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled Bit 6 ICES1 Inpu
36. bor XTAL1 BS1 DATA ADDRO Low Byte DATA Low Byte DATA High Byte ADDR1 Low Byte XAO P d N XA1 N S N Note 1 The timing requirements shown in Figure 109 i e tpyxq txyxL and tj px also apply to reading operation Table 95 Parallel Programming Characteristics Voc 5V 10 Symbol Parameter Min Typ Max Units Vpp Programming Enable Voltage 11 5 12 5 V lpp Programming Enable Current 250 pA tovxH Data and Control Valid before XTAL1 High 67 ns tyLxH XTAL1 Low to XTAL1 High 200 ns iux XTAL1 Pulse Width High 150 ns bx px Data and Control Hold after XTAL1 Low 67 ns t wL XTAL1 Low to WR Low 0 ns ba pH XTAL1 Low to PAGEL high 0 ns ipi xpi PAGEL low to XTAL1 high 150 ns tBvPH BS1 Valid before PAGEL High 67 ns tpHPL PAGEL Pulse Width High 150 ns tpi Bx BS1 Hold after PAGEL Low 67 ns twi Bx BS2 1 Hold after WR Low 67 ns te wL PAGEL Low to WR Low 67 ns tevwL BS1 Valid to WR Low 67 ns twi wH WR Pulse Width Low 150 ns tWLRL WR Low to RDY BSY Low 0 1 Ls lush WR Low to RDY BSY High 3 7 4 5 ms twuRH ce WR Low to RDY BSY High for Chip Erase 7 5 9 ms txLoL XTAL1 Low to OE Low 0 ns AMEL 235 AMEL Table 95 Parallel Programming Characteristics Voc 5V 10 Continued Symbol Parameter Min Typ Max Units tgvpv BS1 Valid to DATA valid 0 250 ns toi pv OE Low to DATA Valid 250 ns toupz OE High to DATA Tri st
37. c05 sei Enable interrupts c06 instr xxx 48 ATmegae8 L E SSS Sa 2486R AVR 07 07 A megae8 L When the BOOTRST Fuse is programmed the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled the most typical and general program setup for the Reset and Interrupt Vector Addresses is AddressLabels Code Comments org c00 c00 rjmp RESET Reset handler c01 rjmp EXT INTO IRQO Handler c02 rjmp EXT INT1 IRQ1 Handler c12 rjmp SPM RDY Store Program Memory Ready Handler c13 RESET ldi r16 high RAMEND Main program start c14 out SPH r16 Set Stack Pointer to top of RAM c15 ldi r16 low RAMEND c16 out SPL r16 c17 sei Enable interrupts c18 instr xxx Moving Interrupts Between The General Interrupt Control Register controls the placement of the Interrupt Vector Application and Boot Space table General Interrupt Control Register GICR Bit 7 6 5 4 3 2 1 0 Wr T Wm T 1 TI L LET ec Read Write R W R W R R R R R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 1 IVSEL Interrupt Vector Select When the IVSEL bit is cleared zero the Interrupt Vectors are placed at the start of the Flash memory When this bit is set one the Interrupt Vectors are moved to the begin ning of the Boot Loader section of the Flash The actual address of the start of the boot Flash section is determined by the BOOTSZ Fuses Re
38. ferential current drawn by the Watchdog Timer Figure 118 Active Supply Current vs Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs FREQUENCY 0 1 1 0 MHz 5 5V 5 0V 4 5V 4 0V 3 3V 3 0V 2 7V 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz AMEL 249 250 Figure 119 Active Supply Current vs Frequency 1 20 MHz 30 25 20 15 lcc mA 10 18 16 14 12 10 lcc mA AMEL ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 5 5V 5 0V 4 5V 3 3V 3 0 2 7V 4 6 8 10 12 14 16 18 20 Frequency MHz Figure 120 Active Supply Current vs Voc Internal RC Oscillator 8 MHz ACTIVE SUPPLY CURRENT vs Vcc NTERNAL RC OSCILLATOR 8 MHz 40 C 25 C 85 C 2 5 3 3 5 4 4 5 5 5 Voc V ATlmega8 L memm 2486R AVR 07 07 A 11 C025 Figure 121 Active Supply Current vs Vcc Internal RC Oscillator 4 MHz ACTIVE SUPPLY CURRENT vs Vcc NTERNAL RC OSCILLATOR 4 MHz 40 C 25 C 85 C ES E 8 Vcc V Figure 122 Active Supply Current vs Vec Internal RC Oscillator 2 MHz ACTIVE SUPPLY CURRENT vs Vcc INTERNAL RC OSCILLATOR 2 MHz 6 25 C Icc mA 2 5 3 3 5 4 4 5 5 5 5 Voc V AMEL 251 2486R AVR 07 07 252 AMEL Figure 123 Active Supply Cu
39. location USART Register Description USART I O Data Register UDR Bit 7 6 5 4 3 2 1 0 UDR Read TXB 7 0 UDR Write Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I O address referred to as USART Data Register or UDR The Transmit Data Buffer Register TXB will be the destination for data written to the UDR Register location Reading the UDR Register location will return the contents of the Receive Data Buffer Register RXB For 5 6 or 7 bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver AMEL 153 2486R AVR 07 07 USART Control and Status Register A UCSRA AMEL The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set Data written to UDR when the UDRE Flag is not set will be ignored by the USART Transmitter When data is written to the transmit buffer and the Transmitter is enabled the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty Then the data will be serially transmitted on the TxD pin The receive buffer consists of a two level FIFO The FIFO will change its state whenever the receive buffer is accessed Due to this behavior of the receive buffer do not use Read Modify Write instructions SBI and CBI on this location Be careful when using bit test ins
40. 0 BS1 Prog enable 0 0 Table 93 XA1 and XAO Coding XA1 0 XAO0 Action when XTAL1 is Pulsed 0 Load Flash or EEPROM Address High or low address byte determined by BS1 0 1 Load Data High or Low data byte for Flash determined by BS1 1 0 Load Command 1 1 No Action Idle Table 94 Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash 0000 0011 Read EEPROM 2486R AVR 07 07 AMEL 227 Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase AMEL The following algorithm puts the device in Parallel Programming mode 1 Apply 4 5 5 5V between Vec and GND and wait at least 100 ps 2 Set RESET to 0 and toggle XTAL1 at least 6 times 3 Set the Prog enable pins listed in Table 92 on page 227 to 0000 and wait at least 100 ns 4 Apply 11 5 12 5V to RESET Any activity on Prog enable pins within 100 ns after 12V has been applied to RESET will cause the device to fail entering Pro gramming mode Note if the RESET pin is disabled by programming the RSTDISBL Fuse it may not be possible to follow the proposed algorithm above The same may a
41. 10 1 MHz Internal RC Oscillator slowly ris ing power Table 3 Number of Watchdog Oscillator Cycles Typical Time out Vcc 5 0V Typical Time out Vec 3 0V Number of Cycles 4 1 ms 4 3 ms 4K 4 096 65 ms 69 ms 64K 65 536 26 ATmegae8 L EEE __ 2486R AVR 07 07 A megae8 L Crystal Oscillator 2486R AVR 07 07 XTAL1 and XTAL2 are input and output respectively of an inverting amplifier which can be configured for use as an On chip Oscillator as shown in Figure 11 Either a quartz crystal or a ceramic resonator may be used The CKOPT Fuse selects between two dif ferent Oscillator amplifier modes When CKOPT is programmed the Oscillator output will oscillate a full rail to rail swing on the output This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clock buffer This mode has a wide frequency range When CKOPT is unprogrammed the Oscillator has a smaller output swing This reduces power consumption considerably This mode has a limited frequency range and it cannot be used to drive other clock buffers For resonators the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed C1 and C2 should always be equal for both crystals and resonators The optimal value of the capacitors depends on the crystal or resonator in use the amount of stray capacitance and the electromagnetic noise of the env
42. 2486R AVR 07 07 Store Program Memory Control Register SPMCR 2486R AVR 07 07 ATmega8 L Table 80 Boot Reset Fuse BOOTRST Reset Address 1 Reset Vector Application Reset address 0x0000 0 Reset Vector Boot Loader Reset see Table 82 on page 220 Note 1 1 means unprogrammed 0 means programmed The Store Program memory Control Register contains the control bits needed to control the Boot Loader operations Bit 7 6 5 4 3 2 1 0 MEL aware etsser Pawar PGERS SPMEN seucn Read Write R W R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 SPMIE SPM Interrupt Enable When the SPMIE bit is written to one and the I bit in the Status Register is set one the SPM ready interrupt will be enabled The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR Register is cleared Bit 6 RWWSB Read While Write Section Busy When a Self Programming page erase or page write operation to the RWW section is initiated the RWWSB will be set one by hardware When the RWWSB bit is set the RWW section cannot be accessed The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self Programming operation is completed Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated Bit 5 Res Reserved Bit This bit is a reserved bit in the ATmega8 and always read as zero Bit4 RWWSRE Read While Write
43. CLI Read TCNT1 into i i TCNT Restore Global Interrupt Flag SREG sreg return i Note 1 See About Code Examples on page 8 The assembly code example returns the TCNT1 value in the r17 r16 Register pair 80 ATmega8 L memm 2486R AVR 07 07 mJ A megae8 L Reusing the Temporary High Byte Register 2486R AVR 07 07 The following code examples show how to do an atomic write of the TCNT1 Register contents Writing any of the OCR1A B or ICR1 Registers can be done by using the same principle Assembly Code Example TIM16 WriteTCNTl Save Global Interrupt Flag in r18 SREG Disable interrupts cli Set TCNT1 to r17 r16 out TCNT1H r17 out TCNT1L r16 Restore Global Interrupt Flag out SREG r18 ret C Code Example void TIM16 WriteTCNT1 unsigned int i unsigned char sreg unsigned int i Save Global Interrupt Flag sreg SREG Disable interrupts _CLI Set TCNT1 to i TCNT1 i Restore Global Interrupt Flag SREG sreg Note 1 See About Code Examples on page 8 The assembly code example requires that the r17 r16 Register pair contains the value to be written to TCNT1 If writing to more than one 16 bit register where the High byte is the same for all regis ters written then the High byte only needs to be written once However note that the same rule of atomic op
44. During Self Programming AMEL Bit 2 PGWRT Page Write If this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cycles executes page write with the data stored in the temporary buffer The page address is taken from the high part of the Z pointer The data in R1 and RO are ignored The PGWRT bit will auto clear upon completion of a page write or if no SPM instruction is executed within four clock cycles The CPU is halted during the entire page write operation if the NRWW section is addressed Bit 1 PGERS Page Erase If this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cycles executes page erase The page address is taken from the high part of the Z pointer The data in R1 and RO are ignored The PGERS bit will auto clear upon completion of a page erase or if no SPM instruction is executed within four clock cycles The CPU is halted during the entire page write operation if the NRWW section is addressed e Bit0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles If written to one together with either RWWSRE BLBSET PGWRT or PGERS the following SPM instruction will have a special meaning see description above If only SPMEN is written the following SPM instruction will store the value in R1 RO in the temporary page buffer addressed by the Z pointer The LSB of the Z pointer is i
45. FPWM and ICFn if used as TOP OCRnx Update at TOP Old OCRnx Value J New OCRnx Value Figure 44 shows the same timing data but with the prescaler enabled 96 ATlmega8 L mmm 2486R AVR 07 07 X X X A megae8 L Figure 44 Timer Counter Timing Diagram with Prescaler f 0 8 Clk o clk clk 8 TCNTn CTC and FPWM TOP 1 i TOP J BOTTOM BOTTOM 1 TCNTn i PC and PFC PWM TOP 1 i TOP i TOP 1 TOP 2 TOVn FPWM and ICFn if used as TOP OCRnx Update at TOP Old OCRnx Value J New OCRnx Value 16 bit Timer Counter Register Description Timer Counter 1 Control l Register A TCCR1A Bt i 6 5 4 3 2 1 0 COMTAT wow TocRIA Read Write R W R W R W R W Ww Ww R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 COM1A1 0 Compare Output Mode for channel A e Bit 5 4 COM1B1 0 Compare Output Mode for channel B The COM1A1 0 and COM1B1 0 control the Output Compare Pins OC1A and OC1B respectively behavior If one or both of the COM1A1 0 bits are written to one the OC1A output overrides the normal port functionality of the I O pin it is connected to If one or both of the COM1B1 0 bit are written to one the OC1B output overrides the normal port funct
46. K Subtract Constant from Register Rd Rd K Z C N V H SBC Rd Rr Subtract with Carry two Registers Rd Rd Rr C Z C N V H SBCI Rd K Subtract with Carry Constant from Reg Rd Rd K C Z C N V H SBIW Rdl K Subtract Immediate from Word Rdh Rdl Rdh Rdl K Z C N V S 2 AND Rd Rr Logical AND Registers Rd Rd Rr ZN V ANDI Rd K Logical AND Register and Constant Rd Rd eK ZN V OR Rd Rr Logical OR Registers Rd Rd v Rr ZN V 1 ORI Rd K Logical OR Register and Constant Rd lt Rdv K ZN V EOR Rd Rr Exclusive OR Registers Rd Rd 6 Rr ZN V COM Rd One s Complement Rd OxFF Rd Z C N V NEG Rd Two s Complement Rd lt 0x00 Rd Z C N V H SBR Rd K Set Bit s in Register Rd Rdv K Z N V CBR Rd K Clear Bit s in Register Rd lt Rd e OxFF K Z N V INC Rd Increment Rd Rd 1 Z N V DEC Rd Decrement Rd Rd 1 Z N V TST Rd Test for Zero or Minus Rd lt Rd Rd Z N V CLR Rd Clear Register Rd lt Rd Rd Z N V SER Rd Set Register Rd OxFF None 1 MUL Rd Rr Multiply Unsigned R1 RO Rd x Rr Z C 2 MULS Rd Rr Multiply Signed R1 RO Rd x Rr Z C 2 MULSU Rd Rr Multiply Signed with Unsigned R1 RO lt Rd x Rr Z C 2 FMUL Rd Rr Fractional Multiply Unsigned R1 RO lt Rd x Rr lt lt 1 Z C 2 FMULS Rd Rr Fractional Multiply Signed R1 RO lt Rd x Rr lt lt 1 Z C 2 FMULSU Rd Rr Fractional Mul iply Signed with Unsigned R1 RO Rd x Rr lt lt 1 Z C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC k 1 None 2 JMP In
47. None 2 LD Rd Y Load Indirect and Post Inc Rd Y Y Y 1 None 2 LD Rd Y Load Indirect and Pre Dec Y Y 1 Rd e Y None 2 LDD Rd Y4 q Load Indirect with Displacement Rd Y q None 2 LD Rd Z Load Indirec Rd Z None 2 LD Rd Z Load Indirect and Post Inc Rd Z Z Z 1 None 2 LD Rd Z Load Indirect and Pre Dec Z Z 1 Rd Z None 2 LDD Rd Z q Load Indirect with Displacement Rd Z4 q None 2 LDS Rd k Load Direct from SRAM Rd lt k None 2 ST X Rr Store Indirec X Rr None 2 ST X Rr Store Indirect and Post Inc X lt Rr X lt X41 None 2 ST X Rr Store Indirect and Pre Dec X lt X 1 X Rr None 2 ST Y Rr Store Indirec Y lt Rr None 2 ST Y Rr Store Indirect and Post Inc Y lt Rr Ye Y 1 None 2 ST Y Rr Store Indirect and Pre Dec Y lt Y 1 Y lt Rr None 2 STD Y q Rr Store Indirect with Displacement Y q Rr None 2 ST Z Rr Store Indirec Z lt Rr None 2 ST Z Rr Store Indirect and Post Inc Z Rr Z lt Z 1 None 2 ST Z Rr Store Indirect and Pre Dec Z lt Z 1 Z lt Rr None 2 STD Z q Rr Store Indirect with Displacement Z q lt Rr None 2 STS k Rr Store Direct to SRAM k lt Rr None 2 LPM Load Program Memory RO lt Z None 3 LPM Rd Z Load Program Memory Rd lt Z None 3 LPM Rd Z Load Program Memory and Post Inc Rd Z Z Z 1 None 3 SPM Store Program Memory Z R1 RO None x IN Rd P In Por Rd lt P None 1 OUT P Rr Out Port P lt Rr None 1 PUSH Rr
48. The ADC will start a con version once the CPU has been halted 3 If no other interrupts occur before the ADC conversion completes the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine If another interrupt wakes up the CPU before the ADC con version is complete that interrupt will be executed and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes The CPU will remain in Active mode until a new sleep command is executed Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption AMEL 201 Analog Input Circuitry Analog Noise Canceling Techniques AMEL The analog input circuitry for single ended channels is illustrated in Figure 95 An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin regardless of whether that channel is selected as input for the ADC When the chan nel is selected the source must drive the S H capacitor through the series resistance combined resistance in the input path The ADC is optimized for analog signals with an output impedance of approximately 10 kQ or less If such a source is used the sampling time will be negligible If a source with higher impedance is used the sampling time will
49. When this is done writing a byte to the SPI Data Register starts the SPI clock generator and the hardware shifts the eight bits into the Slave After shifting one byte the SPI clock gener ator stops setting the end of Transmission Flag SPIF If the SPI interrupt enable bit SPIE in the SPCR Register is set an interrupt is requested The Master may continue to shift the next byte by writing it into SPDR or signal the end of packet by pulling high the Slave Select SS line The last incoming byte will be kept in the Buffer Register for later use When configured as a Slave the SPI interface will remain sleeping with MISO tri stated as long as the SS pin is driven high In this state software may update the contents of the SPI Data Register SPDR but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low As one byte has been completely shifted the end of Transmission Flag SPIF is set If the SPI interrupt enable bit SPIE in the SPCR Register is set an interrupt is requested The Slave may continue to place new data to be sent into SPDR before reading the incoming data The last incoming byte will be kept in the Buffer Register for later use Figure 58 SPI Master Slave Interconnection MSB MASTER LSB MSB SLAVE LSB MISO MISO 8 BIT SHIFT REGISTER lt 8 BIT SHIFT REGISTER x Mosi MOS SHIFT ENABLE LOCK GENERATOR zE aa CLOCK G O 8
50. circuit ensures that the device is reset from Power on Reach ing the Power on Reset threshold voltage invokes the delay counter which determines how long the device is kept in RESET after Voc rise The RESET signal is activated again without any delay when Vcc decreases below the detection level Figure 15 MCU Start up RESET Tied to Voc INTERNAL RESET Figure 16 MCU Start up RESET Extended Externally T d Vpot Voc i VA RESET W Vast TIME OUT i lt trour INTERNAL i RESET AMEL s 2486R AVR 07 07 External Reset Brown out Detection AMEL An External Reset is generated by a low level on the RESET pin Reset pulses longer than the minimum pulse width see Table 15 will generate a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage Vpsr on its positive edge the delay counter starts the MCU after the time out period t 5 7 has expired Figure 17 External Reset During Operation Vcc RESET I i i trout gt TIME OUT i INTERNAL RESET ATmega8 has an On chip Brown out Detection BOD circuit for monitoring the Vec level during operation by comparing it to a fixed trigger level The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2 7V BODLEVEL unprogrammed or 4 0V BODLEVEL programmed The trigger level has a hysteresis to ensure spik
51. 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8k 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0 38 4k 5 0 0 11 0 0 6 7 0 12 0 2 11 0 0 23 0 0 57 6k 3 0 0 7 0 0 3 8 5 8 3 5 7 0 0 15 0 0 76 8k 2 0 0 5 0 0 2 8 5 6 7 0 5 0 0 11 0 0 115 2k 1 0 0 3 0 0 1 8 5 3 8 5 3 0 0 7 0 0 230 4k 0 0 0 1 0 0 0 8 596 1 8 596 1 0 096 3 0 096 250k 0 7 8 1 7 8 0 0 096 1 0 0 1 7 8 3 7 8 0 5M 0 7 8 0 0 096 0 7 8 1 7 8 1M 0 7 8 Max 230 4 kbps 460 8 kbps 250 kbps 0 5 Mbps 460 8 kbps 921 6 kbps 1 UBRR 0 Error 0 0 10 ATmega8 L mmm AT 11 C025 Table 62 Examples of UBRR Settings for Commonly Used Oscillator Frequencies Continued fosc 8 0000 MHz fosc 11 0592 MHz fosc 14 7456 MHz a U2X 0 U2X 1 U2X 0 U2X 1 U2X 0 U2X 1 bps UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0 2 416 0 1 287 0 0 575 0 0 383 0 0 767 0 0 4800 103 0 2 207 0 2 143 0 0 287 0 0 191 0 0 383 0 0 9600 51 0 2 103 0 2 71 0 0 143 0 0 95 0 0 191 0 0 14 4k 34 0 8 68 0 6 47 0 0 95 0 0 63 0 0 127 0 0 19 2k 25 0 2 51 0 2 35 0 0 71 0 0 47 0 0 95 0 0 28 8k 16 2 1 34 0 8 23 0 0 47 0 0 31 0 0 63 0 0 38 4k 12 0 2 25 0 2 17 0 0 35 0 0 23 0 0 47 0 0 57 6k 8 3 5 16 2 1 11 0 0 23 0 0 15 0 0 31 0 0 76 8k 6 7 0 12 0 2 8 0 0 17 0 0 11 0 0 23 0 0 115 2k 3 8 5
52. 0 1 clkyo 1024 From prescaler 1 1 0 External clock source on T1 pin Clock on falling edge 1 1 1 External clock source on T1 pin Clock on rising edge 100 ATmega8 L mmm 2486R AVR 07 07 X X X f megae8 L If external pin modes are used for the Timer Counter1 transitions on the T1 pin will clock the counter even if the pin is configured as an output This feature allows software control of the counting Timer Counter 1 TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNTIH TCNT1 7 0 TCNT1L Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The two Timer Counter I O locations TCNT1H and TCNT1L combined TCNT1 give direct access both for read and for write operations to the Timer Counter unit 16 bit counter To ensure that both the high and Low bytes are read and written simulta neously when the CPU accesses these registers the access is performed using an 8 bit temporary High byte Register TEMP This temporary register is shared by all the other 16 bit registers See Accessing 16 bit Registers on page 79 Modifying the counter TCNT1 while the counter is running introduces a risk of missing a Compare Match between TCNT1 and one of the OCR1x Registers Writing to the TCNT1 Register blocks removes the Compare Match on the following timer clock for all compare units Output Compare Register 1 A OCR1AH and OCR1AL Bit d 6 5 3 2 1 0 OCRIAH OCR1A 7 0 OCR1AL Read Write R W R
53. 1 PCPWM log 2 In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values OxOOFF OxO1FF or OxO3FF WGM13 0 1 2 or 3 the value in ICR1 WGM13 0 10 or the value in OCR1A WGM13 0 11 The counter has then reached the TOP and changes the count direction The TCNT1 value will be equal to TOP for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 39 The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT1 slopes repre sent compare matches between OCR1x and TCNT1 The OC1x Interrupt Flag will be set when a Compare Match occurs Figure 39 Phase Correct PWM Mode Timing Diagram Y OCRnx TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set Interrupt on TOP I A ATARE SETAE sea es ec ata tt A E DE TETTE PEPPER TOVn Interrupt Flag Set Interrupt on Bottom Y Y Z E TCNTn J y l y Y Y OCnx COMnx1 0 2 OCnx COMnx1 0 3 Period le 1 rie 2 ple 3 k 4 The Timer Counter Overflow Flag TOV1 is set each time the counter reaches BOT TOM When either OCR1A or ICR1 is used for defining the TOP value t
54. 255 AMEL o Timer Counter Clock Sources Counter Unit Operation AMEL The Timer Counter can be clocked by an internal or an external clock source The clock source is selected by the clock select logic which is controlled by the clock select CS02 0 bits located in the Timer Counter Control Register TCCRO For details on clock sources and prescaler see Timer CounterO and Timer Counter1 Prescalers on page 74 The main part of the 8 bit Timer Counter is the programmable counter unit Figure 27 shows a block diagram of the counter and its surroundings Figure 27 Counter Unit Block Diagram TOVn DATA BUS Int Req Clock Select Edge Detector From Prescaler Signal description internal signals count Increment TCNTO by 1 clk Timer Counter clock referred to as clkz in the following max Signalize that TCNTO has reached maximum value The counter is incremented at each timer clock clky9 clkzy can be generated from an external or internal clock source selected by the clock select bits CS02 0 When no clock source is selected CS02 0 0 the timer is stopped However the TCNTO value can be accessed by the CPU regardless of whether clky is present or not A CPU write overrides has priority over all counter clear or count operations The counting direction is always up incrementing and no counter clear is performed The counter simply overruns when it passes its maximum 8
55. 8 3 5 5 0 0 11 0 0 7 0 0 15 0 0 230 4k 1 8 5 3 8 5 2 0 0 5 0 0 3 0 0 7 0 0 250k 1 0 0 3 0 0 2 7 8 5 7 8 3 7 8 6 5 3 0 5M 0 0 0 1 0 0 2 7 896 1 7 896 3 7 8 1M 0 0 096 0 7 8 1 7 8 Max 0 5 Mbps 1 Mbps 691 2 kbps 1 3824 Mbps 921 6 kbps 1 8432 Mbps 1 UBRR 0 Error 0 0 AMEL 161 2486R AVR 07 07 AMEL Table 63 Examples of UBRR Settings for Commonly Used Oscillator Frequencies Continued fosc 16 0000 MHz fosc 18 4320 MHz fosc 20 0000 MHz E U2X 0 U2X 1 U2X 0 U2X 1 U2X 0 U2X 1 bps UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 0 1 832 0 0 479 0 0 959 0 0 520 0 0 1041 0 0 4800 207 0 2 416 0 1 239 0 0 479 0 0 259 0 2 520 0 0 9600 103 0 2 207 0 2 119 0 0 239 0 0 129 0 2 259 0 2 14 4k 68 0 6 138 0 1 79 0 0 159 0 0 86 0 2 173 0 2 19 2k 51 0 2 103 0 2 59 0 0 119 0 0 64 0 2 129 0 2 28 8k 34 0 8 68 0 6 39 0 0 79 0 0 42 0 9 86 0 2 38 4k 25 0 2 51 0 2 29 0 0 59 0 0 32 1 496 64 0 296 57 6k 16 2 196 34 0 896 19 0 096 39 0 096 21 1 496 42 0 996 76 8k 12 0 296 25 0 296 14 0 096 29 0 096 15 1 796 32 1 496 115 2k 8 3 5 16 2 1 9 0 0 19 0 0 10 1 4 21 1 4 230 4k 3 8 5 8 3 5 4 0 0 9 0 0 4 8 5 10 1 4 250k 3 0 0 7 0 0 4 7 8 8 2 4 4 0 0 9 0 0 0 5M 1 0 0 3 0 0 4 7 8 4 0 096 1M 0 0 096 1 0 096 Max
56. 8 10 12 14 16 18 20 Frequency MHz AMEL 285 AMEL Figure 191 Reset Pulse Width vs Voc RESET PULSE WIDTH vs Vcc 1400 1200 1000 800 600 Pulsewidth ns 85 C 400 25 C 40 C 200 2 5 3 3 5 4 4 5 5 5 5 Vcc V 236 ATmega8 L m ssm 2486R AVR 07 07 AT 11 C025 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page Ox3F 0x5F SREG l T H S V N Z Cc 11 Ox3E 0x5E SPH SP10 SP9 SP8 13 Ox3D 0x5D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO 13 0x3C 0x5C Reserved 0x3B 0x5B GICR INT1 INTO IVSEL IVCE 49 67 Ox3A 0x5A GIFR INTF1 INTFO 68 0x39 0x59 TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 TOIEO 72 102 122 0x38 0x58 TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 TOVO 73 103 122 0x37 0x57 SPMCR SPMIE RWWSB RWWSRE BLBSET PGWRT PGERS SPMEN 213 0x36 0x56 TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE 171 0x35 0x55 MCUCR SE SM2 SM1 SMO ISC11 ISC10 ISCO1 ISCOO 33 66 0x34 0x54 MCUCSR WDRF BORF EXTRF PORF 41 0x33 0x53 TCCRO cso2 CS01 CS00 72 0x32 0x52 TONTO Timer Counter0 8 Bits 72 0x31 0x51 OSCCAL Oscillator Cal
57. AMEL 259 2486R AVR 07 07 AMEL Figure 139 Standby Supply Current vs Vcc 4 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Vcc 4 MHz RESONATOR WATCHDOG TIMER DISABLED 140 120 100 80 Icc uA 60 40 20 2 5 3 3 5 4 4 5 Voc V Figure 140 Standby Supply Current vs Vcc 4 MHz Xtal Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Vcc 4 MHz XTAL WATCHDOG TIMER DISABLED 140 120 100 80 lcc uA 60 40 20 2 5 3 3 5 4 4 5 Voc V xo ATmega8 L mmm 2486R AVR 07 07 J f megae8 L Figure 141 Standby Supply Current vs Voc 6 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Vcc 6 MHz RESONATOR WATCHDOG TIMER DISABLED 160 140 120 100 T 80 38 60 40 20 0 2 5 3 3 5 4 4 5 5 5 5 Voc V Figure 142 Standby Supply Current vs Vcc 6 MHz Xtal Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs Vcc 6 MHz XTAL WATCHDOG TIMER DISABLED 200 180 160 140 120 100 Icc UA 80 60 40 20 2 5 3 3 5 4 4 5 5 5 5 Voc V AMEL 261 2486R AVR 07 07 AMEL Pin Pull up Figure 143 O Pin Pull up Resistor Current vs Input Voltage Vcc 5V 262 1 0 PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 5V 160 85 C 140
58. ASSR When the AS2 bit in ASSR is set one to enable asynchronous clocking of Timer Counter2 pin PB6 is disconnected from the port and becomes the input of the 58 ATmega8 L memm 2486R AVR 07 07 f 11 C025 inverting Oscillator amplifier In this mode a crystal Oscillator is connected to this pin and the pin can not be used as an I O pin If PB6 is used as a clock pin DDB6 PORTB6 and PINB6 will all read 0 SCK Port B Bit 5 SCK Master Clock output Slave Clock input pin for SPI channel When the SPI is enabled as a Slave this pin is configured as an input regardless of the setting of DDB5 When the SPI is enabled as a Master the data direction of this pin is controlled by DDB5 When the pin is forced by the SPI to be an input the pull up can still be con trolled by the PORTBS bit MISO Port B Bit 4 MISO Master Data input Slave Data output pin for SPI channel When the SPI is enabled as a Master this pin is configured as an input regardless of the setting of DDB4 When the SPI is enabled as a Slave the data direction of this pin is controlled by DDB4 When the pin is forced by the SPI to be an input the pull up can still be con trolled by the PORTBA bit e MOSI OC2 Port B Bit 3 MOSI SPI Master Data output Slave Data input for SPI channel When the SPI is enabled as a Slave this pin is configured as an input regardless of the setting of DDB3 When the SPI is enabled as a Master
59. AVR 07 07 AMEL 189 Miscellaneous States AMEL Figure 85 Formats and States in the Slave Transmitter Mode Reception of the own ned slave address and one or S SLA i R A DATA A DATA A PorS more data bytes nad A8 B8 CO Arbitration lost as master and addressed as slave A BO Last data byte transmitted apod Switched to not addressed A Alli s PorS slave TWEA 0 Pulls C8 qood Any number of data bytes From master to slave DATA A and their associated acknowledge bits From slave to master This number contained in TWSR corresponds to a defined state of the Two Wire Serial Bus The prescaler bits are zero or masked to zero There are two status codes that do not correspond to a defined TWI state see Table 70 Status OxF8 indicates that no relevant information is available because the TWINT Flag is not set This occurs between other states and when the TWI is not involved in a serial transfer Status 0x00 indicates that a bus error has occurred during a Two wire Serial Bus trans fer A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit When a bus error occurs TWINT is set To recover from a bus error the TWSTO Flag must set and TWIN
60. As shown in Figure 3 each register is also assigned a Data memory address mapping them directly into the first 32 locations of the user Data Space Although not being phys ically implemented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z pointer Registers can be set to index any register in the file 12 ATmega8 L memm 2486R AVR 07 07 GXse f rmegaea L The X register Y register and Z register Stack Pointer 2486R AVR 07 07 The registers R26 R31 have some added functions to their general purpose usage These registers are 16 bit address pointers for indirect addressing of the Data Space The three indirect address registers X Y and Z are defined as described in Figure 4 Figure 4 The X Y and Z Registers 15 XH XL 0 Xregister 7 z R27 0x1B R26 0x1A Leer aae 0x1D S aael 0x1C a 0x1F E 0x1E In the different addressing modes these address registers have functions as fixed dis placement automatic increment and automatic decrement see the Instruction Set Reference for details The Stack is mainly used for storing temporary data for storing local variables and for storing return addresses after interrupts and subroutine calls The Stack Pointer Regis ter always points to the top of the Stack Note that the Stack is implemented as growing from higher memory locations to lower memory locations T
61. Compare B match interrupt is enabled The corresponding Interrupt Vector see Interrupts on page 46 is executed when the OCF1B Flag located in TIFR is set e Bit 2 TOIE1 Timer Counter1 Overflow Interrupt Enable When this bit is written to one and the I flag in the Status Register is set interrupts glo bally enabled the Timer Counter1 Overflow Interrupt is enabled The corresponding Interrupt Vector see Interrupts on page 46 is executed when the TOV1 Flag located in TIFR is set 102 ATlmega8 L memm 2486R AVR 07 07 Aimegae8 L Timer Counter Interrupt Flag Register TIFR 2486R AVR 07 07 Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 Ce TOVO TIFR Read Write R W R W R W R W R W R W R R W Initial Value 0 0 0 0 0 0 0 0 Note 1 This register contains flag bits for several Timer Counters but only Timer1 bits are described in this section The remaining bits are described in their respective timer sections Bit 5 ICF1 Timer Counter1 Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin When the Input Capture Register ICR1 is set by the WGM13 0 to be used as the TOP value the ICF1 Flag is set when the counter reaches the TOP value ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed Alter natively ICF1 can be cleared by writing a logic one to its bit location e Bit 4 OCF1A Timer Counter1 Output
62. Master Receiver mode 0x18 SLA W has been transmitted Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will ACK has been received be received No TWDR action or 1 0 1 X Repeated START will be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO Flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x20 SLA W has been transmitted Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will NOT ACK has been received be received No TWDR action or 1 0 1 X Repeated START will be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO Flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x28 Data byte has been transmitted Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will ACK has been received be received No TWDR action or 1 0 1 X Repeated START will be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO Flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x30 Data byte has been transmitted Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will NOT ACK has been received be received No TWDR action or 1 0 1 X Repeated START w
63. Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Symbol Parameter Condition Min Typ Max Units Input Low Voltage except 2 1 Vit XTAL1 and RESET pins Voc 2 7V 5 5V 0 5 0 2 Veg V Input High Voltage except E 2 Viu XTAL1 and RESET pins Vec 2 7V 5 5V 0 6 Voc Veo 0 5 V Input Low Voltage V Voc 2 7V 5 5V 0 5 0 1 Voce V B XTAL1 pin cc a cc Input High Voltage Ving XTAL 1 pin Voc 2 7V 5 5V 0 8 Vo Voc 0 5 V Input Low Voltage V i do Voc 2 7V 5 0 2V V L2 RESET pin cc 2 7V 5 5V 0 5 0 2 Vec Input High Voltage Vine RESET pin Voc 2 7V 5 5V 0 9 Vec Voc 0 5 V Input Low Voltage V D Voc 2 7V 5 5V 0 5 0 2 V V L3 RESET pin as I O E Input High Voltage 0 6 Voc V SEMEN Voc 2 7V 5 5V Vcc 0 5 V H3 RESET pin as I O cc 0 7 Veo ad V Output Low Voltage lo 20 mA Veg 5V 0 7 V BE Ports B C D lo 10 mA Voc 3V 0 5 V V Output High Voltage lon 20 mA Voc 5V 4 2 V 2H Ports B C D lop 10 mA Voc 3V 2 2 V Input Leakage Vcc 5 5V pin low 1 A It Current I O Pin absolute value H Input Leakage Vcc 5 5V pin high 1 A IH Current I O
64. Mode Using MPCM 2486R AVR 07 07 Setting the Multi processor Communication mode MPCM bit in UCSRA enables a fil tering function of incoming frames received by the USART Receiver Frames that do not contain address information will be ignored and not put into the receive buffer This effectively reduces the number of incoming frames that has to be handled by the CPU in a system with multiple MCUs that communicate via the same serial bus The Trans mitter is unaffected by the MPCM setting but has to be used differently when it is a part of a system utilizing the Multi processor Communication mode If the Receiver is set up to receive frames that contain 5 to 8 data bits then the first stop bit indicates if the frame contains data or address information If the Receiver is set up for frames with nine data bits then the ninth bit RXB8 is used for identifying address and data frames When the frame type bit the first stop or the ninth bit is one the frame contains an address When the frame type bit is zero the frame is a data frame The Multi processor Communication mode enables several Slave MCUs to receive data from a Master MCU This is done by first decoding an address frame to find out which MCU has been addressed If a particular Slave MCU has been addressed it will receive the following data frames as normal while the other Slave MCUs will ignore the received frames until another address frame is received For an MCU to act
65. NOT clocked asynchronously Power down mode is recom mended instead of Power save mode because the contents of the registers in the 34 ATlmega8 L memm 2486R AVR 07 07 A 11 C023 Standby Mode asynchronous timer should be considered undefined after wake up in Power save mode if AS2 is 0 This sleep mode basically halts all clocks except clkasy allowing operation only of asyn chronous modules including Timer Counter 2 if clocked asynchronously When the SM2 0 bits are 110 and an external crystal resonator clock option is selected the SLEEP instruction makes the MCU enter Standby mode This mode is identical to Power down with the exception that the Oscillator is kept running From Standby mode the device wakes up in 6 clock cycles Table 14 Active Clock Domains and Wake up Sources in the Different Sleep Modes Active Clock Domains Oscillators Wake up Sources TWI SPM Sleep Main Clock Timer Osc INT1 Address Timer EEPROM Other Mode Clkcpy ClKge As ClKig clKApc ClKasy Source Enabled Enabled INTO Match 2 Ready ADC I O Idle X X X X xe X X X X X X BUS Noise X X X x2 x9 x x X x Reduction Power x9 X Down Power x2 x x9 X x Save Standby X x X Notes 1 External Crystal or resonator selected as clock source 2 If AS2 bit in ASSR is set 3 Only level interrupt INT1 and INTO Minimizing Power Consumption Analog
66. O memory addresses should never be written Some of the Status Flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will operate on all bits in the I O Register writing a one back into any flag read as set thus clearing the flag The CBI and SBI instructions work with reg isters 0x00 to Ox1F only The I O and Peripherals Control Registers are explained in later sections 24 ATmega8 L m I 2486R AVR 07 07 X A mega8 L System Clock and Clock Options Clock Systems and their Distribution 2486R AVR 07 07 Figure 10 presents the principal clock systems in the AVR and their distribution All of the clocks need not be active at a given time In order to reduce power consumption the clocks to modules not being used can be halted by using different sleep modes as described in Power Management and Sleep Modes on page 33 The clock systems are detailed Figure 10 Flash and CPU Core RAM EEPROM ADC AVR Clock clkcpy Control Unit IM Tr Watchdog Clock Watchdog Oscillator Figure 10 Clock Distribution General I O Modules Asynchronous Timer Counter Source Clock Clock Multiplexer Timer Counter External RC Crystal Low Frequency Calibrated RC Oscillator Oscillator External Clock Oscillator Crystal Oscillator Oscillator The CPU clock is routed to parts of the system concerned with operation o
67. Oscillator Frequencies fosc 1 0000 MHz fosc 1 8432 MHz fosc 2 0000 MHz an U2X 0 U2X 1 U2X 0 U2X 1 U2X 0 U2X 1 bps UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 25 0 2 51 0 2 47 0 0 95 0 0 51 0 2 103 0 2 4800 12 0 2 25 0 2 23 0 0 47 0 0 25 0 2 51 0 2 9600 6 7 0 12 0 2 11 0 0 23 0 0 12 0 2 25 0 2 14 4k 3 8 5 8 3 5 7 0 0 15 0 0 8 3 5 16 2 1 19 2k 2 8 5 6 7 0 5 0 0 11 0 0 6 7 0 12 0 2 28 8k 1 8 5 3 8 5 3 0 0 7 0 0 3 8 5 8 3 5 38 4k 1 18 6 2 8 5 2 0 0 5 0 0 2 8 5 6 7 0 57 6k 0 8 5 1 8 5 1 0 0 3 0 0 1 8 5 3 8 5 76 8k 1 18 6 1 25 0 2 0 0 1 18 6 2 8 5 115 2k B 0 8 5 0 0 0 1 0 0 0 8 5 1 8 5 230 4k 0 0 0 250k x 0 0 0 Max 62 5 kbps 125 kbps 115 2 kbps 230 4 kbps 125 kbps 250 kbps 1 UBRR 0 Error 0 0 AMEL 159 EE Sj 2486R AVR 07 07 AMEL Table 61 Examples of UBRR Settings for Commonly Used Oscillator Frequencies Continued fosc 3 6864 MHz fosc 4 0000 MHz fosc 7 3728 MHz nd U2X 0 U2X 1 U2X 0 U2X 1 U2X 0 U2X 1 bps UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0 096 191 0 096 103 0 296 207 0 296 191 0 0 383 0 0 4800 47 0 0 95 0 0 51 0 2 103 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4k 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2k 11
68. PAGESIZEB PAGESIZE 2 PAGESIZEB is page size in BYTES not words org SMALLBOOTSTART Write page page erase ldi spmcrval 1 PGERS 1 SPMEN rcallDo spm re enable the RWW section ldi spmcrval 1 lt lt RWWSRE 1 lt lt SPMEN rcallDo_spm transfer data from RAM to Flash page buffer ldi looplo low PAGESIZEB init loop variable ldi loophi high PAGESIZEB not required for PAGESIZEB 256 Wrloop ld r0 Y ld rl Y ldi spmcrval 1 SPMEN rcallDo spm adiw ZH ZL 2 sbiw loophi looplo 2 use subi for PAGESIZEB 256 brne Wrloop execute page write subi ZL low PAGESIZEB restore pointer sbci ZH high PAGESIZEB not required for PAGESIZEB 256 ldi spmcrval 1 PGWRT 1 SPMEN rcallDo spm re enable the RWW section ldi spmcrval 1 lt lt RWWSRE 1 SPMEN rcallDo spm read back and check optional ldi looplo low PAGESIZEB init loop variable ldi loophi high PAGESIZEB not required for PAGESIZEB 256 subi YL low PAGESIZEB restore pointer sbci YH high PAGESIZEB Rdloop lpm r0 Z ld rl Y cpse r0 r1 rjmp Error AMEL 219 ATmega8 Boot Loader Parameters AMEL sbiw loophi looplo 1 use subi for PAGESIZEB 256 brne Rdloop return to RWW section verify that RWW section is safe to read Return in templ SPMCR sbrs tempi RWWSB If RWWSB is set the RWW section is
69. PBO DDRB 1 lt lt DDB3 1 lt lt DDB2 1 lt lt DDB1 1 DDB0 Insert nop for synchronization _NOP Read port pins i PINB Note 1 For the assembly program two temporary registers are used to minimize the time from pull ups are set on pins 0 1 6 and 7 until the direction bits are correctly set defining bit 2 and 3 as low and redefining bits O and 1 as strong high drivers As shown in Figure 22 the digital input signal can be clamped to ground at the input of the Schmitt trigger The signal denoted SLEEP in the figure is set by the MCU Sleep Controller in Power down mode Power save mode and Standby mode to avoid high power consumption if some input signals are left floating or have an analog signal level close to V 2 SLEEP is overridden for port pins enabled as External Interrupt pins If the External Interrupt Request is not enabled SLEEP is active also for these pins SLEEP is also overridden by various other alternate functions as described in Alternate Port Func tions on page 56 If a logic high level one is present on an Asynchronous External Interrupt pin config ured as Interrupt on Rising Edge Falling Edge or Any Logic Change on Pin while the external interrupt is not enabled the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes as the clamping in these sleep modes produces the requested logic change
70. PWM options by its single slope operation The counter counts from BOTTOM to TOP then restarts from BOTTOM In non inverting Compare Output mode the Output Compare OC1x is cleared on the Compare Match between TCNT1 and OCR1x and set at BOTTOM In inverting Compare Output mode output is set on Compare Match and cleared at BOTTOM Due to the single slope operation the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual slope operation This high frequency makes the fast PWM mode well suited for power regulation rectification and DAC applications High AMEL 2486R AVR 07 07 AMEL frequency allows physically small sized external components coils capacitors hence reduces total system cost The PWM resolution for fast PWM can be fixed to 8 9 or 10 bit or defined by either ICR1 or OCR1A The minimum resolution allowed is 2 bit ICR1 or OCR1A set to 0x0003 and the maximum resolution is 16 bit ICR1 or OCR1A set to MAX The PWM resolution in bits can be calculated by using the following equation R _ log TOP 1 FPWM Tog In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF 0x01FF or 0x03FF WGM13 0 5 6 or 7 the value in ICR1 WGM13 0 14 or the value in OCR1A WGM13 0 15 The counter is then cleared at the following timer clock cycle The timing diagram for the
71. Prescaling ea clk clk 1 i TCNTn MAX 1 MAX BOTTOM BOTTOM 1 TOVn Figure 53 shows the same timing data but with the prescaler enabled Figure 53 Timer Counter Timing Diagram with Prescaler f 0 8 clkig clk n 1 clkyo 8 TCNTn MAX 1 MAX l BOTTOM j BOTTOM 1 TOVn Figure 54 shows the setting of OCF2 in all modes except CTC mode AMEL 115 2486R AVR 07 07 AMEL Figure 54 Timer Counter Timing Diagram Setting of OCF2 with Prescaler fok 0 8 celko clk ck TCNTn OCRn 1 l OCRn OCRn 1 l OCRn 2 OCRn OCRn Value OCFn Figure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode Figure 55 Timer Counter Timing Diagram Clear Timer on Compare Match Mode with Prescaler f 0 8 clk ie
72. Push Register on Stack STACK amp Rr None 2 POP Hd Pop Register from Stack Rd STACK None 2 BIT AND BIT TEST INSTRUCTIONS SB P b Set Bit in I O Register VO P b None 2 CBI P b Clear Bit in I O Register V O P b None 2 LSL Rd Logical Shift Left Rd n 1 TE d 0 0 Z C N V LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 0 Z C N V ROL Rd Rotate Left Through Carry Rd 0 lt C Rd n 1 lt Rd n C lt Rd 7 Z C N V ROR Rd Rotate Right Through Carry Rd 7 lt C Rd n lt Rd n 1 C lt Rd 0 Z C N V ASR Rd Arithmetic Shift Right Rd n Rd n 1 n 0 6 Z C N V 1 SWAP Rd Swap Nibbles Rd 3 0 lt Rd 7 4 Rd 7 4 lt Rd 3 0 None 1 BSET s Flag Set SREG s 1 SREG s BCLR s Flag Clear SREG s 0 SREG s BST Rr b Bit Store from Register to T T lt Rr b T BLD Rd b Bit load from T to Register Rd b T None 1 SEC Set Carry C lt 1 C 1 CLC Clear Carry Cc 0 C SEN Set Negative Flag Nei N 1 CLN Clear Negative Flag Nc 0 N SEZ Set Zero Flag Zei Z CLZ Clear Zero Flag Z lt 0 Z 1 SEI Global Interrupt Enable 1 1 l CLI Global Interrupt Disable l 0 l 1 SES Set Signed Test Flag Sc 1 S CLS Clear Signed Test Flag Sc 0 S SEV Set Twos Complement Overflow Vel V CLV Clear Twos Complement Overflow Vc 0 V 1 SET Set Tin SREG T lt 1 T 1 Mnemonics Operands Description Operation Flags Clocks 290 ATmega8 L mmm 2486R AVR 07 07 m Amegae8 L Instruction Set Summary Continued
73. R16 Assembly Code Example USART Transmit Wait for empty transmit buffer sbis UCSRA UDRE rjmp USART Transmit Copy ninth bit from r17 to TXB8 cbi UCSRB TXB8 sbrc r17 0 sbi UCSRB TXB8 Put LSB data r16 into buffer sends the data out UDR r16 ret C Code Example void USART_Transmit unsigned int data Wait for empty transmit buffer while UCSRA amp 1 lt lt UDRE 1 Copy ninth bit to TXB8 UCSRB amp 1 lt lt TXB8 if data amp 0x0100 UCSRB 1 TXB8 Put data into buffer sends the data UDR data Note 1 These transmit functions are written to be general functions They can be optimized if the contents of the UCSRB is static l e only the TXB8 bit of the UCSRB Register is used after initialization The ninth bit can be used for indicating an address frame when using multi processor communication mode or for other protocol handling as for example synchronization The USART Transmitter has two flags that indicate its state USART Data Register Empty UDRE and Transmit Complete TXC Both flags can be used for generating interrupts The Data Register Empty UDRE Flag indicates whether the transmit buffer is ready to receive new data This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register For compatibility with f
74. Reset and Interrupt Vectors Placement BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x001 1 1 0x000 Boot Reset Address 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address 0x001 Note 1 The Boot Reset Address is shown in Table 82 on page 220 For the BOOTRST Fuse 1 means unprogrammed while 0 means programmed The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8B is addressLabels Code Comments 2486R AVR 07 07 000 rjmp RESET Reset Handler 001 rjmp EXT INTO IRQO Handler 002 rjmp EXT INT1 IRQ1 Handler 003 rjmp TIM2_COMP Timer2 Compare Handler 004 rjmp TIM2 OVF Timer2 Overflow Handler 005 rjmp TIM1 CAPT Timerl Capture Handler 006 rjmp TIM1 COMPA Timerl CompareA Handler 007 rjmp TIM1 COMPB Timerl CompareB Handler 008 rjmp TIM1 OVF Timerl Overflow Handler 009 rjmp TIMO OVF Timer0 Overflow Handler 00a rjmp SPI STC SPI Transfer Complete Handler 00b rjmp USART_RXC USART RX Complete Handler 00c rjmp USART_UDRE UDR Empty Handler 00d rjmp USART TXC USART TX Complete Handler 00e rjmp ADC ADC Conversion Complete Handler Soot rjmp EE_RDY EEPROM Ready Handler 010 rjmp ANA_COMP Analog Comparator Handler 011 rjmp TWSI Two wire Serial Interface Handler 012 rjmp SPM RDY Store Prog
75. Section Read Enable When programming page erase or page write to the RWW section the RWW section is blocked for reading the RWWSB will be set by hardware To re enable the RWW section the user software must wait until the programming is completed SPMEN will be cleared Then if the RWWSRE bit is written to one at the same time as SPMEN the next SPM instruction within four clock cycles re enables the RWW section The RWW section cannot be re enabled while the Flash is busy with a page erase or a page write SPMEN is set If the RWWSRE bit is written while the Flash is being loaded the Flash load operation will abort and the data loaded will be lost The page buffer will be cleared when the Read While Write section is re enabled Bit 3 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cycles sets Boot Lock Bits according to the data in RO The data in R1 and the address in the Z pointer are ignored The BLBSET bit will automatically be cleared upon completion of the lock bit set or if no SPM instruction is executed within four clock cycles An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR Register will read either the Lock Bits or the Fuse Bits depending on ZO in the Z pointer into the destination register See Reading the Fuse and Lock Bits from Soft ware on page 217 for details AMEL 213 Addressing the Flash
76. Synchronous Clock Operation When Synchronous mode is used UMSEL 1 the XCK pin will be used as either clock Frame Formats 2486R AVR 07 07 input Slave or clock output Master The dependency between the clock edges and data sampling or data change is the same The basic principle is that data input on RxD is sampled at the opposite XCK clock edge of the edge the data output TxD is changed Figure 63 Synchronous Mode XCK Timing UCPOL 1 XCK Rest pL XE X RxD TxD x R x Sample UCPOL 0 XCK FOX X RxD TxD N Ec Sample The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change As Figure 63 shows when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge If UCPOL is set the data will be changed at falling XCK edge and sampled at rising XCK edge A serial frame is defined to be one character of data bits with synchronization bits start and stop bits and optionally a parity bit for error checking The USART accepts all 30 combinations of the following as valid frame formats e 1 start bit e 5 6 7 8 or 9 data bits e no even or odd parity bit e 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit Then the next data bits up to a total of nine are succeeding ending with the most significant bit If enabled the parity bit is inserted after the data bits before the st
77. TWCR instructing the TWI hardware to transmit the SLA W present in TWDR Which value to write is described later on However it is important that the TWINT bit is set in the value written Writing a one to TWINT clears the flag The TWI will not start any operation as long as the TWINT bit in TWCR is set Immediately after the application has cleared TWINT the TWI will initiate transmission of the address packet 4 When the address packet has been transmitted the TWINT Flag in TWCR is set and TWSR is updated with a status code indicating that the address packet has successfully been sent The status code will also reflect whether a Slave acknowledged the packet or not 5 The application software should now examine the value of TWSR to make sure that the address packet was successfully transmitted and that the value of the ACK bit was as expected If TWSR indicates otherwise the application software might take some special action like calling an error routine Assuming that the status code is as expected the application must load a data packet into TWDR Subsequently a specific value must be written to TWCR instructing the TWI hardware to transmit the data packet present in TWDR Which value to write is AMEL 175 2486R AVR 07 07 176 AMEL described later on However it is important that the TWINT bit is set in the value written Writing a one to TWINT clears the flag The TWI will not start any opera tion as long as th
78. The Data Direction Register bit for the OC2 pin DDR OC2 must be set as output before the OC2 value is visible on the pin The port override function is independent of the Waveform Generation mode The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled Note that some COM21 0 bit settings are reserved for certain modes of operation See 8 bit Timer Counter Register Description on page 117 AMEL 109 Compare Output Mode and Waveform Generation Modes of Operation Normal Mode AMEL The Waveform Generator uses the COM21 0 bits differently in normal CTC and PWM modes For all modes setting the COM21 0 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match For com pare output actions in the non PWM modes refer to Table 43 on page 118 For fast PWM mode refer to Table 44 on page 118 and for phase correct PWM refer to Table 45 on page 118 A change of the COM21 0 bits state will have effect at the first Compare Match after the bits are written For non PWM modes the action can be forced to have immediate effect by using the FOC2 strobe bits The mode of operation i e the behavior of the Timer Counter and the Output Compare pins is defined by the combination of the Waveform Generation mode WGM21 0 and Compare Output mode COM21 0 bits The Compare Output mode bits do not affect the counting sequence while the
79. Ti T2 T3 Bie rtu X cao X X3 CX CPU I Compute Address X Address Valid j Address i I I Data l 1 I WR l HY Ne I EL I ES Data t t l l l T S f RD Ef Pha eer T T 1 I Memory Vccess Instruction Next Instruction The ATmegae contains 512 bytes of data EEPROM memory It is organized as a sepa rate data space in which single bytes can be read and written The EEPROM has an endurance of at least 100 000 write erase cycles The access between the EEPROM and the CPU is described bellow specifying the EEPROM Address Registers the EEPROM Data Register and the EEPROM Control Register Memory Programming on page 222 contains a detailed description on EEPROM Pro gramming in SPI or Parallel Programming mode The EEPROM Access Registers are accessible in the I O space The write access time for the EEPROM is given in Table 1 on page 21 A self timing function however lets the user software detect when the next byte can be written If the user code contains instructions that write the EEPROM some precautions must be taken In heavily filtered power supplies Voc is likely to rise or fall slowly on Power up down This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used See Preventing EEPROM Corrup tion on page 23 for details on how to avoid problems in these situations
80. Unit ALU operation In a typical ALU operation two operands are output from the Register File the operation is executed and the result is stored back in the Register File in one clock cycle AMEL 2486R AVR 07 07 10 AMEL Six of the 32 registers can be used as three 16 bit indirect address register pointers for Data Space addressing enabling efficient address calculations One of the these address pointers can also be used as an address pointer for look up tables in Flash Pro gram memory These added function registers are the 16 bit X Y and Z register described later in this section The ALU supports arithmetic and logic operations between registers or between a con stant and a register Single register operations can also be executed in the ALU After an arithmetic operation the Status Register is updated to reflect information about the result of the operation The Program flow is provided by conditional and unconditional jump and call instruc tions able to directly address the whole address space Most AVR instructions have a single 16 bit word format Every Program memory address contains a 16 or 32 bit instruction Program Flash memory space is divided in two sections the Boot program section and the Application program section Both sections have dedicated Lock Bits for write and read write protection The SPM instruction that writes into the Application Flash memory section must reside in the Boot
81. W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Output Compare Register 1 B OCR1BH and OCR1BL Bit f 6 5 4 3 2 1 0 OCR1BH OCRIBL Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16 bit value that is continuously compared with the counter value TCNT1 A match can be used to generate an Output Compare Interrupt or to generate a waveform output on the OC1x pin The Output Compare Registers are 16 bit in size To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers the access is performed using an 8 bit temporary High byte Register TEMP This temporary register is shared by all the other 16 bit registers See Accessing 16 bit Registers on page 79 AMEL 101 2486R AVR 07 07 Input Capture Register 1 ICR1H and ICR1L Timer Counter Interrupt Mask Register TIMSK AMEL Bit 7 6 5 4 3 2 1 0 ICR1 15 8 ICR1H ICR1 7 0 ICR1L Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter TCNT1 value each time an event occurs on the ICP1 pin or optionally on the Analog Comparator Output for Timer Counter1 The Input Capture can be used for defining the counter TOP value The Input Capture Register is 16 bit in size To ensure that both the high and Low bytes are read simultaneously when the CPU accesses these registers the access
82. Write Initial Value Bit Read Write Initial Value Bit Read Write Initial Value Bit Read Write Initial Value Bit Read Write Initial Value Bit Read Write Initial Value Bit Read Write Initial Value Bit Read Write Initial Value 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTBO PORTB R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 T 6 5 4 3 2 1 0 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO DDRB R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 T 6 5 4 3 2 1 0 R R R R R R R R N A N A N A N A N A N A N A N A 7 6 5 4 3 2 1 0 Fontes Pontes porros Pontes porto porter rorrco Porte R R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDCO DDRC R R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 p PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINCO PINC R R R R R R R R 0 N A N A N A N A N A N A N A 7 6 5 4 3 2 1 0 PORTD R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 DDDT Done T Doos pops Dbb3 ponz nob bbb pomo R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PIND7 PiNDe T PINDS PiNDa PiND3 PINb2 PiND PiNDo Pio R R R R R R R R N A N A N A N A N A N A N A N A AMEL s External Interrupts MCU Control Register MCUCR AMEL The external interrupts are triggered by the INTO and INT1 pins Observe that if enabled the interrupts will t
83. acknowledgement of the device s own slave address or the general call address TWSTA and TWSTO must be written to zero When TWAR and TWCR have been initialized the TWI waits until it is addressed by its own slave address or the general call address if enabled followed by the data direction bit If the direction bit is O write the TWI will operate in SR mode otherwise ST mode is entered After its own slave address and the write bit have been received the TWINT Flag is set and a valid status code can be read from TWSR The status code is used to determine the appropriate software action The appropriate action to be taken for each status code is detailed in Table 68 The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master mode see states 0x68 and 0x78 If the TWEA bit is reset during a transfer the TWI will return a Not Acknowledge 1 to SDA after the next received data byte This can be used to indicate that the Slave is not able to receive any more bytes While TWEA is zero the TWI does not acknowledge its own slave address However the Two wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two wire Serial Bus In all sleep modes other than Idle mode the clock system to the TWI is turned off If the TWEA bit is set the interface can still acknowle
84. and until the TWINT Flag is cleared by writing it to one Further data transmission will be carried out as normal with the AVR clocks running as normal Observe that if the AVR is set up with a long start up time the SCL line may be held low for a long time blocking other data transmissions Note that the Two wire Serial Interface Data Register TWDR does not reflect the last byte present on the bus when waking up from these sleep modes Table 69 Status Codes for Slave Transmitter Mode Status Code Application Software Response TWSR Status of the Two wire Serial Bus To TWCR Prescaler Bits and Two wire Serial Interface To from TWDR are 0 Hardware STA STO TWINT TWEA Next Action Taken by TWI Hardware 0xA8 Own SLA R has been received Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK should ACK has been returned be received Load data byte X 0 1 1 Data byte will be transmitted and ACK should be re ceived 0xBO Arbitration lost in SLA R W as Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK should Master own SLA R has been be received received ACK has been returned Load data byte x 0 1 1 Data byte will be transmitted and ACK should be re ceived 0xB8 Data byte in TWDR has been Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK should transmitted ACK has been be received received Load data byte X 0 1 1 Data
85. and Boot Loader section from any software update by the MCU Bit 7 6 5 4 3 2 1 0 RO LL LE wn sre amp teor 73 7 7 See Table 78 and Table 79 for how the different settings of the Boot Loader Bits affect the Flash access If bits 5 2 in RO are cleared zero the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR The Z pointer is don t care during this operation but for future compatibility it is recommended to load the Z pointer with Ox0001 same as used for reading the Lock Bits For future compatibility It is also recommended to set bits 7 6 1 and 0 in RO to 1 when writing the Lock Bits When programming the Lock Bits the entire Flash can be read during the operation Note that an EEPROM write operation will block all software programming to Flash Reading the Fuses and Lock Bits from software will also be prevented during the EEPROM write operation It is recommended that the user checks the status bit EEWE in the EECR Register and verifies that the bit is cleared before writing to the SPMCR Register It is possible to read both the Fuse and Lock Bits from software To read the Lock Bits load the Z pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR the value of the Lock Bits will be loaded in the destination reg
86. are controlled for example by disabling interrupts globally so that no interrupts will occur during execution of these functions ATmega8 L memm 2486R AVR 07 07 Aimegae8 L Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 1 WDTON Fuse Unprogrammed Safety Level 2 WDTON Fuse Programmed 2486R AVR 07 07 The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels Separate procedures are described for each level Assembly Code Example WDT off reset WDT WDR Write logical one to WDCE and WDE in r16 WDTCR ori r16 1 WDCE 1 WDE out WDTCR r16 Turn off WDT ldi r16 out WDTCR r16 0 lt lt WDE ret C Code Example void WDT_off void reset WDT WDR Write logical one to WDCE and WDE WDTCR 1 WDCE 1 WDE Turn off WDT WDTCR 0x00 In this mode the Watchdog Timer is initially disabled but can be enabled by writing the WDE bit to 1 without any restriction A timed sequence is needed when changing the Watchdog Time out period or disabling an enabled Watchdog Timer To disable an enabled Watchdog Timer and or changing the Watchdog Time out the following proce dure must be followed 1 Inthe same operation write a logic one to WDCE and WDE A logic one must be written to WDE regardless of the previ
87. as a Master MCU it can use a 9 bit character frame format UCSZ 7 The ninth bit TXB8 must be set when an address frame TXB8 1 or cleared when a data frame TXB 0 is being transmitted The Slave MCUs must in this case be set to use a 9 bit character frame format The following procedure should be used to exchange data in Multi processor Communi cation mode 1 All Slave MCUs are in Multi processor Communication mode MPCM in UCSRA is set 2 The Master MCU sends an address frame and all slaves receive and read this frame In the Slave MCUs the RXC Flag in UCSRA will be set as normal 3 Each Slave MCU reads the UDR Register and determines if it has been selected If so it clears the MPCM bit in UCSRA otherwise it waits for the next address byte and keeps the MPCM setting 4 The addressed MCU will receive all data frames until a new address frame is received The other Slave MCUs which still have the MPCM bit set will ignore the data frames 5 When the last data frame is received by the addressed MCU the addressed MCU sets the MPCM bit and waits for a new address frame from Master The process then repeats from 2 Using any of the 5 to 8 bit character frame formats is possible but impractical since the Receiver must change between using n and n 1 character frame formats This makes full duplex operation difficult since the Transmitter and Receiver uses the same charac ter size setting If 5 to 8 bit character fram
88. before ADCH is read neither register is updated and the result from the con version is lost When ADCH is read ADC access to the ADCH and ADCL Registers is re enabled The ADC has its own interrupt which can be triggered when a conversion completes When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL the interrupt will trigger even if the result is lost A single conversion is started by writing a logical one to the ADC Start Conversion bit ADSC This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed If a different data channel is selected while a conversion is in progress the ADC will finish the current conversion before performing the channel change In Free Running mode the ADC is constantly sampling and updating the ADC Data Register Free Running mode is selected by writing the ADFR bit in ADCSRA to one The first conversion must be started by writing a logical one to the ADSC bit in ADC SRA In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag ADIF is cleared or not Figure 91 ADC Prescaler ADEN START Reset 7 BIT ADC PRESCALER ADPSO ADPS1 ADPS2 ADC CLOCK SOURCE By default the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution If a lower resolution than 10 bits is needed the inpu
89. bit value MAX OxFF and then restarts from the bottom 0x00 In normal operation the Timer Counter Overflow Flag TOVO will be set in the same timer clock cycle as the TCNTO becomes zero The TOVO Flag in this case behaves like a ninth bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOVO Flag the timer resolution can be increased by software A new counter value can be written anytime 70 ATlmega8 L suum 2486R AVR 07 07 m Airmegae8 L Timer Counter Timing The Timer Counter is a synchronous design and the timer clock clky is therefore Diagrams shown as a clock enable signal in the following figures The figures include information on when Interrupt Flags are set Figure 28 contains timing data for basic Timer Counter operation The figure shows the count sequence close to the MAX value Figure 28 Timer Counter Timing Diagram No Prescaling clk 10 clk clk 5 1 TCNTn MAX 1 MAX J BOTTOM BOTTOM 1 TOVn Figure 29 shows the same timing data but with the prescaler enabled Figure 29 Timer Counter Timing Diagram with Prescaler f i 10 8 clk clk clk 8
90. by the CPU When the CPU does an access to the TCNT1H I O location the CPU accesses the High byte temporary register TEMP The temporary register is updated with the TCNT1H value when the TCNT1L is read and TCNT1H is updated with the temporary register value when TCNT1L is written This allows the CPU to read or write the entire 16 bit counter value within one clock cycle via the 8 bit data bus It is impor tant to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results The special cases are described in the sections where they are of importance Depending on the mode of operation used the counter is cleared incremented or dec remented at each timer clock clky The clk can be generated from an external or internal clock source selected by the clock select bits CS12 0 When no clock source is selected CS12 0 0 the timer is stopped However the TCNT1 value can be accessed by the CPU independent of whether clk is present or not A CPU write over rides has priority over all counter clear or count operations 82 ATmega8 L memm 2486R AVR 07 07 X f rmegae8 L The counting sequence is determined by the setting of the Waveform Generation mode bits WGM13 0 located in the Timer Counter Control Registers A and B TCCR1A and TCCR1B There are close connections between how the counter behaves counts and how waveforms are gene
91. byte will be transmitted and ACK should be re ceived 0xCO Data byte in TWDR has been No TWDR action or 0 0 1 0 Switched to the not addressed Slave mode transmitted NOT ACK has been no recognition of own SLA or GCA received No TWDR action or 0 0 1 1 Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 No TWDR action or 1 0 1 0 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free No TWDR action 1 0 1 1 Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the bus becomes free 0xC8 Last data byte in TWDR has been No TWDR action or 0 0 1 0 Switched to the not addressed Slave mode transmitted TWEA 0 ACK no recognition of own SLA or GCA has been received No TWDR action or 0 0 1 1 Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 No TWDR action or 1 0 1 0 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free No TWDR action 1 0 1 1 Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the bus becomes free 2486R
92. clock and shifted into the Receive Shift Register until the first stop bit of a frame is received A second stop bit will be ignored by the Receiver When the first stop bit is received i e a complete serial frame is present in the Receive Shift Register the contents of the Shift Register will be moved into the receive buffer The receive buffer can then be read by reading the UDR I O location The following code example shows a simple USART receive function based on polling of the Receive Complete RXC Flag When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero The USART has to be initialized before the function can be used Assembly Code Example USART Receive Wait for data to be received sbis UCSRA RXC rjmp USART Receive Get and return received data from buffer in r16 UDR ret C Code Example unsigned char USART_Receive void Wait for data to be received while UCSRA amp 1 lt lt RXC Get and return received data from buffer return UDR Note 1 See About Code Examples on page 8 The function simply waits for data to be present in the receive buffer by checking the RXC Flag before reading the buffer and returning the value AMEL 143 AMEL Receiving Frames with 9 Data If 9 bit characters are used UCSZ 7 the ninth bit must be read from the RXB8 bit in Bits UCSRB before reading
93. clock cycle even when the timer is stopped This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer Counter clock is enabled Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle there are risks involved when changing TCNT1 when using any of the Output Compare channels independent of whether the Timer Counter is running or not If the value written to TCNT1 equals the OCR1x value the Compare Match will be missed resulting in incorrect waveform generation Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values The Compare Match for the TOP will be ignored and the counter will continue to OXFFFF Similarly do not write the TCNT1 value equal to BOTTOM when the counter is downcounting The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output The easiest way of setting the OC1x value is to use the Force Output Compare FOC1x strobe bits in Normal mode The OC1x Register keeps its value even when changing between Waveform Generation modes Be aware that the COM1x1 0 bits are not double buffered together with the compare value Changing the COM1x1 0 bits will take effect immediately 86 ATmega8 L mmm 2486R AVR 07 07 ms f 11 C023 Compare Match Output Unit 2486R AVR 07 07 The Compare Output mode COM1x1 0 bits have two functi
94. compiler documentation for more details 8 ATmega8 L m E 2486R AVR 07 07 Aimegae8 L AVR CPU Core Introduction This section discusses the AVR core architecture in general The main function of the CPU core is to ensure correct program execution The CPU must therefore be able to access memories perform calculations control peripherals and handle interrupts Architectural Overview Figure 2 Block Diagram of the AVR MCU Architecture Data Bus 8 bit Program Status Counter and Control SRAM i O Module n Interrupt 32x8 Unit Instruction General Register Purpose SPI Registrers Unit Instruction Watchdog Decoder Timer o Cc E amp Q o o Y E Analog Control Lines S Comparator E 3 o o o 5 a i O Module Data i O Module 2 EEPROM I O Lines In order to maximize performance and parallelism the AVR uses a Harvard architecture with separate memories and buses for program and data Instructions in the Program memory are executed with a single level pipelining While one instruction is being exe cuted the next instruction is pre fetched from the Program memory This concept enables instructions to be executed in every clock cycle The Program memory is In System Reprogrammable Flash memory The fast access Register File contains 32 x 8 bit general purpose working registers with a single clock cycle access time This allows single cycle Arithmetic Logic
95. data will be lost in the process An example of an arbitration situation is depicted below where two masters are trying to transmit data to a Slave Receiver Voc Figure 87 An Arbitration Example Device 1 Device 2 Device 3 MASTER MASTER SLAVE eee Device n R1 R2 TRANSMITTER TRANSMITTER RECEIVER SDA gt SCL Several different scenarios may arise during arbitration as described below AMEL 191 192 AMEL Two or more masters are performing identical communication with the same Slave In this case neither the Slave nor any of the masters will know about the bus contention Two or more masters are accessing the same Slave with different data or direction bit In this case arbitration will occur either in the READ WRITE bit or in the data bits The masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition depending on application software action Two or more masters are accessing different slaves In this case arbitration will occur in the SLA bits Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master If addressed the
96. depend on how long time the source needs to charge the S H capacitor with can vary widely The user is recom mended to only use low impedant sources with slowly varying signals since this minimizes the required charge transfer to the S H capacitor Signal components higher than the Nyquist frequency fapc 2 should not be present for either kind of channels to avoid distortion from unpredictable signal convolution The user is advised to remove high frequency components with a low pass filter before applying the signals as inputs to the ADC Figure 95 Analog Input Circuitry 1 100 kQ D Cojy 14 pF T Voc 2 ADCn WW l Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements If conversion accuracy is critical the noise level can be reduced by applying the following techniques 1 Keep analog signal paths as short as possible Make sure analog tracks run over the ground plane and keep them well away from high speed switching digital tracks 2 The AVggc pin on the device should be connected to the digital Voc supply voltage via an LC network as shown in Figure 96 3 Use the ADC noise canceler function to reduce induced noise from the CPU 4 f any ADC 3 0 port pins are used as digital outputs it is essential that these do not switch while a conversion is in progress However using the Two wire Interface ADC4 and ADC5 will only affect
97. described in System Clock and Clock Options on page 25 If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start up time the MCU will still wake up but no interrupt will be generated The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt The MCU Control Register contains control bits for interrupt sense control and general MCU functions Bit 7 6 5 4 3 2 1 0 Tse sw swi smo isc sci sco T co wcucn Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 3 2 ISC11 ISC10 Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I bit and the corresponding interrupt mask in the GICR are set The level and edges on the external INT1 pin that activate the interrupt are defined in Table 31 The value on the INT1 pin is sampled before detecting edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guaran teed to generate an interrupt If low level interrupt is selected the low level must be held until the completion of the currently executing instruction to generate an interrupt Table 31 Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request 0 1 Any logical change on INT1 genera
98. domain This allows halting the CPU and I O clocks in order to reduce noise generated by digital circuitry This gives more accu rate ADC conversion results The device has the following clock source options selectable by Flash Fuse Bits as shown below The clock from the selected source is input to the AVR clock generator and routed to the appropriate modules Table 2 Device Clocking Options Select Device Clocking Option CKSEL3 0 External Crystal Ceramic Resonator 1111 1010 External Low frequency Crystal 1001 External RC Oscillator 1000 0101 Calibrated Internal RC Oscillator 0100 0001 External Clock 0000 Note 1 Forall fuses 1 means unprogrammed while 0 means programmed The various choices for each clocking option is given in the following sections When the CPU wakes up from Power down or Power save the selected clock source is used to time the start up ensuring stable Oscillator operation before instruction execution starts When the CPU starts from reset there is as an additional delay allowing the power to reach a stable level before commencing normal operation The Watchdog Oscillator is used for timing this real time part of the start up time The number of WDT Oscillator cycles used for each time out is shown in Table 3 The frequency of the Watchdog Oscil lator is voltage dependent as shown in ATmegae8 Typical Characteristics The device is shipped with CKSEL 0001 and SUT
99. e After the TWI has transmitted SLA R W e After the TWI has transmitted an address byte e After the TWI has lost arbitration e After the TWI has been addressed by own slave address or general call e After the TWI has received a data byte e After a STOP or REPEATED START has been received while still addressed as a Slave When a bus error has occurred due to an illegal START or STOP condition Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBRO TWBR Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 0 TWI Bit Rate Register TWBR selects the division factor for the bit rate generator The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes See Bit Rate Generator Unit on page 170 for calculating bit rates Bit 7 6 5 4 3 2 1 0 TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE TWCR Read Write R W R W R W R W R R W R R W Initial Value 0 0 0 0 0 0 0 0 The TWCR is used to control the operation of the TWI It is used to enable the TWI to initiate a Master access by applying a START condition to the bus to generate a Receiver acknowledge to generate a stop condition and to control halting of the bus while the data to be written to the bus are written to the TWDR It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible Bit 7 TWINT TWI Interrupt Flag
100. equation R _ log TOP 1 PFCPWM log 2 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 WGM13 0 8 or the value in OCR1A AMEL ss AMEL WGM13 0 9 The counter has then reached the TOP and changes the count direction The TCNT1 value will be equal to TOP for one timer clock cycle The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 40 The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1 The OC1x Interrupt Flag will be set when a Compare Match occurs Figure 40 Phase and Frequency Correct PWM Mode Timing Diagram OCnA Interrupt Flag Set o pu ny pened ICFn Interrupt Flag Set i i i i Interrupt on TOP OCRnx TOP Update and i TOVn Interrupt Flag Set Y Interrupt on Bottom TCNTn y Y Y y T OCnx COMnx1 0 2 OCnx COMnx1 0 3 Period 1 4 2 Has oe 4 The Timer Counter Overflow Flag TOV1 is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at BOTTOM When either OCRI1A or ICR1 is used
101. for defining the TOP value the OC1A or ICF1 Flag set when TCNT1 has reached TOP The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers If the TOP value is lower than any of the Compare Registers a Compare Match will never occur between the TCNT1 and the OCR1x As Figure 40 shows the output generated is in contrast to the Phase Correct mode symmetrical in all periods Since the OCR1x Registers are updated at BOTTOM the length of the rising and the falling slopes will always be equal This gives symmetrical output pulses and is therefore frequency correct Using the ICR1 Register for defining TOP works well when using fixed TOP values By using ICR1 the OCR1A Register is free to be used for generating a PWM output on OC1A However if the base PWM frequency is actively changed by changing the TOP value using the OCR1A as TOP is clearly a better choice due to its double buffer feature In phase and frequency correct PWM mode the compare units allow generation of PWM waveforms on the OC1x pins Setting the COM1x1 0 bits to 2 will produce a non inverted PWM and an inverted PWM output can be generated by setting the COM1x1 0 94 ATlmega8 L memm 2486R AVR 07 07 2 f 11 C025 LL Timer Counter Timing Diagrams
102. for two cycles before the next instruction is executed Bit 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM When the correct address is set up in the EEAR Register the EERE bit must be written to a logic one to trigger the EEPROM read The EEPROM read access takes one instruction and the requested data is available immediately When the EEPROM is read the CPU is halted for four cycles before the next instruction is executed The user should poll the EEWE bit before starting the read operation If a write operation is in progress it is neither possible to read the EEPROM nor to change the EEAR Register The calibrated Oscillator is used to time the EEPROM accesses Table 1 lists the typical programming time for EEPROM access from the CPU Table 1 EEPROM Programming Time Number of Calibrated RC Symbol Oscillator Cycles Typ Programming Time EEPROM Write from CPU 8448 8 5 ms Note 1 Uses 1 MHz clock independent of CKSEL Fuse settings AMEL n 2486R AVR 07 07 AMEL The following code examples show one assembly and one C function for writing to the EEPROM The examples assume that interrupts are controlled for example by dis abling interrupts globally so that no interrupts will occur during execution of these functions The examples also assume that no Flash boot loader is present in the soft ware If such code is present the EEPROM write function must al
103. from Reset SUT1 0 Power save Vcc 5 0V Recommended Usage 00 18 CK BOD enabled 01 18 CK 4 1 ms Fast rising power 10 18 CK 65 ms Slowly rising power 11 6 CK 4 1 ms Fast rising power or BOD enabled Note 1 This option should not be used when operating close to the maximum frequency of the device AMEL 2 Calibrated Internal RC Oscillator AMEL The calibrated internal RC Oscillator provides a fixed 1 0 2 0 4 0 or 8 0 MHz clock All frequencies are nominal values at 5V and 25 C This clock may be selected as the sys tem clock by programming the CKSEL Fuses as shown in Table 9 If selected it will operate with no external components The CKOPT Fuse should always be unpro grammed when using this clock option During reset hardware loads the 1 MHz calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator At 5V 25 C and 1 0 MHz Oscillator frequency selected this calibration gives a frequency within x 396 of the nominal frequency Using run time calibration methods as described in application notes available at www atmel com avr it is possible to achieve 1 accuracy at any given Voc and Temperature When this Oscillator is used as the chip clock the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time out For more information on the pre programmed calibration value see the section Calibration Byte on page 225 Table 9 Internal
104. further details The Boot Lock Bits can be set in software and in Serial or Parallel Programming mode but they can be cleared by a chip erase command only The general Write Lock Lock bit mode 2 does not control the program ming of the Flash memory by SPM instruction Similarly the general Read Write Lock Lock bit mode 3 does not control reading nor writing by LPM SPM if it is attempted AMEL 211 Entering the Boot Loader Program AMEL Table 78 Boot Lock BitO Protection Modes Application Section BLBO Mode BLBO2 BLBO1 Protection No restrictions for SPM or LPM accessing the Application 1 1 1 section 2 1 0 SPM is not allowed to write to the Application section SPM is not allowed to write to the Application section and LPM executing from the Boot Loader section is not allowed to read 3 0 0 from the Application section If Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section Note 1 1 means unprogrammed 0 means programmed Table 79 Boot Lock Bit1 Protection Modes Boot Loader Section BLB1 Mode BLB12 BLB11 Protection No restrictions for SPM or LPM acces
105. in Timed Sequences for Changing the Configuration of the Watchdog Timer on page 45 Removed bit 4 ADHSM from Special Function IO Register SFIOR on page 58 Added note 2 to Figure 103 on page 215 Updated item 4 in the Serial Programming Algorithm on page 238 Added twp ruse to Table 97 on page 239 and updated Read Calibration Byte Byte 3 in Table 98 on page 240 Updated Absolute Maximum Ratings and DC Characteristics in Electrical Characteristics on page 242 28 ATmega8 L mmm 2486R AVR 07 07 A mega8 L Changes from Rev 2486J 02 03 to Rev 2486K 08 03 Changes from Rev 24861 12 02 to Rev 2486J 02 03 2486R AVR 07 07 10 11 12 13 14 15 16 17 18 Updated Vo values in Table 15 on page 38 Updated ADC Characteristics on page 248 Updated ATmega 8 Typical Characteristics on page 249 Updated Erratas on page 296 Improved the description of Asynchronous Timer Clock clkAsy on page 26 Removed reference to the Multipurpose Oscillator application note and the 32 kHz Crystal Oscillator application note which do not exist Corrected OCn waveforms in Figure 38 on page 90 Various minor Timer 1 corrections Various minor TWI corrections Added note under Filling the Temporary Buffer Page Loading on page 216 about writing to the EEPROM during an SPM Page load Removed ADHSM completely Added section EEPROM Write
106. is set In this case the Compare Match is ignored but the set or clear is done at BOT TOM See Fast PWM Mode on page 89 for more details Table 38 shows the COM1x1 0 bit functionality when the WGM13 0 bits are set to the phase correct or the phase and frequency correct PWM mode Table 38 Compare Output Mode Phase Correct and Phase and Frequency Correct PWM COM1A1 COM1A0 COM1B1 COM1B0 Description 0 0 Normal port operation OC1A OC1B disconnected 0 1 WGM13 0 9 or 14 Toggle OC1A on Compare Match OC1B disconnected normal port operation For all other WGM1 settings normal port operation OC1A OC1B disconnected 1 0 Clear OC1A OC1B on Compare Match when up counting Set OC4A OC1B on Compare Match when downcounting 1 1 Set OC1A OC1B on Compare Match when up counting Clear OC4A OC1B on Compare Match when downcounting Note 1 A special case occurs when OCR1A OCR1B equals TOP and COM1A1 COM1B1 is set See Phase Correct PWM Mode on page 91 for more details Bit 3 FOC1A Force Output Compare for channel A e Bit2 FOCA1B Force Output Compare for channel B The FOC1A FOC1B bits are only active when the WGM13 0 bits specifies a non PWM mode However for ensuring compatibility with future devices these bits must be set to zero when TCCR1A is written when operating in a PWM mode When writing a logical one to the FOC1A FOC1B bit an immediate Compare Match is forced on the waveform g
107. is given as a function parameter For the assembly code the baud rate parameter is assumed to be stored in the r17 r16 Registers When the function writes to the UCSRC Register the URSEL bit MSB must be set due to the sharing of I O location by UBRRH and UCSRC n ATmega8 L memm 2486R AVR 07 07 X f megae8 L Assembly Code Example USART_Init Set baud rate out UBRRH r17 out UBRRL r16 Enable receiver and transmitter ldi r16 1 lt lt RXEN 1 lt lt TXEN out UCSRB r16 Set frame format 8data 2stop bit ldi r16 1 lt lt URSEL 1 lt lt USBS 3 lt lt UCSZ0 out UCSRC r16 ret C Code Example define FOSC 1843200 Clock Speed define BAUD 9600 define MYUBRR FOSC 16 BAUD 1 void main void USART_Init MYUBRR void USART_Init unsigned int ubrr Set baud rate UBRRH unsigned char ubrr gt gt 8 UBRRL unsigned char ubrr Enable receiver and transmitter UCSRB 1 lt lt RXEN 1 lt lt TXEN Set frame format 8data 2stop bit UCSRC 1 lt lt URSEL 1 lt lt USBS 3 UCSZ0 Note 1 See About Code Examples on page 8 More advanced initialization routines can be made that include frame format as parame ters disable interrupts and so on However many applications use a fixed setting of the Baud and Control Registers and for these types of applications the init
108. maximum frequency of an external clock it can detect is half the sampling frequency Nyquist sampling theorem However due to vari ation of the system clock frequency and duty cycle caused by Oscillator source crystal resonator and capacitors tolerances it is recommended that maximum frequency of an external clock source is less than f jo 2 5 An external clock source can not be prescaled Figure 31 Prescaler for Timer CounterO and Timer Counter1 clkig 10 BIT T C PRESCALER PSR10 TIMER COUNTER1 CLOCK SOURCE TIMER COUNTERO CLOCK SOURCE clk clk Note 1 The synchronization logic on the input pins T1 TO is shown in Figure 30 Bit 7 6 5 4 3 2 1 0 TET us T es D PERI sron Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 0 PSR10 Prescaler Reset Timer Counter1 and Timer CounterO When this bit is written to one the Timer Counter1 and Timer CounterO prescaler will be reset The bit will be cleared by hardware after the operation is performed Writing a zero to this bit will have no effect Note that Timer Counter1 and Timer CounterO share the same prescaler and a reset of this prescaler will affect both timers This bit will always be read as zero AMEL AMEL 16 bit The 16 bit Timer Counter unit allows accurate program execution timing event man 1 agement wave generation and signal timing measurement The main feat
109. non inverted PWM For non PWM modes the COM1x1 0 bits control whether the out put should be set cleared or toggle at a Compare Match See Compare Match Output Unit on page 87 For detailed timing information refer to Timer Counter Timing Diagrams on page 95 The simplest mode of operation is the Normal mode WGM13 0 0 In this mode the counting direction is always up incrementing and no counter clear is performed The counter simply overruns when it passes its maximum 16 bit value MAX OxFFFF and then restarts from the BOTTOM 0x0000 In normal operation the Timer Counter Over flow Flag TOV1 will be set in the same timer clock cycle as the TCNT1 becomes zero The TOV1 Flag in this case behaves like a 17th bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOV 1 Flag the timer resolution can be increased by software There are no special cases to consider in the Normal mode a new counter value can be written anytime The Input Capture unit is easy to use in Normal mode However observe that the maxi mum interval between the external events must not exceed the resolution of the counter If the interval between events are too long the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit The Output Compare units can be used to generate interrupts at some given time Using the Output Compare to generate
110. not ready yet ret re enable the RWW section ldi spmcrval 1 lt lt RWWSRE 1 lt lt SPMEN rcallDo_spm rjmp Return Do_spm check for previous SPM complete Wait_spm in temp1 SPMCR sbrc temp1 SPMEN rjmp Wait_spm input spmcrval determines SPM action disable interrupts if enabled store status in temp2 SREG cli check that no EEPROM write access is present Wait ee sbic EECR EEWE rjmp Wait_ee SPM timed sequence out SPMCR spmcrval spm restore SREG to enable interrupts if originally enabled out SREG temp2 ret In Table 82 through Table 84 the parameters used in the description of the self pro gramming are given Table 82 Boot Size Configuration Boot Reset Boot Address Application Loader End Start Boot Boot Flash Flash Application Loader BOOTSZ1 BOOTSZO Size Pages Section Section Section Section 128 0x000 OxF80 i words OxF7F OxFFF OxF7F OxF80 256 0x000 OxFOO words OxEFF oxFFF CEFE OxFOO 512 0x000 OxE00 E L words m OxDFF OxFFF OxDFF OxE00 1024 0x000 0xCOO0 2 9 words 32 OxBFF OxFFF OxBFF OxCOO 220 ATImega8 L mmm 2486R AVR 07 07 X A megae8 L 2486R AVR 07 07 Note The different BOOTSZ Fuse configurations are shown in Figure 102 Table 83 Read While Write Limit Section Pages Address Read While Write section RWW 96 0x000 OXBFF N
111. operation turns the content of every memory location in both the Program and EEPROM arrays into OxFF Depending on CKSEL Fuses a valid clock must be present The minimum low and high periods for the Serial Clock SCK input are defined as follows Low gt 2 CPU clock cycles for fy lt 12 MHz 3 CPU clock cycles for fy 2 12 MHz High gt 2 CPU clock cycles for fax lt 12 MHz 3 CPU clock cycles for fex 12 MHz AMEL 237 AMEL Serial Programming When writing serial data to the ATmega8 data is clocked on the rising edge of SCK Algonkin When reading data from the ATmega8 data is clocked on the falling edge of SCK See Figure 113 for timing details To program and verify the ATmega 8 in the Serial Programming mode the following sequence is recommended See four byte instruction formats in Table 98 1 Power up sequence Apply power between Vcc and GND while RESET and SCK are set to 0 In some systems the programmer can not guarantee that SCK is held low during Power up In this case RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to 0 2 Wait for at least 20 ms and enable Serial Programming by sending the Program ming Enable serial instruction to pin MOSI 3 The Serial Programming instructions will not work if the communication is out of synchronization When in sync the second byte 0x53 will echo back when issuing the third byte of the Programmin
112. presented there one relevant for bus speeds below 100 kHz and one valid for bus speeds up to 400 kHz Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line The level of the data line must be stable when the clock line is high The only exception to this rule is for generating start and stop conditions Figure 69 Data Validity SDA Data Stable Data Stable Data Change The Master initiates and terminates a data transmission The transmission is initiated when the Master issues a START condition on the bus and it is terminated when the Master issues a STOP condition Between a START and a STOP condition the bus is considered busy and no other master should try to seize control of the bus A special case occurs when a new START condition is issued between a START and STOP con dition This is referred to as a REPEATED START condition and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus After a REPEATED START the bus is considered busy until the next STOP This is identical to the START behavior and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet unless otherwise noted As depicted below START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high 164 ATmega8 L _ 2486R AVR 07 07 Address Packet Format 2486R AVR 07 07 ATmega8 L
113. program section During interrupts and subroutine calls the return address Program Counter PC is stored on the Stack The Stack is effectively allocated in the general data SRAM and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM All user programs must initialize the SP in the reset routine before subroutines or interrupts are executed The Stack Pointer SP is read write accessible in the I O space The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture The memory spaces in the AVR architecture are all linear and regular memory maps A flexible interrupt module has its control registers in the I O space with an additional global interrupt enable bit in the Status Register All interrupts have a separate Interrupt Vector in the Interrupt Vector table The interrupts have priority in accordance with their Interrupt Vector position The lower the Interrupt Vector address the higher the priority The I O memory space contains 64 addresses for CPU peripheral functions as Control Registers SPI and other I O functions The I O Memory can be accessed directly or as the Data Space locations following those of the Register File 0x20 Ox5F ATmega8 L memm 2486R AVR 07 07 A rmega8 L Arithmetic Logic Unit ALU Status Register 2486R AVR 07 07 The high performance AVR ALU operates in direct connecti
114. provides a high resolution phase correct PWM waveform generation option The phase correct PWM mode is based on a dual slope operation The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM In non inverting Compare Output mode the Output Compare OC2 is cleared on the Compare Match between TCNT2 and OCR2 while upcounting and set on the Compare Match while downcounting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the symmetric feature of the dual slope PWM modes these modes are preferred for motor control applications The PWM resolution for the phase correct PWM mode is fixed to eight bits In phase correct PWM mode the counter is incremented until the counter value matches MAX When the counter reaches MAX it changes the count direction The TCNT2 value will be equal to MAX for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 51 The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT2 slopes repre sent compare matches between OCR2 and TCNT2 AMEL 113 AMEL Figure 51 Phase Correct PWM Mode Timing Diagram OCn Interrupt Flag Set OCRn Update 4 zE 1
115. rising power 1 01 16K CK _ Crystal Oscillator BOD enabled 1 10 16K CK 4 1 ms Crystal Oscillator fast rising power 1 11 16K CK 65 ms Crystal Oscillator slowly rising power Notes 1 These options should only be used when not operating close to the maximum fre quency of the device and only if frequency stability at start up is not important for the application These options are not suitable for crystals 2 These options are intended for use with ceramic resonators and will ensure fre quency stability at start up They can also be used with crystals when not operating close to the maximum frequency of the device and if frequency stability at start up is not important for the application To use a 32 768 kHz watch crystal as the clock source for the device the Low fre quency Crystal Oscillator must be selected by setting the CKSEL Fuses to 1001 The crystal should be connected as shown in Figure 11 By programming the CKOPT Fuse the user can enable internal capacitors on XTAL1 and XTAL2 thereby removing the need for external capacitors The internal capacitors have a nominal value of 36 pF When this Oscillator is selected start up times are determined by the SUT Fuses as shown in Table 6 Table 6 Start up Times for the Low frequency Crystal Oscillator Clock Selection SUT1 0 00 Start up Time from Power down and Power save 1K CK Additional Delay from Reset Vec 5 0V Recommended Usage
116. slaves that acknowledged the general call Note that transmitting the general call address followed by a Read bit is meaningless as this would cause contention if several slaves started transmitting different data All addresses of the format 1111 xxx should be reserved for future purposes Figure 71 Address Packet Format Addr MSB Addr LSB R W ACK COC SCL AMEL 165 Data Packet Format Combining Address and Data Packets into a Transmission AMEL All data packets transmitted on the TWI bus are nine bits long consisting of one data byte and an acknowledge bit During a data transfer the Master generates the clock and the START and STOP conditions while the Receiver is responsible for acknowledging the reception An Acknowledge ACK is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle If the Receiver leaves the SDA line high a NACK is sig nalled When the Receiver has received the last byte or for some reason cannot receive any more bytes it should inform the Transmitter by sending a NACK after the final byte The MSB of the data byte is transmitted first Figure 72 Data Packet Format Data MSB DataLSB ACK Aggregate 5 aa SDA V j EM i t SDA from x d Transmitter i 1 ji m T l cil sa SDA from Receiver 1 it 1 I SCL from Master 4 B i NT 1 2 7 STOP REPEATED SLA R W Data Byte START or Next i Data Byt
117. the INL is the maximum deviation of an actual transition compared to an ideal transition for any code Ideal value 0 LSB Figure 99 Integral Non linearity INL Bip Ideal ADC Actual ADC p gt Vgge nput Voltage e Differential Non linearity DNL The maximum deviation of the actual code width the interval between two adjacent transitions from the ideal code width 1 LSB Ideal value 0 LSB 24 ATmega8 L memm f megae8 L Figure 100 Differential Non linearity DNL Output Code i sss Ox3FF NI La s o pn 0x000 f 0 Vmgr Input Voltage e Quantization Error Due to the quantization of the input voltage into a finite number of codes a range of input voltages 1 LSB wide will code to the same value Always 0 5 LSB e Absolute accuracy The maximum deviation of an actual unadjusted transition compared to an ideal transition for any code This is the compound effect of offset gain error differential error non linearity and quantization error Ideal value 0 5 LSB ADC Conversion Result After the conversion is complete ADIF is high the conversion result can be found in the ADC Result Registers ADCL ADCH For single ended conversion the result is Vy 1024 ADC IN 7 VREF where Vy is the voltage on the selected input pin and Vgep the selected voltage refer ence see Table 74 on page 206 and Table 75 on page 206 0x000 represen
118. the appro priate software action For each status code the required software action and details of the following serial transfer are given in Table 66 to Table 69 Note that the prescaler bits are masked to zero in these tables vs ATmega8 L mmm 2486R AVR 07 07 A mmega8 L Master Transmitter Mode 2486R AVR 07 07 In the Master Transmitter mode a number of data bytes are transmitted to a Slave Receiver see Figure 78 In order to enter a Master mode a START condition must be transmitted The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered If SLA W is transmitted MT mode is entered if SLA R is transmitted MR mode is entered All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero Voc Device 1 Device 2 MASTER SLAVE Device 3 Device n R1 R2 TRANSMITTER RECEIVER Figure 78 Data Transfer in Master Transmitter Mode SDA SCL A START condition is sent by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 1 0 X 1 0 X TWEN must be set to enable the Two wire Serial Interface TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag The TWI will then test the Two wire Serial Bus and g
119. the conversion on ADC4 and ADC5 and not the other ADC channels 202 ATlmega8 L memm 2486R AVR 07 07 X X f megae8 L Figure 96 ADC Power Connections I gt c I 1 Oo C l 1 0 o a 9 po 5 N C O O S 1 Q A a a a iS S t amp v a c 29 8 8 8 8 a Oo gt Ig a o a T I Oo c I com SI c 1 PC1 ADC1 l I PCO ADCO I I I ADC7 I I I GND L l Zi AREF S I ADC6 Eq c gi e AVCC T I xh adu eat es s uus ees s I PB5 ADC Accuracy Definitions An n bit single ended ADC converts a voltage linearly between GND and Vpe_r in 2 steps LSBs The lowest code is read as 0 and the highest code is read as 2 1 Several parameters describe the deviation from the ideal behavior e Offset The deviation of the first transition 0x000 to 0x001 compared to the ideal transition at 0 5 LSB Ideal value 0 LSB Figure 97 Offset Error Ideal ADC Actual ADC Offset Error gt Veer Input Voltage AMEL 203 2486R AVR 07 07 AMEL e Gain error After adjusting for offset the gain error is found as the deviation of the last transition Ox3FE to Ox3FF compared to the ideal transition at 1 5 LSB below maximum Ideal value 0 LSB Figure 98 Gain Error Output Code A Gain Error Ideal ADC Actual ADC Vrer Input Voltage e Integral Non linearity INL After adjusting for offset and gain error
120. the low bits from the UDR This rule applies to the FE DOR and PE Status Flags as well Read status from UCSRA then data from UDR Reading the UDR I O location will change the state of the receive buffer FIFO and consequently the TXB8 FE DOR and PE bits which all are stored in the FIFO will change 144 ATmega8 L mmm 2486R AVR 07 07 w A mega8 L The following code example shows a simple USART receive function that handles both 9 bit characters and the status bits Assembly Code Example USART Receive Wait for data to be received sbis UCSRA RXC rjmp USART Receive Get status and ninth bit then data from buffer in r18 UCSRA in r17 UCSRB in r16 UDR If error return 1 andi 118 1 lt lt FE 1 lt lt DOR 1 lt lt PE breq USART_ReceiveNoError ldi r17 HIGH 1 ldi r16 LOW 1 USART ReceiveNoError Filter the ninth bit then return lsr r17 andi r17 0x01 ret C Code Example unsigned int USART Receive void unsigned char status resh resl Wait for data to be received while UCSRA amp 1 lt lt RXC Get status and ninth bit then data from buffer status UCSRA resh UCSRB resl UDR If error return 1 if status amp 1 lt lt FE 1 lt lt DOR 1 lt lt PE return 1 Filter the ninth bit then return resh resh 1 amp 0x01 return resh lt lt 8 res1
121. the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test condition 4 Although each I O port can source more than the test conditions 20mA at Vcc 5V 10mA at Vcc 3V under steady state conditions non transient the following must be observed PDIP TQFP and QFN MLF Package 1 The sum of all IOH for all ports should not exceed 300 mA 2 The sum of all IOH for port CO C5 should not exceed 100 mA 3 The sum of all IOH for ports BO B7 C6 DO D7 and XTAL2 should not exceed 200 mA If IOH exceeds the test condition VOH may exceed the related specification Pins are not guaranteed to source current greater than the listed test condition 5 Minimum Vec for Power down is 2 5V 2486R AVR 07 07 AMEL 243 AMEL External Clock Drive Figure 114 External Clock Drive Waveforms Waveforms teHcx t CHCX lcicu gt I I tore Vip A Vit AW toLex teret External Clock Drive Table 99 External Clock Drive Vec 2 7V to 5 5V Voc 4 5V to 5 5V Symbol Parameter Min Max Min Max Units ltojc Oscillator Frequency 0 8 0 16 MHz tercL Clock Period 125 62 5 ns tcucx High Time 50 25 ns teLcx Low Time 50 25 ns lei cH Rise Time 1 6 0 5 us icucL Fall Time 1 6 0 5 us Change in period from one 2 2 AteLcL clock cycle to the next Table 100 External RC Oscillator Typical Fr
122. timer continues to run allowing the user to maintain a timer base while the rest of the device is sleeping The ADC Noise Reduction mode stops the CPU and all O modules except asynchronous timer and ADC to minimize switching noise during ADC conversions In Standby mode the crystal resonator Oscillator is running while the rest of the device is sleeping This allows very fast start up combined with low power consumption The device is manufactured using Atmel s high density non volatile memory technology The Flash Program memory can be reprogrammed In System through an SPI serial interface by a conventional non volatile memory programmer or by an On chip boot program running on the AVR core The boot program can use any interface to download the application program in the Application Flash memory Software in the Boot Flash Section will continue to run while the Application Flash Section is updated providing true Read While Write operation By combining an 8 bit RISC CPU with In System Self Programmable Flash on a monolithic chip the Atmel ATmega8 is a powerful microcon troller that provides a highly flexible and cost effective solution to many embedded control applications The ATmega8 AVR is supported with a full suite of program and system development tools including C compilers macro assemblers program debugger simulators In Cir cuit Emulators and evaluation kits Disclaimer Typical values contained in this datasheet are based o
123. to Digital Converter ADC Analog Comparator 2486R AVR 07 07 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system In general sleep modes should be used as much as possi ble and the sleep mode should be selected so that as few as possible of the device s functions are operating All functions not needed should be disabled In particular the following modules may need special consideration when trying to achieve the lowest possible power consumption If enabled the ADC will be enabled in all sleep modes To save power the ADC should be disabled before entering any sleep mode When the ADC is turned off and on again the next conversion will be an extended conversion Refer to Analog to Digital Con verter on page 196 for details on ADC operation When entering Idle mode the Analog Comparator should be disabled if not used When entering ADC Noise Reduction mode the Analog Comparator should be disabled In the other sleep modes the Analog Comparator is automatically disabled However if the Analog Comparator is set up to use the Internal Voltage Reference as input the Analog Comparator should be disabled in all sleep modes Otherwise the Internal Voltage Ref erence will be enabled independent of sleep mode Refer to Analog Comparator on page 193 for details on how to configure the Analog Comparator AMEL s Brown out Detector Internal Voltage Reference Watc
124. to which the TWI will respond when programmed as a Slave Transmitter or Receiver and not needed in the Master modes In multimaster systems TWAR must be set in masters which can be addressed as Slaves by other Masters The LSB of TWAR is used to enable recognition of the general call address 0x00 There is an associated address comparator that looks for the slave address or general call address if enabled in the received serial address If a match is found an interrupt request is generated Bits 7 1 TWA TWI Slave Address Register These seven bits constitute the slave address of the TWI unit Bit0 TWGCE TWI General Call Recognition Enable Bit If set this bit enables the recognition of a General Call given over the Two wire Serial Bus The AVR TWI is byte oriented and interrupt based Interrupts are issued after all bus events like reception of a byte or transmission of a START condition Because the TWI is interrupt based the application software is free to carry on other operations during a TWI byte transfer Note that the TWI Interrupt Enable TWIE bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT Flag should generate an interrupt request If the TWIE bit is cleared the application must poll the TWINT Flag in order to detect actions on the TWI bus When the TWINT Flag is asserted the TWI has finished an operation and awaits appli
125. user is in doubt whether the time before re entering Power save or Extended Standby mode is sufficient the following algorithm can be used to ensure that one TOSC1 cycle has elapsed 1 Write a value to TCCR2 TCNT2 or OCR2 2 Wait until the corresponding Update Busy Flag in ASSR returns to zero 3 Enter Power save or Extended Standby mode e When the asynchronous operation is selected the 32 768 kHZ Oscillator for Timer Counter2 is always running except in Power down and Standby modes After a Power up Reset or Wake up from Power down or Standby mode the user should be aware of the fact that this Oscillator might take as long as one second to stabilize The user is advised to wait for at least one second before using Timer Counter2 after Power up or Wake up from Power down or Standby mode The contents of all Timer Counter2 Registers must be considered lost after a wake up from Power down or Standby mode due to unstable clock signal upon start up no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin e Description of wake up from Power save or Extended Standby mode when the timer is clocked asynchronously When the interrupt condition is met the wake up process is started on the following cycle of the timer clock that is the timer is always advanced by at least one before the processor can read the counter value After wake up the MCU is halted for four cycles it executes the interrupt routine and
126. when any of the OCR1x Registers are written The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value The ICR1 Register is not double buffered This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value there is a risk that the new ICR1 value written is lower than the current value of TCNT1 The result will then be that the counter will miss the Compare Match at the TOP value The counter will then have to count to the MAX value OxFFFF and wrap around start 90 ATlmega8 L memm X X X f megae8 L Phase Correct PWM Mode 2486R AVR 07 07 ing at Ox0000 before the Compare Match can occur The OCR1A Register however is double buffered This feature allows the OCR1A I O location to be written anytime When the OCR1A I O location is written the value written will be put into the OCR1A Buffer Register The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set Using the ICR1 Register for defining TOP works well when using fixed TOP values By using ICR1 the OCR1A Register is free to be used for generating a PWM output on OC1A However if the base PWM frequency is actively changed by changing the TOP value using the OCR1A as TOP is clearly a bet
127. 0 15 The wave form generated will have a maximum frequency of focia feik o 2 when OCR1A is set to zero 0x0000 This feature is similar to the OC1A toggle in CTC mode except the dou ble buffer feature of the Output Compare unit is enabled in the fast PWM mode The phase correct Pulse Width Modulation or phase correct PWM mode WGM13 0 1 2 3 10 or 11 provides a high resolution phase correct PWM waveform generation option The phase correct PWM mode is like the phase and frequency correct PWM mode based on a dual slope operation The counter counts repeatedly from BOTTOM 0x0000 to TOP and then from TOP to BOTTOM In non inverting Compare Output mode the Output Compare OC1x is cleared on the Compare Match between TCNT1 and OCR1x while upcounting and set on the Compare Match while downcounting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the symmetric feature of the dual slope PWM modes these modes are preferred for motor control applications The PWM resolution for the phase correct PWM mode can be fixed to 8 9 or 10 bit or defined by either ICR1 or OCR1A The minimum resolution allowed is 2 bit ICR1 or AMEL a AMEL OCR1A set to 0x0003 and the maximum resolution is 16 bit ICR1 or OCR1A set to MAX The PWM resolution in bits can be calculated by using the following equation R _ log TOP
128. 0 06 Changes from Rev 24860 10 04 to Rev 2486P 02 06 Changes from Rev 2486N 09 04 to Rev 24860 10 04 2486R AVR 07 07 Please note that the referring page numbers in this section are referred to this docu ment The referring revision in this section are referring to the document revision 1 Added text to Table 81 on page 218 Fixed typo in Peripheral Features on page 1 Updated Table 16 on page 42 Updated Table 75 on page 206 Removed redundancy and updated typo in Notes section of DC Characteris tics on page 242 Updated Timer Counter Oscillator on page 32 Updated Fast PWM Mode on page 89 Updated code example in USART Initialization on page 138 Updated Table 37 on page 98 Table 39 on page 99 Table 42 on page 117 Table 44 on page 118 and Table 98 on page 240 Updated Erratas on page 296 Added Resources on page 7 Updated External Clock on page 32 Updated Serial Peripheral Interface SPI on page 124 Updated Code Example in USART Initialization on page 138 Updated Note in Bit Rate Generator Unit on page 170 Updated Table 98 on page 240 Updated Note in Table 103 on page 248 Updated Erratas on page 296 Removed to instances of analog ground Replaced by ground Updated Table 7 on page 29 Table 15 on page 38 and Table 100 on page 244 Updated Calibrated Internal RC Oscillator on page 30 with the 1 MHz default value Table 89 on page 2
129. 00 before the Compare Match can occur For generating a waveform output in CTC mode the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode COM21 0 1 The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output The waveform generated will have a maximum fre quency of foce fox yo 2 when OCR2 is set to zero 0x00 The waveform frequency is defined by the following equation S foko OCn 2 N 1 0CRn The N variable represents the prescale factor 1 8 32 64 128 256 or 1024 As for the Normal mode of operation the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00 AMEL 111 Fast PWM Mode AMEL The fast Pulse Width Modulation or fast PWM mode WGM21 0 3 provides a high fre quency PWM waveform generation option The fast PWM differs from the other PWM option by its single slope operation The counter counts from BOTTOM to MAX then restarts from BOTTOM In non inverting Compare Output mode the Output Compare OC2 is cleared on the Compare Match between TCNT2 and OCR2 and set at BOT TOM In inverting Compare Output mode the output is set on Compare Match and cleared at BOTTOM Due to the single slope operation the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual slope operation This high frequency mak
130. 05 11 5 11 5 19 2 0 8 95 36 104 58 4 58 4 54 2 0 9 95 81 104 14 4 14 4 19 1 5 10 96 17 103 78 3 78 3 83 15 Table 54 Recommended Maximum Receiver Baud Rate Error for Double Speed Mode U2X 1 Di Max Total Recommended Max Data Parity Bit Reoy Rrast Error 96 Receiver Error 96 5 94 12 105 66 5 66 5 88 2 5 6 94 92 104 92 4 92 5 08 2 0 7 95 52 104 35 4 35 4 48 1 5 8 96 00 103 90 3 90 4 00 1 5 9 96 39 103 53 3 53 3 61 1 5 10 96 70 103 23 3 23 3 30 1 0 The recommendations of the maximum Receiver baud rate error was made under the assumption that the Receiver and Transmitter equally divides the maximum total error There are two possible sources for the Receivers Baud Rate error The Receiver s sys tem clock XTAL will always have some minor instability over the supply voltage range and the temperature range When using a crystal to generate the system clock this is rarely a problem but for a resonator the system clock may differ more than 2 depend ing of the resonators tolerance The second source for the error is more controllable The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted In this case an UBRR value that gives an acceptable low error can be used if possible ATmega8 L memm 2486R AVR 07 07 f 11 C025 Multi processor Communication
131. 120 100 80 lio uA 60 40 20 Figure 144 O Pin Pull up Resistor Current vs Input Voltage Voc 2 7V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 2 7V 90 80 85 C 25 C 70 40 C 60 z 50 2 40 30 20 10 0 0 0 5 1 1 5 2 2 5 3 Vor V ATmega8 L memm ATmega8 L Figure 145 Reset Pull up Resistor Current vs Reset Pin Voltage Vcc 5V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vec 5V Ingser UA Vreser V Figure 146 Reset Pull up Resistor Current vs Reset Pin Voltage Vcc 2 7V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vec 2 7V 45 40 C o 35 30 25 20 Ineser uA 15 10 VRESET V AMEL 263 2486R AVR 07 07 AMEL Pin Driver Strength Figure 147 I O Pin Source Current vs Output Voltage Voc 5V I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Vec 5V lon mA Figure 148 I O Pin Source Current vs Output Voltage Voc 2 7V 1 O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 2 7V lon mA Von V 264 ATmega8 L memm X f mega8 L 2486R AVR 07 07 Figure 149 O Pin Sink Current vs Output Voltage Voc 5V lo mA 1 O PIN SINK CURRENT vs OUTPUT VOLT
132. 2 1 1 0 64 1 1 1 128 The ADC Data Register ADCL and ADCH ADLAR 0 Bit 15 14 13 12 11 10 9 8 a a Aes acu ADCL 7 6 5 4 3 2 1 0 Read Write R R R R R R R R R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLAR 1 Bit 15 14 13 12 11 10 9 8 ADCS ADCH Paper Ano T BRLLBLLLLLLL 7 6 5 4 3 2 1 0 Read Write R R R R R R R R R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete the result is found in these two registers When ADCL is read the ADC Data Register is not updated until ADCH is read Conse quently if the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH The ADLAR bit in ADMUX and the MUXn bits in ADMUX affect the way the result is read from the registers If ADLAR is set the result is left adjusted If ADLAR is cleared default the result is right adjusted ADC9 0 ADC Conversion result These bits represent the result from the conversion as detailed in ADC Conversion Result on page 205 s ATmega8 L mmm 2486R AVR 07 07 Aimegae8 L Boot Loader Support Read While Write Self Programming Boot Loader Features Application and Boot Loader Flash Sections Application Section BLS Boot Loader Section Read While Write and No Read While Write Flash Sections 2486R AVR 07 07 The Boot Loade
133. 2 1 0 a TT9wus Tocmaus Domus aes Read Write R R R R R W R R R Initial Value 0 0 0 0 0 0 0 0 Bit 3 AS2 Asynchronous Timer Counter2 When AS2 is written to zero Timer Counter 2 is clocked from the I O clock clkyo When AS2 is written to one Timer Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 TOSC1 pin When the value of AS2 is changed the contents of TCNT2 OCR2 and TCCR2 might be corrupted AMEL 119 Asynchronous Operation of Timer Counter2 AMEL Bit 2 TCN2UB Timer Counter2 Update Busy When Timer Counter2 operates asynchronously and TCNT2 is written this bit becomes set When TCNT2 has been updated from the temporary storage register this bit is cleared by hardware A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value Bit 1 OCR2UB Output Compare Register2 Update Busy When Timer Counter2 operates asynchronously and OCR2 is written this bit becomes set When OCR2 has been updated from the temporary storage register this bit is cleared by hardware A logical zero in this bit indicates that OCR2 is ready to be updated with a new value e Bit 0 TCR2UB Timer Counter Control Register2 Update Busy When Timer Counter2 operates asynchronously and TCCR2 is written this bit becomes set When TCCR2 has been updated from the temporary storage register this bit is cleared by hardware A logical zero in this bit indicates that TCCR2 is read
134. 2 ENABLE PVOV SPI MSTR OUTPUT OC2 OC1B OC1A 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI SPI SLAVE INPUT SPI SS ICP1 INPUT AIO 60 ATlmega8 L memm 2486R AVR 07 07 A mega8 L Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 25 Table 25 Port C Pins Alternate Functions Port Pin Alternate Function PC6 RESET Reset pin PC5 ADC5 ADC Input Channel 5 SCL Two wire Serial Bus Clock Line ADCA ADC Input Channel 4 FE SDA Two wire Serial Bus Data Input Output Line PC3 ADC3 ADC Input Channel 3 PC2 ADC2 ADC Input Channel 2 PC1 ADC1 ADC Input Channel 1 PCO ADCO ADC Input Channel 0 The alternate pin configuration is as follows RESET Port C Bit 6 RESET Reset pin When the RSTDISBL Fuse is programmed this pin functions as a normal I O pin and the part will have to rely on Power on Reset and Brown out Reset as its reset sources When the RSTDISBL Fuse is unprogrammed the reset circuitry is connected to the pin and the pin can not be used as an I O pin If PC6 is used as a reset pin DDC6 PORTC6 and PINC6 will all read O SCL ADC5 Port C Bit 5 SCL Two wire Serial Interface Clock When the TWEN bit in TWCR is set one to enable the Two wire Serial Interface pin PC5 is disconnected from the port and becomes the Serial Clock I O pin for the Two wire Serial Interface In this mode there is a spike fi
135. 2 for a complete list of parameters Figure 21 I O Pin Equivalent Schematic A A T Pxn e Logic Coin EH See Figure General Digital I O for Details All registers and bit references in this section are written in general form A lower case x represents the numbering letter for the port and a lower case n represents the bit number However when using the register or bit defines in a program the precise form must be used i e PORTB3 for bit 3 in Port B here documented generally as PORTxn The physical I O Registers and bit locations are listed in Register Description for I O Ports on page 65 Three I O memory address locations are allocated for each port one each for the Data Register PORTx Data Direction Register DDRx and the Port Input Pins PINx The Port Input Pins I O location is read only while the Data Register and the Data Direction Register are read write In addition the Pull up Disable PUD bit in SFIOR disables the pull up function for all pins in all ports when set Using the I O port as General Digital I O is described in Ports as General Digital I O on page 52 Most port pins are multiplexed with alternate functions for the peripheral fea tures on the device How each alternate function interferes with the port pin is described in Alternate Port Functions on page 56 Refer to the individual module sections for a full description of the alternate functions
136. 25 and Table 90 on page 225 moved to new section Page Size on page 225 AMEL 297 Changes from Rev 2486M 12 03 to Rev 2486N 09 04 Changes from Rev 2486L 10 03 to Rev 2486M 12 03 Changes from Rev 2486K 08 03 to Rev 2486L 10 03 10 11 AIMEL Updated descripton for bit 4 in Store Program Memory Control Register SPMCR on page 213 Updated Ordering Information on page 292 Added note to MLF package in Pin Configurations on page 2 Updated Internal Voltage Reference Characteristics on page 42 Updated DC Characteristics on page 242 ADC4 and ADC5 support 10 bit accuracy Document updated to reflect this Updated features in Analog to Digital Converter on page 196 Updated ADC Characteristics on page 248 Removed reference to External RC Oscillator application note from Exter nal RC Oscillator on page 29 Updated Calibrated Internal RC Oscillator on page 30 Removed Preliminary and TBDs from the datasheet Renamed ICP to ICP1 in the datasheet Removed instructions CALL and JMP from the datasheet Updated t sr in Table 15 on page 38 Vg in Table 16 on page 42 Table 100 on page 244 and Table 102 on page 246 Replaced text XTAL1 and XTAL2 should be left unconnected NC after Table 9 in Calibrated Internal RC Oscillator on page 30 Added text regard ing XTAL1 XTAL2 and CKOPT Fuse in Timer Counter Oscillator on page 32 Updated Watchdog Timer code examples
137. 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWDO TWDR Read Write R W R W R W R W R W R W R W R W Initial Value 1 1 1 1 1 1 1 1 In Transmit mode TWDR contains the next byte to be transmitted In Receive mode the TWDR contains the last byte received It is writable while the TWI is not in the process of shifting a byte This occurs when the TWI Interrupt Flag TWINT is set by hardware Note that the Data Register cannot be initialized by the user before the first interrupt occurs The data in TWDR remains stable as long as TWINT is set While data is shifted out data on the bus is simultaneously shifted in TWDR always contains the last byte present on the bus except after a wake up from a sleep mode by the TWI interrupt In this case the contents of TWDR is undefined In the case of a lost bus arbitration no data is lost in the transition from Master to Slave Handling of the ACK bit is controlled automatically by the TWI logic the CPU cannot access the ACK bit directly Bits 7 0 TWD TWI Data Register These eight bits constitute the next data byte to be transmitted or the latest data byte received on the Two wire Serial Bus AMEL 173 TWI Slave Address Register TWAR Using the TWI AMEL Bit 7 6 5 4 3 2 1 0 TWA6 TWA5 TWA3 TWA2 TWAO TWGCE TWAR Read Write R W R W R W R W R W R W R W R W Initial Value 1 1 1 1 1 1 1 0 The TWAR should be loaded with the 7 bit Slave address in the seven most significant bits of TWAR
138. 6 55 LL 1 i Vcc v The system is single buffered in the transmit direction and double buffered in the receive direction This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed When receiving data however a received character must be read from the SPI Data Register before the next character has been completely shifted in Otherwise the first byte is lost In SPI Slave mode the control logic will sample the incoming signal of the SCK pin To ensure correct sampling of the clock signal the minimum low and high periods should be Low period longer than 2 CPU clock cycles High period longer than 2 CPU clock cycles When the SPI is enabled the data direction of the MOSI MISO SCK and SS pins is overridden according to Table 47 For more details on automatic port overrides refer to Alternate Port Functions on page 56 AMEL 125 126 AMEL Table 47 SPI Pin Overrides Pin Direction Master SPI Direction Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note 1 See Port B Pins Alternate Functions on page 58 for a detailed description of how to define the direction of the user defined SPI pins The following code examples show how to initialize the SPI as a Master and how to per form a simple transmission DDR SPI in the examples must be replaced by the actual Da
139. 7 Transmission Modes AMEL The TWI can operate in one of four major modes These are named Master Transmitter MT Master Receiver MR Slave Transmitter ST and Slave Receiver SR Several of these modes can be used in the same application As an example the TWI can use MT mode to write data into a TWI EEPROM MR mode to read the data back from the EEPROM If other masters are present in the system some of these might transmit data to the TWI and then SR mode would be used It is the application software that decides which modes are legal The following sections describe each of these modes Possible status codes are described along with figures detailing data transmission in each of the modes These fig ures contain the following abbreviations S START condition Rs REPEATED START condition R Read bit high level at SDA W Write bit low level at SDA A Acknowledge bit low level at SDA A Not acknowledge bit high level at SDA Data 8 bit data byte P STOP condition SLA Slave Address In Figure 79 to Figure 85 circles are used to indicate that the TWINT Flag is set The numbers in the circles show the status code held in TWSR with the prescaler bits masked to zero At these points actions must be taken by the application to continue or complete the TWI transfer The TWI transfer is suspended until the TWINT Flag is cleared by software When the TWINT Flag is set the status code in TWSR is used to determine
140. 7 0 pins to replace the negative input to the Analog Comparator The ADC multiplexer is used to select this input and consequently the ADC must be switched off to utilize this feature If the Analog Comparator Multi plexer Enable bit ACME in SFIOR is set and the ADC is switched off ADEN in ADCSRA is zero MUX2 0 in ADMUX select the input pin to replace the negative input to the Analog Comparator as shown in Table 72 If ACME is cleared or ADEN is set AIN1 is applied to the negative input to the Analog Comparator Table 72 Analog Comparator Multiplexed Input ACME ADEN MUX2 0 Analog Comparator Negative Input 0 X XXX AIN1 1 1 XXX AIN1 1 0 000 ADCO 1 0 001 ADC1 1 0 010 ADC2 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 Note 1 ADC7 6 are only available in TQFP and QFN MLF Package AMEL 195 Analog to Digital Converter Features AMEL 10 bit Resolution 0 5 LSB Integral Non linearity 2 LSB Absolute Accuracy 13 260 ps Conversion Time Up to 15 kSPS at Maximum Resolution 6 Multiplexed Single Ended Input Channels 2 Additional Multiplexed Single Ended Input Channels TQFP and QFN MLF Package only Optional Left Adjustment for ADC Result Readout 0 Vec ADC Input Voltage Range Selectable 2 56V ADC Reference Voltage Free Running or Single Conversion Mode Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler The ATmega 8 feat
141. 7 SPI Block Diagram XTAL MSB parr SuFTREGSTER READ DATA BUFFER DIVIDER 2 4 8 16 32 64 1 28 SPI CLOCK MASTER PIN CONTROL LOGIC SELECT 4MSTR SPE SPI CONTROL EN uw Q wl ul 2 El a oe a 9 g a a O 9 a ao af a o sz 6 6 8 2 O Of o 0 SPI STATUS REGISTER 5s v E SPI INTERRUPT INTERNAL REQUEST DATA BUS Note 1 Refer to Pin Configurations on page 2 and Table 22 on page 58 for SPI pin placement The interconnection between Master and Slave CPUs with SPI is shown in Figure 58 The system consists of two Shift Registers and a Master clock generator The SPI Mas ter initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave Master and Slave prepare the data to be sent in their respective Shift Registers and the Master generates the required clock pulses on the SCK line to inter change data Data is always shifted from Master to Slave on the Master Out Slave In MOSI line and from Slave to Master on the Master In Slave Out MISO line After each data packet the Master will synchronize the Slave by pulling high the Slave Select SS line 124 ATmega8 L mmm X Al megae8 L 2486R AVR 07 07 When configured as a Master the SPI interface has no automatic control of the SS line This must be handled by user software before communication can start
142. 8 1 PB4 MISO AINO PD6 12 17 O PB3 MOSI OC2 AIN1 PD7 J 13 16 L1 PB2 SS OC1B ICP1 PBOL 14 15 L1 PB1 OC1A TQFP Top View TT oa COD concu FNAN eaooo ocoo oo zx xjuaaad E LEcCEsz xss CN Oc 010 wWw QOoOOooooo caaaaanraa ECLCLCLELCLI M T O O Oo r Q n 0 6 Q QW A INT1 PD3 Q 1 Q Qa PC1 ADC1 XCK TO PD4 LJ 2 23 1 PCO ADCO GND 43 22 L1 ADC7 vec 04 21 L1 GND GND 15 20 O AREF vec 416 19 O ADC6 XTAL1 TOSC1 PB6 7 18 O AVCC XTAL2 TOSC2 PB7 C 8 O O PB5 SCK O v o x 0 o Orrrrrre wonoranrt Qaoamtumunmumtmnnmun anuonouononun Co cznwo ezzr OD czZzz 5 n ZLLESLE o E E MLF Top View TT oa Fetes anoU DFAA eoaolmo oooo xw AAAA IPTEN coon A Qandaooooo canananano LLLLDLD OLD LL M T O O oc r on ANDANANAA INT1 PD3 1 Q P 24 0 PC1 ADC1 XCK TO PD4 12 i 23 1 PCO ADCO GND 3 221 ADC7 vCcC 4 21 0 GND GND 5 20 1 AREF vccrje 19 ADC6 XTAL1 TOSC1 PB6 7 A 18 0 AVCC XTAL2 TOSC2 PB7 8 i 17 0 PB5 SCK O v o x od Orrrrrrr O o U O U O UO O NOTE a amp 5 2 m a 8 a The large center pad underneath the MLF aami i i m i packages is made of metal and internally Forrann o connected to GND It should be soldered F2Z2Z240rr OQ or glued to the PCB to ensure good zee 8 8 oz mechanical stability If the center pad is GQ left unconneted the package might a S loosen from the PCB 2486R AVR 07 07 AT 11
143. AGE Vec 5V Va V Figure 150 O Pin Sink Current vs Output Voltage Vec 2 7V lo mA I O PIN SINK CURRENT vs OUTPUT VOLTAGE Vcc 2 7V Va V AMEL 265 AMEL Figure 151 Reset Pin as I O Pin Source Current vs Output Voltage Vec 5V RESET PIN AS I O SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 5V Current mA Vou V Figure 152 Reset Pin as I O Pin Source Current vs Output Voltage Vcc 2 7V RESET PIN AS I O SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 2 7V Von V 26 ATmega8 L mmm 2486R AVR 07 07 A mega8 L Figure 153 Reset Pin as I O Pin Sink Current vs Output Voltage Vcc 5V RESET PIN AS I O SINK CURRENT vs OUTPUT VOLTAGE Vcc 5V 14 40 C 12 25 C 10 c 85 C fas I e 5 6 o 4 2 0 0 0 5 1 1 5 2 2 5 Vo V Figure 154 Reset Pin as I O Pin Sink Current vs Output Voltage Vcc 2 7V RESET PIN AS I O SINK CURRENT vs OUTPUT VOLTAGE Vcc 2 7V Current mA Vo V AMEL 267 2486R AVR 07 07 AMEL Pin Thresholds and Figure 155 O Pin Input Threshold Voltage vs Veg Vi I O Pin Read as 1 Hysteresis I O PIN INPUT THRESHOLD VOLTAGE vs Vcc VIH IO PIN READ AS 1 Threshold V
144. ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life 2007 Atmel Corporation All rights reserved Atmel logo and combinations thereof and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others 2486R AVR 07 07
145. AVR 07 07 AT 11 C025 Power Management and Sleep Modes MCU Control Register MCUCR 2486R AVR 07 07 Sleep modes enable the application to shut down unused modules in the MCU thereby saving power The AVR provides various sleep modes allowing the user to tailor the power consumption to the application s requirements To enter any of the five sleep modes the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed The SM2 SM1 and SMO bits in the MCUCR Register select which sleep mode Idle ADC Noise Reduction Power down Power save or Standby will be activated by the SLEEP instruction See Table 13 for a summary If an enabled interrupt occurs while the MCU is in a sleep mode the MCU wakes up The MCU is then halted for four cycles in addition to the start up time it exe cutes the interrupt routine and resumes execution from the instruction following SLEEP The contents of the Register File and SRAM are unaltered when the device wakes up from sleep If a reset occurs during sleep mode the MCU wakes up and executes from the Reset Vector Note that the Extended Standby mode present in many other AVR MCUs has been removed in the ATmega8 as the TOSC and XTAL inputs share the same physical pins Figure 10 on page 25 presents the different clock systems in the ATmega8 and their distribution The figure is helpful in selecting an appropriate sleep mode The MCU Control Re
146. Bits The value of these bits selects which analog inputs are connected to the ADC See Table 75 for details If these bits are changed during a conversion the change will not go in effect until this conversion is complete ADIF in ADCSRA is set Table 75 Input Channel Selections MUX3 0 Single Ended Input 0000 ADCO 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 1000 1001 1010 1011 1100 1101 1110 1 30V Vag 1111 OV GND ATmega8 L m E 2486R AVR 07 07 m Amegae8 L ADC Control and Status Register A ADCSRA 2486R AVR 07 07 Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADFR ADF ADIE ADPS2 ADPSi ADPSO ADCSRA Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 7 ADEN ADC Enable Writing this bit to one enables the ADC By writing it to zero the ADC is turned off Turn ing the ADC off while a conversion is in progress will terminate this conversion e Bit 6 ADSC ADC Start Conversion In Single Conversion mode write this bit to one to start each conversion In Free Run ning mode write this bit to one to start the first conversion The first conversion after ADSC has been written after the ADC has been enabled or if ADSC is written at the same time as the ADC is enabled will take 25 ADC clock cycles instead of the normal 13 This first co
147. Bits is as follows refer to Programming the Flash on page 229 for details on Command and Data loading 1 A Load Command 0010 0000 2 C Load Data Low byte Bit n 0 programs the Lock bit 3 Give WR a negative pulse and wait for RDY BSY to go high The Lock Bits can only be cleared by executing Chip Erase Reading the Fuse and Lock The algorithm for reading the Fuse and Lock Bits is as follows refer to Programming Bits the Flash on page 229 for details on Command loading 1 A Load Command 0000 0100 2 Set OE to 0 BS2 to 0 and BS1 to 0 The status of the Fuse Low bits can now be read at DATA 0 means programmed 3 Set OE to 0 BS2 to 1 and BS1 to 1 The status of the Fuse High bits can now be read at DATA 0 means programmed 4 Set OE to 0 BS2 to 0 and BS1 to 1 The status of the Lock Bits can now be read at DATA 0 means programmed 5 Set OE to 1 Figure 108 Mapping Between BS1 BS2 and the Fuse and Lock Bits During Read Fuse low byte P 0 DATA Fuse Fuse high byte byte BS2 AMEL 233 2486R AVR 07 07 AMEL Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows refer to Programming the Flash on page 229 for details on Command and Address loading 1 A Load Command 0000 1000 2 B Load Address Low byte 0x00 0x02 3 Set OE to 0 and BS1 to 0 The
148. Boot Lock bit11 unprogrammed An accidental write to the Boot Loader itself can corrupt the entire Boot Loader and further software updates might be impossible If it is not necessary to change the Boot Loader software itself it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes During Self Programming either page erase or page write the RWW section is always blocked for reading The user software itself must prevent that this section is addressed during the self programming operation The RWWSB in the SPMCR will be set as long as the RWW section is busy During Self Programming the Interrupt Vector table should be moved to the BLS as described in Interrupts on page 46 or the interrupts must be disabled Before addressing the RWW section after the programming is completed the user software must clear the RWWSB by writing the RWWSRE See Simple Assembly Code Example for a Boot Loader on page 219 for an example 26 ATmega8 L mmm 2486R AVR 07 07 M1 AT 11 C025 LL Setting the Boot Loader Lock Bits by SPM EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock Bits from Software 2486R AVR 07 07 To set the Boot Loader Lock Bits write the desired data to RO write X0001001 to SPMCR and execute SPM within four clock cycles after writing SPMCR The only accessible Lock Bits are the Boot Lock Bits that may prevent the Application
149. C025 Overview The ATmega8 is a low power CMOS 8 bit microcontroller based on the AVR RISC architecture By executing powerful instructions in a single clock cycle the ATmega8 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed Block Diagram Figure 1 Block Diagram XTAL1 A 1 RESET PCO PC6 PBO PB7 a vcc i r s H9 ED E t HR eel PN ER M Pn E XTAL2 i v PORTC DRIVERS BUFFERS PORTB DRIVERS BUFFERS ae PORTC DIGITAL INTERFACE PORTB DIGITAL INTERFACE i 3 db MUX amp ADC H gt ADC gt INTERFACE fm TWI AGND AREF UTR TIMERS PROGRAM e STACK i counters OSCILLATOR COUNTER POINTER gt i PROGRAM INTERNAL FLASH SRAM gt OSCILLATOR Y Y INSTRUCTION GENERAL WATCHDOG REGISTER PURPOSE TIMER OSCILLATOR REGISTERS x a x i r4 INSTRUCTION MCU CTRL A DECODER x amp TIMING H z v i CONTROL INTERRUPT LINES ALU WIES UNIT id STATUS AVR CPU REGISTER M 77 EEPROM PROGRAMMING y SPI M h M USART py COMP INTERFACE gt EX PORTD
150. C1x state before the output is enabled Note that some COM1x1 0 bit settings are reserved for certain modes of operation See 16 bit Timer Counter Register Description on page 97 The COM1x1 0 bits have no effect on the Input Capture unit AMEL Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match CTC Mode AMEL The waveform generator uses the COM1x1 0 bits differently in normal CTC and PWM modes For all modes setting the COM1x1 0 0 tells the waveform generator that no action on the OC1x Register is to be performed on the next Compare Match For com pare output actions in the non PWM modes refer to Table 36 on page 97 For fast PWM mode refer to Table 37 on page 98 and for phase correct and phase and frequency cor rect PWM refer to Table 38 on page 98 A change of the COM1x1 0 bits state will have effect at the first Compare Match after the bits are written For non PWM modes the action can be forced to have immediate effect by using the FOC1x strobe bits The mode of operation i e the behavior of the Timer Counter and the Output Compare pins is defined by the combination of the Waveform Generation mode WGM13 0 and Compare Output mode COM1x1 0 bits The Compare Output mode bits do not affect the counting sequence while the Waveform Generation mode bits do The COM1x1 0 bits control whether the PWM output generated should be inverted or not inverted or
151. CNT1L r16 Read TCNT1 into r17 r16 in r16 TCNT1L in r17 TCNT1H C Code Example unsigned int i Set TCNT1 to OxO01FF TCNT1 Ox1FF Read TCNT1 into i i TCNT1 Note 1 See About Code Examples on page 8 The assembly code example returns the TCNT1 value in the r17 r16 Register pair It is important to notice that accessing 16 bit registers are atomic operations If an inter rupt occurs between the two instructions accessing the 16 bit register and the interrupt code updates the temporary register by accessing the same or any other of the 16 bit Timer Registers then the result of the access outside the interrupt will be corrupted Therefore when both the main code and the interrupt code update the temporary regis ter the main code must disable the interrupts during the 16 bit access AMEL r AMEL The following code examples show how to do an atomic read of the TCNT1 Register contents Reading any of the OCR1A B or ICR1 Registers can be done by using the same principle Assembly Code Example TIM16_ReadTCNT1 Save Global Interrupt Flag in r18 SREG Disable interrupts cli Read TCNT1 into r17 r16 in r16 TCNT1L in r17 TCNT1H Restore Global Interrupt Flag out SREG r18 ret C Code Example unsigned int TIM16 ReadTCNT1 void unsigned char sreg unsigned int i Save Global Interrupt Flag sreg SREG Disable interrupts
152. Calibrated RC Oscillator Operating Modes CKSEL3 0 Nominal Frequency MHz 0001 1 0 0010 2 0 0011 4 0 0100 8 0 Note 1 The device is shipped with this option selected When this Oscillator is selected start up times are determined by the SUT Fuses as shown in Table 10 PB6 XTAL1 TOSC1 and PB7 XTAL2 TOSC2 can be used as either general I O pins or Timer Oscillator pins Table 10 Start up Times for the Internal Calibrated RC Oscillator Clock Selection Start up Time from Additional Delay Power down and from Reset SUT1 0 Power save Vec 5 0V Recommended Usage 00 6 CK BOD enabled 01 6 CK 4 1 ms Fast rising power 100 6 CK 65 ms Slowly rising power 11 Reserved Note 1 The device is shipped with this option selected 30 ATmega8 L memm 2486R AVR 07 07 AT 11 C025 Oscillator Calibration Register OSCCAL 2486R AVR 07 07 Bit 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CALO OSCCAL Read Write R W R W R W R W R W R W R W R W Initial Value Device Specific Calibration Value Bits 7 0 CAL7 0 Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove pro cess variations from the Oscillator frequency During Reset the 1 MHz calibration value which is located in the signature row High byte address 0x00 is automatically loaded into the OSCCAL Register If the internal RC i
153. Capture Pin The PBO pin can act as an Input Capture Pin for Timer Counter1 Table 23 and Table 24 relate the alternate functions of Port B to the overriding signals shown in Figure 25 on page 56 SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE AMEL so 2486R AVR 07 07 AMEL Table 23 Overriding Signals for Alternate Functions in PB7 PB4 Signal PB7 XTAL2 PB6 XTAL1 Name TOSC2 TOSC1 PB5 SCK PB4 MISO PUOE EXT INTRC INTRC AS2 SPE MSTR SPE MSTR AS2 PUO 0 0 PORTB5 PUD PORTB4 PUD DDOE EXT e INTRC INTRC AS2 SPE MSTR SPE MSTR AS2 DDOV 0 0 0 0 PVOE 0 0 SPE MSTR SPE MSTR PVOV 0 0 SCK OUTPUT SPI SLAVE OUTPUT DIEOE EXT INTRC INTRC AS2 0 0 AS2 DIEOV 0 0 0 0 DI SCK INPUT SPI MSTR INPUT AIO Oscillator Output Oscillator Clock Input Notes 1 INTRC means that the internal RC Oscillator is selected by the CKSEL Fuse CKSEL Fuse Table 24 Overriding Signals for Alternate Functions in PB3 PBO 2 EXT means that the external RC Oscillator or an external clock is selected by the Nine PB3 MOSI OC2 PB2 SS OC1B PB1 OC1A PBO ICP1 PUOE SPE MSTR SPE MSTR 0 0 PUO PORTB3 PUD PORTB2 PUD 0 0 DDOE SPE MSTR SPE MSTR 0 0 DDOV 0 0 0 0 PVOE SPE MSTR OC1B ENABLE OC1A ENABLE 0 OC
154. Compare A Match Flag This flag is set in the timer clock cycle after the counter TCNT1 value matches the Out put Compare Register A OCR1A Note that a Forced Output Compare FOC1A strobe will not set the OCF1A Flag OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed Alternatively OCF1A can be cleared by writing a logic one to its bit location Bit 3 OCF1B Timer Counter1 Output Compare B Match Flag This flag is set in the timer clock cycle after the counter TCNT1 value matches the Out put Compare Register B OCR1B Note that a Forced Output Compare FOC1B strobe will not set the OCF1B Flag OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed Alternatively OCF1B can be cleared by writing a logic one to its bit location Bit 2 TOV1 Timer Counter1 Overflow Flag The setting of this flag is dependent of the WGM13 0 bits setting In normal and CTC modes the TOV1 Flag is set when the timer overflows Refer to Table 39 on page 99 for the TOV1 Flag behavior when using another WGM13 0 bit setting TOV1 is automatically cleared when the Timer Counter1 Overflow Interrupt Vector is executed Alternatively TOV1 can be cleared by writing a logic one to its bit location AMEL 103 AMEL 8 bit Timer Counter2 Timer Counter2 is a general purpose single channel 8 bit Timer Counter module The with PWM and main features are Single Channe
155. D Figure 13 External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 12 Table 12 Start up Times for the External Clock Selection Start up Time from Additional Delay Power down and from Reset SUT1 0 Power save Vec 5 0V Recommended Usage 00 6 CK BOD enabled 01 6 CK 4 1 ms Fast rising power 10 6 CK 65 ms Slowly rising power 11 Reserved When applying an external clock it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU A variation in frequency of more than 2 from one clock cycle to the next can lead to unpredictable behavior It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency For AVR microcontrollers with Timer Counter Oscillator pins TOSC1 and TOSC2 the crystal is connected directly between the pins By programming the CKOPT Fuse the user can enable internal capacitors on XTAL1 and XTAL2 thereby removing the need for external capacitors The Oscillator is optimized for use with a 32 768 kHz watch crys tal Applying an external clock source to TOSC1 is not recommended Note The Timer Counter Oscillator uses the same type of crystal oscillator as Low Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF 32 ATlmega8 L mmm 2486R
156. D in the Z register is used to address the data in the temporary page buffer The temporary buffer will auto erase after a page write operation or by writ ing the RWWSRE bit in SPMCR It is also erased after a System Reset Note that it is not possible to write more than one time to each address without erasing the temporary buffer Note If the EEPROM is written in the middle of an SPM page Load operation all data loaded will be lost To execute page write set up the address in the Z pointer write X0000101 to SPMCR and execute SPM within four clock cycles after writing SPMCR The data in R1 and RO is ignored The page address must be written to PCPAGE Other bits in the Z pointer must be written to zero during this operation e Page Write to the RWW section The NRWW section can be read during the page write e Page Write to the NRWW section The CPU is halted during the operation If the SPM interrupt is enabled the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCR is cleared This means that the interrupt can be used instead of polling the SPMCR Register in software When using the SPM interrupt the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading How to move the interrupts is described in Interrupts on page 46 Special care must be taken if the user allows the Boot Loader section to be updated by leaving
157. DIGITAL INTERFACE i PORTD DRIVERS BUFFERS ETE ET PDO PD7 2486R AVR 07 07 AMEL The AVR core combines a rich instruction set with 32 general purpose working registers All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers The ATmega8 provides the following features 8K bytes of In System Programmable Flash with Read While Write capabilities 512 bytes of EEPROM 1K byte of SRAM 23 general purpose I O lines 32 general purpose working registers three flexible Timer Counters with compare modes internal and external interrupts a serial program mable USART a byte oriented Two wire Serial Interface a 6 channel ADC eight channels in TQFP and QFN MLF packages with 10 bit accuracy a programmable Watchdog Timer with Internal Oscillator an SPI serial port and five software selectable power saving modes The Idle mode stops the CPU while allowing the SRAM Timer Counters SPI port and interrupt system to continue functioning The Power down mode saves the register contents but freezes the Oscillator disabling all other chip functions until the next Interrupt or Hardware Reset In Power save mode the asynchronous
158. EI set global interrupt enable SLEEP enter sleep waiting for interrupt note will enter sleep before any pending interrupt s The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum After four clock cycles the Program Vector address for the actual interrupt handling routine is executed During this 4 clock cycle period the Program Counter is pushed onto the Stack The Vector is normally a jump to the interrupt routine and this jump takes three clock cycles If an interrupt occurs during execution of a multi cycle instruction this instruction is completed before the interrupt is served If an interrupt occurs when the MCU is in sleep mode the interrupt execution response time is increased by four clock cycles This increase comes in addition to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these four clock cycles the Program Counter 2 bytes is popped back from the Stack the Stack Pointer is incremented by 2 and the I bit in SREG is set 16 ATmega8 L m E 2486R AVR 07 07 Aimegae8 L AVR ATmega8 Memories In System Reprogrammable Flash Program Memory 2486R AVR 07 07 This section describes the different memories in the ATmega8 The AVR architecture has two main memory spaces the Data memory and the Program Memory space In additi
159. EL Bit 3 WDE Watchdog Enable When the WDE is written to logic one the Watchdog Timer is enabled and if the WDE is written to logic zero the Watchdog Timer function is disabled WDE can only be cleared if the WDCE bit has logic level one To disable an enabled Watchdog Timer the follow ing procedure must be followed 1 Inthe same operation write a logic one to WDCE and WDE A logic one must be written to WDE even though it is set to one before the disable operation starts 2 Within the next four clock cycles write a logic O to WDE This disables the Watchdog e Bits 2 0 WDP2 WDP1 WDPO Watchdog Timer Prescaler 2 1 and 0 The WDP2 WDP1 and WDPO bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled The different prescaling values and their corresponding Timeout Periods are shown in Table 17 Table 17 Watchdog Timer Prescale Select Number of WDT Typical Time out Typical Time out WDP2 WDP1 WDPO Oscillator Cycles at Vec 3 0V at Voc 5 0V 0 0 0 16K 16 384 17 1 ms 16 3 ms 0 0 1 32K 32 768 34 3 ms 32 5 ms 0 1 0 64K 65 536 68 5 ms 65 ms 0 1 1 128K 131 072 0 14 s 0 13s 1 0 0 256K 262 144 0 27 S 0 26 s 1 0 1 512K 524 288 0 55s 0 52 s 1 1 0 1 024K 1 048 576 1 1s 1 0s 1 1 1 2 048K 2 097 152 22s 24s The following code example shows one assembly and one C function for turning off the WDT The example assumes that interrupts
160. Event 7 0x006 TIMER1 COMPA Timer Counter1 Compare Match A 8 0x007 TIMER1 COMPB Timer Counter1 Compare Match B 9 0x008 TIMER1 OVF Timer Counter1 Overflow 10 0x009 TIMERO OVF Timer CounterO Overflow 11 0x00A SPI STC Serial Transfer Complete 12 0x00B USART RXC USART Rx Complete 13 0x00C USART UDRE USART Data Register Empty 14 0x00D USART TXC USART Tx Complete 15 Ox00E ADC ADC Conversion Complete 16 OxOOF EE RDY EEPROM Ready 17 0x010 ANA_COMP Analog Comparator 18 0x011 TWI Two wire Serial Interface 19 0x012 SPM_RDY Store Program Memory Ready Notes 1 When the BOOTRST Fuse is programmed the device will jump to the Boot Loader address at reset see Boot Loader Support Read While Write Self Programming on page 209 2 When the IVSEL bit in GICR is set Interrupt Vectors will be moved to the start of the boot Flash section The address of each Interrupt Vector will then be the address in this table added to the start address of the boot Flash section Table 19 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings If the program never enables an interrupt source the Interrupt Vectors are not used and regular program code can be placed at these loca tions This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa 46 ATmegae8 L EEE __ 2486R AVR 07 07 AT 11 C025 Table 19
161. Features High performance Low power AVR 8 bit Microcontroller Advanced RISC Architecture 130 Powerful Instructions Most Single clock Cycle Execution 82 x 8 General Purpose Working Registers Fully Static Operation ey Up to 16 MIPS Throughput at 16 MHz On chip 2 cycle Multiplier High Endurance Non volatile Memory segments 8K Bytes of In System Self programmable Flash program memory amp 512 Bytes EEPROM 8 bit AVR 1K Byte Internal SRAM Write Erase Cycles 10 000 Flash 100 000 EEPROM I Data retention 20 years at 85 C 100 years at 25 C 2 with 8K Bytes Optional Boot Code Section with Independent Lock Bits In System Programming by On chip Boot Program In System True Read While Write Operation Programming Lock for Software Security P rog ram mable Peripheral Features Two 8 bit Timer Counters with Separate Prescaler one Compare Mode Flash One 16 bit Timer Counter with Separate Prescaler Compare Mode and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels ATmega8 8 channel ADC in TQFP and QFN MLF package Eight Channels 10 bit Accuracy ATmega8 L 6 channel ADC in PDIP package Six Channels 10 bit Accuracy Byte oriented Two wire Serial Interface Programmable Serial USART Master Slave SPI Serial Interface Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog Comparator Special Microcontroll
162. ILLATOR FREQUENCY vs OSCCAL VALUE Frc MHz a 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 176 Calibrated 2 MHz RC Oscillator Frequency vs Temperature CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 2 1 5 5V 2 05 4 0V 2 m I 195 g Ww 2 7V 1 9 1 85 1 8 60 40 20 0 20 40 60 80 100 Temperature C SESEEEooo oM i 2486R AVR 07 07 A 1 C025 Figure 177 Calibrated 2 MHz RC Oscillator Frequency vs Voc CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs Vcc 2 2 2 1 40 C 25 C PEE KS 85 C o 1 9 1 8 1 7 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 178 Calibrated 2 MHz RC Oscillator Frequency vs Osccal Value CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 3 8 3 3 2 8 2 3 Frc MHz 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE AMEL 279 2486R AVR 07 07 AMEL Figure 179 Calibrated 1 MHz RC Oscillator Frequency vs Temperature CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 1 04 5 5V 1 02 4 0V 1 v 0 98 Ea Q 2 7V uw 0 96 0 94 0 92 0 9 60 40 20 0 20 40 60 80 100 Temperature C Figure 180 Calibrated 1 MHz RC O
163. IVCE bit will disable interrupts as explained in the IVSEL description above See Code Example below Assembly Code Example Move interrupts Enable change of Interrupt Vectors ldi r16 1 lt lt IVCE out GICR r16 Move interrupts to boot Flash section ldi r16 1 lt lt IVSEL out GICR r16 ret C Code Example void Move_interrupts void Enable change of Interrupt Vectors GICR 1 lt lt IVCE Move interrupts to boot Flash section GICR 1 lt lt IVSEL ATmega8 L m I 2486R AVR 07 07 AT 11 C025 l O Ports Introduction 2486R AVR 07 07 All AVR ports have true Read Modify Write functionality when used as general digital I O ports This means that the direction of one port pin can be changed without uninten tionally changing the direction of any other pin with the SBI and CBI instructions The same applies when changing drive value if configured as output or enabling disabling of pull up resistors if configured as input Each output buffer has symmetrical drive characteristics with both high sink and source capability The pin driver is strong enough to drive LED displays directly All port pins have individually selectable pull up resistors with a supply voltage invariant resistance All I O pins have protection diodes to both Vcc and Ground as indicated in Figure 21 Refer to Electrical Characteristics on page 24
164. Initial Value 0 0 0 0 0 0 0 0 e Bit 7 SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit in SREG is set Bit 6 SPE SPI Enable When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations e Bit 5 DORD Data Order When the DORD bit is written to one the LSB of the data word is transmitted first When the DORD bit is written to zero the MSB of the data word is transmitted first e Bit4 MSTR Master Slave Select This bit selects Master SPI mode when written to one and Slave SPI mode when written logic zero If SS is configured as an input and is driven low while MSTR is set MSTR will AMEL 129 130 AMEL be cleared and SPIF in SPSR will become set The user will then have to set MSTR to re enable SPI Master mode Bit 3 CPOL Clock Polarity When this bit is written to one SCK is high when idle When CPOL is written to zero SCK is low when idle Refer to Figure 59 and Figure 60 for an example The CPOL func tionality is summarized below Table 48 CPOL Functionality CPOL Leading Edge Trailing Edge 0 Rising Falling 1 Falling Rising Bit 2 CPHA Clock Phase The settings of the clock phase bit CPHA determine if data is sampled on the leading first or trailing last edge of SCK Refer to Figure 59 and Figure 60 for an ex
165. Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section LPM executing from the Boot Loader section is not allowed to read from the Application section If Interrupt Vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section BLB1 Mode BLB12 BLB11 222 ATmega8 L memm 2486R AVR 07 07 A 11 C023 Table 86 Lock Bit Protection Modes Continued 1 Memory Lock Bits Protection Type No restrictions for SPM or LPM accessing the Boot Loader section 1 0 SPM is not allowed to write to the Boot Loader section SPM is not allowed to write to the Boot Loader section and LPM executing from the Application section is not 0 allowed to read from the Boot Loader section If Interrupt Vectors are placed in the Application section interrupts are disabled while executing from the Boot Loader section LPM executing from the Application section is not allowed to read from the Boot Loader section If Interrupt Vectors are placed in the Application section interrupts are disabled while executing from the Boot Loader section Notes 1 Program the Fuse Bits before programming the Lock Bits 2 1 means unprogrammed 0 means programmed Fuse Bits The ATmega8 has two fuse bytes Table 87 and Table 88 describe briefly the func
166. L UP OVERRIDE ENABLE PUD PULLUP DISABLE PUOVxn Pxn PULL UP OVERRIDE VALUE WDx WRITE DDRx DDOExn Pxn DATA DIRECTION OVERRIDE ENABLE RDx READ DDRx DDOVxn Pxn DATA DIRECTION OVERRIDE VALUE RRx READ PORTx REGISTER PVOExn Pxn PORT VALUE OVERRIDE ENABLE WPx WRITE PORTx PVOVxn Pxn PORT VALUE OVERRIDE VALUE RPx READ PORTx PIN DIEOExn Pxn DIGITAL INPUT ENABLE OVERRIDE ENABLE ck VO CLOCK DIEOVxn Pxn DIGITAL INPUT ENABLE OVERRIDE VALUE Dixn DIGITAL INPUT PIN n ON PORTx SLEEP SLEEP CONTROL AlOxn ANALOG INPUT OUTPUT PIN n ON PORTx Note 1 WPx WDx RRx RPx and RDx are common to all pins within the same port clkyo SLEEP and PUD are common to all ports All other signals are unique for each pin 56 ATlmega8 L memm 2486R AVR 07 07 A 11 C025 Table 21 summarizes the function of the overriding signals The pin and port indexes from Figure 25 are not shown in the succeeding tables The overriding signals are gen erated internally in the modules having the alternate function Table 21 Generic Description of Overriding Signals for Alternate Functions Signal Name PUOE Full Name Pull up Override Enable Description If this signal is set the pull up enable is controlled by the PUOV signal If this signal is cleared the pull up is enabled when DDxn PORTxn PUD 0b010 PUOV Pull up Override Value If PUOE is set the pull up is enabled disabled when PUOV is set cleared regardl
167. LA W A Data A STOP Indicates 2 TWINT set SES 6 TWINT set TWINT set Status code indicates Status code indicates data sent ACK received Status code indicates START condition sent SLA W sent AGK received TWI Hardware Action 1 The first step in a TWI transmission is to transmit a START condition This is done by writing a specific value into TWCR instructing the TWI hardware to transmit a START condition Which value to write is described later on However it is important that the TWINT bit is set in the value written Writing a one to TWINT clears the flag The TWI will not start any operation as long as the TWINT bit in TWCR is set Immediately after the application has cleared TWINT the TWI will initiate transmission of the START condition 2 When the START condition has been transmitted the TWINT Flag in TWCR is set and TWSR is updated with a status code indicating that the START condition has successfully been sent 3 The application software should now examine the value of TWSR to make sure that the START condition was successfully transmitted If TWSR indicates other wise the application software might take some special action like calling an error routine Assuming that the status code is as expected the application must load SLA W into TWDR Remember that TWDR is used both for address and data After TWDR has been loaded with the desired SLA W a specific value must be written to
168. NT bit should be cleared by writing it to one to continue the transfer This is accomplished by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 0 0 X 1 0 X When SLA R have been transmitted and an acknowledgement bit has been received TWINT is set again and a number of status codes in TWSR are possible Possible sta tus codes in Master mode are 0x38 0x40 or 0x48 The appropriate action to be taken for each of these status codes is detailed in Table 67 Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware This scheme is repeated until the last byte has been received After the last byte has been received the MR should inform the ST by sending a NACK after the last received data byte The transfer is ended by generating a STOP condition or a repeated START condition A STOP condition is generated by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 0 1 X 1 0 X A REPEATED START condition is generated by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 1 0 X 1 0 X 182 ATmegae8 L EEyxyeeeeee 2486R AVR 07 07 f mmega8 L After a repeated START condition state 0x10 the Two wire Serial Interface can access the same Slave a
169. NT vs Vcc INTERNAL RC OSCILLATOR 4 MHz 40 C lt 25 C 85 C 2 5 3 3 5 4 Voc V 4 5 5 5 5 ATlmega8 L memm 2486R AVR 07 07 ATmega8 L Figure 129 Idle Supply Current vs Voc Internal RC Oscillator 2 MHz IDLE SUPPLY CURRENT vs Vcc INTERNAL RC OSCILLATOR 2 MHz 40 C 85 C 25 C z 8 Voc V Figure 130 Idle Supply Current vs Vcc Internal RC Oscillator 1 MHz IDLE SUPPLY CURRENT vs Vcc INTERNAL RC OSCILLATOR 1 MHz 0 9 85 C 25 C 0 8 40 C 0 7 _ 06 lt x E05 8 04 0 3 0 2 0 1 0 2 5 3 3 5 4 4 5 5 5 5 Voc V AMEL 255 2486R AVR 07 07 AMEL Figure 131 Idle Supply Current vs Vec 32 kHz External Oscillator IDLE SUPPLY CURRENT vs Vcc 32kHz EXTERNAL OSCILLATOR 40 35 25 C 30 25 20 lcc uA 2 5 3 8 5 4 4 5 5 5 5 Voc V Power down Supply Current Figure 132 Power down Supply Current vs Voc Watchdog Timer Disabled POWER DOWN SUPPLY CURRENT vs Vcc WATCHDOG TIMER DISABLED 2 5 85 C 2 a 19 40 C i 25 C 8 i S m odd 0 2 5 3 3 5 4 4 5 5 5 5 Voc V 26 ATmega8 L mmm ATmega8 L Figure 133 Power down Supply Current vs Voc Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs Vcc WATCHDOG TIMER ENABLED loc UA
170. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I O AMEL s Ports as General Digital y o Configuring the Pin AMEL The ports are bi directional I O ports with optional internal pull ups Figure 22 shows a functional description of one I O port pin here generically called Pxn Figure 22 General Digital I O DATA BUS SYNCHRONIZER WRITE DDRx PUD PULLUP DISABLE RDx READ DDRx SLEEP SLEEP CONTROL WPx WRITE PORTx clk VO CLOCK RRx READ PORTx REGISTER RPx READ PORTx PIN Note 1 WPx WDx RRx RPx and RDx are common to all pins within the same port clkyo SLEEP and PUD are common to all ports Each port pin consists of 3 Register bits DDxn PORTxn and PINxn As shown in Reg ister Description for I O Ports on page 65 the DDxn bits are accessed at the DDRx I O address the PORTxn bits at the PORTx I O address and the PINxn bits at the PINx I O address The DDxn bit in the DDRx Register selects the direction of this pin If DDxn is written logic one Pxn is configured as an output pin If DDxn is written logic zero Pxn is config ured as an input pin If PORTxn is written logic one when the pin is configured as an input pin the pull up resistor is activated To switch the pull up resistor off PORTxn has to be written logic zero or the pin has to be configured as an output pin The port pins are tri stated wh
171. OSI SPI Bus Master Output Slave Input OC2 Timer Counter2 Output Compare Match Output PB2 SS SPI Bus Master Slave select OC1B Timer Counter1 Output Compare Match B Output PB1 OC1A Timer Counter1 Output Compare Match A Output PBO ICP1 Timer Counter1 Input Capture Pin The alternate pin configuration is as follows XTAL2 TOSC2 Port B Bit 7 XTAL2 Chip clock Oscillator pin 2 Used as clock pin for crystal Oscillator or Low fre quency crystal Oscillator When used as a clock pin the pin can not be used as an I O pin TOSC2 Timer Oscillator pin 2 Used only if internal calibrated RC Oscillator is selected as chip clock source and the asynchronous timer is enabled by the correct setting in ASSR When the AS2 bit in ASSR is set one to enable asynchronous clocking of Timer Counter2 pin PB7 is disconnected from the port and becomes the inverting out put of the Oscillator amplifier In this mode a crystal Oscillator is connected to this pin and the pin cannot be used as an O pin If PB7 is used as a clock pin DDB7 PORTB7 and PINB7 will all read O e XTAL1 TOSC1 Port B Bit 6 XTAL1 Chip clock Oscillator pin 1 Used for all chip clock sources except internal cali brated RC Oscillator When used as a clock pin the pin can not be used as an I O pin TOSC1 Timer Oscillator pin 1 Used only if internal calibrated RC Oscillator is selected as chip clock source and the asynchronous timer is enabled by the correct setting in
172. PD3 INT1 External Interrupt 1 Input PD2 INTO External Interrupt O Input PD1 TXD USART Output Pin PDO RXD USART Input Pin The alternate pin configuration is as follows AIN1 Port D Bit 7 AIN1 Analog Comparator Negative Input Configure the port pin as input with the inter nal pull up switched off to avoid the digital port function from interfering with the function of the Analog Comparator AINO Port D Bit 6 AINO Analog Comparator Positive Input Configure the port pin as input with the internal pull up switched off to avoid the digital port function from interfering with the function of the Analog Comparator T1 Port D Bit 5 T1 Timer Counter1 counter source e XCK TO Port D Bit 4 XCK USART external clock TO Timer CounterO counter source INT1 Port D Bit 3 INT1 External Interrupt source 1 The PD3 pin can serve as an external interrupt source INTO Port D Bit 2 INTO External Interrupt source 0 The PD2 pin can serve as an external interrupt source TXD Port D Bit 1 TXD Transmit Data Data output pin for the USART When the USART Transmitter is enabled this pin is configured as an output regardless of the value of DDD1 RXD Port D Bit 0 RXD Receive Data Data input pin for the USART When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDDO When the USART forces this pin to be an input the pull up ca
173. PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTBO 65 0x17 0x37 DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO 65 0x16 0x36 PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINBO 65 0x15 0x35 PORTC PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTCO 65 0x14 0x34 DDRC DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDCO 65 0x13 0x33 PINC PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINCO 65 0x12 0x32 PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTDO 65 0x11 0x31 DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDDO 65 0x10 0x30 PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PINDO 65 OxOF 0x2F SPDR SPI Data Register 131 OxOE 0x2E SPSR SPIF WCOL SPI2X 131 0x0D 0x2D SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPRO 129 Ox0C 0x2C UDR USART I O Data Register 153 0x0B 0x2B UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 154 Ox0A 0x2A UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 155 0x09 0x29 UBRRL USART Baud Rate Register Low byte 158 0x08 0x28 ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACISO 194 0x07 0x27 ADMUX REFS1 REFSO ADLAR MUX3 MUX2 MUX1 MUXO 205 0x06 0x26 ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPSO 207 0x05 0x25 ADCH ADC Data Register High byte 208 0x04 0x24 ADCL ADC Data Register Low byte 208 0x03 0x23 TWDR Two wire Serial Interface Data Register 173 0x02 0x22 TWAR TWA6 TWAS TWA4 TWAS3 TWA2 TWA1 TWAO TWGCE 174 2486R AVR 07 07 AMEL 287 Register Summary Continued AMEL
174. Pin absolute value H Rast Reset Pull up Resistor 30 80 kQ ATmega8 L 2486R AVR 07 07 AT 11 C025 T4 40 C to 85 C Vec 2 7V to 5 5V unless otherwise noted Continued Symbol Parameter Condition Min Typ Max Units Rou I O Pin Pull up Resistor 20 50 kQ Active 4 MHz Voc 3V ATmega8L S mA Active 8 MHz Voc 5V 15 mA ATmega8 Power Supply Current Idle 4 MHz Vcc 3V 2 in loc ATmega8L Idle 8 MHz Vcc 5V ATmega8 1 In WDT enabled Vcc 3V 28 pA Power down mode WDT disabled Voc 3V 3 yA Analog Comparator Voc 5V Vacio Input Offset Voltage Vin Vcc 2 is me Analog Comparator Voc 5V F lACLK Input Leakage Current Vin Vcc 2 is n t Analog Comparator Voc 2 7V 750 ris AGED Propagation Delay Voc 5 0V 500 Notes 1 Max means the highest value where the pin is guaranteed to be read as low 2 Min means the lowest value where the pin is guaranteed to be read as high 3 Although each I O port can sink more than the test conditions 20mA at Vcc 5V 10mA at Vcc 3V under steady state conditions non transient the following must be observed PDIP TQFP and QFN MLF Package 1 The sum of all IOL for all ports should not exceed 300 mA 2 The sum of all IOL for ports CO C5 should not exceed 100 mA 3 The sum of all IOL for ports BO B7 C6 DO D7 and XTAL2 should not exceed 200 mA If IOL exceeds
175. Q Notes 1 Values are guidelines only 2 Minimum for AV g is 2 7V 3 Maximum for AV g is 5 5V 4 Maximum conversion time is 1 50kHz 25 0 5 ms 248 ATmega8 L memm 2486R AVR 07 07 f 11 C025 ATmega Typical Characteristics Active Supply Current 2486R AVR 07 07 The following charts show typical behavior These figures are not tested during manu facturing All current consumption measurements are performed with all I O pins configured as inputs and with internal pull ups enabled A sine wave generator with Rail to Rail output is used as clock source The power consumption in Power down mode is independent of clock selection The current consumption is a function of several factors such as operating voltage operating frequency loading of I O pins switching rate of I O pins code executed and ambient temperature The dominating factors are operating voltage and frequency The current drawn from capacitive loaded pins may be estimated for one pin as C Voc f where C load capacitance Ve operating voltage and f average switch ing frequency of I O pin The parts are characterized at frequencies higher than test limits Parts are not guaran teed to function properly at frequencies higher than the ordering code indicates The difference between current consumption in Power down mode with Watchdog Timer enabled and Power down mode with Watchdog Timer disabled represents the dif
176. S Stop Bit s 0 1 bit 1 2 bit Bit 2 1 UCSZ1 0 Character Size The UCSZ1 0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits Character Size in a frame the Receiver and Transmitter use Table 58 UCSZ Bits Settings UCSZ2 UCSZ1 UCSZO Character Size 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit Bit 0 UCPOL Clock Polarity AMEL 157 USART Baud Rate Registers UBRRL and UBRRHs 158 AMEL This bit is used for Synchronous mode only Write this bit to zero when Asynchronous mode is used The UCPOL bit sets the relationship between data output change and data input sample and the synchronous clock XCK Table 59 UCPOL Bit Settings Transmitted Data Changed Output of Received Data Sampled Input on UCPOL TxD Pin RxD Pin 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge Bit 15 14 13 12 11 10 9 8 Fuse 7 T BRT UBRRL 7 6 5 4 3 2 1 0 Read Write R W R R R R W R W R W R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The UBRRH Register shares the same I O location as the UCSRC Register See the Accessing UBRRH UCSRC Registers on page 152 section which describes how to access this register Bit 15 URSEL Register Select This bit selects between accessing the UBRRH or the UCSRC Register It is
177. T must be cleared by writing a logic one to it This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag no other bits in TWCR are affected The SDA and SCL lines are released and no STOP condition is transmitted Table 70 Miscellaneous States Status Code TWSR Application Software Response Status of the Two wire Serial To TWCR Prescaler Bits Bus and Two wire Serial Inter to from TWDR are 0 face Hardware STA STO TWINT TWEA Next Action Taken by TWI Hardware OxF8 No relevant state information No TWDR action No TWCR action Wait or proceed current transfer available TWINT 0 0x00 Bus error due to an illegal No TWDR action 0 1 1 X Only the internal hardware is affected no STOP condi START or STOP condition tion is sent on the bus In all cases the bus is released and TWSTO is cleared 190 ATmegae8 L iOO 2486R AVR 07 07 A 11 C025 Combining Several TWI Modes Multi master Systems and Arbitration 2486R AVR 07 07 In some cases several TWI modes must be combined in order to complete the desired action Consider for example reading data from a serial EEPROM Typically such a transfer involves the following steps 1 The transfer must be initiated 2 The EEPROM must be instructed what location should be read 3 The reading must be performed 4 The transfer must be finished Note that data is transm
178. TTOM The counter reaches the BOTTOM when it becomes zero 0x00 MAX The counter reaches its MAXimum when it becomes OxFF decimal 255 TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence The TOP value can be assigned to be the fixed value OxFF MAX or the value stored in the OCR2 Register The assignment is dependent on the mode of operation The Timer Counter can be clocked by an internal synchronous or an external asynchro nous clock source The clock source clky is by default equal to the MCU clock clkjo When the AS2 bit in the ASSR Register is written to logic one the clock source is taken from the Timer Counter Oscillator connected to TOSC1 and TOSC2 For details on asynchronous operation see Asynchronous Status Register ASSR on page 119 For details on clock sources and prescaler see Timer Counter Prescaler on page 123 AMEL 105 AMEL Counter Unit The main part of the 8 bit Timer Counter is the programmable bi directional counter unit Figure 46 shows a block diagram of the counter and its surrounding environment Figure 46 Counter Unit Block Diagram TOVn Int Req Prescaler DATA BUS T C clear Control Logic Oscillator clk Signal description internal signals count Increment or decrement TCNT2 by 1 direction Selects between increment and decrement clear Clear TCNT2 set all bits to zero clky gt Timer C
179. TWCR The Address Match unit is able to com pare addresses even when the AVR MCU is in sleep mode enabling the MCU to wake up if addressed by a Master If another interrupt e g INTO occurs during TWI Power down address match and wakes up the CPU the TWI aborts operation and return to it s idle state If this cause any problems ensure that TWI Address Match is the only enabled interrupt when entering Power down The Control unit monitors the TWI bus and generates responses corresponding to set tings in the TWI Control Register TWCR When an event requiring the attention of the application occurs on the TWI bus the TWI Interrupt Flag TWINT is asserted In the next clock cycle the TWI Status Register TWSR is updated with a status code identify ing the event The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted At all other times the TWSR contains a special status code indicating that no relevant status information is available As long as the TWINT Flag is vo ATmega8 L mmm 2486R AVR 07 07 XX 9X A megae8 L TWI Register Description TWI Bit Rate Register TWBR TWI Control Register TWCR 2486R AVR 07 07 set the SCL line is held low This allows the application software to complete its tasks before allowing the TWI transmission to continue The TWINT Flag is set in the following situations e After the TWI has transmitted a START REPEATED START condition
180. The TWI hardware checks if the bus is available and generates a START condition on the bus if it is free However if the bus is not free the TWI waits until a STOP condition is detected and then generates a new START condition to claim the bus Master status TWSTA must be cleared by software when the START condition has been transmitted Bit4 TWSTO TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two wire Serial Bus When the STOP condition is executed on the bus the TWSTO bit is cleared automatically In Slave mode setting the TWSTO bit can be used to recover from an error condition This will not generate a STOP condition but the TWI returns to a well defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state Bit3 TWWC TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register TWDR when TWINT is low This flag is cleared by writing the TWDR Register when TWINT is high Bit2 TWEN TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface When TWEN is written to one the TWI takes control over the I O pins connected to the SCL and SDA pins enabling the slew rate limiters and spike filters If this bit is written to zero the TWI is switched off and all TWI transmissions are terminated regardless of any ongoing operation Bit 1 Res Reserved Bit This bit is a rese
181. This bit is set by hardware when the TWI has finished its current job and expects appli cation software response If the I bit in SREG and TWIE in TWCR are set the MCU will jump to the TWI Interrupt Vector While the TWINT Flag is set the SCL low period is stretched The TWINT Flag must be cleared by software by writing a logic one to it Note that this flag is not automatically cleared by hardware when executing the interrupt rou tine Also note that clearing this flag starts the operation of the TWI so all accesses to the TWI Address Register TWAR TWI Status Register TWSR and TWI Data Regis ter TWDR must be complete before clearing this flag Bit6 TWEA TWI Enable Acknowledge Bit AMEL 171 172 AMEL The TWEA bit controls the generation of the acknowledge pulse If the TWEA bit is writ ten to one the ACK pulse is generated on the TWI bus if the following conditions are met 1 The device s own slave address has been received 2 Ageneral call has been received while the TWGCE bit in the TWAR is set 3 A data byte has been received in Master Receiver or Slave Receiver mode By writing the TWEA bit to zero the device can be virtually disconnected from the Two wire Serial Bus temporarily Address recognition can then be resumed by writing the TWEA bit to one again Bit 5 TWSTA TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the Two wire Serial Bus
182. VR 07 07 T Master Receiver Mode AMEL In the Master Receiver mode a number of data bytes are received from a Slave Trans mitter see Figure 80 In order to enter a Master mode a START condition must be transmitted The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered If SLA W is transmitted MT mode is entered if SLA R is transmitted MR mode is entered All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero Voc Figure 80 Data Transfer in Master Receiver Mode Device 1 Device 2 MASTER SLAVE Device3 Device n R1 R2 RECEIVER TRANSMITTER SDA SCL A START condition is sent by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 1 0 X 1 0 X TWEN must be written to one to enable the Two wire Serial Interface TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag The TWI will then test the Two wire Serial Bus and generate a START condition as soon as the bus becomes free After a START condition has been transmitted the TWINT Flag is set by hardware and the status code in TWSR will be 0x08 See Table 66 In order to enter MR mode SLA R must be transmitted This is done by writing SLA R to TWDR Thereafter the TWI
183. Value of Pull up resistor fac gt 100 kHz Voc 0 4 300ns F Q 3mA C tup sTa Hold Time repeated START Condition fsc gt 100 kHz 0 6 us fgc lt 100 kHz 9 4 7 us tiow Low Period of the SCL Clock fsc gt 100 kHz 1 3 us fasc 100 kHz 4 0 Hs tuicH High period of the SCL clock fec gt 100 kHz 0 6 x Us fec lt 100 kHz 4 7 us tsu sta Set up time for a repeated START condition fsc gt 100 kHz 0 6 us fasc lt 100 kHz 0 3 45 us tup pat Data hold time fsc gt 100 kHz 0 0 9 us fgg 100 kHz 250 ns tsu pAT Data setup time fsc gt 100 kHz 100 ns tsu sto Setup time for STOP condition fsc gt 100 KHz 0 6 us i Bus free time between a STOP and START fsc lt 100 kHz 4 7 us iil condition fac gt 100 kHz 1 3 us Notes 1 In ATmegaS this parameter is characterized and not 100 tested 2 Required only for fac 100 kHz 3 C capacitance of one bus line in pF 4 fox CPU clock frequency AMEL 245 aa O 2486R AVR 07 07 AMEL 5 This requirement applies to all ATmega8 Two wire Serial Interface operation Other devices connected to the Two wire Serial Bus need only obey the general fasc requirement 6 The actual low period generated by the ATmega8 Two wire Serial Interface is 1 fac 2 fc thus fc must be greater than 6 MHz for the low time requirement to be strictly met at fac 100 kHz 7 The actual low period generated by the ATmega8 Two wire Serial Interface is 1 fac 2 f
184. W R W R W R W R W R W Initial Value 1 0 0 0 0 1 1 0 The UCSRC Register shares the same I O location as the UBRRH Register See the Accessing UBRRH UCSRC Registers on page 152 section which describes how to access this register Bit 7 URSEL Register Select This bit selects between accessing the UCSRC or the UBRRH Register It is read as one when reading UCSRC The URSEL must be one when writing the UCSRC e Bit6 UMSEL USART Mode Select This bit selects between Asynchronous and Synchronous mode of operation Table 55 UMSEL Bit Settings UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation ss ATmega8 L memm 2486R AVR 07 07 AT 11 C025 2486R AVR 07 07 e Bit 5 4 UPM1 0 Parity Mode These bits enable and set type of Parity Generation and Check If enabled the Trans mitter will automatically generate and send the parity of the transmitted data bits within each frame The Receiver will generate a parity value for the incoming data and com pare it to the UPMO setting If a mismatch is detected the PE Flag in UCSRA will be set Table 56 UPM Bits Settings UPM1 UPMO Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled Even Parity 1 1 Enabled Odd Parity e Bit 3 USBS Stop Bit Select This bit selects the number of stop bits to be inserted by the trAnsmitter The Receiver ignores this setting Table 57 USBS Bit Settings USB
185. W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 0 TOIEO Timer CounterO Overflow Interrupt Enable When the TOIEO bit is written to one and the I bit in the Status Register is set one the Timer CounterO Overflow interrupt is enabled The corresponding interrupt is executed if an overflow in Timer CounterO occurs i e when the TOVO bit is set in the Timer Counter Interrupt Flag Register TIFR 72 ATmega8 L memm 2486R AVR 07 07 Aimegae8 L Timer Counter Interrupt Flag Register TIFR 2486R AVR 07 07 Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 TOVO TIFR Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 0 TOVO Timer Counter0 Overflow Flag The bit TOVO is set one when an overflow occurs in Timer CounterO TOVO is cleared by hardware when executing the corresponding interrupt Handling Vector Alternatively TOVO is cleared by writing a logic one to the flag When the SREG I bit TOIEO Timer CounterO Overflow Interrupt Enable and TOVO are set one the Timer CounterO Overflow interrupt is executed AMEL 7 Timer CounterO and Timer Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source AMEL Timer Counter1 and Timer CounterO share the same prescaler module but the Timer Counters can have different prescaler settings The description below applies to both Timer Counter1 and Timer Counte
186. Waveform Generation mode bits do The COM21 0 bits control whether the PWM output generated should be inverted or not inverted or non inverted PWM For non PWM modes the COM21 0 bits control whether the output should be set cleared or toggled at a Compare Match see Compare Match Output Unit on page 109 For detailed timing information refer to Timer Counter Timing Diagrams on page 115 The simplest mode of operation is the Normal mode WGM21 0 0 In this mode the counting direction is always up incrementing and no counter clear is performed The counter simply overruns when it passes its maximum 8 bit value TOP OxFF and then restarts from the bottom 0x00 In normal operation the Timer Counter Overflow Flag TOV2 will be set in the same timer clock cycle as the TCNT2 becomes zero The TOV2 Flag in this case behaves like a ninth bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOV2 Flag the timer resolution can be increased by software There are no special cases to consider in the Normal mode a new counter value can be written anytime The Output Compare unit can be used to generate interrupts at some given time Using the Output Compare to generate waveforms in Normal mode is not recommended since this will occupy too much of the CPU time no ATmega8 L m 2486R AVR 07 07 X X X f megae8 L Clear Timer on Co
187. When the INT1 bit is set one and the I bit in the Status Register SREG is set one the external pin interrupt is enabled The Interrupt Sense Control1 bits 1 0 ISC11 and ISC10 in the MCU general Control Register MCUCR define whether the external interrupt is activated on rising and or falling edge of the INT1 pin or level sensed Activity on the pin will cause an interrupt request even if INT1 is configured as an output The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Inter rupt Vector Bit 6 INTO External Interrupt Request 0 Enable When the INTO bit is set one and the I bit in the Status Register SREG is set one the external pin interrupt is enabled The Interrupt Sense ControlO bits 1 0 ISCO1 and ISCOO in the MCU general Control Register MCUCR define whether the external interrupt is activated on rising and or falling edge of the INTO pin or level sensed Activity on the pin will cause an interrupt request even if INTO is configured as an output The corresponding interrupt of External Interrupt Request 0 is executed from the INTO Inter rupt Vector AMEL 7 General Interrupt Flag Register GIFR AMEL Bit 7 6 5 4 3 2 1 0 NTFT INTFO es 9 Read Write R W R W R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 INTF1 External Interrupt Flag 1 When an event on the INT1 pin triggers an interrupt request INTF1 becomes set one If the I bit in SREG and the INT1 bi
188. ad as one AMEL 217 AMEL Preventing Flash Corruption During periods of low Vec the Flash program can be corrupted because the supply volt age is too low for the CPU and the Flash to operate properly These issues are the same as for board level systems using the Flash and the same design solutions should be applied A Flash program corruption can be caused by two situations when the voltage is too low First a regular write sequence to the Flash requires a minimum voltage to operate cor rectly Secondly the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low Flash corruption can easily be avoided by following these design recommendations one is sufficient 1 If there is no need for a Boot Loader update in the system program the Boot Loader Lock Bits to prevent any Boot Loader software updates 2 Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating voltage matches the detection level If not an external low Voc Reset Protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient 3 Keep the AVR core in Power down sleep mode during periods of low Vcc This will prevent the CPU from attempting to decode and execute instructions effec tive
189. age 159 The transfer rate can be doubled by setting the U2X bit in UCSRA Setting this bit only has effect for the asynchronous operation Set this bit to zero when using synchronous operation Setting this bit will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication Note however that the Receiver will in this case only use half the number of samples reduced from 16 to 8 for data sampling and clock recovery and therefore a more accurate baud rate setting and system clock are required when this mode is used For the Transmitter there are no downsides External clocking is used by the Synchronous Slave modes of operation The descrip tion in this section refers to Figure 62 for details External clock input from the XCK pin is sampled by a synchronization register to mini mize the chance of meta stability The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver This process introduces a two CPU clock period delay and therefore the max imum external XCK clock frequency is limited by the following equation fosc fxcK lt 4 Note that f depends on the stability of the system clock source It is therefore recom mended to add some margin to avoid possible loss of data due to frequency variations n ATmega8 L mmm 2486R AVR 07 07 X f megae8 L
190. age 25 Port C is an 7 bit bi directional l O port with internal pull up resistors selected for each bit The Port C output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running If the RSTDISBL Fuse is programmed PC6 is used as an I O pin Note that the electri cal characteristics of PC6 differ from those of the other pins of Port C If the RSTDISBL Fuse is unprogrammed PC6 is used as a Reset input A low level on this pin for longer than the minimum pulse length will generate a Reset even if the clock is not running The minimum pulse length is given in Table 15 on page 38 Shorter pulses are not guaranteed to generate a Reset The various special features of Port C are elaborated on page 61 Port D is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port D output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port D pins that are externally pulled low will source current if the pull up resistors are activated The Port D pins are tri stated when a reset condition becomes active even if the clock is not running Port D also serves the functions of various special features of the ATmega as l
191. alog Comparator The user can select Interrupt triggering on comparator output rise fall or toggle A block dia gram of the comparator and its surrounding logic is shown in Figure 89 Figure 89 Analog Comparator Block Diagram ANALOG INTERRUPT COMPARATOR SELECT IRQ ACI ACIS1 ACISO ACIC NEN TO T C1 CAPTURE TRIGGER MUX ADC MULTIPLEXER OUTPUT Notes 1 See Table 72 on page 195 2 Refer to Pin Configurations on page 2 and Table 28 on page 63 for Analog Compar ator pin placement Special Function IO Register SFIOR Bit 7 6 5 4 3 2 1 0 LL ELLELLCLLDAWeT T SFIOR Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 3 ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off ADEN in ADCSRA is zero the ADC multiplexer selects the negative input to the Analog Comparator When this bit is written logic zero AIN1 is applied to the negative input of the Analog Compar ator For a detailed description of this bit see Analog Comparator Multiplexed Input on page 195 AMEL 193 2486R AVR 07 07 Analog Comparator Control and Status Register ACSR AMEL Bit 7 6 5 4 3 2 1 0 ACD ACBG ACIE ACIC ACIS1 ACISO ACSR Read Write R W R W R R W R W R W R W R W Initial Value 0 0 N A 0 0 0 0 0 e Bit 7 ACD Analog Comparator Disable When this bit is written logic one the power to the Analog Comparator is switched off T
192. alue WMG13 0 11 and COM1A1 0 1 the OC1A output will toggle with a 50 duty cycle The phase and frequency correct Pulse Width Modulation or phase and frequency cor rect PWM mode WGM13 0 8 or 9 provides a high resolution phase and frequency correct PWM waveform generation option The phase and frequency correct PWM mode is like the phase correct PWM mode based on a dual slope operation The counter counts repeatedly from BOTTOM 0x0000 to TOP and then from TOP to BOT TOM In non inverting Compare Output mode the Output Compare OC1x is cleared on the Compare Match between TCNT1 and OCR1x while upcounting and set on the Compare Match while downcounting In inverting Compare Output mode the operation is inverted The dual slope operation gives a lower maximum operation frequency com pared to the single slope operation However due to the symmetric feature of the dual slope PWM modes these modes are preferred for motor control applications The main difference between the phase correct and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register see Figure 39 and Figure 40 The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A The minimum resolution allowed is 2 bit ICR1 or OCR1A set to 0x0003 and the maximum resolution is 16 bit ICR1 or OCR1A set to MAX The PWM resolution in bits can be calculated using the following
193. ample The CPHA functionality is summarized below Table 49 CPHA Functionality CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1 0 SPR1 SPRO SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master SPR1 and SPRO have no effect on the Slave The relationship between SCK and the Oscillator Clock frequency f is shown in the following table Table 50 Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPRO SCK Frequency 0 0 0 fos 4 0 0 1 fosc 16 0 1 0 foso 64 0 1 1 f5 128 1 0 0 2 1 0 1 f54 8 1 1 0 foso 32 1 1 1 foso 64 ATmega8 L memm 2486R AVR 07 07 A megae8 L SPI Status Register SPSR SPI Data Register SPDR 2486R AVR 07 07 Bit 7 6 5 4 3 2 1 0 Ser woot CL LLLLLLLLSEE ses Read Write R R R R R R R R W Initial Value 0 0 0 0 0 0 0 0 e Bit7 SPIF SPI Interrupt Flag When a serial transfer is complete the SPIF Flag is set An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled If SS is an input and is driven low when the SPI is in Master mode this will also set the SPIF Flag SPIF is cleared by hardware when executing the corresponding interrupt Handling Vector Alternatively the SPIF bit is cleared by first reading the SPI Status Register with SPIF set then accessing the SPI Data Register SPDR
194. and Figure 60 Data bits are shifted out and latched in on oppo site edges of the SCK signal ensuring sufficient time for data signals to stabilize This is clearly seen by summarizing Table 48 and Table 49 as done below Table 51 CPOL and CPHA Functionality Leading Edge Trailing Edge SPI Mode CPOL 0 CPHA 0 Sample Rising Setup Falling 0 CPOL 0 CPHA 1 Setup Rising Sample Falling 1 CPOL 1 CPHA 0 Sample Falling Setup Rising 2 CPOL 1 CPHA 1 Setup Falling Sample Rising 3 Figure 59 SPI Transfer Format with CPHA 0 ScK CPOL 0 mode 0 SCK CPOL 1 mode 2 SAMPLE MOSI MISO marn VC MOSI PIN CHANGE 0 i L MISO PIN SS MSB first DORD 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB first DORD 1 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Figure 60 SPI Transfer Format with CPHA 1 SCK CPOL 0 mode 1 SCK CPOL 1 mode 3 MOSI MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first DORD 0 MSB Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 LSB LSB first DORD 1 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB ATmegae8 L 2486R AVR 07 07 f 11 C025 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter USART is a highly flexible serial communication device The main features are F
195. apture Noise Canceler ICNC1 bit in Timer Counter Control Register B TCCR1B When enabled the noise canceler intro duces additional four system clock cycles of delay from a change applied to the input to the update of the ICR1 Register The noise canceler uses the system clock and is there fore not affected by the prescaler The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events The time between two events is critical If the processor has not read the captured value in the ICR1 Register before the next event occurs the ICR1 will be overwritten with a new value In this case the result of the cap ture will be incorrect When using the Input Capture interrupt the ICR1 Register should be read as early in the interrupt handler routine as possible Even though the Input Capture interrupt has rela tively high priority the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests Using the Input Capture unit in any mode of operation when the TOP value resolution is actively changed during operation is not recommended Measurement of an external signal s duty cycle requires that the trigger edge is changed after each capture Changing the edge sensing must be done as early as possible after the ICR1 Register has been read After a change of the edge the Input Capture Flag 84 ATmega8 L memm
196. arator Output ACO and this change confirms to the setting of the edge detector a capture will be triggered When a capture is triggered the 16 bit value of the counter TCNT1 is written to the nput Capture Register ICR1 The Input Capture Flag ICF1 is set at the same system clock as the TCNT1 value is copied into ICR1 Register If enabled TICIE1 1 the Input Capture Flag generates an Input Capture interrupt The ICF1 Flag is automatically cleared when the interrupt is executed Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I O bit location AMEL s 2486R AVR 07 07 Input Capture Pin Source Noise Canceler Using the Input Capture Unit AMEL Reading the 16 bit value in the Input Capture Register ICR1 is done by first reading the Low byte ICR1L and then the High byte ICR1H When the Low byte is read the High byte is copied into the High byte temporary register TEMP When the CPU reads the ICR1H I O location it will access the TEMP Register The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter s TOP value In these cases the Waveform Generation mode WGM13 0 bits must be set before the TOP value can be written to the ICR1 Register When writing the ICR1 Register the High byte must be writ ten to the ICR1H I O location before the Low byte is written to ICR1L For more information on how to acces
197. assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt Depending on the Program Counter value interrupts may be automatically disabled when Boot Lock Bits BLBO2 or BLB12 are programmed This feature improves software security See the section Memory Programming on page 222 for details The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors The complete list of Vectors is shown in Interrupts on page 46 The list also determines the priority levels of the different interrupts The lower the address the higher is the priority level RESET has the highest priority and next is INTO the External Interrupt Request 0 The Interrupt Vectors can be moved to the start 14 ATmega8 L memm 2486R AVR 07 07 f mega8 L 2486R AVR 07 07 of the boot Flash section by setting the Interrupt Vector Select IVSEL bit in the General Interrupt Control Register GICR Refer to Interrupts on page 46 for more information The Reset Vector can also be moved to the start of the boot Flash section by program ming the BOOTRST Fuse see Boot Loader Support Read While Write Self Programming on page 209 When an interrupt occurs the Global Interrupt Enable I bit is cleared and all interrupts are disabled The user software can write logic one to the I bit to ena
198. ata from data register in r16 EEDR ret C Code Example unsigned char EEPROM read unsigned int uiAddress Wait for completion of previous write while EECR amp 1 EEWE Set up address register EEAR uiAddress Start eeprom read by writing EERE EECR 1 EERE Return data from data register return EEDR EEPROM Write during Power When entering Power down sleep mode while an EEPROM write operation is active the down Sleep Mode EEPROM write operation will continue and will complete before the Write Access time has passed However when the write operation is completed the Oscillator continues running and as a consequence the device does not enter Power down entirely It is therefore recommended to verify that the EEPROM write operation is completed before entering Power down Preventing EEPROM During periods of low Voc the EEPROM data can be corrupted because the supply volt Corruption age is too low for the CPU and the EEPROM to operate properly These issues are the same as for board level systems using EEPROM and the same design solutions should be applied An EEPROM data corruption can be caused by two situations when the voltage is too low First a regular write sequence to the EEPROM requires a minimum voltage to operate correctly Second the CPU itself can execute instructions incorrectly if the sup ply vol
199. ated 250 ns Notes 1 tw Rn is valid for the Write Flash Write EEPROM Write Fuse Bits and Write Lock Bits commands 2 twerH_ce S valid for the Chip Erase command 2 ATmega8 L memm f mega8 L Serial Downloading Serial Programming Pin Mapping 2486R AVR 07 07 Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND The serial interface consists of pins SCK MOSI input and MISO output After RESET is set low the Programming Enable instruction needs to be executed first before program erase operations can be executed NOTE in Table 96 on page 237 the pin mapping for SPI programming is listed Not all parts use the SPI pins dedicated for the internal SPI interface Table 96 Pin Mapping Serial Programming Symbol Pins yo Description MOSI PB3 l Serial data in MISO PB4 O Serial data out SCK PB5 l Serial clock Figure 112 Serial Programming and Verify MOSI MISO SCK Notes 1 If the device is clocked by the Internal Oscillator it is no need to connect a clock source to the XTAL1 pin 2 Vec 0 3 lt AVoc lt Vec 0 3 however AVcc should always be within 2 7 5 5V When programming the EEPROM an auto erase cycle is built into the self timed pro gramming operation in the Serial mode ONLY and there is no need to first execute the Chip Erase instruction The Chip Erase
200. be programmed simultaneously The programming algorithm for the EEPROM Data memory is as follows refer to Programming the Flash on page 229 for details on Command Address and Data loading 1 A Load Command 0001 0001 2 G Load Address High byte 0x00 OxFF 3 B Load Address Low byte 0x00 OxFF 4 C Load Data 0x00 OxFF 5 E Latch data give PAGEL a positive pulse K Repeat 3 through 5 until the entire buffer is filled L Program EEPROM page 1 Set BS1 to 0 2 Give WR a negative pulse This starts programming of the EEPROM page RDY BSY goes low 3 Wait until to RDY BSY goes high before programming the next page See Figure 107 for signal waveforms AMEL 231 2486R AVR 07 07 AMEL Figure 107 Programming the EEPROM Waveforms K OSs A G B C E B C E L DATA X om Yaon many aooniowy oara Y xx aon vow oaa Y x n N xao ae ae si f xri Exe AG X X Wn des RDY BSY EMT S RESET 12V OE PAGEL cs BS2 Reading the Flash The algorithm for reading the Flash memory is as follows refer to Programming the Flash on page 229 for details on Command and Address loading 1 A Load Command 0000 0010 2 G Load Address High byte 0x00 OxFF 3 B Load Address Low byte 0x00 OxFF 4 Set OE to 0 and BS1 to 0 The Flash word Low byte can now be read at DATA 5 Set BS1 to 1 The Flash word High byte can no
201. bit is set if the next character in the receive buffer had a Frame Error when received i e when the first stop bit of the next character in the receive buffer is zero This bit is valid until the receive buffer UDR is read The FE bit is zero when the stop bit of received data is one Always set this bit to zero when writing to UCSRA Bit 3 DOR Data OverRun This bit is set if a Data OverRun condition is detected A Data OverRun occurs when the receive buffer is full two characters it is a new character waiting in the Receive Shift Register and a new start bit is detected This bit is valid until the receive buffer UDR is read Always set this bit to zero when writing to UCSRA e Bit 2 PE Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point UPM1 1 This bit is valid until the receive buffer UDR is read Always set this bit to zero when writing to UCSRA Bit 1 U2X Double the USART transmission speed 154 ATmega8 L mmm 2486R AVR 07 07 X X X A megae8 L USART Control and Status Register B UCSRB 2486R AVR 07 07 This bit only has effect for the asynchronous operation Write this bit to zero when using synchronous operation Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec tively doubling the transfer rate for asynchronous com
202. ble 91 Pins not described in the following table are referenced by pin names The XA1 XAO pins determine the action executed when the XTAL1 pin is given a posi tive pulse The bit coding is shown in Table 93 When pulsing WR or OE the command loaded determines the action executed The dif ferent Commands are shown in Table 94 Figure 104 Parallel Programming 5V o RDY BSY OE oy WR AVCC BSI PC 1 0 PBI5 0 DATA XAO XA1 PAGEL 12 V BS2 Table 91 Pin Name Mapping Signal Name in Programming Mode Pin Name I O Function RDY BSY PDI o 0 Device is busy programming 1 Device is ready for new command OE PD2 Output Enable Active low WR PD3 Write Pulse Active low Byte Select 1 0 selects Low byte 1 BSI PDA l selects High byte XAO PD5 XTAL Action Bit 0 XA1 PD6 XTAL Action Bit 1 22 ATmega8 L mmm 2486R AVR 07 07 XX A megae8 L Table 91 Pin Name Mapping Continued Signal Name in Programming Mode Pin Name I O Function Program memory and EEPROM Data low PAGEL coe Page Load Byte Select 2 0 selects Low byte 1 BS2 pee selects 2 nd High byte DATA PC 1 0 PB 5 0 1O Bi directional Data bus Output when OE is Table 92 Pin Values used to Enter Programming Mode Pin Symbol Value PAGEL Prog enable 3 0 XA1 Prog enable 2 0 XAO Prog enable 1
203. ble nested inter rupts All enabled interrupts can then interrupt the current interrupt routine The I bit is automatically set when a Return from Interrupt instruction RETI is executed There are basically two types of interrupts The first type is triggered by an event that sets the Interrupt Flag For these interrupts the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine and hardware clears the corresponding Interrupt Flag Interrupt Flags can also be cleared by writing a logic one to the flag bit position s to be cleared If an interrupt condition occurs while the corresponding interrupt enable bit is cleared the Interrupt Flag will be set and remem bered until the interrupt is enabled or the flag is cleared by software Similarly if one or more interrupt conditions occur while the global interrupt enable bit is cleared the corre sponding Interrupt Flag s will be set and remembered until the global interrupt enable bit is set and will then be executed by order of priority The second type of interrupts will trigger as long as the interrupt condition is present These interrupts do not necessarily have Interrupt Flags If the interrupt condition disap pears before the interrupt is enabled the interrupt will not be triggered When the AVR exits from an interrupt it will always return to the main program and exe cute one more instruction before any pending interrupt is
204. boxes in the block diagram separate the three main parts of the USART listed from the top Clock generator Transmitter and Receiver Control Registers are shared by all units The clock generation logic consists of synchronization logic for exter nal clock input used by synchronous slave operation and the baud rate generator The XCK transfer clock pin is only used by synchronous transfer mode The Transmitter consists of a single write buffer a serial Shift Register Parity Generator and control logic for handling different serial frame formats The write buffer allows a continuous transfer of data without any delay between frames The Receiver is the most complex part of the USART module due to its clock and data recovery units The recovery units are used for asynchronous data reception In addition to the recovery units the Receiver includes a parity checker control logic a Shift Register and a two level receive buffer UDR The Receiver supports the same frame formats as the Transmitter and can detect Frame Error Data OverRun and Parity Errors The USART is fully compatible with the AVR UART regarding e Bit locations inside all USART Registers e Baud Rate Generation e Transmitter Operation e Transmit Buffer Functionality e Receiver Operation However the receive buffering has two improvements that will affect the compatibility in some special cases e Asecond Buffer Register has been added The two Buffer Registers opera
205. by improv ing the noise immunity of the Receiver The asynchronous reception operational range depends on the accuracy of the internal baud rate clock the rate of the incoming frames and the frame size in number of bits The clock recovery logic synchronizes internal clock to the incoming serial frames Fig ure 65 illustrates the sampling process of the start bit of an incoming frame The sample rate is 16 times the baud rate for Normal mode and eight times the baud rate for Double Speed mode The horizontal arrows illustrate the synchronization variation due to the sampling process Note the larger time variation when using the Double Speed mode AMEL 147 Asynchronous Data Recovery AMEL U2X 1 of operation Samples denoted zero are samples done when the RxD line is idle i e no communication activity Figure 65 Start Bit Sampling RxD IDLE START BIT 0 cme t fet f PP tttttittttittt U2X 0 1 6 8 10 11 12 13 14 15 16 2 n o w o ae o 9 Oo 0 Sample NN 0 U2X 1 1 When the clock recovery logic detects a high idle to low start transition on the RxD line the start bit detection sequence is initiated Let sample 1 denote the first zero sample as shown in the figure The clock recovery logic then uses samples 8 9 and 10 for Normal mode and samples 4 5 and 6 for Double Speed mode indicated with sample numbers inside boxes on the figure to deci
206. cation response In this case the TWI Status Register TWSR contains a value indicating the current state of the TWI bus The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers Figure 77 is a simple example of how the application can interface to the TWI hardware In this example a Master wishes to transmit a single data byte to a Slave This descrip tion is quite abstract a more detailed explanation follows later in this section A simple code example implementing the desired behavior is also presented 174 ATmega8 L mmm 2486R AVR 07 07 Figure 77 Interfacing the Application to the TWI in a Typical Transmission ATmega8 L 1 Application 9 zr ed o a M ini ee tO SER il SLAW was 7 Check TWSR to see if data was sent writes to TWCR to sent Application loads A into sent and ACK received and ACK received Sc Bos TWDR and loads appropriate control Application loads data into TWDR and ER he Go initiate Application loads appropriate control os esi signals into TWCR makin sure that loads appropriate control signals into o transmission of signals to send STOP into TWCR g START TWINT is written to one TWCR making sure that TWINT is makina sure that TWINT is written to one x and TWSTA is written to zero written to one g TWI bus START S
207. code is detailed in Table 69 The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master mode see state OxBO If the TWEA bit is written to zero during a transfer the TWI will transmit the last byte of the transfer State OxCO or state OxC8 will be entered depending on whether the Master Receiver transmits a NACK or ACK after the final byte The TWI is switched to the not addressed Slave mode and will ignore the Master if it continues the transfer Thus the Master Receiver receives all 1 as serial data State OxC8 is entered if the Master demands additional data bytes by transmitting ACK even though the Slave has trans mitted the last byte TWEA zero and expecting NACK from the Master While TWEA is zero the TWI does not respond to its own slave address However the Two wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two wire Serial Bus 188 ATmega8 L memm 2486R AVR 07 07 AT 11 C025 In all sleep modes other than Idle mode the clock system to the TWI is turned off If the TWEA bit is set the interface can still acknowledge its own slave address or the general call address by using the Two wire Serial Bus clock as a clock source The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up
208. ction must be inserted as indicated in Figure 24 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay t through the synchronizer is 1 system clock period Figure 24 Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 OxF i INSTRUCTIONS DAD GE NNE GEIULINA GN SYNC LATCH PINxn r17 0x00 FF E ATmega8 L mmm 2486R AVR 07 07 X mJ Aimegae8 L Digital Input Enable and Sleep Modes 2486R AVR 07 07 The following code example shows how to set port B pins 0 and 1 high 2 and 3 low and define the port pins from 4 to 7 as input with pull ups assigned to port pins 6 and 7 The resulting pin values are read back again but as previously discussed a nop instruction is included to be able to read back the value recently assigned to some of the pins Assembly Code Example Define pull ups and set outputs high Define directions for port pins ldi r16 1 lt lt PB7 1 lt lt PB6 1 lt lt PB1 1 lt lt PBO ldi r17 1 lt lt DDB3 1 lt lt DDB2 1 lt lt DDB1 1 DDBO out PORTB r16 out DDRB r17 Insert nop for synchronization nop Read port pins in rl16 PINB C Code Example unsigned char i Define pull ups and set outputs high Define directions for port pins PORTB 1 lt lt PB7 1 lt lt PB6 1 lt lt PB1 1 lt lt
209. d to the ADC through a passive switch The internal 2 56V reference is generated from the internal bandgap reference Vga through an internal amplifier In either case the external AREF pin is directly connected to the ADC and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground Vgege can also be measured at the AREF pin with a high impedant voltmeter Note that Vpep is a high impedant source and only a capacitive load should be connected in a system If the user has a fixed voltage source connected to the AREF pin the user may not use the other reference voltage options in the application as they will be shorted to the external voltage If no external voltage is applied to the AREF pin the user may switch between AVcc and 2 56V as reference selection The first ADC conversion result after switching reference voltage source may be inaccurate and the user is advised to dis card this result The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I O peripherals The noise canceler can be used with ADC Noise Reduction and Idle mode To make use of this feature the following procedure should be used 1 Make sure that the ADC is enabled and is not busy converting Single Con version mode must be selected and the ADC conversion complete interrupt must be enabled 2 Enter ADC Noise Reduction mode or Idle mode
210. de if a valid start bit is received If two or more of these three samples have logical high levels the majority wins the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low transition If however a valid start bit is detected the clock recovery logic is synchronized and the data recovery can begin The synchronization process is repeated for each start bit When the Receiver clock is synchronized to the start bit the data recovery can begin The data recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode Figure 66 shows the sam pling of the data bits and the parity bit Each of the samples is given a number that is equal to the state of the recovery unit Figure 66 Sampling of Data and Parity Bit RxD Ed BIT n 2s LT Shi Hs U2X 0 1 Sample ty U2X 1 A u M P ov v oP The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit The center samples are emphasized on the figure by having the sample number inside boxes The majority voting process is done as follows If two or all three samples have high levels the received bit is registered to be a logic 1 If two or all three samples have low levels the received bit is registered to b
211. dge its own slave address or the general call address by using the Two wire Serial Bus clock as a clock source The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared by writing it to one Further data reception will be car ried out as normal with the AVR clocks running as normal Observe that if the AVR is set up with a long start up time the SCL line may be held low for a long time blocking other data transmissions Note that the Two wire Serial Interface Data Register TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes AMEL 185 Table 68 Status Codes for Slave Receiver Mode Status Code TWSR Status of the Two wire Serial Bus AMEL Application Software Response Prescaler Bits and Two wire Serial Interface To from TWDR ALLE are 0 Hardware STA STO TWINT TWEA Next Action Taken by TWI Hardware 0x60 Own SLA W has been received No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be ACK has been returned returned No TWDR action X 0 1 1 Data byte will be received and ACK will be returned 0x68 Arbitration lost in SLA R W as No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be Master own SLA W has been returned received ACK has been returned No TWDR action X 0 1 1 Data byte will b
212. direct Jump to Z PC lt Z None 2 RCALL k Relative Subroutine Call PC lt PC k 1 None 3 CALL Indirect Call to Z PCez None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK l 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC PC 20r3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 83 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 20r3 None 1 2 3 SBIC P b Skip if Bit in O Register Cleared if P b 0 PC lt PC 20r3 None 1 2 3 SBIS P b Skip if Bit in I O Register is Set if P b 1 PC lt PC 20r3 None 1 2 3 BRBS Sk Branch if Status Flag Set if SREG s 1 then PC lt PC k 1 None 172 BRBC s k Branch if Status Flag Cleared if SREG s 0 then PC lt PC k 1 None 1 2 BREQ Branch if Equal if Z 1 then PC PC k 1 None 1 2 BRNE Branch if Not Equal if Z 0 then PC PC k 1 None 1 2 BRCS Branch if Carry Set if C 1 then PC PC k 1 None 1 2 BRCC Branch if Carry Cleared if C 0 then PC PC k 1 None 1 2 BRSH Branch if Same or Higher if C 0 then PC PC k 1 None 1 2 BRLO Branch if Lower if C 1 then PC PC k 1 None 1 2 BRMI Branch if Minus if N 1 then PC PC k 1 None 1 2 BRPL Branch if Plus if N 0 then PC PC k 1 None 1 2 BRGE Branch if Greater or Equal S
213. during Power down Sleep Mode on page 23 Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of Port B PB7 PBO XTAL1 XTAL2 TOSC1 TOSC2 on page 5 Improved the table under SPI Timing Characteristics on page 246 and removed the table under SPI Serial Programming Characteristics on page 241 Corrected PC6 in Alternate Functions of Port C on page 61 Corrected PB6 and PB7 in Alternate Functions of Port B on page 58 Corrected 230 4 Mbps to 230 4 kbps under Examples of Baud Rate Setting on page 159 Added information about PWM symmetry for Timer 2 in Phase Correct PWM Mode on page 113 Added thick lines around accessible registers in Figure 76 on page 169 Changed will be ignored to must be written to zero for unused Z pointer bits under Performing a Page Write on page 216 Added note for RSTDISBL Fuse in Table 87 on page 223 Updated drawings in Packaging Information on page 293 AMEL 299 Changes from Rev 2486H 09 02 to Rev 24861 12 02 Changes from Rev 2486G 09 02 to Rev 2486H 09 02 Changes from Rev 2486F 07 02 to Rev 2486G 09 02 Changes from Rev 2486E 06 02 to Rev 2486F 07 02 Changes from Rev 2486D 03 02 to Rev 2486E 06 02 Changes from Rev 2486C 03 02 to Rev 2486D 03 02 AMEL Added errata for Rev D E and F on page 296 Changed the Endurance on the Flash to 10 000 Write Erase Cycles Updated Table 103 ADC Characteris
214. e A transmission basically consists of a START condition a SLA R W one or more data packets and a STOP condition An empty message consisting of a START followed by a STOP condition is illegal Note that the Wired ANDing of the SCL line can be used to implement handshaking between the Master and the Slave The Slave can extend the SCL low period by pulling the SCL line low This is useful if the clock speed set up by the Master is too fast for the Slave or the Slave needs extra time for processing between the data transmissions The Slave extending the SCL low period will not affect the SCL high period which is determined by the Master As a consequence the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle Figure 73 shows a typical data transmission Note that several data bytes can be trans mitted between the SLA R W and the STOP condition depending on the software protocol implemented by the application software Figure 73 Typical Data Transmission Addr MSB Addr LSB RW ACK Data MSB Data LSB ACK ON S S v SAN X X XXX BR b 4 sc E E 1 2 7 8 9 1 2 7 8 9 2 START SLA R W Data Byte STOP 16 ATmegae8 L SESEEEooo oM i 2486R AVR 07 07 AT 11 C025 Multi master Bus The TWI protocol allows bus systems with several masters Special concerns have Systems Arbitration and been taken in order to ensure that transmissions
215. e free Brown out Detection The hysteresis on the detection level should be interpreted as Vaor Vgor VhysT 2 and Vgor Veor Viysr 2 The BOD circuit can be enabled disabled by the fuse BODEN When the BOD is enabled BODEN programmed and Vcc decreases to a value below the trigger level Vgor in Figure 18 the Brown out Reset is immediately activated When Voc increases above the trigger level Vgoz in Figure 18 the delay counter starts the MCU after the time out period troyr has expired The BOD circuit will only detect a drop in Vec if the voltage stays below the trigger level for longer than tgop given in Table 15 Figure 18 Brown out Reset During Operation INTERNAL RESET 40 ATlmega8 L sume 2486R AVR 07 07 X X A mega8 L Watchdog Reset MCU Control and Status Register MCUCSR 2486R AVR 07 07 When the Watchdog times out it will generate a short reset pulse of 1 CK cycle dura tion On the falling edge of this pulse the delay timer starts counting the time out period trout Refer to page 43 for details on operation of the Watchdog Timer Figure 19 Watchdog Reset During Operation Vcc RESET gt i 1 CK Cycle WDT TIME OUT l i 1 lt t RESET et MJ TIME OUT i 1 INTERNAL RESET The MCU Control and Status Register provides information on which reset source caused an MCU Reset Bit 7 6 5 4 3 2 1 0 EUREN Torr sor extar Ponr wcucsn Read Wri
216. e 102 on page 246 Updated Programming Figures Figure 104 on page 226 and Figure 112 on page 237 are updated to also reflect that AVcc must be connected during Programming mode Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Disabled or if External Oscillators are Selected Added a note in section Enter Programming Mode on page 228 AMEL 301 AMEL 302 ATmega8 L memm Table of Contents 2486R AVR 07 07 qj T 1 PIN Configurations C 2 1717 E sessed 3 Block Diagrams icta ic E atr m ak a p LO ene 3 BIETET E 4 PiniBescriptions te tr E E PUE eei IE espe 5 FOS OUNCES eT 7 About Code EXAmpIGB iiie ia setae eran an aa aliis rer oUE aka Pulsa axe yvu needs eade hdd 8 AVR CPU CONG ense ederet teda n vi utut poU ed candid 9 WME CU CUO IA prm 9 Architectural Overview nennen nennen nnne trennen enters 9 Arithmetic Logic Unit ALU seesseeseeeeeennne enne 11 Status Register eed eei x EH Fue as TEE va Ug rece xe Maan heed 11 General Purpose Register File ssssssssseeeeenneeeneennenn 12 Stack Pointer deme eI ae SER pan sus REPE EA OEE A ERN ER ESETE 13 Instruction Execution TMN sssr kn naine EREA n EESE 14 Reset and Interrupt Handling essen 14 AVA ATmega8 Memories iisiusess i
217. e TWINT bit in TWCR is set Immediately after the application has cleared TWINT the TWI will initiate transmission of the data packet 6 When the data packet has been transmitted the TWINT Flag in TWCR is set and TWSR is updated with a status code indicating that the data packet has suc cessfully been sent The status code will also reflect whether a Slave acknowledged the packet or not 7 The application software should now examine the value of TWSR to make sure that the data packet was successfully transmitted and that the value of the ACK bit was as expected If TWSR indicates otherwise the application software might take some special action like calling an error routine Assuming that the status code is as expected the application must write a specific value to TWCR instructing the TWI hardware to transmit a STOP condition Which value to write is described later on However it is important that the TWINT bit is set in the value written Writing a one to TWINT clears the flag The TWI will not start any operation as long as the TWINT bit in TWCR is set Immediately after the appli cation has cleared TWINT the TWI will initiate transmission of the STOP condition Note that TWINT is NOT set after a STOP condition has been sent Even though this example is simple it shows the principles involved in all TWI transmis sions These can be summarized as follows e When the TWI has finished an operation and expects application response
218. e a logic 0 This majority voting process acts as a low pass filter for the incoming signal on the RxD pin The recovery process is then repeated until a complete frame is received Including the first stop bit Note that the Receiver only uses the first stop bit of a frame Figure 67 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame 1483 ATmega8 L mmm 2486R AVR 07 07 ATmega8 L Figure 67 Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 A 8 C E l tttttt U2X 0 1 Sample PANT U2X 1 1 oP o The same majority voting is done to the stop bit as done for the other bits in the frame If the stop bit is registered to have a logic 0 value the Frame Error FE Flag will be set A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting For Normal Speed mode the first low level sample can be at point marked A in Figure 67 For Double Speed mode the first low level must be delayed to B C marks a stop bit of full length The early start bit detec tion influences the operational range of the Receiver Asynchronous Operational The operational range of the Receiver is dependent on the mismatch between the Range received bit rate and the internally generated baud rate If the Transmitter is sending frames at too fast or
219. e received and ACK will be returned 0x70 General call address has been No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be received ACK has been returned returned No TWDR action X 0 1 1 Data byte will be received and ACK will be returned 0x78 Arbitration lost in SLA R W as No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be Master General call address has returned been received ACK has been No TWDR action X 0 1 1 Data byte will be received and ACK will be returned returned 0x80 Previously addressed with own Read data byte or X 0 1 0 Data byte will be received and NOT ACK will be SLA W data has been received returned ACK has been returned Read data byte 0 1 1 Data byte will be received and ACK will be returned 0x88 Previously addressed with own Read data byte or 0 0 1 0 Switched to the not addressed Slave mode SLA W data has been received no recognition of own SLA or GCA NOT ACK has been returned Read data byte or 0 0 1 1 Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 Read data byte or 1 0 1 0 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free Read data byte 1 0 1 1 Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the bus becomes free 0x90 P
220. e small n in the regis ter and bit names indicates the device number n 1 for Timer Counter 1 and the x indicates Output Compare unit A B The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded Figure 35 Output Compare Unit Block Diagram DATA BUS e bit TEMP 8 bit TCNTnH 8 bit TCNTnL 8 bit PY OCRnxH Buf 8 bit OCRnxL Buf 8 bit OCRnx Buffer 16 bit Register Hd n MCN NENNEN OCRnxH 8 bit OCRnxL 8 bit TCNTn 16 bit Counter OCRnx 16 bit Register 16 bit Comparator OCFnx Int Req Waveform Generator WGMn3 0 COMnx1 0 TOP BOTTOM The OCR1x Register is double buffered when using any of the twelve Pulse Width Mod ulation PWM modes For the normal and Clear Timer on Compare CTC modes of operation the double buffering is disabled The double buffering synchronizes the AMEL ss Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit AMEL update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence The synchronization prevents the occurrence of odd length non symmetrical PWM pulses thereby making the output glitch free The OCR1x Register access may seem complex but this is not case When the double buffering is enabled the CPU has access to the OCR1x Buffer Register and if double buffering is di
221. e the following in mind As a chip erased device contains OxFF in all locations programming of addresses that are meant to contain OxFF can be skipped This does not apply if the EEPROM is Re programmed without chip erasing the device In this case data polling cannot be used for the value OxFF and the user will have to wait at least twp ceEpRom before programming the next byte See Table 97 for tw eeprom value Table 97 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay lwp FUsE 4 5 ms lwp FLASH 4 5 ms lwp EEPROM 9 0 ms lwp ERASE 9 0 ms Figure 113 Serial Programming Waveforms eee fas X X XC OCC OG aarti week Ju 1 M M LSB SERIAL CLOCK INPUT SCK SAMPLE i A A A aA A AMEL 239 Table 98 Serial Programming Instruction Set AMEL Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 XXXX XXXX XXXX XXXX Enable Serial Programming after RESET goes low Chip Erase 1010 1100 100x xxxx XXXX XXXX xxxx xxxx Chip Erase EEPROM and Flash Read Program Memory 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H high or low data o from Program memory at word address a b Load Program Memory 0100 H000 0000 xxxx xxxb bbbb iiii iiii Write H high or low data i to Pa
222. ed in separate control registers If the Global Interrupt Enable Register is cleared none of the interrupts are enabled independent of the individual interrupt enable settings The I bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts The I bit can also be set and cleared by the application with the SEI and CLI instructions as described in the Instruction Set Reference e Bit 6 T Bit Copy Storage The Bit Copy instructions BLD Bit LoaD and BST Bit STore use the T bit as source or destination for the operated bit A bit from a register in the Register File can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction e Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry is useful in BCD arithmetic See the Instruction Set Description for detailed information e Bit4 S Sign Bit S N V The S bit is always an exclusive or between the Negative Flag N and the Two s Comple ment Overflow Flag V See the Instruction Set Description for detailed information Bit 3 V Two s Complement Overflow Flag The Two s Complement Overflow Flag V supports two s complement arithmetics See the Instruction Set Description for detailed information e Bit 2 N Negative Flag The Negative Flag N indicates a negative result
223. eeeeeeeeee 191 Analog COmpDSFSIOE uae dehienabia a akon UAR RARE RE KEIRA 193 Analog Comparator Multiplexed Input sesessseeeeeeene 195 Analog to Digital Converter eee esee esee enne nnn nnn 196 E N se 196 Starting aA COnWerSIOn cocto oit d e caia pre ep d eee ERE d 198 Prescaling and Conversion Timing 198 Changing Channel or Reference Selection ssssssesess 200 ADC Noise Canceler essssssssssseeeeeeeeeen nennen enne 201 ADC Conversion Result nennen nnne nnne nnns 205 AMEL iii AMEL Boot Loader Support Read While Write Self Programming 209 Boot Loader Features sessssssesssseeeeee eene nennen nennen nnne 209 Application and Boot Loader Flash Sections sssssseessss 209 Read While Write and No Read While Write Flash Sections 209 Boot Loader Lock Bits iue tom HERE Ge eee eee 211 Entering the Boot Loader Program seen 212 Addressing the Flash During Self Programming seeessss 214 Self Programming the Flash sesssssssseseseeeeeeeeneeeneeennenn nnne 215 Memory Programining ueeesssu ione o a nate aaa a a napa ey sys s kd avus aereas eiiis 222 Program And Data Memory Lock Bits essseeeeeeenn 222 git yaicsp c A OORO 223 Signature Bytes terio rete eer ditte d etia t
224. en a reset condition becomes active even if no clocks are running If PORTxn is written logic one when the pin is configured as an output pin the port pin is driven high one If PORTxn is written logic zero when the pin is configured as an out put pin the port pin is driven low zero 52 ATmega8 L memm 2486R AVR 07 07 X f mega8 L Reading the Pin Value 2486R AVR 07 07 When switching between tri state DDxn PORTxn 0b00 and output high DDxn PORTxn 0b11 an intermediate state with either pull up enabled DDxn PORTxn 0b01 or output low DDxn PORTxn 0610 must occur Normally the pull up enabled state is fully acceptable as a high impedant environment will not notice the dif ference between a strong high driver and a pull up If this is not the case the PUD bit in the SFIOR Register can be set to disable all pull ups in all ports Switching between input with pull up and output low generates the same problem The user must use either the tri state DDxn PORTxn 0b00 or the output high state DDxn PORTxn 0b11 as an intermediate step Table 20 summarizes the control signals for the pin value Table 20 Port Pin Configurations DDxn PORTxn in SHOR yo Pull up Comment 0 0 X Input No Tri state Hi Z 0 4 0 Input Yes ae current if external 0 1 1 Input No Tri state Hi Z 1 0 X Output No Output Low Sink 1 1 X Output No O
225. enerate a START condition as soon as the bus becomes free After a START condition has been transmit ted the TWINT Flag is set by hardware and the status code in TWSR will be Ox08 see Table 66 In order to enter MT mode SLA W must be transmitted This is done by writ ing SLA W to TWDR Thereafter the TWINT bit should be cleared by writing it to one to continue the transfer This is accomplished by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 0 0 X 1 0 X When SLA W have been transmitted and an acknowledgement bit has been received TWINT is set again and a number of status codes in TWSR are possible Possible sta tus codes in Master mode are 0x18 0x20 or 0x38 The appropriate action to be taken for each of these status codes is detailed in Table 66 When SLA W has been successfully transmitted a data packet should be transmitted This is done by writing the data byte to TWDR TWDR must only be written when TWINT is high If not the access will be discarded and the Write Collision bit TWWC will be set in the TWCR Register After updating TWDR the TWINT bit should be cleared by writing it to one to continue the transfer This is accomplished by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 0 0 X 1 0 X AMEL 179 AMEL This scheme is repeated until the last byte
226. eneration unit The OC1A OC1B output is changed according to its COM1x1 0 bits set ting Note that the FOC1A FOC1B bits are implemented as strobes Therefore it is the value present in the COM1x1 0 bits that determine the effect of the forced compare A FOC1A FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match CTC mode using OCR1A as TOP The FOC1A FOC1B bits are always read as zero Bit 1 0 WGM11 0 Waveform Generation Mode 98 ATmega8 L memm 2486R AVR 07 07 f mega8 L Combined with the WGM13 2 bits found in the TCCR1B Register these bits control the counting sequence of the counter the source for maximum TOP counter value and what type of waveform generation to be used see Table 39 Modes of operation sup ported by the Timer Counter unit are Normal mode counter Clear Timer on Compare Match CTC mode and three types of Pulse Width Modulation PWM modes See Modes of Operation on page 88 Table 39 Waveform Generation Mode Bit Description WGM12 WGM11 WGM10 Timer Counter Mode of Update of TOV1 Flag Mode WGM13 CTC1 PWM11 PWM10 Operation TOP OCR1x Set on 0 0 0 0 0 Normal OxFFFF Immediate MAX 1 0 0 0 1 PWM Phase Correct 8 bit OxOOFF TOP BOTTOM 2 0 0 1 0 PWM Phase Correct 9 bit OxO1FF TOP BOTTOM 3 0 0 1 1 PWM Phase Correct 10 bit OxOSFF
227. equencies R ko C pF f 33 22 650 kHz 10 22 2 0 MHz Notes 1 R should be in the range 3 kQ 100 kQ and C should be at least 20 pF The C values given in the table includes pin capacitance This will vary with package type 2 The frequency will vary with package type and board layout 24 ATmega8 L mmm 2486R AVR 07 07 A megae8 L Two wire Serial Interface Characteristics Table 101 describes the requirements for devices connected to the Two wire Serial Bus The ATmega8 Two wire Serial Interface meets or exceeds these requirements under the noted conditions Timing symbols refer to Figure 115 Table 101 Two wire Serial Bus Requirements Symbol Parameter Condition Min Max Units Viu Input Low voltage 0 5 0 3 Vec V Vin Input High voltage 0 7 Vec Voc 0 5 V Vays Hysteresis of Schmitt Trigger Inputs 0 05 Vo V VoL Output Low voltage 3 mA sink current 0 0 4 V AD Rise Time for both SDA and SCL 20 0 10 9 300 ns to Output Fall Time from Vy to ViLmax 10 pF lt C lt 400 pF 20 0 10 9 250 ns tsp Spikes Suppressed by Input Filter 0 502 ns l Input Current each I O Pin 0 1Vcc lt Vj lt 0 9Vcc 10 10 pA c Capacitance for each I O Pin 10 pF feo SCL Clock Frequency fox gt max 16fgc 250kHz 0 400 kHz fac lt 100 kHz Voc 0 4V 1000ns o 3mA C Rp
228. er Features Power on Reset and Programmable Brown out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes Idle ADC Noise Reduction Power save Power down and Standby I O and Packages 23 Programmable I O Lines 28 lead PDIP 32 lead TQFP and 32 pad QFN MLF Operating Voltages 2 7 5 5V ATmega8L 4 5 5 5V ATmega8 Speed Grades 0 8 MHz ATmega8L 0 16 MHz ATmega8 Power Consumption at 4 Mhz 3V 25 C Active 3 6 mA Idle Mode 1 0 mA Power down Mode 0 5 pA Notes 1 At 85 C Guaranteed after last write cycle 2 Failure rate less than 1 ppm 3 Characterized through accelerated tests 2486R AVR 07 07 AMEL EE dpi Pin Configurations ATmega8 L AMEL PDIP RESET PC6 1 28 PC5 ADC5 SCL RXD PDOL 2 27 O PC4 ADC4 SDA TXD PD1 O 3 26 PC3 ADC3 INTO PD2 O 4 25 0 PC2 ADC2 INT1 PD3 5 24 PC1 ADC1 XCK TO PD4 C 6 23 PCO ADCO vcc 7 22 GND GND 48 21 O AREF XTAL1 TOSC1 PB6 9 20 O AVCC XTAL2 TOSC2 PB7 10 19 L1 PB5 SCK T1 PD5 E 11 1
229. eration described previously also applies in this case AMEL a Timer Counter Clock Sources Counter Unit AMEL The Timer Counter can be clocked by an internal or an external clock source The clock source is selected by the clock select logic which is controlled by the clock select CS12 0 bits located in the Timer Counter Control Register B TCCR1B For details on clock sources and prescaler see Timer CounterO and Timer Counter1 Prescalers on page 74 The main part of the 16 bit Timer Counter is the programmable 16 bit bi directional counter unit Figure 33 shows a block diagram of the counter and its surroundings Figure 33 Counter Unit Block Diagram DATA BUS eit TOVn Int Req TEMP 8 bit Edge Detector From Prescaler TCNTnH 8 bit TCNTnL 8 bit TCNTn 16 bit Counter Control Logic BOTTOM Signal description internal signals count Increment or decrement TCNT1 by 1 direction Select between increment and decrement clear Clear TCNT1 set all bits to zero clk Timer Counter clock TOP Signalize that TCNT1 has reached maximum value BOTTOM Signalize that TCNT1 has reached minimum value zero The 16 bit counter is mapped into two 8 bit I O memory locations counter high TCNT1H containing the upper eight bits of the counter and Counter Low TCNT1L containing the lower eight bits The TCNT1H Register can only be indirectly accessed
230. es are used the Transmitter must be set to use two stop bit USBS 1 since the first stop bit is used for indicating the frame type Do not use Read Modify Write instructions SBI and CBI to set or clear the MPCM bit The MPCM bit shares the same I O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions AMEL 151 Accessing UBRRH UCSRC Registers Write Access AMEL The UBRRH Register shares the same I O location as the UCSRC Register Therefore some special consideration must be taken when accessing this I O location When doing a write access of this I O location the high bit of the value written the USART Register Select URSEL bit controls which one of the two registers that will be written If URSEL is zero during a write operation the UBRRH value will be updated If URSEL is one the UCSRC setting will be updated The following code examples show how to access the two registers Assembly Code Examples Set UBRRH to 2 1dir16 0x02 out UBRRH r16 Set the USBS and the UCSZ1 bit to one and the remaining bits to zero ldi r16 1 lt lt URSEL 1 lt lt USBS 1 UCSZ1 out UCSRC r16 C Code Examples Set UBRRH to 2 UBRRH 0x02 Set the USBS and the UCSZ1 bit to one and the remaining bits to zero UCSRC 1 lt lt URSEL 1 lt lt USBS 1 lt lt UCSZ1 Note 1 See About Code Examples o
231. es the fast PWM mode well suited for power regulation rectification and DAC applications High frequency allows physically small sized external components coils capacitors and therefore reduces total system cost In fast PWM mode the counter is incremented until the counter value matches the MAX value The counter is then cleared at the following timer clock cycle The timing diagram for the fast PWM mode is shown in Figure 50 The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2 OCRn Update 4 4 and i TOVn Interrupt Flag Set Figure 50 Fast PWM Mode Timing Diagram Td m a TCNTn L 14 OCn COMn1 0 2 OCn COMn1 0 3 Period 1 re 2 gt 3 gt 4 gt __ 5 P 6 9 7 The Timer Counter Overflow Flag TOV2 is set each time the counter reaches MAX If the interrupt is enabled the interrupt handler routine can be used for updating the com pare value In fast PWM mode the compare unit allows generation of PWM waveforms on the OC2 pin Setting the COM21 0 bits to 2 will produce a non inverted PWM and an inverted PWM output can be generated by setting the COM21 0 to 3 see Table 44 on page 118 The actual OC2 va
232. escription on page 72 Figure 26 8 bit Timer Counter Block Diagram TOVn Int Req gt Edge Detector From Prescaler DATA BUS Timer Counter The Timer Counter TCNTO is an 8 bit register Interrupt request abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFR All interrupts are individually masked with the Timer Interrupt Mask Register TIMSK TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units The Timer Counter can be clocked internally or via the prescaler or by an external clock Source on the TO pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment its value The Timer Counter is inactive when no clock source is selected The output from the clock select logic is referred to as the timer clock clky9 Many register and bit references in this document are written in general form A lower case n replaces the Timer Counter number in this case 0 However when using the register or bit defines in a program the precise form must be used i e TCNTO for accessing Timer CounterO counter value and so on The definitions in Table 33 are also used extensively throughout this datasheet Table 33 Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes OxFF decimal
233. ess Low byte C Load Data Low byte 1 Set XA1 XAO to 01 This enables data loading 2 Set DATA Data Low byte 0x00 OxFF 3 Give XTAL1 a positive pulse This loads the data byte D Load Data High byte 1 Set BS1 to 1 This selects high data byte 2 Set XA1 XAO to 01 This enables data loading 3 Set DATA Data High byte 0x00 OxFF 4 Give XTAL1 a positive pulse This loads the data byte E Latch Data 1 Set BS1 to 1 This selects high data byte 2 Give PAGEL a positive pulse This latches the data bytes See Figure 106 for signal waveforms F Repeat B through E until the entire buffer is filled or until all data within the page is loaded While the lower bits in the address are mapped to words within the page the higher bits address the pages within the FLASH This is illustrated in Figure 105 on page 230 Note that if less than eight bits are required to address words in the page pagesize 256 the most significant bit s in the address Low byte are used to address the page when performing a page write G Load Address High byte 1 Set XA1 XAO to 00 This enables address loading 2 Set BS1 to 1 This selects high address 3 Set DATA Address High byte 0x00 OxFF 4 Give XTAL1 a positive pulse This loads the address High byte H Program Page AMEL 229 2486R AVR 07 07 AMEL 1 Set BS1 0 2 Give WR a negative pulse This starts programmin
234. ess of the setting of the DDxn PORTxn and PUD Register bits DDOE Data Direction Override Enable If this signal is set the Output Driver Enable is controlled by the DDOV signal If this signal is cleared the Output driver is enabled by the DDxn Register bit DDOV Data Direction Override Value If DDOE is set the Output Driver is enabled disabled when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled the port value is controlled by the PVOV signal If PVOE is cleared and the Output Driver is enabled the port Value is controlled by the PORTxn Register bit PVOV Port Value Override Value If PVOE is set the port value is set to PVOV regardless of the setting of the PORTxn Register bit DIEOE Digital Input Enable Override Enable If this bit is set the Digital Input Enable is controlled by the DIEOV signal If this signal is cleared the Digital Input Enable is determined by MCU state Normal mode sleep modes DIEOV Digital Input Enable Override Value If DIEOE is set the Digital Input is enabled disabled when DIEOV is set cleared regardless of the MCU state Normal mode sleep modes DI Digital Input This is the Digital Input to alternate functions In the figure the signal is connected to the output of the schmitt trigger but before the synchronizer Un
235. ette este rae 225 Calibration Byte ssssssssssssseeeseeeennenennenenn nennen nennen nnns nnns nnne 225 xe 225 Parallel Programming Parameters Pin Mapping and Commands 226 Parallel Programming sossarna E nennen nennen nnne 228 Serial Downloading sssri ceairde n cr ee idc ed eee Erga 237 Serial Programming Pin Mapping eesseeseeeeeeeeennenennnen nnn 237 Electrical Charaeteristies uuiiisiissiiaei si didis pd pad naar andas 242 Absolute Maximum Ratings eesssssseeeeeeeennn eene 242 DC Characteristics isng niniin decet tette sir eter ta eco e Dee End 242 External Clock Drive Waveforms ssessssseeeeeeeeeeenennnenn nens 244 External ClOGK dB 244 Two wire Serial Interface Characteristics sessssseseeeeese 245 SPI Timing Characteristics sssssssseseseeeeneneeee nennen 246 ADC Characteristics esssssssssseseeseeeeeeeneeee nennen nennen nnns 248 ATmega8 Typical Characteristics eeeeeseseeee 249 Register Summary esee esses eese e sees ean a ananas ansa aaa an nnn nn nau uuu 287 Instruction Set SUummaty 2 uoocu earn sx xs sra syYv nop auekexo teu U iiaia 289 Ordering Inform ealiOl needs atuu eua acaa Mapas c kx t UEE RR RE ER d 292 Packaging Information iussisti raus ad kuxu mn
236. f the AVR core Examples of such modules are the General Purpose Register File the Status Reg ister and the Data memory holding the Stack Pointer Halting the CPU clock inhibits the core from performing general operations and calculations The I O clock is used by the majority of the I O modules like Timer Counters SPI and USART The I O clock is also used by the External Interrupt module but note that some external interrupts are detected by asynchronous logic allowing such interrupts to be detected even if the I O clock is halted Also note that address recognition in the TWI module is carried out asynchronously when clk o is halted enabling TWI address recep tion in all sleep modes The Flash clock controls operation of the Flash interface The Flash clock is usually active simultaneously with the CPU clock AMEL a Asynchronous Timer Clock clKasy Clock Sources AMEL The Asynchronous Timer clock allows the Asynchronous Timer Counter to be clocked directly from an external 32 kHz clock crystal The dedicated clock domain allows using this Timer Counter as a real time counter even when the device is in sleep mode The Asynchronous Timer Counter uses the same XTAL pins as the CPU main clock but requires a CPU main clock frequency of more than four times the Oscillator frequency Thus asynchronous operation is only available while the chip is clocked on the Internal Oscillator The ADC is provided with a dedicated clock
237. fast PWM mode is shown in Figure 38 The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP The TCNT1 value is in the timing diagram shown as a histogram for illus trating the single slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1 The OC1x Interrupt Flag will be set when a Com pare Match occurs Figure 38 Fast PWM Mode Timing Diagram OCRnx TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set Interrupt on TOP TCNTn OCnx COMnx1 0 2 OCnx COMnx1 0 3 Period 1 rl 2 re 3 de 4 P45 6 1 7 8 The Timer Counter Overflow Flag TOV1 is set each time the counter reaches TOP In addition the OCF1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value If one of the interrupts are enabled the interrupt handler routine can be used for updating the TOP and com pare values When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers If the TOP value is lower than any of the Compare Registers a Compare Match will never occur between the TCNT1 and the OCR1x Note that when using fixed TOP values the unused bits are masked to zero
238. feature which allows the user software to first read the page do the necessary changes and then write back the modified data If alternative 2 is used it is not possible to read the old data while loading since the page is already erased The temporary page buffer can be accessed in a random sequence It is essential that the page address used in both the page erase and page write operation is addressing the same page See Simple AMEL 215 2486R AVR 07 07 Performing Page Erase by SPM Filling the Temporary Buffer Page Loading Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self Programming AMEL Assembly Code Example for a Boot Loader on page 219 for an assembly code example To execute page erase set up the address in the Z pointer write X0000011 to SPMCR and execute SPM within four clock cycles after writing SPMCR The data in R1 and RO is ignored The page address must be written to PCPAGE in the Z register Other bits in the Z pointer will be ignored during this operation e Page Erase to the RWW section The NRWW section can be read during the page erase e Page Erase to the NRWW section The CPU is halted during the operation To write an instruction word set up the address in the Z pointer and data in R1 RO write 00000001 to SPMCR and execute SPM within four clock cycles after writing SPMCR The content of PCWOR
239. fer to the section Boot Loader Support Read While Write Self Programming on page 209 for details To avoid unin tentional changes of Interrupt Vector tables a special write procedure must be followed to change the IVSEL bit 1 Write the Interrupt Vector Change Enable IVCE bit to one 2 Within four cycles write the desired value to IVSEL while writing a zero to IVCE Interrupts will automatically be disabled while this sequence is executed Interrupts are disabled in the cycle IVCE is set and they remain disabled until after the instruction fol lowing the write to IVSEL If IVSEL is not written interrupts remain disabled for four cycles The I bit in the Status Register is unaffected by the automatic disabling Note If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLBO2 is programmed interrupts are disabled while executing from the Application section If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro gramed interrupts are disabled while executing from the Boot Loader section Refer to the section Boot Loader Support Read While Write Self Programming on page 209 for details on Boot Lock Bits AMEL s 2486R AVR 07 07 50 AMEL Bit 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit IVCE is cleared by hardware four cycles after it is written or when IVSEL is written Setting the
240. g Enable instruction Whether the echo is correct or not all four bytes of the instruction must be transmitted If the 0x53 did not echo back give RESET a positive pulse and issue a new Programming Enable command 4 The Flash is programmed one page at a time The page size is found in Table 89 on page 225 The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction To ensure correct loading of the page the data Low byte must be loaded before data High byte is applied for a given address The Program mem ory Page is stored by loading the Write Program memory Page instruction with the 7 MSB of the address If polling is not used the user must wait at least twp ri Asu before issuing the next page See Table 97 Note If other commands than polling read are applied before any write operation FLASH EEPROM Lock Bits Fuses is completed it may result in incorrect programming 5 The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction An EEPROM memory location is first automatically erased before new data is written If polling is not used the user must wait at least twp eeprom before issuing the next byte See Table 97 on page 239 In a chip erased device no OxFFs in the data file s need to be programmed 6 Any memory location can be verified by using the Read instructi
241. g of the entire page of data RDY BSY goes low 3 Wait until RDY BSY goes high See Figure 106 for signal waveforms Repeat B through H until the entire Flash is programmed or until all data has been programmed J End Page Programming 1 Set XA1 XAO to 10 This enables command loading 2 Set DATA to 0000 0000 This is the command for No Operation 3 Give XTAL1 a positive pulse This loads the command and the internal write sig nals are reset Figure 105 Addressing the Flash which is Organized in Pages PROGRAM PCMSB PAGEMSB COUNTER PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD PAGEMSB 0 00 INSTRUCTION WORD 01 02 PAGEEND Note 1 PCPAGE and PCWORD are listed in Table 89 on page 225 230 ATmega8 L mmm 2486R AVR 07 07 w AT 11 C025 Figure 106 Programming the Flash Waveforms F SS A B Cc D E B Cc D E G H 0x10 ADDR LOWX DATA LOW X DATA HIGH XX ADDR LOW DATA LOW X DATA HIGH XX ADDR HIGH XX XTAL1 E m JL WR _ RDY BSY RESET 12V Note 1 XX is don t care The letters refer to the programming description above Programming the EEPROM The EEPROM is organized in pages see Table 90 on page 225 When programming the EEPROM the program data is latched into a page buffer This allows one page of data to
242. gain or a new Slave without transmitting a STOP condition Repeated START enables the Master to switch between Slaves Master Transmitter mode and Master Receiver mode without losing control over the bus Table 67 Status codes for Master Receiver Mode Status Code Application Software Response TWSR Status of the Two wire Serial To TWCR Prescaler Bits Bus and Two wire Serial Inter to from TWDR are 0 face Hardware STA STO TWINT TWEA Next Action Taken by TWI Hardware 0x08 A START condition has been Load SLA R 0 0 1 X SLA R will be transmitted transmitted ACK or NOT ACK will be received 0x10 A repeated START condition Load SLA R or 0 0 1 X SLA R will be transmitted has been transmitted ACK or NOT ACK will be received Load SLA W 0 0 1 X SLA W will be transmitted Logic will switch to Master Transmitter mode 0x38 Arbitration lost in SLA R or NOT No TWDR action or 0 0 1 X Two wire Serial Bus will be released and not addressed ACK bit Slave mode will be entered No TWDR action 1 0 1 X A START condition will be transmitted when the bus becomes free 0x40 SLA R has been transmitted No TWDR action or 0 0 1 0 Data byte will be received and NOT ACK will be ACK has been received returned No TWDR action 0 0 1 1 Data byte will be received and ACK will be returned 0x48 SLA R has been transmitted No TWDR action or 1 0 1 X Repeated START will be transmitted NOT ACK has been received No TWDR action
243. ge Program memory page at word address b Data Low byte must be loaded before Data High byte is applied within the same address Write Program Memory 0100 1100 0000 aaaa bbbb xxxx xxxx xxxx Write Program memory Page at Page address a b Read EEPROM Memory 1010 0000 00xx xxxa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a b Write EEPROM Memory 1100 0000 00xx xxxa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a b Read Lock Bits 0101 1000 0000 0000 XXXX XXXX xxoo oooo Read Lock Bits 0 programmed 1 unprogrammed See Table 85 on page 222 for details Write Lock Bits 1010 1100 111x xxxx XXXX XXXX llii iiii Write Lock Bits Set bits 0 to program Lock Bits See Table 85 on page 222 for details Read Signature Byte 0011 0000 OOxx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b Write Fuse Bits 1010 1100 1010 0000 XXXX XXXX iiii iiii Set bits 0 to program 1 to unprogram See Table 88 on page 224 for details Write Fuse High Bits 1010 1100 1010 1000 XXXX XXXX iiii iiii Set bits 0 to program 1 to unprogram See Table 87 on page 223 for details Read Fuse Bits 0101 0000 0000 0000 XXXX XXXX oooo oooo Read Fuse Bits 0 programmed 1 unprogrammed See Table 88 on page 224 for details Read Fuse High Bits 0101 1000 0000 1000 XXXX XXXX oooo oooo Read Fuse high bits 0 pro grammed 1 unprogrammed See Table 87 on page 223 for detai
244. gister contains control bits for power management Bit 7 6 5 4 3 2 1 0 Ts sui sm T scr cw cor sco cuca Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed To avoid the MCU entering the sleep mode unless it is the programmer s purpose it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction Bits 6 4 SM2 0 Sleep Mode Select Bits 2 1 and 0 These bits select between the five available sleep modes as shown in Table 13 Table 13 Sleep Mode Select SM2 SM1 SMO Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 0 1 0 Power down 0 1 1 Power save 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby Note 1 Standby mode is only available with external crystals or resonators AMEL s Idle Mode ADC Noise Reduction Mode Power down Mode Power save Mode AMEL When the SM2 0 bits are written to 000 the SLEEP instruction makes the MCU enter Idle mode stopping the CPU but allowing SPI USART Analog Comparator ADC Two wire Serial Interface Timer Counters Watchdog and the interrupt system to continue operating This sleep mode basically halts clkgpy and clke_asy while allowing the other clocks to run Idle mode enables the MCU to wake up from external triggered i
245. gnored The SPMEN bit will auto clear upon completion of an SPM instruction or if no SPM instruction is executed within four clock cycles During page erase and page write the SPMEN bit remains high until the operation is completed Writing any other combination than 10001 01001 00101 00011 or 00001 in the lower five bits will have no effect The Z pointer is used to address the SPM commands Bit 15 14 13 12 11 10 9 8 wew a es ee T 29 75 ZL R30 Ca a RN RE RN RR RR RN 7 6 5 4 3 2 1 0 Since the Flash is organized in pages see Table 89 on page 225 the Program Counter can be treated as having two different sections One section consisting of the least sig nificant bits is addressing the words within a page while the most significant bits are addressing the pages This is shown in Figure 103 Note that the page erase and page write operations are addressed independently Therefore it is of major importance that the Boot Loader software addresses the same page in both the page erase and page write operation Once a programming operation is initiated the address is latched and the Z pointer can be used for other operations The only SPM operation that does not use the Z pointer is Setting the Boot Loader Lock Bits The content of the Z pointer is ignored and will have no effect on the operation The LPM instruction does also use the Z pointer to store the address Since this instruction addresses the Fla
246. has been sent and the transfer is ended by generating a STOP condition or a repeated START condition A STOP condition is gen erated by writing the following value to TWCR TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 0 A REPEATED START condition is generated by writing the following value to TWCR TWCR 1 X 1 0 X TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE value 1 X 1 0 X 1 0 X After a repeated START condition state 0x10 the Two wire Serial Interface can access the same Slave again or a new Slave without transmitting a STOP condition Repeated START enables the Master to switch between Slaves Master Transmitter mode and Master Receiver mode without losing control of the bus Table 66 Status codes for Master Transmitter Mode Status Code Application Software Response TWSR Status of the Two wire Serial To from TWDR To TWCR Prescaler Bits Bus and Two wire Serial Inter are 0 face Hardware STA STO TWINT TWEA Next Action Taken by TWI Hardware 0x08 A START condition has been Load SLA W 0 0 1 X SLA W will be transmitted transmitted ACK or NOT ACK will be received 0x10 A repeated START condition Load SLA W or 0 0 1 X SLA W will be transmitted has been transmitted ACK or NOT ACK will be received Load SLA R 0 0 1 X SLA R will be transmitted Logic will switch to
247. hdog Timer Port Pins AMEL If the Brown out Detector is not needed in the application this module should be turned off If the Brown out Detector is enabled by the BODEN Fuse it will be enabled in all sleep modes and hence always consume power In the deeper sleep modes this will contribute significantly to the total current consumption Refer to Brown out Detection on page 40 for details on how to configure the Brown out Detector The Internal Voltage Reference will be enabled when needed by the Brown out Detec tor the Analog Comparator or the ADC If these modules are disabled as described in the sections above the internal voltage reference will be disabled and it will not be con suming power When turned on again the user must allow the reference to start up before the output is used If the reference is kept on in sleep mode the output can be used immediately Refer to Internal Voltage Reference on page 42 for details on the start up time If the Watchdog Timer is not needed in the application this module should be turned off If the Watchdog Timer is enabled it will be enabled in all sleep modes and hence always consume power In the deeper sleep modes this will contribute significantly to the total current consumption Refer to Watchdog Timer on page 43 for details on how to configure the Watchdog Timer When entering a sleep mode all port pins should be configured to use minimum power The most important thing
248. he OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at TOP The Interrupt Flags can be used to gen erate an interrupt each time the counter reaches the TOP or BOTTOM value When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers If the TOP value is lower than any of the Compare Registers a Compare Match will never occur between the TCNT1 and the OCR1x Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written As the third period shown in Figure 39 illustrates changing the TOP actively while the Timer Counter is running in the Phase Correct mode can result in an unsymmetrical output The reason for this can be found in the time of update of the OCR1x Register Since the OCR1x update occurs at TOP the PWM period starts and ends at TOP This implies that the length of the fall ing slope is determined by the previous TOP value while the length of the rising slope is determined by the new TOP value When these two values differ the two slopes of the 92 ATlmega8 L memm AT 11 C025 Phase and Frequency Correct PWM Mode 2486R AVR 07 07 period will differ in length The difference in length gives the unsymmetrical result on the output It is recommended to use the Phase and Frequency Correc
249. he Program memory has been completely erased The Fuse Bits are not changed A Chip Erase must be performed before the Flash and or the EEPROM are reprogrammed Note 1 The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is programmed Load Command Chip Erase 1 Set XA1 XAO to 10 This enables command loading Set BS1 to 0 Set DATA to 1000 0000 This is the command for Chip Erase Give XTAL1 a positive pulse This loads the command Give WR a negative pulse This starts the Chip Erase RDY BSY goes low ak woh 228 ATmega8 L memm 2486R AVR 07 07 A mega8 L 6 Wait until RDY BSY goes high before loading a new command Programming the Flash The Flash is organized in pages see Table 89 on page 225 When programming the Flash the program data is latched into a page buffer This allows one page of program data to be programmed simultaneously The following procedure describes how to pro gram the entire Flash memory A Load Command Write Flash 1 Set XA1 XAO to 10 This enables command loading 2 Set BS1 to 0 3 Set DATA to 0001 0000 This is the command for Write Flash 4 Give XTAL1 a positive pulse This loads the command B Load Address Low byte 1 Set XA1 XAO to 00 This enables address loading 2 Set BS1 to 0 This selects low address 3 Set DATA Address Low byte 0x00 OxFF 4 Give XTAL1 a positive pulse This loads the addr
250. he XCK pin is only active when using Synchronous mode Figure 62 shows a block diagram of the clock generation logic 1344 ATmega8 L mmm 2486R AVR 07 07 X X f megae8 L Internal Clock Generation The Baud Rate Generator 2486R AVR 07 07 Figure 62 Clock Generation Logic Block Diagram UBRR U2X Y fosc Prescaling UBRR 1 Down Counter 2 4 2 gt OSC txclk DDR_XCK Y y Sync Edge xcki Register Detector m k A UMSEL xcko Pin lg Y DDR XCK UCPOL rxclk Signal description txclk Transmitter clock Internal Signal rxclk Receiver base clock Internal Signal xcki Input from XCK pin internal Signal Used for synchronous slave operation xcko Clock output to XCK pin Internal Signal Used for synchronous master operation fosc XTAL pin frequency System Clock Internal clock generation is used for the asynchronous and the Synchronous Master modes of operation The description in this section refers to Figure 62 The USART Baud Rate Register UBRR and the down counter connected to it function as a programmable prescaler or baud rate generator The down counter running at sys tem clock fosc is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written A clock is generated each time the counter
251. he counter reaches the BOTTOM when it becomes 0x0000 MAX The counter reaches its MAXimum when it becomes OxFFFF decimal 65535 TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence The TOP value can be assigned to be one of the fixed values OxOOFF Ox01FF or OxOSFF or to the value stored in the OCR1A or ICR1 Register The assignment is dependent of the mode of operation Compatibility The 16 bit Timer Counter has been updated and improved from previous versions of the 16 bit AVR Timer Counter This 16 bit Timer Counter is fully compatible with the earlier version regarding e All 16 bit Timer Counter related I O Register address locations including Timer Interrupt Registers e Bit locations inside all 16 bit Timer Counter Registers including Timer Interrupt Registers e Interrupt Vectors The following control bits have changed name but have same functionality and register location e PWM10 is changed to WGM10 e PWM11 is changed to WGM11 e CTC1 is changed to WGM12 The following bits are added to the 16 bit Timer Counter Control Registers e FOC1A and FOC1B are added to TCCRIA e WGM13 is added to TCCR1B The 16 bit Timer Counter has improvements that will affect the compatibility in some special cases 78 ATmegae8 L LSS 2486R AVR 07 07 XX f mega8 L Accessing 16 bit Registers 2486R AVR 07 07 The TCNT1 OCR1A B and ICR1 are 16 bit registers tha
252. he revision letter in this section refers to the revision of the ATmega8 device First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer Signature may be Erased in Serial Programming Mode CKOPT Does not Enable Internal Capacitors on XTALn TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer Counter2 First Analog Comparator conversion may be delayed If the device is powered by a slow rising Voc the first Analog Comparator conver sion will take longer than expected on some devices Problem Fix Workaround When the device has been powered or reset disable then enable theAnalog Com parator before the first conversion Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs the interrupt may be lost Problem Fix Workaround Always check that the Timer2 Timer Counter register TCNT2 does not have the value OxFF before writing the Timer2 Control Register TCCR2 or Output Compare Register OCR2 Signature may be Erased in Serial Programming Mode If the signature bytes are read before a chiperase command is completed the sig nature may be erased causing the device ID and calibration bytes to disappear This is critical especially if the part is running on internal RC o
253. he send and receive logic and drop any partially received data in the Shift Register When the SPI is configured as a Master MSTR in SPCR is set the user can determine the direction of the SS pin If SS is configured as an output the pin is a general output pin which does not affect the SPI system Typically the pin will be driving the SS pin of the SPI Slave If SS is configured as an input it must be held high to ensure Master SPI operation If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input the SPI system interprets this as another Master selecting the SPI as a Slave and starting to send data to it To avoid bus contention the SPI system takes the following actions 1 The MSTR bit in SPCR is cleared and the SPI system becomes a Slave As a result of the SPI becoming a Slave the MOSI and SCK pins become inputs 2 The SPIF Flag in SPSR is set and if the SPI interrupt is enabled and the I bit in SREG is set the interrupt routine will be executed Thus when interrupt driven SPI transmission is used in Master mode and there exists a possibility that SS is driven low the interrupt should always check that the MSTR bit is still set If the MSTR bit has been cleared by a Slave Select it must be set by the user to re enable SPI Master mode Bit 7 6 5 4 3 2 1 0 SPIE DORD MSTR CPOL CPHA SPRI SPRO SPCR Read Write R W R W R W R W R W R W R W R W
254. his bit can be set at any time to turn off the Analog Comparator This will reduce power consumption in Active and Idle mode When changing the ACD bit the Analog Compar ator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed Bit 6 ACBG Analog Comparator Bandgap Select When this bit is set a fixed bandgap reference voltage replaces the positive input to the Analog Comparator When this bit is cleared AINO is applied to the positive input of the Analog Comparator See Internal Voltage Reference on page 42 Bit 5 ACO Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO The synchronization introduces a delay of 1 2 clock cycles e Bit4 ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACISO The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I bit in SREG is set ACI is cleared by hardware when execut ing the corresponding interrupt Handling Vector Alternatively ACI is cleared by writing a logic one to the flag e Bit 3 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I bit in the Status Register is set the Ana log Comparator interrupt is activated When written logic zero the interrupt is disabled e Bit2 ACIC Anal
255. his implies that a Stack PUSH command decreases the Stack Pointer The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter rupt Stacks are located This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled The Stack Pointer must be set to point above 0x60 The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction and it is incremented by two when address is popped from the Stack with return from subroutine RET or return from interrupt RETI The AVR Stack Pointer is implemented as two 8 bit registers in the I O space The num ber of bits actually used is implementation dependent Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed In this case the SPH Register will not be present Bit 15 14 13 12 11 10 9 8 S19 SPw Sew SP spr sro sro See SPH Ser sro spo spa SP SP Sei Seo SPL 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMEL i Instruction Execution Timing Reset and Interrupt Handling AMEL This sectio
256. ialization code can be placed directly in the main routine or be combined with initialization code for other I O modules 2486R AVR 07 07 AMEL 139 AMEL Data Transmission The The USART Transmitter is enabled by setting the Transmit Enable TXEN bit in the USART Transmitter Sending Frames with 5 to 8 Data Bits UCSRB Register When the Transmitter is enabled the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter s serial output The baud rate mode of operation and frame format must be set up once before doing any transmissions If synchronous operation is used the clock on the XCK pin will be overridden and used as transmission clock A data transmission is initiated by loading the transmit buffer with the data to be trans mitted The CPU can load the transmit buffer by writing to the UDR I O location The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame The Shift Register is loaded with new data if it is in idle state no ongoing transmission or immediately after the last stop bit of the previ ous frame is transmitted When the Shift Register is loaded with new data it will transfer one complete frame at the rate given by the Baud Register U2X bit or by XCK depend ing on mode of operation The following code examples show a simple USART transmit function based on polling of the Da
257. ibration Register 31 0x30 0x50 SFIOR ACME PUD PSR2 PSR10 58 75 123 193 Ox2F 0x4F TCCR1A COM1A1 COM1A0 COM1B1 COM1BO FOC1A FOC1B WGM 1 WGM10 97 Ox2E 0x4E TCCR1B ICNC1 ICES1 WGM13 WGM12 C812 CS11 CS10 100 Ox2D 0x4D TCNT1H Timer Counter1 Counter Register High byte 101 0x2C 0x4C TCNTIL Timer Counter1 Counter Register Low byte 101 0x2B 0x4B OCR1AH Timer Counter1 Output Compare Register A High byte 101 Ox2A 0x4A OCR1AL Timer Counter1 Output Compare Register A Low byte 101 0x29 0x49 OCR1BH Timer Counter1 Output Compare Register B High byte 101 0x28 0x48 OCR1BL Timer Counter1 Output Compare Register B Low byte 101 0x27 0x47 ICR1H Timer Counter1 Input Capture Register High byte 102 0x26 0x46 ICR1L Timer Counter1 Input Capture Register Low byte 102 0x25 0x45 TCCR2 FOC2 WGM20 COM 1 COM20 WGMe 1 CS22 CS21 CS20 117 0x24 0x44 TCNT2 Timer Counter2 8 Bits 119 0x23 0x43 OCR2 Timer Counter2 Output Compare Register 119 0x22 0x42 ASSR AS2 TCN2UB OCR2UB TCR2UB 119 0x21 0x41 WDTCR WDCE WDE WDP2 WDP1 WDPO 43 UBRRH URSEL UBRR 11 8 158 0x20 0x40 UCSRC URSEL UMSEL UPM1 UPMO USBS UCSZ1 UCSZO UCPOL 156 Ox1F 0x3F EEARH EEAR8 20 Ox1E 0x3E EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEARO 20 0x1D 0x3D EEDR EEPROM Data Register 20 0x1C 0x3C EECR EERIE EEMWE EEWE EERE 20 0x1B 0x3B Reserved 0x1A 0x3A Reserved 0x19 0x39 Reserved 0x18 0x38
258. igger level 1 unprogrammed BODEN 6 Brown out detector enable 1 unprogrammed BOD disabled SUT1 5 Select start up time 1 unprogrammed SUTO 4 Select start up time 0 programmed CKSEL3 3 Select Clock source 0 programmed CKSEL2 2 Select Clock source 0 programmed CKSEL1 1 Select Clock source 0 programmed CKSELO 0 Select Clock source 1 unprogrammed Notes 1 The default value of SUT1 0 results in maximum start up time SeeTable 10 on page 30 for details 2 The default setting of CKSEL3 0 results in internal RC Oscillator 1MHz See Table 2 on page 26 for details The status of the Fuse Bits is not affected by Chip Erase Note that the Fuse Bits are locked if lock bit1 LB1 is programmed Program the Fuse Bits before programming the Lock Bits The fuse values are latched when the device enters Programming mode and changes of the fuse values will have no effect until the part leaves Programming mode This does not apply to the EESAVE Fuse which will take effect once it is programmed The fuses are also latched on Power up in Normal mode ATmega8 L memm 2486R AVR 07 07 f 11 C025 Signature Bytes Calibration Byte Page Size 2486R AVR 07 07 All Atmel microcontrollers have a 3 byte signature code which identifies the device This code can be read in both Serial and Parallel mode also when the device is locked The three bytes reside in a separate address space
259. igned if N 6 V 0 then PC PC k 1 None 1 2 BRLT k Branch if Less Than Zero Signed if N 6 V 1 then PC PC k 1 None 1 2 BRHS Branch if Half Carry Flag Set if H 1 then PC PC k 1 None 1 2 BRHC Branch if Half Carry Flag Cleared if H 0 then PC PC k 1 None 1 2 BRTS Branch if T Flag Set if T 1 then PC PC k 1 None 1 2 BRTC Branch if T Flag Cleared if T 0 then PC PC k 1 None 1 2 BRVS Branch if Overflow Flag is Set if V 1 then PC PC k 1 None 1 2 BRVC k Branch if Overflow Flag is Cleared if V 0 then PC PO k 1 None 1 2 Mnemonics Operands Description Operation Flags Clocks AMEL 289 AMEL Instruction Set Summary Continued BRIE k Branch if Interrupt Enabled if 1 1 then PC PC k 1 None 1 2 BRID k Branch if Interrupt Disabled l 0 then PC PC k 1 None 1 2 DATA TRANSFER INSTRUCTIONS MOV Rd Rr Move Between Registers Rd Rr None 1 MOVW Rd Rr Copy Register Word Rd 1 Rd lt Rr 1 Rr None 1 LDI Rd K Load Immediate Rd K None 1 LD Rd X Load Indirec Rd lt X None 2 LD Rd X Load Indirect and Post Inc Rd lt X X X 1 None 2 LD Rd X Load Indirect and Pre Dec X lt X 1 Rd lt X None 2 LD Rd Y Load Indirec Rd lt Y
260. ill be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO Flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x38 Arbitration lost in SLA W or data No TWDR action or 0 0 1 X Two wire Serial Bus will be released and not addressed bytes Slave mode entered No TWDR action 1 0 1 X A START condition will be transmitted when the bus be comes free 180 ATmega8 L SS I 2486R AVR 07 07 ATmega8 L Figure 79 Formats and States in the Master Transmitter Mode MT Successfull T transmission S SLA QW A DATA A P to a slave receiver 08 18 28 Next transfer T started with a Rs SLA 1 Ww repeated start I condition Not acknowledge R received after the A P slave address MR Not acknowledge received after a data A P byte Arbitration lost in slave AOA Other master Other master address or data byte or continues continues LLL Arbitration lost and addressed as slave Other master continues To corresponding states in slave mode pc Any number of data bytes From master to slave DATA A and their associated acknowledge bits From slave to master Cr This number contained in TWSR corresponds to a defined state of the Two Wire Serial Bus The prescaler bits are zero or masked to zero AIMEL tei 2486R A
261. in an arithmetic or logic operation See the Instruction Set Description for detailed information Bit 1 Z Zero Flag AMEL n General Purpose Register File AMEL The Zero Flag Z indicates a zero result in an arithmetic or logic operation See the Instruction Set Description for detailed information Bit 0 C Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation See the Instruc tion Set Description for detailed information The Register File is optimized for the AVR Enhanced RISC instruction set In order to achieve the required performance and flexibility the following input output schemes are supported by the Register File e One 8 bit output operand and one 8 bit result input e Two 8 bit output operands and one 8 bit result input e Two 8 bit output operands and one 16 bit result input e One 16 bit output operand and one 16 bit result input Figure 3 shows the structure of the 32 general purpose working registers in the CPU Figure 3 AVR CPU General Purpose Working Registers 7 0 Adar 0x00 0x01 0x02 0x0D General Ox0E Purpose OxOF Working 0x10 Registers 0x11 Ox1A X register Low Byte Ox1B X register High Byte Ox1C Y register Low Byte Ox1D Y register High Byte Ox1E Z register Low Byte Ox1F Z register High Byte Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions
262. ion on page 28 Table 6 Start up Times for the Low frequency Crystal Oscillator Clock Selection on page 28 Table 8 Start up Times for the External RC Oscillator Clock Selec tion on page 29 and Table 12 Start up Times for the External Clock Selection on page 32 xo ATmega8 L memm 2486R AVR 07 07 AT 11 C025 Changes from Rev 2486B 12 01 to Rev 2486C 03 02 2486R AVR 07 07 Added ATmega8 Typical Characteristics on page 249 Updated TWI Chapter More details regarding use of the TWI Power down operation and using the TWI as Master with low TWBRR values are added into the datasheet Added the note at the end of the Bit Rate Generator Unit on page 170 Added the description at the end of Address Match Unit on page 170 Updated Description of OSCCAL Calibration Byte In the datasheet it was not explained how to take advantage of the calibration bytes for 2 4 and 8 MHz Oscillator selections This is now added in the following sections Improved description of Oscillator Calibration Register OSCCAL on page 31 and Calibration Byte on page 225 Added Some Preliminary Test Limits and Characterization Data Removed some of the TBD s in the following tables and pages Table 3 on page 26 Table 15 on page 38 Table 16 on page 42 Table 17 on page 44 T4 40 C to 85 C Voc 2 7V to 5 5V unless otherwise noted on page 242 Table 99 on page 244 and Tabl
263. ionality of the I O pin it is connected to However note that the Data Direction Reg ister DDR bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver When the OC1A or OC1B is connected to the pin the function of the COM1x1 0 bits is dependent of the WGM13 0 bits setting Table 36 shows the COM1x1 0 bit functionality when the WGM13 0 bits are set to a normal or a CTC mode non PWM Table 36 Compare Output Mode Non PWM COM1A1 COM1A0 COM1B1 COM1BO Description 0 0 Normal port operation OC1A OC1B disconnected 0 1 Toggle OC1A OC1B on Compare Match 1 0 Clear OC1A OC1B on Compare Match Set output to low level 1 1 Set OC1A OC1B on Compare Match Set output to high level AMEL 7 2486R AVR 07 07 AMEL Table 37 shows the COM1x1 0 bit functionality when the WGM13 0 bits are set to the fast PWM mode Table 37 Compare Output Mode Fast PWM COM1A1 COM1A0 COM1B1 COM1B0 Description 0 0 Normal port operation OC1A OC1B disconnected 0 1 WGM13 0 15 Toggle OC1A on Compare Match OC1B disconnected normal port operation For all other WGM1 settings normal port operation OC1A OC1B disconnected 1 0 Clear OC1A OC1B on Compare Match set OC1A OC1B at BOTTOM non inverting mode 1 1 Set OC1A OC1B on Compare Match clear OC1A OC1B at BOTTOM inverting mode Note 1 A special case occurs when OCR1A OCR1B equals TOP and COM1A1 COM1B1
264. iron ment Some initial guidelines for choosing capacitors for use with crystals are given in Table 4 For ceramic resonators the capacitor values given by the manufacturer should be used Figure 11 Crystal Oscillator Connections 2 E ET XTAL2 L 4 S 4 xr GND The Oscillator can operate in three different modes each optimized for a specific fre quency range The operating mode is selected by the fuses CKSEL3 1 as shown in Table 4 Table 4 Crystal Oscillator Operating Modes Frequency Recommended Range for Capacitors CKOPT CKSEL3 1 Range MHz C1 and C2 for Use with Crystals pF 1 101 0 4 0 9 1 110 0 9 3 0 12 22 1 111 3 0 8 0 12 22 0 101 110 111 1 0 lt 12 22 Note 1 This option should not be used with crystals only with ceramic resonators The CKSELO Fuse together with the SUT1 0 Fuses select the start up times as shown in Table 5 AMEL 2r Low frequency Crystal Oscillator AMEL Table 5 Start up Times for the Crystal Oscillator Clock Selection Start up Time Additional Delay from Power down from Reset CKSELO SUT1 0 and Power save Vec 5 0V Recommended Usage 0 00 258 CK done Ceramic resonator fast rising power 0 01 258 CK 65 ms Ceramic resonator slowly rising power 0 10 1K CK _ Ceramic resonator BOD enabled 0 11 1K CK Aims Ceramic resonator fast rising power 1 00 1K CK 65 ms Ceramic resonator slowly
265. is ter The BLBSET and SPMEN bits will auto clear upon completion of reading the Lock Bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles When BLBSET and SPMEN are cleared LPM will work as described in the Instruction set Manual Bit 7 6 5 4 3 2 1 0 Re ee eter ates ere tee ie The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock Bits To read the Fuse Low bits load the Z pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCR When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR the value of the Fuse Low bits FLB will be loaded in the destination register as shown below Refer to Table 88 on page 224 for a detailed description and mapping of the fuse low bits Bit 7 6 5 4 3 2 1 0 Re Similarly when reading the Fuse High bits load 0x0003 in the Z pointer When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR the value of the Fuse High bits FHB will be loaded in the destination reg ister as shown below Refer to Table 87 on page 223 for detailed description and mapping of the fuse high bits Bit 7 6 5 4 3 2 1 0 Rd EHE FHB6 FHBS FHB4 FHB3 SEHBS FHB1 i FHBO Fuse and Lock Bits that are programmed will be read as zero Fuse and Lock Bits that are unprogrammed will be re
266. is per formed using an 8 bit temporary High byte Register TEMP This temporary register is shared by all the other 16 bit registers See Accessing 16 bit Registers on page 79 Bit 7 6 5 4 3 2 1 0 ocea 7 oz mor Toce oce rer Toro we Read Write R W R W R W R W R W R W R R W Initial Value 0 0 0 0 0 0 0 0 Note 1 This register contains interrupt control bits for several Timer Counters but only Timer1 bits are described in this section The remaining bits are described in their respective timer sections e Bit 5 TICIE1 Timer Counter1 Input Capture Interrupt Enable When this bit is written to one and the I flag in the Status Register is set interrupts glo bally enabled the Timer Counter1 Input Capture Interrupt is enabled The corresponding Interrupt Vector see Interrupts on page 46 is executed when the ICF1 Flag located in TIFR is set Bit4 OCIE1A Timer Counter1 Output Compare A Match Interrupt Enable When this bit is written to one and the I flag in the Status Register is set interrupts glo bally enabled the Timer Counter1 Output Compare A match interrupt is enabled The corresponding Interrupt Vector see Interrupts on page 46 is executed when the OCF1A Flag located in TIFR is set Bit 3 OCIE1B Timer Counter1 Output Compare B Match Interrupt Enable When this bit is written to one and the I flag in the Status Register is set interrupts glo bally enabled the Timer Counter1 Output
267. is then to ensure that no pins drive resistive loads In sleep modes where the both the I O clock clkyo and the ADC clock clkA5c are stopped the input buffers of the device will be disabled This ensures that no power is consumed by the input logic when not needed In some cases the input logic is needed for detecting wake up conditions and it will then be enabled Refer to the section Digital Input Enable and Sleep Modes on page 55 for details on which pins are enabled If the input buffer is enabled and the input signal is left floating or have an analog signal level close to Vcc 2 the input buffer will use excessive power 36 ATmega8 L m I 2486R AVR 07 07 X A mega8 L System Control and Reset Resetting the AVR Reset Sources 2486R AVR 07 07 During Reset all l O Registers are set to their initial values and the program starts exe cution from the Reset Vector If the program never enables an interrupt source the Interrupt Vectors are not used and regular program code can be placed at these loca tions This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa The circuit diagram in Figure 14 shows the Reset Logic Table 15 defines the electrical parameters of the reset circuitry The I O ports of the AVR are immediately reset to their initial state when a reset source goes active This does not require any clock
268. is used the interrupt handling routine does not have to clear the TXC Flag this is done automat ically when the interrupt is executed The Parity Generator calculates the parity bit for the serial frame data When parity bit is enabled UPM1 1 the Transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent The disabling of the Transmitter setting the TXEN to zero will not become effective until ongoing and pending transmissions are completed i e when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted When dis abled the Transmitter will no longer override the TxD pin 142 ATmega8 L memm 2486R AVR 07 07 A mega8 L Data Reception The USART Receiver Receiving Frames with 5 to 8 Data Bits 2486R AVR 07 07 The USART Receiver is enabled by writing the Receive Enable RXEN bit in the UCSRB Register to one When the Receiver is enabled the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver s serial input The baud rate mode of operation and frame format must be set up once before any serial reception can be done If synchronous operation is used the clock on the XCK pin will be used as transfer clock The Receiver starts data reception when it detects a valid start bit Each bit that follows the start bit will be sampled at the baud rate or XCK
269. isted on page 63 Reset input A low level on this pin for longer than the minimum pulse length will gener ate a reset even if the clock is not running The minimum pulse length is given in Table 15 on page 38 Shorter pulses are not guaranteed to generate a reset AMEL s AMEL AVcc AV cg is the supply voltage pin for the A D Converter Port C 3 0 and ADC 7 6 It should be externally connected to Voc even if the ADC is not used If the ADC is used it should be connected to Ve through a low pass filter Note that Port C 5 4 use digital supply voltage Voc AREF AREF is the analog reference pin for the A D Converter ADC7 6 TQFP and QFN MLF In the TQFP and QFN MLF package ADC7 6 serve as analog inputs to the A D con Package Only verter These pins are powered from the analog supply and serve as 10 bit ADC channels 2486R AVR 07 07 A megae8 L Resources A comprehensive set of development tools application notes and datasheets are avail able for download on http www atmel com avr AMEL r 2486R AVR 07 07 AMEL About Code This datasheet contains simple code examples that briefly show how to use various Examples parts of the device These code examples assume that the part specific header file is included before compilation Be aware that not all C compiler vendors include bit defini tions in the header files and interrupt handling in C is compiler dependent Please confirm with the C
270. itch 0 50 mm Quad Flat No Lead Micro Lead Frame Package QFN MLF 22 ATmega8 L mmm f mega8 L Packaging Information 32A LLL ANMLUUNNTAN Q PIN 1 IDENTIFIER Notes 1 This package conforms to JEDEC reference MS 026 Variation ABA 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 10 mm maximum TITLE SYMBOL A COMMON DIMENSIONS Unit of Measure mm MIN NOM MAX 1 20 A1 0 15 A2 1 05 D 9 25 D1 7 10 E 9 25 E1 7 10 0 45 0 20 B C L 0 75 0 80 TYP IMEL cues One Parkway 32A 32 lead 7 x 7 mm Body Size 1 0 mm Body Thickness 0 8 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP AIMEL San Jose CA 95131 AMEL 2486R AVR 07 07 10 5 2001 DRAWING NO REV 32A B 293 AMEL 28P3 E it ua t SEATING iE MEN mE d A1 Jhe l aB 4 PLACES
271. itted both from Master to Slave and vice versa The Master must instruct the Slave what location it wants to read requiring the use of the MT mode Sub sequently data must be read from the Slave implying the use of the MR mode Thus the transfer direction must be changed The Master must keep control of the bus during all these steps and the steps should be carried out as an atomical operation If this prin ciple is violated in a multimaster system another Master can alter the data pointer in the EEPROM between steps 2 and 3 and the Master will read the wrong data location Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data After a REPEATED START the Master keeps ownership of the bus The following figure shows the flow in this transfer Figure 86 Combining Several TWI Modes to Access a Serial EEPROM Master Transmitter Master Receiver pesce ees quce pee S SLA W A ADDRESS A Rs SLA R A DATA A B S START Rs REPEATED START P STOP Transmitted from master to slave Transmitted from slave to master If multiple masters are connected to the same bus transmissions may be initiated simul taneously by one or more of them The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the trans fer and that no
272. l Counter Asynch ronous Clear Timer on Compare Match Auto Reload Operation Glitch free phase Correct Pulse Width Modulator PWM Frequency Generator 10 bit Clock Prescaler Overflow and Compare Match Interrupt Sources TOV2 and OCF2 Allows Clocking from External 32 kHz Watch Crystal Independent of the I O Clock Overview A simplified block diagram of the 8 bit Timer Counter is shown in Figure 45 For the actual placement of I O pins refer to Pin Configurations on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the 8 bit Timer Counter Register Description on page 117 Figure 45 8 bit Timer Counter Block Diagram TOVn Int Req Tn TOSC1 T C Prescaler Oscillator Timer Counter TCNTn OCn m elk gt Int Req Ee my Generation clk p DATA BUS Synchronized Status Flags 19 Dom asynchronous Mode Select ASn Synchronization Unit Clk sy Status Flags 14 ATmega8g L 2486R AVR 07 07 9 A mega8 L Registers Definitions Timer Counter Clock Sources 2486R AVR 07 07 The Timer Counter TCNT2 and Output Compare Register OCR2 are 8 bit registers Interrupt request shorten as Int Req signals are all visible in the Timer Interrupt Flag Register TIFR All interrupts are individually masked with the Timer Interru
273. lear OC2 on Compare Match 1 1 Set OC2 on Compare Match Table 44 shows the COM21 0 bit functionality when the WGM21 0 bits are set to fast PWM mode Table 44 Compare Output Mode Fast PWM Mode COM 1 COM20 Description 0 0 Normal port operation OC2 disconnected 0 1 Reserved 1 0 Clear OC2 on Compare Match set OC2 at BOTTOM non inverting mode 1 1 Set OC2 on Compare Match clear OC2 at BOTTOM inverting mode Note 1 A special case occurs when OCR2 equals TOP and COM21 is set In this case the Compare Match is ignored but the set or clear is done at BOTTOM See Fast PWM Mode on page 112 for more details Table 45 shows the COM21 0 bit functionality when the WGM21 0 bits are set to phase correct PWM mode Table 45 Compare Output Mode Phase Correct PWM Mode COM21 COM20 Description 0 0 Normal port operation OC2 disconnected 0 1 Reserved Clear OC2 on Compare Match when up counting Set OC2 on Compare f d Match when downcounting Set OC2 on Compare Match when up counting Clear OC2 on Compare 1 Match when downcounting Note 1 A special case occurs when OCR2 equals TOP and COM21 is set In this case the Compare Match is ignored but the set or clear is done at TOP See Phase Correct PWM Mode on page 113 for more details uns ATmega8 L mmm 2486R AVR 07 07 AT 11 C025 Timer Counter Register TCNT2 Output Compare Register OCR2
274. less the Digital Input is used as a clock source the module with the alternate function will use its own synchronizer AIO Analog Input output This is the Analog Input output to from alternate functions The signal is connected directly to the pad and can be used bi directionally The following subsections shortly describe the alternate functions for each port and relate the overriding signals to the alternate function Refer to the alternate function description for further details 2486R AVR 07 07 AMEL 57 Special Function IO Register SFIOR Alternate Functions of Port B AMEL Bit 7 6 5 4 3 2 1 0 Rene Pub Psae PSR sron Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 2 PUD Pull up Disable When this bit is written to one the pull ups in the I O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull ups DDxn PORTxn 0b01 See Configuring the Pin on page 52 for more details about this feature The Port B pins with alternate functions are shown in Table 22 Table 22 Port B Pins Alternate Functions Port Pin Alternate Functions PB7 XTAL2 Chip Clock Oscillator pin 2 TOSC2 Timer Oscillator pin 2 PB6 XTAL1 Chip Clock Oscillator pin 1 or External clock input TOSC1 Timer Oscillator pin 1 PB5 SCK SPI Bus Master clock Input PB4 MISO SPI Bus Master Input Slave Output PB3 M
275. llowed between e A REPEATED START condition and a data bit e ASTOP condition and a data bit e A REPEATED START and a STOP condition It is the user software s responsibility to ensure that these illegal arbitration conditions never occur This implies that in multi master systems all data transfers must use the same composition of SLA R W and data packets In other words All transmissions must contain the same number of data packets otherwise the result of the arbitration is undefined ATmega8 L memm 2486R AVR 07 07 ATmega8 L Overview of the TWI The TWI module is comprised of several submodules as shown in Figure 76 All regis Module ters drawn in a thick line are accessible through the AVR data bus Figure 76 Overview of the TWI Module Slew rate Spike Slew rate Spike Control Filter Control Filter Bus Interface Unit Bit Rate Generator START STOP i Control Spike Suppression Prescaler a Address Data Shift Bit Rate Register Arbitration detection Register TWDR A TWBR Address Match Unit Control Unit Address Register Status Register Control Register TWAR TWSR TWCR State Machine and Address Comparator SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system The output drivers contain a slew rate limiter in order to conform to the TWI specification The input stages contain a spike suppression unit removing spikes shorter than 50 ns Note that the inter nal
276. loader section see Figure 102 The size of the different sections is configured by the BOOTSZ Fuses as shown in Table 82 on page 220 and Figure 102 These two sec tions can have different level of protection since they have different sets of Lock Bits The application section is the section of the Flash that is used for storing the application code The protection level for the application section can be selected by the application boot Lock Bits Boot Lock Bits 0 see Table 78 on page 212 The application section can never store any Boot Loader code since the SPM instruction is disabled when exe cuted from the application section While the application section is used for storing the application code the The Boot Loader software must be located in the BLS since the SPM instruction can initiate a pro gramming when executing from the BLS only The SPM instruction can access the entire Flash including the BLS itself The protection level for the Boot Loader section can be selected by the Boot Loader Lock Bits Boot Lock Bits 1 see Table 79 on page 212 Whether the CPU supports Read While Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed In addition to the two sections that are configurable by the BOOTSZ Fuses as described above the Flash is also divided into two fixed sections the Read While Write RWW section and the No Read While Write NRWW section The limit betwee
277. lock cycle If enabled OCIE2 1 the Output Compare Flag generates an Output Compare interrupt The OCF2 Flag is automatically cleared when the interrupt is executed Alternatively the OCF2 Flag can be cleared by software by writing a logical one to its I O bit location The waveform gen erator uses the match signal to generate an output according to operating mode set by the WGM21 0 bits and Compare Output mode COM21 0 bits The max and bottom sig nals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation see Modes of Operation on page 110 Figure 47 shows a block diagram of the Output Compare unit Figure 47 Output Compare Unit Block Diagram DATA BUS 8 bit Comparator OCFn Int Req TOP BOTTOM Waveform Generator FOCn WGMn1 0 COMn1 0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation PWM modes For the normal and Clear Timer on Compare CTC modes of operation the double buffering is disabled The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence The synchro nization prevents the occurrence of odd length non symmetrical PWM pulses thereby making the output glitch free The OCR2 Register access may seem complex but this is not case When the double buffering is enabled the CPU has access to the OCR2 Buffer Register and if double b
278. low prescaler value must be done with care since the CTC mode does not have the double buffering feature If the new value written to OCRI1A or ICR1 is lower than the current value of TCNT1 the counter will miss the Compare Match The counter will then have to count to its maximum value OxFFFF and wrap around starting at Ox0000 before the Compare Match can occur In many cases this feature is not desirable An alternative will then be to use the fast PWM mode using OCR1A for defining TOP WGM13 0 15 since the OCR1A then will be double buffered For generating a waveform output in CTC mode the OC1A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode COM1A1 0 1 The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output DDR OC1A 1 The waveform generated will have a maximum frequency of foc1a fox 10 2 when OCRIA is set to zero 0x0000 The waveform frequency is defined by the following equation AR fok Vo OCnA 2 N 1 OCRnA The N variable represents the prescaler factor 1 8 64 256 or 1024 As for the Normal mode of operation the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode WGM13 0 5 6 7 14 or 15 pro vides a high frequency PWM waveform generation option The fast PWM differs from the other
279. ls Read Calibration Byte 0011 1000 OOxx xxxx 0000 00bb e000 oooo Read Calibration Byte Note a address high bits b address low bits H 0 Low byte 1 High byte o data out i data in x don t care 240 ATmega8 L mmm 2486R AVR 07 07 X 9O A megae8 L SPI Serial Programming For characteristics of the SPI module see SPI Timing Characteristics on page 246 Characteristics AMEL 241 2486R AVR 07 07 AMEL Electrical Characteristics Note Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manu factured on the same process technology Min and Max values will be available after the device is characterized Absolute Maximum Ratings Operating Temperature ss 55 C to 125 C Storage Temperature sssssss 65 C to 150 C Voltage on any Pin except RESET with respect to Ground sssss 0 5V to Vcc40 5V Voltage on RESET with respect to Ground 0 5V to 13 0V Maximum Operating Voltage eeeeeesss 6 0V DC Current per I O Pin eene 40 0 mA DC Current Voc and GND Pins ss 300 0 mA DC Characteristics T4 40 C to 85 C Vec 2 7V to 5 5V unless otherwise noted NOTICE Stresses beyond those listed under Absolute
280. lter on the pin to suppress spikes shorter than 50 ns on the input signal and the pin is driven by an open drain driver with slew rate limitation PC5 can also be used as ADC input Channel 5 Note that ADC input channel 5 uses dig ital power SDA ADCA Port C Bit 4 SDA Two wire Serial Interface Data When the TWEN bit in TWCR is set one to enable the Two wire Serial Interface pin PC4 is disconnected from the port and becomes the Serial Data I O pin for the Two wire Serial Interface In this mode there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal and the pin is driven by an open drain driver with slew rate limitation PC4 can also be used as ADC input Channel 4 Note that ADC input channel 4 uses dig ital power e ADC3 Port C Bit 3 PC3 can also be used as ADC input Channel 3 Note that ADC input channel 3 uses analog power ADC2 Port C Bit 2 PC2 can also be used as ADC input Channel 2 Note that ADC input channel 2 uses analog power ADC1 Port C Bit 1 AMEL s 2486R AVR 07 07 AMEL PC1 can also be used as ADC input Channel 1 Note that ADC input channel 1 uses analog power ADCO Port C Bit 0 PCO can also be used as ADC input Channel 0 Note that ADC input channel 0 uses analog power Table 26 and Table 27 relate the alternate functions of Port C to the overriding signals shown in Figure 25 on page 56 Table 26 Overriding Signals for Alternate F
281. lue will only be visible on the port pin if the data direction for the port pin is set as output The PWM waveform is generated by setting or clearing the OC2 Register at the Compare Match between OCR2 and TCNT2 and clearing or setting the OC2 Register at the timer clock cycle the counter is cleared changes from MAX to BOTTOM 112 ATmega8 L memm 2486R AVR 07 07 X f mega8 L Phase Correct PWM Mode 2486R AVR 07 07 The PWM frequency for the output can be calculated by the following equation f _ fok Vo OCnPWM N 256 The N variable represents the prescale factor 1 8 32 64 128 256 or 1024 The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode If the OCR2 is set equal to BOTTOM the output will be a narrow spike for each MAX 1 timer clock cycle Setting the OCR2 equal to MAX will result in a constantly high or low output depending on the polarity of the out put set by the COM21 0 bits A frequency with 50 duty cycle waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match COM21 0 1 The waveform generated will have a maximum frequency Of fooo for 0 2 when OCR2 is set to zero This feature is similar to the OC2 toggle in CTC mode except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode The phase correct PWM mode WGM21 0 1
282. ly protecting the SPMCR Register and thus the Flash from unintentional writes Programming Time for Flash The calibrated RC Oscillator is used to time Flash accesses Table 81 shows the typical when using SPM programming time for Flash accesses from the CPU Table 81 SPM Programming Time Symbol Min Programming Time Max Programming Time Flash write page erase page write and write Lock Bits by SPM 3 7 ms 4 5 ms 1 Minimum and maximum programming time is per individual operation 28 ATmega8 L m ERN 2486R AVR 07 07 X Al mega8 L Simple Assembly Code Example for a Boot Loader 2486R AVR 07 07 the routine writes one page of data from RAM to Flash the first data location in RAM is pointed to by the Y pointer the first data location in Flash is pointed to by the Z pointer error handling is not included the routine must be placed inside the boot space at least the Do spm sub routine Only code inside NRWW section can be read during self programming page erase and page write registers used r0 r1 templ r16 temp2 r17 looplo r24 loophi r25 spmcrval r20 Storing and restoring of registers is not included in the routine register usage can be optimized at the expense of code size It is assumed that either the interrupt table is moved to the Boot loader section or that the interrupts are disabled equ
283. m l i Fixed OCFnB P i Ea Int Req Waveform m Generation OGne x a i From Analog Comparator Ouput m gt ICFn Int Req Edge Detector DNE en er ee pro EA TCCRnA TCCRnB Note 1 Refer to Pin Configurations on page 2 Table 22 on page 58 and Table 28 on page 63 for Timer Counter1 pin placement and description Registers The Timer Counter TCNT1 Output Compare Registers OCR1A B and Input Capture Register ICR1 are all 16 bit registers Special procedures must be followed when accessing the 16 bit registers These procedures are described in the section Access ing 16 bit Registers on page 79 The Timer Counter Control Registers TCCR1A B are 8 bit registers and have no CPU access restrictions Interrupt requests abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFR All interrupts are individually masked with the Timer Interrupt Mask Register TIMSK TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units The Timer Counter can be clocked internally via the prescaler or by an external clock source on the T1 pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is selected The output from the clock select logic is referred to as the timer clock clky
284. mory Control Register SPMCR will be read as logical one as long as the RWW section is blocked for reading After a programming is completed the RWWSB must be cleared by software before reading code located in the RWW section See Store Program Memory Control Register SPMCR on page 213 for details on how to clear RWWSB The code located in the NRWW section can be read when the Boot Loader software is updating a page in the RWW section When the Boot Loader code updates the NRWW section the CPU is halted during the entire page erase or page write operation Table 77 Read While Write Features Which Section does the Z Which Section Can be Read While pointer Address during the Read during Is the CPU Write Programming Programming Halted Supported RWW section NRWW section No Yes NRWW section None Yes No Figure 101 Read While Write vs No Read While Write Read While Write RWW Section Z pointer Addresses NRWW Z pointer section Addresses RWW section No Read While Write NRWW Section CPU is Halted during the Operation Code Located in NRWW Section Can be Read during the Operation 20 ATmega8 L memm 2486R AVR 07 07 A mega8 L Boot Loader Lock Bits 2486R AVR 07 07 Figure 102 Memory Sections Program Memory Program Memory BOOTSZ 11 BOOTSZ 10 0000 0000 E E 9 E o o o o 2 Application Flash Section 2 Application Flash Section
285. mpare Match CTC Mode 2486R AVR 07 07 In Clear Timer on Compare or CTC mode WGM21 0 2 the OCR2 Register is used to manipulate the counter resolution In CTC mode the counter is cleared to zero when the counter value TCNT2 matches the OCR2 The OCR2 defines the top value for the counter hence also its resolution This mode allows greater control of the Compare Match output frequency It also simplifies the operation of counting external events The timing diagram for the CTC mode is shown in Figure 49 The counter value TCNT2 increases until a Compare Match occurs between TCNT2 and OCR2 and then counter TCNT2 is cleared 4 OCn Interrupt Flag Set Y Figure 49 CTC Mode Timing Diagram ooo ll ANN Y Y Y TCNTn Yay Toggle COMn1 0 1 Period 1 ba 2 bla 3 4 4 gt An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag If the interrupt is enabled the interrupt handler routine can be used for updating the TOP value However changing the TOP to a value close to BOT TOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature If the new value written to OCR2 is lower than the current value of TCNT2 the counter will miss the Compare Match The counter will then have to count to its maximum value OxFF and wrap around starting at 0x
286. mpled once every system clock cycle by the pin syn chronization logic The synchronized sampled signal is then passed through the edge detector Figure 30 shows a functional equivalent block diagram of the T1 TO synchroni zation and edge detector logic The registers are clocked at the positive edge of the internal system clock clkyo9 The latch is transparent in the high period of the internal system clock The edge detector generates one clk clk pulse for each positive CSn2 0 7 or neg ative CSn2 0 6 edge it detects Figure 30 T1 TO Pin Sampling Tn sync To Clock Select Logic Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2 5 to 3 5 system clock cycles from an edge has been applied to the T1 TO pin to the counter is updated Enabling and disabling of the clock input must be done when T1 TO has been stable for at least one system clock cycle otherwise it is a risk that a false Timer Counter clock pulse is generated 74 ATmega8 L mmm 2486R AVR 07 07 n Armega8 L Special Function IO Register SFIOR 2486R AVR 07 07 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling The external clock must be guaranteed to have less than half the system clock frequency feci lt fox 10 2 given a 50 50 duty cycle Since the edge detector uses sampling the
287. munication Bit 0 MPCM Multi processor Communication Mode This bit enables the Multi processor Communication mode When the MPCM bit is writ ten to one all the incoming frames received by the USART Receiver that do not contain address information will be ignored The Transmitter is unaffected by the MPCM setting For more detailed information see Multi processor Communication Mode on page 151 Bit 7 6 5 4 3 2 1 0 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB Read Write R W R W R W R W R W R W R R W Initial Value 0 0 0 0 0 0 0 0 e Bit 7 RXCIE RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC Flag A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set Bit6 TXCIE TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC Flag A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one the Global Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set Bit5 UDRIE USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE Flag A Data Register Empty inter rupt will be generated only if the UDRIE bit is written to one the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set e Bit 4 RXEN Receiver Enable W
288. must always allow the reference to start up before the output from the Analog Com parator or ADC is used To reduce power consumption in Power down mode the user can avoid the three conditions above to ensure that the reference is turned off before entering Power down mode Table 16 Internal Voltage Reference Characteristics ATmega8 features an internal bandgap reference This reference is used for Brown out Detection and it can be used as an input to the Analog Comparator or the ADC The 2 56V reference to the ADC is generated from the internal bandgap reference The voltage reference has a start up time that may influence the way it should be used The start up time is given in Table 16 To save power the reference is not always turned on The reference is on during the following situations Symbol Parameter Min Typ Max Units VBG Bandgap reference voltage 1 15 1 30 1 40 V tag Bandgap reference start up time 40 70 us IBG Bandgap reference current consumption 10 pA ATmega8 L memm 2486R AVR 07 07 un JT 11 C023 LL Watchdog Timer Watchdog Timer Control Register WDTCR 2486R AVR 07 07 The Watchdog Timer is clocked from a separate On chip Oscillator which runs at 1 MHz This is the typical value at Vcc 5V See characterization data for typical values at other Vcc levels By controlling the Watchdog Timer prescaler the Watchdog Reset interval can be adjusted as sho
289. n describes the general access timing concepts for instruction execution The AVR CPU is driven by the CPU clock clkcp directly generated from the selected clock source for the chip No internal clock division is used Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept This is the basic pipelin ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost functions per clocks and functions per power unit Figure 5 The Parallel Instruction Fetches and Instruction Executions T1 T2 TS T4 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch i i i i Figure 6 shows the internal timing concept for the Register File In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register Figure 6 Single Cycle ALU Operation T1 T2 T3 T4 I 1 orc XS CX l2 Se CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The AVR provides several different interrupt sources These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space All interrupts are
290. n page 8 As the code examples illustrate write accesses of the two registers are relatively unaf fected of the sharing of I O location 152 ATmega8 L suum 2486R AVR 07 07 mn AT 11 C025 Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex opera tion However in most applications it is rarely necessary to read any of these registers The read access is controlled by a timed sequence Reading the I O location once returns the UBRRH Register contents If the register location was read in previous sys tem clock cycle reading the register in the current clock cycle will return the UCSRC contents Note that the timed sequence for reading the UCSRC is an atomic operation Interrupts must therefore be controlled e g by disabling interrupts globally during the read operation The following code example shows how to read the UCSRC Register contents Assembly Code Example USART_ReadUCSRC Read UCSRC in r16 UBRRH in r16 UCSRC ret C Code Example unsigned char USART ReadUCSRC void unsigned char ucsrc Read UCSRC ucsrc UBRRH ucsrc UCSRC return ucsrc Note 1 See About Code Examples on page 8 The assembly code example returns the UCSRC value in r16 Reading the UBRRH contents is not an atomic operation and therefore it can be read as an ordinary register as long as the previous instruction did not access the register
291. n simulations and characteriza tion of other AVR microcontrollers manufactured on the same process technology Min and Max values will be available after the device is characterized 4 ATmega8 L Sse 2486R AVR 07 07 AT 11 C025 Pin Descriptions VCC GND Port B PB7 PB0 XTAL1 XTAL2 TOSC1 TOSC2 Port C PC5 PCO PC6 RESET Port D PD7 PD0 RESET 2486R AVR 07 07 Digital supply voltage Ground Port B is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port B output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port B pins that are externally pulled low will source current if the pull up resistors are activated The Port B pins are tri stated when a reset condition becomes active even if the clock is not running Depending on the clock selection fuse settings PB6 can be used as input to the invert ing Oscillator amplifier and input to the internal clock operating circuit Depending on the clock selection fuse settings PB7 can be used as output from the inverting Oscillator amplifier If the Internal Calibrated RC Oscillator is used as chip clock source PB7 6 is used as TOSC2 1 input for the Asynchronous Timer Counter2 if the AS2 bit in ASSR is set The various special features of Port B are elaborated in Alternate Functions of Port B on page 58 and System Clock and Clock Options on p
292. n still be controlled by the PORTDO bit AMEL ss 2486R AVR 07 07 64 Table 29 and Table 30 relate the alternate functions of Port D to the overriding signals AMEL shown in Figure 25 on page 56 Table 29 Overriding Signals for Alternate Functions PD7 PD4 Signal Name PD7 AIN1 PD6 AINO PD5 T1 PD4 XCK TO PUOE 0 0 0 0 PUO 0 0 0 0 OOE 0 0 0 0 OO 0 0 0 0 PVOE 0 0 0 UMSEL PVO 0 0 0 XCK OUTPUT DIEOE 0 0 0 0 DIEO 0 0 0 0 DI 7 T1 INPUT XCK INPUT TO INPUT AlO AIN1 INPUT AINO INPUT Table 30 Overriding Signals for Alternate Functions in PD3 PDO Signal Name PD3 INT1 PD2 INTO PD1 TXD PDO RXD PUOE 0 0 TXEN RXEN PUO 0 0 0 PORTDO PUD OOE 0 0 TXEN RXEN OO 0 0 1 0 PVOE 0 0 TXEN 0 PVO 0 0 TXD 0 DIEOE INT1 ENABLE INTO ENABLE 0 0 DIEO 1 1 0 0 DI INT1 INPUT INTO INPUT RXD AIO ATlmega8 L memm 2486R AVR 07 07 X X9X A mega8 L Register Description for I O Ports The Port B Data Register PORTB The Port B Data Direction Register DDRB The Port B Input Pins Address PINB The Port C Data Register PORTC The Port C Data Direction Register DDRC The Port C Input Pins Address PINC The Port D Data Register PORTD The Port D Data Direction Register DDRD The Port D Input Pins Address PIND 2486R AVR 07 07 Bit Read Write Initial Value Bit Read
293. n the RWW and NRWW sections is given in Table 83 on page 221 and Figure 102 on page 211 The main difference between the two sections is When erasing or writing a page located inside the RWW section the NRWW section can be read during the operation e When erasing or writing a page located inside the NRWW section the CPU is halted during the entire operation AMEL 209 RWW Read While Write Section NRWW No Read While Write Section AMEL Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation The syntax Read While Write sec tion refers to which section that is being programmed erased or written not which section that actually is being read during a Boot Loader software update If a Boot Loader software update is programming a page inside the RWW section it is possible to read code from the Flash but only code that is located in the NRWW sec tion During an on going programming the software must ensure that the RWW section never is being read If the user software is trying to read code that is located inside the RWW section i e by a call rimp Ipm or an interrupt during programming the software might end up in an unknown state To avoid this the interrupts should either be disabled or moved to the Boot Loader Section The Boot Loader Section is always located in the NRWW section The RWW Section Busy bit RWWSB in the Store Program me
294. n to the 8 bit TWDR the Bus Interface Unit also contains a register containing the N ACK bit to be transmitted or received This N ACK Register is not directly accessible by the applica tion software However when receiving it can be set or cleared by manipulating the TWI Control Register TWCR When in Transmitter mode the value of the received N ACK bit can be determined by the value in the TWSR The START STOP Controller is responsible for generation and detection of START REPEATED START and STOP conditions The START STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes enabling the MCU to wake up if addressed by a Master If the TWI has initiated a transmission as Master the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process If the TWI has lost an arbitration the Control Unit is informed Correct action can then be taken and appropriate status codes generated The Address Match unit checks if received address bytes match the seven bit address in the TWI Address Register TWAR If the TWI General Call Recognition Enable TWGCE bit in the TWAR is written to one all incoming address bits will also be com pared against the General Call address Upon an address match the Control Unit is informed allowing correct action to be taken The TWI may or may not acknowledge its address depending on settings in the
295. nded For Timer Counter2 the possible prescaled selections are clky54 8 Clkt29 32 clky54 64 CIKy55 128 clk159 256 and clk 25 1024 Additionally clKros as well as 0 stop may be selected Setting the PSR2 bit in SFIOR resets the prescaler This allows the user to operate with a predictable prescaler Bit rj 6 5 4 3 2 1 0 p ACME PUD PSR2 PSR10 SFIOR Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 1 PSR2 Prescaler Reset Timer Counter2 When this bit is written to one the Timer Counter2 prescaler will be reset The bit will be cleared by hardware after the operation is performed Writing a zero to this bit will have no effect This bit will always be read as zero if Timer Counter2 is clocked by the internal CPU clock If this bit is written when Timer Counter2 is operating in Asynchronous mode the bit will remain one until the prescaler has been reset AMEL 123 AMEL Serial Peripheral The Serial Peripheral Interface SPI allows high speed synchronous data transfer Interface SPI between the ATmega8 and peripheral devices or between several AVR devices The ATmega8 SPI includes the following features Full duplex Three wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake up from Idle Mode Double Speed CK 2 Master SPI Mode Figure 5
296. nterrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts If wake up from the Analog Comparator interrupt is not required the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Sta tus Register ACSR This will reduce power consumption in Idle mode If the ADC is enabled a conversion starts automatically when this mode is entered When the SM2 0 bits are written to 001 the SLEEP instruction makes the MCU enter ADC Noise Reduction mode stopping the CPU but allowing the ADC the external interrupts the Two wire Serial Interface address watch Timer Counter2 and the Watchdog to continue operating if enabled This sleep mode basically halts clkjo clkcpy and clkg asy while allowing the other clocks to run This improves the noise environment for the ADC enabling higher resolution measure ments If the ADC is enabled a conversion starts automatically when this mode is entered Apart form the ADC Conversion Complete interrupt only an External Reset a Watchdog Reset a Brown out Reset a Two wire Serial Interface address match inter rupt a Timer Counter2 interrupt an SPM EEPROM ready interrupt or an external level interrupt on INTO or INT1 can wake up the MCU from ADC Noise Reduction mode When the SM2 0 bits are written to 010 the SLEEP instruction makes the MCU enter Power down mode In this mode the External Oscillator is stopped while the ex
297. nversion performs initialization of the ADC ADSC will read as one as long as a conversion is in progress When the conversion is complete it returns to zero Writing zero to this bit has no effect e Bit 5 ADFR ADC Free Running Select When this bit is set one the ADC operates in Free Running mode In this mode the ADC samples and updates the Data Registers continuously Clearing this bit zero will terminate Free Running mode e Bit4 ADIF ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I bit in SREG are set ADIF is cleared by hardware when executing the corresponding interrupt Handling Vector Alternatively ADIF is cleared by writing a logical one to the flag Beware that if doing a Read Modify Write on ADCSRA a pending interrupt can be dis abled This also applies if the SBI and CBI instructions are used e Bit 3 ADIE ADC Interrupt Enable When this bit is written to one and the I bit in SREG is set the ADC Conversion Com plete Interrupt is activated AMEL 207 Bits 2 0 ADPS2 0 ADC Prescaler Select Bits AMEL These bits determine the division factor between the XTAL frequency and the input clock to the ADC Table 76 ADC Prescaler Selections ADPS2 ADPS1 ADPSO Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 3
298. nverted The relation between the parity bit and data bits is as follows even d 49 d3 d5 6 d4 6 dy 6 O P aa d 9 6d464d 6d 6461 Paven Parity bit using even parity Paa Parity bit using odd parity d Data bit n of the character If used the parity bit is located between the last data bit and first stop bit of a serial frame The USART has to be initialized before any communication can take place The initial ization process normally consists of setting the baud rate setting frame format and enabling the Transmitter or the Receiver depending on the usage For interrupt driven USART operation the Global Interrupt Flag should be cleared and interrupts globally disabled when doing the initialization Before doing a re initialization with changed baud rate or frame format be sure that there are no ongoing transmissions during the period the registers are changed The TXC Flag can be used to check that the Transmitter has completed all transfers and the RXC Flag can be used to check that there are no unread data in the receive buffer Note that the TXC Flag must be cleared before each transmission before UDR is written if it is used for this purpose The following simple USART initialization code examples show one assembly and one C function that are equal in functionality The examples assume asynchronous opera tion using polling no interrupts enabled and a fixed frame format The baud rate
299. o Read While Write section NRWW 32 0xCO00 OxFFF For details about these two section see NRWW No Read While Write Section on page 210 and RWW Read While Write Section on page 210 Table 84 Explanation of Different Variables used in Figure 103 and the Mapping to the Z pointer Corresponding Variable Z value Description PCMSB 11 Most significant bit in the Program Counter The Program Counter is 12 bits PC 11 0 PAGEMSB 4 Most significant bit which is used to address the words within one page 32 words in a page requires 5 bits PC 4 0 ZPCMSB Z12 Bit in Z register that is mapped to PCMSB Because ZO is not used the ZPCMSB equals PCMSB 1 ZPAGEMSB Z5 Bit in Z register that is mapped to PAGEMSB Because ZO is not used the ZPAGEMSB equals PAGEMSB 1 PCPAGE PC 11 5 Z12 26 Program counter page address Page select for page erase and page write PCWORD PC 4 0 Z5 Z1 Program counter word address Word select for filling temporary buffer must be zero during page write operation Note 1 Z15 Z13 always ignored Z0 should be zero for all SPM commands byte select for the LPM instruction See Addressing the Flash During Self Programming on page 214 for details about the use of Z pointer during Self Programming AMEL 221 Memory Programming Program And Data Memory Lock Bits AMEL The ATmega8 provides six Lock Bits which can be left unprogrammed
300. o types of Pulse Width Modulation PWM modes See Table 42 and Modes of Operation on page 110 Table 42 Waveform Generation Mode Bit Description WGM21 WGM20 Timer Counter Mode Update of TOV2 Flag Mode CTC2 PWM2 of Operation TOP OCR2 Set 0 0 0 Normal OxFF Immediate MAX 1 0 1 PWM Phase Correct OxFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM OxFF BOTTOM MAX Note 1 The CTC2 and PWM2 bit definition names are now obsolete Use the WGM21 0 def initions However the functionality and location of these bits are compatible with previous versions of the timer Bit 5 4 COM21 0 Compare Match Output Mode These bits control the Output Compare Pin OC2 behavior If one or both of the COM21 0 bits are set the OC2 output overrides the normal port functionality of the I O pin it is connected to However note that the Data Direction Register DDR bit corre sponding to OC2 pin must be set in order to enable the output driver When OC2 is connected to the pin the function of the COM21 0 bits depends on the WGM21 0 bit setting Table 43 shows the COM21 0 bit functionality when the WGM21 0 bits are set to a normal or CTC mode non PWM AMEL 117 2486R AVR 07 07 AMEL Table 43 Compare Output Mode Non PWM Mode COM21 COM20 Description 0 0 Normal port operation OC2 disconnected 0 1 Toggle OC2 on Compare Match 1 0 C
301. og Comparator Input Capture Enable When written logic one this bit enables the Input Capture function in Timer Counter1 to be triggered by the Analog Comparator The comparator output is in this case directly connected to the Input Capture front end logic making the comparator utilize the noise canceler and edge select features of the Timer Counter1 Input Capture interrupt When written logic zero no connection between the Analog Comparator and the Input Capture function exists To make the comparator trigger the Timer Counter1 Input Capture inter rupt the TICIE1 bit in the Timer Interrupt Mask Register TIMSK must be set Bits 1 0 ACIS1 ACISO Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator inter rupt The different settings are shown in Table 71 Table 71 ACIS1 ACISO Settings ACIS1 ACISO Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge 194 ATmega8 L memm 2486R AVR 07 07 AT 11 C025 Analog Comparator Multiplexed Input 2486R AVR 07 07 When changing the ACIS1 ACISO bits the Analog Comparator Interrupt must be dis abled by clearing its Interrupt Enable bit in the ACSR Register Otherwise an interrupt can occur when the bits are changed It is possible to select any of the ADC
302. ognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the bus becomes free 186 ATmega8 L SS I 2486R AVR 07 07 ATmega8 L Figure 83 Formats and States in the Slave Receiver Mode Reception of the own slave address and one or S more data bytes All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call address and one or more data bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call DATA A DATA A PorS 80 80 A0 A PorS 88 General Call A DATA A DATA A PorS i COEM 70 90 90 A0 A PorS 98 A 78 From master to slave From slave to master _ e en AIMEL 2486R AVR 07 07 T Any number of data bytes and their associated acknowledge bits This number contained in TWSR corresponds to a defined state of the Two Wire Serial Bus The prescaler bits are zero or masked to zero 187 Slave Transmitter Mode AMEL In the Slave Transmitter mode a number of data bytes are transmitted to a Master Receiver see Figure 84 All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero Figure 84 Data Transfer in Slave Transmitter Mode
303. ollowing definitions are frequently encountered in this section Table 64 TWI Terminology Term Master Description The device that initiates and terminates a transmission The Master also generates the SCL clock Slave The device addressed by a Master Transmitter The device placing data on the bus Receiver 2486R AVR 07 07 The device reading data from the bus AMEL 163 Electrical Interconnection Data Transfer and Frame Format Transferring Bits START and STOP Conditions AMEL As depicted in Figure 68 both bus lines are connected to the positive supply voltage through pull up resistors The bus drivers of all TWl compliant devices are open drain or open collector This implements a wired AND function which is essential to the opera tion of the interface A low level on a TWI bus line is generated when one or more TWI devices output a zero A high level is output when all TWI devices tri state their outputs allowing the pull up resistors to pull the line high Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7 bit slave address space A detailed specification of the electrical characteristics of the TWI is given in Two wire Serial Interface Character istics on page 245 Two different sets of specifications are
304. on the ATmega8 features an EEPROM Memory for data storage All three mem ory spaces are linear and regular The ATmega8 contains 8K bytes On chip In System Reprogrammable Flash memory for program storage Since all AVR instructions are 16 or 32 bits wide the Flash is organized as 4K x 16 bits For software security the Flash Program memory space is divided into two sections Boot Program section and Application Program section The Flash memory has an endurance of at least 10 000 write erase cycles The ATmega8 Program Counter PC is 12 bits wide thus addressing the 4K Program mem ory locations The operation of Boot Program section and associated Boot Lock Bits for software protection are described in detail in Boot Loader Support Read While Write Self Programming on page 209 Memory Programming on page 222 contains a detailed description on Flash Programming in SPI or Parallel Programming mode Constant tables can be allocated within the entire Program memory address space see the LPM Load Program memory instruction description Timing diagrams for instruction fetch and execution are presented in Instruction Execu tion Timing on page 14 Figure 7 Program Memory Map 000 Application Flash Section Boot Flash Section FFF AMEL L SRAM Data Memory AMEL Figure 8 shows how the ATmega8 SRAM Memory is organized The lower 1120 Data memory locations address the Register File the I O Memory and
305. on which returns the content at the selected address at serial output MISO 7 Atthe end of the programming session RESET can be set high to commence normal operation 8 Power off sequence if needed Set RESET to 1 Turn Vec power off Data Polling Flash When a page is being programmed into the Flash reading an address location within the page being programmed will give the value OxFF At the time the device is ready for a new page the programmed value will read correctly This is used to determine when the next page can be written Note that the entire page is written simultaneously and any address within the page can be used for polling Data polling of the Flash will not work for the value OxFF so when programming this value the user will have to wait for at least two e Asa before programming the next page As a chip erased device contains 233 ATmega8 L mmm A mega8 L Data Polling EEPROM 2486R AVR 07 07 OxFF in all locations programming of addresses that are meant to contain OxFF can be skipped See Table 97 for twp c 4s value When a new byte has been written and is being programmed into EEPROM reading the address location being programmed will give the value OxFF At the time the device is ready for a new byte the programmed value will read correctly This is used to deter mine when the next byte can be written This will not work for the value OxFF but the user should hav
306. on with all the 32 general purpose working registers Within a single clock cycle arithmetic operations between general purpose registers or between a register and an immediate are executed The ALU operations are divided into three main categories arithmetic logical and bit func tions Some implementations of the architecture also provide a powerful multiplier supporting both signed unsigned multiplication and fractional format See the Instruc tion Set section for a detailed description The Status Register contains information about the result of the most recently executed arithmetic instruction This information can be used for altering program flow in order to perform conditional operations Note that the Status Register is updated after all ALU operations as specified in the Instruction Set Reference This will in many cases remove the need for using the dedicated compare instructions resulting in faster and more compact code The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt This must be handled by software The AVR Status Register SREG is defined as Bit 7 6 5 4 3 2 1 0 1173 Ps TO TON se Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 I Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled The individ ual interrupt enable control is then perform
307. ons The waveform genera tor uses the COM1x1 0 bits for defining the Output Compare OC1x state at the next Compare Match Secondly the COM1x1 0 bits control the OC1x pin output source Fig ure 36 shows a simplified schematic of the logic affected by the COM1x1 0 bit setting The I O Registers I O bits and I O pins in the figure are shown in bold Only the parts of the general I O Port Control Registers DDR and PORT that are affected by the COM 1x1 0 bits are shown When referring to the OC1x state the reference is for the internal OC1x Register not the OC1x pin If a System Reset occur the OC1x Register is reset to 0 Figure 36 Compare Match Output Unit Schematic COMnx1 COMnxo Waveform FOCnx Generator OCnx OCnx Pin N A PORT DATABUS SZ DDR celko The general I O port function is overridden by the Output Compare OC1x from the waveform generator if either of the COM1x1 0 bits are set However the OC1x pin direction input or output is still controlled by the Data Direction Register DDR for the port pin The Data Direction Register bit for the OC1x pin DDR OC1x must be set as output before the OC1x value is visible on the pin The port override function is generally independent of the Waveform Generation mode but there are some exceptions Refer to Table 36 Table 37 and Table 38 for details The design of the Output Compare Pin logic allows initialization of the O
308. op bits When a com plete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an idle high state Figure 64 illustrates the possible combinations of the frame formats Bits inside brackets are optional Figure 64 Frame Formats v IDLE i 0 1 2 i 3 4 s 86 7 al P1 sv Sp2 St IDLE St Start bit always low n Data bits 0 to 8 P Parity bit Can be odd or even AMEL 137 Parity Bit Calculation USART Initialization AMEL Sp Stop bit always high IDLE No transfers on the communication line RxD or TxD An IDLE line must be high The frame format used by the USART is set by the UCSZ2 0 UPM1 0 and USBS bits in UCSRB and UCSRC The Receiver and Transmitter use the same setting Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter The USART Character SiZe UCSZ2 0 bits select the number of data bits in the frame The USART Parity mode UPM1 0 bits enable and set the type of parity bit The selec tion between one or two stop bits is done by the USART Stop Bit Select USBS bit The Receiver ignores the second stop bit An FE Frame Error will therefore only be detected in the cases where the first stop bit is zero The parity bit is calculated by doing an exclusive or of all the data bits If odd parity is used the result of the exclusive or is i
309. or 0 1 1 X STOP condition will be transmitted and TWSTO Flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x50 Data byte has been received Read data byte or 0 0 1 0 Data byte will be received and NOT ACK will be ACK has been returned returned Read data byte 0 0 1 1 Data byte will be received and ACK will be returned 0x58 Data byte has been received Read data byte or 1 0 1 X Repeated START will be transmitted NOT ACK has been returned Read data byte or 0 1 1 X STOP condition will be transmitted and TWSTO Flag will be reset Read data byte 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 2486R AVR 07 07 AMEL 183 AMEL Figure 81 Formats and States in the Master Receiver Mode MR Y cpm Successfull reception S SLA A R A DATA A DATA A IP from a slave ame receiver 08 40 50 58 Next transfer started with a Rs SLA 1 R repeated start condition Not acknowledge Ww received after the A P slave address n 48 Y LL MT Arbitration lost in slave Other master Other master address or data byte AoA continues A continues 38 38 ER gt Arbitration lost and Other master addressed as slave A continues gt To corresponding 68
310. ot write a new value before the contents of the temporary register have been transferred to its destination Each of the three mentioned registers have their individual temporary register which means that e g writing to TCNT2 does not disturb an OCR2 write in progress To detect that a transfer to the destination register has taken place the Asynchronous Status Register ASSR has been implemented e When entering Power save mode after having written to TCNT2 OCR2 or TCCR2 the user must wait until the written register has been updated if Timer Counter2 is used to wake up the device Otherwise the MCU will enter sleep mode before the 120 ATmega8 L _ 2486R AVR 07 07 X f mega8 L changes are effective This is particularly important if the Output Compare2 interrupt is used to wake up the device since the Output Compare function is disabled during writing to OCR2 or TCNT2 If the write cycle is not finished and the MCU enters sleep mode before the OCR2UB bit returns to zero the device will never receive a Compare Match interrupt and the MCU will not wake up e f Timer Counter2 is used to wake the device up from Power save mode precautions must be taken if the user wants to re enter one of these modes The interrupt logic needs one TOSC1 cycle to be reset If the time between wake up and re entering sleep mode is less than one TOSC1 cycle the interrupt will not occur and the device will fail to wake up If the
311. ounter clock TOP Signalizes that TCNT2 has reached maximum value BOTTOM Signalizes that TCNT2 has reached minimum value zero Depending on the mode of operation used the counter is cleared incremented or dec remented at each timer clock clk clk can be generated from an external or internal clock source selected by the clock select bits CS22 0 When no clock source is selected CS22 0 0 the timer is stopped However the TCNT2 value can be accessed by the CPU regardless of whether clk is present or not A CPU write overrides has priority over all counter clear or count operations The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer Counter Control Register TCCR2 There are close connections between how the counter behaves counts and how waveforms are generated on the Output Compare Output OC2 For more details about advanced counting sequences and waveform generation see Modes of Operation on page 110 The Timer Counter Overflow TOV2 Flag is set according to the mode of operation selected by the WGM21 0 bits TOV2 can be used for generating a CPU interrupt 16 ATmega8 L mmm 2486R AVR 07 07 X A mega8 L Output Compare Unit The 8 bit comparator continuously compares TCNT2 with the Output Compare Register OCR2 Whenever TCNT2 equals OCR2 the comparator signals a match A match will set the Output Compare Flag OCF2 at the next timer c
312. ous value of the WDE bit 2 Within the next four clock cycles in the same operation write the WDE and WDP bits as desired but with the WDCE bit cleared In this mode the Watchdog Timer is always enabled and the WDE bit will always read as one A timed sequence is needed when changing the Watchdog Time out period To change the Watchdog Time out the following procedure must be followed 1 In the same operation write a logical one to WDCE and WDE Even though the WDE always is set the WDE must be written to one to start the timed sequence Within the next four clock cycles in the same operation write the WDP bits as desired but with the WDCE bit cleared The value written to the WDE bit is irrelevant AMEL s Interrupts Interrupt Vectors in AMEL This section describes the specifics of the interrupt handling performed by the ATmega8 For a general explanation of the AVR interrupt handling refer to Reset and Interrupt Handling on page 14 ATmega8 Table 18 Reset and Interrupt Vectors Program Vector No Address Source Interrupt Definition 1 Ox000 RESET External Pin Power on Reset Brown out Reset and Watchdog Reset 2 0x001 INTO External Interrupt Request 0 3 0x002 INT1 External Interrupt Request 1 4 0x003 TIMER2 COMP Timer Counter2 Compare Match 5 0x004 TIMER2 OVF Timer Counter2 Overflow 6 0x005 TIMER1 CAPT Timer Counter1 Capture
313. ox thus the low time requirement will not be strictly met for fgg gt 308 kHz when fox 8 MHz Still ATmega8 devices connected to the bus may communicate at full speed 400 kHz with other ATmega8 devices as well as any other device with a proper t oy acceptance margin Figure 115 Two wire Serial Bus Timing che HIGH gt N tlow SCL ISUSTA lt e gt HD STA HD DAT lt gt lt gt tsy DAT e gt SDA 3 1 tgur SPI Timing See Figure 116 and Figure 117 for details Characteristics D Table 102 SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 50 2 SCK high low Master 50 duty cycle 3 Rise Fall time Master 3 6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0 5 tec 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 tok ns 11 SCK high low Slave 2e tok 12 Rise Fall time Slave 1 6 13 Setup Slave 10 14 Hold Slave 10 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri state Slave 10 18 SS low to SCK Salve 2e tok Note 1 In SPI Programming mode the minimum SCK high low period is 2tpi ci for fc lt 12 MHz Stai ci for fox gt 12 MHz 246 ATmegae8 L EEE __ 2486R AVR 07 07 ATmega8 L Figure 116 SPI interface timing requirements Master Mode
314. parity checking was enabled at that point UPM1 1 This bit is valid until the receive buffer UDR is read In contrast to the Transmitter disabling of the Receiver will be immediate Data from ongoing receptions will therefore be lost When disabled i e the RXEN is set to zero the Receiver will no longer override the normal function of the RxD port pin The Receiver buffer FIFO will be flushed when the Receiver is disabled Remaining data in the buffer will be lost The Receiver buffer FIFO will be flushed when the Receiver is disabled i e the buffer will be emptied of its contents Unread data will be lost If the buffer has to be flushed during normal operation due to for instance an error condition read the UDR I O loca tion until the RXC Flag is cleared The following code example shows how to flush the receive buffer Assembly Code Example USART Flush sbis UCSRA RXC ret in r16 UDR rjmp USART_Flush C Code Example void USART_Flush void unsigned char dummy while UCSRA amp 1 lt lt RXC dummy UDR Note 1 See About Code Examples on page 8 The USART includes a clock recovery and a data recovery unit for handling asynchro nous data reception The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin The data recovery logic samples and low pass filters each incoming bit there
315. pin minus 1 LSB Optionally AVcc or an internal 2 56V refer ence voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity The analog input channel is selected by writing to the MUX bits in ADMUX Any of the ADC input pins as well as GND and a fixed bandgap voltage reference can be selected as single ended inputs to the ADC The ADC is enabled by setting the ADC Enable bit ADEN in ADCSRA Voltage reference and input channel selections will not go into effect until ADEN is set The ADC does not consume power when ADEN is cleared so it is recommended to switch off the ADC before entering power saving sleep modes The ADC generates a 10 bit result which is presented in the ADC Data Registers ADCH and ADCL By default the result is presented right adjusted but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX AMEL 197 2486R AVR 07 07 Starting a Conversion Prescaling and Conversion Timing AMEL If the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH to ensure that the content of the Data Registers belongs to the same conversion Once ADCL is read ADC access to Data Registers is blocked This means that if ADCL has been read and a conversion completes
316. pply when External Crystal or External RC configuration is selected because it is not possible to apply qual ified XTAL1 pulses In such cases the following algorithm should be followed 1 Set Prog enable pins listed in Table 92 on page 227 to 0000 2 Apply 4 5 5 5V between Vcc and GND simultaneously as 11 5 12 5V is applied to RESET 3 Wait 100 ns 4 Re program the fuses to ensure that External Clock is selected as clock source CKSEL3 0 0 b0000 and RESET pin is activated RSTDISBL unprogrammed If Lock Bits are programmed a chip erase command must be executed before changing the fuses 5 Exit Programming mode by power the device down or by bringing RESET pin to O bO 6 Entering Programming mode with the original algorithm as described above The loaded command and address are retained in the device during programming For efficient programming the following should be considered e The command needs only be loaded once when writing or reading multiple memory locations e Skip writing the data value OxFF that is the contents of the entire EEPROM unless the EESAVE Fuse is programmed and Flash after a Chip Erase e Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM This consideration also applies to Signature bytes reading The Chip Erase will erase the Flash and EEPROM memories plus Lock Bits The Lock Bits are not reset until t
317. pt Mask Register TIMSK TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units The Timer Counter can be clocked internally via the prescaler or asynchronously clocked from the TOSC1 2 pins as detailed later in this section The asynchronous operation is controlled by the Asynchronous Status Register ASSR The Clock Select logic block controls which clock source the Timer Counter uses to increment or decre ment its value The Timer Counter is inactive when no clock source is selected The output from the clock select logic is referred to as the timer clock clk The double buffered Output Compare Register OCR2 is compared with the Timer Counter value at all times The result of the compare can be used by the wave form generator to generate a PWM or variable frequency output on the Output Compare Pin OC2 For details see Output Compare Unit on page 107 The Compare Match event will also set the Compare Flag OCF2 which can be used to generate an Output Compare interrupt request Many register and bit references in this document are written in general form A lower case n replaces the Timer Counter number in this case 2 However when using the register or bit defines in a program the precise form must be used i e TCNT2 for accessing Timer Counter2 counter value and so on The definitions in Table 41 are also used extensively throughout the document Table 41 Definitions BO
318. pull ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins as explained in the I O Port section The internal pull ups can in some systems eliminate the need for external ones AMEL 169 2486R AVR 07 07 Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit AMEL This unit controls the period of SCL when operating in a Master mode The SCL period is controlled by settings in the TWI Bit Rate Register TWBR and the Prescaler bits in the TWI Status Register TWSR Slave operation does not depend on Bit Rate or Pres caler settings but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency Note that slaves may prolong the SCL low period thereby reducing the average TWI bus clock period The SCL frequency is generated according to the following equation CPU Clock frequency SCL frequency TWPS 16 2 TWBR 4 e TWBR Value of the TWI Bit Rate Register e TWPS Value of the prescaler bits in the TWI Status Register Note Pull up resistor values should be selected according to the SCL frequency and the capacitive bus line load See Table 101 on page 245 for value of pull up resistor This unit contains the Data and Address Shift Register TWDR a START STOP Con troller and Arbitration detection hardware The TWDR contains the address or data bytes to be transmitted or the address or data bytes received In additio
319. r Support provides a real Read While Write Self Programming mecha nism for downloading and uploading program code by the MCU itself This feature allows flexible application software updates controlled by the MCU using a Flash resi dent Boot Loader program The Boot Loader program can use any available data interface and associated protocol to read code and write program that code into the Flash memory or read the code from the Program memory The program code within the Boot Loader section has the capability to write into the entire Flash including the Boot Loader Memory The Boot Loader can thus even modify itself and it can also erase itself from the code if the feature is not needed anymore The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently This gives the user a unique flexibility to select different levels of protection Read While Write Self Programming Flexible Boot Memory Size High Security Separate Boot Lock Bits for a Flexible Protection Separate Fuse to Select Reset Vector Optimized Page Size Code Efficient Algorithm Efficient Read Modify Write Support Note 1 A page is a section in the Flash consisting of several bytes see Table 89 on page 225 used during programming The page organization does not affect normal operation The Flash memory is organized in two main sections the Application section and the Boot
320. r together with the frame for which they indicate the error status Due to the buffering of the error flags the UCSRA must be read before the receive buffer UDR since reading the UDR I O location changes the buffer read location Another equality for the error flags is that they can not be altered by software doing a write to the flag location However all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations None of the error flags can generate interrupts The Frame Error FE Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer The FE Flag is zero when the stop bit was correctly read as one and the FE Flag will be one when the stop bit was incorrect zero This flag can be used for detecting out of sync conditions detecting break conditions and protocol handling The FE Flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all except for the first stop bits For compatibility with future devices always set this bit to zero when writing to UCSRA The Data OverRun DOR Flag indicates data loss due to a Receiver buffer full condi tion A Data OverRun occurs when the receive buffer is full two characters it is a new character waiting in the Receive Shift Register and a new start bit is detected If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR and
321. rO The Timer Counter can be clocked directly by the system clock by setting the CSn2 0 1 This provides the fastest operation with a maximum Timer Counter clock frequency equal to system clock frequency fc o Alternatively one of four taps from the pres caler can be used as a clock source The prescaled clock has a frequency of either fork uo 8 fci vo 64 fork vo 256 or fork 9 1024 The prescaler is free running i e operates independently of the clock select logic of the Timer Counter and it is shared by Timer Counter1 and Timer CounterO Since the pres caler is not affected by the Timer Counter s clock select the state of the prescaler will have implications for situations where a prescaled clock is used One example of pres caling artifacts occurs when the timer is enabled and clocked by the prescaler 6 CSn2 0 1 The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N 1 system clock cycles where N equals the prescaler divisor 8 64 256 or 1024 It is possible to use the prescaler reset for synchronizing the Timer Counter to program execution However care must be taken if the other Timer Counter that shares the same prescaler also uses prescaling A prescaler reset will affect the prescaler period for all Timer Counters it is connected to An external clock source applied to the T1 TO pin can be used as Timer Counter clock clKky clkz9 The T1 TO pin is sa
322. ram Memory Ready Handler 013 RESET ldi r16 high RAMEND Main program start 014 out SPH r16 Set Stack Pointer to top of RAM 015 ldi r16 10w RAMEND 016 out SPL r16 017 sei Enable interrupts 018 lt instr gt xxx AMEL 47 AMEL When the BOOTRST Fuse is unprogrammed the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled the most typical and general program setup for the Reset and Interrupt Vector Addresses is AddressLabels Code Comments 000 rjmp RESET Reset handler 001 RESET 1di r16 high RAMEND Main program start 002 out SPH r16 Set Stack Pointer to top of RAM 003 ldi r16 1ow RAMEND 004 out SPL r16 005 sei Enable interrupts 006 instr xxx org c01 c01 rjmp EXT INTO IRQO Handler c02 rjmp EXT INT1 IRQ1 Handler c12 rjmp SPM RDY Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the boot section size set to 2K bytes the most typical and general program setup for the Reset and Interrupt Vector Addresses is AddressLabels Code Comments org 001 001 rjmp EXT INTO IRQO Handler 002 rjmp EXT INT1 IRQ1 Handler 012 rjmp SPM RDY Store Program Memory Ready Handler org c00 c00 rjmp RESET Reset handler c01 RESET 1di r16 high RAMEND Main program start c02 out SPH r16 Set Stack Pointer to top of RAM c03 ldi r16 10ow RAMEND c04 out SPL r16
323. rated on the Output Compare Outputs OC1x For more details about advanced counting sequences and waveform generation see Modes of Opera tion on page 88 The Timer Counter Overflow TOV1 fLag is set according to the mode of operation selected by the WGM13 0 bits TOV1 can be used for generating a CPU interrupt Input Capture Unit The Timer Counter incorporates an Input Capture unit that can capture external events and give them a time stamp indicating time of occurrence The external signal indicating an event or multiple events can be applied via the ICP1 pin or alternatively via the Analog Comparator unit The time stamps can then be used to calculate frequency duty cycle and other features of the signal applied Alternatively the time stamps can be used for creating a log of the events The Input Capture unit is illustrated by the block diagram shown in Figure 34 The ele ments of the block diagram that are not directly a part of the Input Capture unit are gray shaded The small n in register and bit names indicates the Timer Counter number Figure 34 Input Capture Unit Block Diagram DATA BUS 8 bit J NEM REN EN romeo TENTAL ea WRITE ICRn 16 bit Register TCNTn 16 bit Counter i Analog ACIC ICNC ICES Comparator Noise Edge gt ICFn Int Req ICPn When a change of the logic level an event occurs on the nput Capture Pin ICP1 alternatively on the Analog Comp
324. re the Interrupt Flag used as trigger source is cleared When updating ADMUX in one of these conditions the new settings will affect the next ADC conversion 0 ATmega8 L memm 2486R AVR 07 07 f mega8 L ADC Input Channels ADC Voltage Reference ADC Noise Canceler 2486R AVR 07 07 When changing channel selections the user should observe the following guidelines to ensure that the correct channel is selected In Single Conversion mode always select the channel before starting the conversion The channel selection may be changed one ADC clock cycle after writing one to ADSC However the simplest method is to wait for the conversion to complete before changing the channel selection In Free Running mode always select the channel before starting the first conversion The channel selection may be changed one ADC clock cycle after writing one to ADSC However the simplest method is to wait for the first conversion to complete and then change the channel selection Since the next conversion has already started automati cally the next result will reflect the previous channel selection Subsequent conversions will reflect the new channel selection The reference voltage for the ADC Vgge indicates the conversion range for the ADC Single ended channels that exceed Vper will result in codes close to OXSFF Vref can be selected as either AVcc internal 2 56V reference or external AREF pin AVcc is connecte
325. reaches zero This clock is the baud rate generator clock output fosc UBRR 1 The Transmitter divides the baud rate generator clock output by 2 8 or 16 depending on mode The baud rate generator output is used directly by the Receiver s clock and data recovery units However the recovery units use a state machine that uses 2 8 or 16 states depending on mode set by the state of the UMSEL U2X and DDR XCK bits Table 52 contains equations for calculating the baud rate in bits per second and for calculating the UBRR value for each mode of operation using an internally generated clock source AMEL 135 Double Speed Operation U2X External Clock AMEL Table 52 Equations for Calculating Baud Rate Register Setting Equation for Calculating Equation for Calculating Operating Mode Baud Rate UBRR Value Asynchronous Normal mode f f U2X 0 BAUD 93 UBRR O3C 16 UBRR 1 16BAUD Asynchronous Double Speed f f Mode U2X 1 BAUD 25C UBRR 98C _ 1 8 UBRR 1 8BAUD Synchronous Master Mode f f BAUD 2C UBRR O3C _ 2 UBRR 1 2BAUD Note 1 The baud rate is defined to be the transfer rate in bit per second bps BAUD Baud rate in bits per second bps fosc System Oscillator clock frequency UBRR Contents of the UBRRH and UBRRL Registers 0 4095 Some examples of UBRR values for some system clock frequencies are found in Table 60 see p
326. read as zero when reading UBRRH The URSEL must be zero when writing the UBRRH Bit 14 12 Reserved Bits These bits are reserved for future use For compatibility with future devices these bit must be written to zero when UBRRH is written Bit 11 0 UBRR11 0 USART Baud Rate Register This is a 12 bit register which contains the USART baud rate The UBRRH contains the four most significant bits and the UBRRL contains the eight least significant bits of the USART baud rate Ongoing transmissions by the Transmitter and Receiver will be cor rupted if the baud rate is changed Writing UBRRL will trigger an immediate update of the baud rate prescaler ATmega8 L memm 2486R AVR 07 07 m Amega8 L Examples of Baud Rate Setting For standard crystal and resonator frequencies the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 60 UBRR values which yield an actual baud rate differing less than 0 596 from the target baud rate are bold in the table Higher error ratings are acceptable but the Receiver will have less noise resistance when the error ratings are high especially for large serial frames see Asynchronous Operational Range on page 149 The error values are cal culated using the following equation BaudRate Error p Maten 1 e 100 Table 60 Examples of UBRR Settings for Commonly Used
327. resumes execution from the instruction following SLEEP e Reading of the TCNT2 Register shortly after wake up from Power save may give an incorrect result Since TCNT2 is clocked on the asynchronous TOSC clock reading TCNT2 must be done through a register synchronized to the internal I O clock domain Synchronization takes place for every rising TOSC1 edge When waking up from Power save mode and the I O clock clkyo again becomes active TCNT2 will read as the previous value before entering sleep until the next rising TOSC1 edge The phase of the TOSC clock after waking up from Power save mode is essentially unpredictable as it depends on the wake up time The recommended procedure for reading TCNT2 is thus as follows 1 Write any value to either of the registers OCR2 or TCCR2 2 Wait for the corresponding Update Busy Flag to be cleared 3 Read TCNT2 e During asynchronous operation the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock AMEL 121 2486R AVR 07 07 Timer Counter Interrupt Mask Register TIMSK Timer Counter Interrupt Flag Register TIFR AMEL Bit 7 6 5 4 3 2 1 0 ocea 7 oz noer Tocem oce ToT
328. reviously addressed with Read data byte or X 0 1 0 Data byte will be received and NOT ACK will be general call data has been re returned ceived ACK has been returned Read data byte 0 1 1 Data byte will be received and ACK will be returned 0x98 Previously addressed with Read data byte or 0 0 1 0 Switched to the not addressed Slave mode general call data has been no recognition of own SLA or GCA received NOT ACK has been Read data byte or 0 0 1 1 Switched to the not addressed Slave mode returned own SLA will be recognized GCA will be recognized if TWGCE 1 Read data byte or 1 0 1 0 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free Read data byte 1 0 1 1 Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the bus becomes free OxA0 A STOP condition or repeated No action 0 0 1 0 Switched to the not addressed Slave mode START condition has been no recognition of own SLA or GCA received while still addressed as 0 0 1 1 Switched to the not addressed Slave mode Slave own SLA will be recognized GCA will be recognized if TWGCE 1 1 0 1 0 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free 1 0 1 1 Switched to the not addressed Slave mode own SLA will be rec
329. rigger even if the INTO 1 pins are configured as outputs This feature provides a way of generating a software interrupt The external interrupts can be triggered by a falling or rising edge or a low level This is set up as indicated in the specification for the MCU Control Register MCUCR When the external interrupt is enabled and is configured as level triggered the interrupt will trigger as long as the pin is held low Note that recognition of falling or rising edge interrupts on INTO and INT1 requires the presence of an I O clock described in Clock Systems and their Distribu tion on page 25 Low level interrupts on INTO INT1 are detected asynchronously This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode The I O clock is halted in all sleep modes except Idle mode Note that if a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time to wake up the MCU This makes the MCU less sensitive to noise The changed level is sampled twice by the Watchdog Oscillator clock The period of the Watchdog Oscillator is 1 us nominal at 5 0V and 25 C The frequency of the Watchdog Oscillator is voltage dependent as shown in Electrical Char acteristics on page 242 The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start up time The start up time is defined by the SUT Fuses as
330. riting this bit to one enables the USART Receiver The Receiver will override normal port operation for the RxD pin when enabled Disabling the Receiver will flush the receive buffer invalidating the FE DOR and PE Flags e Bit 3 TXEN Transmitter Enable Writing this bit to one enables the USART Transmitter The Transmitter will override nor mal port operation for the TxD pin when enabled The disabling of the Transmitter writing TXEN to zero will not become effective until ongoing and pending transmis sions are completed i e when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted When disabled the Transmitter will no longer override the TxD port Bit 2 UCSZ2 Character Size The UCSZ2 bits combined with the UCSZ1 0 bit in UCSRC sets the number of data bits Character Size in a frame the Receiver and Transmitter use Bit 1 RXB8 Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits Must be read before reading the low bits from UDR e Bit 0 TXB8 Transmit Data Bit 8 AMEL 155 USART Control and Status Register C UCSRC AMEL TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits Must be written before writing the low bits to UDR Bit 7 6 5 4 3 2 1 0 URSEL UMSEL UPMI USBS UCSZ1 UCSZO UCPOL UCSRC Read Write R W R W R
331. rrent vs Vcc Internal RC Oscillator 1 MHz ACTIVE SUPPLY CURRENT vs Voc INTERNAL RC OSCILLATOR 1 MHz 85 C 2 5 3 3 5 4 4 5 5 5 5 Voo V Figure 124 Active Supply Current vs Vcc 32 kHz External Oscillator ACTIVE SUPPLY CURRENT vs Vcc 32kHz EXTERNAL OSCILLATOR 120 100 25 C 80 60 8 40 20 0 2 5 3 3 5 4 4 5 5 5 5 Voc V ATmega8 L suum 2486R AVR 07 07 Almega8 L Idle Supply Current 2486R AVR 07 07 Figure 125 Idle Supply Current vs Frequency 0 1 1 0 MHz Icc mA loc mA 0 7 0 6 0 5 0 4 0 3 0 2 0 1 14 12 10 IDLE SUPPLY CURRENT vs FREQUENCY 0 1 1 0 MHz 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz Figure 126 Idle Supply Current vs Frequency 1 20 MHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20MHz 4 0V 3 3V 3 0 2 7V 2 4 6 8 10 12 14 16 18 AMEL Frequency MHz 20 5 5V 5 0V 4 5V 4 0V 3 3V 3 0V 2 7V 5 5V 5 0V 4 5V 253 254 AMEL Figure 127 Idle Supply Current vs Ve Internal RC Oscillator 8 MHz IDLE SUPPLY CURRENT vs Voc INTERNAL RC OSCILLATOR 8 MHz 40 C 25 C 85 C Icc mA Voc V Figure 128 Idle Supply Current vs Vcc Internal RC Oscillator 4 MHz IDLE SUPPLY CURRE
332. rsion im Sample amp Hold Complete MUX and REFS Update Table 73 ADC Conversion Time Sample amp Hold Cycles Conversion Time Condition from Start of Conversion Cycles Extended conversion 13 5 25 Normal conversions single ended 1 5 13 The MUXn and REFS1 0 bits in the ADMUX Register are single buffered through a tem porary register to which the CPU has random access This ensures that the channels and reference selection only takes place at a safe point during the conversion The channel and reference selection is continuously updated until a conversion is started Once the conversion starts the channel and reference selection is locked to ensure a sufficient sampling time for the ADC Continuous updating resumes in the last ADC clock cycle before the conversion completes ADIF in ADCSRA is set Note that the conversion starts on the following rising ADC clock edge after ADSC is written The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written If both ADFR and ADEN is written to one an interrupt event can occur at any time If the ADMUX Register is changed in this period the user cannot tell if the next conversion is based on the old or the new settings ADMUX can be safely updated in the following ways 1 When ADFR or ADEN is cleared 2 During conversion minimum one ADC clock cycle after the trigger event 3 After a conversion befo
333. rsion times see Table 73 Figure 92 ADC Timing Diagram First Conversion Single Conversion Mode First Conversion Conversion 4 15 16 17 18 19 20 21 22 23 24 25 t L4 L4 L N N o cones cm Cycle Number ADC Clock ADEN i i V E ES ADSC ADIF RV BITTE TH TTTTTTTELTLETITETTTTTELTUTTTTLTLTTIBTTITE SEES aoc ZZZ LETTE TLL 8 est um MUX and REFS A Conversion v xd TN qus an REFS Sample amp Hold Update Complete Figure 93 ADC Timing Diagram Single Conversion One Conversion Next Conversion lt lt Cycle Number 1 2 3 4 5 6 7 8 9 to 11 12 13 1 2 3 l l ADC Clock ALITY l l i 4 LI ADSC m VIT ADIF t H Z TL III MIEL LL MB of Result ADCL TII TIIVIIT y 7 7 7 LSB of Result YK Sample amp Hold Conversion ad E MUX and REFS MUX and REFS Complete Update Update AMEL 199 2486R AVR 07 07 Changing Channel or Reference Selection AMEL Figure 94 ADC Timing Diagram Free Running Conversion One Conversion Next Conversion l Cycle Number 11 12 13 1 2 3 4 acce PLT ALIS LT ADSC I t ADIF I ADCH VT B TTT Ti 1 MSB of Result I ADCL LSB ol Result I I Conve
334. rved bit and will always read as zero Bit0 TWIE TWI Interrupt Enable When this bit is written to one and the I bit in SREG is set the TWI interrupt request will be activated for as long as the TWINT Flag is high ATmega8 L m 2486R AVR 07 07 AT 11 C023 TWI Status Register TWSR TWI Data Register TWDR 2486R AVR 07 07 Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 TWPS1 TWPSO TWSR Read Write R R R R R R R W R W Initial Value 1 1 1 1 1 0 0 0 Bits 7 3 TWS TWI Status These 5 bits reflect the status of the TWI logic and the Two wire Serial Bus The differ ent status codes are described later in this section Note that the value read from TWSR contains both the 5 bit status value and the 2 bit prescaler value The application designer should mask the prescaler bits to zero when checking the Status bits This makes status checking independent of prescaler setting This approach is used in this datasheet unless otherwise noted e Bit2 Res Reserved Bit This bit is reserved and will always read as zero Bits 1 0 TWPS TWI Prescaler Bits These bits can be read and written and control the bit rate prescaler Table 65 TWI Bit Rate Prescaler TWPS1 TWPSO Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates see Bit Rate Generator Unit on page 170 The value of TWPS1 0 is used in the equation Bit 7 6 5 4
335. s the 16 bit registers refer to Accessing 16 bit Registers on page 79 The main trigger source for the Input Capture unit is the nput Capture Pin ICP1 Timer Counter 1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture unit The Analog Comparator is selected as trigger source by set ting the Analog Comparator Input Capture ACIC bit in the Analog Comparator Control and Status Register ACSR Be aware that changing trigger source can trigger a cap ture The Input Capture Flag must therefore be cleared after the change Both the nput Capture Pin ICP1 and the Analog Comparator Output ACO inputs are sampled using the same technique as for the T1 pin Figure 30 on page 74 The edge detector is also identical However when the noise canceler is enabled additional logic is inserted before the edge detector which increases the delay by four system clock cycles Note that the input of the noise canceler and edge detector is always enabled unless the Timer Counter is set in a Waveform Generation mode that uses ICR1 to define TOP An Input Capture can be triggered by software by controlling the port of the ICP1 pin The noise canceler improves noise immunity by using a simple digital filtering scheme The noise canceler input is monitored over four samples and all four must be equal for changing the output that in turn is used by the edge detector The noise canceler is enabled by setting the Input C
336. s used at other frequencies the calibration values must be loaded manually This can be done by first reading the signature row by a programmer and then store the calibration values in the Flash or EEPROM Then the value can be read by software and loaded into the OSCCAL Register When OSCCAL is zero the lowest available frequency is chosen Writing non zero values to this register will increase the frequency of the Internal Oscillator Writing OxFF to the register gives the highest available frequency The calibrated Oscillator is used to time EEPROM and Flash access If EEPROM or Flash is written do not calibrate to more than 10 above the nominal frequency Otherwise the EEPROM or Flash write may fail Note that the Oscillator is intended for calibration to 1 0 2 0 4 0 or 8 0 MHz Tuning to other values is not guaranteed as indicated in Table 11 Table 11 Internal RC Oscillator Frequency Range Min Frequency in Percentage of Max Frequency in Percentage of OSCCAL Value Nominal Frequency Nominal Frequency 96 0x00 50 100 Ox7F 75 150 OxFF 100 200 AMEL s External Clock Timer Counter Oscillator AMEL To drive the device from an external clock source XTAL1 should be driven as shown in Figure 13 To run the device on an external clock the CKSEL Fuses must be pro grammed to 0000 By programming the CKOPT Fuse the user can enable an internal 36 pF capacitor between XTAL1 and GND and XTAL2 and GN
337. sabled the CPU will access the OCR1x directly The content of the OCR1x Buffer or Compare Register is only changed by a write operation the Timer Counter does not update this register automatically as the TCNT1 and ICR1 Register Therefore OCR1x is not read via the High byte temporary register TEMP However it is a good practice to read the Low byte first as when accessing other 16 bit registers Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bit is done continuously The High byte OCR1xH has to be written first When the High byte I O location is written by the CPU the TEMP Register will be updated by the value writ ten Then when the Low byte OCR1xL is written to the lower eight bits the High byte will be copied into the upper 8 bits of either the OCR1x buffer or OCR1x Compare Reg ister in the same system clock cycle For more information of how to access the 16 bit registers refer to Accessing 16 bit Registers on page 79 In non PWM Waveform Generation modes the match output of the comparator can be forced by writing a one to the Force Output Compare FOC1x bit Forcing Compare Match will not set the OCF1x Flag or reload clear the timer but the OC1x pin will be updated as if a real Compare Match had occurred the COM1x1 0 bits settings define whether the OC1x pin is set cleared or toggled All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer
338. scillator Problem Fix Workaround Ensure that the chiperase command has exceeded before applying the next command CKOPT Does not Enable Internal Capacitors on XTALn TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer Counter2 When the internal RC Oscillator is used as the main clock source it is possible to run the Timer Counter2 asynchronously by connecting a 32 KHz Oscillator between XTAL1 TOSC1 and XTAL2 TOSC2 But when the internal RC Oscillator is selected as the main clock source the CKOPT Fuse does not control the internal capacitors on XTAL1 TOSC1 and XTAL2 TOSC2 As long as there are no capacitors con nected to XTAL1 TOSC1 and XTAL2 TOSC2 safe operation of the Oscillator is not guaranteed Problem fix Workaround Use external capacitors in the range of 20 36 pF on XTAL1 TOSC1 and XTAL2 TOSC2 This will be fixed in ATmega8 Rev G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source For ATmega8 Rev G CKOPT 0 programmed will enable the internal capacitors on XTAL1 and XTAL2 Customers who want compatibility between Rev G and older revisions must ensure that CKOPT is unprogrammed CKOPT 1 26 ATmega8 L m 2486R AVR 07 07 iu A megae8 L Datasheet Revision History Changes from Rev 2486Q 10 06 to Rev 2486R 07 07 Changes from Rev 2486P 02 06 to Rev 2486Q 1
339. scillator Frequency vs Voc CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs Vcc 1 1 1 05 40 C F 25 C 1 o 85 C c iL 0 95 0 9 2 5 3 3 5 4 4 5 5 5 5 Voc V 0 ATmega8 L mmm B ATmega8 L Figure 181 Calibrated 1 MHz RC Oscillator Frequency vs Osccal Value CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE R 1 3 I 1 1 0 9 0 7 0 5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Current Consumption of Figure 182 Brown out Detector Current vs Voc Peripheral Units BROWN OUT DETECTOR CURRENT vs Voc 30 25 P 40 C 25 C 85 C 15 8 10 5 0 2 5 3 3 5 4 4 5 5 5 5 Vcc V AMEL 281 2486R AVR 07 07 AMEL Figure 183 ADC Current vs Voc AREF AV c ADC CURRENT vs Vcc AREF AVCC 450 400 25 C 350 300 250 Icc uA 200 150 100 50 Vcc V Figure 184 AREF External Reference Current vs Voc AREF EXTERNAL REFERENCE CURRENT vs Vcc 250 200 85 C 150 lcc uA 100 50 Vcc V 282 ATmega8 L memm 2486R AVR 07 07 Aimega8 L 2486R AVR 07 07 Figure 185 32 kHz TOSC Current vs Voc Watchdog Timer Disabled 32 kHz TOSC CURRENT vs Voc 55 WATCHDOG TIMER DISABLED 20 25 C lcc UA
340. selected Signature byte can now be read at DATA 4 Set OE to 1 Reading the Calibration Byte The algorithm for reading the Calibration bytes is as follows refer to Programming the Flash on page 229 for details on Command and Address loading 1 A Load Command 0000 1000 2 B Load Address Low byte 0x00 0x03 3 Set OE to 0 and BS1 to 1 The Calibration byte can now be read at DATA 4 Set OE to 1 Parallel Programming Figure 109 Parallel Programming Timing Including some General Timing Characteristics Requirements txtwe XTAL1 Data amp Contol DATA XA0 1 BS1 BS2 PAGEL WR teLwe gt RDY BSY OK o e gt WLRH Figure 110 Parallel Programming Timing Loading Sequence with Timing Requirements LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS LOW BYTE LOW BYTE HIGH BYTE LOW BYTE mm mm m Oe mm t ba xn XL PH tPLXH XTAL1 BS1 PAGEL DATA ADDRO Low Byte DATA Low Byte DATA High Byte ADDR1 Low Byte XAO N d BN Note 1 The timing requirements shown in Figure 109 i e tpyxq txyxL and tj px also apply to loading operation 234 ATmega8 L memm X X X f megae8 L 2486R AVR 07 07 Figure 111 Parallel Programming Timing Reading Sequence within the same Page with Timing Requirements LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS LOW BYTE LOW BYTE HIGH BYTE LOW BYTE ooo ee aoa mm
341. served Note that the Status Register is not automatically stored when entering an interrupt rou tine nor restored when returning from an interrupt routine This must be handled by software When using the CLI instruction to disable interrupts the interrupts will be immediately disabled No interrupt will be executed after the CLI instruction even if it occurs simulta neously with the CLI instruction The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence Assembly Code Example in r16 SREG store SREG value cli disable interrupts during timed sequence sbiEECR EEMWE start EEPROM write sbi EECR EEWE out SREG r16 restore SREG value I bit C Code Example char cSREG CSREG SREG store SREG value disable interrupts during timed sequence CLI EECR 1 lt lt EEMWE start EEPROM write EECR 1 lt lt EEWE SREG cSREG restore SREG value I bit AMEL Interrupt Response Time AMEL When using the SEI instruction to enable interrupts the instruction following SEI will be executed before any pending interrupts as shown in the following example Assembly Code Example sei set global interrupt enable Sleep enter sleep waiting for interrupt note will enter sleep before any pending interrupt s C Code Example JS
342. setting the OC2 value is to use the Force Out put Compare FOC2 strobe bit in Normal mode The OC2 Register keeps its value even when changing between waveform generation modes Be aware that the COM21 0 bits are not double buffered together with the compare value Changing the COM21 0 bits will take effect immediately 108 ATmega8 L mmm 2486R AVR 07 07 f mega8 L Compare Match Output Unit 2486R AVR 07 07 The Compare Output mode COM21 0 bits have two functions The waveform genera tor uses the COM21 0 bits for defining the Output Compare OC2 state at the next Compare Match Also the COM21 0 bits control the OC2 pin output source Figure 48 shows a simplified schematic of the logic affected by the COM21 0 bit setting The I O Registers I O bits and I O pins in the figure are shown in bold Only the parts of the general I O Port Control Registers DDR and PORT that are affected by the COM21 0 bits are shown When referring to the OC2 state the reference is for the internal OC2 Register not the OC2 pin Figure 48 Compare Match Output Unit Schematic COMn1 COMno Waveform FOCn Generator DATABUS DDR Clk o The general I O port function is overridden by the Output Compare OC2 from the waveform generator if either of the COM21 0 bits are set However the OC2 pin direc tion input or output is still controlled by the Data Direction Register DDR for the port pin
343. sh byte by byte also the LSB bit ZO of the Z pointer is used 24 ATmega8 L memm 2486R AVR 07 07 ATmega8 L Figure 103 Addressing the Flash during SPM BIT 15 ZPCMSB ZPAGEMSB 1 0 PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM COUNTER WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD PAGEMSB 0 00 INSTRUCTION WORD 01 02 PAGEEND Notes 1 The different variables used in the figure are listed in Table 84 on page 221 2 PCPAGE and PCWORD are listed in Table 89 on page 225 Self Programming the The Program memory is updated in a page by page fashion Before programming a Flash page with the data stored in the temporary page buffer the page must be erased The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the page erase command or between a page erase and a page write operation Alternative 1 fill the buffer before a page erase Fill temporary page buffer e Perform a page erase e Perform a page write Alternative 2 fill the buffer after page erase e Perform a page erase Fill temporary page buffer Perform a page write If only a part of the page needs to be changed the rest of the page must be stored for example in the temporary page buffer before the erase and then be rewritten When using alternative 1 the boot loader provides an effective Read Modify Write
344. siissecsu aas duse vv hed unda os duRR ESSE aa dins 17 In System Reprogrammable Flash Program Memory seeeeseeee 17 SRAM Data Memoly ctetu pee ftt ba eed ade Eid eee ak eec E bee gun 18 Data Memory Access Times seeesesssssseeseeeeeeneee nennen nennen nnne 19 EEPROM Data Memory sssssssesssseeeeeneeeenneen nennen nnns ennt e nnne rennen 19 lean Em 24 System Clock and Clock Options eese 25 Clock Systems and their Distribution ssseseeseeeeeeene 25 eller dero 26 Crystal Oscillator seessssssssesseeseeeeeee nennen 27 Low frequency Crystal Oscillator sssseseseeeeeeeneennenne 28 External RC Oscillator essen nennen 29 Calibrated Internal RC Oscillator ssseseeeenneennennn 30 External ClOCK d 32 Timer Co nter Oscillator niet rt anaia iaaa 32 Power Management and Sleep Modes 33 Idle MOdG t Rte t i ee et E eeu Deer Po HE a 34 ADC Noise Reduction Mode sssssssssssseeeeeeeeeeeen nennen nennen 34 Power down Mode i c d e e E RE eie ye eH ave 34 AIMED AMEL Power save MOde t rte eder ata OaE S E Ra NEERA 34 Standby MOde e ero et ete RE ce etie tee Doe da is 35 Minimizing Power Consumption ssessssseseseeeeeeeeeeeenmenen nennen 35 S
345. sing the Boot Loader 1 1 1 section 2 1 0 SPM is not allowed to write to the Boot Loader section SPM is not allowed to write to the Boot Loader section and LPM executing from the Application section is not allowed to read 3 0 0 from the Boot Loader section If Interrupt Vectors are placed in the Application section interrupts are disabled while executing from the Boot Loader section LPM executing from the Application section is not allowed to read from the Boot Loader section If Interrupt Vectors are placed in the Application section interrupts are disabled while executing from the Boot Loader section Note 1 1 means unprogrammed 0 means programmed Entering the Boot Loader takes place by a jump or call from the application program This may be initiated by a trigger such as a command received via USART or SPI inter face Alternatively the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset In this case the Boot Loader is started after a reset After the application code is loaded the program can start execut ing the application code Note that the fuses cannot be changed by the MCU itself This means that once the Boot Reset Fuse is programmed the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface 2 ATmega8 L m m
346. so wait for any ongoing SPM command to finish Assembly Code Example EEPROM write Wait for completion of previous write Sbic EECR EEWE rjmp EEPROM write Set up address r18 r17 in address register out EEARH r18 out EEARL r17 Write data r16 to data register out EEDR r16 Write logical one to EEMWE sbi EECR EEMWE Start eeprom write by setting EEWE sbi EECR EEWE ret C Code Example void EEPROM write unsigned int uiAddress unsigned char ucData Wait for completion of previous write while EECR amp 1 EEWE Set up address and data registers EEAR uiAddress EEDR ucData Write logical one to EEMWE EECR 1 lt lt EEMWE Start eeprom write by setting EEWE EECR 1 lt lt EEWE j 22 ATmegae8 L T 2486R AVR 07 07 A 11 C025 The next code examples show assembly and C functions for reading the EEPROM The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions Assembly Code Example EEPROM_read Wait for completion of previous write Sbic EECR EEWE rjmp EEPROM read Set up address r18 r17 in address register out EEARH r18 out EEARL r17 Start eeprom read by writing EERE sbi EECR EERE Read d
347. source to be running After all reset sources have gone inactive a delay counter is invoked stretching the internal reset This allows the power to reach a stable level before normal operation starts The time out period of the delay counter is defined by the user through the CKSEL Fuses The different selections for the delay period are presented in Clock Sources on page 26 The ATmega8 has four sources of Reset e Power on Reset The MCU is reset when the supply voltage is below the Power on Reset threshold Vpo e External Reset The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length e Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled e Brown out Reset The MCU is reset when the supply voltage Vec is below the Brown out Reset threshold Vgo7 and the Brown out Detector is enabled AMEL s 38 AMEL Figure 14 Reset Logic BODEN eae BODLEVEL Reset Circuit DATA BUS MCU Control and Status Register MCUCSR PORF BOR EXTRF WDRF vec Power On Reset Circuit Pull up Resistor SPIKE Sas RESET Reset Circuit Watchdog Timer COUNTER RESET 4 o o INTERNAL RESET Watchdog Oscillator Clock Generator CKSEL 3 0 SUT 1 0 TIMEOUT Delay Counters Table 15 Reset Characteristics
348. sssseseeeeeeeeenenen nene 82 COUNTER UNM e 82 Input Capture Uni ier te t ERE Gabe ee te Eas sees 83 Output Compare Uhiits corriere eerte ce aa aaa Een 85 Compare Match Output Unit ennt 87 Modes of Operation e au eei LU puta dera Ug ce awed 88 Timer Counter Timing Diagrams esssssseeeeeneeneennenenneen nennen 95 16 bit Timer Counter Register Description ssseeeneee 97 8 bit Timer Counter2 with PWM and Asynchronous Operation 104 e M H uuu 104 Timer Counter Clock SOUICES ccccceecccceeseeeececeeeseeeeeeseuseeuueseeeeeseuaeeeeeeeeeeaas 105 Counter ribs cases a E aa Ea RUDI NN DN Di DeL aia 106 2486R AVR 07 07 2486R AVR 07 07 Output Compare Uri e tact cete pra ce b o eere dn 107 Compare Match Output Unit eene nennen nnne 109 Modes of Operation ieri tann e ese ede ences Loa HELL o Su RE 110 Timer Counter Timing Diagrams essssssseeeeeeeneeneennneen nnns 115 8 bit Timer Counter Register Description sssseeeeeee 117 Asynchronous Operation of the Timer Counter ssseseeesss 119 Timer Counter Prescaler cnt rre cen eb ek Ru XE RR e peg 123 Serial Peripheral Interface SPl c ccrerrs 124 SS PiriFuibighialilyssa srs sina ounce capa ee a E a TM EIDEE 129 pw rcse c
349. t Capture Edge Select This bit selects which edge on the Input Capture Pin ICP1 that is used to trigger a cap ture event When the ICES1 bit is written to zero a falling negative edge is used as trigger and when the ICES1 bit is written to one a rising positive edge will trigger the capture When a capture is triggered according to the ICES1 setting the counter value is copied into the Input Capture Register ICR1 The event will also set the Input Capture Flag ICF1 and this can be used to cause an Input Capture Interrupt if this interrupt is enabled When the ICR1 is used as TOP value see description of the WGM13 0 bits located in the TCCR1A and the TCCR1B Register the ICP1 is disconnected and consequently the Input Capture function is disabled Bit 5 Reserved Bit This bit is reserved for future use For ensuring compatibility with future devices this bit must be written to zero when TCCR1B is written Bit 4 3 C WGM13 2 Waveform Generation Mode See TCCR1A Register description Bit 2 0 CS12 0 Clock Select The three clock select bits select the clock source to be used by the Timer Counter see Figure 41 and Figure 42 Table 40 Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source Timer Counter stopped 0 0 1 clkyo 1 No prescaling 0 1 0 clkyo 8 From prescaler 0 1 1 Clkyo 64 From prescaler 1 0 0 clkyo 256 From prescaler 1
350. t Rln RE Ek xx exa URN Ud un dS RUNE 293 BOA 293 ll 294 SA T ETAN 295 AS RW T 296 ATmega8 PROV sD tO E oci erede hir ET ceu NA Psp e RR RRPENE RR MA D DN ANDRE 296 2486R AVR 07 07 2486R AVR 07 07 Table of Contents AmE Datasheet Revision History sssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 297 Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev Changes from Rev 2486Q 10 06 to Rev 2486R 07 07 essss 297 2486P 02 06 to Rev 2486Q 10 06 297 24860 10 04 to Rev 2486P 02 06 s 297 2486N 09 04 to Rev 24860 10 04 esses 297 2486M 12 03 to Rev 2486N 09 04 ssis 298 2486L 10 03 to Rev 2486M 12 03 sessss 298 2486K 08 03 to Rev 2486L 10 08 sss 298 2486J 02 03 to Rev 2486K 08 03 sess 299 24861 12 02 to Rev 2486J 02 03 sese 299 2486H 09 02 to Rev 24861 12 02 sess 300 2486G 09 02 to Rev 2486H 09 02
351. t can be accessed by the AVR CPU via the 8 bit data bus The 16 bit register must be byte accessed using two read or write operations The 16 bit timer has a single 8 bit register for temporary storing of the High byte of the 16 bit access The same temporary register is shared between all 16 bit registers within the 16 bit timer Accessing the Low byte triggers the 16 bit read or write operation When the Low byte of a 16 bit register is written by the CPU the High byte stored in the temporary register and the Low byte written are both copied into the 16 bit register in the same clock cycle When the Low byte of a 16 bit register is read by the CPU the High byte of the 16 bit register is copied into the temporary register in the same clock cycle as the Low byte is read Not all 16 bit accesses uses the temporary register for the High byte Reading the OCR14A B 16 bit registers does not involve using the temporary register To do a 16 bit write the High byte must be written before the Low byte For a 16 bit read the Low byte must be read before the High byte The following code examples show how to access the 16 bit Timer Registers assuming that no interrupts updates the temporary register The same principle can be used directly for accessing the OCR1A B and ICR1 Registers Note that when using C the compiler handles the 16 bit access Assembly Code Example Set TCNT1 to Ox01FF 1dir17 0x01 1dir16 0xFF out TCNT1H r17 out T
352. t clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate The ADC module contains a prescaler which generates an acceptable ADC clock fre quency from any CPU frequency above 100 kHz The prescaling is set by the ADPS bits in ADCSRA The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA The prescaler keeps running for as long as the ADEN bit is set and is continuously reset when ADEN is low When initiating a single ended conversion by setting the ADSC bit in ADCSRA the con version starts at the following rising edge of the ADC clock cycle A normal conversion 198 ATmega8 L memm 2486R AVR 07 07 f mega8 L takes 13 ADC clock cycles The first conversion after the ADC is switched on ADEN in ADCSRA is set takes 25 ADC clock cycles in order to initialize the analog circuitry The actual sample and hold takes place 1 5 ADC clock cycles after the start of a normal conversion and 13 5 ADC clock cycles after the start of an first conversion When a con version is complete the result is written to the ADC Data Registers and ADIF is set In single conversion mode ADSC is cleared simultaneously The software may then set ADSC again and a new conversion will be initiated on the first rising ADC clock edge In Free Running mode a new conversion will be started immediately after the conver sion completes while ADSC remains high For a summary of conve
353. t in GICR are set one the MCU will jump to the cor responding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical one to it This flag is always cleared when INT1 is configured as a level interrupt Bit 6 INTFO External Interrupt Flag 0 When an event on the INTO pin triggers an interrupt request INTFO becomes set one If the I bit in SREG and the INTO bit in GICR are set one the MCU will jump to the cor responding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical one to it This flag is always cleared when INTO is configured as a level interrupt 68 ATmega8 L m I 2486R AVR 07 07 f megae8 L 8 bit Timer CounterO Overview Registers Definitions 2486R AVR 07 07 Timer CounterO is a general purpose single channel 8 bit Timer Counter module The main features are Single Channel Counter Frequency Generator External Event Counter 10 bit Clock Prescaler A simplified block diagram of the 8 bit Timer Counter is shown in Figure 26 For the actual placement of I O pins refer to Pin Configurations on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the 8 bit Timer Counter Register D
354. t mode instead of the Phase Correct mode when changing the TOP value while the Timer Counter is running When using a static TOP value there are practically no differences between the two modes of operation In phase correct PWM mode the compare units allow generation of PWM waveforms on the OC1x pins Setting the COM1x1 0 bits to 2 will produce a non inverted PWM and an inverted PWM output can be generated by setting the COM1x1 0 to 3 See Table 38 on page 98 The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output DDR OC1x The PWM waveform is generated by set ting or clearing the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments and clearing or setting the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements The PWM frequency for the output when using phase correct PWM can be calculated by the following equation _ _ Fok yo focnxPCPWM 2 Ne TOP The N variable represents the prescaler divider 1 8 64 256 or 1024 The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values If OCR1A is used to define the TOP v
355. ta Direction Register controlling the SPI pins DD MOSI DD MISO and DD SCK must be replaced by the actual data direction bits for these pins E g if MOSI is placed on pin PB5 replace DD MOSI with DDB5 and DDR SPI with DDRB ATmega8 L memm 2486R AVR 07 07 f mmega8 L 2486R AVR 07 07 Assembly Code Example SPI MasterInit T Set MOSI and SCK output all others input ldi r17 1 DD MOSI 1 DD SCK out DDR SPI r17 Enable SPI Master set clock rate fck 16 ldi r17 1 SPE 1 MSTR 1 lt lt SPRO out SPCR r17 ret SPI MasterTransmit H Start transmission of data r16 out SPDR r16 Wait Transmit f Wait for transmission complete sbis SPSR SPIF rjmp Wait_Transmit ret C Code Example void SPI MasterInit void Set MOSI and SCK output all others input DDR SPI 1 DD MOSI 1 DD SCK Enable SPI Master set clock rate fck 16 SPCR 1 lt lt SPE 1 lt lt MSTR 1 SPRO void SPI _MasterTransmit char cData Start transmission SPDR cData Wait for transmission complete while SPSR amp 1 lt lt SPIF 1 Note 1 See About Code Examples on page 8 AMEL 127 128 AMEL The following code examples show how to initialize the SPI as a Slave and how to per form a simple reception Assembly Code Example SPI Sla
356. ta Register Empty UDRE Flag When using frames with less than eight bits the most significant bits written to the UDR are ignored The USART has to be initialized before the function can be used For the assembly code the data to be sent is assumed to be stored in Register R16 Assembly Code Example USART Transmit Wait for empty transmit buffer Sbis UCSRA UDRE rjmp USART Transmit Put data r16 into buffer sends the data out UDR r16 ret C Code Example void USART Transmit unsigned char data Wait for empty transmit buffer while UCSRA amp 1 UDRE Put data into buffer sends the data UDR data Note 1 See About Code Examples on page 8 The function simply waits for the transmit buffer to be empty by checking the UDRE Flag before loading it with new data to be transmitted If the Data Register Empty Inter rupt is utilized the interrupt routine writes the data into the buffer 140 ATmega8 L mmm 2486R AVR 07 07 f 11 C025 Sending Frames with 9 Data Bits Transmitter Flags and Interrupts 2486R AVR 07 07 If 9 bit characters are used UCSZ 7 the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR The following code examples show a transmit function that handles 9 bit characters For the assembly code the data to be sent is assumed to be stored in registers R17
357. tage is too low EEPROM data corruption can easily be avoided by following this design recommendation AMEL 2 2486R AVR 07 07 l O Memory AMEL Keep the AVR RESET active low during periods of insufficient power supply volt age This can be done by enabling the internal Brown out Detector BOD If the detection level of the internal BOD does not match the needed detection level an external low Vcc Reset Protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient The I O space definition of the ATmega8 is shown in on page 287 All ATmega8 I Os and peripherals are placed in the I O space The I O locations are accessed by the IN and OUT instructions transferring data between the 32 general pur pose working registers and the I O space I O Registers within the address range 0x00 Ox1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions Refer to the instruction set section for more details When using the I O specific commands IN and OUT the I O addresses 0x00 Ox3F must be used When addressing I O Registers as data space using LD and ST instructions OX20 must be added to these addresses For compatibility with future devices reserved bits should be written to zero if accessed Reserved I
358. te R R R R R W R W R W R W Initial Value 0 0 0 0 See Bit Description Bit 7 4 Res Reserved Bits These bits are reserved bits in the ATmega8 and always read as zero Bit3 WDRF Watchdog Reset Flag This bit is set if a Watchdog Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 2 BORF Brown out Reset Flag This bit is set if a Brown out Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 1 EXTRF External Reset Flag This bit is set if an External Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 0 PORF Power on Reset Flag This bit is set if a Power on Reset occurs The bit is reset only by writing a logic zero to the flag To make use of the Reset Flags to identify a reset condition the user should read and then reset the MCUCSR as early as possible in the program If the register is cleared before another reset occurs the source of the reset can be found by examining the Reset Flags AMEL n Internal Voltage Reference Voltage Reference Enable Signals and Start up Time 42 AMEL 1 When the BOD is enabled by programming the BODEN Fuse 2 When the bandgap reference is connected to the Analog Comparator by setting the ACBG bit in ACSR 3 When the ADC is enabled Thus when the BOD is not enabled after setting the ACBG bit or enabling the ADC the user
359. te as a circular FIFO buffer Therefore the UDR must only be read once for each incoming data More important is the fact that the Error Flags FE and DOR and the ninth data bit RXB8 are buffered with the data in the receive buffer Therefore the status bits must always be read before the UDR Register is read Otherwise the error status will be lost since the buffer state is lost e The Receiver Shift Register can now act as a third buffer level This is done by allowing the received data to remain in the serial Shift Register see Figure 61 if the Buffer Registers are full until a new start bit is detected The USART is therefore more resistant to Data OverRun DOR error conditions The following control bits have changed name but have same functionality and register location e CHR9 is changed to UCSZ2 e ORis changed to DOR The clock generation logic generates the base clock for the Transmitter and Receiver The USART supports four modes of clock operation normal asynchronous double speed asynchronous Master synchronous and Slave Synchronous mode The UMSEL bit in USART Control and Status Register C UCSRC selects between asynchronous and synchronous operation Double speed Asynchronous mode only is controlled by the U2X found in the UCSRA Register When using Synchronous mode UMSEL 1 the Data Direction Register for the XCK pin DDR XCK controls whether the clock source is internal Master mode or external Slave mode T
360. ted e Bit 6 TOV2 Timer Counter2 Overflow Flag The TOV2 bit is set one when an overflow occurs in Timer Counter2 TOV2 is cleared by hardware when executing the corresponding interrupt Handling Vector Alternatively TOV2 is cleared by writing a logic one to the flag When the SREG I bit TOIE2 Timer Counter2 Overflow Interrupt Enable and TOV2 are set one the Timer Counter2 Overflow interrupt is executed In PWM mode this bit is set when Timer Counter2 changes counting direction at 0x00 122 ATlmega8 L mm 2486R AVR 07 07 Timer Counter Prescaler Special Function IO Register SFIOR 2486R AVR 07 07 ATmega8 L Figure 56 Prescaler for Timer Counter2 Kres gt Cear TOBIT TCPRESCALER 10 BIT gt Cear TOBIT TCPRESCALER PRESCALER TOSC1 i kiai CS20 CS21 CS22 TIMER COUNTER2 CLOCK SOURCE clk T2 The clock source for Timer Counter2 is named clkyag clky5s is by default connected to the main system I O clock clkyo By setting the AS2 bit in ASSR Timer Counter2 is asynchronously clocked from the TOSC1 pin This enables use of Timer Counter2 as a Real Time Counter RTC When AS2 is set pins TOSC1 and TOSC2 are disconnected from Port B A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer Counter2 The Oscillator is optimized for use with a 32 768 kHz crystal Applying an external clock source to TOSC1 is not recomme
361. ter choice due to its double buffer feature In fast PWM mode the compare units allow generation of PWM waveforms on the OC1x pins Setting the COM1x1 0 bits to 2 will produce a non inverted PWM and an inverted PWM output can be generated by setting the COM1x1 0 to 3 See Table 37 on page 98 The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output DDR OC1x The PWM waveform is generated by set ting or clearing the OC1x Register at the Compare Match between OCR1x and TCNT1 and clearing or setting the OC1x Register at the timer clock cycle the counter is cleared changes from TOP to BOTTOM The PWM frequency for the output can be calculated by the following equation _ ek yo focnxewm 7 N 1 TOP The N variable represents the prescaler divider 1 8 64 256 or 1024 The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode If the OCR1x is set equal to BOTTOM 0x0000 the output will be a narrow spike for each TOP 1 timer clock cycle Setting the OCR1x equal to TOP will result in a constant high or low output depending on the polar ity of the output set by the COM1x1 0 bits A frequency with 50 duty cycle waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each Compare Match COM1A1 0 1 This applies only if OCR1A is used to define the TOP value WGM13
362. ternal interrupts the Two wire Serial Interface address watch and the Watchdog continue operating if enabled Only an External Reset a Watchdog Reset a Brown out Reset a Two wire Serial Interface address match interrupt or an external level interrupt on INTO or INT1 can wake up the MCU This sleep mode basically halts all generated clocks allowing operation of asynchronous modules only Note that if a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time to wake up the MCU Refer to External Inter rupts on page 66 for details When waking up from Power down mode there is a delay from the wake up condition occurs until the wake up becomes effective This allows the clock to restart and become stable after having been stopped The wake up period is defined by the same CKSEL Fuses that define the Reset Time out period as described in Clock Sources on page 26 When the SM2 0 bits are written to 011 the SLEEP instruction makes the MCU enter Power save mode This mode is identical to Power down with one exception If Timer Counter2 is clocked asynchronously i e the AS2 bit in ASSR is set Timer Counter2 will run during sleep The device can wake up from either Timer Overflow or Output Compare event from Timer Counter2 if the corresponding Timer Counter2 interrupt enable bits are set in TIMSK and the global interrupt enable bit in SREG is set If the asynchronous timer is
363. tes an interrupt request 1 0 The falling edge of INT1 generates an interrupt request 1 1 The rising edge of INT1 generates an interrupt request 66 ATmega8 L memm 2486R AVR 07 07 AT 11 C025 General Interrupt Control Register GICR 2486R AVR 07 07 Bit 1 0 ISCO1 ISCOO Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INTO if the SREG I flag and the corresponding interrupt mask are set The level and edges on the external INTO pin that activate the interrupt are defined in Table 32 The value on the INTO pin is sampled before detecting edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guaranteed to generate an interrupt If low level interrupt is selected the low level must be held until the completion of the currently executing instruction to generate an interrupt Table 32 Interrupt O Sense Control ISCO1 ISCOO Description 0 0 The low level of INTO generates an interrupt request 0 1 Any logical change on INTO generates an interrupt request 1 0 The falling edge of INTO generates an interrupt request 1 1 The rising edge of INTO generates an interrupt request Bit 7 6 5 4 3 2 1 0 wn o LLELLLELLMETwe se Read Write R W R W R R R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 INT1 External Interrupt Request 1 Enable
364. the TWINT Flag is set The SCL line is pulled low until TWINT is cleared When the TWINT Flag is set the user must update all TWI Registers with the value relevant for the next TWI bus cycle As an example TWDR must be loaded with the value to be transmitted in the next bus cycle e After all TWI Register updates and other pending application software tasks have been completed TWCR is written When writing TWCR the TWINT bit should be set Writing a one to TWINT clears the flag The TWI will then commence executing whatever operation was specified by the TWCR setting In the following an assembly and C implementation of the example is given Note that the code below assumes that several definitions have been made for example by using include files ATlmega8 L memm m JT 11 C025 Assembly Code Example C Example Comments 1 ldi r16 1 lt lt TWINT 1 lt lt TWSTA TWCR 1 lt lt TWINT 1 lt lt TWSTA Send START condition 1 lt lt TWEN 1 lt lt TWEN out TWCR r16 2 waitl while TWCR amp 1 TWINT Wait for TWINT Flag set This in r16 TWCR indicates that the START condition sbrs r16 TWINT has been transmitted rjmp waitl 3 in r16 TWSR if TWSR amp OxF8 START Check value of TWI Status andi r16 OxF8 ERROR Register Mask prescaler bits If cpi r16 START status different from START go to ERROR brne ERROR ldi r16 SLAW TWDR
365. the combined SCL line goes high or low respectively Figure 74 SCL Synchronization Between Multiple Masters TA low I TA high MCN SCL from e Master A d SCL from YU N T WE Master B SCL Bus Line TB ow TB righ lt gt q p Su Masters Start Tues Masters Start Counting Low Period Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after out putting data If the value read from the SDA line does not match the value the Master had output it has lost the arbitration Note that a Master can only lose arbitration when it outputs a high SDA value while another Master outputs a low value The losing Master should immediately go to Slave mode checking if it is being addressed by the winning Master The SDA line should be left high but losing masters are allowed to generate a clock signal until the end of the current data or address packet Arbitration will continue until only one Master remains and this may take many bits If several masters are trying to address the same Slave arbitration will continue into the data packet AMEL 167 2486R AVR 07 07 168 AMEL Figure 75 Arbitration Between Two Masters START Master A Loses rbitration SDA SDA SDA from Master A SDA from 3 Master B WM EE GENS WEN SDALine OJ Zum O O O O Synchronized SCL Line AF Aa N Note that arbitration is not a
366. the data direction of this pin is controlled by DDB3 When the pin is forced by the SPI to be an input the pull up can still be con trolled by the PORTBS bit OC2 Output Compare Match Output The PB3 pin can serve as an external output for the Timer Counter2 Compare Match The PB3 pin has to be configured as an output DDB3 set one to serve this function The OC2 pin is also the output pin for the PWM mode timer function e SS OC1B Port B Bit 2 SS Slave Select input When the SPI is enabled as a Slave this pin is configured as an input regardless of the setting of DDB2 As a Slave the SPI is activated when this pin is driven low When the SPI is enabled as a Master the data direction of this pin is con trolled by DDB2 When the pin is forced by the SPI to be an input the pull up can still be controlled by the PORTB2 bit OC1B Output Compare Match output The PB2 pin can serve as an external output for the Timer Counter1 Compare Match B The PB2 pin has to be configured as an output DDB2 set one to serve this function The OC1B pin is also the output pin for the PWM mode timer function e OC1A Port B Bit 1 OC1A Output Compare Match output The PB1 pin can serve as an external output for the Timer Counter1 Compare Match A The PB1 pin has to be configured as an output DDB1 set one to serve this function The OC1A pin is also the output pin for the PWM mode timer function e CP1 Port B Bit 0 ICP1 Input
367. the internal data SRAM The first 96 locations address the Register File and I O Mem ory and the next 1024 locations address the internal data SRAM The five different addressing modes for the Data memory cover Direct Indirect with Displacement Indirect Indirect with Pre decrement and Indirect with Post increment In the Register File registers R26 to R31 feature the indirect addressing pointer registers The direct addressing reaches the entire data space The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y or Z register When using register indirect addressing modes with automatic pre decrement and post increment the address registers X Y and Z are decremented or incremented The 32 general purpose working registers 64 I O Registers and the 1024 bytes of inter nal data SRAM in the ATmega8 are all accessible through all these addressing modes The Register File is described in General Purpose Register File on page 12 Figure 8 Data Memory Map Register File Data Address Space 18 ATlmega8 L memm 2486R AVR 07 07 AT 11 C025 Data Memory Access Times EEPROM Data Memory EEPROM Read Write Access 2486R AVR 07 07 This section describes the general access timing concepts for internal memory access The internal data SRAM access is performed in two clkcpy cycles as described in Figure 9 Figure 9 On chip Data SRAM Access Cycles
368. the next frame read from UDR For compatibility with future devices always write this bit to zero when writing to UCSRA The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer The Parity Error PE Flag indicates that the next frame in the receive buffer had a parity error when received If parity check is not enabled the PE bit will always be read zero For compatibility with future devices always set this bit to zero when writing to UCSRA For more details see Parity Bit Calculation on page 138 and Parity Checker on page 147 146 ATmega8 L mmm 2486R AVR 07 07 f mega8 L Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery 2486R AVR 07 07 The Parity Checker is active when the high USART Parity mode UPM1 bit is set Type of parity check to be performed odd or even is selected by the UPMO bit When enabled the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame The result of the check is stored in the receive buffer together with the received data and stop bits The Parity Error PE Flag can then be read by software to check if the frame had a parity error The PE bit is set if the next character that can be read from the receive buffer had a par ity error when received and the
369. tics on page 248 Changes in Digital Input Enable and Sleep Modes on page 55 Addition of OCS2 in MOSI OC2 Port B Bit 3 on page 59 The following tables have been updated Table 51 CPOL and CPHA Functionality on page 132 Table 59 UCPOL Bit Set tings on page 158 Table 72 Analog Comparator Multiplexed Input on page 195 Table 73 ADC Conversion Time on page 200 Table 75 Input Chan nel Selections on page 206 and Table 84 Explanation of Different Variables used in Figure 103 and the Mapping to the Z pointer on page 221 Changes in Reading the Calibration Byte on page 234 Corrected Errors in Cross References Updated Some Preliminary Test Limits and Characterization Data The following tables have been updated Table 15 Reset Characteristics on page 38 Table 16 Internal Voltage Refer ence Characteristics on page 42 DC Characteristics on page 242 Table ADC Characteristics on page 248 Changes in External Clock Frequency Added the description at the end of External Clock on page 32 Added period changing data in Table 99 External Clock Drive on page 244 Updated TWI Chapter More details regarding use of the TWI bit rate prescaler and a Table 65 TWI Bit Rate Prescaler on page 173 Updated Typical Start up Times The following tables has been updated Table 5 Start up Times for the Crystal Oscillator Clock Select
370. tional ity of all the fuses and how they are mapped into the fuse bytes Note that the fuses are read as logical zero 0 if they are programmed Table 87 Fuse High Byte Fuse High Bit Byte No Description Default Value 1 unprogrammed PC6 is 4 RSIDISBL T Select if PC6 is I O pin or RESET pin RESET pin 1 unprogrammed WDT TIBUS 6 WDT always on enabled by WDTCR 1 Enable Serial Program and Data O programmed SPI prog SPIEN 5 Downloading enabled CKOPT 4 Oscillator options 1 unprogrammed EESAVE 3 EEPROM memory is preserved 1 unprogrammed through the Chip Erase EEPROM not preserved Select Boot Size see Table 82 for BOOTSZI details 0 programmed Select Boot Size see Table 82 for BOOTSZN details 0 programmed BOOTRST 0 Select Reset Vector 1 unprogrammed Notes 1 The SPIEN Fuse is not accessible in Serial Programming mode 2 The CKOPT Fuse functionality depends on the setting of the CKSEL bits see Clock Sources on page 26 for details 3 The default value of BOOTSZ1 0 results in maximum Boot Size See Table 82 on page 220 4 When programming the RSTDISBL Fuse Parallel Programming has to be used to change fuses or perform further programming 2486R AVR 07 07 AMEL 223 Latching of Fuses 224 AMEL Table 88 Fuse Low Byte Fuse Low Bit Byte No Description Default Value BODLEVEL 7 Brown out detector tr
371. too slow bit rates or the internally generated baud rate of the Receiver does not have a similar see Table 53 base frequency the Receiver will not be able to synchronize the frames to the start bit The following equations can be used to calculate the ratio of the incoming data rate and internal Receiver baud rate R LL D 05 Ros D 2 5_ slow S 14 D S S fast D 1 S Sy D Sum of character size and parity size D 5 to 10 bit S Samples per bit S 16 for Normal Speed mode and S 8 for Double Speed mode S First sample number used for majority voting Se 8 for Normal Speed and Se 4 for Double Speed mode Sm Middle sample number used for majority voting Sj 9 for Normal Speed and S 5 for Double Speed mode Rgow is the ratio of the slowest incoming data rate that can be accepted in relation to the Receiver baud rate Rias is the ratio of the fastest incoming data rate that can be accepted in relation to the Receiver baud rate Table 53 and Table 54 list the maximum Receiver baud rate error that can be tolerated Note that Normal Speed mode has higher toleration of baud rate variations AMEL 149 2486R AVR 07 07 150 AMEL Table 53 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode U2X 0 D Max Total Recommended Max Data Parity Bit Retowl Reast Error Receiver Error 5 93 20 106 67 6 67 6 8 3 0 6 94 12 105 79 5 79 5 88 2 0 7 94 81 1
372. tructions SBIC and SBIS since these also will change the state of the FIFO Bit 7 6 5 4 3 2 1 0 RXC me J UDRE pon PE Ux T wecw ucsra Read Write R R W R R R R R W R W Initial Value 0 0 1 0 0 0 0 0 Bit 7 RXC USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty i e does not contain any unread data If the Receiver is dis abled the receive buffer will be flushed and consequently the RXC bit will become zero The RXC Flag can be used to generate a Receive Complete interrupt see description of the RXCIE bit Bit6 TXC USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer UDR The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed or it can be cleared by writing a one to its bit location The TXC Flag can generate a Transmit Complete interrupt see description of the TXCIE bit Bit 5 UDRE USART Data Register Empty The UDRE Flag indicates if the transmit buffer UDR is ready to receive new data If UDRE is one the buffer is empty and therefore ready to be written The UDRE Flag can generate a Data Register Empty interrupt see description of the UDRIE bit UDRE is set after a reset to indicate that the Transmitter is ready Bit4 FE Frame Error This
373. ts ground and Ox3FF represents the selected reference voltage minus one LSB ADC Multiplexer Selection Register ADMUX Bit 7 6 5 4 3 2 1 0 REFS REFSO ADLAR wuxs muxe wuxi muxo bwux Read Write R W R W R W R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 REFS1 0 Reference Selection Bits These bits select the voltage reference for the ADC as shown in Table 74 If these bits are changed during a conversion the change will not go in effect until this conversion is complete ADIF in ADCSRA is set The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin AMEL 205 2486R AVR 07 07 206 AMEL Table 74 Voltage Reference Selections for ADC REFS1 REFSO Voltage Reference Selection 0 0 AREF Internal Ve turned off 0 1 AVcc with external capacitor at AREF pin 1 0 Reserved 1 1 Internal 2 56V Voltage Reference with external capacitor at AREF pin Bit5 ADLAR ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register Write one to ADLAR to left adjust the result Otherwise the result is right adjusted Changing the ADLAR bit will affect the ADC Data Register immediately regardless of any ongoing conversions For a complete description of this bit see The ADC Data Register ADCL and ADCH on page 208 Bits 3 0 MUX3 0 Analog Channel Selection
374. ual to MAX the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values At the very start of period 2 in Figure 51 OCn has a transition from high to low even though there is no Compare Match The point of this transition is to guarantee symmetry around BOTTOM There are two cases that give a transition without Compare Match e OCR2A changes its value from MAX like in Figure 51 When the OCR2A value is MAX the OCn pin value is the same as the result of a down counting Compare Match To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up counting Compare Match 14 ATmega8 L mmm 2486R AVR 07 07 X X f megae8 L e The timer starts counting from a value higher than the one in OCR2A and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up Timer Counter Timing The following figures show the Timer Counter in Synchronous mode and the timer clock Diagrams clKz5 is therefore shown as a clock enable signal In Asynchronous mode clk o should be replaced by the Timer Counter Oscillator clock The figures include information on when Interrupt Flags are set Figure 52 contains timing data for basic Timer Counter operation The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode Figure 52 Timer Counter Timing Diagram no
375. uffering is disabled the CPU will access the OCR2 directly AMEL 107 2486R AVR 07 07 Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit AMEL In non PWM Waveform Generation modes the match output of the comparator can be forced by writing a one to the Force Output Compare FOC2 bit Forcing Compare Match will not set the OCF2 Flag or reload clear the timer but the OC2 pin will be updated as if a real Compare Match had occurred the COM21 0 bits settings define whether the OC2 pin is set cleared or toggled All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock cycle even when the timer is stopped This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer Counter clock is enabled Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle there are risks involved when changing TCNT2 when using the Output Compare channel independently of whether the Timer Counter is running or not If the value written to TCNT2 equals the OCR2 value the Compare Match will be missed resulting in incorrect waveform generation Similarly do not write the TCNT2 value equal to BOTTOM when the counter is downcounting The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output The easiest way of
376. ull Duplex Operation Independent Serial Receive and Transmit Registers Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Supports Serial Frames with 5 6 7 8 or 9 Databits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete TX Data Register Empty and RX Complete Multi processor Communication Mode Double Speed Asynchronous Communication Mode Overview A simplified block diagram of the USART Transmitter is shown in Figure 61 CPU acces sible I O Registers and I O pins are shown in bold Figure 61 USART Block Diagram Clock Generator UBRR H L BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL KOK Transmitter UDR Transmit lt a ek PARITY GENERATOR PIN CONTROL MA TRANSMIT SHIFT REGISTER DATABUS Receiver CLOCK RX RECOVERY CONTROL DATA PIN rigide SHIFT REGISTER RECOVERY CONTROL mo E PARITY UDR Receiv CHECKER UCSRA UCSRB UCSRC Note 1 Referto Pin Configurations on page 2 Table 30 on page 64 and Table 29 on page 64 for USART pin placement AMEL 133 2486R AVR 07 07 AVR USART vs AVR UART Compatibility Clock Generation AMEL The dashed
377. unctions in PC6 PC4 Signal Name PC6 RESET PC5 SCL ADC5 PC4 SDA ADC4 PUOE RSTDISBL TWEN TWEN PUOV 1 PORTCS5 PUD PORTC4 PUD DDOE RSTDISBL TWEN TWEN DDOV 0 SCL OUT SDA OUT PVOE 0 TWEN TWEN PVOV 0 0 0 DIEOE RSTDISBL 0 0 DIEOV 0 0 0 DI AIO RESET INPUT ADC5 INPUT SCL INPUT ADC4 INPUT SDA INPUT Table 27 Overriding Signals for Alternate Functions in PC3 PCO Signal Name PC3 ADC3 PC2 ADC2 PC1 ADC1 PCO ADCO PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI x AlO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADCO INPUT Note 1 When enabled the Two wire Serial Interface enables slew rate controls on the output pins PC4 and PC5 This is not shown in the figure In addition spike filters are con nected between the AIO outputs shown in the port figure and the digital logic of the TWI module 62 ATmega8 L memm 2486R AVR 07 07 X A mega8 L Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 28 Table 28 Port D Pins Alternate Functions Port Pin Alternate Function PD7 AIN1 Analog Comparator Negative Input PD6 AINO Analog Comparator Positive Input PD5 T1 Timer Counter 1 External Counter Input PD4 XCK USART External Clock Input Output TO Timer Counter 0 External Counter Input
378. ure 41 shows a timing diagram for the setting of OCF1x Figure 41 Timer Counter Timing Diagram Setting of OCF1x no Prescaling clkig clk clk 5 1 TCNTn OCRnx 1 OCRnx OCRnx 1 OCRnx 2 OCRnx OCRnx Value OCFnx Figure 42 shows the same timing data but with the prescaler enabled AMEL AMEL Figure 42 Timer Counter Timing Diagram Setting of OCF1x with Prescaler fok 0 8 Clk o clk clk 8 TCNTn OCRnx 1 l OCRnx OCRnx 1 OCRnx 2 i i 1 1 1 OCRnx OCRnx Value OCFnx Figure 43 shows the count sequence close to TOP in various modes When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM The timing diagrams will be the same but TOP should be replaced by BOTTOM TOP 1 by BOTTOM 1 and so on The same renaming applies for modes that set the TOV1 Flag at BOTTOM Figure 43 Timer Counter Timing Diagram no Prescaling clk 1 0 clk clk 1 TCNTn CTC and FPWM TOP 1 J TOP BOTTOM BOTTOM 1 TONTn PC and PFC PWM TOP 1 l TOP j TOP 1 J TOP 2 TOVn
379. ures a 10 bit successive approximation ADC The ADC is connected to an 8 channel Analog Multiplexer which allows eight single ended voltage inputs con structed from the pins of Port C The single ended voltage inputs refer to OV GND The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion A block diagram of the ADC is shown in Figure 90 The ADC has a separate analog supply voltage pin AVcc AVcc must not differ more than 0 3V from Voc See the paragraph ADC Noise Canceler on page 201 on how to connect this pin Internal reference voltages of nominally 2 56V or AVcc are provided On chip The volt age reference may be externally decoupled at the AREF pin by a capacitor for better noise performance ns ATmega8 L memm 2486R AVR 07 07 ATmega8 L Figure 90 Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ 8 BIT DATA BUS ADC DATA REGISTER ADCL o ADC MULTIPLEXER SELECT ADMUX c el y 3 Y MUX DECODER REFS1 REFSO ADI MUX MUX MUX1 MUXO ADEN ADC 9 0 CHANNEL SELECTION SAMPLE amp HOLD COMPARATOR 10 BIT DAC ADC MULTIPLEXER e gt OUTPUT The ADC converts an analog input voltage to a 10 bit digital value through successive approximation The minimum value represents GND and the maximum value represents the voltage on the AREF
380. ures are Timer Counter1 aue e bit Did i e allows 16 bit PWM i Two Independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match Auto Reload Glitch free Phase Correct Pulse Width Modulator PWM Variable PWM Period Frequency Generator External Event Counter Four Independent Interrupt Sources TOV1 OCF1A OCF1B and ICF1 Overview Most register and bit references in this section are written b general form A lower case n replaces the Timer Counter number and a lower case x replaces the Output Com pare unit channel However when using the register or bit defines in a program the precise form must be used i e TCNT1 for accessing Timer Counter1 counter value and SO on A simplified block diagram of the 16 bit Timer Counter is shown in Figure 32 For the actual placement of I O pins refer to Pin Configurations on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the 16 bit Timer Counter Register Description on page 97 76 ATmegae8 L O l al 2486R AVR 07 07 ATmega8 L Figure 32 16 bit Timer Counter Block Diagram Count TOVn Clear Int Req Control Logic clk Tn TOP BOTTOM ZON Timer Counter OCFnA Int Req l Wavefor
381. ut from the EEPROM at the address given by EEAR Bit 7 6 5 4 3 2 1 0 a reos ee Ee Bene TIL BER Read Write R R R R R W R W RW RW Initial Value 0 0 0 0 0 0 x 0 e Bits 7 4 Res Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero e Bit 3 EERIE EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set Writing EERIE to zero disables the interrupt The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared Bit 2 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written When EEMWE is set setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero setting EEWE will have no effect When EEMWE has been written to one by software hardware clears the bit to zero after four clock cycles See the description of the EEWE bit for an EEPROM write procedure Bit 1 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM When address and data are correctly set up the EEWE bit must be written to one to write the 20 ATmega8 L memm 2486R AVR 07 07 f 11 C025 value into the EEPROM The EEMWE bit must be written to one before a logical one is written to EEWE otherwise no EEPROM write takes place The following procedure should be followed when
382. utput High Source Independent of the setting of Data Direction bit DDxn the port pin can be read through the PINxn Register Bit As shown in Figure 22 the PINxn Register bit and the preceding latch constitute a synchronizer This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock but it also introduces a delay Figure 23 shows a timing diagram of the synchronization when reading an externally applied pin value The maximum and minimum propagation delays are denoted t 4 max and tpd min respectively Figure 23 Synchronization when Reading an Externally Applied Pin Value systmcek_ 1 I INSTRUCTIONS xXx XX X WHLPME SYNC LATCH WLR 4 PINxn r17 0x00 OxFF t pd max toa min AMEL s AMEL Consider the clock period starting shortly after the first falling edge of the system clock The latch is closed when the clock is low and goes transparent when the clock is high as indicated by the shaded region of the SYNC LATCH signal The signal value is latched when the system clock goes low It is clocked into the PINxn Register at the suc ceeding positive clock edge As indicated by the two arrows tog max and tog mins a single signal transition on the pin will be delayed between 12 and 1 12 system clock period depending upon the time of assertion When reading back a software assigned pin value a nop instru
383. uture devices always write this bit to zero when writing the UCSRA Register When the Data Register empty Interrupt Enable UDRIE bit in UCSRB is written to one the USART Data Register Empty Interrupt will be executed as long as UDRE is set pro vided that global interrupts are enabled UDRE is cleared by writing UDR When AMEL 141 Parity Generator Disabling the Transmitter AMEL interrupt driven data transmission is used the Data Register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register empty Interrupt otherwise a new interrupt will occur once the interrupt routine terminates The Transmit Complete TXC Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed or it can be cleared by writing a one to its bit location The TXC Flag is useful in half duplex communication interfaces like the RS485 standard where a transmitting application must enter Receive mode and free the communication bus immediately after completing the transmission When the Transmit Compete Interrupt Enable TXCIE bit in UCSRB is set the USART Transmit Complete Interrupt will be executed when the TXC Flag becomes set pro vided that global interrupts are enabled When the transmit complete interrupt
384. veInit Set MISO output all others input ldi r17 1 DD MISO out DDR SPI r17 Enable SPI ldi r17 1 lt lt SPI out SPCR r17 Lj ret SPI SlaveReceive Wait for reception complete sbis SPSR SPIF rjmp SPI SlaveReceive Read received data and return in r16 SPDR ret C Code Example void SPI SlaveInit void Set MISO output all others input DDR SPI 1 lt lt DD MISO Enable SPI SPCR 1 lt lt SPE char SPI_SlaveReceive void Wait for reception complete while SPSR amp 1 SPIF Return data register return SPDR Note 1 See About Code Examples on page 8 ATlmega8 L m ERN 2486R AVR 07 07 A mega8 L SS Pin Functionality Slave Mode Master Mode SPI Control Register SPCR 2486R AVR 07 07 When the SPI is configured as a Slave the Slave Select SS pin is always input When SS is held low the SPI is activated and MISO becomes an output if configured so by the user All other pins are inputs When SS is driven high all pins are inputs and the SPI is passive which means that it will not receive incoming data Note that the SPI logic will be reset once the SS pin is driven high The SS pin is useful for packet byte synchronization to keep the Slave bit counter syn chronous with the master clock generator When the SS pin is driven high the SPI Slave will immediately reset t
385. w be read at DATA 6 Set OE to 1 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows refer to Programming the Flash on page 229 for details on Command and Address loading 1 A Load Command 0000 0011 2 G Load Address High byte 0x00 OxFF 3 B Load Address Low byte 0x00 OxFF 4 Set OE to 0 and BS1 to 0 The EEPROM Data byte can now be read at DATA 5 Set OE to 1 Programming the Fuse Low The algorithm for programming the Fuse Low bits is as follows refer to Programming Bits the Flash on page 229 for details on Command and Data loading 1 A Load Command 0100 0000 2 C Load Data Low byte Bit n 0 programs and bit n 1 erases the Fuse bit 3 Set BS1 and BS2 to 0 4 Give WR a negative pulse and wait for RDY BSY to go high 232 ATmega8 L suum AT 11 C025 Programming the Fuse High The algorithm for programming the Fuse high bits is as follows refer to Programming Bits the Flash on page 229 for details on Command and Data loading 1 A Load Command 0100 0000 2 C Load Data Low byte Bit n 0 programs and bit n 1 erases the Fuse bit 3 Set BS1 to 1 and BS2 to 0 This selects high data byte 4 Give WR a negative pulse and wait for RDY BSY to go high 5 Set BS1 to 0 This selects low data byte Programming the Lock Bits The algorithm for programming the Lock
386. waveforms in Normal mode is not recommended since this will occupy too much of the CPU time In Clear Timer on Compare or CTC mode WGM13 0 4 or 12 the OCR1A or ICR1 Register are used to manipulate the counter resolution In CTC mode the counter is cleared to zero when the counter value TCNT1 matches either the OCR1A WGM13 0 4 or the ICR1 WGM13 0 12 The OCR1A or ICR1 define the top value for the counter hence also its resolution This mode allows greater control of the Compare Match output frequency It also simplifies the operation of counting external events The timing diagram for the CTC mode is shown in Figure 37 The counter value TCNT1 increases until a Compare Match occurs with either OCR1A or ICR1 and then counter TCNT1 is cleared 88 ATmega8 L memm 2486R AVR 07 07 ATmega8 L Figure 37 CTC Mode Timing Diagram OCnA Interrupt Flag Set p quee cu pA pp 7 or ICFn Interrupt Flag Set i H ME UN Interrupt on TOP TCNTn vi VA Y Y y aaa COMnA1 0 1 Period 1 2 4 3 4 gt An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value If the interrupt is enabled the interrupt handler routine can be used for updating the TOP value However changing the TOP to a value close to BOTTOM when the counter is running with none or a
387. will proceed as normal even if two or Synchronization more masters initiate a transmission at the same time Two problems arise in multi mas ter systems e Analgorithm must be implemented allowing only one of the masters to complete the transmission All other masters should cease transmission when they discover that they have lost the selection process This selection process is called arbitration When a contending master discovers that it has lost the arbitration process it should immediately switch to Slave mode to check whether it is being addressed by the winning master The fact that multiple masters have started transmission at the same time should not be detectable to the slaves i e the data being transferred on the bus must not be corrupted e Different masters may use different SCL frequencies A scheme must be devised to synchronize the serial clocks from all masters in order to let the transmission proceed in a lockstep fashion This will facilitate the arbitration process The wired ANDing of the bus lines is used to solve both these problems The serial clocks from all masters will be wired ANDed yielding a combined clock with a high period equal to the one from the Master with the shortest high period The low period of the combined clock is equal to the low period of the Master with the longest low period Note that all masters listen to the SCL line effectively starting to count their SCL high and low time out periods when
388. wn in Table 17 on page 44 The WDR Watchdog Reset instruction resets the Watchdog Timer The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs Eight different clock cycle periods can be selected to determine the reset period If the reset period expires without another Watchdog Reset the ATmega8 resets and executes from the Reset Vector For timing details on the Watchdog Reset refer to page 41 To prevent unintentional disabling of the Watchdog a special turn off sequence must be followed when the Watchdog is disabled Refer to the description of the Watchdog Timer Control Register for details Figure 20 Watchdog Timer WATCHDOG WATCHDOG OSCILLATOR PRESCALER OSC 32K WATCHDOG RESET OSC 1024K OSC 2048K MCU RESET Bit 7 6 5 4 3 2 1 0 O wece woe T woez woe woo worcr Read Write R R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bits 7 5 Res Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero Bit4 WDCE Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero Otherwise the Watchdog will not be disabled Once written to one hardware will clear this bit after four clock cycles Refer to the description of the WDE bit for a Watchdog disable procedure In Safety Level 1 and 2 this bit must also be set when changing the prescaler bits See the Code Examples on page 45 AMEL t 44 AM
389. writing the EEPROM the order of steps 3 and 4 is not essential Wait until EEWE becomes zero Wait until SPMEN in SPMCR becomes zero Write new EEPROM address to EEAR optional Write new EEPROM data to EEDR optional Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR Within four clock cycles after setting EEMWE write a logical one to EEWE an rwhnr nr The EEPROM can not be programmed during a CPU write to the Flash memory The software must check that the Flash programming is completed before initiating a new EEPROM write Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash If the Flash is never being updated by the CPU step 2 can be omitted See Boot Loader Support Read While Write Self Programming on page 209 for details about boot programming Caution An interrupt between step 5 and step 6 will make the write cycle fail since the EEPROM Master Write Enable will time out If an interrupt routine accessing the EEPROM is interrupting another EEPROM access the EEAR or EEDR Register will be modified causing the interrupted EEPROM access to fail It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems When the write access time has elapsed the EEWE bit is cleared by hardware The user software can poll this bit and wait for a zero before writing the next byte When EEWE has been set the CPU is halted
390. y to be updated with a new value If a write is performed to any of the three Timer Counter2 Registers while its update busy flag is set the updated value might get corrupted and cause an unintentional inter rupt to occur The mechanisms for reading TCNT2 OCR2 and TCCR2 are different When reading TCNT2 the actual timer value is read When reading OCR2 or TCCR2 the value in the temporary storage register is read When Timer Counter2 operates asynchronously some considerations must be taken e Warning When switching between asynchronous and synchronous clocking of Timer Counter2 the Timer Registers TCNT2 OCR2 and TCCR2 might be corrupted A safe procedure for switching clock source is 1 Disable the Timer Counter2 interrupts by clearing OCIE2 and TOIE2 2 Select clock source by setting AS2 as appropriate 3 Write new values to TCNT2 OCR2 and TCCR2 4 To switch to asynchronous operation Wait for TCN2UB OCR2UB and TCR2UB 5 Clear the Timer Counter2 Interrupt Flags 6 Enable interrupts if needed e The Oscillator is optimized for use with a 32 768 kHz watch crystal Applying an external clock to the TOSC1 pin may result in incorrect Timer Counter2 operation The CPU main clock frequency must be more than four times the Oscillator frequency e When writing to one of the registers TCNT2 OCR2 or TCCR2 the value is transferred to a temporary register and latched after two positive edges on TOSC1 The user should n
391. y will switch to SR or ST mode depending on the value of the READ WRITE bit If they are not being addressed they will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition depending on application software action This is summarized in Figure 88 Possible status values are given in circles Figure 88 Possible Status Codes Caused by Arbitration START SLA Data STOP Arbitration lost in SLA Arbitration lost in Data Address i Call No 38 a Twi bus will be released and not addressed slave mode will be entered A A START condition will be transmitted when the bus becomes free received CUM Write 68 78 Data byte will be received and NOT ACK will be returned irection Data byte will be received and ACK will be returned Read Last data byte will be transmitted and NOT ACK should be received B0 Data byte will be transmitted and ACK should be received ATmega8 L m U U 2486R AVR 07 07 f megae8 L Analog Comparator The Analog Comparator compares the input values on the positive pin AINO and nega tive pin AIN1 When the voltage on the positive pin AINO is higher than the voltage on the negative pin AIN1 the Analog Comparator Output ACO is set The comparator s output can be set to trigger the Timer Counter1 Input Capture function In addition the comparator can trigger a separate interrupt exclusive to the An
392. ystem Control and Reset rese eee e essen enn nana nana an 37 Internal Voltage Reference eessssessesesseeeeeeennne nnne nnns 42 Watchdog BITTER 43 Timed Sequences for Changing the Configuration of the Watchdog Timer 45 TINCT ONS 46 Interrupt Vectors in ATMOQaB ccceeecceeeeeeeeeceeeeseeeeeeeesseaeeeeteseeeeeeeeeneneenteetaes 46 DO POS A EEEE E E rM crc UR 51 Aae Saa a PED 51 Ports as General Digital 1 O sessssseeeeeeeneeeeeeenneenn enne 52 Alternate Port Functions esesssseseeseeeeeeeenen mener 56 Register Description for I O Ports 65 External InterrUptS E 66 gs EY I117 15 0091 10 7 y Bt 69 eus 69 Timer Counter Clock Sources sse nennen 70 Counter UMit e 70 isum M 70 Timer Counter Timing Diagrams ssssssseeeeneeeeeenneeeenneen nennen 71 8 bit Timer Counter Register Description ssseeeneee 72 Timer Counter0 and Timer Counter1 Prescalers 74 16 bit Tim r Cou ter Toussaint Gonna 76 eu M 76 Accessing 16 bit Registers ssssssseessseenenm eene menn 79 Timer Counter Clock Sources sesssss

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