Cypress NoBL CY7C1371D User's Manual
Contents
1. Address 2 pm Operation Used CE2 ZZ ADV LD WE OE CLK DQ Deselect Cycle None H X X L L X X X L gt H Tri State Deselect Cycle None X X H L L X X X L H Tri State Deselect Cycle None X L X L L X X X L gt H Tri State Continue Deselect Cycle None X X X L H X X X L H Tri State Read Cycle Begin Burst External L H L L L H X L gt Out Q Read Cycle Continue Burst Next X X X L H X X L L gt H Data Out Q NOP Dummy Read Begin Burst External L H L L L H X H L H Tri State Dummy Read Continue Burst Next X X X L H X X H L gt H Tri State Write Cycle Begin Burst External L H L L L L L X L gt H Data In D Write Cycle Continue Burst Next X X X L H X L X L gt H In D NOP Write Abort Begin Burst None L H L L L L H X L gt H Tri State Write Abort Continue Burst Next X X X L H X H X L H Tri State Ignore Clock Edge Stall Current X X X L X X X X gt Sleep Mode None X X X H X X X X X X Tri State Partial Truth Table for Read Write 3 9 Function CY7C1371D WE BW BWg BWc BWp Read H X X X X Write No bytes written L H H H H Write Byte A DQ L L H H H Write Byte B DQg and L H L H H Write Byte C DQc and DQPc L H H L H Write Byte D DQp and DQPp L H H H L Write All Bytes L L L L L2. DQ OE COMMAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A241 0 4 1 DON T CARE UNDEFINED Notes 25 this waveform ZZ is tied LOW 26 When CE is LOW CE is LOW is HIGH and is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH 27 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05556 Rev F Page 22 of 29 Feedback CY7C1371D CY7C1373D PERFORM Switching Waveforms continued NOP STALL AND DESELECT 26 28 aA IA Mt A I a A IA ELL ADDRESS I NA RESI QU M34 D DQ CONTINUE DESELECT COMMAND WRITE NOP D A4 READ Q A3 DONT CARE UNDEFINED READ STALL Q A2 WRITE READ D A1 5 Note 28 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause A write is not performed during this cycle Document 38 05556 Rev F Page 23 of 29 Feedback Switching Waveforms continued ZZ Mode Timing 30 CY7C1371D CY7C1373D 77 g
3. Document 38 05556 Rev F Page 25 of 29 Feedback PERFORM Package Diagrams Figure 1 16 00 0 20 LA 140040790 100 81 RRRRRRRRERRRRRRHERRRRR 1 of m 80 zo ES ES E 0 30 0 08 ES ES ES E o o EZ 8 o EH ES R m d ES 0 65 ES Ez En TYP ES ES ES EB 51 1 FABER HH EB 31 50 R 0 08 MIN 0 20 MAX s 0 MIN STAND OFF TE 0 05 MIN a H 0 15 MAX GAUGE PLANE L Y ERR Y xS i R 0 08 MIN 0 7 0 20 0 60 0 15 d 020 MIN 1 00 REF DETAIL Document 38 05556 Rev 1 STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 CY7C1371D CY7C1373D 1 40 0 05 SEE DETAIL A m 0 20 MAX 1 60 MAX 0 10 x 51 85050 26 29 Feedback PERFORM Package Diagrams continued Figure 2 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 A1 CORNER 1 00 3 REF 123456 7 gt cHormvz2ernr
4. 0 90 0 05 025 M _ 0 70 12 00 30 gt 2 40MAX Re PEG ma 015 20 32 1 27 CY7C1371D CY7C1373D 0 05 ME 2025MC B 0 75 0 15 119X 7654321 I 000 hooo OOC 2000 pOOO 10 16 ood ood j O O A p M Ore OOO C OOQOOO ooec Q Caco gt 22 00 0 20 SEATING PLANE 0 56 4i Document 38 05556 Rev F 0 60 0 10 _ 7 62 lt lt 14 00 0 20 D 0 15 4X 127 51 85115 Page 27 of 29 Feedback CY7C1371D YPRESS CY7C1373D PERFORM SM Saar P 2 i SSS gt Se i lt Package Diagrams continued Figure 3 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW p 0 05
5. Vss ZZ DQ Vss DQ DQ DQ VDDQ DOA DOA CY7C1371D CY7C1373D BYTEB BYTEA Page 3 of 29 Feedback CY7C1371D CYPRESS CY7C1373D LIUM PERFORM Pin Configurations continued 100 Pin TQFP Pinout lt lt lt S 9955955933959 588865835885 NC 1 80 A NC 2 79 NC NC 3 78 NC VDDQ 4 77 Vss 5 76 Vss NC 6 75 NC NC 7 74 8 73 DQ DQg 9 72 DQ Vss 10 71 Vss 11 70 O DQg 12 69 poma CY7C1373D L 14 67 Vss 15 66 NC BYTE BYTE B NCC 16 65 Vpp Vss 17 64 22 DQg 18 63 DQA DQg 19 62 7 20 61 Vss 121 60 1 Vss DQg 22 59 DQ DQg 23 58 DQPg 24 57 NC NC 25 56 NC Vss L 26 55 Vss Vppo 27 54 28 53 29 52 30 51 58588288582 9 5 52295 55 5 0 AGuUddgguuuuuuuuugJuuuuuu CL
6. VDD 3 3V 0 165V unless otherwise noted l Parameter Description Description Conditions Min Max Unit Output HIGH Voltage lon 4 0 mA Vppo 3 3V 24 V 1 0 mA Vppo 2 5V 2 0 V Output HIGH Voltage lop 7100 pA Vppo 3 3V 2 9 V Vppo 2 5V 2 1 V Vout Output LOW Voltage lo 8 0 mA Vppo 3 3V 0 4 V lo 1 0 mA Vppo 2 5V 0 4 V Voi Output LOW Voltage lo 100 pA Vppo 3 3V 0 2 V Vppo 2 5V 0 2 V Input HIGH Voltage Vppo 3 3V 2 0 Vpp 0 3 V 2 5V 1 7 Vpp 0 3 V Input LOW Voltage Vppo 3 3V 0 5 0 7 V Vppo 2 5V 0 3 0 7 V Ix Input Load Current GND lt Vin lt Vppa 5 5 Note 12 All voltages referenced to Vss GND Document 38 05556 Rev F Page 15 of 29 ee s CY7C1371D CYPRESS die PERFORM Identification Register Definitions CY7C1371D CY7C1373D Instruction Field 512K X 36 1M X 18 Description Revision Number 31 29 000 000 Describes the version number Device Depth 28 24 01011 01011 Reserved for internal use Device Width 23 18 001001 001001 Defines memory type and architecture Cypress Device ID 17 12 100101 010101 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 Indicates the presence of an ID register Scan Register Sizes
7. 8 gt lt lt lt lt lt lt lt E Ei EE 99 22 zz Document 38 05556 Rev F Page 4 of 29 Feedback CY7C1371D gt CY7C1373D 1 2 CYPRESS PERFORM Pin Configurations continued 119 Ball BGA Pinout CY7C1371D 512K x 36 1 2 3 4 5 6 7 Wace 576 CE A ADV LD A CE NC Vip A A NC D DQc DQPc Vss NC Vss DQPg DQc DQc Vss CE Vss DQg DQg F DQc Vss OE Vss DQg G BW BW DQ Vss WE Vss J VDDQ Vpp NC Vpp NC Vpp VDDQ Dap Vss CLK Vss DQ L DQp DQp BWp NC BWA DQA DQA M DQp Vss CEN Vss DQA Vss 1 Vss DQ P DQp DQPp Vss Vss DQPA 144 MODE Vpp NC A NC 288M T NC NC 72M A A A NC 36M LL TMS TDI TCK TDO NC Vong CY7C1373D 1Mx 18 1 2 3 4 5 6 7 Vo 576 ADV LD A NCAG A A DQg NC Vss NC Vss NC E NC Wes Vss NC DQ F NC Vss Vss DQ Vppo G NC DQg BWs DQ H Vss WE Vss NC J VDDQ VDD NC VDD NC VDD VDDQ K NC Vss CLK Vss NC DQA L DQ NC NC NC
8. 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND First Second Third Fourth conduct up to four Write operations without reasserting the address inputs ADV LD must be driven LOW to load the initial Address Address Address Address 1 0 1 0 1 0 1 0 address as described in the Single Write Access section above When ADV LD is driven HIGH on the subsequent clock 00 01 10 11 rise the Chip Enables CE4 and CE3 and WE inputs are ignored and the burst counter is incremented The correct 01 10 11 00 BW inputs must be driven in each cycle of the burst write to 40 11 00 01 write the correct bytes of data Sleep Mode 11 00 01 10 The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 80 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 21 ns tz7zREC ZZ recovery time ZZ 0 2V 2tcyc ns tzzi ZZ active to sleep current This parameter is sampled 2 ns tRzzi ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 38 05556 Rev F Page 9 of 29 CY7C1371D ZCYPRESS 0 CYrctarsD PERFORM Truth Tablet 3 4 5 6 7 8
9. BWA DQ NC M Vss CEN Vss NC DQg NC Vss A1 Vss NC P NC Vss Vss NC DQ R 144 A MODE Vpp NC A NC 288M T NC 72M A A NC 36M A A ZZ Vooo TMS TDI TCK TDO NC Mane Document 38 05556 Rev F Page 5 of 29 Feedback CY7C1371D SES Cons SWORE PERFORM Pin Configurations continued 165 Ball FBGA Pinout CY7C1371D 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A 576 BWe BW ADV LD NC 1G 2 BWp BWa CLK WE OE A A NC Vss Vss Vss Vss Vss VDDQ NC DQPg D Vpp Vss Vss Vss Vpp VDDQ VDDQ Vpp Vss Vss Vss Vpp VDDQ DQg F DQc Vpp Vss Vss Vss Vpp G DQc DQc Vpp Vss Vss Vss VDD VDDQ DQg DQg H NC NC NC Vpp Vss Vss Vss NC NC ZZ J DQp DQp VDDQ VDD Vss Vss Vss Vpp DQA DQa K DQp DQp Vpp Vss Vss Vss Vpp VDDQ L DQp DQp Vpp Vss Vss Vss Vpp VDDQ DQa M DQp DQp Vpp Vss Vss Vss VDD VDDQ DQa N DOP NC Voa Vss NC NC NC Vss Vong NC DOR NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS A0 TCK A A A A CY7C1373D 1M x 18 1 2 3 4 5 6 7 8 9 10 11 A 57
10. H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 E6 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83 N4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 A5 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K Notes 13 Balls which are NC No Connect are pre set LOW 14 Bit 85 is pre set HIGH Document 38 05556 Rev F Page 17 of 29 Feedback ee s 1 2 CYPRESS PERFORM 165 Ball BGA Boundary Scan Order 13 151 CY7C1371D Bit Ball ID Bit Ball ID N6 31 D10 2 N7 32 C11 3 N10 33 A11 4 P11 34 B11 5 P8 35 A10 6 R8 36 B10 7 R9 37 A9 8 P9 38 B9 9 P10 39 C10 10 R10 40 A8 11 R11 41 B8 12 H11 42 AT 13 N11 43 B7 14 M11 44 B6 15 L11 45 A6 16 K11 46 B5 17 J11 47 A5 18 M10 48 A4 19 L10 49 B4 20 K10 50 B3 21 J10 51 A3 22 H9 52 A2 23 H10 53 B2 24 G11 54 C2 25 F11 55 B1 26 E11 56 A1 27 D11 57 C1 28 G10 58 D1 29 F10 59 E1 30 E10 60 F1 CY7C1373D Bit Ball ID 61 G1
11. MC A PIN 1 CORNER 0 25 B 60 50 99 1 2 3 4 5 6 7 8 9 10 11 11 10 5 8 7 6 5 4 3 2 1 eoooo oooodc Y 990900000000 8 D t F 2 e le 5 18 G C e G gt Q H H 8 8 1 y 00000000000 8 B 00000000000 In 99 J 1 00 1 5 00 10 00 B 13 00 0 10 gt 49 13 00 0 10 A 0 15 4X gJ 8 NOTES 3 3 5 SOLDER PAD NON SOLDER MASK DEFINED NSMD amp o T 5 PACKAGE WEIGHT 0 475g q JEDEC REFERENCE MO 216 DESIGN 4 6C i PACKAGE CODE BBOAC _ SEATING PLANE 3 51 85180 0 35 0 06 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05556 Rev F Page 28 of 29 Cypress Semiconductor Corporation 2004 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypr
12. TAP CONTROLLER TCK TMS Performing a TAP Reset A RESET is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE Page 11 of 29 Feedback instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip cer
13. a High Z condition TAP Timing Test Clock TCK CY7C1371D CY7C1373D This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Test Mode Select TMS Test Data In TDI Test Data Out TDO Document 38 05556 Rev F DON T CARE UNDEFINED Page 13 of 29 Feedback ee s CY7C1371D F CYPRESS PERFORM AC Switching Characteristics Over the Operating Rangel 111 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns Clock Frequency 20 MHz Clock HIGH time 20 ns tn TCK Clock LOW time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns ttpox TCK Clock LOW to TDO Invalid 0 ns Setup Times ttuss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 n
14. controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Document 38 05556 Rev F CY7C1371D CY7C1373D Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram Bypass Register i mH Selection Circuitry Selection Circuitry Instruction Register TDI TDO gt 3130129 121110 Identification Register 2 Boundary Scan Register buo oT Ge
15. scope 5 Note 18 Tested initially and after any design or process change that may affect these parameters Document 38 05556 Rev F Page 20 of 29 Feedback Switching Characteristics Over the Operating Rangel 241 CY7C1371D CY7C1373D 133 MHz 100 MHz Parameter Description Min Max Min Max Unit tower 91 1 1 ms Clock Clock Cycle Time 7 5 10 ns tcu Clock HIGH 2 1 2 5 ns teL Clock LOW 2 1 2 5 ns Output Times tepv Data Output Valid After CLK Rise 6 5 8 5 ns Data Output Hold After CLK Rise 2 0 2 0 ns iis Clock to 2120 21 22 2 0 2 0 ns Clock to High z 20 21 22 4 0 5 0 ns tory OE LOW to Output Valid 3 2 3 8 ns toeLz OE LOW to Output 2120 21 22 0 0 ns toEuz OE HIGH to Output 2120 21 22 4 0 5 0 ns Setup Times tas Address Setup Before CLK Rise 1 5 1 5 ns tats ADV LD Setup Before CLK Rise 1 5 1 5 ns twes WE BW Setup Before CLK Rise 1 5 1 5 ns icENS CEN Setup Before CLK Rise 1 5 1 5 ns tps Data Input Setup Before CLK Rise 1 5 1 5 ns tcEs Chip Enable Setup Before CLK Rise 1 5 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 5 0 5 ns tALH ADV LD Hold After CLK Rise 0 5 0 5 ns tWeH WE BW Hold After CLK Rise 0 5 0 5 ns tcENH CEN Hold After CLK Rise 0 5 0 5 ns Data Input Hold After Rise 0 5 0 5 ns Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 19 This part ha
16. 4 1709 408 943 2600 Revised July 09 2007 Cypress Semiconductor Corporation Document 38 05556 Rev F Feedback Logic Block Diagram CY7C1371D 512K x 36 CY7C1371D CY7C1373D WRITE DRIVERS dodi ADDRESS REGISTER MODE C CE ADV LD CEN d Fe WRITE ADDRESS REGISTER ADV LD BWA WRITE REGISTRY BWs AND DATA COHERENCY I CONTROL LOGIC BWc BWp WE 2 7 READ LOGIC CE2 SLEEP 2 CONTROL Logic Block Diagram CY7C1373D 1M x 18 WRITE DRIVERS ADDRESS REGISTER MODE C ADV LD CEN q WRITE ADDRESS REGISTER ADV LD PWA WRITE REGISTRY BWs AND DATA COHERENCY CONTROL LOGIC WE cm READ LOGIC tna ca SLEEP CONTROL Document 38 05556 Rev F U T D P S A U E T T N A MEMORY E ARRAY Sr gt T F Bon A E i DOP M E R R DOPc S S DQPp N E G INPUT K RE
17. 6 A BWg NC CEN ADV LD B NC 1G A CE2 NC BW CLK WE OE A A NC Vppa Vss Vss Vss Vss Vss VDDQ NC D NC DQg VDDQ VDD Vss Vss Vss VDD VDDQ NC NC DQg VDD Vss Vss Vss Vpp NC DQA F NC DQg VDD Vss Vss Vss Vpp NC G NC DQg VDDQ VDD Vss Vss Vss VDD VDDQ NC NC NC NC Vbi Vss Vss Vss Voo NC NC ZZ J DQg NC Vppa Vpp Vss Vss Vss Vpp Vppa DQA NC K VDD Vss Vss Vss VDD Vppa DQa NC L VDD Vss Vss Vss VDD VDDQ DQA NC M Vpp Vss Vss Vss Vpp DQA NC NC Vss NC NC NC Vss NC NC P NC 144M NC 72M A A TDI A1 TDO A A NC 288M R MODE NC 36M A A TMS AO TCK A A A Document 38 05556 Rev F Page 6 of 29 Feedback ae 2 d SS CYPRESS PERFORM Pin Definitions CY7C1371D CY7C1373D Name IO Description Ay Input Address Inputs used to select one of the address locations Sampled at the rising edge of the Synchronous CLK 0 are fed to the two bit burst counter BWA BWg Input Byte Write Inputs Active LOW Qualified with WE to conduct writes to the SRAM Sampled on BWc BWp Synchronous the rising edge of CLK WE Input Write Enable Input Active LOW Sampled on the rising edge of CLK if CEN
18. 62 D2 63 E2 64 F2 65 G2 66 H1 67 H3 68 J1 69 K1 70 L1 71 M1 72 J2 73 K2 74 L2 75 M2 76 N1 77 2 78 P1 79 R1 80 R2 81 P3 82 R3 83 P2 84 R4 85 P4 86 N5 87 P6 88 R6 89 Internal Note 15 Bit 89 is pre set HIGH Document 38 05556 Rev F Page 18 of 29 Feedback CY7C1371D T CY7C1373D 2 CYPRESS PERFORM 1 DC Input Voltage 0 5V to Vpp 0 5V Maximum Ratings 3 Current into Outputs LOW eene 20 mA Exceeding maximum ratings may impair the useful life of the UA device These user guidelines are not tested Mc gt 2001V Storage Temperature 65 to 150 o E TER Ambient Temperature with atch up gt 200m Power Applied oen 55 C to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 5V to Vpp Range Temperature Vpp Voltage Applied to Outputs Commercial 0 C to 70 3 3V 5 10 2 5V 5 in 2 0 5V to 0 5V Industrial 40 C to 85 to Vpp Electrical Characteristics Over the Operati
19. GISTER 0 U T D P A U T T A MEMORY B gt 5 U bas 4 E E DOPs R R S N E G INPUT lt REGISTER lt 2 29 Feedback Pin Configurations 100 Pin TQFP Pinout IS lt a gt an KSE lt lt lt Sgsg5952329598929359929895 DQPc 3 1 80 DQc L2 79 DQc 13 78 4 7T Vss 5 76 BYTE C 6 75 DQc L3 7 74 DQc L8 73 9 72 Vss 10 71 11 70 12 69 13 68 NC B 14 CY7C1371D 67 Vpp 15 66 NCC 16 65 Vss 17 64 18 63 DQp 19 62 Vppa 20 61 Vss 21 60 J 22 59 BYTED H 23 58 24 57 Dap C 25 56 Vss L 26 55 27 54 28 53 DQp 29 52 DQPp 30 51 1 0 Vpp NC 72M MODE NC 36M Document 38 05556 Rev F NC 288M Vss NC 144M lt lt lt lt lt lt lt DOP Vss VDDQ
20. Partial Truth Table for Read Write 3 9 Function CY7C1373D WE BW BWs Read H X X Write No bytes written L H H Write Byte A DQ and L L H Write Byte B DQg L H L Write All Bytes L L L Notes 2 X Don t Care H Logic HIGH L Logic LOW BWy 0 signifies at least one Byte Write Select is active BWy Valid signifies that the desired byte write selects are asserted see truth table for details 3 Write is defined by BWx and WE See truth table for Read Write 4 When a write cycle is detected all IOs are tri stated even during byte writes 5 The DQs and DQP pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 6 CEN inserts wait states 7 Device powers up deselected and the lOs in a tri state condition regardless of OE 8 OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and DQPy Tri state when is inactive or when the device is deselected and DQs DQPy data when OE is active 9 Table only lists a partial listing of the byte write combinations Any Combination of i is valid Appropriate write is based on which byte write is active Document 38 05556 Rev F Page 10 of 29 Feedback IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1371D CY7C1373D incorporates a serial boundary scan test access port TAP This
21. Register Name Bit Size x36 Bit Size x18 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 Ball BGA package 85 85 Boundary Scan Order 165 Ball FBGA package 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and Forces all SRAM outputs to High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures IO ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 de the bypass register between TDI and TDO This operation does not affect SRAM operations Document 38 05556 Rev F Page 16 of 29 Feedback CY7C1371D SES PERFORM 119 Ball BGA Boundary Scan Order 73 141 Bit Ball ID Bit Ball ID Bit Ball ID Bit Ball ID 1
22. a _ e Se SSE ecr CY7C1371D CY7C1373D YPRESS PERFOR 18 Mbit 512K x 36 1M x 18 Flow Through SRAM with NoBL Architecture Features No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles Supports up to 133 MHz bus operations with zero wait states Data is transferred on every clock Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to eliminate the need to use OE Registered inputs for flow through operation Byte Write capability 3 3V 2 5V IO power supply Vppq Fast clock to output times 6 5 ns for 133 MHz device Clock Enable CEN pin to enable clock and suspend operation Synchronous self timed writes Asynchronous Output Enable Available in JEDEC standard Pb free 100 pin TQFP Pb free and non Pb free 119 Ball BGA and 165 Ball FBGA package Three chip enables for simple depth expansion Automatic Power down feature available using ZZ mode or CE deselect IEEE 1149 1 JTAG Compatible Boundary Scan Burst Capability linear or interleaved burst order Low standby power Selection Guide Functional Description The CY7C1371D CY7C1373D is a 3 3V 512K x 36 1M x 18 Synchronous flow through Burst SRAM designed specifically to support unlimited true back to back Read Write operatio
23. anged try tr from 25 ns to 20 ns and from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table p 1274734 See ECN VKN AESA Corrected typo in the STALL and DESELECT Cycles waveform Document 38 05556 Rev F Page 29 of 29 Feedback
24. ces all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into t
25. d A in the burst sequence and wraps around when incremented sufficiently A HIGH input on ADV LD increments the internal burst counter regardless of the state of chip enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE2 and CE are ALL asserted active and 3 the write signal WE is asserted LOW The address presented to the address bus is loaded into the Address Register The write signals are latched into the Control Logic block The data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQs and DQPy On the next clock rise the data presented to DQs and DOP or a subset for byte write operations see truth table for Page 8 of 29 Feedback details inputs is latched into the device and the write is complete Additional accesses Read Write Deselect can be initiated on this cycle The data written during the Write operation is controlled by BW signals The CY7C1371D CY7C1373D provides byte write capability that is described in the truth table Asserting the Write Enable input WE with the selected Byte Write Select input selectively writes to only the desired bytes Bytes not selected duri
26. e Deselected All Speeds 80 mA Power down Vin gt Vpp 0 3V or Vin lt gay f 7 Current TTL Inputs 0 inputs static Notes 16 Overshoot lt 1 5V Pulse width less than 2 undershoot Vi AC gt 2V Pulse width less than 2 17 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt and lt Vpp Document 38 05556 Rev F Page 19 of 29 CY7C1371D yz CY7C1373D Capacitance l 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit CiN Input Capacitance TA 25 f 1 MHz 5 8 9 pF Vpp 3 3V Clock Input Capacitance 2 5V 5 8 9 Cio Input Output Capacitance 5 8 9 pF Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit OJA Thermal Resistance Test conditions follow standard 28 66 23 8 20 7 C W Junction to Ambient test methods and procedures for measuring thermal Thermal Resistance impedance according to 4 08 6 2 4 0 CN Junction to Case EIA JESD51 AC Test Loads and Waveforms 3 3V IO Test Load R 3170 OUTPUT 3 3V ALL INPUT PULSES OUTPUT 500 5pF L R 3510 1 5V INCLUDING a JIG AND a scope 5 25V R 16670 OUTPUT 500 5pF L 15380 1 25V INCLUDING A JIG AND c
27. ed state when the device has been deselected CEN Input Clock Enable Input Active LOW When asserted LOW the Clock signal is recognized by the Synchronous SRAM When deasserted HIGH the Clock signal is masked While deasserting CEN does not deselect the device use CEN to extend the previous cycle when required ZZ Input ZZ Sleep Input This active HIGH input places the device in a non time critical sleep condition Asynchronous with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQ Bidirectional Data IO lines As inputs they feed into on chip data register that is triggered by Synchronous he rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ and placed in a tri state condition The outputs are automatically tri stated during the data portion ate write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPx Bidirectional Data Parity IO Lines Functionally these signals are identical to Synchronous MODE Input Strap Mode Input Selects the burst order of the device When tied to Gnd selects l
28. ess products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CY7C1371D lle CY7C1373D Document History Page Document Title CY7C1371D CY7C1373D 18 Mbit 512K x 36 1 Mbit x 18 flow through SRAM with NoBL Architecture Document Number 38 05556 Issue Orig of REV ECN NO Date Change Description of Change TE 254513 See RKF New data sheet 288531 See SYT Edited description under IEEE 1149 1 Serial Boundary Scan JTAG for non compliance with 1149 1 Removed 117 Mhz Speed Bin Added Pb free information for 100 Pin TQFP 119 BGA and 165 FBGA Packages Added comment of Pb free BG packages availability below the Ordering Infor mation B 326078 See PCI Address expansion pins balls in the pinouts for all packages are modified according to JEDEC standard Added description on EXTEST Output Bus Tri State Changed description on the Tap Instruction Set Ove
29. he Shift DR state This places the bound ary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri or to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the Page 12 of 29 Feedback YPRESS PERFORM boundary scan path when multiple devices are connected together on a board EXTEST Output Bus Tri State IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 85 for 119 BGA package or bit 89 for 165 fBGA package When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into
30. ial CY7C1373D 133AXI CY7C1371D 133BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1373D 133BGI CY7C1371D 133BGXI 51 85115 119 Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1373D 133BGXI CY7C1371D 133BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1373D 133BZI CY7C1371D 133BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1373D 133BZXI 100 CY7C1371D 100AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1373D 100AXC CY7C1371D 100BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1373D 100BGC CY7C1371D 100BGXC 51 85115 119 Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1373D 100BGXC CY7C1371D 100BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1373D 100BZC CY7C1371D 100BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1373D 100BZXC CY7C1371D 100AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1373D 100AXI CY7C1371D 100BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1373D 100BGI CY7C1371D 100BGXI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1373D 100BGXI CY7C1371D 100BZI 51 85180 165 Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1373D 100BZI CY7C1371D 100BZXI 51 85180 165 Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1373D 100BZXI
31. inear burst sequence When tied to Vpp or leftfloating selects interleaved burst sequence Vpp Power Supply Power supply inputs to the core of the device Vppa IO Power Power supply for the IO circuitry Supply Vss Ground Ground for the device Document 38 05556 Rev F Page 7 of 29 Feedback CY7C1371D CY7C1373D Pin Definitions continued Name IO Description TDO JTAG serial Serial data out to the JTAG circuit Delivers data on the negative edge of TCK If the JTAG output feature is not being used this pin must be left unconnected This pin is not available on TQFP Synchronous packages TDI JTAG serial Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature is not input being used this pin can be left floating or connected to Vpp through a pull up resistor This pin is Synchronous not available on TQFP packages TMS JTAG serial Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature is not input being used this pin can be disconnected or connected to Vpp This pin is not available on TQFP Synchronous packages TCK JTAG Clock input to the JTAG circuitry If the JTAG feature is not being used this pin must be Clock connected to Vss This pin is not available on TQFP packages NC No Connects Not internally connected to the die NC 36 M 72 M 144 M 288M 576M 1 address expansion pins and are not internally c
32. is active LOW This Synchronous signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to advance the on chip address counter or load a new address When Synchronous HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD must be driven LOW to load a new address CLK Input Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN CLK Clock is only recognized if CEN is active LOW CE Input Chip Enable 1 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous gt and CE to select deselect the device Input Chip Enable 2 Input Active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device CE Input Chip Enable 3 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous and CE to select deselect the device OE Input Output Enable asynchronous input Active LOW Combined with the synchronous logic block Asynchronous inside the device to control the direction of the pins When LOW the IO pins are allowed to behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselect
33. ng Rangel 17 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ IO Supply Voltage for 3 3V IO 3 135 Vpp V for 2 5V IO 2 375 2 625 V Output HIGH Voltage for 3 3V IO 4 0 24 V for 2 5V IO lop 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V IO Io 8 0 mA 0 4 V for 2 5V IO Io 1 0 mA 0 4 V Input HIGH Voltagel 6l for 3 3V 10 20 Vpp 03V V for 2 5V IO 1 7 Vpp 03V V Vit Input LOW Voltagel 4l for 3 3V IO 0 3 0 8 V for 2 5V IO 0 3 0 7 V Ix Input Leakage Current GND x Vj lt 5 5 except ZZ and MODE Input Current of MODE Input Vss 30 uA Input Vpp 5 Input Current of ZZ Input Vss 5 Input Vpp 30 155 Vpp Operating Supply Vpp Max 0 mA 7 5 ns cycle 133 MHz 210 mA Current f fmax 10 ns cycle 100 MHz 175 mA Isp4 Automatic CE Vpp Max Device Deselected 7 5 ns cycle 133 MHz 140 mA Power down Vin gt or Vin E Vi Current TTL Inputs f fmax inputs switching 10s eyele TOU MIS 120 mA Ispo Automatic CE Vpp Max Device Deselected All speeds 70 mA Power down Vin lt 0 3V or Vin gt Vpop 0 3 Current CMOS Inputs f 0 inputs static Automatic CE Vpp Max Device Deselected or 7 5 ns cycle 133 MHz 130 mA Power down Vin 0 3V or Vin gt 0 3V Current CMOS Inputs f fmax inputs switching 10e cyclen 4 Automatic CE Vpp Max Devic
34. ng a byte write operation remains unaltered A synchronous self timed write mechanism has been provided to simplify the write operations Byte write capability has been included to greatly simplify Read Modify Write sequences which can be reduced to simple byte write operations Because the CY7C1371D CY7C1373D is a common IO device data must not be driven into the device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQs DQPx inputs Doing so tri states the output drivers As a safety precaution DQs and DQPy are automatically tri stated during the data portion of a write cycle regardless of the state of OE Burst Write Accesses The CY7C1371D CY7C1373D has an on chip burst counter that allows the user the ability to supply a single address and CY7C1371D CY7C1373D clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE and CE3 must remain inactive for the duration of tzzggc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address 0 A0 AO AO 00 01 10 11 01 00 11 10
35. ns with no wait state insertion The CY7C1371D CY7C1373D is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read Write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximum access delay from the clock rise is 6 5 ns 133 MHz device Write operations are controlled by the two or four Byte Write Select BWy and a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE4 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control To avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 5 ns Maximum Operating Current 210 175 mA Maximum CMOS Standby Current 70 70 Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com 198 Champion Court Jose CA 9513
36. onnected to the die Functional Overview The CY7C1371D CY7C1373D is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recog nized and all internal states are maintained All synchronous operations are qualified with CEN Maximum access delay from the clock rise tcpy is 6 5 ns 133 MHz device Accesses can be initiated by asserting all three Chip Enables CE4 CE2 CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device is latched The access can either be a read or write operation depending on the status of the Write Enable WE BW be used to conduct byte write operations Write operations are qualified by the Write Enable WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE4 CE3 and an asynchronous Output Enable OE simplify depth expansion All operations Reads Writes and Deselects are pipelined ADV LD must be driven LOW after the device has been deselected to load a new address for the next operation Single Read Accesses A read access is initiated when these conditions are sa
37. ons are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and must not be used The other five instruc tions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction after it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST The EXTEST instruction enables the preloaded data to be driven outthrough the system output pins This instruction also selects the boundary scan register to be connected for serial Document 38 05556 Rev F CY7C1371D CY7C1373D access between the TDI and TDO in the shift DR controller state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also pla
38. part is fully compliant with 1149 1 The TAP operates using JEDEC standard 3 3V or 2 5V IO logic levels The CY7C1371D CY7C1373D contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device is up in a reset state which does not interfere with the operation of the device TAP Controller State Diagram e TEST LOGIC RESET 0 Y SELECT IR SCAN SELECT DR SCAN 0 0 Y Y CAPTURE DR CAPTURE IR Cy RUN TEST IDLE D 4 UPDATE DR UPDATE IR Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP
39. rview and Extest Changed and for TQFP Package from 31 and 6 C W to 28 66 and 4 08 C W respectively Changed and Oc for BGA Package from 45 and 7 C W to 23 8 and 6 2 C W respectively Changed and for FBGA Package from 46 and 3 C W to 20 7 and 4 0 C W respectively Modified VoL Vox test conditions Removed comment of Pb free BG packages availability below the Ordering Infor mation Updated Ordering Information Table C 345117 See ECN PCI Updated Ordering Information Table Changed from Preliminary to Final North First Street to 198 Champion Court NEN In the Partial Truth Table for Read Write on page 10 the BW of Write Byte A DQ and and BWg of Write Byte DQg and DQPg has been changed from H to L Changed the description of lx from Input Load Current to Input Leakage Current on 20 Changed the Ix current values of MODE on page 20 from 5 uA and 30 pA to 30 uA and 5 pA Changed the Ix current values of ZZ on page 20 from 30 pA and 5 pA to 5 pA and 30 pA Changed Vpp to lt Vppon page 20 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table D 416321 See NXR Changed address of Cypress Semiconductor Corporation on 1 from 3901 E 475677 See Added the Maximum Rating for Supply Voltage Vppo Relative to GND Ch
40. s tes Capture Setup to TCK Rise 5 ns Hold Times ttmsH TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns tcu Capture Hold after Clock Rise 5 ns Notes 10 tcs and refer to the setup and hold time requirements of latching data from the boundary scan register 11 Test conditions are specified using the load AC test Conditions tp tp 1 ns Document 38 05556 Rev F Page 14 of 29 Feedback CY7C1371D SES Cons DUCI PERFORM 3 3V TAP AC Test Conditions 2 5V TAP AC Test Conditions Input pulse levels ne to 3 3V Inp t p lse level nr Vss to 2 5V Input rise and fall 22 222 1 ns Input rise and fall time 2 2 24 4 022 1ns Input timing reference levels 1 5V Input timing reference 1 25V Output reference 1 5V Output reference levels 1 25V Test load termination supply voltage 1 5V Test load termination supply voltage 1 25V 3 3V TAP AC Output Load Equivalent 2 5V TAP AC Output Load Equivalent 1 5V 1 25V 500 500 TDO TDO Zo 500 20pF Z4 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt lt 70
41. s a voltage regulator internally tpowe_r is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 20 tcuz 2 togr z and togpz are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 21 At any voltage and temperature togpz is less than tog 7 and is less than 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 22 This parameter is sampled and not 100 tested 23 Timing reference level is 1 5V when 3 3V and is 1 25V when 2 5V 24 Test conditions shown in a of AC Test Loads unless otherwise noted Document 38 05556 Rev F Page 21 of 29 Feedback CY7C1371D CYPRESS CYPRESS CY7C1373D PERFORM Switching Waveforms Read Write Waveforms2 26 27 1 2 toc 3 4 5 6 7 8 9 10 1 tcENH J cL A UA aA nm HH P ER EL A Hi V BWx A XI ADDRESS 2 NS 6 tas tcHz
42. t lt y CLK t77 ZZ zz supp 10022 ALL INPUTS except ZZ DESELECT or READ Only Outputs Notes 29 Device must be deselected when entering ZZ mode See truth table for all possible signal conditions to deselect the device 30 DGs are in high Z when exiting ZZ sleep mode Document 38 05556 Rev F W DON T CARE Page 24 of 29 Feedback T CY7C1371D b eos CY7C1373D j PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 133 CY7C1371D 133AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1373D 133AXC CY7C1371D 133BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1373D 133BGC CY7C1371D 133BGXC 51 85115 119 Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1373D 133BGXC CY7C1371D 133BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 CY7C1373D 133BZC CY7C1371D 133BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1373D 133BZXC CY7C1371D 133AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industr
43. tain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the ldentification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinati
44. tisfied at clock rise CEN is asserted LOW CE4 CE and are ALL asserted active The Write Enable input signal WE is deasserted HIGH ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic The control logic determines that a read access Document 38 05556 Rev F is in progress and allows the requested data to propagate to the output buffers The data is available within 6 5 ns 133 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data On the subsequent clock another operation Read Write Deselect can be initiated When the SRAM is deselected at clock rise by one of the chip enable signals its output is tri stated immediately Burst Read Accesses The CY7C1371D CY7C1373D has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is deter mined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use Ag an
Download Pdf Manuals
Related Search