adcrm/d
Contents
1. S8CM CD CC CB CA Input Result Register 0 0 0 0 0 ANO RSLTO 0 0 0 0 1 AN1 RSLTO RSLT3 0 0 0 1 0 AN2 RSLTO RSLT3 0 0 0 1 1 AN3 RSLTO RSLT3 0 0 1 0 0 AN4 RSLTO RSLT3 0 0 1 0 1 AN5 RSLTO RSLT3 0 0 1 1 0 ANG RSLTO RSLT3 0 0 1 1 1 AN7 RSLTO RSLT3 0 1 0 0 0 Reserved RSLTO RSLT3 0 1 0 0 1 Reserved RSLTO RSLT3 0 1 0 1 0 Reserved RSLTO 0 1 0 1 1 Reserved RSLTO RSLT3 0 1 1 0 0 VRH RSLTO RSLT3 0 1 1 0 1 VRL RSLTO RSLT3 0 1 1 1 0 VRH VAL 2 RSLTO RSLT3 0 1 1 1 1 Test Reserved RSLTO 1 0 0 0 0 RSLTO RSLT7 1 0 0 0 1 AN1 RSLTO RSLT7 1 0 0 1 0 AN2 RSLTO RSLT7 1 0 0 1 1 AN3 RSLTO RSLT7 1 0 1 0 0 AN4 RSLTO RSLT7 1 0 1 0 1 AN5 RSLTO RSLT7 1 0 1 1 0 ANG RSLTO RSLT7 1 0 1 1 1 AN7 RSLTO RSLT7 1 1 0 0 0 Reserved RSLTO RSLT7 1 1 0 0 1 Reserved RSLTO RSLT7 1 1 0 1 0 Reserved RSLTO RSLT7 1 1 0 1 1 Reserved RSLTO RSLT7 1 1 1 0 0 VRH RSLTO RSLT7 1 1 1 0 1 VRL RSLTO RSLT7 1 1 1 1 0 VRH VRL 2 RSLTO RSLT7 1 1 1 1 1 Test Reserved RSLTO RSLT7 MOTOROLA 5 6 DIGITAL CONTROL SUBSYSTEM ADC REFERENCE MANUAL Table 5 6 Multiple Channel Conversions S8CM CD CC CB CA Input Result Register 0 0 0 X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 AN3 RSLT3 0 0 1 X X AN4 RSLTO AN5 RSLT1 AN6 RSLT2 AN7 RSLT3 0 1 0 X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Res2. Modular Microcontroller Family ADC ANALOG TO DIGITAL CONVERTER Reference Manual Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any cl
3. 1 1 Analog Subsystem The analog subsystem consists of a multiplexer an input sample amplifier a resistor capacitor digital to analog converter RC DAC array and a high gain comparator The multiplexer selects one of eight internal or eight external signal sources for con version The sample amplifier buffers external high impedance sources from the inter nal circuitry The RC DAC array performs two functions it acts as a sample and hold circuit and it provides the digital to analog comparison output necessary for succes sive approximation conversion The comparator indicates whether each successive output of the RC DAC array is higher or lower than the sampled input SECTION 4 AN ALOG SUBSYSTEM describes this subsystem in greater detail 1 2 Digital Control Subsystem The digital control subsystem contains registers and logic to control the conversion process Control registers and associated logic select the conversion resolution eight or ten bits multiplexer input conversion sequencing mode sample time and ADC clock cycle As each input is converted the digital control subsystem stores the result one bit at a time in the successive approximation register SAR and then transfers the result to one of eight result registers Each result is available in three formats right justified unsigned left justified signed and left justified unsigned depending on the address from which it is read SECTION 5 DIGITAL CONTROL SUBSYSTEM de
4. Refer to 5 2 Clock and Prescaler Control for more information ADCTL1 ADC Control Register 1 XXXXOC 15 8 7 6 5 4 3 2 1 0 NOT USED SCAN MULT secm CD cc CB CA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAN Scan Mode Selection Bit 0 Single conversion sequence 1 Continuous conversion MULT Multichannel Conversion Bit 0 Conversion sequence s run on a channel selected by CD CA 1 Sequential conversion of four or eight channels selected by CD CA S8CM Select Eight Conversion Sequence Mode 0 Four conversion sequence 1 Eight conversion sequence CD CA Channel Selection The bits in this field are used to select an input or block of inputs for A D conversion Table 5 5 and Table 5 6 explain the operation of these fields ADSTAT ADC Status Register XXXXOE 15 14 11 10 8 7 0 SCF NOT USED CCTR CCF RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCF Sequence Complete Flag This bit is set at the end of the conversion sequence when SCAN 0 in ADCTL1 and set at the end of the first conversion sequence when SCAN 1 0 Sequence not complete 1 Sequence complete ADC MEMORY MAP AND REGISTERS MOTOROLA REFERENCE MANUAL B 3 CCTR 2 0 Conversion Counter This field shows the content of the conversion counter pointer during a conversion se quence The value is the number of the next result register to be written to i e the channel currently
5. scribes the digital control functions in detail ADC FUNCTIONAL OVERVIEW MOTOROLA REFERENCE MANUAL 1 1 VDDA lt veca SUPPLY yet REFERENCE RC DAC ARRAY 2 AND AN7 PADA7 COMPARATOR ANG PADAG ANALOG L ANS PADAS MUX L ANA PADAA AND SAMPLE L ANS PADA3 BUFFER AMP L AN2 PADA2 ANTIPADAT ANO PADAO SAR RESERVED RESERVED MODE RESERVED RESERVED INTERNAL TIMIN RESERVED i PORT ADA DATA REGISTER 1 gt PADB7 gt PADB6 5 PORT ADB gt EADS L gt PADB4 REGISTER gt EADBS RESULT 6 gt PADB2 __1 gt PADBA RESULT 7 SD 1 1 1 1 1 1 1 1 1 1 INTERMODULE BUS IMB Figure 1 1 ADC Block Diagram 1 3 General Purpose I O In addition to use as multiplexer inputs the eight analog inputs can be used as a gen eral purpose digital input port port ADA provided signals are within logic level spec ification Port ADB is a dedicated output port A port data register PDR is used to access data from these ports Refer to SECTION 2 SIGNAL DESCRIPTIONS and 3 3 General Purpose I O for more information on ports ADA and ADB 1 4 Module Configuration The ADC module configuration register ADCMCR controls the interaction between the ADC and other modules Low power stop mode and freeze mode are ADC oper ating modes associated with assertion of IMB signals by other mic
6. S U ADC Result Register 7 RSLT7 S Supervisor accessible only S U Supervisor or user accessible depending on state of the SUPV bit in the ADCMCR MOTOROLA 1 4 FUNCTIONAL OVERVIEW ADC REFERENCE MANUAL SECTION 2 SIGNAL DESCRIPTIONS The ADC uses up to 20 pins Up to eight pins are analog inputs which can also be used as digital inputs two pins are analog reference connections and two pins are analog supply connections In addition eight pins serve as digital output pins in certain microcontroller systems In systems not requiring these pins they are not implement ed and the outputs from the module are not connected Refer to the appropriate mi crocontroller user s manual for specific information 2 1 Analog Digital Input Pins AN 7 0 PADA 7 0 Each of the eight analog input pins AN 7 0 is connected to a multiplexer in the ADC The multiplexer selects an analog input to convert to digital data Input voltages to the multiplexer must be between Vr and Refer to SECTION 6 PIN CONNECTION CONSIDERATIONS for recommendations on filtering the analog inputs The analog input pins can also be read as digital inputs provided the applied voltage is within the limits specified in APPENDIX A ELECTRICAL CHARACTERISTICS When used as digital inputs the pins are organized into an 8 bit port port ADA Data for port A is latched in the lower half of the 16 bit port data register PDR The digital inputs are then ref
7. VrH This results in a maximum obtainable 10 bit conversion value of 3FE At the bottom of the signal range Vssa is 15 mV higher than VRL resulting in a minimum obtainable 10 bit conversion value of 3 10 BIT RESULT 0 N 0 010 020 030 5100 5110 5120 5130 5 140 INPUT IN VOLTS VRH 5 120 V VRL 0 V Figure 6 2 Errors Resulting from Clipping 6 3 Analog Input Pins Analog inputs should have low AC impedance at the pins Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part Ideally that capacitor should be as large as possible within the practi MOTOROLA PIN CONNECTION CONSIDERATIONS ADC 6 2 REFERENCE MANUAL cal range of capacitors that still have good high frequency characteristics This capac itor has two effects First it helps attenuate any noise that may exist on the input Second it sources charge during the sample period when the analog signal source is a high impedance source Series resistance can be used with the capacitor on an input pin to implement a simple RC filter The maximum level of filtering at the input pins is application dependent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input Simple RC filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analo
8. additional in formation PRS 4 0 Prescaler Rate Selection 00000 System Clock 4 00001 System Clock 4 00010 System Clock 6 00011 System Clock 8 11101 System Clock 60 11110 System Clock 62 11111 System Clock 64 The system clock is divided by the PRS value plus one then divided by two to deter mine the ADC clock Assigning a value of zero to this field however has the same effect as assigning a value of one Refer to 5 2 Clock and Prescaler Control for more information 5 7 2 ADC Control Register 1 ADCTL1 ADCTL1 is used to select the conversion mode and the channel or channels to be con verted Writing to this register aborts any conversion in progress and initiates a new conversion Refer to 5 5 Conversion Mode and 5 6 Channel Selection for additional information on these fields ADCTL1 ADC Control Register 1 XXXXOC 15 8 7 6 5 4 3 2 1 0 NOT USED SCAN MULT secm cb CC cB CA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAN Scan Mode Selection 0 Single conversion sequence 1 Continuous conversion MOTOROLA DIGITAL CONTROL SUBSYSTEM ADC 5 8 REFERENCE MANUAL MULT Multichannel Conversion 0 Conversion sequence s run on a channel selected by CD CA 1 Sequential conversion of four or eight channels selected by CD CA S8CM Select Eight Conversion Sequence Mode 0 Four conversion sequence 1 Eight conversion sequence CD CA Cha
9. bit Result 10 bit Result Not Used The conversion result is unsigned left justified data Bits 15 6 are used for 10 bit res olution bits 15 8 are used for 8 bit conversion bits 7 6 are zero Bits 5 0 always return zero when read MOTOROLA MEMORY MAP AND REGISTERS ADC B 4 REFERENCE MANUAL
10. resumes If the ADC freezes during a conversion activity resumes with the next step in the con version sequence However capacitors in the analog conversion circuitry may dis charge while the ADC is frozen and conversion results may be inaccurate 3 2 3 Privilege Levels To protect system resources the processor in certain MCUs can operate at either of two privilege levels user or supervisor In systems that support privilege levels ac cesses of the ADCMCR and ADCTEST registers are permissible only when the CPU is operating at the supervisor privilege level The remaining ADC registers are pro grammable to permit supervisor access only or to permit access when the CPU is op erating at either privilege level If the SUPV bit in the ADCMCR is set access to ADC registers is permitted only when the CPU is operating at the supervisor level If SUPV is clear then both user and su pervisor accesses of all registers other than the ADCMCR and ADCTEST register are permitted The ADC does not respond to a read or write of a supervisor access register when the CPU is operating at the user privilege level Attempting such a read or write results in the bus access being transferred externally Refer to the SIM or SCIM section of the appropriate MCU user s manual for details on external bus cycles to unimplemented locations MOTOROLA CONFIGURATION AND CONTROL ADC 3 2 REFERENCE MANUAL MCUs that do not support privilege levels always operate a
11. the control and status registers Register diagrams are provided later in this section They are also provided in APPENDIX B MEMORY MAP AND REGISTERS 5 1 Conversion Timing Total conversion time is made up of initial sample time transfer time final sample time and resolution time Initial sample time refers to the time during which the selected in put channel is connected to the sample capacitor at the input of the sample buffer am plifier During the transfer period the sample capacitor is disconnected from the multiplexer and the stored voltage is buffered and transferred to the RC DAC array During the final sampling period the sample capacitor and amplifier are bypassed and the multiplexer input charges the RC DAC array directly During the resolution pe riod the voltage in the RC DAC array is converted to a digital value and stored in the SAR Initial sample time and transfer time are fixed at 2 ADC clock cycles each Final sample time can be 2 4 8 or 16 ADC clock cycles depending on the value of the STS field in ADCTLO Refer to 5 3 Final Sample Time Resolution time is 10 cycles for 8 bit conversion and 12 cycles for 10 bit conversion Transfer and resolution therefore require a minimum of 16 ADC clocks 8 us with a 2 1 MHz ADC clock for 8 bit resolution or 18 ADC clocks 9 us with a 2 1 MHz ADC clock for 10 bit resolution If the user selects the maximum final sample time period of 16 ADC clocks the total conversion
12. 2 V one 10 bit count 5 mV and one 8 bit count 20 mV 3 8 bit absolute error of 1 count 20 mV includes 1 2 count 10 mV inherent quantization error and 1 2 count 10 mV circuit differential integral and offset error 4 10 bit absolute error of 2 5 counts 12 5 mV includes 1 2 count 2 5 mV inherent quantization error and 2 counts 10 mV circuit differential integral and offset error 5 Maximum source impedance is application dependent Error resulting from pin leakage depends on junction leakage into the pin and on charge sharing effects with internal capacitors Error from junction leakage is a func tion of source impedance and input leakage current Verr Rs lorr where lorr is a function of operating temperature See note 4 in Table A 2 Charge sharing effects with internal capacitors are a function of ADC clock speed the number of channels being scanned and source impedance For 10 bit conversions charge pump leakage is computed as follows Vero 25 PF Vona Rse ADCLK 9 e number of channels For 8 bit conversions charge pump leakage is computed as follows Verg 25 PF e Vppa Rg e ADCLK 8 e number of channels ADC ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 3 O S P KL 2 IDEAL TRANSFER CURVE 8 BIT TRANSFER CURVE a NO CIRCUIT ERROR E i 2 5 E ES o O a N E J a ES Ze a LS 0 20 40 60 80 INPUT IN mV VRH V
13. 3 Analog IMPUI PINS itt e a aula 6 3 1 Settling Time for the External Circuit ocooonnnncccnnnnnnnncnnccccnnnnnnnnncnnos 6 3 2 Error Resulting from Leakage esses APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B MEMORY MAP AND REGISTERS B 1 Memory Map uoo oie aos anon defer paa Jon usce pet B 2 MOTOROLA iv ADC REFERENCE MANUAL LIST OF ILLUSTRATIONS Figure Title 1 1 ADG Block Diagram eec letus 5 1 8 Bit Conversion Timing ccccoononccccnnnnnccononcncnnnnnnnnnncnnnncnnnnnos 5 2 10 Bit Conversion Timing eeseeesseee 5 3 ADC Clock and Prescaler Control 6 1 Analog Input Circuitry sc ida ua t oda icu onus aec d den 6 2 Errors Resulting from Clipping ies 6 3 Electrical Model of an A D Input Pin A 1 Circuit and Quantization Error in 8 Bit Conversions A 2 Circuit and Quantization Error in 10 Bit Conversions ADC REFERENCE MANUAL MOTOROLA LIST OF ILLUSTRATIONS Continued Figure Title Page MOTOROLA ADC vi REFERENCE MANUAL LIST OF TABLES Table Title Page 1 1 Module Memory Map eiit eii a li 1 4 FRZ Field Selection bie aie et 3 2 5 1 CE 5 3 BAe S TS Held OSelGclo i o cer ea ee DR te CEU Na e 5 4 5 3 Conversion Mode x i te tele 5 4 ADC Conversi
14. 4 0 MHz 16 8 MHz 11101 System Clock 60 30 0 MHz 11110 System Clock 62 31 0 MHz 11111 System Clock 64 32 0 MHz 5 3 Final Sample Time ADC DIGITAL CONTROL SUBSYSTEM During the final sample period the selected channel is connected directly to the RC DAC array for the specified sample time The value of the STS sample time select field in ADCTLO determines final sample time in ADC clock cycles The sample period is thus determined by both the PRS field which controls the ADC clock period and the STS field Final sample time can be 2 4 8 or 16 ADC clocks see Table 5 2 MOTOROLA REFERENCE MANUAL 5 3 Table 5 2 STS Field Selection STS 1 0 Sample Time 00 2 A D Clock Periods 01 4 A D Clock Periods 10 8 A D Clock Periods 11 16 A D Clock Periods 5 4 Resolution ADC resolution can be either eight or ten bits Resolution is determined by the state of the RES10 bit in ADCTLO 0 8 bit resolution 1 10 bit resolution Both 8 bit and 10 bit conversion results are automatically aligned in the result registers Refer to 5 1 Conversion Timing for the time required for 8 and 10 bit conversions 5 5 Conversion Mode Conversion mode is controlled by three bits in ADCTL1 Table 5 3 shows the meaning of these bits Table 5 3 Conversion Mode Bits Bit Meaning SCAN Conversion can be limited to a single sequence or performed Scan mode selection continuously 0 Single sequence 1 Conti
15. AL 5 120 V A 1 2 count 10 mV inherent quantization error B Circuit contributed 10 mV error 20 mV absolute error one 8 bit count Figure A 1 Circuit and Quantization Error in 8 Bit Conversions MOTOROLA ELECTRICAL CHARACTERISTICS ADC A 4 REFERENCE MANUAL n 9 IDEAL TRANSFER CURVE SA 10 BIT TRANSFER CURVE od NO CIRCUIT ERROR E A 5 SR a XU 5 a O S E A 2d 4 0 20 40 60 80 INPUT IN mV Van 5 120 V A 1 2 count 2 5 mV inherent quantization error B Circuit contributed 10 mV error C 412 5 mV absolute error 2 1 2 10 bit counts Figure A 2 Circuit and Quantization Error in 10 Bit Conversions ADC ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 5 MOTOROLA ELECTRICAL CHARACTERISTICS ADC A 6 REFERENCE MANUAL APPENDIX B MEMORY MAP AND REGISTERS B 1 Memory Map Address Access Conirol Registers XXXX00 S Module Configuration Register ADCMCR XXXX02 S ADC Test Register ADCTEST XXXX04 S Reserved XXXX06 S U Port Data Register PDR XXXX08 S U Reserved XXXX0A S U ADC Control Register 0 ADCTLO XXXX0C S U ADC Control Register 1 ADCTL1 XXXXOE S U ADC Status Register ADSTAT Address Access Right Justified Unsigned Result Registers XXXX10 S U ADC Result Register 0 RSLTO XXXX12 S U ADC Resul
16. Access Control Registers XXXX00 S Module Configuration Register ADCMCR XXXX02 S ADC Test Register ADCTEST XXXX04 S Reserved XXXX06 S U Port Data Register PDR XXXX08 S U Reserved XXXX0A S U ADC Control Register 0 ADCTLO XXXX0C S U ADC Control Register 1 ADCTL1 XXXXOE S U ADC Status Register ADSTAT Address Access Right Justified Unsigned Result Registers XXXX10 S U ADC Result Register 0 RSLTO XXXX12 S U ADC Result Register 1 RSLT1 XXXX14 S U ADC Result Register 2 RSLT2 XXXX16 S U ADC Result Register 3 RSLT3 XXXX18 S U ADC Result Register 4 RSLT4 XXXX1A S U ADC Result Register 5 RSLT5 XXXX1C S U ADC Result Register 6 RSLT6 XXXX1E S U ADC Result Register 7 RSLT7 Address Access Left Justified Signed Result Registers XXXX20 S U ADC Result Register 0 RSLTO XXXX22 S U ADC Result Register 1 RSLT1 XXXX24 S U ADC Result Register 2 RSLT2 XXXX26 S U ADC Result Register 3 RSLT3 XXXX28 S U ADC Result Register 4 RSLT4 XXXX2A S U ADC Result Register 5 RSLT5 XXXX2C S U ADC Result Register 6 RSLT6 XXXX2E S U ADC Result Register 7 RSLT7 Address Access Left Justified Unsigned Result Registers XXXX30 S U ADC Result Register 0 RSLTO XXXX32 S U ADC Result Register 1 RSLT1 XXXX34 S U ADC Result Register 2 RSLT2 XXXX36 S U ADC Result Register 3 RSLT3 XXXX38 S U ADC Result Register 4 RSLT4 XXXX3A S U ADC Result Register 5 RSLT5 XXXX3C S U ADC Result Register 6 RSLT6 XXXX3E
17. RE AND SEQUENCE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4 CHANNEL MODE ENDS IF IN THE 8 CHANNEL MODE Figure 5 2 10 Bit Conversion Timing MOTOROLA DIGITAL CONTROL SUBSYSTEM ADC 5 2 REFERENCE MANUAL 5 2 Clock and Prescaler Control The ADC clock is derived from the system clock by a programmable prescaler The prescaler has two stages The first stage is a 5 bit modulus counter contained in the PRS field in ADCTLO The system clock is divided by this value 1 and then fed to the second stage a divide by two circuit to generate the ADC clock Figure 5 3 illustrates the relationship of ADC clock to system clock PR 4 0 SYSTEM CLOCK MODULUS COUNTER es ADC CLOCK Figure 5 3 ADC Clock and Prescaler Control ADC clock frequency must be between 0 5 and 2 1 MHz The reset value of the PRS field is 00011 which divides a nominal 16 78 MHz system clock by eight yielding maximum ADC clock frequency The clock generation circuitry ensures that the ADC clock can never be faster than one fourth the system clock speed Thus there are a minimum of four full IMB clock cycles for each ADC clock cycle Table 5 1 shows prescaler output values and associated minimum and maximum sys tem clock speeds Table 5 1 Prescaler Output PRS 4 0 ADC Clock Minimum Maximum System Clock System Clock 00000 Reserved 00001 System Clock 4 2 0 MHz 8 4 MHz 00010 System Clock 6 3 0 MHz 12 6 MHz 00011 System Clock 8
18. Register ADCMCR 3 3 3 3 General PurposeT scite ete ro opor e a esr Pierce pe e che 3 3 3 4 ADC Test Register ADCTEST nenea 3 4 3 5 Initialization roi eant setae d a 3 4 SECTION 4 ANALOG SUBSYSTEM 4 1 ITUNES Ease ates ed od ata ex t b a a ei E datu ud 4 1 4 2 Sample Buffer Amplifier aaa pestes 4 1 4 3 ROG DAGAA nn ile 4 2 4 4 ata 4 2 4 5 Successive Approximation Register SAR 4 2 SECTION 5 DIGITAL CONTROL SUBSYSTEM 5 1 Conversion TINTING o 5 1 5 2 Glock arid Prescaler Control se iata c a aaa 5 3 5 3 Final Sample Tide sicario ae 5 3 5 4 ESO e o ol 5 4 5 5 Conversion Mode 5 4 ADC MOTOROLA REFERENCE MANUAL iii TABLE OF CONTENTS Continued Paragraph Title 5 6 Channel Selecione E EE a ater edo d DU d n 5 7 Control and Status Registers 2 2 5 7 1 ADC Control Register 0 ADCTLO 5 7 2 ADC Control Register 1 5 7 3 ADC Status Register ADSTAT 5 8 Result Registers RSLTO RSLT7 SECTION 6 PIN CONNECTION CONSIDERATIONS 6 1 Analog Reference RIAS our a a ata 6 2 Analog Power PINS unirte til 6
19. Timing for additional information on ADC conversion timing ADC ANALOG SUBSYSTEM MOTOROLA REFERENCE MANUAL 4 1 4 3 RC DAC Array The RC DAC array consists of binary weighted capacitors and a resistor divider chain The array performs two functions it acts as a sample and hold circuit during conver sion and provides each successive digital to analog comparison voltage to the com parator Conversion begins with MSB comparison and ends with LSB comparison Array switching is controlled by the digital subsystem 4 4 Comparator The comparator indicates whether each approximation output from the RC DAC array during resolution is higher or lower than the sampled input voltage Comparator output is fed to the digital control logic which sets or clears each bit in the successive approx imation register in sequence MSB first 4 5 Successive Approximation Register SAR The SAR accumulates the result of each conversion one bit at a time starting with the most significant bit At the start of the resolution period the MSB of the SAR is set and all less significant bits are cleared Depending on the result of the first comparison the MSB is either left set or cleared Each successive bit is set or left cleared in descend ing order until all eight or ten bits have been resolved When conversion is complete the content of the SAR is transferred to the appropriate result register where it can be read by software The SAR itself is not accessib
20. aim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA and registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer MOTOROLA INC 1996 TABLE OF CONTENTS Paragraph Title Page SECTION 1FUNCTIONAL OVERVIEW 1 1 Analog SUDSVSIGITI tit A iS 1 1 1 2 Digital Control Subsystem oooooccccccnccccocccococononancccnnnnnnnnnnnnncnnnnnnnnnnncnncnnnnnnnns 1 1 1 3 General Purpose VO cion a dedic 1 2 1 4 Module Configuration 5 5 natus qae ot fag atten ot end 1 2 1 5 O assem Eu a rus 1 3 1 6 Memory 1 3 SECTION 2 SIGNAL DESCRIPTIONS 2 1 Analog Digital Input Pins AN 7 0 PADA 7 0 2 1 2 2 Digital Output Pins PADB 7 0 ropes 2 1 2 3 Analog Reference PINS ebd ae Meee eet txt a eevee RE ROMS 2 1 2 4 Analog Supply PINS sierra sica A EE 2 2 SECTION 3CONFIGURATION AND CONTROL 3 1 ADG Busintertace Unitarios oo 3 1 3 2 Module Configuration ba 3 1 3 2 1 Low Power Stop Operation 3 1 3 2 2 Freeze Mode Operation 3 2 3 2 3 Privilege Levels seed cnet o denen cet ee eles Sa 3 2 3 2 4 ADC Module Configuration
21. ample Buffer Amplifier Each of the eight external input channels is associated with a sample capacitor and share a single sample buffer amplifier After a conversion is initiated the multiplexer output is connected to the sample capacitor at the input of the sample buffer amplifier for the first two ADC clock cycles of the sampling period The sample amplifier buffers the input channel from the relatively large capacitance of the RC DAC array The input channel sees only the small sample capacitors during this period During the second two ADC clock cycles of the sampling period the sample capacitor is disconnected from the multiplexer and the stored level in the sample capacitor is transferred to the RC DAC array via the sample buffer amplifier During the third part of the sampling period the sample capacitor and amplifier are by passed and the multiplexer input charges the RC DAC array directly Charging the RC DAC array directly once the stored voltage level approaches the input voltage allows the ADC to achieve a high degree of accuracy Moreover since the voltage on the RC DAC array is nearly equal to the external voltage by the start of this third period this RC DAC voltage presents very little loading to the external circuitry This results in higher allowable input impedance and virtually no charge sharing between channels The length of this third period is determined by the value in the STS field of ADCTLO Refer to 5 1 Conversion
22. ation FRZ 1 0 Freeze The FRZ field determines ADC response to assertion of the FREEZE signal by the CPU 00 Ignore FREEZE 01 Reserved 10 Finish conversion then freeze 11 Freeze immediately SUPV Supervisor Unrestricted 0 Unrestricted access to registers controlled by the SUPV bit 1 Supervisor access only PDR Port Data Register XXXX06 15 8 7 0 Port ADB Output Data Port ADA Input Data RESET 0 0 0 0 0 0 0 0 State of input pins ADCTLO ADC Control Register 0 XXXX0A 15 8 7 6 5 4 3 2 1 0 NOT USED RES10 STS PRS RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RES10 10 Bit Resolution 0 8 bit conversion 1 10 bit conversion STS 1 0 Sample Time Select Field The STS field selects the initial sample time 00 2 A D clock periods 01 4 A D clock periods 10 8 A D clock periods 11 16 A D clock periods Refer to 5 1 Conversion Timing and 5 3 Final Sample Time for additional informa tion MOTOROLA MEMORY MAP AND REGISTERS ADC B 2 REFERENCE MANUAL PRS 4 0 Prescaler Rate Selection Field 00000 System Clock 4 00001 System Clock 4 00010 System Clock 6 00011 System Clock 8 11101 System Clock 60 11110 System Clock 62 11111 System Clock 64 The system clock is divided by the PRS value plus one then divided by two to deter mine the ADC clock Assigning a value of zero to this field however has the same effect as assigning a value of one
23. being converted CCF 7 0 Conversion Complete Each bit in this field corresponds to an A D result register CCF7 corresponds to RSLT7 etc A bit is set when conversion of the corresponding input is complete and is cleared when the result register containing the converted value is read RSLTO RSLT7 Result Registers Right Justified XXXX10 XXXX1F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not Used 10 bit Result 8 10 bit Result The conversion result is unsigned right justified data Bits 9 0 are used for 10 bit res olution bits 7 0 are used for 8 bit conversion bits 9 8 are zero Bits 15 10 always return zero when read RSLTO RSLT7 Result Registers Signed Left Justified XXXX20 XXXX2F 15 14 13 12 11 10 9 8 TA 6 5 4 3 2 1 0 8 10 bit Result 10 bit Result Not Used The conversion result is signed left justified data Bits 15 6 are used for 10 bit reso lution bits 15 8 are used for 8 bit conversion bits 7 6 are zero Although the ADC is a unipolar converter this data format is provided by assuming that the zero refer ence point is Vay Vni 2 A read of bit 15 returns the inverse of the stored value and indicates the sign of the result The value read from this register is thus an offset binary twos complement number Bits 5 0 return zero when read RSLTO RSLT7 Result Registers Unsigned Left Justified XXXX30 XXXX3F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 10
24. erred to as PADA 7 0 When used for digital input each of these pins is conditioned by a synchronizer with an enable feature The synchronizer is not enabled until the actual IMB bus cycle addressing the PDR begins This minimizes the high current effect of mid level signals on the inputs This is particularly important when some of the inputs are being used as digital inputs and some as analog inputs Refer to 3 3 General Purpose I O for more information on port ADA 2 2 Digital Output Pins PADB 7 0 The eight digital output pins PADB 7 0 make up port ADB an output only port Data for port ADB is latched in the upper half of the PDR On some MCUS these pins are left unconnected and port ADB is not implemented A read of the upper byte of the port data register returns the digital value in the output register of port ADB Refer to 3 3 General Purpose I O for more information on this output port 2 3 Analog Reference Pins Separate high VRH and low VRL analog reference voltages are connected to the analog reference pins Because they are separated from the analog power supply pins VppA and Vssa the reference pins can be connected to regulated and filtered sup plies that allow the ADC to achieve its highest degree of accuracy Refer to SECTION 6 PIN CONNECTION CONSIDERATIONS for recommendations on filtering and con ditioning the analog reference inputs ADC SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL 2 1 The required refere
25. erved RSLT3 0 1 1 X X VRH RSLTO VRL RSLT1 VAL 2 RSLT2 Test Reserved RSLT3 1 0 X X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 AN3 RSLT3 AN4 RSLT4 AN5 RSLT5 ANG RSLT6 AN7 RSLT7 1 1 X X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 VRH RSLT4 VRL RSLT5 VRH VR 2 RSLT6 Test Reserved RSLT7 5 7 Control and Status Registers There are two control registers and one status register Writes to ADCTL1 initiate a conversion If a conversion sequence is already in progress a write to either control register aborts it and resets the SCF and CCF flags in ADSTAT 5 7 1 ADC Control Register 0 ADCTLO ADCTLO is used to select the conversion resolution 8 or 10 bits the sample time and the clock prescaler value Writing to this register aborts any conversion in progress and ADC activity halts until a write to ADCTL1 occurs ADC DIGITAL CONTROL SUBSYSTEM MOTOROLA REFERENCE MANUAL 5 7 ADCTLO ADC Control Register 0 XXXX0A 15 8 7 6 5 4 3 2 1 0 NOT USED RES10 STS PRS RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RES10 10 Bit Resolution 0 8 bit conversion 1 10 bit conversion STS 1 0 Sample Time Select 00 2 A D Clock Periods 01 4 A D Clock Periods 10 8 A D Clock Periods 11 16 A D Clock Periods The STS field selects the final sample time after the buffered sample transfer has oc curred Referto 5 1 Conversion Timing and 5 3 Final Sample Time for
26. ffect of different levels of total leak age on accuracy for different values of source impedance The error is listed in terms of 10 bit counts Notice that leakage from the part of 10 nA is obtainable only within a limited temperature range Table 6 2 Error Resulting from Input Leakage loFF Source Leakage Value 10 bit Conversions Impedance 10nA 50 nA 100 nA 1000 nA 1kQ 0 2 counts 10kQ 0 1 counts 0 2 counts 2 counts 100kQ 0 2 counts 1 count 2 counts 20 counts ADC PIN CONNECTION CONSIDERATIONS MOTOROLA REFERENCE MANUAL 6 5 MOTOROLA PIN CONNECTION CONSIDERATIONS ADC 6 6 REFERENCE MANUAL APPENDIX A ELECTRICAL CHARACTERISTICS The following ratings define the conditions under which the ADC can operate without damage Table A 1 Maximum Ratings Num Parameter Symbol Min Max Unit 1 Analog Supply VDDA 0 3 6 5 V 2 Internal Digital Supply Vppi 0 3 6 5 V 3 Reference Supply VAL 0 3 6 5 V 4 Vgg Differential Voltage Vss Vssa 0 1 0 1 V 5 Vpp Differential Voltage Vppi VppA 6 5 6 5 V 6 Vngr Differential Voltage Vnu VRL 6 5 6 5 V 7 VREF to VDDA Differential Voltage VRH VDDA 6 5 6 5 8 Disruptive Input Current INA 15 15 uA NOTES 1 Below disruptive current conditions the channel being stressed will have conversion values of 3FF for analog inputs greater than Vay 000 for values less than Vg This assumes tha
27. g signal to be measured Refer to 6 3 2 Error Resulting from Leakage In some cases the size of the capac itor at the pin may be very small Figure 6 3 is a simplified model of an input channel Refer to this model in the follow ing discussion of the interaction between the user s external circuitry and the circuitry inside the ADC EXTERNAL CIRCUIT INTERNAL CIRCUIT MODEL 51 52 53 54 oo o O O oro Y 64 VSRC VSRC Source voltage RF Filter impedance source impedance included CF Filter capacitor Cg Internal capacitance for a bypassed channel this is the CDAC capacitance CDAC DAC capacitor array V Internal voltage source for precharge VD 2 Figure 6 3 Electrical Model of an A D Input Pin In Figure 6 3 Rp and Cr comprise the user s external filter circuit Cs is the internal sample capacitor The value for this capacitor is 2 pF Each channel has its own ca pacitor The 2 pF capacitor is never precharged it retains the value of the last sample V is an internal voltage source used to precharge the DAC capacitor array CpAc be fore each sample The value of this supply is Vpp 2 or 2 5 volts for 5 volt operation The following paragraphs provide a simplified description of the interaction between the ADC and the user s external circuitry This circuitry is assumed to be a simple RC low pass filter passing a signal from a source to the ADC input pin The following sim plifying assum
28. igned Left Justified Format XXXX30 XXXX3F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 10 Bit Result 10 Bit Result Not Used The conversion result is unsigned left justified data Bits 15 6 are used for 10 bit res olution bits 15 8 are used for 8 bit resolution bits 7 6 are zero Bits 5 0 always return zero when read MOTOROLA DIGITAL CONTROL SUBSYSTEM ADC 5 10 REFERENCE MANUAL 6 1 6 2 ADC SECTION 6 PIN CONNECTION CONSIDERATIONS The ADC requires accurate noise free input signals for proper operation This section discusses the design of external circuitry to maximize ADC performance Analog Reference Pins No A D converter can be more accurate than its analog reference Any noise in the reference can result in at least that much error in a conversion The reference for the ADC supplied by pins VRH and VrL should be low pass filtered from its source to ob tain a noise free clean signal In many cases simple capacitive bypassing may suf fice In extreme cases inductors or ferrite beads may be necessary if noise or RF energy is present Series resistance is not advisable since there is an effective DC cur rent requirement from the reference voltage by the internal resistor string in the RC DAC array External resistance may introduce error in this architecture under certain conditions Any series devices in the filter network should contain a minimum amount of DC resistance For accurate conversion res
29. ing the ADC is not affecting the charging Table 6 1 External Circuit Settling Time 10 Bit Conversions Filter Source Resistance Capacitor 1 uF 1 uF 01 uF 001 uF 100 pF The external circuit described in Table 6 1 is a low pass filter A user interested in measuring an AC component of the external signal must take the characteristics of this filter into account 6 3 2 Error Resulting from Leakage A series resistor can limit the current to a pin but input leakage acting through a large source impedance can degrade A D accuracy The maximum input leakage current is specified in APPENDIX A ELECTRICAL CHARACTERISTICS Input leakage is greatest at high operating temperatures and as a general rule decreased by one half for each 10 C decrease in temperature When Vp Vni 5 12 V 1 count assuming 10 bit resolution corresponds to 5 mV of input voltage A typical input leakage of 50 nA acting through 100 kQ of external se MOTOROLA PIN CONNECTION CONSIDERATIONS ADC 6 4 REFERENCE MANUAL ries resistance results in an error of less than 1 count 5 0 mV If the source imped ance is 1 MQ and a typical leakage of 50 nA is present an error of 10 counts 50 mV is introduced In addition to internal junction leakage external leakage e g if external clamping di odes are used and charge sharing effects with internal capacitors also contribute to the total leakage current Table 6 2 illustrates the e
30. le to user software MOTOROLA ANALOG SUBSYSTEM ADC 4 2 REFERENCE MANUAL SECTION 5 DIGITAL CONTROL SUBSYSTEM The digital control subsystem includes control and status registers clock and prescal er control logic channel and reference select logic conversion sequence control logic and eight result registers The successive approximation register which holds each conversion result before it is transferred to the appropriate result register is discussed in SECTION 4 ANALOG SUBSYSTEM ADCTLO and ADCTL1 ADC control registers 0 and 1 and associated logic select the conversion resolution 8 or 10 bits input channel conversion mode sample time and ADC clock cycle ADSTAT the ADC status register contains flags indicating the com pletion of A D conversions Writing to ADCTL1 initiates a conversion Conversion results are stored one bit at a time in the SAR Results are discrete val ues between 0 and 255 28 1 for 8 bit conversions and between 0 and 1023 210 1 for 10 bit conversions One binary unit VRH VRL 2 where n 8 or 10 Each converted result is transferred from the SAR to bits 7 0 for 8 bit conversion or 9 0 for 10 bit conversion of the appropriate result register Each result is available in three formats right justified unsigned left justified signed and left justified unsigned depending on the address from which it is read The following subsections discuss control functions involving
31. lock Data format de pends on the address from which it is read The result registers reside on the internal differential data bus ADC DIGITAL CONTROL SUBSYSTEM MOTOROLA REFERENCE MANUAL 5 9 Unsigned Right Justified Format XXXX10 XXXX1F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not Used 10 Bit Result 8 10 Bit Result The conversion result is unsigned right justified data Bits 9 0 are used for 10 bit res olution bits 7 0 are used for 8 bit resolution bits 9 8 are zero Bits 15 10 always return zero when read Signed Left Justified Format XXXX20 XXXX2F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 10 Bit Result 10 Bit Result Not Used The conversion result is signed left justified data Bits 15 6 are used for 10 bit reso lution bits 15 8 are used for 8 bit resolution bits 7 6 are zero Although the ADC is a unipolar converter this data format is provided by assuming that the zero reference point is VRH VRL 2 When the register is read bit 15 re turns zero for a positive number and one for a negative number For a negative num ber the value read is in twos complement form Bits 5 0 return zeros when read For eight bit conversions the table below summarizes the results of a read of the upper byte of this register Input Voltage Digital Result Full scale VRH 7F Bipolar zero VRH VRH 2 00 Zero 1 count FF Full scale VRL 80 Uns
32. lso manages data bus routing to ac commodate the three conversion data formats and controls the interface to the ADC internal bus ADC registers are updated immediately when written to However if a conversion is in progress when a control bit is written conversion halts and must be restarted before the new control parameter can take effect Communication between the IMB and the ADC is interleaved with internal ADC com munication ADC register accesses by the host system require bus cycles of three MCU clocks so that each bus cycle contains six clock edges Internal I O SAR to re sult registers and I O from the IMB occur during pre assigned non conflicting times This ensures that the ADC can access the SAR and result registers at all times 3 2 Module Configuration The ADCMCR contains bits that control the interaction of the ADC module with other MCU modules These bits place the ADC in low power or normal operation determine the reaction of the ADC module to assertion of the CPU FREEZE command and de termine the privilege level required to access most ADC registers 3 2 1 Low Power Stop Operation When the STOP bit in the ADCMCR is set the IMB clock signal internal to the ADC is disabled This places the module in an idle state and minimizes power consumption The bus interface unit does not shut down and ADC registers are still accessible Any conversion in progress when STOP is set is aborted Software can write to the ADCMCR t
33. nce voltage levels are provided in APPENDIX A ELECTRICAL CHARACTERISTICS 2 4 Analog Supply Pins Pins Vppa and Vssa supply power to the analog circuitry associated with the sample amplifier and RC DAC array Other circuitry in the ADC is powered from the digital power bus pins and Vss Dedicated power for the RC DAC array is necessary to isolate sensitive analog circuitry from noise on the digital power bus Refer to AP PENDIX A ELECTRICAL CHARACTERISTICS for precise electrical specifications MOTOROLA SIGNAL DESCRIPTIONS ADC 2 2 REFERENCE MANUAL SECTION 3CONFIGURATION AND CONTROL Other microcontroller modules communicate with the ADC module via the intermodule bus IMB The ADC bus interface unit ABIU coordinates IMB activity with internal ADC bus activity The first part of this section explains the operation of the ABIU The second part of this section describes the ADC module configuration register ADCM CR which contains bits used to configure the ADC module The final parts of this sec tion discuss the general purpose I O functions of the ADC module and provide a checklist for initializing the ADC 3 1 ADC Bus Interface Unit The ABIU is designed to act as a slave device on the IMB The IMB handles commu nication between the ADC and other microcontroller modules and supplies timing sig nals to the ADC The ABIU provides IMB bus cycle termination and synchronizes internal ADC signals with IMB signals The ABIU a
34. nnel Selection The bits in this field are used to select an input or block of inputs for A D conversion Table 5 5 and Table 5 6 explain the operation of these fields 5 7 3 ADC Status Register ADSTAT ADSTAT is a read only register that contains the sequence complete flag SCF con version counter CCTR and one channel converted flag CCF for each of the eight channels ADSTAT ADC Status Register XXXXOE 15 14 11 10 8 7 0 SCF NOT USED CCTR CCF RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCF Sequence Complete Flag This bit is set at the end of the conversion sequence when SCAN 0 in ADCTL1 and set at the end of the first conversion sequence when SCAN 1 0 Sequence not complete 1 Sequence complete CCTR 2 0 Conversion Counter This field shows the content of the conversion counter pointer during a conversion se quence The value is the number of the next result register to be written to i e the channel currently being converted CCF 7 0 Conversion Complete Flags Each bit in this field corresponds to an A D result register CCF7 corresponds to RSLT7 etc A bit is set when conversion of the corresponding input is complete and is cleared when the result register containing the converted value is read 5 8 Result Registers RSLTO RSLT7 The eight read only result registers store data after conversion is complete Each reg ister can be read from three different addresses in the register b
35. nuous conversions MULT Conversion can be run on a single channel or on a block of four or Multichannel conversions eight channels depending on S8CM 0 Single channel 1 Multiple channels S8CM Length of a conversion sequence Select 8 conversion 0 4 conversions sequence mode 1 8 conversions The combination of these bits determines the conversion mode as shown in Table 5 4 and explained in the following paragraphs Conversion begins with the multiplexer input specified by the value in the CD CA field of ADCTL1 Table 5 4 ADC Conversion Modes SCAN MULT S8CM 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 MOTOROLA DIGITAL CONTROL SUBSYSTEM ADC 5 4 REFERENCE MANUAL Mode 0 A single 4 conversion sequence is performed on a single input channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the conversion sequence is com plete Mode 1 A single 8 conversion sequence is performed on a single input channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the conversion sequence is com plete Mode 2 A single conversion is performed on each of fo
36. o obtain full scale full range results VssA lt VnL lt ViNDC lt VRH lt VDDA 3 Current measured at maximum system clock frequency with all modules active 4 Maximum leakage occurs at maximum operating temperature As a general rule current decreases by half for each 10 C below maximum temperature 0 2 Table A 3 ADC AC Characteristics Operating VDD and VDDA 5 0 Vdc 10 VSS 0 Vdc TA within operating temperature range Parameter IMB Clock Frequency ADC Clock Frequency 8 bit Conversion Time 16 ADC Clocks 10 bit Conversion Time 18 ADC Clocks Stop Recovery Time NOTES 1 Assumes 2 1 MHz ADC clock and selection of minimum sample time 2 ADC clocks MOTOROLA ELECTRICAL CHARACTERISTICS ADC A 2 REFERENCE MANUAL Table A 4 Analog Converter Characteristics Operating VDD and VDDA 5 0 Vdc 10 VSS 0 Vde TA TL to TH ADCLK 2 1 MHz Parameter Symbol i Unit 2 3 1 8 bit Resolution 1 Count mV 2 8 bit Differential Nonlinearity DNL Counts 3 8 bit Integral Nonlinearity INL Counts 4 8 bit Absolute Error AE Counts 5 10 bit Resolution 1 Count mV 6 10 bit Differential Nonlinearity Counts 7 10 bit Integral Nonlinearity Counts 8 10 bit Absolute Error 2 5 Counts 9 Source Impedance at Input See Note 5 NOTES 1 Vay Vr 5 12 V Vopa Vssa 5 12 V 2 At Vaer 5 1
37. o set the STOP bit In addition system reset ei ther internally or externally generated sets this bit Following either of these condi tions the STOP bit must be cleared before the ADC can be used Because analog circuit bias currents are turned off when STOP is set the ADC requires recovery time after the STOP bit is cleared ADC CONFIGURATION AND CONTROL MOTOROLA REFERENCE MANUAL 3 1 Execution of the CPU LPSTOP command can place the entire modular microcontrol ler including the ADC in low power stop mode by turning off the system clock This command does not set the STOP bit in the ADCMCR Before issuing the LPSTOP command the user should assert the STOP bit in the ADCMCR so that the module stops in a known state 3 2 2 Freeze Mode Operation When the CPU enters background debugging mode the FREEZE signal is asserted The ADC can respond to internal assertion of FREEZE in three ways it can ignore FREEZE assertion finish the current conversion and then freeze or freeze immedi ately The type of response is determined by the value of the FRZ 1 0 field in the AD CMCR see Table 3 1 Table 3 1 FRZ Field Selection FRZ Response 00 Ignore FREEZE 01 Reserved 10 Finish conversion then freeze 11 Freeze immediately When the ADC freezes the ADC clock stops and all sequential activity ceases Con tents of control and status registers remain valid while frozen When the FREEZE sig nal is negated ADC activity
38. on MOUGS gn ED e e deco exu ic 5 4 5 5 Single Channel Conversions mmm nenea anna 5 6 5 6 Multiple Channel Conversions mmmmnnee nenea eene nennen nnne nnne 5 7 6 1 External Circuit Settling Time 10 Bit 6 4 6 2 Error Resulting from Input Leakage 6 5 AFT Maximum I M TM A 1 2 ADC DC Electrical Characteristics A 2 ADC AC Characteristics A 2 A 4 Analog Converter Characteristics A 3 ADC MOTOROLA REFERENCE MANUAL vii LIST OF TABLES Continued Table Title Page MOTOROLA ADC viii REFERENCE MANUAL SECTION 1FUNCTIONAL OVERVIEW The analog to digital converter ADC a module in Motorola s family of modular micro controllers is a unipolar successive approximation converter with eight modes of op eration and selectable 8 or 10 bit resolution Monotonicity is guaranteed for both 8 and 10 bit conversions With a 16 78 MHz system clock the ADC can perform an 8 bit single conversion in 8 microseconds or a 10 bit single conversion in 9 microsec onds The ADC contains an analog and a digital subsystem Figure 1 1 is a functional block diagram of the ADC module
39. on modes and the ADC control and status registers MOTOROLA CONFIGURATION AND CONTROL ADC 3 4 REFERENCE MANUAL SECTION 4 ANALOG SUBSYSTEM This section describes the operation of the analog subsystem Understanding this sub system is helpful in designing ADC applications and in using the digital control func tions that regulate A D conversion Refer to SECTION 6 PIN CONNECTION CONSIDERATIONS for ADC design considerations and SECTION 5 DIGITAL CON TROL SUBSYSTEM for details concerning digital control functions The analog subsystem consists of a multiplexer sample capacitors a buffer amplifier an RC DAC array and a high gain comparator Comparator output is used to se quence the successive approximation register SAR Since the SAR like the rest of the analog subsystem is not directly accessible to user software its description is in cluded in this section 4 1 Multiplexer The multiplexer selects one of eight external or eight internal sources for conversion The eight internal sources include VRH VRL VRH VRL 2 and five reserved chan nels Multiplexer operation is controlled by channel selection field CD CA in ADCTL1 Refer to 5 6 Channel Selection for details on selecting a conversion channel The multiplexer contains positive clamping and negative stress protection circuitry This circuitry prevents voltages within certain limits on other input channels from af fecting the current conversion 4 2 S
40. on the input pin is not within and Vj specification i e if the signal is in the dead band region a read of the PDR returns an undetermined value Port ADB an output only port uses pins PADB 7 0 Data for Port ADB is latched in the upper half of the PDR On some MCUS port ADB is not implemented On these MCUS reads of the upper half of the PDR return whatever value was last written to the upper half of the register ADC CONFIGURATION AND CONTROL MOTOROLA REFERENCE MANUAL 3 3 PDR Port Data Register XXXX02 15 8 7 0 Port ADB Output Data Port ADA Input Data RESET 0 0 0 0 0 0 0 0 State of input pins 3 4 ADC Test Register ADCTEST ADCTEST ADC Test Register XXXX06 ADCTEST is used only during factory testing of the MCU 3 5 Initialization Checklist To initialize the ADC submodule and begin a conversion sequence follow these steps 1 Write to the ADCMCR to ensure the STOP and FREEZE bits are cleared and assign the desired value to the SUPV bit 2 Write to ADCTLO to select the sample time ADC clock prescaler and 8 or 10 bit resolution 3 Write to ADCTL1 to select the conversion mode SCAN MULT and S8CM bits and conversion channel or channels CD CA and to begin a conversion se quence Once a conversion sequence has begun the type of conversion mode selected deter mines the programming sequence Refer to SECTION 5 DIGITAL CONTROL SUB SYSTEM for additional information on conversi
41. onversions are performed on each of four sequential input channels starting with the channel specified by the value in CD CC Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the first 4 conversion sequence is complete Mode 7 Continuous conversions are performed on each of eight sequential input channels starting with the channel specified by the value in CD Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the first 8 conversion sequence is complete DIGITAL CONTROL SUBSYSTEM MOTOROLA REFERENCE MANUAL 5 5 5 6 Channel Selection The value of the channel selection field CD CA in ADCTL1 determines which multi plexer input or inputs are used in a conversion sequence There are 16 possible in puts Eight inputs are external pins AN 7 0 and eight are internal Table 5 5 summarizes ADC operation when MULT is cleared single channel modes Table 5 6 summarizes ADC operation when MULT is set multichannel modes The SCAN bit determines whether single or continuous conversion sequences are per formed Channel numbers are given in order of conversion Table 5 5 Single Channel Conversions
42. ptions are made ADC PIN CONNECTION CONSIDERATIONS MOTOROLA REFERENCE MANUAL 6 3 The source impedance is included with the series resistor of the RC filter The external capacitor is perfect no leakage no significant dielectric absorption characteristics etc All parasitic capacitance associated with the input pin is included in the value of the external capacitor Inductance is ignored The or resistance of the internal switches is zero ohms and the off resistance is infinite 6 3 1 Settling Time for the External Circuit The values for RF and Cr in the user s external circuitry determine the length of time required to charge Cr to the source voltage level Vsrc At time t 0 51 in Figure 6 3 closes S2 is open disconnecting the internal circuitry from the external circuitry Assume that the initial voltage across Cr is 0 As Cr charges the voltage across it is determined by the following equation where t is the total charge time Vcr Vsnc 1 e VRFCF When t 0 the voltage across Cr 0 As t approaches infinity Vcr will equal Vsnc This assumes no internal leakage With 10 bit resolution 1 2 of a count is equal to 1 2048 full scale value Assuming worst case Vsnc full scale Table 6 1 shows the required time for Cr to charge to within 1 2 of a count of the actual source voltage dur ing 10 bit conversions Note that these times are completely independent of the A D converter architecture assum
43. rocontroller modules MOTOROLA FUNCTIONAL OVERVIEW ADC 1 2 REFERENCE MANUAL or by external sources The ADCMCR also determines the privilege level at which most ADC registers operate Refer to 3 2 Module Configuration for additional infor mation 1 5 Bus Organization The ADC bus interface unit ABIU serves as an interface between the ADC and the intermodule bus IMB The IMB handles communication between the ADC and other microcontroller modules and supplies timing signals to the ADC For additional infor mation on the ABIU refer to 3 1 ADC Bus Interface Unit 1 6 Memory Map The ADC module is mapped into 32 words of address space see Table 1 1 Five words are control and status registers one word is digital port data and 24 words pro vide access to the results of A D conversion eight addresses for each type of convert ed data Two words are reserved for expansion The addresses provided in Table 1 1 and elsewhere in this manual are offsets from the ADC base address For the pre cise locations of these registers consult the user s manual for the specific microcon troller unit MCU The column labeled Access in Table 1 1 specifies which registers are supervisor only and which can be programmed to operate at either access level ADC FUNCTIONAL OVERVIEW MOTOROLA REFERENCE MANUAL 1 3 Table 1 1 ADC Module Memory Map Address
44. t Register 1 RSLT1 XXXX14 S U ADC Result Register 2 RSLT2 XXXX16 S U ADC Result Register 3 RSLT3 XXXX18 S U ADC Result Register 4 RSLT4 XXXX1A S U ADC Result Register 5 RSLT5 XXXX1C S U ADC Result Register 6 RSLT6 XXXX1E S U ADC Result Register 7 RSLT7 Address Access Left Justified Signed Result Registers XXXX20 S U ADC Result Register 0 RSLTO XXXX22 S U ADC Result Register 1 RSLT1 XXXX24 S U ADC Result Register 2 RSLT2 XXXX26 S U ADC Result Register 3 RSLT3 XXXX28 S U ADC Result Register 4 RSLT4 XXXX2A S U ADC Result Register 5 RSLT5 XXXX2C S U ADC Result Register 6 RSLT6 XXXX2E S U ADC Result Register 7 RSLT7 Address Access Left Justified Unsigned Result Registers XXXX30 S U ADC Result Register 0 RSLTO XXXX32 S U ADC Result Register 1 RSLT1 XXXX34 S U ADC Result Register 2 RSLT2 XXXX36 S U ADC Result Register 3 RSLT3 XXXX38 S U ADC Result Register 4 RSLT4 XXXX3A S U ADC Result Register 5 RSLT5 XXXX3C S U ADC Result Register 6 RSLT6 XXXX3E S U ADC Result Register 7 RSLT7 S Supervisor accessible only S U Supervisor or user accessible depending on state of the SUPV bit in the ADCMCR ADC MEMORY MAP AND REGISTERS MOTOROLA REFERENCE MANUAL B 1 B 2 Registers ADCMCR ADC Module Configuration Register XXXX00 15 14 13 12 8 7 6 0 STOP FRZ NOT USED SUPV NOT USED RESET 1 0 0 0 STOP STOP Mode 0 Normal operation 1 Low power oper
45. t Vay VppA and Va gt Vssa due to the presence of the sample amplifier Other channels are not affected by non disruptive conditions 2 Input signals with large slew rates or high frequency noise components cannot be converted accu rately These signals also interfere with conversion of other channels ADC ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 1 2 3 Table A 2 ADC DC Electrical Characteristics Operating VSS 0 Vdc ADCLK 2 1 MHz TA within operating temperature range Parameter Symbol Analog Supply VDDA Internal Digital Supply Vppi Vss Differential Voltage Vssi VssA Vpp Differential Voltage Vppi VDDA Reference Voltage Low Reference Voltage High VRL Vopa 2 VDDA Vrer Differential Voltage 4 5 5 5 Ni By CO N Input Voltage Vssa VDDA Input High Digital Port 0 7 VppA VDDA 4 0 3 Input Low Digital Port 0 2 VppA lt lt lt lt lt lt lt lt CMOS Output High Digital Port loH 10 0 uA Output Low Digital Port 0 2 loL 10 0 uA Output High Digital Port lou 0 8 Output Low Digital Port lot 1 6 Analog Supply Current Reference Supply Current Input Current Off Channel Total Input Capacitance Not Sampling Total Input Capacitance Sampling NOTES 1 Refers to operation over full temperature and frequency range 2 T
46. t the supervisor level so that ADC registers are always accessible 3 2 4 ADC Module Configuration Register ADCMCR The ADCMCR contains fields and bits that control freeze and stop modes and deter mine the privilege level required to access most ADC registers ADCMCR ADC Module Configuration Register XXXX00 15 14 18 12 8 7 6 0 STOP FRZ NOT USED SUPV NOT USED RESET 1 0 0 0 STOP STOP Mode 0 Normal operation 1 Low power operation FRZ 1 0 Freeze The FRZ field determines ADC response to assertion of the FREEZE signal by the CPU 00 Ignore FREEZE 01 Reserved 10 Finish conversion then freeze 11 Freeze immediately SUPV Supervisor User 0 User access permitted to registers controlled by the SUPV bit 1 Supervisor access only permitted to ADC registers 3 3 General Purpose I O Two digital ports are associated with the ADC These ports are accessed through the 16 bit port data register PDR Port ADA an input only port uses the eight analog in put pins Certain MCUs may provide fewer than eight analog input pins Refer to the appropriate MCU user s manual for details Data for port ADA is accessed in the lower half of the PDR The digital level of an input port pin may be read at any time A read of the PDR does not affect an A D conversion in progress Use of any port A pin for digital input does not preclude the use of any other port A pin for analog input If the signal
47. time is 15 us for an 8 bit conversion or 16 us for a 10 bit conversion with a 2 1 MHz ADC clock ADC DIGITAL CONTROL SUBSYSTEM MOTOROLA REFERENCE MANUAL 5 1 Figure 5 1 and Figure 5 2 illustrate the timing for 8 and 10 bit conversions respec tively These diagrams assume a final sampling period of two ADC clocks INITIAL FINAL RESULT REGISTER AND SET CCF SAMPLE TRANSFER SAMPLE lt gt lt TIME TIME TIME gt lt RESOLUTION TIME gt 1 16 2 1 1 1 1 1 1 1 1 6 CYCLES CYCLES CYCLE CYCLEICYCLE CYCLE CYCLE CYCLE CYCLE CYCLE SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SARI SARO EOC SAMPLE AND TRANSFER gt lt SUCCESSIVE APPROXIMATION gt gt END PERIOD SEQUENCE CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 SCF FLAG SET HERE AND SEQUENCE SCF FLAG SET HERE AND SEQUENCE PAING IC INI TIIS MAN mainam m me AIA MAn Figure 5 1 8 Bit Conversion Timing TRANSFER CONVERSION TO INITIAL FINAL RESULT REGISTER AND SET CCF SAMPLE TRANSFER SAMPLE lt gt r TIME TIME TIME gt gt lt RESOLUTION TIME gt 16 1 2 1 1 1 1 1 1 1 1 1 1 6 CYCLES CYCLES CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SARI SARO EOC lt lt lt SAMPLE AND TRANSFER gt lt SUCCESSIVE APPROXIMATION gt END PERIOD SEQUENCE CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 SCF FLAG SET HE
48. ults the analog reference voltages must be within the lim its defined by VppA and Vssa as explained in the following subsection Analog Power Pins The analog supply pins VppA Vssa define the limits of the analog reference volt ages and VrL and of the analog multiplexer inputs Figure 6 1 is a diagram of the analog input circuitry VDDA VRH lt SAMPLE AMP COMPARATOR 8 CHANNELS TOTAL lt Q REF1 VSSA VRL REF2 Figure 6 1 Analog Input Circuitry PIN CONNECTION CONSIDERATIONS MOTOROLA REFERENCE MANUAL 6 1 Since the sample amplifier is powered by Vppa and Vssa it can accurately transfer input signal levels up to but not exceeding VppA and down to but not below Vssa If the input signal is outside of this range the output from the sample amplifier is clipped In addition VRH and Vn must be within the range defined by VppA and Vssa As long as is less than or equal to VppA and is greater than or equal to VssA and the sample amplifier has accurately transferred the input signal resolution is rati ometric within the limits defined by Va and VRu If VRH is greater than Vppa the sample amplifier can never transfer a full scale value If is less than Vssa the sample amplifier can never transfer a zero value Figure 6 2 shows the results of reference voltages outside the range defined by VppA and Vesa At the top of the input signal range VppA is 10 mV lower than
49. ur sequential input chan nels starting with the channel specified by the value in CD CC Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the last conversion is complete Mode 3 A single conversion is performed on each of eight sequential input chan nels starting with the channel specified by the value in CD Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in AD STAT is set as each register is filled The SCF bit in ADSTAT is set when the last conversion is complete Mode 4 Continuous 4 conversion sequences are performed on a single input channel specified by the value in CD CA Each result is stored in a separate re sult register RSLTO to RSLT3 Previous results are overwritten when a se quence repeats The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the first 4 conversion sequence is complete Mode 5 Continuous 8 conversion sequences are performed on a single input channel specified by the value in CD CA Each result is stored in a separate re sult register RSLTO to RSLT7 Previous results are overwritten when a se quence repeats The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the first 8 conversion sequence is complete Mode 6 Continuous c
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