Can microcontroller that utilizes a dedicated RAM memory space to
Contents
1. Acceptance Filtering In general because the XA C3 microcontroller 20 pro vides the user with the ability to program separate Match ID and Mask fields for each of the 32 independent Message Objects on an object by object basis as described previously the Acceptance Filtering process performed by the XA C3 microcontroller 20 can be characterized as a match and mask technique The basic objective of this Acceptance Filtering process is to determine whether a Screener ID field of the received CAN Frame excluding the don t care bits masked by the Mask field for each Message Object matches the Match ID of any enabled one of the 32 Message Objects that has been designated a Receive Mes sage Object If there is a match between the received CAN Frame and more than one Message Object then the received CAN Frame will be deemed to have matched the Message Object with the lowest object number n 05 6 493 287 9 Acceptance Filtering is performed as follows by the XA C3 microcontroller 20 1 A Screener ID field is extracted from the incoming received CAN Frame In this regard the Screener ID field that is assembled from the incoming bit stream is different for Standard and Extended CAN Frames In particular as is illustrated in FIG 9 the Screener ID field for a Standard CAN Frame is 28 bits consisting of 11 CAN ID bits extracted from the header of the received CAN Frame 2x8 16 bits from the first and second data bytes Dat2. Address MMR Space Offset 512 Bytes Object Registers FIG 6 Offset FFFh U S Patent Dec 10 2002 Sheet 5 of 7 US 6 493 287 Segment in Data Memory Space xyFFFFh 203 16 15 Object nT Object n Message Buffer Buffer 14 1 MnBLR eS XRAM 512 Bytes 423 16 a15 28 a7 20 hens xy0000h FIG 7 Segment xy in Data Memory Space Ll 423 416 alo 4 14 4 7 0 MnBLR Object n Message Buffer RENE c Object n XRAM Buffer size 912 Bytes 223 416 215 28 7 a 4 lt MBXSRI7 0 XRAMBU 1 0 a xy0000h FIG 8 U S Patent Dec 10 2002 Sheet 6 of 7 US 6 493 287 Object n Match ID Field MnMIDH and MnMIDL Mid28 Mid18 Midi7 Mid10 Mid9 Mid2 Midi Mido MIDE Object n Mask Field MnMSKH and MnMSKL Msk28 Mski8 Mskt7 Msk10 Msk9 Msk2 Mski Screener ID Field assembled from incoming bit stream IDE Object n Match ID Field MnMIDH and MnMIDL Mid28 Midi8 Midi7 Mid10 Mid9 Mid2 Midi Midd MIDE Object n Mask Field MnMSKH and MnMSKL Msk28 Msk18 Msk17 Msk10 Msk9 Msk2 Screener ID Field assembled from incoming bit stream CAN 10 28 CAN ID 0 FG 10 U S Patent Dec 10 2002 Sheet 7 of 7 US 6 493 287 Framelnfo Data Byte 1 Data Byte 2 Data Byte DLC Frame
3. Message Object n for Remote Transmit Request RTR handling In CANopen and OSEK systems the user must also initialize the MnFCR register associated with each Message Object n As previously mentioned on set up the user must con figure program the global GCTL register whose bits control global parameters that apply to all Message Objects In particular the user can configure program the GCTL register in order to specify the high level CAL protocol if any being used e g DeviceNet CANopen or OSEK in order to enable or disable automatic acknowledgment of CANopen Frames CANopen auto acknowledge and in order to specify which of two transmit Tx pre arbitration schemes policies is to be utilized ie either Tx pre arbitration based on CAN ID with the object number being used as a secondary tie breaker or Tx pre arbitration based on object number only Receive Message Objects and the Receive Process During reception i e when an incoming CAN Frame is being received by the XA C3 microcontroller 20 the CAN CAL module 77 will store the incoming CAN Frame in a temporary 13 Byte buffer and determine whether a complete error free CAN frame has been successfully received If it is determined that a complete error free CAN Frame has been successfully received then the CAN CAL module 77 will initiate Acceptance Filtering in order to determine whether to accept and store that CAN Frame or to ignore discard that CAN Frame
4. every time an incoming CAN Frame is accepted Since the incoming CAN Frame must pass through the Acceptance Filter before it can be accepted only the bits that are masked out will change Therefore the criteria for match and mask Acceptance Filtering will not change as a result of the contents of the MnMIDH and MnMIDL registers being changed in response to an accepted incoming CAN Frame being transferred to the appropriate message buffer Fragmented Message Assembly For Message Objects that have been set up with automatic fragmented message handling enabled 1 with the FRAG bit in the MnCTL register for that Message Object set to 17 masking of the 11 29 bit CAN ID field is disallowed As such the CAN ID of the accepted CAN Frame is known unambiguously and is contained in the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match Therefore there is no need to write the CAN ID of the accepted CAN Frame into the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match As subsequent CAN Frames of a fragmented message are received the new data bytes are appended to the end of the previously received and stored data bytes This process continues until a complete multi frame message has been received and stored in the appropriate message buffer Under CAL protocols DeviceNet CANopen and OSEK if a Message Object is an enabled Receive Me
5. of the memory mapped registers is mapped to a respective storage location within 51 Int aeter trees 13 00 the dedicated RAM memory space In one embodiment the 62 US 0 365 244 idt ud i po dedicated RAM memory space encompasses a plurality of 58 Field of S h 365 230 08 240 separate RAM modules each RAM module being dedicated 58 Field o ps 5 344 709 250 214 700 1 711 202 19 4 respective one of the command control fields The d i 1 09 memory mapped registers corresponding to a respective one of the command control fields are located in respective designated addressable memory storage locations within the 56 References Cited separate RAM module dedicated to that command control U S PATENT DOCUMENTS field with a different addressable memory storage location UT SAU ZH udi Soin being designated for each respective one of the message 5627840 51 pedis Aa nor 2 objects In particular implementation all of the 5674507 A 10 1997 Banker et al Kane 424 401 memory mapped registers corresponding to a respective one 5 893 162 A 4 1999 Lau et al 711 153 Of the command control fields are located in a respective one 6 434 432 8 2002 Hao et al 370 312 Of the separate RAM modules dedicated to that command control field FOREIGN PATENT DOCUMENTS DE 4129412 3 1993 GO06F 13 38 20 Claims 7 Drawing Sheets 20 CEL I oes PEDIR GN j ere ADDRESS DA
6. M by hardware within the CAN microcontroller BRIEF DESCRIPTION OF THE DRAWINGS These and various other aspects features and advantages of the present invention will be readily understood with reference to the following detailed description of the inven tion read in conjunction with the accompanying drawings in which FIG 1 is a diagram illustrating the format of a Standard CAN Frame and the format of an Extended CAN Frame FIG 2 is a diagram illustrating the interleaving of CAN Data Frames of different unrelated messages FIG 3 is a high level functional block diagram of the XA C3 microcontroller FIG 4 is a table listing all of the Memory Mapped Registers MMRs provided by the XA C3 microcontroller FIG 5 is a diagram illustrating the mapping of the overall data memory space of the XA C3 microcontroller FIG 6 is a diagram illustrating the MMR space contained within the overall data memory space of the XA C3 micro controller FIG 7 is a diagram illustrating formation of the base address of the on chip XRAM of the XA C3 microcontroller with an object n message buffer mapped into off chip data memory FIG 8 is a diagram illustrating formation of the base address of the on chip of the XA C3 microcontroller with an object n message buffer mapped into the on chip XRAM FIG 9 is a diagram illustrating the Screener ID Field for a Standard CAN Frame FIG 10 is a diagram illustrating the Screener ID Field f
7. TA BUS PORTS 0 3 r53 TIMERO gt TIMER 1 je 54 2 e U S Patent Dec 10 2002 Sheet 1 of 7 US 6 493 287 STANDARD CAN ID CRC JACK JACK EOF iro Bus idle hi hy DB DE 08 64 i 1 bit 1 0 ol Mm 15 bi Pie Beca EXTENDED RemoteTransmitRequest SRR SubstituteRemoteRequest IDE ID Extension r1 r0 reserved bits 010 DataLengthCode 0 1 8 IFS InterFrameSpace CAN bus CAL Message B Aeg CAN CAL Message C Data Frame 8 Byte p Saa 886 8 Byte CAL Message D 8 Byt ene 922592985 ig CURES THEE ES FIG 2 U S Patent Dec 10 2002 Sheet 2 of 7 i 34 CORE DATA BUS PROGRAM BUS 32K BYTES ROM EPROM DAT 26 1024 BYTES BUS DATA RAM 27 EXTERNAL ADDRESS T ee DATABUS MEMORY MMR BUS gt 4 32 gt 08 CAN DLL do Tra 42 CORE US 6 493 287 SFR BUS 43 41 UART 0 SPI TIMER 0 TIMER 1 TIMER 2 WATCHDOG TIMER CPU CORE 22 U S Patent Dec 10 2002 Sheet 3 of 7 US 6 493 287 MMRs MMR name RAW Reset Access Address Offset Message Object Registers n 0 31 OOngngngn4nq0000b nOh Message n Match ID High MMOL RW oxh Word only 000 797917000108 101 Message n Match ID Low 0 10 14 Messag
8. US006493287B1 United States Patent 12 10 Patent No US 6 493 287 B1 Birns et al 45 Date of Patent Dec 10 2002 54 CAN MICROCONTROLLER THAT UTILIZES EP 1085423 2 3 2001 GO06F 15 00 A DEDICATED RAM MEMORY SPACE TO STORE MESSAGE OBJECT cited by examiner CONFIGURATION INFORMATION 75 Inventors Neil Edward Birns Cupertino CA Primary Examiner Richard Elms wey S J Slivkoff San Jose Assistant Examiner VanThu Nguyen CA US 57 ABSTRACT 73 Assignee Koninklijke Philips Electronics N V Eindhoven NL A CAN microcontroller that supports a plurality of message objects including a processor core that runs CAN Notice Subject to any disclaimer the term of this applications a CAN CAL module that processes incoming patent is extended or adjusted under 35 messages and a data memory space The data memory space U S C 154 b by 305 days includes a plurality of message buffers associated with respective ones of the message objects and a dedicated 21 Appl No 09 630 665 RAM memory space that contains a plurality of memory nor mapped registers associated with each of the message 22 Filed Aug 1 2000 objects The plurality of memory mapped registers associ Related U S Application Data ated with each message object correspond to respective 60 Provisional application No 60 154 022 filed on Sep 15 command control fields for facilitating configuration and 1999 setup of that message object Each
9. a Byte 1 and Data Byte 2 of the received CAN Frame the IDE bit Thus the user is required to set the Msk1 and Msk0 bits in the Mask Field MnMSKL register for Standard CAN Frame Message Objects i e to don t care In addition in many applications based on Standard CAN Frames either Data Byte 1 Data Byte 2 or both do not participate in Acceptance Filtering In those applications the user must also mask out the unused Data Byte s The IDE bit is not maskable As is illustrated in FIG 10 the Screener ID field for an Extended CAN Frame is 30 bits consisting of 29 CAN ID bits extracted from the header of the incoming CAN Frame the IDE bit Again the IDE bit is not maskable 2 The assembled Screener ID field of the received CAN Frame is then sequentially compared to the corresponding Match ID values specified in the MnMIDH and MnMIDL registers for all currently enabled Receive Message Objects Of course any bits in the Screener ID field that are masked by a particular Message Object are not included in the comparison That is if there is a 1 in a bit position of the Mask field specified in the MnMSKH and MnMSKL reg isters for a particular Message Object then the correspond ing bit position in the Match ID field for that particular Message Object becomes a don t care i e always yields a match with the corresponding bit of the Screener ID of the received CAN Frame 3 If the above comparison process yields a ma
10. age Object n the DMA engine 38 will generate addresses automatically starting from the base address of that message buffer as specified in the MnBLR register associated with that Message Object n Since the size of that message buffer is specified in the MnBSZ register associated with that Message Object n the DMA engine 38 can determined when it has reached the top location of that message buffer If the DMA engine 38 determines that it has reached the top location of that message buffer and that the message being written into that message buffer has not been completely transferred yet the DMA engine 38 will wrap around by generating addresses starting from the base address of that message buffer again Some time before this happens a warning interrupt will be generated so that the user application can take the necessary action to prevent data loss The message handler will keep track of the current address location of the message buffer being written to by the DMA engine 38 and the number of bytes of each CAL message as it is being assembled in the designated message buffer After an End of Message for CAL message is decoded the message handler will finish moving the com plete CAL message and the Byte Count into the designated message buffer via the DMA engine 38 and then generate an interrupt to the XA CPU Core 22 indicating that a complete message has been received Since Data Byte 1 of each CAN Frame contains the fragmenta
11. ast one control field that specifies whether that message object is enabled or disabled that specifies whether that message object is a transmit or receive message object and or that specifies whether auto matic hardware assembly of fragmented receive messages is enabled or disabled for that message object 19 The CAN microcontroller as set forth in claim 1 wherein the memory mapped registers appear as special function registers to the CAN applications that run on the processor core 20 The CAN microcontroller as set forth in claim 19 wherein the memory mapped registers are accessed as RAM by hardware within the CAN microcontroller 20 25 35 45
12. base address of the message buffer for each particular Message Object n by programming the MnBLR register associated with that Message Object n 10 15 20 25 30 35 40 45 50 55 60 65 8 The upper 8 bits of the 24 bit address for all Message Objects are specified by the contents of the MBXSR register as previously discussed so that the message buffers for all Message Objects reside within the same 64 KByte memory segment The user is also responsible on set up for specifying the size of the message buffer for each Message Object n In particular the user can specify the size of the message buffer for each particular Message Object n by programming the MnBSZ register associated with that Mes sage Object n The top location of the message buffer for each Message Object n is determined by the size of that message buffer as specified in the corresponding MnBSZ register The user can configure program the MnCTL register associated with each particular Message Object n in order to enable or disable that Message Object n in order to define or designate that Message Object n as a Tx or Rx Message Object in order to enable or disable automatic hardware assembly of fragmented Rx messages 1 automatic frag mented message handling for that Message Object n in order to enable or disable automatic generation of a Message Complete Interrupt for that Message Object n and in order to enable or not enable that
13. bus 25 A map of the code memory space is depicted in FIG 4 a Data RAM 26 internal or scratch pad data memory that is currently implemented as a 1024 Byte portion of the overall XA C3 data memory space and that is bi directionally coupled to the XA CPU Core 22 via an internal DATA bus 27 an on chip message buffer RAM or XRAM 28 that is currently implemented as a 512 Byte portion of the overall XA C3 data memory space which may contain part or all of the CAN CAL Transmit amp Receive Object message buff ers a Memory Interface MIF unit 30 that provides interfaces to generic memory devices such as SRAM DRAM flash ROM and EPROM memory devices via an external address data bus 32 via an internal Core Data bus 34 and via an internal MMR bus 36 a DMA engine 38 that provides 32 CAL DMA Channels a plurality of on chip Memory Mapped Registers MMRs 40 that are mapped to the overall XA C3 data memory space a 4K Byte portion of the overall XA C3 data memory space is reserved for MMRs These MMRs include 32 Message Object or Address Pointers and 32 ID Screeners or Match IDs corre sponding to the 32 CAL Message Objects A complete listing of all MMRs is provided in the Table depicted in FIG 5 a 2 0B CAN DLL Core 42 that is the CAN Controller Core from the Philips SJA1000 CAN 2 0A B Data Link Layer CDLL device hereinafter referred to as the CAN Core Block CCB and an array of standard microcontroller periphera
14. e n Mask High Word only O00ngngngnng0110b n6h Message n Mask Low O0Ongngngn4ngt000b 180 Message n Control O00runanontnotO10b nAh Message n Buffer Location 00 11006 nCh Message n Buffer Size OQ 0n4nanonino 10b nEh Message n Fragmentation Count i MCR 19 0 ByeWod 7 Message Complete Info Reg MER 9 000d 8yeWoo 2h Message Error Info Register Frame Error Status Register Byte Word Frame Error Enable Register SCP SPI Registers 0000h RW Oh ByteWord 281 SCP SPIDaa LSPCS RW oon ByteWord Beor Mh RW 0 ByeWod 1278 CANBus Timing Reg high RW j0n ByeWod 27 Tx ErrorCounter 2 RERC RW 00 2h Rx Error Counter 9 SyeWod Error Warning Limit Register 10 000h Byte Word LALR RO 0 Avbiration Lost Capture Reg 0000 MIF Registers FEh Legend R W Read amp Write RO Read Only WO Write Only R C Read amp Clear W Writable only during F 0 4 CAN Reset mode x undefined after reset i U S Patent Dec 10 2002 Sheet 4 of 7 US 6 493 287 Data Memory Segment 0 OOFFFFh Off Chip AK Byles MMR Space MMR Base Address E Off Chip XRAM Off Chip Data Memory Scratch Pad 000000h FIG 5 XRAM Base
15. e retrieved transmit message data to the CCB 42 for transmission The same DMA engine and address pointer logic is used for message retrieval of trans mit messages as is used for message storage of receive messages as described previously Further message buffer location and size information is specified in the same way as described previously In short when a transmit message is retrieved it will be written by the DMA engine 38 to the CCB 42 sequentially During this process the DMA engine 38 will keep requesting the bus when bus access is granted the DMA engine 38 will sequentially read the transmit message data from the location in the message buffer cur rently pointed to by the address pointer logic and the DMA engine 38 will sequentially write the retrieved transmit message data to the CCB 42 It is noted that when preparing a message for transmission the user application must not include the CAN ID and Frame Information fields in the transmit message data written into the designated message buffer since the Transmit Tx logic will retrieve this information directly from the appropriate MnMIDH MnMIDL and MnMSKH registers The XA C3 microcontroller 20 does not handle the trans mission of fragmented messages in hardware It is the user s responsibility to write each CAN Frame of a fragmented message to the appropriate message buffer enable the asso ciated Transmit Message Object for transmission and wait for a completion befo
16. e transmitted completely before the next transmit US 6 493 287 13 message gets transmitted For the third case above the transmit message will not be transmitted Instead a transmit message with new content will enter Tx Pre Arbitration There is an additional mechanism that prevents corruption of a message that is being transmitted In particular if a transmission is ongoing for a Transmit Message Object the user will be prevented from clearing the bit in the MnCTL register associated with that particular Transmit Message Object CAN CAL Related Interrupts The CAN CAL module 77 of the XA C3 microcontroller 20 is presently configured to generate the following five different Event interrupts to the XA CPU Core 22 1 Rx Message Complete 2 Tx Message Complete 3 Rx Buffer Full 4 Message Error 5 Frame Error For single frame messages the Message Complete con dition occurs at the end of the single frame For multi frame fragmented messages the Message Complete condition occurs after the last frame is received and stored Since the XA C3 microcontroller 20 hardware does not recognize or handle fragmentation for transmit messages the Tx Message Complete condition will always be generated at the end of each successfully transmitted frame As previously mentioned there is a control bit associated with each Message Object indicating whether a Message Complete condition should generate an interrupt o
17. emory space encompasses a plurality of separate RAM modules each RAM module being dedicated to a respective one of the command control fields The memory mapped registers cor responding to a respective one of the command control fields are located in respective designated addressable memory storage locations within the separate RAM module dedicated to that command control field with a different addressable memory storage location being designated for each respective one of the message objects In one particular implementation all of the memory mapped registers corre sponding to a respective one of the command control fields are located in a respective one of the separate RAM modules dedicated to that command control field In a presently preferred embodiment the CAN microcon troller supports a number n of message objects each having a number m of associated memory mapped registers corre sponding to m respective command control fields with n different addressable storage locations being designated in each separate RAM module one for each of the n respective message objects In this embodiment the dedicated RAM memory space encompasses m separate RAM modules each of the separate RAM modules corresponding to a respective one of the m command control fields 05 6 493 287 3 Preferably the memory mapped registers appear as spe cial function registers to the CAN applications that run on the processor core but are accessed as RA
18. er Controller User Manual both of which are part of the parent Provisional Application Serial No 60 154 022 the disclo sure of which has been fully incorporated herein for all purposes THE PRESENT INVENTION As was previously described in detail hereinabove the XA C3 microcontroller 20 supports up to 32 separate and independent Message Objects each of which is set up or defined by virtue of the user programmer configuring programming some or all of the eight MMRs 40 dedicated to that Message Object In accordance with the present invention a significant amount of die area is conserved by implementing these MMRs 40 in Random Access Memory 10 15 20 25 30 40 45 50 60 65 14 RAM modules as opposed to flip flop based registers The command control field corresponding to each MMR 40 appears to the user software as a special function register and is addressed as such by the software Physically however these command control fields reside in the RAM modules and are accessed as RAM by the hardware With the XA C3 microcontroller 20 a total of 256 command control fields are provided 1 8 fields per Message Objectx 32 Message Objects which would require a total of nearly 3 000 flip flops if they were implemented as conventional special function registers This would have consumed a great deal of die area which would have resulted in increased power consumption and radiated noise due to tremendous
19. for each of the n respective message objects and the dedicated RAM memory space comprises m separate RAM modules each of the separate RAM modules corresponding to a respective one of the m command control fields 16 10 The CAN microcontroller as set forth in claim 1 wherein the CAN microcontroller supports a number n of message objects each having a number m of associated memory 5 mapped registers corresponding to m respective command control fields n different addressable storage locations are designated in each separate RAM module one for each of the n respective message objects and the dedicated RAM memory space comprises m separate RAM modules each of the separate RAM modules corresponding to a respective one of the m command control fields 11 The CAN microcontroller as set forth in claim 1 wherein the command control fields associated with each message object include at least one message acceptance filtering screener field 12 The CAN microcontroller as set forth in claim 1 wherein the command control fields associated with each message object include at least one message acceptance filtering match ID field and at least one message acceptance filtering mask ID field 13 The CAN microcontroller as set forth in claim 1 wherein the command control fields associated with each message object include at least one buffer location field that specifies a base address in the data memory space for the message buffer as
20. foregoing it can be appreciated that there presently exists a need in the art for a hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance assignee of the present invention has recently devel oped a new microcontroller product designated XA C3 that fulfills this need in the art The XA C3 is the newest member of the Philips XA eXtended Architecture family of 10 15 20 25 35 40 45 50 55 60 65 2 high performance 16 bit single chip microcontrollers It is believed that the XA C3 is the first chip that features hardware CAL support The XA C3 is a CMOS 16 bit CAL CAN 2 0B micro controller that incorporates a number of different inventions including the present invention These inventions include novel techniques and hardware for filtering buffering handling and processing CAL CAN messages including the automatic assembly of multi frame fragmented mes sages with minimal CPU intervention as well as for man aging the storage and retrieval of the message data and the memory resources utilized therefor The present invention relates to a CAN microcontroller that utilizes a dedicated RAM memory space e g dedicated RAM modules to store setup and configuration information command control fields for eac
21. h of a plurality of message objects supported by the CAN microcontroller A significant amount of die area is conserved by implementing these memory mapped registers in RAM modules as opposed to conventional flip flop based registers The use of conven tional flip flop based registers also would result in increased power consumption and radiated noise due to tremendously increased parasitic loading on clock lines as well as entail ing significant additional costs Thus the present invention achieves enhanced performance lower cost and smaller size relative to the presently available technology SUMMARY OF THE INVENTION present invention encompasses a CAN microcontrol ler that supports a plurality of message objects including a processor core that runs CAN applications a CAN CAL module that processes incoming messages and a data memory space The data memory space includes a plurality of message buffers associated with respective ones of the message objects and a dedicated RAM memory space that contains a plurality of memory mapped registers associated with each of the message objects The plurality of memory mapped registers associated with each message object cor respond to respective command control fields for facilitating configuration and setup of that message object Each of the memory mapped registers is mapped to a respective storage location within the dedicated RAM memory space In one embodiment the dedicated RAM m
22. have heretofore been implemented primarily in software with very little hardware CAL support Consequently CALs have heretofore required a great deal of host CPU intervention thereby increasing the processing overhead and diminishing the performance of the host CPU Thus there is a need in the art for a CAN hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU to the CAN hardware thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance One of the most demanding and CPU resource intensive CAL functions is message management which entails the handling storage and processing of incoming CAL CAN messages received over the CAN serial communications bus and or outgoing CAL CAN messages transmitted over the CAN serial com munications bus CAL protocols such as DeviceNet CANopen and OSEK deliver long messages distributed over many CAN frames which methodology is sometimes referred to as fragmented or segmented messaging The process of assembling such fragmented multi frame mes sages has heretofore required a great deal of host CPU intervention In particular CAL software running on the host CPU actively monitors and manages the buffering and processing of the message data in order to facilitate the assembly of the message fragments or segments into com plete messages Based on the above and
23. he DMA engine 38 will keep requesting the bus writing message data sequen tially to the appropriate message buffer location until the 10 15 20 25 30 35 40 45 50 55 60 65 10 whole accepted CAN Frame is transferred After the DMA engine 38 has successfully transferred an accepted CAN Frame to the appropriate message buffer location the con tents of the message buffer will depend upon whether the message that the CAN Frame belongs to is a non fragmented single frame message or a fragmented message Each case is described below Non Fragmented Message Assembly For Message Objects that have been set up with automatic fragmented message handling disabled not enabled i e the FRAG bit in the MnCTL register for that Message Object is set to 0 the complete CAN ID of the accepted CAN Frame which is either 11 or 29 bits depending on whether the accepted CAN Frame is a Standard or Extended CAN Frame is written into the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match once the DMA engine 38 has successfully transferred the accepted CAN Frame to the message buffer associated with that Message Object This will permit the user application to see the exact CAN ID which resulted in the match even if a portion of the CAN ID was masked for Acceptance Filtering As a result of this mechanism the contents of the MnMIDH and MnMIDL registers can change
24. he user in designated MMRs Individual Mask patterns assure that single Receive Objects can Screen for multiple acknowledged CAL CAN Frames and thus minimize the number of Receive Objects that must be dedicated to such lower priority Frames This ability to Mask individual Message Objects is an important new CAL feature CAL CAN Application Layer A generic term for any high level protocol which extends the capabilities of CAN while employing the CAN physical layer and the CAN frame format and which adheres to the CAN specification Among other things CALs permit transmission of Messages which exceed the 8 byte data limit inherent to CAN Frames This is accomplished by dividing each message into multiple packets with each packet being transmitted as a single CAN Frame consisting of a maximum of 8 data bytes Such messages are commonly referred to as segmented or fragmented messages The individual CAN Frames con stituting a complete fragmented message are not typically transmitted in a contiguous fashion but rather the individual CAN Frames of different unrelated messages are inter leaved on the CAN bus as is illustrated in FIG 2 Fragmented Message A lengthy message in excess of 8 bytes divided into data packets and transmitted using a sequence of individual CAN Frames The specific ways that sequences of CAN Frames construct these lengthy messages is defined within the context of a specific CAL The XA C3 microcontroller auto
25. ignated MBXSR and XRAMB see FIG 4 user can place the 4 KByte space reserved for MMRs 40 anywhere within the entire 16 Mbyte data memory space supported by the XA architecture other than at the very bottom of the memory space 1 the first 1 KByte portion starting address of 000000h where it would conflict with the on chip Data RAM 26 that serves as the internal or scratch pad memory The 4 KBytes of MMR space will always start at a 4K boundary The reset values for MRBH and MRBL are OFh and FOh respectively Therefore after a reset the MMR space is mapped to the uppermost 4K Bytes of Data Segment OFh but access to the MMRs 40 is disabled The first 512 Bytes offset 000h 1FFh of MMR space are the Message Object Registers eight per Message Object for objects n20 31 as is shown in FIG 6 base address of the XRAM 28 is determined by the contents of the MMRs designated MBXSR and XRAMB as is shown in FIGS 7 and 8 As previously mentioned the 512 Byte XRAM 28 is where some or all of the 32 Rx Tx message buffers corresponding to Message Objects 0 31 reside The message buffers can be extended off 05 6 493 287 7 chip to a maximum of 8 KBytes This off chip expansion capability can accommodate up to thirty two 256 Byte message buffers Since the uppermost 8 bits of all message buffer addresses are formed by the contents of the MBXSR register the XRAM 28 and all 32 message buffers must reside
26. igned Message Object Message Object A Receive RAM buffer of pre specified size up to 256 bytes for CAL messages and associated with a particular Acceptance Filter or a Transmit RAM buffer which the User preloads with all necessary data to transmit a complete CAN Data Frame A Message Object can be considered to be a communication channel over which a complete message or succession of messages can be transmitted CAN Arbitration ID An 11 bit Standard CAN 2 0 Frame or 29 bit Extended CAN 2 0B Frame identifier field placed in the CAN Frame Header This ID field is used to arbitrate Frame access to the CAN bus Also used in Acceptance Filtering for CAN Frame reception and Transmit Pre Arbitration Screener ID 30 bit field extracted from the incoming message which is then used in Acceptance Filtering The Screener ID includes the CAN Arbitration ID and the IDE bit and can include up to 2 Data Bytes These 30 extracted bits are the information qualified by Acceptance Filtering Match ID A 30 bit field pre specified by the user to which the incoming Screener ID is compared Individual Match IDs for each of 32 Message Objects are programmed by the user into designated Memory Mapped Registers Mask A 29 bit field pre specified by the user which can override Mask a Match ID comparison at any particular bit or combination of bits in an Acceptance Filter Individual Masks one for each Message Object are programmed by t
27. in the same 64K Byte data memory segment Since the XA C3 microcontroller 20 only provides address lines 0 19 for accessing external memory all external memory addresses must be within the lowest 1 MByte of address space Therefore if there is external memory in the system into which any of the 32 message buffers will be mapped then all 32 message buffers and the XRAM 28 must also be mapped entirely into that same 64K Byte segment which must be below the 1 MByte address limit After the memory space has been mapped the user can set up or define up to 32 separate Message Objects each of which can be either a Transmit Tx or a Receive Rx Message Object A Rx Message Object can be associated either with a unique CAN ID or with a set of CAN IDs which share certain ID bit fields As previously mentioned each Message Object has its own reserved block of data memory space up to 256 Bytes which is referred to as that Message Object s message buffer As will be seen both the size and the base address of each Message Object s message buffer is programmable As previously mentioned each Message Object is asso ciated with a set of eight MMRs 40 dedicated to that Message Object Some of these registers function differently for Tx Message Objects than they do for Rx Message Objects These eight MMRs 40 are designated Message Object Registers see FIG 4 The names of these eight MMRs 49 are MnMIDH Message n Match ID High M
28. inventive con cepts taught herein which may appear to those skilled in the pertinent art will still fall within the spirit and scope of the present invention as defined in the appended claims 05 6 493 287 15 What is claimed is 1 A CAN microcontroller that supports a plurality of message objects comprising a processor core that runs CAN applications a CAN CAL module that processes incoming messages a data memory space including a plurality of message buffers associated with respective ones of the message objects and a dedicated RAM memory space that contains a plurality of memory mapped registers asso ciated with each of the message objects the plurality of memory mapped registers associated with each mes sage object corresponding to respective command control fields for facilitating configuration and setup of that message object and wherein each of the memory mapped registers is mapped to a respective storage location within the dedicated RAM memory space 2 The CAN microcontroller as set forth in claim 1 wherein the incoming messages include multi frame frag mented messages and the CAN CAL module automatically assembles the multi frame fragmented messages 3 The CAN microcontroller as set forth in claim 1 wherein the CAN CAL module includes the dedicated RAM memory space 4 The CAN microcontroller as set forth in claim 1 wherein the processor core the CAN CAL module and the dedicated RAM memory s
29. lnfo next Data Byte 1 next Data Byte 2 next FIG 12 DIRECTION OF INCREASING ADDRESS DIRECTION OF INCREASING ADDRESS US 6 493 287 B1 1 CAN MICROCONTROLLER THAT UTILIZES A DEDICATED RAM MEMORY SPACE TO STORE MESSAGE OBJECT CONFIGURATION INFORMATION This application claims the full benefit and priority of U S Provisional Application Serial No 60 154 022 filed on Sep 15 1999 the disclosure of which is fully incorporated herein for all purposes BACKGROUND OF THE INVENTION The present invention relates generally to the field of data communications and more particularly to the field of serial communications bus controllers and microcontrollers that incorporate the same CAN Control Area Network is an industry standard two wire serial communications bus that is widely used in automotive and industrial control applications as well as in medical devices avionics office automation equipment consumer appliances and many other products and appli cations CAN controllers are currently available either as stand alone devices adapted to interface with a microcon troller or as circuitry integrated into or modules embedded in a microcontroller chip Since 1986 CAN users software programmers have developed numerous high level CAN Application Layers CALs which extend the capabilities of the CAN while employing the CAN physical layer and the CAN frame format and adhering to the CAN specification CALs
30. ls that are bi directionally coupled to the XA CPU Core 22 via a Special Function Register SFR bus 43 These stan dard microcontroller peripherals include Universal Asynchronous Receiver Transmitter UART 49 an SPI serial interface port 51 three standard timers counters with toggle output capability namely Timer 0 amp Timer 1 included in Timer block 53 and Timer 2 included in Timer block 54 a Watchdog Timer 55 and 10 15 20 25 40 45 50 55 60 65 6 four 8 bit I O ports namely Ports 0 3 included in block 61 each of which has 4 programmable output configurations The DMA engine 38 the MMRs 40 and the CCB 42 can collectively be considered to constitute a CAN CAL module 77 and will be referred to as such at various times through out the following description Further the particular logic elements within the CAN CAL module 77 that perform message management and message handling functions will sometimes be referred to as the message management engine and the message handler respectively at various times throughout the following description Other nomen clature will be defined as it introduced throughout the following description As previously mentioned the XA C3 microcontroller 20 automatically implements in hardware many message man agement and other functions that were previously only implemented in software running on the host CPU or not implemented at all incl
31. ly increased parasitic loading on the clock lines as well as significant additional costs In accordance with the specific implementation of the present invention embodied in the XA C3 microcontroller 20 a separate dedicated RAM module or RAM memory space is provided for each of the eight command control fields with each dedicated RAM module being 32 words deep in order to thereby provide one addressable memory location corresponding to each of the 32 respective Message Objects Thus the MMR 40 corresponding to a given command control field for a given Message Object will be located in a designated addressable memory location for that Message Object within the respective one of the eight RAM modules that is dedicated to that command control field Thus each of the eight RAM modules will contain a respective one of the eight MMRs 40 for each of the thirty two Message Objects i e each RAM module will contain 32 of the 256 total MMRs 40 user software accesses these RAM modules as memory mapped special function registers which reside within the overall addressable memory space of the XA C3 microcontroller 20 which is currently configured to be a 16 Mbyte memory space as previously discussed A full 24 bit address is employed to identify each register within this 16 Mbyte memory space It is not apparent in any way to the user that these registers differ from any other special function registers on the chip i e the fact
32. matically re assembles these packets into the original lengthy message in hardware and reports via an interrupt when the completed re assembled message is available as an associated Receive Message Object US 6 493 287 5 Message Buffer Ablock of locations in XA Data memory where incoming received messages are stored or where outgoing transmit messages are staged MMR Memory Mapped Register An on chip command control status register whose address is mapped into XA Data memory space and is accessed as Data memory by the XA processor With the XA C3 microcontroller a set of eight dedicated MMRs are associated with each Message Object Additionally there are several MMRs whose bits control global parameters that apply to all Message Objects With reference now to FIG 3 there can be seen a high level block diagram of the XA C3 microcontroller 20 The XA C3 microcontroller 20 includes the following func tional blocks that are fabricated on a single integrated circuit IC chip packaged in a 44 pin PLCC or a 44 pin LQFP package an XA CPU Core 22 that is currently implemented as a 16 bit fully static CPU with 24 bit program and data address range that is upwardly compatible with the 80C51 architecture and that has an operating fre quency of up to 30 MHz a program or code memory 24 that is currently imple mented as a 32K ROM EPROM and that is bi directionally coupled to the XA CPU Core 22 via an internal Program
33. nMIDL Message n Match ID Low MnMSKH Message n Mask High MnMSKL Message n Mask Low MnCTL Message n Control MnBLR Message n Buffer Location Register MnBSZ Message n Buffer Size MnFCR Message n Fragment Count Register where n ranges from 0 to 31 ie corresponding to 32 independent Message Objects In general the user defines or sets up a Message Object by configuring programming some or all of the eight MMRs dedicated to that Message Object as will be described below Additionally as will be described below the user must configure program the global GCTL register whose bits control global parameters that apply to all Message Objects In particular the user can specify the Match ID value for each Message Object to be compared against the Screener IDs extracted from incoming CAN Frames for Acceptance Filtering The Match ID value for each Message Object n is specified in the MnMIDH and MnMIDL registers associated with that Message Object n The user can mask any Screener ID bits which are not intended to be used in Acceptance Filtering on an object by object basis by writing a logic 1 in the desired to be masked bit position s in the appro priate MnMSKH and or MnMSKL registers associated with each particular Message Object n The user is responsible on set up for assigning a unique message buffer location for each Message Object n In particular the user can specify the least significant 16 bits of the
34. or an Extended CAN Frame FIG 11 is a diagram illustrating the message storage format for fragmented CAL messages and FIG 12 is a diagram illustrating the message storage format for fragmented CAN messages DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is described below in the context of a particular implementation thereof 1 in the context of the XA C3 microcontroller manufactured by Philips Semicon ductors Of course it should be clearly understood that the present invention is not limited to this particular implementation as any one or more of the various aspects and features of the present invention disclosed herein can be utilized either individually or any combination thereof and in any desired application e g a stand alone CAN controller device or as part of any other microcontroller or system The following terms used herein in the context of describ ing the preferred embodiment of the present invention the XA C3 microcontroller are defined as follows Standard CAN Frame format of a Standard CAN Frame is depicted in FIG 1 Extended CAN Frame The format of an Extended CAN Frame is also depicted in FIG 1 10 15 20 25 30 35 40 45 50 55 60 65 4 Acceptance Filtering process a CAN device implements in order to deter mine if a CAN frame should be accepted or ignored and if accepted to store that frame in a pre ass
35. pace are contained on a single integrated circuit chip 5 The CAN microcontroller as set forth in claim 1 wherein the processor core the CAN CAL module and the data memory space are contained on a single integrated circuit chip 6 The CAN microcontroller as set forth in claim 1 wherein the dedicated RAM memory space comprises a plurality of separate RAM modules each RAM module being dedicated to a respective one of the command control fields 7 The CAN microcontroller as set forth in claim 6 wherein all of the memory mapped registers corresponding to a respective one of the command control fields are located in a respective one of the separate RAM modules dedicated to that command control field 8 The CAN microcontroller as set forth in claim 7 wherein the memory mapped registers corresponding to a respective one of the command control fields are located in respective designated addressable memory storage loca tions within the separate RAM module dedicated to that command control field with a different addressable memory storage location being designated for each respective one of the message objects 9 The CAN microcontroller as set forth in claim 8 wherein the CAN microcontroller supports a number n of message objects each having a number m of associated memory mapped registers corresponding to m respective command control fields n different addressable storage locations are designated in each separate RAM module one
36. r just set a Message Complete Status Flag for polling without generating an interrupt This is the INT_EN bit in the MnCTL register associated with each Message Object n There are two 16 bit MMRs 40 MCPLH and MCPLL which contain the Message Complete Status Flags for all 32 Message Objects When a Message Complete Tx or Rx condition is detected for a particular Message Object the corresponding bit in the MCPLH or MCPLL register will be set This will occur regardless of whether the INT EN bit is set for that particular Message Object in its associated MnCTL register or whether Message Complete Status Flags have already been set for any other Message Objects In addition to these 32 Message Complete Status Flags there is a Tx Message Complete Interrupt Flag and an Rx Message Complete Interrupt Flag corresponding to bits 1 and 0 respectively of an MMR 40 designated CANINTFLG which will generate the actual Event inter rupt requests to the XA CPU Core 22 When an End of Message condition occurs at the same moment that the Message Complete Status Flag is set the appropriate Tx or Rx Message Complete Interrupt flip flop will be set pro vided that INT EN 1 for the associated Message Object and provided that the interrupt is not already set and pend ing Further details regarding the generation of interrupts and the associated registers can be found in the XA C3 Func tional Specification and in the XA C3 CAN Transport Lay
37. re writing the next CAN Frame of that fragmented message to the appropriate message buffer The user application must therefore transmit multiple CAN Frames one at a time until the whole multi frame frag mented transmit message is successfully transmitted However by using multiple Transmit Message Objects whose object numbers increase sequentially and whose CAN IDs have been configured identically several CAN Frames of a fragmented transmit message can be queued up and enabled and then transmitted in order avoid data corruption when transmitting messages there are three possible approaches 1 If the Tx Message Complete interrupt is enabled for the transmit message the user application would write the next transmit message to the designated transmit message buffer upon receipt of the Tx Message Complete interrupt Once the interrupt flag is set it is known for certain that the pending transmit message has already been transmitted 2 Wait until the bit of the MnCTL register of the associated Transmit Message Object clears before writ ing to the associated transmit message buffer This can be accomplished by polling the bit of the MnCTL register of the associated Transmit Message Object 3 Clear the bit of the MnCTL register of the associated Transmit Message Object while that Transmit Message Object is still in Tx Pre Arbitration In the first two cases above the pending transmit message will b
38. sociated with that message object and at least one buffer size field that specifies a size of the message buffer associated with that message object 14 The CAN microcontroller as set forth in claim 13 wherein the command control fields associated with each message object further include at least one buffer location field that specifies a base address in the data memory space for the message buffer associated with that message object and at least one buffer size field that specifies a size of the message buffer associated with that message object 15 The CAN microcontroller as set forth in claim 1 wherein the command control fields associated with each message object include at least one control field that speci fies whether that message object is enabled or disabled 16 The CAN microcontroller as set forth in claim 1 wherein the command control fields associated with each message object include at least one control field that speci fies whether that message object is a transmit or receive message object 17 The CAN microcontroller as set forth in claim 1 wherein the command control fields associated with each message object include at least one control field that speci fies whether automatic hardware assembly of fragmented receive messages is enabled or disabled for that message object 18 The CAN microcontroller as set forth in claim 14 wherein the command control fields associated with each message object further include at le
39. ssage Object and its associated MnCTL register has its FRAG bit set to 1 i e automatic fragmented message assembly is enabled for that particular Receive Message Object then the first data byte Data Byte 1 of each received CAN Frame that matches that particular Receive Message Object will be used to encode fragmentation information only and thus will not be stored in the message buffer for that particular Receive Message Object Thus message storage for such enabled Receive Message Objects will start with the second data byte Data Byte 2 and proceed in the previously described manner until a complete multi frame message has been received and stored in the appropriate message buffer This message storage format is illustrated in FIG 11 The message handler hardware will use the fragmentation infor mation contained in Data Byte 1 of each CAN Frame to facilitate this process US 6 493 287 11 Under the CAN protocol if a Message Object is an enabled Receive Message Object and its associated MnCTL register has its FRAG bit set to 1 1 automatic frag mented message assembly is enabled for that particular Receive Message Object then the CAN Frames that match that particular Receive Message Object will be stored sequentially in the message buffer for that particular Receive Message Object using the format shown in FIG 12 When writing message data into a message buffer asso ciated with a Mess
40. tch with more than one Message Object then the received CAN Frame will be deemed to have matched the Message Object having the lowest object number n Message Storage Each incoming received CAN Frame that passes Accep tance Filtering will be automatically stored via the DMA engine 38 into the message buffer for the Receive Message Object that particular CAN Frame was found to have matched In an exemplary implementation the message buffers for all Message Objects are contained in the XRAM 28 Message Assembly In general the DMA engine 38 will transfer each accepted CAN Frame from the 13 byte pre buffer to the appropriate message buffer e g in the XRAM 28 one word at a time starting from the address pointed to by the contents of the MBXSR and MnBLR registers Every time the DMA engine 38 transfers a byte or a word it has to request the bus In this regard the MIF unit 30 arbitrates between accesses from the XA CPU Core 22 and from the DMA engine 38 In general bus arbitration is done on an alternate policy After a DMA bus access the XA CPU Core 22 will be granted bus access if requested After an XA CPU bus access the DMA engine 38 will be granted bus access if requested However a burst access by the XA CPU Core 22 cannot be interrupted by a DMA bus access Once bus access is granted by the MIF unit 30 the DMA engine 38 will write data from the 13 byte pre buffer to the appropriate message buffer location T
41. ted with that Transmit Mes sage Object n must be set except when transmitting an Auto Acknowledge Frame in CANopen This will allow this ready to transmit message to participate in the pre arbitration process In this connection if more than one message is ready to be transmitted i e if more than one Transmit Message Object is enabled a Tx Pre Arbitration process will be performed to determine which enabled 10 15 25 30 35 45 50 55 60 65 12 Transmit Message Object will be selected for transmission There are two Tx Pre Arbitration policies which the user can choose between by setting or clearing the Pre Arb bit in the GCTL register After a Tx Message Complete interrupt is generated in response to a determination being made by the message handler that a completed message has been successfully transmitted the Tx Pre Arbitration process is reset and begins again Also if the winning Transmit Message Object subsequently loses arbitration on the CAN bus the Tx Pre Arbitration process gets reset and begins again If there is only one Transmit Message Object whose EN bit is set it will be selected regardless of the Tx Pre Arbitration policy selected Once an enabled Transmit Message Object has been selected for transmission the DMA engine 38 will begin retrieving the transmit message data from the message buffer associated with that Transmit Message Object and will begin transferring th
42. that these registers are embodied as addressable memory locations within dedicated RAM memory space rather than as flip flop based SFRs is transparent to the user When the hardware accesses these registers or command control fields for read write operations it uses a 5 bit address in order to address the RAM modules as independent stand alone RAMS distinct from the overall memory space of the XA C3 microcontroller 20 In certain cases different RAM modules which are accessed independently by the software are accessed simul taneously as a single entity by the hardware For example the two match ID fields for a Message Object and the two corresponding mask ID fields are all located in separate independent RAM modules as far as the software is concerned i e four individual write read instructions must be executed in order to access these fields During the input message acceptance filtering process however the hardware accesses all four of these locations concurrently Another example is the message buffer pointer and the message size fields which are accessed concurrently by the hardware as part of the DMA process but are independently addressed by the software Although the present invention has been described in detail hereinabove in the context of a specific preferred embodiment implementation it should be clearly under stood that many variations modifications and or alternative embodiments implementations of the basic
43. tion information it will never be stored in the designated message buffer for that CAN Frame Thus up to seven data bytes of each CAN Frame will be stored After the entire message has been stored the designated message buffer will contain all of the actual informational data bytes received exclusive of fragmentation information bytes plus the Byte Count at location 00 which will contain the total number of informational data bytes stored It is noted that there are several specific user set up programming procedures that must be followed when invok ing automatic hardware assembly of fragmented OSEK and CANopen messages These and other particulars can be found in the XA C3 CAN Transport Layer Controller User Manual that is part of the parent Provisional Application Serial No 60 154 022 the disclosure of which has been fully incorporated herein for all purposes Transmit Message Objects and the Transmit Process In order to transmit a message the XA application pro gram must first assemble the complete message and store it in the designated message buffer for the appropriate Trans mit Message Object n The message header CAN ID and Frame Information must be written into the MnMIDH MnMIDL and MnMSKH registers associated with that Transmit Message Object n After these steps are completed the XA application is ready to transmit the message To initiate a transmission the object enable bit OBJ bit of the MnCTL register associa
44. uding transparent automatic re assembly of up to 32 concurrent interleaved multi frame fragmented CAL messages For each application that is installed to run on the host CPU 1 the XA CPU Core 22 the user software programmer must set up the hard ware for performing these functions by programming certain ones of the MMRs and SFRs in the manner set forth in the XA C3 Functional Specification and XA C3 CAN Transport Layer Controller User Manual The register programming procedures that are most relevant to an understanding of the present invention are described below followed by a description of the various message management and other functions that are automatically performed by the CAL CAN module 77 during operation of the XA C3 microcon troller 20 after it has been properly set up by the user Following these sections a more detailed description of the particular invention to which this application is directed is provided Set up Programming Procedures As an initial matter the user must map the overall XA C3 data memory space as illustrated in FIG 5 In particular subject to certain constraints the user must specify the starting or base address of the XRAM 28 and the starting or base address of the MMRs 40 The base address of the MMRs 40 can be specified by appropriately programming Special Function Registers SFRs MRBL and MRBH The base address of the XRAM 28 can be specified by appro priately programming the MMRs des
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