TE0300 Board Reference Manual
Contents
1. FPGA ba dir FPGA FPGA B2B name nk name pin name 1 VccIO VccO 0 I I O VccO VccIO 2 3 VccIO VccO 0 I I O VccO VccIO 4 5 B3 LO1 P Cl IO LOIP 3 IO 3 3V Y Y 3 3V IO 3 IO L07P G6 B3 L07 P 6 7 B3 LO1 N C2 IO LOIN 3 IO 3 3V Y Y 3 3V IO 3 IO LO N G5 B3 L07 N 8 9 B3 L02 P Di IO LO2P 3 IO 3 3V Y Y 3 3V IO 3 IO LO3N Ei B3 LO3 N 10 11 B3 L02 N D2 IEEE 3 IO 3 3V Y Y 3 3V IO 3 IO LO3P E2 B3 LO3P 12 13 GND GND 14 15 BO IO C3 C3 IO L25P 0 IO VccIO N Y VccIO IO O IO L19 P F7 BO Li9 P 16 17 BO L24 N B4 IO L24 N O IO VccIO Y Y VccIO IO O br E7 BO LION 18 19 BO L24 P A4 10 L24P 0 IO VccIO Y Y VccIO IO O IO L21N E6 BO L21 N 20 21 B0 IO C4 C4 IO O IO VccIO N Y VccIO IO O IO L21P D6 BO L21 P 22 23 GND GND 24 IO L23N IO L18N 25 BO L23 N D5 VREF 0 IO VccIO Y Y VccIO IO 0 VREF D7 BO LI8 N 26 27 BO L23 P C5 IO L23P 0 IO VccIO Y Y VccIO IO O IO_L18P C7 BO L18 P 28 29 BO L20 P B6 IO L20P 20 IO VccIO Y Y VccIO IO O IO L17N N F8 BO L17N 30 31 BO L20 N A6 IO L2ON O IO VccIO Y Y VccIO IO O IO L17P ES BO Li7 P 32 33 3 3 V 3 3 V 34 35 BO IO A7 A7 IO O IO VccIO N N VccIO IO 0 IO A8 BO IO A8 36 IO L14N 37 BO IO G9 G9 IO 0 IO VccIO N Y VccIO IO 0 GCLK11 D9 GCLK_L14_N 38 IP L13P IO L14P 39 GCLK L13 P B8 GCLK8 O I VccIO Y Y VccIO IO O GCLK10 C9 GCLK L14 P 40 IP L13N IO L11N 41 GCLK_L13 N B9 J GCLKO O I VccIO Y Y VccIO IO O J GCLK5 E10 GCLK_L11 N 42 IO L11P 43 GND Y VccIO IO 0 GCLK4 D10 GCLK L11 P 44 IO L12P 45 GCLK2. r Trenz Electronic GmbH Spa rtan 3E FPGA e tren info trenz electronic de o electronic www trenz electronic de Industrial Micromodule on Rev 1 14 as of 2009 09 03 User Manual Features Industrial temperature grade avail u able on request m High density plug in Xilinx Spartan m Low cost versatile and ruggedized 3E module design USB 2 0 interface with high speed 480 Mbit s data rate m Large SPI flash for configuration and Specifications user storage accessible via USB or SPI m FPGA Xilinx Spartan 3E XC3S500E connector XC3S1600E m Large DDR SDRAM USB controller Cypress EZ USB FX2 m FPGA configuration is implemented via USB 2 0 microcontroller CY7C68013A JTAG SPI Flash or USB S6LFX 3 on board high power high effi Non volatile memory 16 MBit 64 ciency switch mode DC DC convert Mbit SPI Flash for FPGA configuration ers 1 A for each voltage rail 1 2 V and user data 2 5 V 3 3 V a Volatile memory 512 Mbit x 16 DDR m Power supply via USB or B2B carrier SDRAM with up to 666 Mbyte s board m Flexible expansion via high density shockproof B2B board to board connectors m Most I O s on the B2B connectors are routed as LVDS pairs Up to 110 FPGA user I Os Supply voltage range 4 0 V 5 5V 1 push button 1 LED Small size only 40 5 mm x 47 5 mm m Evenly spread supply pins for good Signal integrity is ti Figure 2 TEO300 bottom view Trenz Electronic GmbH 1 Spart
3. ioc EEPROM Files iic y Abbrechen I Schreibgesch tzt ffnen Y 5 Netzwerkumgeb Dateityp Upgrade progress is displayed in status window and is completed when Down load Successful text is displayed Trenz Electronic GmbH User Manual 7 EZ USB Interface Device USE Device a ee Co Ee El ed Get Dev Get Conf Get Pipes Get Strings Download e Load ig EEPROM URB Stat HOLD RUN vend Req Red 0x00 Yalue 0x084E Index 0x0000 Length jo Dir jo out y Hex Bytes C0 B4 04 81 00 01 00 y o Tran Pipe ES Length 1128 Packet Size Ej Packets a Bulk Trar Pipe Length 64 Hex Bytes BB ea Reset Pipe Abort Pipe File Trans Pipe Po Set IFace Interface o AltSetting jo 0000 02 OD 91 BB 01 OC ES 82 29 FS 82 ES 83 3A FS 83 EO 22 50 06 ES 25 82 F8 ES 22 BB FE 06 E9 25 82 F8 EZ 22 ES 82 29 FS 82 ES 83 3A F5 83 E4 93 22 F8 BB 01 OD ES 82 29 FS 82 ES 83 3A FS 83 ES FO 22 SO 06 ES 25 82 CS F6 22 BB FE 05 E9 25 82 C8 F2 22 EB SF FS FO EA 9E 42 FO ES 9D 42 FO ES 9C 45 FO 22 Downloading file C 1TEO3001usb iic Disconnect the USB cable Dedicated USB Firmware Driver Installation Check the configuration switches against the following table DIP on left off right switch S1 EEPROM S2 Run S3 FX2 PON S4 X X Reconnect the USB cable to run the newly uploaded firmware in the USB microcon troller Under the default switch configur ation the USB mic
4. debug_module_wrapper test_mux_O_wrapper I dimb_cntlr_wrapper I dimb_wrapper E download_cclktemp bit ilmb_cntlr_wrapper E system bit ilmb_wrapper 5 lmb_bram_wrapper O mb_opb_wrapper O microblaze_O_wrapper H opb_dma_0_wrapper L opb fx2 0 wrapper download bit FPGA Bit Files bit v The following warning is normal Warning This is probably the one and only file with your design Ee Add Device 2 tes Congratulations 16 Spartan 3E FPGA Industrial Micromodule El Add Device x i You have completed the device File entry a Click Ok to continue Click GENERATE FILE or select from menu Operations Generate file E iMPACT C Xilinx default ipf PROM File Formatter loj xj L Eile Edit View Operations Window Help 8 x eas le ee aa E SHH x 23 Boundary Scan i Gal SlaveSerial e Ba SelectMAP 8 Desktop Configuration ia Direct SPI Configuration I B System CE xc3s400 PROM File Formatter download bit xi A PROM File Generation Target Xilinx PROM 1 699 136 Bits used File fpga in Location C xilinx f Ai You are done Trenz Electronic GmbH User Manual EL iMPACT C xilinx default ipf PROM File Formatter i lol xj L Eile Edit View Operations Window Help 8 x PATIESI EACE SHH x H SlBoundary Scan is Ta SlaveS erial e Ba SelectMAP i 33 Desktop Configurati
5. The Spartan 3E architecture organizes I Os into four I O banks see Table 3 Bank Supply Min Max Voltage V V V B0 VccIO 1 2 3 3 B1 2 5 B2 3 3 B3 3 3 Table 3 I O banks power supply Voltage for banks B1 B2 and B3 is fixed respectively to 2 5 V 3 3 V and 3 3 V Voltage VccIO for bank BO shall span from 1 2 V to 3 3 V VccIO can be sup plied either externally or internally to the micromodule Externally Supplied VccIO VccIO can be externally supplied over the B2B connector J4 If bank BO is not used then VccIO can be left open Spartan 3E FPGA Industrial Micromodule Internally Supplied VccIO If VccIO is not externally supplied it can be internally supplied by one of the in ternal power rails of 2 5 V and 3 3 V This is possible by short circuiting one of the two pad pairs placed on the right of con nector J4 at the top right corner of the bottom side of the micromodule Figure 9 shows how to short circuit VccIO to internal 3 3 V power rail Figure 10 shows how to short circuit Vc cIO to internal 2 5 V power rail Figure 9 R102 pad pair blue high light for 3 3 V internal supply Figure 10 R103 pad pair blue high light for 2 5 V internal supply Two suitable ways of shirt circuiting the paid pair are by means of a zero ohm 0603 1608 metric chip resistor or a solder blob Trenz Electronic GmbH User Manual FPGA User I Os A tot
6. acne 11 Verification romp_etec PROGRESS END End Crcra icn Elaps d toe 4E sev v gt Watt Confguraticn PatformCeble USD C Milz usb hs 20 Spartan 3E FPGA Industrial Micromodule Switch S2 back to the Run position In case you uploaded the test design you Should see the on board led blinking at 0 5 Hz For further information about direct pure SPI in system programming of SPI Flash memories please see Xilinx Application Note XAPP951 Configuring Xilinx FPGAs with SPI Serial Flash SPI Indirect In System Programming ISP Check the configuration switches against the following table DIP on left off right switch S1 X X S2 Run S3 PON S4 X X Connect the host computer to the micro module through both the SPI flying leads cable and the USB cable Start Xilinx ISE MPACT The following ex ample shows the case of iMPACT 10 1 If the iMPACT Project window pops up press the Cancel button E iMPACT Project want to v Browse C Load most recent project file when iMPACT starts create a new project ipf default ipf B Cancel Double click the Boundary Scan option in the Modes panel Trenz Electronic GmbH User Manual Right click the Boundary Scan to initial ize the chain and select Initialize Chain J Options Ducput Debug Window kelf Gp Ele Edt View Cpe
7. 14 15 B3 L22 N PA IO L22N 3 IO 3 3V Y Y 3 3V IO 3 IO L21N PL B3 L2IN 16 17 B2 IP va va IP LO2P 2 I 33VN Y 33V IO 3 IO L21P P2 B3 L21 P 18 19 B3 L20 P NA IO L20P 3 IO 3 3V Y Y 3 3V IO 3 IO L23N R2 B3 L23 N 20 gt 21 B3 L20 N N5 IO L20N 3 IO 3 3V Y Y 3 3V IO 3 IO L23P R3 B3 L23 P 22 23 GND GND 24 25 B2 L04 N T5 IO LOAN 2 IO 3 3V Y N3 3V IO 3 IO L18N M3 B3 IO L18N 26 10_LO3P 27 B2 L04 P R5 IO LO4P 2 IO 3 3V Y N3 3V IO 2 DOUT U4 B2 IO L03 28 BUSY 29 B2 L05 P R6 IO LOSP 2 IO 3 3V Y N 3 3V IO pacer U5 B2 10 U5 30 31 B2 L05 N P6 IO LOSN 2 IO 3 3V Y Y 3 3V IO 2 IO LOOP V5 B2 L06 P 32 33 B2 IO V7 V7 10 IO 3 3V N Y 3 3V IO 2 CREE V6 B2 L06 N 34 35 3 3 V 3 3V 36 37 B2 L07 N P7 IO LO7N 2 IO 3 3V Y N 3 3V IO 10 U6 B2 IO U6 38 39 B2 LO7P N7 IO L07P 2 IO 3 3V Y Y 3 3V IO 3 Fri L5 B3 L17N 40 IO L12N 41 B2 GCLK12 M9 D6 2 1 33VN Y 33V IO 3 IO L17P L6 B3 L17P 42 GCLK12 43 GND GND 44 45 B2 L10 N T8 IO LION 2 IO 333V Y N3 3V I 2 IP Losp 17 B2 IP 17 46 47 B2 L10 P RS IO LIOP 2 IO 3 3V Y N3 3V I 2 IP L11P US B2 IP U8 48 IO L13N 49 B2 GCLK L13 N V9 D3 2 103 3V Y Y 3 3V IO 3 IO L1I19P M5 B3 L19 P 50 GCLK15 IO L13P 51 B2 GCLK L13P U9 D4 2 IO 33VY Y 3 3V IO 3 IO L19N M6 B3 L19N 52 GCLK14 53 2 5 V 3 3 V 25V 54 5 B2 L18 N N11 IO LI8N 2 10 3 3V Y Y 3 3V IO 2 IO LOOP P8 B2 L09 P 56 57 B2 L18 P P11 IO L18P 2 IO 3 3V Y Y 3 3V IO 2 IO LO9N N8 B2 L09 N 58 59 B2 L20N R12 IO L20N 2 10 33VY N 33VIO 2 IO PO B2 IO P9 60 61 B2 L20 P T12 IO L20P 2 IO 3 3V Y
8. Generic USB Device has been added Ger te Manager Datei Aktion Ansicht amp amp R Ra BR Prozessoren See Speichervolumes 9 Systemger te gt Tastaturen Ih USB Controller gt CA 200 E Cypress Generic USB Device amp Intel R ICHS Family USB Universal Host Controller 2830 2 Intel R ICHS Family USB Universal Host Controller 2831 amp Intel R ICHS Family USB Universal Host Controller 2832 amp Intel R ICHS Family USB Universal Host Controller 2834 C amp Intel R ICHS Family USB Universal Host Controller 2835 CS Intel R ICHS Family USB2 Enhanced Host Controller 2836 2 Intel R ICHS Family USB2 Enhanced Host Controller 2834 2 USB Root Hub 2 USB Root Hub gt USB Root Hub 2 USB Root Hub 2 USB Root Hub gt USB Root Hub 2 USB Root Hub Now the USB microcontroller can be ac cessed from the host computer through dedicated software Trenz Electronic GmbH User Manual EZ USB FX2 EEPROM Programming First of all check that S1 is actually switched to EEPROM The USB EEPROM can be programmed by opening the dedicated software Cypress USB Console double click the CyCon sole exe file in the 1st_program CyCon sole folder 7 Cypress USB Console File Options Help n el a a DI Selected Script Select Device Address Name in Windows Device Mar from inf USB Device Cypress Generic USB Device Device Properties Control Endpt
9. S2 S2 enables disables the reset line The reset line available also on 2 contacts of the B2B connector resets the USB micro controller and the FPGA S2 has to be turned off Reset if the user wants to program the SPI Flash memory in direct mode For programming the SPI Flash memory in indirect mode over JTAG S2 has to be turned on Run Run on system running Reset off system reset Table 8 S2 default Run For further information please read para graph Software Configuration DIP Switch S3 S3 conditionally unconditionally enables the 1 2 V and 2 5 V power rails When S3 is turned on the 1 2 V and 2 5 V power rails are controlled by the USB microcontroller At start up the USB mi User Manual Spartan 3E FPGA Industrial Micromodule crocontroller switches off the 1 2 V and 2 5 V power rails and starts up the mod ule in low power mode After enumera tion the USB microcontroller firmware switches the 1 2 V and 2 5 V power rails on if enough current is available from the USB bus When S3 is turned off the 1 2 V and 2 5 V power rails are always enabled FX2 PON on rails controlled by FX2 PON off rails always enabled Table 9 S3 default FX2 PON The 3 3 V power rail though is out of the control of the USB microcontroller and is supplied down converting the 5 V power supply provided by either the USB bus or the B2B receptacle connecto
10. e g Xilinx Chip Scope Xilinx Microprocessor Debugger The SPI interface allows a fast frequent and non volatile configuration of the TEO300 module Configuration of the TEO300 module through a USB host is recommended for occasional non volatile on site opera tions such as firmware upgrade System Requirements TEO300 modules can be configured through a host computer with the follow ing system requirements m Operating system Microsoft Windows 2000 Microsoft Windows XP Microsoft Vista m Xilinx ISE 10 1 or later for indirect SPI in system programming see Xilinx An swer AR 25377 m Xilinx EDK for some reference designs m Interface USB host m JTAG SPI USB cable with flying leads EZ USB FX2 Microcontroller Firmware If the EEPROM has never been pro grammed before virgin board S1 can be switched to EEPROM The USB micro 10 Spartan 3E FPGA Industrial Micromodule controller will detect an empty EEPROM and will provide its default vendor ID and device ID to the USB host DIP on left off right switch S1 EEPROM 52 Run S3 X X S4 X X If the EEPROM has been programmed be fore EEPROM not empty S1 must be Switched to Off The USB microcontroller will detect a missing EEPROM and will provide its default vendor ID and device ID to the USB host DIP on left off right switch S1 Off S2 Run S3 X X S4 X X Generic USB Micro
11. ohm to ad jacent connector pins These lines can be used for high speed signaling up to 666 Mbit s per differential pair see Xilinx Application Note XAPP485 User Button and LED LED The LED is lit when the U_LED line pin R10 is set high as detailed in the follow ing table Signal FPGA pin FPGA ball IO L15P 2 U LED bank 2 R10 Tabelle 5 user led signal details Push Button The push button is connected to the PB input pin V16 as detailed in the follow ing table Signal FPGA pin FPGA ball IP PB bank 2 V16 Tabelle 6 user button signal details The input is normally low The input is pulled up when pressed Configuration Switches The micromodule hosts 4 DIP switches on the top side S1 S2 S3 and S4 For customers requesting a sufficient amount of units the micromodules can be manufactured replacing the switches by fixed connections Trenz Electronic GmbH User Manual DIP Switch S1 S1 enables disables the communication between the Cypress EZ USB FX2 micro controller and the I2C CMOS Serial EEP ROM Turn S1 off when programming the USB EEPROM storing the USB vendor ID and device ID This will force the USB micro controller to provide its default vendor ID and device ID EEPROM on EEPROM enabled Off off EEPROM disabled Table 7 Si default EEPROM For further information please read para graph Software Configuration DIP Switch
12. present on the module STMicro electronics M25P32 in the example a 32 Mbit 4M x 8 Serial Flash memory Trenz Electronic GmbH User Manual E FPGA SP Flash Association Select SPI Flash FPGA SPI Flash acd 200e M25P32 IMPACT should now look like this EL iMPACT Boundary Scan 9 File Edt View Cpe atons Gutput Debug Wndaw Help AREA uw x dary Scar O slaveseral a Select AP gt Gct Di Signaturo Usercode SD coletop Zanficuration mp Lhezt Idcoda Sart SFI Fnaligrat rn me Fra Status Regen SystemacCL B PRUM Fie Fecrmatter res Ceb e ccnnecticn Firmwarc versicn 1302 File vers ua U Ci Sil_us 10 1 ISE date susb_xlp usx 1302 Firmware hex T3 e versenn SI jpc CxO004 N upLiun 20C0047B45B701 Ir earn IM Wh ve reion 0012h PFOGRESZ_END Ind Crerazicn Klapsed tome z ser Attempting gt identify devices in the kcundary scan chain conZiguration 2 177 3ATCH CMD Idert z PROGRESS START 5 Gperaticn Icentifying he n zortenzs 1 Msnulascturer s ID X112nx xc3s1z20Ce Version 0 INFO iMFACT 1777 ading Ci Xilinx 10 1 ISE spartarle data xc e1200 ksd INFO 1MFACT SOl 1 Added Device x 38 12008 su Efu v gt Confgraticn PatformCeble USDC Millz usbrhs Right click the Flash device and select the Program operation SEIE BHAHAPEX SF Ra i Fluwy SelGiect SFI faniga SystemaCL B PRUM Fi
13. D Vref 3 3 V Table 11 JTAG header J2 SPI Header SPI signals are routed to from bank 2 of the FPGA as detailed in Table 12 and made available on the dedicated header J3 accessible through an SPI programmer with flying leads as described in Table 13 Trenz Electronic GmbH User Manual Signal FPGA pin FPGA ball SPI S IO_LO1P_2 U3 SPI D IO_LO3N_2 T4 SPI Q IO L16N 2 N10 SPI C IO L26N 2 U16 Table 12 SPI signal details bank 2 SPI S SPI D SPIQ SPI C GND Vref 3 3 V Table 13 SPI header J3 Spartan 3E FPGA Industrial Micromodule Clock Networks 24 MHz Clock Oscillator The module has a 24 MHz SMD clock os cillator providing a clock source for both the USB microcontroller and the FPGA as detailed in Table 14 Signal FPGA pin FPGA ball IO L12P 2 24MHZ1 bank 2 N9 Table 14 24 MHz clock signal details Main Clock Oscillator The module has a main SMD clock oscil lator providing a clock source for the FPGA as detailed in Table 15 Signal FPGA pin FPGA ball 100MHZ GCLKO U10 125MHZ bank 2 Table 15 main clock signal details Standard frequencies are 100 MHz and 125 MHz please visit Trenz Electronic website for current ordering information The lower the main clock frequency the lower the module power consumption Moreover as the main clock is preferably used as DDR SDRAM clock a lower clock frequency makes easier for the de
14. I flying leads cable and the USB cable Start Xilinx ISE iMPACT The following ex ample shows the case of iMPACT 9 2 If the iMPACT Project window pops up press the Cancel button 18 Spartan 3E FPGA Industrial Micromodule iMPACT Project want to v Browse C Load most recent project file when iMPACT starts create a new project ipf default jpf Browse Cancel Double click the Direct SPI Configura tion option in the Modes panel File Edt view Cgeratiors Optiors Outpu Desug Window Help IPR IEEE IEEE i SHO ew Right click the Direct SPI Configuration panel to add a device and select Add SPI Device Fie Edit Yisw Operacions Opzions Du pit Debug Widow Help IPR ABER SRN i SSO wv Flnwz X ee x waBaundarv 3 gt 3n al Deskto Corfiguraion Ba Direct SPI Corfigaretion Right diuk Ls A 44 De vive ur Idenili v Device 5 1 5 5 tem l 2 PRON Fle Fomrette Weleme 23 1HPACT ftt BATCH CMD gatNod spi DATCH CMD s tMod spi Trenz Electronic GmbH User Manual You can now select the file corresponding to your device In the following example we will show how to select the micromod ule reference device blinking mcs in the TEO300 folder Add Device Suchen in E TEO300 e 1 Fa o blink1600 mcs Zuletzt O 1st_program verwendete D Desktop Eig
15. L12 P B10 GCLK6 O IO VccIO Y GND 46 47 GCLK L12 N A10 Te IO VccIO Y Y VccIO IO O IO LO9N Dili BO LO9 N 48 49 BO L15 P E9 IO L15P 0 IO VccIO Y Y VccIO IO O IO LOOP Cii BO LO9 P 50 51 BO L15 N F9 IO L15N 0 IO VccIO Y N VccIO IO O IO All B0 IO All 52 53 2 5 V 2 5 V 54 55 BO LO8_ P E11 IO LO8P 0 IO VccIO Y N VccIO IO O IO VREF Bii B0 IO B11 56 57 BO L08 N F11 IO LO8P O IO VccIO Y N VccIO IO O IO A12 BO IO A12 58 59 BO LO5_P A13 IO LO5P 0 IO VccIO Y Y VccIO IO O IO LO6P F12 BO LO6 P 60 61 BO LO5 N B13 REO O IO VccIO Y Y VccIO IO O IO LOGN E12 BO L06 N 62 63 GND GND 64 65 BO LO4 N A14 IO LO4N 0 IO VccIO Y N VcclO IO 0 IO D13 BO IO D13 66 67 B0 LO4 P B14 IO LO4P 0 IO VccIO Y N VcclO IO 0 IO E13 B0 IO E13 68 69 BO LO3N C14 Ar O IOVccI0 Y 33V 1 2 TDI a2 TDI 70 71 BO LO3 P D14 IO LO3P 0 IO VccIO Y 3 3V 02 TDO C16 TDO 72 73 1 2 V 1 2 V 74 75 BO LO1 N A16 IO LOIN O IO VccIO Y 3 3V I 2 TCK A17 TCK 76 77 B0 LOi P B16 IO LO1P 0 IO VcclO Y 33VW I 2 TMS D15 TMS 78 79 GND GND 80 receptacle connector J4 pinout information FPGA FPGA ba ba FPGA FPGA B2B E dir dir pin name nk nk name pin name 1 5Vb2b I I 5Vb2b 2 3 5Vb2b I I 5Vb2b 4 5 5V O I MR 6 7 B2B D P IO Y O RESET 8 9 B2B D N IO Y O RESET 10 11 GND GND 12 13 B3 L22 P P3 10 L22P 3 IO 3 3V Y N3 3V IO 3 IO L24P T2 B3 IO T2
16. N 33VIO 2 10 Ri B2 IO Rll 62 63 GND GND 64 IO L19N IO L15N 65 B2L9N vi3 IO 2 103 3V Y N 33V IO 2 D1 P10 B2 IO P10 66 VREF GCLK3 67 B2 L19 P V12 IO L19P 2 10 3 3V Y N 33V IO 2 Fe R9 B2 IO R9 68 69 B2 L22 N R13 TON 2 IO 33V Y Y 3 3V IO 2 IO L21N P12 B2L21 N 70 71 B2122P P13 Eea 2 IO 3 3V Y Y 3 3V IO 2 IO L21P N12 B2 L21 P 72 73 1 2 V 12V 74 IO L24P 75 B2124P T14 a 2 103 3V Y N3 3V 1 2 IPL23P V14 B2 IP V14 76 IO L24N 77 B2124N R14 co 2 103 3VYN3 3VI0 2 IO U13 B2 IO U13 78 79 GND GND 380 receptacle connector J5 pinout information
17. Such und Installationsoptionen Verwenden Sie die Kontrollk stchen um die Standardsuche zu erweitern oder einzuschr nken Lokale Pfade und Wechselmedien sind in der Standardsuche mit einbegriffen Der zutreffendste Treiber wird installiert _ Wechselmedien durchsuchen Diskette CD Folgende Quelle ebenfalls durchsuchen CATEO3004 driver v Durchsuchen Nicht suchen sondern den zu installierenden Treiber selbst w hlen Verwenden Sie diese Option um einen Geratetreiber aus einer Liste zu w hlen Es wird nicht garantiert dass der von Ihnen gew hlte Treiber der Hardware am besten entspricht Casa Trenz Electronic GmbH User Manual Assistent f r das Suchen neuer Hardware Fertigstellen des Assistenten Die Software f r die folgende Hardware wurde installiert gt DEWESoft USB Device Klicken Sie auf Fertig stellen um den Vorgang abzuschlie en Check that in the Device Manager under USB Controller the DEWESoft USB Device 0 has been added Ger te Manager Datei Aktion Ansicht gt gt asp2 3 Prozessoren 9 Speichervolumes Systemger te Tastaturen USB Controller gt CA 200 DEWESoft USB Device 0 amp Intel R ICHS Family USB Universal Host Controller 2830 6 Intel R ICHS Family USB Universal Host Controller 2831 CS Intel R ICHS Family USB Universal Host Controller 2832 C amp Intel R ICHS Family USB Universal Host Contro
18. X PON position In case you uploaded the reference design you should see the on board led blinking at 0 5 Hz For further information about indirect SPI over JTAG in system programming of SPI Flash memories please see Xilinx Application Note XAPP974 Indirect Pro gramming of SPI Serial Flash PROMs with Spartan 3A FPGAs Changes from TEO300 00 to TEO300 01 Clocks TEO300 00 has a 50MHz secondary clock whereas TEO300 01 has a 125MHz sec ondary clock Volatile Memory Interface TEO300 00 could access the DDR SDRAM only with Xilinx OPB on chip peripheral bus cores TEO300 01 can also access the DDR SDRAM through the dedicated Xilinx MIG memory interface generator memory in terface 23 Spartan 3E FPGA Industrial Micromodule B2B Connectors Contact 14 of connector J5 has been ex tended from an input in TEO300 00 to an I O in TEO300 01 Therefore hardware designs developed for the TEO300 00 are compatible with the TEO300 01 whereas those developed for the TEO300 01 are compatible with the TEO300 00 if that contact is configured as input Contact 76 of connector J5 has mis takenly been described as I O in TEO300 OO but it has always been an input only contact as documented for TEO300 01 Connector J4 has not been changed LED With TEO300 00 the LED is lit when the U_LED line on pin T15 is set high whereas with TEO300 01 the LED is lit when the U_LED line on pin R10 is set high Ordering Inf
19. Xters Other Endpt Xters Misc WendorlD 0x04B 4 ProductlD OXFF Manufacturer Protocol OxFF Product bedDevice 0 4001 Serial Number Device Configurations 1 Attributes 0x01 0x80 0x32 100 m Configuration Interfaces 4 inte tt seting Clese_ __ Subciass__ Pee OxFF Vendor OxFF OxFF Wendor OxFF OxFF Wendor OxFF Interface Endpoints 0 Max Pkt Size Click Options gt EZ USB Interface to Open EZ USB Interface window 12 Spartan 3E FPGA Industrial Micromodule 7 EZ USB Interface Device USE Device EEES ed Get Dev Get Conf Get Pipes Get Strings Download Re Load Ec testi URB Stat HOLD RUN vend Req Req 0x00 Yalue 0x0000 Index 0x0000 Length jo Dir o OUT y Hex Bytes CO B4 04 81 00 01 00 y o Trans Pipe Po l Length 1128 Packet Size I Packets Bulk Trar Pef i Length 64 Hex Bytes man Reset Pipe Abort Pipe File Trans Pipe mm Set IFace Interface 0 AltSetting jo S EEPROM button refers to the small EEPROM 256 bytes whereas the Lg EE PROM refers to the large EEPROM 64 kB Press the Lg EEPROM button se lect the USB iic file and press the Open button to start writing to EEPROM Large 512 64K byte EEPROM Download Suchen in ea TEO300 e amp ex Ed driver EP i cyConsole Zuletzt verwendete D Desktop Eigene Dateien Pr Arbeitsplatz Dateiname fusb iic
20. acle The ordering numbers of the connector receptacles are given in Table 1 supplier header Digikey H2373CT ND Hirose DF17 3 0 080DS 0 5V 51 Trenz Electronic 22684 Table 1 equivalent part numbers of the receptacle connectors J4 and J5 The on board receptacles mate with their corresponding headers on the carrier board Figure 6 Figure 6 mating header The ordering number of the headers is given in Table 2 Trenz Electronic GmbH User Manual supplier header Digikey H2407CT ND Hirose DF17 4 0 80DP 0 5V 51 Trenz Electronic 22938 Table 2 equivalent part numbers of the mating connectors Figure 7 shows the definition of stacking height featured by the combination of the TEO300 receptacle with its corresponding header Receptacle Header Figure 7 stacking height h The stacking height of the TEO300 B2B connectors is 7 seven mm The stacking height does not include the solder paste thickness USB Connector The micromodule uses a mini USB B type receptacle connector Figure 8 mini USB B type recept acle connector Spartan 3E FPGA Industrial Micromodule Power Supply The module can be powered by the B2B connector or the USB connector If both power supplies are available the B2B connector power supply takes preced ence disabling the USB power supply automatically B2B Connector Power Supply The B2B connector power supply r
21. al of 110 FPGA user I Os are avail able on corresponding contacts of B2B connectors J4 and J5 see Appedix m 3 7 differential digital I O pairs each pair is configurable as 2 single ended digital I Os corresponding to a maximum of 74 single ended digital I Os m 4 differential clock input pairs each pair is configurable as differential digital I O pair or 2 single ended clock inputs or 2 single ended digital I Os or combination thereof correspond ing to from a maximum of 8 independ ent clock inputs to a maximum of 8 in dependent digital I Os m 1 differential clock input pair the pair is configurable as differential digital input pair or as 2 single ended clock inputs or 2 single ended digital inputs or combination thereof cor responding to from a maximum of 2 independent clock inputs to a maxim um of 2 independent digital inputs m 21 single ended digital I Os m 5 single ended inputs Table 4 summarizes the maximum avail able FPGA user I Os divided by supply voltage type VccIO 3 3V diff I O pairs lt 18 lt 23 diff inputs lt 1 none diff clocks lt 4 lt 1 s I Os lt 46 lt 58 s e inputs lt 2 lt 4 s e cloks lt 8 lt 3 Table 4 maximum FPGA user 1 Os by supply voltage Spartan 3E FPGA Industrial Micromodule Differential Pairs The micromodule has a total of 42 differ ential signal pairs routed pairwise with a differential impedance of 100
22. an 3E FPGA Industrial Micromodule Applications IP intellectual property development Digital signal processing Image processing Cryptography Industrial control Low power design General purpose prototyping platform Description The FPGA industrial micromodule integ rates a leading edge Xilinx Spartan 3E FPGA an USB 2 0 microcontroller config uration Flash DDR SDRAM and power Supplies on a tiny footprint A large num ber of configurable I Os are provided via B2B mini connectors The module is intended to be used as an OEM board or to be combined with our carrier boards It is a powerful system widely used for educational and research activities Boards with other configurations larger FPGA s or equipped with industrial tem perature grade parts are available on re quest Software for SPI flash programming over USB as well as reference designs for high speed data transfer over USB are in cluded Physical Features Board Dimensions The module measures 40 50 mm by 47 50 mm Trenz Electronic GmbH User Manual 23 25 e EN LO e 59 o Ba top view LO o a O 0 Figure 3 module dimensions in mm top view Board to Board Connectors Figure 4 connector receptacles J4 and J5 bottom view The module has two B2B board to board receptacle connectors J4 and J5 for a total of 160 contacts Figure 5 Spartan 3E FPGA Industrial Micromodule Figure 5 micromodule recept
23. controller Driver installation If the USB microcontroller Cypress EZ ESB FX2 driver is not installed on the host computer then the easiest way to do it is the following m disconnect the micromobule or leave the micromodule unconnected configure the micromodule such that the USB microcontroller will provide its default vendor ID and device ID to the USB host i e S1 OFF see para graph EZ USB FX2 Microcontroller Firmware connect the micromodule to the host computer through the USB interface Trenz Electronic GmbH User Manual m wait until the operating system detects new hardware and starts the hardware assistant m if Si is not already switched to EEP ROM do it now m answer the hardware assistant ques tions as shown in the following ex ample Assistent f r das Suchen neuer Hardware Willkommen Mit diesem Assistenten konnen Sie Software fur die folgende Hardwarekomponente installieren USB Device C Falls die Hardwarekomponente mit einer CD oder Diskette geliefert wurde legen Sie diese gt jetzt ein Wie mochten Sie vorgehen Software automatisch installieren empfohlen Klicken Sie auf weiter um den Vorgang fortzusetzen Assistent f r das Suchen neuer Hardware Wahlen Sie die Such und Installationsoptionen SS I Diese Quellen nach dem zutreffendsten Treiber durchsuchen Verwenden Sie die Kontrollk stchen um die Standardsuche zu erweitern o
24. der einzuschr nken Lokale Pfade und Wechselmedien sind in der Standardsuche mit einbegriffen Der zutreffendste Treiber wird installiert Wechselmedien durchsuchen Diskette CD Folgende Quelle ebenfalls durchsuchen CATEOSO0 driver Nicht suchen sondern den zu installierenden Treiber selbst w hlen Verwenden Sie diese Option um einen Geratetreiber aus einer Liste zu w hlen Es wird nicht garantiert dass der von Ihnen gew hlte Treiber der Hardware am besten entspricht 11 Spartan 3E FPGA Industrial Micromodule Hardwareinstallation Die Software die f r diese Hardware installiert wird Cypress Generic USB Device hat den W indows Logo T est nicht bestanden der die Kompatibilit t mit Windows XP berpr ft Warum ist dieser Test wichtig Das Fortsetzen der Installation dieser Software kann die korrekte Funktion des Systems direkt oder in Zukunft beeintr chtigen Microsoft empfiehlt strengstens die Installation jetzt abzubrechen und sich mit dem Hardwarehersteller f r Software die den Windows Logo Test bestanden hat in Verbindung zu setzen Installation fortsetzen Installation abbrechen Assistent f r das Suchen neuer Hardware Fertigstellen des Assistenten Die Software f r die folgende Hardware wurde installiert Cypress Generic USB Device Klicken Sie auf Fertig stellen um den Yorgang abzuschlie en Check that in the Device Manager under USB Controller the Cypress
25. e Fermatter 4 Losding file E TEO3CO blinkin wce ine INTO iMFACT E assec time 0 ssc rne FF ss amp ELTCH CED set toribute positicn 1 sttr packagaNsme vslue fr In the Device Programming Properties window just leave the default settings and press the OK button 22 Spartan 3E FPGA Industrial Micromodule Device Programming Properties Device 1 Programming Properties uNndary scan ice 1 FPGA xc3s1200e ice 1 Attached FLASH M25P32 Property Name Value CPLD And PROM Properties Erase Before Programming FPGA Device Specific Programming Properties Assert Cable INIT during programming After programming Flash automatically load FPGA with currently assigned bitst IMPACT will first erase the memory E Progress Dialog 1 Executing command i Cancel and then write it Cancel After successful programming you should read the message Program Succeeded popping up for a few seconds in the Boundary Scan panel Trenz Electronic GmbH User Manual impact Boundary Scan Statu gister values A CT C011 011 10C1 1030 0003 000 3C00 00C INFO iMTACT 570 11 Corgletca dowalocd ng kit file to dew ec FO CT _ Checking done rin done 1 Pregrammec surcessZully PROGRESS END End Crerasien Elaps d toe 61 sev Confgraticn PatformCeble USDC Milz usbrhs Switch S3 back to the F
26. ene Dateien Arbeitsplatz Netzwerkumgeb Dateiname biinkin mes ung Dateityp an Design Files mes exo Abbrechen A Select the part name corresponding to the SPI flash present on the module STMicroelectronics M25P32 a 32 Mbit 4M x 8 Serial Flash memory B Select Device Part Name Select PROM Part Name Cancel IMPACT should now look like this 19 Spartan 3E FPGA Industrial Micromodule IMPACT Direct SP Configuration HER P Fie Edit Yisw Operations Opzions Oucput Debug Wndow Help EPR AG AC SRG HI SHO wie el Baundary 323n Avaiki Operalivr x are EMS avsi sial 22 5 2fecIMAP elDeskto Corfiguraiion D Bh Direct SPI Corfiguetion E Stema k sn mz9032 3 P30M Fle Fonrette pinkin mes MEO Mudes Operstiuns Welcome 23 10PacT Zi BATCH CMD gatNod spi ff DATCH CMD s tMod spi Selevred part MAHPHZ INFO iNPAST 501 11 Added Dovice M25P32 ouezcoozally Pines SP Panfc raten Loadirg Zilc 2 TEO3CO blirkin mco INFO 1NPAZT Elspsei tima 0 sec cone ff DATCHO CMD set tzceibut position 1 attr packageNeme value 2 IR hi Jupit ro Warning No Cable Connection Right click the SPI PROM device and se lect the Program operation E IMPACT Direct SP Configuration HER Fie Edit Yisw Operacions Dpzions Ducprt Debug Wrdow Help El 46 Gx see x TB undam 3 gt 3n Arailss
27. equires a single nominal 5 V DC power supply The power is usually supplied to the mod ule through the 5 V contacts 5Vb2b of the B2B connectors J5 see Appendix The recommended minimum supply voltage is 4V The maximum supply voltage is 5 5 V The recommended max imum continuous supply current is 1 5 A USB Power Supply The module is powered by the USB con nector if the following conditions are met m the module is equipped with an USB connector m the module is connected to a USB bus no power supply is provided by the B2B connectors In this case other components e g ex tension or carrier boards may also be powered by the corresponding 5 Volt line 5V of the B2B connector J5 On board Power Rails Three on board voltage regulators provide the following power supply rails needed by the components on the micro module m 1 2V 1A max m 2 5V 1 A max m 3 3 V 1 A max The power rails are available for the FPGA and can be shared with a baseboard by the corresponding lines of the B2B con Trenz Electronic GmbH User Manual nectors J4 and J5 Please note that the power consumption of the FPGA is highly dependent on the design actu ally loaded So please use a tool like Xil inx Xpower to determine the expected power consumption Even if the provided voltages of the mod ule are not used on the baseboard it is recommended to bypass them to ground with 10 nF 100 nF capacitors I O Banks Power Supply
28. he File name field and select for in stance the sample firmware upload file TEO300_v1012 fwu in the USB FWUTool FWUs folder Suchen in FwUs af TE0300_v0812 Fwu Zuletzt verwendete D Desktop Eigene Dateien Arbeitsplatz TE0300_v0812 fwu y Dateityp Fw Update Files fwu v Abbrechen D Netzwerkumgeb Dateiname un gt USB Firmware Upgrade Tool Device USB Device File name TEO300 SBFWUToolFwUs TEOS00_v1012 Upload Yersion 7 6 Trenz Electronic GmbH User Manual Press the Upload button to upload the micromodule firmware and check the FPGA uploading progress bar USB Firmware Upgrade Tool USE Device FPGA uploading 223 Yersion 2 6 After successful completion of the firm ware upload procedure the following message should pop up USB Firmware Upgrade Tool E Firmware upgrade successfull Reboot the micromodule with the new firmware by disconnecting and reconnect ing the USB cable You may want to test the sample application TEO300_API_Ex ample exe in the TEO300_API_Example Debug folder To generate your own firmware upload file please read the document Generat ing _FWU_file doc in the USBFWUTool folder SPI Direct In System Programming ISP Make sure S2 is switched to Reset off during programming Connect the host computer to the micro module through both the SP
29. iMPACT Welcome to iMPACT i 51 xj Please select an action from the list below C Configure devices using Boundary Scan JT AG Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File C Configure devices using Slave Serial mode Select BIN as output g iMPACT Prepare PROM Files 51 xj want to target a e ilins PROM Generic Parallel PROM 3rd Party SPI PROM C PROM Supporting Multiple Design Versions Spartan3E MultiBoot PROM File Format MCS BIER UFP C format C EXO BIN C ISC C HEX ja Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name lipga Location Cilia Browse lt Back nw Cancel Set PROM File Name to fpga and change Location to a suitable name and location 15 Spartan 3E FPGA Industrial Micromodule E iMPACT Specify Xilinx PROM Device v SP pe cpt ees F Enable Revisionina Number of Revisions a J Enable Compression a Add rj Part flan Check Auto Select PROM Add Device x i a Navigate to your project s IMPLEMENTA TION folder and select download bit Trenz Electronic GmbH User Manual Add Device Sopb_intc_0_wrapper O chipscope_icon_0_wrapper rs232_wrapper O chipscope_opb_iba_O_wrapper sdram_16mx16_wrapper G dcm_0_wrapper Ospi_adc_0_wrapper dem_1_wrapper Ospi_mon_0_wrapper
30. k Operaliur s are I Boonen i GalSekecIMar il Verify e Desk Corfiguraion N Erste BI Direct SP Corfigaretion gt blark Check Rlank Crerk a S etem lz w Fesdyack A Readkecs PROM Fle Foratte nan mea MSG Operaliuns Fire SP Canficuraten welcome gt gt 1MPACT ff BATCH CMD gatNod spi ff DATCI CMD sstNods spi Selected part MZ5P32 INFO iNPAST 501 L Addcd Doviec M25P32 ouezcooially Acsigr New Cerfigurston Fila to Loading file 2 TEO3CO blirkin mco IHTO 1NPALT Elspse3 tim 0 sec cone ff DATCHO CMD set tzcibut position 1 attr packageNeme value A lt z Jupet Zro I yanina No Cable Connection In the Programming Properties window just leave the default settings and press the OK button E Programming Properties Category Programming Properties Advanced PROM Programming Properties Revision Properties Verify General CPLD And PROM Properties Erase Before Programming Read Protect PROM CoolRunner II Usercode 8 Hex Digits CPLD Specific Properties Write Protect Functional Test On The Fly Program APLA UES Enter up to 13 characters PROM Specific Properties Load FPGA Parallel Mode Use D4 for CF Spartan34N Programming Properties Data Protect Data Lockdown FPGA Device Specific Programming Properties Pulse PROG Program Key C Assert Cable INIT during programming Trenz Electronic G
31. ller 2834 C amp Intel R ICHS Family USB Universal Host Controller 2835 2 Intel R ICHS Family USB2 Enhanced Host Controller 2836 2 Intel R ICHS Family USB2 Enhanced Host Controller 2834 2 USB Root Hub 2 USB Root Hub 6 USB Root Hub 2 USB Root Hub 2 USB Root Hub gt USB Root Hub gt USB Root Hub FWU File Generation The TEO300 micromodule can be con figured by means of a firmware upgrade FWU file see next section Micromodule Configuration for further reference The first step in generating the FWU file is to generate the fpga bin file corresponding to a given FPGA design 14 Spartan 3E FPGA Industrial Micromodule The TEO300 reference projects provide a way to generate the fpga bin file in an automatic way i e by executing the fol lowing batch file XilinxEdkReferenceProject PREPARE_FW TEO300_usb_fw bat where XilinxEdkReferenceProject is the base directory of the corresponding reference project Alternatively you can use Xilinx IMPACT from Start Programs Xilinx ISE Ac cessories Impact Select create new project EL iMPACT Project xj want to pornenenconcncacenconencnnonencononenconenrenenconenencros C iload most recent project default ipf Load most recent project file when iMPACT starts create a new project ipf default ipf Browse OK Cancel Select prepare PROM file Trenz Electronic GmbH User Manual e
32. mbH User Manual IMPACT will first erase the memory no tice the mismatch between the two pro gress indicators Progress Dialog 61 Executing command Cancel and then write it notice the match between the two progress indicators Progress Dialog 10 Executing command Cancel After successful programming you should read the message Program Succeeded popping up for a few seconds in the Dir ect SPI Configuration panel g iMPACT Direct SPI Configuration Up File Edt View Cperatons Gutput Window Help SB BRAM SRM 0123303 N F2 Dourday Scar Avail Opcratore are o Slaveseral gt Frogram a Selevtv AP gt Verily SD coltop Zanficuratioa mhtrase ESDiert SFI Enaligurat on Blar k Check SystemaCE gt F eadach SS ro PRUM H skermalter binl r mz B whl Program Succeeded Moon Anerainrs E Unect 32 Lontguraton Zr nl Tevire validated successfully 11 Ercozng Devices PFOGRESZ_3TART 3LaLlL 1y Cpelalica 11 Prrgrammirg Jevine 1 Reeding deviez contenta Une 11t veritisatinan mmp Pen PROGRESS EN gt End Crerazicn Elaps d time 4C sec ff TUF LOCA CPD s Prograr p 1 e Y netaiitversinr II Validating davice 1 IDCODE is 202016 ir hex 1 ID Check rass d Tevize validated successfully 1 Cresing Devics PFOGRESZ_START Scarting Operacicn 111 Pregrammirg Javice 1 Receding deviez contento
33. on 22 Direct SPI Configuration xcf02s xc3s400 dowenload bit ix PROM File Generation Succeeded Dperations E Eb PROM File Formatter amp Writing file C Xilinx fpga prm Writing file C Xilinx fpga sig PROM File Generation Target Xilinx PROM 1 699 136 Bits used File fpga in Location C xilinx Y Don t forget to save your project for fur ther use Once you have got your fpga in file you can proceed and generate your FWU file The FWU file is a ZIP file containing 3 files m Bootload ini booting settings m fpga bin FPGA programming file m usb bin FX2 firmware To create your FWU file you need to m replace the existing USBFWUTool FWUs fpga bin with the latest fpga bin Bootload ini and us b bin are always unchanged m zip the 3 files m change the zip file extension to fwu upload the file as explained in the next section Micromodule Configuration 17 Spartan 3E FPGA Industrial Micromodule Micromodule Configuration The micromodule can now be pro grammed with its dedicated firmware up load tool Turn S1 S2 S3 and S4 on Open the dedicated firmware upgrade tool USB Firmware Upgrade Tool double click the USBFirmwareUpgrade Tool exe file in the USBFWUTool folder USB Firmware Upgrade Tool Device USB Device File name a Yersion 7 6 Press the button corresponding to t
34. ormation For the latest product details and avail able options please visit www trenz electronic de shop trenz electronic de Revision History Rev Date 1 06 2008 12 08 Who FDR User Manual Description DIP switches revised 1 07 2009 02 16 FDR fixed DIP switches overview picture 1 08 2009 03 09 FDR clarified warning regarding 3 3 V power rail 1 09 2009 03 16 FDR fixed and improved switch settings 2009 06 03 FDR added FWU File Generation sec tion 2009 07 23 FDR clarified changes LED section 2009 08 24 FDR added FPGA signal details for main user Signals 2009 09 01 FDR improved On board Memories chapter 2009 09 03 FDR improved clock memory and con figuration chapters Table 17 revision history Appendix Rev Date Who Description 0 1 2008 04 24 FDR created 1 0 2008 08 01 FDR completed 1 01 2008 08 08 TT 50MHz to 125MHz clock 1 02 2008 10 17 FDR U_LED for TEO300 00 1 03 2008 10 17 FDR updated FUT from 1 9 to 2 6 1 04 2008 10 27 FDR DIP switches overview 1 05 2008 10 29 FDR stacking height Trenz Electronic GmbH The following tables reports pin out in formation of B2B board to board re ceptacle connectors J4 and J5 respect ively 24
35. part_inf o fbga decoder Spartan 3E FPGA Industrial Micromodule When developing DDR SDRAM designs with Xilinx tools e g MIG MPMC you should select the following product type MT46V32M16 6 Should it be not available you can use one of the following product types MT46V32M16 5 MT46V32M16XX 5B MT46V32M16BN 5B MT46V32M16FN 5B MT46V32M16P 5B MT46V32M16TG 5B TEO300 modules with the following part numbers TEO300 00 TEO300 00 415C TEO300 00B TEO300 01 TEO300 01B TEO300 01BLP were assembled with Qimonda HYB25DC512160CF 6 512Mb DDR SDRAM components When developing DDR SDRAM designs with Xil inx tools you should select the following product type HYB25D512160BF 6 SPI Flah TEO300 modules have a STMicroelectronics M25P32 32 Mbit low voltage serial Flash memory with 75 MHz SPI bus interface for config uration and operating storage accessible through USB or SPI Serial EEPROM TEO300 modules have a Micron Technology 24LC128 Trenz Electronic GmbH User Manual 128K I2C CMOS Serial EEPROM for EZ USB FX2 firmware vendor ID and device ID storage accessible through the EZ USB FX2 microcontroller Module Configuration This section describes how to configure the TEO300 module and access some of its resources The JTAG interface allows a fast frequent but volatile configuration of the TEO300 module However only through the JTAG interface it is possible to develop and de bug with Xilinx tools
36. r In this case signals that are applied to the 3 3 V I O banks do not need to be disconnec ted when power rails are disabled by the USB microcontroller DIP Switch S4 S4 enables disables the FPGA configura tion through the SPI interface The FPGA configuration through the JTAG interface cannot be disabled When S4 is turned on the FPGA tries to configure from the SPI Flash memory The FPGA can be configured by the JTAG interface at any time When S4 is turned off the FPGA waits to be configured by the JTAG interface For further information about direct pure SPI indirect SPI over JTAG in system programming of SPI flash memories please see Xilinx Application Notes XAP P951 Configuring Xilinx FPGAs with SPI Trenz Electronic GmbH Serial Flash and XAPP974 Indirect Pro gramming of SPI Serial Flash PROMs with Spartan 3A FPGAs S4 position SPI on JTAG off FPGA configuration JTAG SPI FPGA configuration JTAG Table 10 S4 default SPI DIP Switches Overview Figure 11 summarizes functions and loca tion of the four DIP switches off PON S3 power rails on FX2 PON DIE 4 FPGA configuration _ Figure 11 DIP switches overview Spartan 3E FPGA Industrial Micromodule JTAG and SPI JTAG Header JTAG signals are available on the dedic ated header J2 through a JTAG program mer with flying leads as described in Table 11 TMS TDI TDO TCK GN
37. ratons gt tM SPERM REE T X J MPACT gt Lesse An Assign New Configuration File dialog window should pop up automatically You can now select the file corresponding to your design In the following example we will show how to select the micromodule reference design blinking bit in the TEO300 folder Do not forget to select the Enable Programming of SPI Flash Device Attached to this FPGA option in the same window 21 Spartan 3E FPGA Industrial Micromodule g Assign New Configuration File Look in E TE0300 O 1st_program 5 blinkin bit E blinkin1600 bit File name blinkin bit File type All Design Files bit rbt nky ise bsd v Cancel All O None Enable Programming of SPI Flash Device Attached to this FPGA Enable Programming of BPI Flash Device Attached to this FPGA An Add PROM File dialog window should pop up automatically You can now select the file corresponding to your design In the following example we will show how to select the micromodule reference design blinking mcs in the TEO300 folder Add PROM File Suchen in E temp_TE0300 e c E BUTS Zuletzt verwendete D Desktop Eigene Dateien Arbeitsplatz Netzwerkumgeb Dateiname ung blinkin mes gt Dateityp MCS Files mes v Abbrechen Select now the SPI Flash corresponding to the one
38. rocontroller is now ready to provide dedicated vendor 1D and device ID Wait until the operating sys tem detects new hardware and starts the hardware assistant and answer the hard ware assistant questions as shown in the following example 13 Spartan 3E FPGA Industrial Micromodule Assistent f r das Suchen neuer Hardware Willkommen Mit diesem Assistenten konnen Sie Software fur die folgende Hardwarekomponente installieren DeweSoft USB Device 5 Falls die Hardwarekomponente mit einer CD oder Diskette geliefert wurde legen Sie diese jetzt ein Wie m chten Sie vorgehen Software automatisch installieren empfohlen Software von einer Liste oder bestimmten Quelle installieren fur fortgeschrittene Benutzer i Klicken Sie auf Weiter um den Vorgang fortzusetzen Har dwareinstallation A Die Software die fur diese Hardware installiert wird DEWESoft USB Device hat den W indows Logo Test nicht bestanden der die Kompatibilit t mit Windows XP berpr ft Warum ist dieser Test wichtig Das Fortsetzen der Installation dieser Software kann die korrekte Funktion des Systems direkt oder in Zukunft beeintrachtigen Microsoft empfiehlt strengstens die Installation jetzt abzubrechen und sich mit dem Hardwarehersteller fur Software die den Windows Logo Test bestanden hat in Verbindung zu setzen Installation fortsetzen Installation abbrechen Assistent f r das Suchen neuer Hardware Wahlen Sie die
39. velop ment tools to meet the timing require ments particularly for DDR SDRAM For customized boards this clock can be changed according to user requirements Interface Clock IFCLK The IFCLK line synchronizes the commu nication between the USB microcontroller and bank3 of the FPGA as detailed in Table 16 Trenz Electronic GmbH User Manual Signal FPGA pin FPGA ball LHCLK5 IFCLK bank 3 K4 Table 16 interface clock signal de tails bank 3 Digital Clock Manager DCM The DCMs of the FPGA can be used to synthesize arbitrary clock frequencies from any on board clock network differ ential clock input pair or single ended clock input For further reference please read Xilinx data sheet DS485 Digital Clock Manager DCM Module dcm_module pdf and Xilinx application note XAPP462 Using Digital Clock Man agers DCMs in Spartan 3 FPGAs xap p462 pdf On board Memories The TEO300 has three on board memor ies m DDR SDRAM m SPI Flash m serial EEPROM DDR SDRAM TEO300 modules have a 512Mb DDR SDRAM component for operation code and data accessible through the FPGA Commercial grade modules mount the following component Micron Technology MT46V32M16BN 6 Industrial grade modules mount the fol lowing component Micron Technology MT46V32M16BN 6 IT You can get the exact part number of the component mounted on your module from the Micron FBGA decoder http www micron com support
Download Pdf Manuals
Related Search