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USER`S MANUAL - SeekDataSheet

1. DA DEC tes eerta e erede DECW Decrement DI Disable Interrupts DIV Divide Unsigned a MER RRDIBBICIBIZMUIPBIILIBBMAD DJNZ Decrement and Jump if Non Zero ssssssse EI Enable Enter EXIUS cedet A A IDLE Idle Operation tenn oet oon Detox DU DD Ee INC aei INCW increment ope ocv e c IRET JP SR cu nD JR Jump Relative 2 LD M ML LDB irons eerie cate cee DL en S3P80C5 C80C5 C80C8 MICROCONTROLLER Page Number xix List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LDC LDE MEMON ahe unused obs dus Pit Lo ON ets 6 52 LDCD LDED Load Memory and Decrement nennen nnn 6 54 LDCI LDEI Load Memory and nnn 6 55 LDCPD LDEPD Load Memory with 6 56 LDCPI LDEPI Load Memory with
2. 2 5 2 4 Set 1 Set 2 and Area Register 2 7 2 5 8 Byte Working Register Areas 2 8 2 6 Contiguous 16 Byte Working Register Block 2 9 2 7 Non Contiguous 16 Byte Working Register 2 10 2 8 16 Bit Register tectae ast ieee 2 11 2 9 Register File 2 12 2 10 Common Working Register 2 13 2 11 4 Bit Working Register 2 15 2 12 4 Bit Working Register Addressing 8 2 15 2 13 8 Bit Working Register 2 16 2 14 8 Bit Working Register Addressing Example 2 17 2 15 Stack ant 2 18 3 1 Register 3 2 3 2 Working Register 0 3 2 3 3 Indirect Register Addressing to Register 2200440010 3 3 3 4 Indirect Register Addressing to Program 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register
3. nnne Flags Register 2222000 54 Flag Descriptions Instruction Set Notation Condition GOdeS ole cec Se er tuv Instr ction Descriptions nie dxudnmo GbbbninebcbD5nsbeesnens nnies vi S3P80C5 C80C5 C80C8 MICROCONTROLLER Table of Contents Continued Table of Contents Continued Part Il Hardware Descriptions S3P80C5 C80C5 C80C8 MICROCONTROLLER Chapter 7 Clock Circuit hoo to to bot Seat 7 1 system X m 7 1 Clock Status During Power Down 7 2 System Clock Control Register 7 3 Chapter 8 RESET and Power Down System RESO Es 8 1 HYD RESET oc ento Mee een Secs bem M LM en em 8 1 Interrupt with Reset 8 2 WatchsDog Timer BesotL orte Eie 8 2 Power on Reset 0 4 11 02 0 000 nnn nnns 8 2 System 8 3
4. 4 7 EMT External Memory Timing 4 8 FLAGS System Flags Register enne nnne nennen 4 9 IMR Interrupt Mask Register 4 10 IPH Instruction Pointer High 4 11 IPL Instruction Pointer LOW Byte 4 11 IPR Interrupt Priority 4 12 IRQ Interrupt Request 4 13 POCONH Port 0 Control Register High nn 4 14 POCONL Port 0 Control Register Low 4 15 POINT Port 0 Interrupt Control 4 16 POPND Port 0 Interrupt Pending Register 4 17 POPUR Port 0 Pull up Resistor Enable 4 18 P1CONH Port 1 Control Register High 4 19 P1CONL Port 1 Control Register Low 4 20 P1PUR Port 1 Pull up Resistor Enable Register 4 21 P2CON Port2 Gontrol 4 22 PP Register Page Polntet c deterrere edd 4 23 RPO Register 4 24 RP1 Register POINTER T 2 rrr rr ERE ERR 4 24 SPL Stack Pointer Low Byte 4 25 S
5. tananana Ran talaan iaa iaa 8 4 46 5 222 8 6 9 M M t 8 6 Using POR to Release Stop 8 6 Using an INTR to Release Stop Mode 8 6 e Moro e n PH 8 9 Summary Table of Stop Mode and Idle 8 10 Chapter 9 Ports OVENI WES e sooo RUM EE A 9 1 Port Data Registers iin REFER EERERAEXRERTRE ER EBENE YR NXREERESERERYMPNM P RDEMIRX RR RR 9 2 Pull Up Resistor Enable 9 2 molo EE Et 9 4 Port 0 Interrupt Enable Register 9 5 Port 0 Interrupt Pending Register 9 5 D x uM REPE 9 7 9 9 Chapter 10 Basic Timer and Timer 0 T PO 10 1 Basic Timer Control Register 10 1 Basic Timer Function Description icc e 10 3 Timer 0 Control Register 10 3 Timer 0 Function 10 5 vii Table of Contents Concluded Chapter 11 Timer 1 II T
6. 11 1 Timer 1 Overflow 11 2 Timers Match Interrupt seisen aran te x n RO ERE EXER EEEE KE 11 2 Timer 1 Control Register 11 4 Chapter 12 Counter A OVerIVIeW vest E SR 12 1 Counter A Control Register 12 3 Counter A Pulse Width Calculations 0000 0 0 20000 12 4 Chapter 13 Electrical Data 13 1 Chapter 14 Mechanical Data 14 1 viii SSP80C5 C80C5 C80C8 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 PCT weet On Oe ae ON Seeker ie 1 3 1 2 Pin Assignment Diagram 24 Pin SOP SDIP Package 1 4 1 3 Pin Circuit Type 1 0 nennen nnne nnns 1 6 1 4 Pin Gircuit Type 2 serere enm aea cere epo ed eer 1 7 1 5 Pin Circuit Type 2 0 nennen nennen nnns 1 8 1 6 Pin Circuit Type 4 9 1 9 1 7 Pin Circuit Type 5 2 2 0 1 10 2 1 Program Memory Address 000224 00001 2 2 2 2 Internal Register File 1 2 4 2 3 Register Page Pointer PP
7. 6mA 0 7 voltage EJ Port 2 1 only TA 25 C Vbpp 2 4 2 2mA Vpp 0 7 E Port 2 0 2 2 25 C All output pins except Port2 25 C 13 2 ELECTRONICS 3 80 5 80 5 80 8 ELECTRICAL DATA Table 13 2 D C Electrical Characteristics Continued TA 40 to 85 Vpp 2 0V to 3 6 V Output Low Vou Vop 24 lo 12 mA port voltage 2 1 only TA 25 C Port 2 0 2 2 TA 25 C Ports 0 and 1 25 C Input High Voo leakage current All input pins except X and Xout Vin Xin Input Low Vin OV leakage current All input pins except Xin Xin and mme 0 0 nm leakage current All output pins Emme leakage current All output pins Pull up resistors 2 4 Vin 0 V 44 55 95 KQ Supply current 1551 3 6 V 10 2 6 5 mA note 4 MHz crystal Idle mode 0 7 2 0 4 2 crystal 150 Stop mode 1 uA NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads ELECTRONICS 13 3 ELECTRICAL DATA S3P80C5 C80C5 C80C8 Table 13 3 Characteristics of Low Voltage Detect circuit TA 40 C to 85 C Hysteresys Voltage of LVD Slew Rate of LVD Low level detect voltage vp S3C80C5 C80C8 Table 13 4 Data Retention Supply Voltage in Stop Mode TA 40 C
8. 5 13 5 9 Interrupt Request Register 5 14 6 1 System Flags Register 6 6 7 1 Main Oscillator Circuit External Crystal or Ceramic Resonator 7 1 7 2 External Clock Circuit sss nennen nennen nnne nnn nnns 7 1 7 3 System Clock Circuit 7 2 7 4 System Clock Control Register 7 3 8 1 Reset Block Diagram 8 1 8 2 Power on Reset 8 2 8 3 Timing Diagram for Power on Reset 8 3 9 1 SSP80C5 C80C5 C80C8 I O Port 0 Data Register 9 2 9 2 SSP80C5 C80C5 C80C8 I O Port 1 Data Register 9 3 9 3 Port 0 High Byte Control Register 9 4 9 4 Port 0 Low Byte Control Register 9 5 9 5 Port 0 External Interrupt Control Register 9 6 9 6 Port 0 External Interrupt Pending Register 9 7 9 7 Port 1 High Byte Control Register 9 7 9 8 Port 1 Low Byte Control Register 9 8 9 9 Port 2 Control Register 9 9 9
9. 1 Push pull output mode C MOS input mode interrupt on rising edges NOTES 1 INT4 external interrupts at the 0 7 0 4 pins share the same interrupt level IRQ7 and interrupt vector address E8H 2 You can assign pull up resistors to individual port 0 pins by making the appropriate settings to the POPUR register 4 14 ELECTRONICS S3P80C5 C80C5 C80C8 CONTROL REGISTERS POCONL Port 0 Control Register Low Byte Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 INT3 Mode Selection Bits C MOS input mode interrupt falling edges fo 4 C MOS input mode interrupt on rising and falling edges Push pull output mode C MOS input mode interrupt on rising edges 5 4 0 21 2 Mode Selection Bits input mode erupt onfaling edges 791 GMOS input mode inerupt on ising ana taling edges Pi 0 3 2 0 11 1 Mode Selection Bits input mode iteruptonfaling edges 79111 Tomos input mode inerupt on ising ana taling edges Pi 0 1 0 PO 0 INTO Mode Selection Bits C MOS input mode interrupt falling edges Lo 4 C MOS input mode interrupt on rising and falling edges 1 Push pull output mode C MOS input mode interrupt on rising edges NOTES 1 ext
10. When a fast interrupt occurs the contents of the FLAGS register is stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3P80C5 C80C5 C80C8 microcontroller the service routine for any one of the five interrupt levels IRQO IRQ1 IRQ4 or 6 can be selected for fast interrupt processing Procedure for Initiating Fast Interrupts To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced Qv o Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register 7 The fast interrupt status bit in FLAGS is cleared automatically Relationship to Interrupt Pending Bit Types As described previously t
11. 1105H RO 1105H RO RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 no change 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 no change RO contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into external data memory location 0105H 01H 0104H RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H RO lt contents of program memory location 1104H RO 88H RO lt contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H 11H contents of RO is loaded into external data memory location 1105H 1105H lt NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3P80C5 C80C5 C80C8 L
12. Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register OOH register 01H 02H and register 02H CLR OOH gt Register OOH OOH 01H gt Register 01H 02H register 02 00H In Register R addressing mode the statement CLR OOH clears the destination register OOH value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET COM Complement COM dst Operation dst NOT dst The contents of the destination location are complemented one s complement all 1s are changed to 05 and vice versa Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM 1 gt 1 OF8H COM 1 gt 1 07H register 07H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H
13. 6 34 Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 RO C e lt 0 Bits 4 7 3 bits 0 3 C R1 lt 3CH DA R1 R1 lt 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 1 lt 31 0 leave the value 31 BCD address 27H 1 ELECTRONICS S3P80C5 C80C5 C80C8 DEC Decrement DEC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D H Unaffected Unaffected Bytes Cycles Opcode Hex opc dst 2 4 00 01 Given R1 and register 03H 10H DEC R1 gt R1 02H DEC gt Register 03H OFH INSTRUCTION SET Addr Mode dst R IR In
14. 6 57 LDW Eoad 6 58 MULT Multiply Unsigned 6 59 NEXT AT ET AT T TE T 6 60 N Operations 6 61 OR 6 62 Pop cet 6 63 POPUD Pop User Stack 6 64 POPUI Pop User Stack 6 65 PUSH Push to nnns 6 66 PUSHUD Push User Stack 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Carry in ok de DD D LAU es a 6 69 RET Retiran a 6 70 RL Rotate Betti osos ahs S a a 6 71 RLC Rotate Left through 0000 6 72 RR Fotate Right so ok ok an ME o PCIE 6 73 RRC Rotate Right through 6 74 SBO Select Bank eee en cere Gam 6 75 SB1 Select Bank 6 76 SBC SubtracbWitli 2c nhs Oe 6 77 SCF SOU Camry lagena 6 78 SRA Shift Right Aritbimrielle aka i 6 79 SRP SRPO SRP1 Sel Register te HET EIE De ETe ME
15. Examples cc dst Conditional dst Unconditional If is true PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 DA cc 0 to F opc dst 2 8 30 IRR NOTES 1 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W LABEL W 1000H PC 1000H JP 00 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement 00 replaces the contents of the PC with the contents of the register pair
16. Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing because it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 8 16 Bit Register Pair ELECTRONICS 2 11 ADDRESS SPACES S3P80C5 C80C5 C80C8 Special Purpose Registers General Purpose Register Set 1 Control Registers System Registers Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and 1 to locations C8H CFH that is to the common working register area NOTE Only page 0 is implemented Page 0 Contains all of the addressable registers in the internal register file Page 0 Page 0 m Register Addressing Only All Indirect Addressing Register Modes Indexed Addressing Can be Pointed by Register Pointer Modes Figure 2 9 Register File Addre
17. WATCHDOG TIMER RESET The S3P80C5 C80C5 C80C8 build a watch dog timer that can recover to normal operation from abnormal function Watchdog timer generates a system reset signal if not clearing a BT Basic Counter within a specific time by program System reset can return to the proper operation of chip POWER ON RESET POR The power on reset circuit is built on the S3P80C5 C80C5 C80C8 product During a power on reset the voltage at Vpp goes to High level and the Schmitt trigger input of POR circuit is forced to Low level and then to High level The power on reset circuit makes a reset signal whenever the power supply voltage is powering up and the Schmitt trigger input senses the Low level This on chip POR circuit consists of an internal resistor an internal capacitor and a Schmitt trigger input transistor R On Chip Resistor C On Chip Capacitor System Reset I C Schmitt Trigger Inverter Vss Figure 8 2 Power on Reset Circuit 8 2 ELECTRONICS S3P80C5 C80C5 C80C8 RESET and POWER DOWN If Va voltage is under the 0 4 Vpp Reset pulse signal is gernerated If Va voltage is over than 0 4 VDD Reset pulse is not gernerated Voltage V TVDD Rising Time VDD L VIH 0 85 VDD ViL 0 4 V 0 Reset Pulse Width Reset pulse Time Figure 8 3 Timing Diagram for Power on Reset Circuit SYSTEM RESET OPERATION System reset starts the oscillation circuit synchronize chip operation with CPU clo
18. 4 external interrupt P0 3 external interrupt POCONL E9H P0 2 external interrupt POINT F1H 0 1 external interrupt POPND F2H P0 0 external interrupt NOTE Because the timer 0 and timer 1 overflow interrupts are cleared by hardware the TOCON and T1CON registers control only the enable disable functions The TOCON and T1CON registers contain enable disable and pending bits for the timer 0 and timer 1 match interrupts respectively ELECTRONICS 5 9 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 7 SYM 1 and SYM 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register An Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation in order to enable interrupt processing Although you can manipulate SYM 0 directly to enable and disable interrupts during normal operation we recommend using the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W External Global interrupt enable bit tri 2 it 0 Disable all interrupts 0 Normal Tri state 1 Enable all inter
19. ELECTRONICS 3 9 ADDRESSING MODES S3P80C5 C80C5 C80C8 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Upper Address Byte Lower Address Byte LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed NOTE LDE command is not available because an external interface is not implemented for the S3C80C5 C80C8 C804C Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS 3 80 5 80 5 80 8 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is
20. S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H 0 RLC 00H Register 00H 54H C 1 RLC 01H gt Register 01H 02H register 02H 2 0 In the first example if general register 00H has the value OAAH 10101010B the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register resets the carry flag to 1 and sets the overflow flag ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET RR Rotate Right RR Operation dst C lt dst 0 dst 7 lt dst 0 dst lt dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occu
21. Sans Teas eaaa tent E 1 6 Chapter 2 Address Spaces 2 1 Program Memory RR 2 2 Register 2 3 Register Page Pointer PP zi et Ea 2 5 Daan E E A eA ON 2 6 2 6 Prime Register spacer ou aude aquse Aaa a A 2 7 Working 2 8 Using The Register 2 9 Register Addressing Maken eee toe Seta Mec AA 2 11 Common Working Register Area 2 13 4 Bit Working Register 9 2 14 8 Bit Working Register 90 2 16 systemvand WSer Stacks iier nt 2 18 Chapter 3 Addressing Modes enlm 3 1 Register Addressing Mode 3 2 Indirect Register Addressing Mode 3 3 Indexed Addressing Mode 2 02022 3 7 Direct Address Mode 3 10 Indirect Address Mod
22. fx 2 x 1us 13 Method 2 When CAOF 1 tuig 15 us CADATAL 2 fx CADATAL 2 x 1us CADATAL 13 24 us 2 2 x tus 22 12 4 ELECTRONICS S3P80C5 C80C5 C80C8 COUNTER A Counter A Clock 0 CADATAL 01 FFH CADATAH 001H CAOF 0 CADATAL 00H CADATAH 01 FFH CAOF 0 CADATAL 00H CADATAH 00H CAOF 1 CADATAL 00H CADATAH 00H Counter A Clock 0 CADATAL DEH CADATAH 1EH CAOF 0 CADATAL DEH CADATAH 1EH CAOF 1 CADATAL 7EH CADATAH 7EH 0 CADATAL 7 CADATAH 7EH Figure 12 4 Counter A Output flip flop Waveforms in Repeat Mode ELECTRONICS 12 5 COUNTER A S3P80C5 C80C5 C80C8 PROGRAMMING TIP To Generate 38 kHz 1 3duty Signal Through P2 1 This example sets Counter A to the repeat mode sets the oscillation frequency as the Counter A clock source and CADATAH and CADATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us 17 59 us 37 9 kHz 1 3 Duty Counter A is used in repeat mode Oscillation frequency is 4 MHz 0 25 us 8 795 us 0 25 us 35 18 CADATAL 17 59 us 0 25 us 70 36 Set P2 1 C MOS push pull output CAOF mode ORG START DI LD LD LD LD LD 12 6 0100H CADATAL 70 2 CADATAH 35 2 P2CON
23. 1 1024 8 Bit Basic Counter Read Only UX 8 Bit Comparator Timer 0 Buffer Reg Bits 5 4 N C Match Signal Timer 0 Data Register Basic Timer Control Register Read Write Timer 0 Control Register Data Bus NOTES 1 During a power on reset operation the CPU is idle during the required oscillation stabilizatiin interval until bit 4 of the basic timer counter overflows 2 It is available only in using interval mode Figure 10 5 Basic Timer and Timer 0 Block Diagram ELECTRONICS 10 7 BASIC TIMER and TIMER 0 S3P80C5 C80C5 C80C8 7 PROGRAMMING Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications ORG 0100H RESET LD BTCON 03H LD CLKCON 18H CLR SYM CLR SPL SRP 0C0H EI MAIN LD BTCON 02H NOP NOP JP T MAIN 10 8 Disable all interrupts Enable the watchdog timer Non divided clock Disable global and fast interrupts Stack pointer low byte lt 0 Stack area starts at OFFH Set register pointer lt 0 Enable interrupts Enable the watchdog timer Basic timer clock 105 4096 Clear basic timer counter ELECTRONICS 3 80 5 80 5 80 8 Programming Tip Programming Timer 0 BASIC TIMER AND TIMER 0 This sample program sets timer 0 to interval timer mode sets the frequency of the oscillator clock and determines the execution sequence which follows a timer 0 interrupt The program parameters are
24. 10101010B CACON 00000110B P2 20H Reset address Set 17 5 us Set 8 75 us Set P2 to C MOS push pull output Set P2 1 to REM output Clock Source fosc Disable Counter A interrupt Select repeat mode for Counter A Start Counter A operation Set Counter A Output Flip flop CAOF high Set P2 5 Carrier On Off to high This command generates 38 kHz 1 3duty pulse signal through P2 1 ELECTRONICS 3 80 5 80 5 80 8 COUNTER 87 PROGRAMMING TIP To Generate One Pulse Signal Through P2 1 This example sets Counter A to the one shot mode sets the oscillation frequency as the Counter A clock source and CADATAH and CADATAL to make a 40 us width pulse The program parameters are 40 us 22 gt Counter is used one shot mode Oscillation frequency is 4 MHz 1 clock 0 25 us 40 0 25 us 160 CADATAL 1 Set P2 1 C MOS push pull output and CAOF mode ORG 0100H START DI LD CADATAH 160 2 LD CADATAL 1 LD P2CON 10101010B LD CACON 00000001B LD P2 20H Pulse_out LD CACON 00000101B ELECTRONICS Reset address Set 40 Set any value except 00H Set P2 to C MOS push pull output Set P2 1 to REM output Clock Source lt fosc Disable Counter A interrupt Select one shot mode for Counter A Stop Counter A operation Set Counter A Output flip flop CAOF high Set P2 5 Carrier On Off to high Start Counter A operation
25. Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3P80C5 C80C5 C80C8 EXIT exit EXIT Operation Flags Format Example 6 42 IP lt SP SP e SP 2 PC lt P lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to use an EXIT statement Before After Address Data 0052 Data Address Data 0060 PCL old 60 60 Main PCH 00 SP 0022 Exit 2F Memory 22 m Memory Stack ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET IDLE Operation IDLE Operation Flags Format Example The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F x The instruction IDLE stops the CPU clock but not the system clock ELECTRONICS 6 43 INSTRUCTION SET INC Increment INC dst Operation dst dst 1 The contents of the destination o
26. This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory if implemented Register File oe RPO or RP1 gt RPO or RP1 Selected RP Paints to Instruction Ng OPERAND Working Register Block Program Memory Base Address Address nes petal dst src Instruction Point to One of the Example orking Register 1 of 8 Sample Instruction LD BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3P80C5 C80C5 C80C8 INDEXED ADDRESSING MODE Continued 3 8 Register File MSB Points to RPO or RP1 gt RPO or RP1 Selected RP Points to Start of Working Register OFFSET ad E Register Register Address OPGODE int to Working Pair Register Pair Program Memory Addr
27. or n channel open drain output mode Input mode with pull up resistors are assignable by software The two pins of port 2 have high current drive ELECTRONICS 1 5 PRODUCT OVERVIEW S3P80C5 C80C5 C80C8 PIN CIRCUITS Pull up Resistor Input Output Output Disable External Interrupt Stop Figure 1 3 Pin Circuit Type 1 Port 0 NOTE Interrupt with reset INTR is assigned to port 0 of S3P80C5 C80C5 C80C8 It is designed to release stop status with reset When the falling rising edge is detected at any pin of Port 0 during stop status non vectored interrupt INTR signal occurs after then system reset occurs automatically It is designed for a application which are using stop mode like remote controller If stop mode is not used INTR do not operates and it can be discarded 1 6 ELECTRONICS 3 80 5 80 5 80 8 PRODUCT OVERVIEW Pull up Resistor Input Output Open drain Output Disable Figure 1 4 Pin Circuit Type 2 Port 1 Pull up Resistor Typical 21KQ 5 2 0 Port 2 0 Data TO P2 0 TOPWN Open drain Output Disable Figure 1 5 Pin Circuit Type 3 P2 0 ELECTRONICS 1 7 PRODUCT OVERVIEW S3P80C5 C80C5 C80C8 Pull up Resistor Typical 21KQ Pull up Enable P2CON 1 CAOF CACON 0 Carrier On Off P2 5 P2 1 REM TOCK Open Drain o Output o Disable P2 1 Input o TOCK 0 Figure 1 6 Pin Circuit Type
28. to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts 12 7 COUNTER A S3P80C5 C80C5 C80C8 NOTES 12 8 ELECTRONICS 3 80 5 80 5 80 8 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section S8P80C5 C80C5 C80C8 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings D C electrical characteristics Data retention supply voltage in Stop mode Stop mode release timing when initiated by a Reset capacitance electrical characteristics Input timing for external interrupts port 0 Oscillation characteristics Oscillation stabilization time ELECTRONICS 13 1 ELECTRICAL DATA S3P80C5 C80C5 C80C8 Table 13 1 Absolute Maximum Ratings 25 C Parameter Conditions _ um 36 8 88 6 Yon Output current Low Total pin current for ports 0 1 and 2 Total pin current for port 3 Output current High loH Operating temperature Storage temperature Table 13 2 D C Electrical Characteristics TA 40 C to 85 C Vpp 2 0 V to 3 6 V Operating Voltage Vpp fosc 4MHz 1 7 Instruction clock 0 67 MHz Input High Vind All input pins except V5 0 8 Vpp Input Low voltage Vii 4 All input pins except Vi and Vii 5 Output High Vout 2 4 V
29. 4 13 5 Input Output 13 4 13 6 A C Electrical 13 4 13 7 Oscillation 13 5 13 8 Oscillation Stabilization 4000 1 000 13 6 SSP80C5 C80C5 C80C8 MICROCONTROLLER xiii List of Programming Tips Description Page Number Chapter 2 Address Spaces setting the Register POIDters 2 9 Using the RPs to Calculate the Sum of a Series of 2 10 Addressing the Common Working Register 2 14 Standard Stack Operations Using PUSH 2 19 Chapter 8 RESET and Power Down To Divide STOP Mode Releasing and nennen nnne 8 8 Chapter 10 Basic Timer and Timer 0 Configuring the Basic 10 8 Programming Kmer Orsai endo ect o le late cele gates eie decd 10 9 Chapter 12 Counter A To Generate 38 kHz 1 3duty Signal Through 12 6 To Generate a One Pulse Signal Through 2 7777 nnne nnn nnns 12 7 S3P80C5 C80C5 C80C8 MICROCONTROLLER XV List of Register Descriptions Register Full Register Name Page Identifier Number BTCON Basic Timer Control 7 4 5 Counter A Control 4 6 CLKCON System Clock Control
30. 4 P2 1 Pull up Resistor Typical 21KQ Pull up 2 Enable In Out Open drain Output Disable Normal Input Figure 1 7 Pin Circuit Type 5 P2 2 1 8 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3P80C5 C80C5 C80C8 microcontroller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C80C5 has an internal 15 872 byte programmable ROM the S3C80C8 has an internal 8 Kbyte programmable ROM An external memory interface is not implemented The 256 byte physical RAM space is expanded into an addressable area of 320 bytes by the use of addressing modes There are 312 mapped registers in the internal register file Of these 272 are for general purpose use This number includes a 16 byte working register common area that is used as a scratch area for data operations a 256 prime register area that is used for general purpose and stack operation Eighteen 8 bit registers are used for CPU and system control and 22 registers are mapped peripheral control and data registers ELECTRONICS 2 1 ADDRESS SPACES S3P80C5 C80C5 C80C8 PROGRAM MEMORY ROM Program memory stores program code or table data The S3C80C5 has 15 872 bytes of internal programmable program memory and the program mem
31. 5 Mode Selection Bits o Open lt ran ouput 1 0 P1 4 Mode Selection Bits 0 0 C Mosinputmode 0 1 Open drain output mode 1 0 Push pull output mode o ELECTRONICS 4 19 CONTROL REGISTERS S3P80C5 C80C5 C80C8 P1CONL Port 1 Control Register Low Byte EBH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 Mode Selection Bits 0 0 C Mosinputmode 0 1 Open drain output mode o 1 5 4 P1 2 Mode Selection Bits 71 Fo t owmednowumde ooo 3 2 P1 1 Mode Selection Bits 71129 ouputmode 1 0 P1 0 Mode Selection Bits 0 0 CMOS inputmods 0 1 Open drain output mode 1 4 20 ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS P1PUR Porto Pull up Resistor Enable Register ECH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 6 P1 6 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 P1 5 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P1 4 Pull up Resistor Enable Bit Disa
32. 80 8 CLOCK CIRCUITS SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in set 1 address D4H It is read write addressable and has the following functions Oscillator frequency divide by value CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release This is called the IRQ wake up function The IRQ wake up enable bit is CLKCON 7 In S3P80C5 C80C5 C80C8 this bit is not valid any more Actually bit 7 6 5 2 1 and 0 no meaning S3P80C5 C80C5 C80C8 After a reset the main oscillator is activated and the 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fosc fosc 2 or 8 System Clock Control Register CLKCON D4H Set 1 R W Not used Not used Divide by selection bits for CPU clock frequency 00 fosc 16 01 fosc 8 10 fosc 2 11 fosc non divided Not used Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 3 CLOCK CIRCUITS S3P80C5 C80C5 C80C8 NOTES 7 4 ELECTRONICS 3 80 5 80 5 80 8 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET S3P80C5 C80C5 C80C8 has four different system reset sources as followings Low Voltage Detect LVD Internal POR circuit INTR Interrupt with RESET Basic Timer Watchdog timer Enable Disable Noise Filter Stop
33. Addressing Modes contains detailed descriptions of the addressing modes that are supported by the KS88 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C80C5 C80C8 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the inform
34. Control Bit 1 Normal operation disable tri state operation Set external interface lines to high impedance enable tri state operation 6 5 Not used for S3P80C5 C80C5 C80C8 4 2 Fast Interrupt Level Selection Bits 2 4 Fast Interrupt Enable Bit 9 ol Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit 4 Disable global interrupt processing Enable global interrupt processing NOTES 1 Because an external interface is not implemented for the S3P80C5 C80C5 C80C8 SYM 7 must always be 2 You can select only one interrupt level at a time for fast interrupt processing 3 Setting SYM 1 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 4 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to 5 0 4 26 ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS Timer 0 Control Register D2H Set 1 Bit Identifier 7 8 5 4 21 29 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer 0 Input Clock Selection Bits UO C NEN Fe festo S apop _ _ o External clock input at the TOCK pin P2 1 5 4 Timer 0 Operating Mode Selection Bits Interval timer mode counter cleared by match signal EXER Overflow mode OVF in
35. ELECTRONICS 3 5 ADDRESSING MODES S3P80C5 C80C5 C80C8 INDIRECT REGISTER ADDRESSING MODE Continued Register File e i RPO or RP1 RPO or RP1 Selected RP Points to Start of Working Register ELI MSS Program Memory 4 bit Working Register Address Register Next 2 bit Point Pair kp eo an 0 References either Register Pair 16 Bit Program Memory or 1 of 4 el Data Memory Address LSB Selects Program Memory Points to or Program Data Memory Memory or Data Memory Value used in Instruction OPERAND Sample Instructions LDC R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access NOTE LDE command is not available because an external interface is not implemented for the S8C80C5 C80C8 C80C4 Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS 3 80 5 80 5 80 8 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory if implemented You cannot however access locations COH FFH in set 1 using Indexed addressing In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127
36. General purpose registers Register Space Peripheral control registers Figure 2 4 Set 1 Set 2 and Prime Area Register Map ELECTRONICS 2 7 ADDRESS SPACES S3P80C5 C80C5 C80C8 WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as consisting of 32 8 byte register groups or slices Each slice consists of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 working register block is 16 bytes sixteen 8 bit working registers RO R15 All of the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in regist
37. INSTRUCTION SET BXOR Bit XOR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOZONO Bytes Cycles Opcode Addr Mode Hex dst src opc sbio sc 3 6 27 0 opc dst 3 6 27 Rb T NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 0000001 1B BXOR HR1 01H 1 gt R1 06H register 01H BXOR 01H 2 R1 gt Register01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011 The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONIC
38. OOH and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3P80C5 C80C5 C80C8 JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc is true PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL X 1FF7H JR C LLABEL X PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are af
39. R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits Destination page 0 note 3 0 Source Register Page Selection Bits Bits 910 0 0 source pageot l NOTE In the S8P80C5 C80C5 C80C8 microcontroller a paged expansion of the internal register file is not implemented For this reason only page 0 settings are valid Register page pointer values for the source and destination register page are automatically set to 0000B following a hardware reset These values should not be changed during normal operation ELECTRONICS 4 23 CONTROL REGISTERS S3P80C5 C80C5 C80C8 RPO Register Pointer 0 D6H Set 1 RESET Value 1 1 0 0 0 E Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Destination Register Page Selection Bits Register pointer 0 can independently point to one of the 24 8 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for S3P80C5 C80C5 C80C8 1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 1 Address Value Register pointer 1 can indep
40. RO gt RO R2 C ADC RO R3 RO RO R3 C ADC RO R4 RO RO R4 C ADC RO R5 RO RO 5 The sum of these six registers 6FH is located the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H gt 80H 81H ADC 80H 82H 80H gt 80H 82H C ADC 80H 83H 80H 80H 83H C ADC 80H 84H 80H gt 80H 84H C ADC 80H 85H 80H gt 80H 85H Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code instead of 12 bytes and its execution time is 50 cycles instead of 36 cycles 2 10 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access all locations in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space
41. STOPCON Figure 8 1 Reset Block Diagram LVD RESET The Low Voltage detect circuit is built on the S3P80C5 C80C5 C80C8 product for system reset in stop mode When the operating status is not stop mode it detects a slope by comparing the voltage at Vpp with V Low level Detect Voltage The reset pulse is generated by the rising slope of Vpp While the voltage at Vpp is rising up and passing yp the reset pulse is occurred at the moment Vpp gt V yp This function is disabled when the operating state is stop mode to reduce the current consumption under 1 uA instead of 6 uA ELECTRONICS 8 1 RESET and POWER DOWN S3P80C5 C80C5 C80C8 INTERRUPT WITH RESET INTR vectored interrupt called Interrupt with reset INTR is built in S3C80C5 C80C8 to release stop status with system reset When a falling rising edge occurs at Port 0 during stop mode INTR signal is generated and it makes the system reset pulse An INTR signal is generated relating to interaction between Port 0 and operating status It is enabled by STOP status and occurs by falling rising edge at 0 So only when the chip status is STOP it is available If the operating status is not stop status INTR does not occurs NOTE This INTR is supplementary function to make system reset for an application which is using stop mode like remote controller an application which is not using stop mode INTR function can be discarded
42. Stack address lt PUSH RPO Stack address lt RPO PUSH Stack address OFCH lt PUSH R3 Stack address OFBH lt POP R3 lt Stack address OFBH POP RP1 RP1 lt Stack address OFCH POP RPO RPO lt Stack address OFDH POP PP PP lt Stack address OFEH ELECTRONICS 2 19 ADDRESS SPACES S3P80C5 C80C5 C80C8 NOTES 2 20 ELECTRONICS 3 80 5 80 5 80 8 ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3P80C5 C80C5 C80C8 REGISTER ADDRESSING MODE R In Register addressing mode the operand is the content of a specified register or register pair See Figure 3 1 Working register addressing differs from Register addressing because it
43. are directly accessible at all times using the Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Section 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 All set 2 locations COH FFH are addressed as part of page 0 in the S8P80C5 C80C5 C80C8 register space The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations 2 6 ELECTRONICS S3P80C5 C80C5 C80C8 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes of the 256 byte physical internal register file 00 is called the prime register space or more simply the prime area You can access registers in this address using any addressing mode In other words there is no addressing mode restriction for these registers as is the case for set 1 and set 2 registers registers in prime area locations are addressable immediately following a reset CPU and system registers Prime
44. as unsigned integers Flags C Set if the V flag is set and quotient is between 28 and 29 41 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 03H R2 40H register 40H 80H DIV RRO R2 gt RO R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO 03H R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET DJNZ Decrement Jump if Non Zero DJNZ Operation Flags Format Example r dst rer If r z0 lt PC dst The working register being used as a counter is decremented If the contents of the
45. can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 A
46. common working register area the 256 byte prime register area CPU and system control registers Mapped clock peripheral and I O control and data registers Total Addressable Bytes a ELECTRONICS 2 3 ADDRESS SPACES S3P80C5 C80C5 C80C8 System and Peripheral Conirol Registers Pegan 2 General Purpose Data Register 64 Bytes System Registers Indirect Register or Register Addressing Indexed addressing Mode modes or stack operations Working Registers Working Register Addressing Mode 256 Bytes 192 Bytes Prime Data Registers All Addressing Modes Figure 2 2 Internal Register File Organization 2 4 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 15 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3P80C5 C80C5 C80C8 microcontroller a paged register file expansion is not implemented and the register page pointer settings therefore always point to page 0 Following a reset the page pointer s source value lower nibble and destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing These page pointer PP register settings as shown in Figure 2 3 should not be
47. determine whether to write or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3P80C5 C80C5 C80C8 SUB Subtract SUB Operation Flags Format Examples 6 82 dst src dst lt
48. dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 22 r r SIC 6 23 r Ir opc SIC dst 3 6 24 R R 6 25 R IR opc dst SIC 3 6 26 R IM Given R1 12H R2 register 01H 21H register 02H register OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H register 02H SUB 01H 02H gt Register 01H 17H register 02H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H gt Register 01H C and S 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subt
49. logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 72 6 73 r Ir opc SIC dst 3 6 74 R R 6 75 R IR opc dst SIC 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM RO R1 E RO 0C7H R1 02H Z 0 RO R1 gt RO 0C7H R1 02H register 02H 23H Z 0 00H 01H gt Register OOH 2BH register 01H 02H Z 0 00H 01H gt Register 00 2BH register 01H 02H register 02H 23H Z 0 00H 54H gt Register 00H 2BH Z 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3P80C5 C80C5 C80C8 WEI wait For Interrupt WFI Operat
50. manatee terete tec emt DE Tcu 6 80 STOP SLOP Operations sioe SE DLL c M DUE 6 81 SUB ACL E 6 82 SWAP SWap NIDDIes x Deve e 6 83 TCM Test Complement under 6 84 Testinder Masks uci OO 6 85 WFI Wait for 6 86 XOR Logical Exclusive 6 87 XX SSP80C5 C80C5 C80C8 MICROCONTROLLER S3P80C5 C80C5 C80C8 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes Important CPU features include Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode release by interrupt Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum six CPU clocks can be assigned to specific interrupt levels S3P80C5 C80C5 C80C8 MICROCONTROLLER S3P80C5 C80C5 C80C8 single chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung s newest CPU architecture The S3C80C5 C80C8 is the microcontroller which has mask programmab
51. modified during normal operation Register Page Pointer PP DFH Set 1 R W Dectination register page selection bits Source register page selection bits 0000 Destination page 0 0000 Source page 0 NOTE In the S3C80C5 C80C8 microcontroller only pate 0 is implemented A hardware reset operation writes the 4 bit destination and source values shown above to the register pate pointer These values should not be modified Figure 2 3 Register Page Pointer PP ELECTRONICS 2 5 ADDRESS SPACES S3P80C5 C80C5 C80C8 REGISTER SET 1 The term set 7 refers to the upper 64 bytes of the register file locations COH FFH In some S3C8 series microcontrollers the upper 32 byte area of this 64 byte space EOH FFH is divided into two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other In the SSP80C5 C80C5 C80C8 microcontroller bank 1 is not implemented A hardware reset operation therefore always selects bank 0 addressing and the SBO and SB1 instructions are not necessary The upper 32 byte area of set 1 contains 26 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DFH DOH and a 16 byte common working register area COH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations
52. occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR 1 IR Given RO 1AH R1 02H register 02H OFH and register INCW RRO gt RO 1AH R1 03H INCW QHR1 gt Register 02H 10H register OOH In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to 00H and register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3P80C5 C80C5 C80C8 IRET Interrupt Return Operation Flags Format Example NOTE 6 46 IRET Normal IRET Fast FLAGS lt SP o IP SP lt SP 1 FLAGS lt FLAGS PC SP FIS 0 SP lt SP 2 SYM 0 lt 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fa
53. pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110
54. pulse that is output at the TOPWM As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer 0 overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TOPWM pin is held to Low level as long as the reference data value is ess than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to x 256 see Figure 11 4 IRQO TOINT TOCON 0 Interrupt Enable Disable TOCON 1 Counter IRQO TOOVF High level when Low level when data counter TOCON 5 Buffer Register TOCON 4 Match Signal TOCON 3 TOOVF Data Register NOTE Interrupts are usually not used when timer 0 is configurared to operate in PWM mode Figure 10 4 Simplified Timer 0 Function Diagram PWM Mode 10 6 ELECTRONICS S3P80C5 C80C5 C80C8 BASIC TIMER AND TIMER 0 RESET or Stop Basic Timer Control Register Write 1010xxxxB to disable y Data Bus E Data Bus 1 1024 8 Bit Up Counter p 4 Read Only E gt P2 1 TOCK TOCON O Clear 1 4096
55. register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location OCOH to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0 DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3P80C5 C80C5 C80C8 El Enable Interrupts Operation Flags Format Example 6 40 SYM 0 lt 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to b
56. the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 8 51 IR Given Register 00H 01H register 01H SPH OD8H 00H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00H gt Register OOH 01H register 01H 55H SP OOFCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location OOFBH 55H into destination register and then increments the stack pointer by one Register OOH then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3P80C5 C80C5 C80C8 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example 6 64 dst src dst lt src IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 92 R IR Given Register OOH 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6FH If general register OOH contains the value 42H and register 42H the value 6FH t
57. the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3P80C5 C80C5 C80C8 BTJRT sit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24 dst src b If src b is 1 then PC PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3P80C5 C80C5 C80C8
58. thirteen possible interrupt sources When a service routine starts the respective pending bit is either cleared automatically by hardware or is must be cleared manually by program software The characteristics of the source s pending mechanism determine which method is used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 INTERRUPT TYPES The three components of the S3C8 interrupt structure described above levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source 1 Type 2 One level IRQn one vector V4 multiple sources S1 Sp Type 3 One level IRQn multiple vectors V4 Vn multiple sources 84 Sn Sn 1 Sn m In the S8P80C5 C80C5 C80C8 microcontroller all three interrupt types are implemented Levels Vectors Sources Type 1 81 51 2 2 5 5 51 3 IRQn 52 NOTES 1 number of Sn and Vn value is expandable 2 Inthe S8P80C5 C80C5 C80C8 implementation interrupt types 1 2 and is used Figure 5 1 S3C8
59. to 85 C Conditions oM MT Data retention supply voltage Data retention supply 15508 Vpppr 1 0 V current Stop mode Table 13 5 Input output Capacitance 40 to 85 C Vpp 0 Symbol Conditions min Input Cin f 1 MHz unmeasured pins capacitance are connected to Vss Output Cout capacitance I O capacitance Table 13 6 A C Electrical Characteristics TA 40 to 85 Interrupt input 0 0 7 Vpp 3 6 y High Low width 13 4 ELECTRONICS 3 80 5 80 5 80 8 ELECTRICAL DATA NOTE unit tcPU means one CPU clock period Figure 13 1 Input Timing for External Interrupts Port 0 Table 13 7 Oscillation Characteristics 40 85 C 2 Crystal CPU clock oscillation frequency Ceramic CPU clock oscillation frequency External clock External Clock Open Pin ELECTRONICS 13 5 ELECTRICAL DATA S3P80C5 C80C5 C80C8 Table 13 8 Oscillation Stabilization Time Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range Oscillator twait when released by a reset 7 stabilization NOTES wait time 1 fosc is the oscillator frequency 2 The duration of the oscillation stabilization time twat when it is released by an interrupt is determined by the setting in the basic timer control register BTCON Instruction Instruct
60. uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File amp otRegster OPERAND OPCODE Point to One E Register in Register One Operand Instruction Example piei Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Points to Bene BRI RPO or RP1 Selected RP Points to Start of Working Register Program Memory 4 bit OPCODE Points to the Working Register Two Operand A 1 of 8 Instruction Example Working Register OPERAND Block Sample Instruction ADD R1 R2 Where R1 R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS 3 80 5 80 5 80 8 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space if implemented see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indir
61. 0 7 also called level 0 level 7 Each interrupt level directly corresponds to interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3P80C5 C80C5 C80C8 interrupt structure recognizes five interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are simply identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware The S8P80C5 C80C5 C80C8 uses ten vectors One vector address is shared by four interrupt sources Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow for example Each vector can have several interrupt sources In the 53 80 5 80 5 80 8 interrupt structure there are
62. 01 fosc 2 1 T FF is High Counter A mode selection bit 0 One shot mode Counter A interrupt selection bits 1 Repeating mode 00 Elapsed time for Low data value 01 Elapsed time for High data value 10 Elapsed time for Low and High data values 11 Invalid setting Counter A interrupt enable bit 0 Disable interrupt 1 Enable interrupt Counter A start stop bit 0 Stop counter A 1 Start counter A Figure 12 2 Counter A Control Register CACON ELECTRONICS 12 3 COUNTER A S3P80C5 C80C5 C80C8 Counter A Data High Byte Register CADATAH F4H Set 1 R W Reset Value FFh Counter A Data Low Byte Register CADATAL F5H Set 1 R W Reset Value FFh Figure 12 3 Counter A Registers COUNTER A PULSE WIDTH CALCULATIONS tHIGH To generate the above repeated waveform consisted of low period time t and high period time t jc When CAOF 0 CADATAL 2 x 1 fxx OH lt CADATAL lt 100H where The selected clock tHIGH CADATAH 2 x 1 fxx OH CADATAH 100H where fx The selected clock When CAOF 1 2 x 1 fxx lt lt 100H where fx The selected clock tHIGH CADATAL 2 x 1 fxx OH CADATAL 100H where fx The selected clock Method 1 When CAOF 0 ti ow 24 us CADATAL 2 CADATAL 2 x 1us CADATAL 22 tuig 15 us CADATAH 2
63. 1 gives you a general overview of S3P80C5 C80C5 C80C8 port functions Table 9 1 S3P80C5 C80C5 C80C8 Port Configuration Overview Configuration Options 8 bit general purpose port Input or push pull output external interrupt input on falling edges rising edges or both edges all PO pin circuits have noise filters and interrupt enable disable POINT and pending control POPND Pull up resistors can be assigned to individual PO pins using POPUR register settings Specially Interrupt with Reset INTR is assigned to release stop mode with system reset 8 bit general purpose port Input open drain output or push pull output Pull up resistors can be assigned to individual P1 pins using P1PUR register settings 3 bit port input mode with or without pull up push pull or open drain output mode REM and TOPWM can be assigned Port 2 pins have high current drive capability to support LED applications The port 2 data register contains three status bits three for P2 0 P2 1 and P2 2 and one for remote controller carrier signal on off status ELECTRONICS 9 1 PORTS S3P80C5 C80C5 C80C8 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all three S3C80C5 C80C8 port data registers Data registers for ports 0 and 1 have the general format NOTE The data register for port 2 P2 contains three bits for P2 0 P2 1 and P2 2 and an additional status bit for carrier signal on off Tab
64. 10 Port 2 Data Register 2 9 10 x S3P80C5 C80C5 C80C8 MICROCONTROLLER List of Figures Concluded Figure Title Page Number Number 10 1 Basic Timer Control Register 10 2 10 2 Timer 0 Control Register 10 4 10 3 Simplified Timer 0 Function Diagram Interval Timer 10 5 10 4 Simplified Timer 0 Function Diagram PWM 10 6 Simplified Timer 1 Function Diagram Interval Timer 11 2 Timer 1 Block 11 3 11 3 Timer 1 Control Register 1 _ enn nnns 11 4 11 4 Mic IEEE 11 5 12 1 Counter Block 12 2 12 2 Counter A Control Register 02 0000 0 nns 12 3 12 3 Counter A 12 4 12 4 Counter A Output Flip Flop Waveforms in Repeat 12 5 13 1 Input Timing for External Interrupts Port 0 13 5 13 2 Operating Voltage Range 13 6 14 1 24 SOP Package Mechanical 14 1 14 2 24 Pin SDIP Package Mechanical 14 2 S3P80C5 C80C5 C80C8 MICROCONTROLLER xi List of Tables Table Title Page Number Number 1 1 Pin Descriptions 5 9 ahaa eta net
65. 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET S3P80C5 C80C5 C80C8 CP Compare Operation Flags Format Examples 6 30 dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Setif a borrow occurred src dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst sic opc dst 2 4 A2 r r SIC 6 r Ir opc SIC dst 3 6 A4 R R 5 R IR opc dst SIC 3 6 A6 R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jum
66. 21 S3 P80C5 C80C5 C80C8 052002 USER S MANUAL S3P80C5 C80C5 C80C8 8 Bit CMOS Microcontrollers Revision 1 ELECTRONICS S3P80C5 C80C5 C80C8 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3P80C5 C80C5 C80C8 8 Bit CMOS Microcontrollers User s Manual Revision 1 Publication Number 21 S3 P80C5 C80C5 C80C8 052002 2002 Samsung Electronics Typical parameters
67. 7 In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET BTJRF sit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC PC dst The specified bit within the source operand is tested If it is a the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains
68. 7 External Interrupt INT4 Pending Flag te PO 7 external interrupt pending when read 1 P0 7 external interrupt is pending when read 6 0 6 External Interrupt INT4 Pending Flag No 6 external interrupt pending when read 1 6 external interrupt is pending when read 5 PO 5 External Interrupt INT4 Pending Flag No 0 5 external interrupt pending when read 1 P0 5 external interrupt is pending when read 4 0 4 External Interrupt INT4 Pending Flag 4 external interrupt pending when read 1 4 external interrupt is pending when read 3 0 3 External Interrupt INT3 Pending Flag external interrupt pending when read external interrupt is pending when read 2 P0 2 External Interrupt INT2 Pending Flag No 2 external interrupt pending when read 1 P0 2 external interrupt is pending when read 1 0 1 External Interrupt INT1 Pending Flag No 1 external interrupt pending when read gt 0 1 external interrupt is pending when read 0 0 0 External Interrupt INTO Pending Flag No PO0 0 external interrupt pending when read 1 P0 0 external interrupt is pending when read NOTE To clear an interrupt pending condition write a 0 to the appropriate pending flag Writing a 1 to an interrupt pending flag POND 0 7 has no effect N ELECTRONICS 4 CONTROL REGISTERS S3P80C5 C80C5 C80C8 POPUR Porto P
69. Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data Memory 3 9 3 10 Direct Addressing for Load 3 10 3 11 Direct Addressing for Call and Jump 6 00 3 11 3 12 Indirect Addressing i Rte rere pr pe eret 3 12 3 13 Relative nnne nnns 3 13 3 14 Immediate 00 0 3 14 4 1 Register Description 4 4 S3P80C5 C80C5 C80C8 MICROCONTROLLER ix List of Figures Continued Figure Title Page Number Number 5 1 KS88 Series Interrupt 5 2 5 3 ROM Vector Address Area 20 0000000 nennen nnns 5 5 5 2 Interrupt Structure 5 4 5 4 Interrupt Function 5 8 5 5 System Mode Register 5 5 10 5 6 Interrupt Mask Register 5 11 5 7 Interrupt Request Priority Groups 0222 0000 5 12 5 8 Interrupt Priority Register 402 220 0 00
70. B 2 14 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES Selects RPO or RP1 Address OPCODE 4 bit Address Register Pointer Provides Three Provides Five Low order Bits High order Bits ll EE M Together They Create an 8 bit Register Address Figure 2 11 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Instruction 01110 Address 0110 1110 incre 76H Figure 2 12 4 Bit Working Register Addressing Example ELECTRONICS 2 15 ADDRESS SPACES S3P80C5 C80C5 C80C8 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five hi
71. Bit Counter A Interrupt Disable mask 1 Enable un mask Not used for S3P80C5 C80C5 C80C8 Interrupt Level 1 IRQ1 Enable Bit Timer 1 Match Overflow Disable mask 1 Enable un mask 0 Interrupt Level 0 IRQO Enable Bit Timer 0 Match or Overflow Disable mask 1 Enable un mask NOTES 1 When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU 2 Interrupt levels IRQ2 IRQ3 and IRQ5 are not used in the S8P80C5 C80C5 C80C8 interrupt structure S3P80C5 C80C5 C80C8 CONTROL REGISTERS IPH instruction Pointer High Byte DAH Set 1 Bit Identifier 85 4 j 3 2 4 j 9 X X X X X X X RESET Value x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 1P8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET Value x x x x x x x X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS 4 11
72. CONTROL REGISTERS S3P80C5 C80C5 C80C8 IPR Interrupt Priority Register FFH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Bit Addressing Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C Fo 0 Grouppronty undeined o Fo r e as826 O i e e osas8 Feel Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 1 Not used for S3P80C5 C80C5 C80C8 o p 2 Input Group B Priority Control Bit IRQ4 IRQ4 0 Interrupt Group A Priority Control Bit gt IRQ1 IRQ1 gt IRQO NOTE S3P80C5 C80C5 C80C8 interrupt structure uses only five levels IRQO IRQ1 IRQ4 IRQ6 IRQ7 Because IRQ2 IRQ3 IRQ5 are not recognized the interrupt subgroup and group C settings IPR 2 3 and IPR 5 are not evaluated 1 3 80 5 80 5 80 8 CONTROL REGISTERS IRQ Interrupt Request Register DCH Set 1 Bit Identifier o8 4 j 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit External Interrupts 0 7 0 4 Not pending 1 Pending 6 Level 6 IRQ6 Request Pending Bit External Interrupts 0 3 0 0 Not pending Pending Not used f
73. CTRONICS 6 11 INSTRUCTION SET S3P80C5 C80C5 C80C8 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes mmy geet 0000 Always false 1000 T Always true 0111 Carry 1111 note Il note No carry 0110 note Zero 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 1110 note Not equal 1001 Greater than or equal 0001 Less than 1010 Greater than 0010 Less than or equal 1111 note Unsigned greater than or equal 0111 note Unsigned less than 1011 Unsigned greater than 0011 Unsigned less than or equal N Il Il Il O O O O S S V V Z N Il 1 OR 0 1 V 0 V 1 NWN GD OO x I NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but af
74. DCD LDED Load Memory and Decrement LDCD LDED dstsrc Operation Flags Format Examples 6 54 dst src r lt e m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 E2 Given R6 10H R7 33H R8 12H program memory location 1033H external data memory location 1033H ODDH LDCD R8 Q9 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 82H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 10H R7 32H ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dst src dst src r m 1 These instructions are used for u
75. DD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 1 RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 12 R2 R1 IR2 R1 R1 IM r1 b R2 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 12 R2 R1 IR2 R1 R1 IM r2 b RA 4 DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 12 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x rl A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 112 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 112 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA r2 lrr1 IA1 IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 lrr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs 6 10 ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELE
76. FLAGS 4 be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W cary tag c z o cero tag qe status flag FIS Sign flag S Half carry flag H Overflow V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET FLAG DESCRIPTIONS FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear o
77. H register OOH 2BH register 01H 02H and register 02H 23H XOR RO R1 XOR RO R1 XOR 00H 01H XOR 00H 01H XOR 00H 54H gt 3 E RO R1 02H RO OE4H 1 02H register 02H 23H Register 00H 29H register 01H 02H Register OOH 08H register 01H 02H register 02H Register OOH 7FH 23H In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result in the destination register RO ELECTRONICS 6 87 INSTRUCTION SET S3P80C5 C80C5 C80C8 NOTES 6 88 ELECTRONICS 3 80 5 80 5 80 8 CLOCK CIRCUITS CLOCK CIRCUITS OVERVIEW The clock frequency generated for the S3P80C5 C80C5 C80C8 by an external crystal or supplied by an external clock source can range from 1MHz to 4 MHz The maximum CPU clock frequency as determined by CLKCON register settings is 4 MHz The Xy and pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fosc divided by 1 2 8 or 16 Clock circuit control register CLKCON External C
78. INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels used in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt source is active the source with the highest priority level is serviced first If both sources belong to the same interrupt level the source with the lowest vector address usually has priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQO IRQ1 Group B IRQ4 Group C IRQ6 IRQ7 IRQO IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A the setting 101B would select the relationship gt B gt A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group C interrupts Interrupt group B has a subgroup to provide an addi
79. R JP LD STOP NOP NOP JP RO RO RO R0O 0BOH UGE CHK_W STOP T MAIN STOPCON 0A5H RESET Enter the STOP mode S3P80C5 C80C5 C80C8 ELECTRONICS S3P80C5 C80C5 C80C8 RESET and POWER DOWN IDLE MODE Idle mode is invoked by the instruction IDLE OPCODE 6 In Idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU and from all but the following peripherals which remain active Interrupt logic Timer 0 Timer 1 Counter I O port pins retain the mode input or output they had at the time Idle mode was entered Idle Mode Release You can release Idle mode in one of two ways 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slowest clock because of the hardware reset value for the CLKCON register If all external interrupts are masked in the IMR register a reset is the only way you can release Idle mode 2 Activate any enabled interrupt internal or external When you use an interrupt to release Idle mode the 2 bit CLKCON 4 CLKCON 3 value remains unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt condition IRET occurs the instruction immediately following the on
80. S 6 25 INSTRUCTION SET S3P80C5 C80C5 C80C8 CALL Call Procedure CALL Operation Flags Format Examples 6 26 dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 Given RO 35H R1 21H 1A47H and SP 0002H CALL 3521H gt SP 0000 Memory locations 0000H 0001H where 4AH is the address that follows the instruction CALL RRO SP 0000H 0000H 0001H 49H CALL 40H 9 SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program s
81. S W E2H external interrupt S W P0 0 external interrupt S W PO 7 external interrupt S W P0 6 external interrupt S W P0 5 external interrupt S W P0 4 external interrupt S W NOTE For interrupt levels with two or more vectors the lowest vector address usually the highest priority For example FAH has the higher priority 0 than FCH 1 within level IRQO These priorities are fixed in hardware Figure 5 2 S3P80C5 C80C5 C80C8 Interrupt Structure 5 4 ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3P80C5 C80C5 C80C8 interrupt structure are stored in the vector address area of the internal program memory ROM 00 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 2 lists all vector addresses The program reset address in the ROM is 0100H Decimal 15 872 15 Kbyte 53 80 5 1FFFH S3C80C8 Interrupt Vector Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 Table 5 1 S3P80C5 C80C5 C80C8 Interrupt Vectors Interrupt Source Reset Clear Dur a Value Value Level Level m NOTES 1 Interrupt priorities are identified in inverse order 0 is highest priority 1 is th
82. Series Interrupt Types 5 2 ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE 3 80 5 80 5 80 8 INTERRUPT STRUCTURE The S3P80C5 microcontroller supports two kinds interrupt structure Vectored Interrupt Non vectored interrupt Reset interrupt INTR The S3P80C5 C80C5 C80C8 microcontroller supports thirteen interrupt sources Nine of the interrupt sources have a corresponding interrupt vector address the remaining four interrupt sources share the same vector address Five interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and state flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed The S3P80C5 C80C5 C80C8 microcontroller supports non vectored interrupt Interrupt with Reset INTR to o
83. T instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address Top of Stack Stack Contents Stack Contents After a Call After an Interrupt Instruction Low Address Figure 2 15 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL Register location D9H contain the 8 bit stack pointer SPL that is used for system stack operations After a reset the SPL value is undetermined Because only internal memory 256 byte is implemented in S3P80C5 C80C5 C80C8 the SPL must be initialized to an 8 bit value the range 00H FFH 2 18 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SPL 0FFH SPL Normally the SPL is set to OFFH by the initialization routine PUSH PP
84. TCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically TIMER 0 CONTROL REGISTER TOCON You use the timer 0 control register TOCON to Select the timer 0 operating mode interval timer Select the timer 0 input clock frequency Clear the timer 0 counter TOCNT Enable the timer 0 overflow interrupt or timer 0 match interrupt Clear timer 0 match interrupt pending conditions TOCON is located in set 1 at address D2H and is read write addressable using Register addressing mode A reset clears to 00 This sets timer 0 to normal interval timer mode selects an input clock frequency of fog 4096 and disables all timer 0 interrupts You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 3 The timer O overflow interrupt TOOVF is interrupt level IRQO and has the vector address FAH When a timer 0 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer 0 match interrupt IRQO vector FCH
85. TOPCON Stop Control Beglster ph ned P b E pep RR PR ERE 4 25 SYM System Mode Register 0422 00 senem nnns 4 26 TOCON Timer 0 Control 4 27 T1CON Timer 1 Control Register ete septies ves pasiva exe eir a RR 4 28 SSP80C5 C80C5 C80C8 MICROCONTROLLER xvii List of Instruction Descriptions Instruction Full Register Name Mnemonic ADC Add with acte adeste dade edad ADD AND Logical AND A NA UE BAND BELAND a cate cea ce Bit Compare BITC Bit BITR nisi p EEUU BITS IIR e ora BTJRF Bit Test Jump Relative on BTJRT Bit Test Jump Relative on BXOR streets cmt cate et cce cim CALL Call CCF Complement Carry 0 CLR ete ttr aor Sen oe One or oo eat te So Oe COM gt Compare Increment and Jump on CPIJNE Compare Increment and Jump on
86. UPT SOURCE POLLING SEQUENCE The E EE interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced the following conditions must be met If all The PON gt Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register of the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch
87. W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 External WAIT Input Function Enable Bit Disable WAIT input function for external device Enable WAIT input function for external device 6 Slow Memory Timing Enable Bit Disable WAIT input function for external device Enable WAIT input function for external device 5 4 Program Memory Automatic Wait Control Bits Nowait 00 025 1 Waitone cyce 00 1 0 Waittwocycles 00 00 3 2 Data Memory Automatic Wait Control Bits 0 1 Waitone cyce 00 1 0 Waittwocycles o 1 Stack Area Selection Bit Select internal register file area Select external data memory area 0 Not used for S3P80C5 C80C5 C80C8 NOTE The EMT register is not used for 53 80 5 80 5 80 8 because an external peripheral interface is not implemented in the 53 80 5 80 5 80 8 The program initialization routine should clear the EMT register to 00H following a reset Modification of EMT values during normal operation may cause a system malfunction 4 8 ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS 1 FLAGS System Flags Register D5H Set RESET Value X X x x x x 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into
88. a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3P80C5 C80C5 C80C8 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero urren Instruction OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS 3 80 5 80 5 80 8 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a two s complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instructi
89. a aloes chen 1 5 2 1 Register Type 2 3 4 1 Mapped Registers 4 2 5 1 Interrupt 5 6 5 2 Interrupt Control Register Overview 2 5 7 5 3 Interrupt Source Control and Data 5 9 6 1 Instruction Group nnn 6 2 6 2 Flag Notation Conventions 6 8 6 3 Instruction Set 6 8 6 4 Instruction Notation 4 2 0 0 0002 nennen 6 9 6 5 Opcode Quick Reference 22 228 6 10 6 6 Condition 6 12 8 1 Set 1 Register Values After 0004 4 4 nnns 8 4 8 2 Summary of Each 8 10 9 1 S3P80C5 C80C5 C80C8 Port Configuration 9 1 9 2 Port Data Register 9 2 13 1 Absolute Maximum 13 2 13 2 D C Electrical Characteristics 00244 13 2 13 3 Characteristics of Low Voltage Detect 13 4 13 4 Data Retention Supply Voltage in Stop 13
90. ags are noted by shaded table cells ELECTRONICS 8 5 RESET and POWER DOWN S3P80C5 C80C5 C80C8 POWER DOWN MODES STOP MODE Stop mode is invoked by stop control register STOPCON setting and the instruction STOP In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 uA at 5 5 V All system functions stop when the clock freezes Stop mode can be released of two ways by an INTR Interrupt with Reset or by a POR Power On Reset USING POR TO RELEASE STOP MODE Stop mode is released when the reset signal goes active by power on reset POR all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are unknown states When the oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H USING AN INTR TO RELEASE STOP MODE Stop mode is released when INTR Interrupt with Reset occurs INTR occurs when falling rising edge is detected at PO during stop mode and it make system reset NOTE 1 Do not use stop mode if you are using an external clock source because input must be cleared internally to Vgs to reduce current leakage 2 STOP mode always be released by the system reset INTR or POR so the system register value and control register value are initialize
91. and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 42 6 43 r Ir opc SIC dst 3 6 44 R R 45 R IR opc dst SIC 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H register 01H 37H OR 01H 00H gt Register OOH 08H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into
92. anged during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 R 4 C1 IR Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H E Register 00H 2AH C 1 RRC 01H gt Register 01H 02H register 02H 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2 00101010 in destination register OOH The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3P80C5 C80C5 C80C8 SB1 Select Bank 1 SB1 Operation BANK lt 1 SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the re
93. as follows Timer 0 is used in interval mode the timer interval is set to 4 milliseconds Oscillation frequency is 4 MHz General register 60H page 0 lt 60H 61H 62H 63H 64H page 0 is executed after a timer 0 interrupt ORG OFAH VECTOR TOOVER ORG OFCH VECTOR TOINT ORG RESET LD BTCON 0AAH LD CLKCON 18H CLR SYM CLR SPL LD TOCON 4BH LD TODATA 5DH SRP 0COH El ELECTRONICS Timer 0 overflow interrupt Timer 0 match capture interrupt 0100H Disable all interrupts Disable the watchdog timer Select non divided clock Disable global and fast interrupts Stack pointer low byte lt 0 Stack area starts at OFFH Write 01001011B Input clock is fog 256 Interval timer mode Enable the timer 0 interrupt Disable the timer 0 overflow interrupt Settimer interval to 4 milliseconds 4 MHz 256 93 1 0 166 kHz 6 ms Setregister pointer lt 0 Enable interrupts 10 9 BASIC TIMER and TIMER 0 S3P80C5 C80C5 C80C8 PROGRAMMING TIP Programming Timer 0 Continued TOINT PUSH RPO SRPO 60H INC RO ADD R2 RO ADC R3 R2 ADC R4 RO CP R0 32H JR ULT NO_300MS_SET BITS R1 2 NO_300MS_SET LD TOCON 42H POP RPO TOOVER IRET 10 10 Save RPO to stack RPO lt 60H RO RO 1 R2 R2 R0 lt R3 R2 Carry R4 lt R4 RO Carry 50 x 6 300 ms Bit setting 61 2H Clear pending bit Restore register pointer 0 va
94. ation in Part as necessary Part I hardware Descriptions has detailed information about specific hardware components of the S3C80C5 C80C8 microcontroller Also included in Part II are electrical mechanical OTP and development tools data It has eight chapters Chapter 7 Clock Circuit Chapter 11 Timer 1 Chapter 8 RESET and Power Down Chapter 12 Counter A Chapter 9 Ports Chapter 13 Electrical Data Chapter 10 Basic Timer and Timer 0 Chapter 14 Mechanical Data Two order forms are included at the back of this manual to facilitate customer order for S3C80C5 C80C8 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative S3P80C5 C80C5 C80C8 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview OVOIVIOW c ur voler c ur volun Mode dels 1 1 S3P80C5 C80C5 C80C8 Microcontroller 2220 nnn nnne nnns 1 1 1 2 UO 1 2 1 3 AAs SAA Sects cause a a 1 4 DIEI 0110 A Mc 1 5
95. avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value OOH in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3P80C5 C80C5 C80C8 DIV Divide Unsigned DIV dst src Operation dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated
96. ber for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Im or Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt RR6 1 7FH contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 RR6 1 7FH contents of RO is loaded into external data memory location 2200H 21FFH 1H 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET S3P80C5 C80C5 C80C8 LDW Load Word LDW Operation Flags Format Examples 6 58 dst src dst src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 C4 RR RR 8 C5 RR IR opc dst SIC 4 8 C6 RR IML 05H R7 02H register OOH Given R4 06 R5 1CH R6 03H and register O3H OFH register 01H 02H register 02H LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 00H 03H register 01H OFH register 02H register OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H OFH LDW RR6 1234H gt 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register OEDH In the second example please note that the statement LDW 00 02 load
97. ble pull up resistor 1 Enable pull up resistor 3 P1 3 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P1 2 Pull up Resistor Enable Bit Disable pull up resistor le Enable pull up resistor P1 1 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 0 P1 0 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor ELECTRONICS 4 CONTROL REGISTERS S3P80C5 C80C5 C80C8 P2CON Port 2 Control Register FOH Set 1 Bit Identifier o8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 2 2 Mode Selection Bits 0 0 CMOS inputmods 0 1 Open drain output mode o 1 Push pull output mode C MOS input with pull up mode 5 4 P2 1 Mode Selection Bits Fo 71129 ouputmode 3 2 P2 0 Mode Selection Bits 0 0 C Mosinputmode o Open drain output mode 1 0 Push pull output mode C MOS input with pull up mode 1 P2 1 Alternative Function Selection Bits Normal I O function REM TOCK function 0 P2 0 Alternative Function Selection Bits 0 Normal function E TOPWN function 4 22 ELECTRONICS S3P80C5 C80C5 C80C8 CONTROL REGISTERS PP Register Page Pointer DFH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W
98. ccur interrupt with system reset The Interrupt with Reset INTR has nothing to do with interrupt levels vectors and the registers that are related to interrupt setting It occurs only according to the PO during STOP regardless any other things Namely only when a falling rising edge occurs at any pin of Port 0 during STOP status this INTR and a system reset occurs even though SYM 0 is O Disable interrupt But it dose not occurs while the oscillation IDLE or OPERATING status even though a falling rising edge occurs at port 0 Following is the sequence that occurs Interrupt with Reset INTR The oscillation status is freeze STOP mode A falling rising edge is detected to any pin of Port 0 INTR occurs and it makes system reset PON gt STOP mode is released by this system reset NOTE Because H W reset occurs whenever INTR occurs A user should aware of the each ports system register control register etc ELECTRONICS 5 3 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 Levels Vectors Sources Reset Clear RESET 100H Basic timer overflow INTR POR H W Timer 0 match S W IRQO Timer 0 overflow H W F6H Timer 1 match S W _ Timer 1 overflow H W Counter A H W E6H P0 3 external interrupt S W P0 2 external interrupt
99. ck and initialize the internal CPU and peripheral modules This procedure brings the S3P80C5 C80C5 C80C8 into a known operating status To allow time for internal CPU clock oscillation to stabilize the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance The minimum required reset operation for a oscillation stabilization time is 16 oscillation clocks All system and peripheral control registers are then reset to their default hardware values see Tables 5 1 In summary the following sequence of events occurs during a reset operation Allinterrupts are disabled The watchdog function basic timer is enabled Ports 0 1 and 2 are set to input mode and all pull up resistors are disabled for the I O port pin circuits Peripheral control and data register settings are disabled and reset to their default hardware values see Table 5 1 The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed ELECTRONICS 8 3 RESET and POWER DOWN S3P80C5 C80C5 C80C8 HARDWARE RESET VALUES Tables 5 1 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent res
100. d as reset value And when the reset occurs from INTR the prime register value will be retained but it will be unknown states if it occurs from POR So an application which is using stop mode should be added specific S W which divide the system reset into STOP mode releasing or power on reset Following Programming Tip can be useful for more understanding 8 6 ELECTRONICS S3P80C5 C80C5 C80C8 RESET and POWER DOWN 8 PROGRAMMING TIP To Divide STOP Mode Releasing and POR This example shows how to enter the stop mode and how to know it is stop mode releasing or power on RESET ORG 0100H Reset address START DI LD BTCON 03h enable basic timer counter LD SPL 0FFH Initialize the system register CLR SYM CLR PP CLR EMT CLR IPR LD POCONH 00H Initialize the control register LD POCONL 00H LD POPUR 0FFH CHECK_RAM Check the RAM data whether it is stop mode releasing or Power On RESET LD RO Z0BFH If Power On Reset go to POR RESET CHK R CP RO GRO JR NE POR_RESET DEC RO CP RO 0BOH JR UGE CHK_R STOP_RESET STOP mode releasing JR MAIN POR_RESET LD RO 0FFH Power On Reset CHECK RAM data are failed so clear all RAM data RAM CLR CLR RO DJNJ RO RAMCLR LD Initialize the CHECK RAM data as default value ELECTRONICS 8 7 RESET and POWER DOWN PROGRAMMING TIP To Divide STOP Mode Releasing and POR Continued CHK_W MAIN ENT_STOP 8 8 LD DEC JR J
101. d from the writing program For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book NOTE Please one more check whether the selected device is S3P80A4 P80A8 P80A5 or S3P80B4 P80B8 P80B5 BOOK SPINE TEXT SAMSUNG Logo S3P80C5 C80C5 C80C8 Microcontrollers User s Manual Rev 1 May 2002
102. de Hex dst 4 7 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R13 o R1 OFH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111 ELECTRONICS 6 21 INSTRUCTION SET S3P80C5 C80C5 C80C8 BOR Bit or BOR BOR Operation Flags Format Examples 6 22 dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOZONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 3 6 07 Rb r0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H BOR 01H 2 R1 gt Register 01H 07H R1 0
103. ded to the register name for bit addressing S3P80C5 C80C5 C80C8 Name of individual bit or related bits Register ID FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Mode R Read only W Write only R W Read write Register location in the internal register file Register address Register name hexadecimal D5H Set 1 7 6 5s 4 3 2 a 9 x x x x X X x gt 0 R W R W R W R W R W R W Register addressing modelonly R W R W Carry Flag C EN Operation does not generate a carry or borrow condition Operation generates carry out or borrow into high order bit 7 Zero Flag Z EN Operation result is a non zero value Operation result is zero Sign Flag Operation generates positive number MSB 0 Operation generates negative number MSB 1 Bit number MSB Bit 7 LSB Bit 0 Description of the effect of specific bit settings Not used Addressing mode or modes you can use to modify register values 4 4 RESET value notation Not used x Undetermined value 0 Logic zero 1 2 Logic one Figure 4 1 Register Description Format ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS Basic Timer Control Register D3H Set 1 Bit Identifier 7 8 8 24 3 2 3 o 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Bit Addressin
104. e nnns nnn nnns 3 12 Relative Address Mode enhn nnns sss en nnn nnns 3 13 imimediate Mode IMM he edet unus Cus aO DUPLO RR ua te C ee tO veu Mt 3 14 S3P80C5 C80C5 C80C8 MICROCONTROLLER Chapter Control Registers Chapter 5 weht 5 1 Interrupt TYPeS 5 2 Interrupt Structur gt 2 7 o aset e ERR 5 3 Interrupt Vector Addresses 2 5 5 Enable Disable Interrupt Instructions El DI 2 System Level Interrupt Control Registers 5 7 5 8 5 9 System Mode Register SYM 20 5 10 Interrupt Mask Register IMR 5 11 Interrupt Priority Register IPR 5 12 Interrupt Request Register IRQ 2 5 14 Interrupt Pending Function Types 0 5 15 Interrupt Source Polling Sequence 0 5 16 Interrupt Service Routines 0 5 16 Generating Interrupt Vector Addresses 4 Nesting of Vectored Interrupts 22 2 2 4 290000000 senes Instruction Pointer 7 Fast Interrupt Processing 5 17 Chapter Instruction Set Overview 6 1 Register Addressing Addressing 20222990000140 16 6
105. e Used same micom before Quality of documentation Samsung reputation Customer Information Company Name Telephone number Signatures Person placing the order Technical Manager For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book NOTE Please one more check whether the selected device is S3P80A4 P80A8 P80A5 or S3P80B4 P80B8 P80B5 S3C80C5 C80C8 OTP FACTORY WRITING ORDER FORM 2 2 Device Number S3P80C5 S3P8 write down the ROM code number note Customer Checksums Company Name Signature Engineer Read Protection Yes Please answer the following questions 87 Are you going to continue ordering this device Yes No If so how much will you be ordering No pcs oe Application Product Model ID Audio Video LCD Databank Caller ID Industrials Home Appliance Other Please describe in detail its application NOTES 1 Telecom LCD Game Office Automation Once you choose a read protection you cannot read again the programming code from the EPROM 2 OTP Writing will be executed in our manufacturing site 3 writing program is completely verified by a customer Samsung does not take on any responsibility for errors occurre
106. e increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask dst src Test under mask 6 4 ELECTRONICS 3 80 5 80 5 80 8 Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF IDLE NOP RCF SBO SB1 SCF SRP src SRPO SIC SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6 5 INSTRUCTION SET S3P80C5 C80C5 C80C8 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7
107. e or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOZONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 3 6 67 Rb r0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND 1 01 1 gt R1 O6H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 000001 11B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit O value of register R1 destination leaving the value 06H 000001 10B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3P80C5 C80C5 C80C8 BCP Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The conte
108. e carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R 4 D1 IR Given Register 00H 9AH register 02H register OBCH and 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H 03H register 03H ODEH C 0 In the first example if general register contains the value 10011010B the statement SRA 00H shifts the bit values in register OOH right one bit position Bit zero 0 clears the flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in destination register OOH ELECTRONICS 6 79 INSTRUCTION SET S3P80C5 C80C5 C80C8 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 src src src If src 1 1 and src 0 Othen RPO 3 7 lt 3 7 If src 1 Oandsrc 0 1 then RP1 3 7 lt src 3 7 If src 1 O and src 0 Othen RPO 4 7 lt 4 7 RPO 3 lt 0 RP1 4 7 lt src 4 7 RP1 3 lt 1 source data bits one and zero LSB
109. e next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 5 6 ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur and according to the established priorities NOTE The system initialization routine that is executed following a reset must always contain an EI instruction to globally enable the interrupt structure During normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register Although you can manipulate 5 0 directly to enable or disable interrupts we recommend that you use the El and DI instructions instead SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains
110. e serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction No flags are affected Bytes Cycles Opcode Hex 1 4 Given SYM OOH EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM O is the enable bit for global interrupt processing ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 SP lt IP IP IP IP IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement After Address Address Data IP IP Address Address Data PC 40 Enter PC 40 Enter 41 Address 41 Address 42 Address L 42 Address L SP 43 Address H SP 43 Address H 20 110 Routine 21 IPL 50 22 Data 22
111. e which initiated Idle mode is executed NOTE Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode without reset To release Idle mode you can use either an external interrupt or an internally generated interrupt ELECTRONICS 8 9 RESET and POWER DOWN S3P80C5 C80C5 C80C8 SUMMARY TABLE OF STOP MODE AND IDLE MODE Table 8 2 Summary of Each Mode Item Mode IDLE STOP Approach Condition Vpp is higher than yp Vj yp lt Vpp Vpp is higher than yp Vi yp lt Vopn IDLE instruction STOPCON x A5H STOP instruction Release Source Interrupt TO T1 interrupt Counter A interrupt Ext interrupt PortO RESET POR LVD WDT 8 10 ELECTRONICS 3 80 5 80 5 80 8 PORTS PORTS OVERVIEW The S3P80C5 C80C5 C80C8 microcontroller has three bit programmable ports 2 Two ports PO P1 are 8 bit ports and P2 is a 3 bit port This gives a total of 19 I O pins in the S8P80C5 C80C5 C80C8 s 24 package Each port is bit programmable and can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special instructions are required For IR universal remote controller applications ports 0 and1 are usually configured to the keyboard matrix and port 2 is used to transmit the remote controller carrier signal or to indicate operating status by turning on a LED Table 9
112. ectly address another memory location Remember however that locations in set 1 cannot be accessed using Indirect Register addressing mode Program Memory Register File Z 8 bit Register aoo Register in One Operand Register File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3P80C5 C80C5 C80C8 INDIRECT REGISTER ADDRESSING MODE Continued Register File Example Instruction aa Program Peaster Pel 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS 3 80 5 80 5 80 8 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File 1 2 gt RPO or RP1 a RP Points to Start of Program Memory Woking J ee Working weet ADDRESS Register E Sre anae Address OPCODE Working Register 21 ef L1 Sample Instruction OR GR6 Value used in OPERAND Instruction Figure 3 5 Indirect Working Register Addressing to Register File
113. egister or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONICS See list of condition codes in Table 6 6 Rn n 0 15 Rn b n 0 15 b 0 7 Rn n 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where 0 2 14 addr addr 0 254 even number only Rn n 0 15 Rn or reg reg 0 255 n 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where 0 2 14 reg Rn reg 0 255 0 15 addr RRp addr range 128 to 127 where 0 2 14 addr RRp addr range 0 65535 where 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 6 9 INSTRUCTION SET S3P80C5 C80C5 C80C8 Table 6 5 Opcode Quick Reference ie ee ae ADD ADD ADD ADD A
114. endently point to one of the 24 8 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice 2 0 Not used for S3P80C5 C80C5 C80C8 4 24 ELECTRONICS S3P80C5 C80C5 C80C8 CONTROL REGISTERS SPL stack Pointer Low Byte D9H Set 1 Bit Identifier 7 6 8 4 3 2 3 29 X X X X X X X X RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The SP value is undefined following a reset Stop Control Register FBH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W Addressing Mode Register addressing mode only 7 0 Stop Control Register enable bits JEnbeSTOPON NOTES 1 get into STOP mode stop control register must be enabled just before STOP instruction 2 When STOP mode is released stop control register STOPCON value is cleared automatically 3 Itis prohibited to write another value into STOPCON ELECTRONICS 4 25 CONTROL REGISTERS S3P80C5 C80C5 C80C8 SYM System Mode Register DEH Set 1 RESET Value 0 E X X X 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Tri State External Interface
115. equence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given carry 0 CCF If the carry 0 the CCF instruction complements it in the FLAGS register 005 changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3P80C5 C80C5 C80C8 CLR Clear CLR dst Operation dst lt 0 Flags Format Examples 6 28 The destination location is cleared to 0 No flags are affected
116. er pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F2 r Given RO 77H R6 30H and R7 OOH LDCPD RR 6 RO RR6 lt RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR 6 RO RR6 RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples dst src r m 1 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes an even number for program memory and odd num
117. er pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 Slice 31 11111XXX Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX Figure 2 5 8 Byte Working Register Areas Slices 2 8 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline we recommend that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary
118. ernal interrupts at 0 3 0 0 are interrupt level IRQ6 Each interrupt has a separate vector address 2 You can assign pull up resistors to individual port 0 pins by making the appropriate settings to the POPUR register ELECTRONICS 4 15 CONTROL REGISTERS S3P80C5 C80C5 C80C8 POINT Port 0 External Interrupt Enable Register F1H Set 1 Bit Identifier _ 5 4 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R R R R Addressing Mode Register addressing mode only 7 0 7 External Interrupt INT4 Enable Bit Disable interrupt 1 Enable interrupt 6 0 6 External Interrupt INT4 Enable Bit Disable interrupt le Enable interrupt 5 0 5 External Interrupt INT4 Enable Bit Disable interrupt 1 Enable interrupt 4 0 4 External Interrupt INT4 Enable Bit Disable interrupt 1 Enable interrupt 3 0 3 External Interrupt INT3 Enable Bit Disable interrupt 1 Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit Disable interrupt 1 Enable interrupt PO External Interrupt INT1 Enable Bit Disable interrupt 1 Enable interrupt 0 P0 0 External Interrupt INTO Enable Bit Disable interrupt 1 Enable interrupt 4 16 ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS POPND Port 0 External Interrupt Pending Register F2H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0
119. es Cycles Opcode Addr Mode Hex dst src ope dst sre 2 10 C3 r Irr OpC src dst 2 10 D3 Irr r XSi opc src dst 3 12 F7 XSi r opc dst src XL XL 4 14 A7 r XL rr opc src dst XL XL 4 14 B7 XL rr r dst 0000 DA DA 4 14 DA opc dst 0001 DA DAY 4 14 A7 r DA opc src 0001 DA DAY 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 Forformats 3 and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address rr and the source address rr are each two bytes 4 The DA and r source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory ELECTRONICS S3P80C5 C80C5 C80C8 LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 0103H 4FH 0104H INSTRUCTION SET 34H R2 01H R3 04H Program memory locations 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC LDE LDC note LDE LDC LDE LDC note LDE LDC LDE LDC LDE LDC note LDE RO RR2 RO RR2 RR2 R0 RR2 R0 RO 01H RR2 RO 01H RR2 01H RR2 RO 01H RR2 RO 0 1000 RO 1 000H RR2 0 1104 0 1104
120. escriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual Data and counter registers are not described in detail in this reference section More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual ELECTRONICS 4 1 CONTROL REGISTERS S3P80C5 C80C5 C80C8 Table 4 1 Mapped Registers Set 1 Registerame mnemonic Hex nw medserpomero _ ro m RW Imemwteaesegser mo wm Rw R R RW R R Rw R 559 DEH DFH EOH E1H E2H tug RW RW RW RW E7H E8H E9H EAH EBH ECH RW I R note R W FOH F2H 3H F4H F6H F7H F8H 4 2 ELECTRONICS S3P80C5 C80C5 C80C8 CONTROL REGISTERS Table 4 1 Mapped Registers Continued Register Name Mnemonic Decimal nw Timer 1 aata register ow byte moara 29 RW 26 SToPCON 1 Locations is not eS NOTE You cannot use a read only register as a destination for the instructions OR AND LD or LDB ELECTRONICS 4 3 CONTROL REGISTERS Bit number s that is are appen
121. ess Added to Program Memory Offset or Data Memory 8 Bits 16 Bits Value used In OPERAND Instruction 16 Bits Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed NOTE LDE command is not available because an external interface is not implemented for the S3C80C5 C80C8 C80CA Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset ELECTRONICS 3 80 5 80 5 80 8 ADDRESSING MODES INDEXED ADDRESSING MODE Continued Register File S RPO or 1 gt RPO Selected Points 1 of orking OFFSET dics OFFSET Next 2 Bits 4 Bit Working Register Register Address OPCODE Point to Working Pair Register Pair 16 Bit Address LSB Selects Added to Program Memory Offset or Data Memory 8 Bits 16 Bits OPERAND Value used in Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed NOTE LDE command is not available because an external interface is not implemented for the S3C80C5 C80C8 C80CA Figure 3 9 Indexed Addressing to Program or Data Memory
122. et values 1 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset Adash means that the bit is either not used or not mapped but a 0 is read from the bit position Table 8 1 Set 1 Register Values After Reset BN SUN E ee moont se oon TimerOcontrolregister TOCON 210 O 0 0 Basic timer control register BTCON 211 0 0 0 0 Clock control register CLKCON 22 O O 0 System flags register 1 FLAGS 213 DSH x x x x x x 0 0 aa Register pointer 4 1 215 1 4 0 of 4 Location D8H SPH is not mapped Stack pointer low byte 94 217 x x x x x x x x Instruction pointer high byte IPH 218 DAH x x x x x x x x Instruction pointer byte 219 DBH x x x x x x x x Interrupt request register read only IRQ 220 DCH 0 Interrupt mask register 221 DDH x x x x x x x x ee eee H Register page pointer DFH 0 0 0 0 ge ORA RED EAD ERR EDD ER 2dataregisior P Location E3H E6H is not mapped meu
123. etic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 2 4 12 EL 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 03H flag 1 register 01H 20H register 02H 03H register OAH ADC R1 R2 gt 1 14H R2 03H ADC R1 R2 gt 1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H gt gt ADC 01H 02H Register 01H 2BH register 02H 03H ADC 01H 11H Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET ADD ADD dst src Opera
124. ex dst src 2 4 32 6 33 r Ir opc SIC dst 3 6 34 R R 6 35 R IR opc dst SIC 3 6 36 R IM Given R1 10H R2 1 register 01H 20H register 02H and register OAH SBC R1 R2 SBC R1 R2 R1 OCH R2 03H R1 05H R2 register OAH SBC 01H 02H Register 01H 1CH register 02H SBC 01H 02H Register 01H 15H register 02H register OAH SBC 01H 8AH gt Register 01H 95H C S and V 1 gt gt gt gt In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3P80C5 C80C5 C80C8 SCF set Carry Flag SCF Operation Flags Format Example 6 78 lt 1 The carry flag is set logic regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles Opcode Hex ope 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET SRA Shift Right Arithmetic SRA Operation dst dst 7 lt dst 7 lt dst 0 dst lt dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces th
125. exible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI 6 2 Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src Src dst src dst src S3P80C5 C80C5 C80C8 Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load externa
126. fected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 rC r r8 r dst 2 4 9 R r OtoF 2 4 C7 r D7 Ir E5 R dst src 3 6 E6 R D6 IR opc SIC dst 3 6 F5 IR 3 6 87 r opc 3 6 9 ELECTRONICS sre IM R x r 6 49 INSTRUCTION SET LD Load LD Continued S3P80C5 C80C5 C80C8 Examples Given RO 01H R1 OAH register 01H register 01H 20H register 02H 02H LOOP and register OFFH LD LD LD LD LD LD LD LD LD LD LD LD 6 50 RO 10H 0 01 01H RO R1 RO RO R1 00H 01H 02H 00H 00H 0AH 00H 10H 00H 02H gt RO LOOP R1 gt LOOP RO R1 gt RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01H 20H Register 02H 20H register 00 01H Register OOH OAH Register 00H 01H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 OAH Register 31H OAH RO 01H R1 OAH ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affec
127. following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3P80C5 C80C5 C80C8 Table 6 2 Flag Notation Conventions Flag Deseription 2 5 V D H 0 1 6 8 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of r
128. g Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset ajoja Disable watchdog timer function Any other value Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits 1 1 Invalid setting not used for S3P80C5 C80C5 C80C8 4 Basic Timer Counter Clear Bit 1 No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 2 No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cleared to O 2 When you write a 1 to 0 the corresponding frequency divider is cleared 00H Immediately following the write operation the 0 value is automatically cleared to O ELECTRONICS 4 5 CONTROL REGISTERS S3P80C5 C80C5 C80C8 CACON Counter A Control Register F3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Counter A Input Clock Selection Bits 5 4 Counter A Interrupt Timing Selection Bits Elapsed time for Low data value Elapsed time for High data value 1 Elapsed time for combined Low and High data values Invalid setting not used for S3C80C5 C80C8 3 Counter A Interrupt Enable Bit Disable interr
129. gh order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or RP1 Address These Address Bits Indicate 8 bit 8 bit Logical Working Register Address Addressing Register Pointer hree low Provides Five order Bits High order Bits 1 8 bit Physical Address Figure 2 13 8 Bit Working Register Addressing 2 16 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES Selects RP1 R11 8 bit Address Form Instruction LD R11 R2 Specifies Working Register Addressing Register Address 10 10 1 0 1 1 Figure 2 14 8 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES S3P80C5 C80C5 C80C8 SYSTEM AND USER STACKS S3C8 series microcontrollers use the system stack for subroutine calls and returns and to store data The PUSH and POP instructions are used to control system stack operations The S3P80C5 C80C5 C80C8 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RE
130. gister file Bank 1 is not implemented in some KS88 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex OpC 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET SBC subtract with Carry SBC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands C Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode H
131. h bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Read only Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the othe
132. he statement POPUD 02H 00H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 900H gt Register OOH 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02 00 loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3P80C5 C80C5 C80C8 PUSH Push To Stack PUSH Operation Flags Format Examples 6 66 src SP lt SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation
133. he timer 0 match interrupt TOINT TOOVF is interrupt level IRQO vector TOINT also belongs to interrupt level IRQO but is assigned the separate vector address FCH A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced The TOINT pending condition must however be cleared by the application s interrupt service routine by writing a 0 to the TOCON O interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the TO reference data register TODATA The match signal generates a timer 0 match interrupt TOINT vector FCH and clears the counter If for example you write the value 10H to TODATA and OBH to TOCON the counter will increment until it reaches 10H At this point the TO interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer 0 output pin is inverted see Figure 10 3 IRQO INT Pending TOCON 0 Interrupt Enable Disable TOCON 1 TOCON 5 Buffer Register TOCON 4 Match Signal TOCON 3 Data Register Figure 10 3 Simplified Timer 0 Function Diagram Interval Timer Mode ELECTRONICS 10 5 BASIC TIMER and TIMER 0 S3P80C5 C80C5 C80C8 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the
134. here are two types of interrupt pending bits One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed and the other type must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with either type of pending condition clear function by hardware or by software Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends 5 18 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Fl
135. high order bit 7 6 Zero Flag Z Operation result is a non zero value 1 Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 1 Operation generates negative number MSB 1 4 Overflow Flag V Operation result is lt 127 or gt 128 Operation result is gt 127 lt 128 3 Decimal Adjust Flag D Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 Fast Interrupt Status Flag FIS 70 Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag BA Bank 0 is selected normal setting for S3C80C5 C80C8 Invalid selection bank 1 is not implemented ELECTRONICS 4 9 CONTROL REGISTERS S3P80C5 C80C5 C80C8 IMR Interrupt Mask Register DDH Set 1 Bit Identifier 85 4 3 2 4 j 9 X X X X X X X RESET Value x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit External Interrupts 0 7 0 4 1 Enable un mask 6 Interrupt Level 6 IRQ6 Enable Bit External Interrupts 0 3 0 0 Disable mask 1 Enable un mask Not used for S3P80C5 C80C5 C80C8 4 Interrupt Level 4 IRQ4 Enable
136. iagram Interval Timer Mode 11 2 ELECTRONICS S3P80C5 C80C5 C80C8 TIMER 1 T1CON 2 T1CON 7 6 ovr gm 5 T1CON 3 fosc 4 Bir Clear E gt 16 Bit Up Counter _ 4 g 5 MU Read Only E fosc 16 Match rote 16 Bit Comparator T1CON 1 Timer 1 High Low T1CON 5 4 1 0 Buffer Register Timer 1 Data High Low Register Data Bus T1CON 3 Match Signal TIOVF NOTES Match signal is occured only in interval mode Figure 11 2 Timer 1 Block Diagram ELECTRONICS 11 3 TIMER 1 S3P80C5 C80C5 C80C8 TIMER 1 CONTROL REGISTER T1CON The timer 1 control register 1 is located in set 1 and is read write addressable T1CON contains control settings for the following T1 functions Timer 1 input clock selection Timer 1 operating mode selection Timer 1 16 bit down counter clear Timer 1 overflow interrupt enable disable Timer 1 match interrupt enable disable Timer 1 interrupt pending control read for status write to clear A reset operation clears T1CON to 00H selecting fosc divided by 4 as the T1 clock configuring timer 1 as a normal interval timer and disabling the timer 1 interrupts Timer 1 Control Register T1CON FAH R W Timer 1 input clock selection bits Timer 1 match interrupt pending bit 00 fosc 4 0 No interrupt pending 01 fosc 8 0 Clear pending bit write 10 fosc 16 1 Interrupt is pending 11 2 Internal c
137. interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register iw RW Function Description Interrupt mask register IMR R W Bit settings in the IMR register enable or disable interrupt processing for each of the five interrupt levels IRQO IRQ1 IRQ4 and IRQ6 IRQ7 Interrupt priority register R W Controls the relative processing priorities of the interrupt levels The five levels of the S3P80C5 C80C5 C80C8 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ4 and group C is IRQ6 and IRQ7 Interrupt request register EAE This register contains a request pending bit for each interrupt level System mode register SYM R W Dynamic global interrupt processing enable disable fast interrupt processing and external interface control An external memory interface is not implemented in the S3P80C5 C80C5 C80C8 microcontroller ELECTRONICS 5 7 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are therefore Global i
138. ion Flags Format Example 6 86 The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F 1 2 3 The following sample program structure shows the sequence of operations that follow WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3P80C5 C80C5 C80C8 XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst lt dst src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results 1 bit being stored whenever the corresponding bits in the operands are different otherwise a bit is stored Unaffected Always reset to 0 Unaffected Unaffected lt SIC dst opc dst SIC Set if the result is 0 cleared otherwise Setif the result bit 7 is set cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst 2 4 B2 r B3 r 3 6 B4 R B5 R 3 6 B6 R src r Given RO 0C7H R1 02H R2 18
139. ion Clock 1 33 MHz 1 00 MHz 670 kHz 500 kHz 250 kHz 8 32 kH 400 kH pe Supply Voltage V Instruction Clock 1 6n x oscillator frequency n 1 2 8 16 A1 7V 4MHz b2 0V 8MHz Figure 13 2 Operating Voltage Range of S3P80C5 C80C5 C80C8 13 6 ELECTRONICS 3 80 5 80 5 80 8 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3P80C5 C80C5 C80C8 microcontroller is currently available a 24 SOP and SDIP package 10 30 0 30 7 50 0 20 0 85 0 20 15 74 MAX 15 34 0 20 2 50 MAX gt 5 0 10 WAX NOTE Dimensions are in millimeters Figure 14 1 24 Pin SOP Package Mechanical Data ELECTRONICS 14 1 MECHANICAL DATA S3P80C5 C80C5 C80C8 24 SDIP 300 6 40 0 20 23 35 MAX 22 95 0 20 5 08 MAX e Te e 3 30 0 30 NOTE Dimensions are in millimeters Figure 14 2 24 Pin SDIP Package Mechanical Data 14 2 ELECTRONICS S3C8 SERIES MASK ROM ORDER FORM Product description Device Number 3 5 53 80 8 S3C write down the ROM code number note Product Order Form Package Pelet Wafer Package Type Package Marking Check One Standard Custom A Custom 10 chars 10 chars each line SEC YWW YWW YWW Device Name Device Name ___ H Assembly site code Y Last number of assembly year WW Week of asse
140. it product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET S3P80C5 C80C5 C80C8 NEXT next NEXT Operation Flags Format Example Address 6 60 IP IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex ope 1 10 OF The following diagram shows one example of how to use the NEXT instruction Before Data Address H 01 Address H Address L Address L Address H Address H Routine ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET NOP No Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex ope 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3P80C5 C80C5 C80C8 OR Logical OR OR Operation Flags Format Examples 6 62 dst src dst lt dst OR src The source operand is logically ORed with the destination operand
141. it up counter When you set the timer 1 overflow interrupt enable bit T1CON 2 to 1 the overflow interrupt is generated each time the 16 bit up counter reaches FFFFH After the interrupt request is generated the counter value is automatically cleared to OOH and up counting resumes By writing a 1 to T1CON 3 you can clear reset the 16 bit counter value at any time during program operation TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt IRQ1 vector F6H whenever the 16 bit counter value matches the value that is written to the timer 1 reference data registers T1DATAH and T1DATAL When a match condition is detected by the 16 bit comparator the match interrupt is generated the counter value is cleared and up counting resumes from In match mode program software can poll the timer 1 match interrupt pending bit T1 CON O to detect when timer 1 match interrupt pending condition exists T1CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a 0 to T1 CON O IRQ1 T1INT Pending T1CON 0 Interrupt Enable Disable T1CON 2 16 Bit UP Counter Read Only 16 Bit Comparator Timer 1 High Low CN Buffer Register N Match Signal Timer 1 Data High Low Buffer Register T1CON 3 Figure 11 1 Simplified Timer 1 Function D
142. l data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3P80C5 C80C5 C80C8 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compar
143. le 9 2 Port Data Register Summary C register Name Mnemonic Decimal Port 1 data register Port 2 data register Because port 2 is a 3 bit I O port the port 2 data register only contains values for P2 0 P2 1 and P2 2 The P2 register also contains values for P2 0 P2 1 and P2 2 The P2 register also contains a special carrier on off bit P2 5 See the port 2 description for details All other S3P80C5 C80C5 C80C8 ports are 8 bit PULL UP RESISTOR ENABLE REGISTERS PortO Pull up Resistor Enable Register POPUR E7H R W P0 7 PO 6 P0 5 0 4 PO 3 PO 2 PO 00 Pull up resistor enable bit 0 Enable pull up resistor 1 Disable pull up resistor NOTE Pull up resistors can be assigned to the port 2 pins P2 0 P2 1 and P2 2 by marking the appropriate the port 2 control register P2CON Figure 9 1 S3P80C5 C80C5 C80C8 I O Port 0 Data Register Format 9 2 ELECTRONICS S3P80C5 C80C5 C80C8 PORTS Port1 Pull up Resistor Enable Register P1PUR ECH R W P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Pull up resistor enable bit 0 Disable pull up resistor 1 Enable pull up resistor Pull up resistors can be assigned to the port 2 pins P2 0 P2 1 and P2 2 by marking the appropriate the port 2 control register P2CON NOTE Figure 9 2 S3P80C5 C80C5 C80C8 I O Port 1 Data Register Format ELECTRONICS 9 3 PORTS S3P80C5 C80C5 C80C8 PORT 0 Port 0 is a general purpose 8 bit I O port It i
144. le ROM The S3P80C5 is the microcontroller which has one time programmable EPROM Using a proven modular design approach Samsung engineers developed the S3P80C5 C80C5 C80C8 by integrating the following peripheral modules with the powerful SAM87 RC core Three programmable ports including two 8 bit ports and one 3 bit port for a total of 19 pins Internal LVD circuit and eight bit programmable pins for external interrupts One 8 bit basic timer for oscillation stabilization and watchdog functions system reset One 8 bit timer counter and one 16 bit timer counter with selectable operating modes One 8 bit counter with auto reload function and one shot or repeat control The S3P80C5 C80C5 C80C8 is a versatile general purpose microcontroller which is especially suitable for use as remote transmitter controller It is currently available in a 24 pin SOP and SDIP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM87RC CPU Memory Program memory ROM S3C80C8 8 Kbyte 0000H 1FFFH S3C80C5 15 872 byte 0000H 3E00H Data memory 256 byte RAM Instruction Set e 78 instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time e 1000 ns at 4 MHz fosc minimum Interrupts e 13 interrupt sources with 10 vector e blevel 10 vector interrupt structure Ports Two 8 bit I O ports PO P1 and one 3 bit port P2 for a
145. lear Bit No effect when write Clear T1 counter when write 2 Timer 1 Overflow Interrupt Enable Bit note 0 Disable T1 overflow interrupt Enable T1 overflow interrupt Timer 1 Match Capture Interrupt Enable 0 Disable T1 match interrupt Enable T1 match interrupt 0 Timer 1 Match Capture Interrupt Pending Flag No T1 match interrupt pending when read E Clear T1 match interrupt pending condition when write T1 match interrupt is pending when read No effect when write NOTE Atimer 1 overflow interrupt pending condition is automatically cleared by hardware However the timer 1 match capture interrupt IRQ1 vector F6H must be cleared by the interrupt service routine 4 28 ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM87 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels
146. ll semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea Box 37 Suwon 440 900 TEL 82 31 209 1934 FAX 82 31 209 1899 Home Page http Wwww samsungsemi com Printed in the Republic of Korea Preface The S3C80C5 C80C8 Microcontroller User s Manual is designed for application designers and programmers who are using the S3C80C5 C80C8 microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C80C5 C80C8 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter
147. lock 7 Open Pin C2 XOUT XOUT Figure 7 1 Main Oscillator Circuit Figure 7 2 External Clock Circuit External Crystal or Ceramic Resonator ELECTRONICS 7 1 CLOCK CIRCUITS S3P80C5 C80C5 C80C8 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator started by Power On Reset operation or by a non vectored interrupt interrupt with reset INTR To enter the Stop mode STOPCON STOP Control register has to be loaded with value 0A5H before STOP instruction execution After recovering from the Stop mode by reset or interrupt STOPCON register is automatically cleared n Idle mode the internal clock signal is gated away from the CPU but continues to be supplied to the interrupt structure timer 0 and counter A Idle mode is released by a reset or by an interrupt external or internally generated STOP STOPCON Instruction CLKCON 3 4 Oscillator Stop Oscillator Wake up Noise filter INT Pin NOTES 1 An external interrupt with an RC delay noise filter for S3C80C5 C80C8 INTO 4 is fiexed to release Stop mode and wake up the main oscillator Because the 53 80 5 80 8 has no subsystem clock the 3 bit signature code CLKCON 2 CLKCON 0 is no meaning Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS 3 80 5 80 5
148. lock T F F Timer 1 match interrupt enable bit Timer 1 operating mode selection bits 0 Disable interrupt Interval mode 1 Enable interrupt Overflow mode OVF interrupt can occur 01 Overflow mode OVF interrupt can occur 01 Overflow mode OVF interrupt can occur Timer 1 overflow interrupt enable bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 1 counter clear bit 0 No effect 1 Clear the timer 1 counter when write Figure 11 3 Timer 1 Control Register T1CON 11 4 ELECTRONICS S3P80C5 C80C5 C80C8 TIMER 1 Timer 1 Counter High Byte Register T1 CNTH F6H Set 1 R Reset Value 00H Timer 1 Counter Low Byte Register T1CNTL F7H Set 1 R Reset Value 00H Timer 1 Data High Byte Register T1DATAH F8H Set 1 R W Reset Value FFh Timer 1 Data Low Byte Register T1DATAL F9H Set 1 R W Reset Value FFh Figure 11 4 Timer 1 Registers ELECTRONICS 11 5 TIMER 1 S3P80C5 C80C5 C80C8 NOTES 11 6 ELECTRONICS S3P80C5 C80C5 C80C8 COUNTER A COUNTER OVERVIEW The S3P80C5 C80C5 C80C8 microcontroller has an 8 bit counter called counter A Counter A which can be used to generate the carrier frequency has the following components see Figure 12 1 Counter A control register CACON 8 bit down counter with auto reload function Two 8 bit reference data registers CADATAH and CADATAL Counter A has two functions Asanormal inte
149. lue Return from interrupt service routine ELECTRONICS 3 80 5 80 5 80 8 TIMER 1 11 OVERVIEW The S3C80C5 C80C8 microcontroller has a 16 bit timer counter called timer 1 T1 For universal remote controller applications timer 1 can be used to generate the envelope pattern for the remote controller signal Timer 1 has the following components One control register T1 CON set 1 FAH R W Two 8 bit counter registers and T1CNTL set 1 and F7H read only Two 8 bit reference data registers T1DATAH and T1DATAL set 1 F8H and F9H R W A 16 bit comparator You can select one of the following clock sources as the timer 1 clock Oscillator frequency fosc divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 1 in two ways As anormal free run counter generating a timer 1 overflow interrupt IRQ1 vector at programmed time intervals To generate a timer 1 match interrupt IRQ1 vector F6H when the 16 bit timer 1 count value matches the 16 bit value written to the reference data registers In the S3C80C5 C80C8 interrupt structure the timer 1 overflow interrupt has higher priority than the timer 1 match ELECTRONICS 11 1 TIMER 1 S3P80C5 C80C5 C80C8 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt IRQ1 F4H whenever an overflow occurs in the 16 b
150. m T 231 POCONH POCONL E9H 8 4 ELECTRONICS S3P80C5 C80C5 C80C8 RESET and POWER DOWN Table 8 1 Set 1 Register Values After Reset Continued mem Hex 7 6 5 2 51419191 Port control register high byte PICONH 254 EAH o 0 0 0 Port 1 control register low byte PICONL 235 EBH o o o o o Port 1 pull up enable register PiPur 236 ECH o o o o o 0 Location EDH EFH is not mapped Port 2 control register 2o FH o o e e e o 0 interrupt enable register Pont 24 o o o Port 0 interrupt pending register POPND 242 0 CowtrAcomolrgster cacon 243 Fan o o o o o imer 1 counter register high byte TICNTH 246 Fen o 6 6 0 6 6 Timer counter register ow byte TiGNTL 247 Fm o o o o o o 0 0 Timer 1 control register NOTES 1 Although the SYM register is not used for the S3P80C5 C80C5 C80C8 SYM 5 should always be 0 If you accidentally write a 1 to this bit during normal operation a system malfunction may occur 2 Except for TOCNT IRQ T1CNTL and BTCNT which are read only all registers set 1 are read write addressable 3 You cannot use a read only register as a destination field for the instructions OR AND LD and LDB 4 Interrupt pending fl
151. mbly Delivery Dates and Quantities ROM code Po Not applicable See ROM Selection Form Please answer the following questions For what kind of product will you be using this order New product Upgrade of an existing product Replacement of an existing product Other If you are replacing an existing product please indicate the former product name 8 Whatare the main reasons you decided to use a Samsung microcontroller in your product Please check all that apply Price Product quality Features and functions Development system Technical support Delivery on time Used same micom before Quality of documentation Samsung reputation Mask Charge US Won Customer Information Company Name Telephone number Signatures Person placing the order Technical Manager For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book NOTE Please one more check whether the selected device is S380A4 C80A8 C80A5 or S3C80B4 C80B8 C80B5 5 8 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information Company Name Department Telephone Number Fax Date Risk Order Information Device 3 5 53 80 8 S3C write down the ROM code number n
152. nted by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET 3 80 5 80 5 80 8 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example 6 32 dst src RA If dst src 0 lt RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src ope 3 12 D2 Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 03H 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer regi
153. nterrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing the part of your application program that handles interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Polling Register Read only Cycle IRQO IRQ1 IRQ4 and IRQ6 IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer 0 match or timer 0 TOCON note D2H overflow TODATA D1H Timer 1 match or timer 1 IRQ1 T1CON note FAH overflow T1DATAH T1DATAL F8H F9H Counter A IRQ4 CACON F3H CADATAH CADATAL F4H F5H 0 7 external interrupt IRQ7 E8H 6 external interrupt F1H P0 5 external interrupt F2H
154. nts of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst 4 57 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit addres
155. on The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 4 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register 00H 55H 1 RL 01H gt Register 01H 02H register 02H 2 0 In the first example if general register 00H contains the value 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3P80C5 C80C5 C80C8 RLC Rotate Left Through Carry RLC Operation dst dst 0 lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples 6 72 C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise
156. on immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE TX Program Memory Address Used RENE Go EN Current Instruction OPCODE Signed Displacement dC Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3P80C5 C80C5 C80C8 IMMEDIATE MODE IM In Immediate IM mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD Figure 3 14 Immediate Addressing 3 14 ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section detailed descriptions of the S3P80C5 C80C5 C80C8 control registers are presented an easy to read format You can use this section as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register d
157. or S3P80C5 C80C5 C80C8 4 Level 4 IRQ4 Request Pending Bit Counter A Interrupt Not pending Pending Not used for S3P80C5 C80C5 C80C8 T Level 1 IRQ1 Request Pending Bit Timer 1 Match or Overflow Not pending Pending 0 Level 0 IRQO Request Pending Bit Timer 0 Match or Overflow Not pending 1 Pending NOTE Interrupt level IRQ2 IRQ3 and is not used in the S3P80C5 C80C5 C80C8 interrupt structure ELECTRONICS 4 1 CONTROL REGISTERS S3P80C5 C80C5 C80C8 POCONH Port 0 Control Register High Byte E8H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 0 7 1 4 Mode Selection Bits C MOS input mode interrupt falling edges ESSEN C MOS input mode interrupt on rising and falling edges 1 Push pull output mode C MOS input mode interrupt on rising edges 5 4 0 61 4 Mode Selection Bits input mode 72111 Tomos input mode inerupt on ising ana taling edges Pi 0 3 2 P0 5 INT4 Mode Selection Bits input mode teruptonfaling edges 79111 input mode inerupt on ising ana taling edges Pi fo OOS 1 0 0 41 4 Mode Selection Bits C MOS input mode interrupt falling edges C MOS input mode interrupt on rising and falling edges
158. ority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the above procedure to some extent INSTRUCTION POINTER IP The instruction pointer IP is used by all S3C8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The IP register names are IPH high byte 15 8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in approximately six clock cycles instead of the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 ELECTRONICS 5 17 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and
159. ory address range is therefore 0000H 3E00H of ROM The S3C80C8 has 8 Kbyte 0000H 1FFFH of internal programmable program memory see Figure 2 1 The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you do use the vector address area to store program code be careful to avoid overwriting vector addresses stored in these locations The ROM address at which program execution starts after a reset is 0100H Decimal 15 872 15 Kbyte S3C80C5 Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES REGISTER ARCHITECTURE The S3P80C5 C80C5 C80C8 register file has 312 registers The upper 64 bytes register files are addressed as system control register and working register The lower 192 byte area of the physical register 00 contains freely addressable general purpose registers called prime registers It can be also used for stack operation The extension of register space into separately addressable sets is supported internally by addressing mode restrictions Specific register types and the area in bytes they occupy the S3P80C5 C80C5 C80C8 internal register space are summarized in Table 2 1 Table 2 1 S3P80C5 C80C5 C80C8 Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte
160. ote Package Number of Pins Package Type Intended Application Product Model Number Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to be in full compliance with all SEC production specifications and to this extent agree to assume responsibility for any and all production risks involved Order Quantity and Delivery Schedule Risk Order Quantity PCS Delivery Schedule Signatures Person Placing the Risk Order SEC Sales Representative For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book NOTE Please one more check whether the selected device is S380A4 C80A8 C80A5 or S3C80B4 C80B8 C80B5 53 80 5 80 8 MASK OPTION SELECTION FORM Device __ 3 80 5 53 80 8 5368 write down the ROM code number note Attachment Check one Diskette PROM Customer Checksum Company Name Signature Engineer Please answer the following questions e Application Product Model ID Audio LCD Databank Caller ID LCD Game Industrials Office Automation Remocon Other Please describe in detail its applica
161. p to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET CPIJE Compare Increment and Jump on Equal Operation Flags Format Example dst src RA If dst src 0 PC PC RA 1 The source operand is compared to subtracted from the destination operand If the result is 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 7 row NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 02H R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is increme
162. perand are incremented by one Unaffected Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected Flags TOSONOE Format Bytes Cycles dst opc 1 4 opc dst 2 4 Examples Given RO 1BH register OOH OCH and register 1BH OFH INC RO gt RO 1CH INC OOH gt Register INC RO RO 1 register 01H 10H S3P80C5 C80C5 C80C8 Opcode Addr Mode Hex dst rE r r to 20 R 21 IR In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register 00H assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H 6 44 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise V Set if arithmetic overflow
163. r complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET
164. r type must be cleared by the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the SSP80C5 C80C5 C80C8 interrupt structure the timer 0 and timer 1 overflow interrupts IRQO and IRQ1 and the counter A interrupt IRQ4 belong to this category of interrupts whose pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit must be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S8P80C5 C80C5 C80C8 interrupt structure pending conditions for all interrupt sources except the timer 0 and timer 1 overflow interrupts and the counter A borrow interrupt must be cleared by the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 INTERR
165. racts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET SWAP Swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 lt gt dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R 4 F1 IR Given Register OOH register 02H 03H and register OA4H SWAP OOH gt Register OOH OE3H SWAP 02H gt Register 02H register In the first example if general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value 1110001 1B ELECTRONICS 6 83 INSTRUCTION SET S3P80C5 C80C5 C80C8 TCM rest Complement Under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination ope
166. rand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 62 6 63 r Ir opc SIC dst 3 6 64 R R 6 65 R IR opc dst SIC 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register OOH 2BH register 01H 02H and register 02H 23H TCM RO R1 TCM RO R1 TCM 00H 01H TCM 00H 01H RO 0C7H R1 02H Z 1 RO 0C7H R1 02H register 02H 23H Z 0 Register OOH 2BH register 01H 02H Z 1 Register 00H 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register 00H 2BH Z 0 E gt EN In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET Test Under Mask Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a
167. rator Counter A 1 3 PRODUCT OVERVIEW PIN ASSIGNMENTS 1 4 XOUT TEST PO O INTO INTR RESET PO0 2 INT2 INTR PO S INT3 INTR PO 4 INTA4 INTR PO 5 INT4 INTR PO 6 INT4 INTR PO 7 INT4 INTR O S3C80C5 C80C8 24 SOP SDIP TOP VIEW S3P80C5 C80C5 C80C8 VDD P2 2 P2 1 REM SCLK P2 0 TOPWN TOCK SDAT P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Figure 1 2 Pin Assignment Diagram 24 Pin SOP SDIP Package ELECTRONICS S3P80C5 C80C5 C80C8 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 Pin Descriptions Circuit 24 Pin Shared ln es Number Functions P0 0 PO0 7 port with bit programmable pins 5 12 INTO INT4 INTR Configurable to input or push pull output mode Pull up resistors are assignable by software Pins can be assigned individually as external interrupt inputs with noise filters interrupt enable disable and interrupt pending control Interrupt with Reset INTR is assigned to Port 0 1 0 1 7 port with bit programmable pins 13 20 Configurable to input mode or output mode Pin circuits are either push pull or n channel open drain type Pull up resistors are assignable by software System clock input and output pins Test signal input pin for factory use only must be connected to Vgs em 3 bit port with bit programmable pins 21 23 REM TOCK Configurable to input mode push pull output mode
168. rce operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 52 6 53 r Ir opc SIC dst 3 6 54 R R 55 R IR opc dst SIC 3 6 56 R IM Given R1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02 03H 01H 02H gt Register 01H 00H register 02 03H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst O lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the sourc
169. rol registers are cleared to 00H configuring port 0 initially to Input mode To assign pull up resistors to P1 pins you make the appropriate settings to the port 1 pull up resistor enable register P1PUR Port 1 Control Register High Byte P1 CONH EAH Set 1 R W Input mode Open drain output mode Push pull output mode Invalid setting Figure 9 7 Port 1 High Byte Control Register P1CONH ELECTRONICS 9 7 VO PORTS S3P80C5 C80C5 C80C8 Port 1 Control Register Low Byte P1CONL EBH Set 1 R W Input mode Open drain output mode Push pull output mode Invalid setting Figure 9 8 Port 1 Low Byte Control Register P1CONL 9 8 ELECTRONICS S3P80C5 C80C5 C80C8 PORTS PORT 2 Port 2 is a bit programmable 3 bit I O port Port 2 pins are accessed directly by read write operations to the port 2 data register P2 set 1 E2H You can configure port 2 pins individually to Input mode open drain output mode or push pull output mode P2 0 P2 1 P2 2 are configured by writing 6 bit data value to the port 2 control register 2 You configure these pins to support input functions Input mode with or without pull up for TOCK or output functions push pull or open drain output mode for REM and timer 0 PWM Port 2 pins have high current drive capability to support LED applications A reset operation clears P2CON to 00H selecting Input mode as the initial port 2 function Port 2 Control Regis
170. rred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Given Register OOH 31H register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H 1 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register contains the value 31H 00110001B the statement RR OOH rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000 in the destination register The initial bit zero also resets the C to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3P80C5 C80C5 C80C8 RRC Rotate Right Through Carry RRC Operation dst dst 7 C lt dst 0 dst lt dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples 6 74 C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination ch
171. rupts 1 High Tri state Fast interrupt enable bit Not used for the S3C80C5 C80C8 Fast interrupt level 0 Disable fast interrupt selection bits 1 Enable fast interrupt IRQO IRQ1 Not used Not used Not used Not used IRQ6 IRQ7 4A 0000 NOTE An external memory interface is not implemented Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W Not used Interrupt level enable bits 7 6 4 1 0 0 Disable mask interrupt 1 Enable un mask interrupt Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8
172. rval timer generating a counter A interrupt IRQ4 vector ECH at programmed time intervals To supply aclock source to the 16 bit timer counter module timer 1 for generating the timer 1 overflow interrupt ELECTRONICS 12 1 COUNTER A S3P80C5 C80C5 C80C8 CACON 6 7 0 To Other Block P3 1 REM Interrupt Control Counter A Data CACON 2 CACON 4 5 Low Byte Register Counter A Data High Byte Register Data Bus NOTES The value of the CADATAL register is loaded into the 8 bit counter when the operaion of the counter A Starts If a borrow occurs in the counter the value of the CADATAH register is loaded into the 8 bit counter However if the next borrow ovvurs the value of the CADATAL register is loaded into the 8 bit counter Figure 12 1 Counter A Block Diagram 12 2 ELECTRONICS 3 80 5 80 5 80 8 COUNTER COUNTER A CONTROL REGISTER The counter A control register CACON is located in set 1 bank 0 F3H and is read write addressable CACON contains control settings for the following functions see Figure 12 2 Counter A clock source selection Counter A interrupt enable disable Counter A interrupt pending control read for status write to clear Counter A interrupt time selection Counter A Control Register CACON F3H Set 1 R W Counter A input clock Counter A output flip flop selection bits control bit 00 fosc 0 T FF is Low
173. s b is three bits and the LSB address value is one bit in length Given R1 07H BITC R11 o R1 05H If working register R1 contains the value 07H 000001 11B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101 in register R1 Because the result of the complement is not 0 the zero flag 2 in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3P80C5 C80C5 C80C8 BITR Bit Reset BITR Operation Flags Format Example 6 20 dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst 4 7 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H R11 o R1 05H If the value of working register R1 is 07H 00000111B the statement R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET BITS Bit Set BITS dst b Operation dst b 1 Flags Format Example The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mo
174. s bit programmable Port 0 pins are accessed directly by read write operations to the port 0 data register PO set 1 The PO pin circuits support pull up resistor assignment using POPUR register settings and all pins have noise filters for external interrupt inputs Two 8 bit control registers are used to configure port 0 pins POCONH set 1 E8H for the upper nibble pins P0 7 P0 4 and POCONL set 1 E9H for lower nibble pins PO 3 PO0 0 Each control register byte contains four bit pairs and each bit pair configures one pin see Figures 9 2 and 9 3 A hardware reset clears all PO control and data registers to 00 A separate register the port 0 interrupt control register POINT set 1 F1H is used to enable and disable external interrupt input You can poll the port 0 interrupt pending register POPND to detect and clear pending conditions for these interrupts The lower nibble pins 0 3 0 0 are used for INT3 INTO input IRQ6 respectively The upper nibble pins P0 7 P0 4 are all used for INT4 input IRQ7 Interrupts that are detected at any of these four pins are processed using the same vector address E8H Port 0 P0 0 PO 7 is assigned interrupt with reset INTR to release stop mode with system reset Port 0 Control Register High Byte POCONH E8H Set 1 R W mm 4 INT4 mn 5 INT4 PO 6 INT4 PO 7 INT4 POCONH Pin Configureation Settings Input mode interrupt on falling edges Input mode interrup
175. s initialization routine must enable the required external interrupts for port 0 and for the other I O ports ELECTRONICS 9 5 VO PORTS 9 6 Port 0 Interrup Enable Register POINT F1H Set 1 R W PO 6 INT4 PO 4 INT4 PO 2 INT2 PO O INTO PO 7 INT4 PO 5 INT4 PO 3 INT3 1 Port 0 Interrupt Enable Bits 0 Disable interrupt 1 Enable interrupt Figure 9 5 Port 0 External Interrupt Control Register POINT Port 0 Interrup Pending Register POPND F2H Set 1 R W PO 6 INT4 PO 4 INT4 PO 2 INT2 PO O INTO PO 7 INT4 PO 5 INTA PO 3 INT3 1 Port 0 Interrupt Pending Bits Interrupt not pending Clear PO n pending condition when write PO n interrupt is pending No effect when write Figure 9 6 Port 0 External Interrupt Pending Register POPND S3P80C5 C80C5 C80C8 ELECTRONICS 3 80 5 80 5 80 8 PORTS 1 Port 1 is a bit programmable 8 bit I O port Port 1 pins are accessed directly by read write operations to the port 1 data register P1 set 1 E1H To configure port 1 the initialization routine writes the appropriate values to the two port 1 control registers P1CONH set 1 EAH for the upper nibble pins 1 7 1 4 P1CONL set 1 EBH for the lower nibble pins 1 3 1 0 Each 8 bit control register contains four bit pairs and each 2 bit value configures one port pin see Figures 9 6 and 9 7 Following a hardware reset the port 1 cont
176. s of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 1 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3P80C5 C80C5 C80C8 RET Return RET Operation Flags Format Example 6 70 lt SP SP lt SP 2 RET instruction is normally used to return to the previously executing procedure the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 lt dst 7 dst 1 lt dst n 0 6 The contents of the destination operand are rotated left one bit positi
177. s the contents of the source word 02H into the destination word 01H This leaves the value 03H in general register OOH and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET MULT multiply Unsigned MULT dst src Operation dst lt dst x src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Flags Set if result is gt 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst sic opc SIC dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H register 02H 09H register 06H MULT 00H 02H gt Register OOH 01H register 01H 20H register 02 09H MULT 00H Q01H Register OOH OOH register 01H OCOH MULT OOH 30H gt Register OOH 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 b
178. sable the watchdog function you must write the signature code 1010B to the basic timer register control bits 7 4 For more reliability we recommend to use the Watch dog timer function in remote controller and hand held product application ELECTRONICS 10 1 BASIC TIMER and TIMER 0 S3P80C5 C80C5 C80C8 Basic Timer Control Register BTCON D3H Set 1 R W Watchdog function enable bits Divider clear bit for basic 1010B Disable watchdog timer timer and timer 0 Other value Enable watchdog timer 0 No effect 1 Clear both dividers Basic timer input clock selection bits 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fosc 4096 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS 3 80 5 80 5 80 8 BASIC TIMER AND TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by enabling the watchdog function A reset clears BTCON to 00 automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current register setting divided by 4096 as the BT clock A reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to B
179. ser stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 E3 Given R6 10H R7 33H R8 12H program memory locations 1033H 1034H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and is incremented by one RR6 lt RR6 1 R8 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3P80C5 C80C5 C80C8 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples 6 56 dst src m m 41 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working regist
180. ssing 2 12 ELECTRONICS 3 80 5 80 5 80 8 ADDRESS SPACES COMMON WORKING REGISTER AREA After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Register a hardware reset register pointers RPO and RP1 point to the commom working register area locations COH CfH RP02 1100 0000 1 1100 1000 Figure 2 10 Common Working Register Area ELECTRONICS 2 13 ADDRESS SPACES S3P80C5 C80C5 C80C8 PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations using working register addressing mode only Example 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H lt the value in location 40H Example 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 C3H lt R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register
181. st interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal Opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast OpC 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS S3P80C5 C80C5 C80C8 INSTRUCTION SET JP Jump JP JP Operation Flags Format 1
182. ster R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET DA Decimal Adjust DA Operation Instruction ADD ADC SUB SBC Flags Format dst dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 06 0 0 0 9 1 0 3 06 0 0 A F 0 0 9 60 1 0 9 0 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 0 0 8 1 6 06 0 1 7 F 0 0 9 AO 60 1 1 6 1 6 9A 66 1 C Set if there was a carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3P80C5 C80C5 C80C8 DA Decimal Adjust DA Example
183. t on rising and falling edges Push pull output mode Input mode interrupt on rising edges Figure 9 3 Port 0 High Byte Control Register POCONH 9 4 ELECTRONICS S3P80C5 C80C5 C80C8 PORTS Port 0 Control Register Low Byte POCONL Set 1 R W e mi O INTO 1 INT1 PO 2 INT2 PO 3 INT3 POCONL Pin Configureation Settings Input mode interrupt on falling edges Input mode interrupt on rising and falling edges Push pull output mode Input mode interrupt on rising edges Figure 9 4 Port 0 Low Byte Control Register POCONL PORT 0 INTERRUPT ENABLE REGISTER POINT The port 0 interrupt control register POINT is used to enable and disable external interrupt input at individual PO pins see Figure 10 5 To enable a specific external interrupt you set its POINT n bit to 1 You must also be sure to make the correct settings in the corresponding port 0 control register POCONH POCONL PORT 0 INTERRUPT PENDING REGISTER POPND The port 0 interrupt pending register POPND contains pending bits flags for each port 0 interrupt see Figure 10 6 When a PO external interrupt is acknowledged by the CPU the service routine must clear the pending condition by writing a to the appropriate pending flag in the POPND register Writing 1 to the pending bit has no effect NOTE A hardware reset INTR POR clears the POINT and POPND registers to For this reason the application program
184. ted The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc sbio sc 3 6 47 0 Rb opc dst 3 6 47 Rb T NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register OOH 05H LDB R0 00H2 gt RO 07H register OOH 05H LDB 00H 0 RO gt RO 06H register OOH 04H In the first example destination working register RO contains the value 06H and the source general register 00H the value 05H The statement LD R0 00H 2 loads the bit two value of the 00H register into bit zero of the RO register leaving the value 07H in register RO In the second example OOH is the destination register The statement LD 00H 0 RO0 loads bit zero of register RO to the specified bit bit zero of the destination register leaving O4H in general register OOH ELECTRONICS 6 51 INSTRUCTION SET S3P80C5 C80C5 C80C8 LDC LDE Load Memory LDC LDE Operation Flags Format 6 52 dst src dst src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or rr values an even number for program memory and odd an odd number for data memory No flags are affected Byt
185. ter P2CON FOH R W Alternative Function Enable Normal I O Function REM TOCK Alternative Function Enable Normal I O Function TOPWM Figure 9 9 Port 2 Control Register P2CON ELECTRONICS 9 9 VO PORTS S3P80C5 C80C5 C80C8 Port 2 Data Register P2 E2H R W Not used for S3C80C5 P2 0 TO PWM P2 1 REM TOCK Carrier on off for Remote Controller P2 2 Not used for S3C80C5 Figure 9 10 Port 2 Data Register P2 9 10 ELECTRONICS S3P80C5 C80C5 C80C8 BASIC TIMER AND TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3P80C5 C80C5 C80C8 has two default timers an 8 bit basic timer and one 8 bit general purpose timer counter The 8 bit timer counter is called timer 0 Basic Timer BT You can use the basic timer BT in two different ways Asawatchdog timer to provide an automatic reset mechanism in the event of a system malfunction or To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode system reset clears BTCON This enables the watchdog function and selects a basic timer clock frequency of 4096 To di
186. ter an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the 8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3P80C5 C80C5 C80C8 ADC with carry ADC Operation Flags Format Examples dst src dst lt dst src The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithm
187. terrupt can occur 1 Overflow mode OVF interrupt can occur 1 PWM mode OVF interrupt can occur 3 Timer 0 Counter Clear Bit No effect when write Clear counter TOCNT when write 2 Timer 0 Overflow Interrupt Enable Bit note Disable TO overflow interrupt Enable TO overflow interrupt Timer 0 Match Interrupt Enable Bit EN Disable TO match interrupt Enable TO match interrupt 0 Timer 0 Match Interrupt Pending Flag No TO match interrupt pending when read Clear TO match interrupt pending condition when write TO match interrupt is pending when read No effect when write NOTE timer 0 overflow interrupt pending condition is automatically cleared by hardware However the timer 0 match capture interrupt IRQO vector FCH must be cleared by the interrupt service routine ELECTRONICS 4 27 CONTROL REGISTERS S3P80C5 C80C5 C80C8 T1CON Timer 1 Control Register FAH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer 1 Input Clock Selection Bits Internal clock counter a flip flop T FF 5 4 Timer 1 Operating Mode Selection Bits Interval timer mode counter cleared by match signal Lo 4 Overflow mode OVF interrupt can occur 1 Overflow mode OVF interrupt can occur 1 Overflow mode OVF interrupt can occur i Timer 1 Counter C
188. the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags and sets SYM 0 to 1 allowing the CPU to process the next interrupt request ELECTRONICS 3 80 5 80 5 80 8 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM OOH FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location o gi m gt Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher pri
189. the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register O3H by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3P80C5 C80C5 C80C8 DECW Decrement Word DECW Operation Flags Format Examples NOTE 6 36 dst dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 81 IR Given RO 12H R1 34H R2 register and register 31H 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 20H In the first example destination register RO contains the value 12H and register R1 the value The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To
190. the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 200H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3P80C5 C80C5 C80C8 PUSHUI Push user stack Incrementing PUSHUI Operation Flags Format Example 6 68 dst src IR IR 1 dst src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst SIC 3 8 83 IR R Given Register 00H register 01H 05H and register 04H 2AH PUSHUI 00 01 Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example 0 The carry flag is cleared to logic zero regardles
191. then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH OOH and SPL OOH PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4 OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS 3 80 5 80 5 80 8 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst SIC 3 8 82 IR R Given Register OOH 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register OOH 02H register 01H 05H register 02 05H If
192. tion For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book NOTE Please one more check whether the selected device is S3P80A4 P80A8 P80A5 or S3P80B4 P80B8 P80B5 S3C8 SERIES OTP FACTORY WRITING ORDER FORM 1 2 Product Description Device Number S3P80C5 S3P8 write down the ROM code number note Product Order Form Package Pellet Wafer If the product order form is package Package Type Package Marking Check One Standard Custom A C Custom B Max 10 chars Max 10 chars each line SEC YWW YWW YWW Device Name Device Name p d Assembly site code Y Last number of assembly year WW Week of assembly Delivery Dates and Quantity ROM Code Release Date Required Delivery Date of Device Please answer the following questions 5 what is the purpose of this order New product development Upgrade of an existing product Replacement of an existing microcontroller Other If you are replacing an existing microcontroller please indicate the former microcontroller name 87 Whatare the main reasons you decided to use a Samsung microcontroller in your product Please check all that apply Price Product quality Features and functions Development system Technical support Delivery on tim
193. tion dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst sic 2 4 02 6 03 r Ir opc SIC dst 3 6 04 R R 05 R IR opc dst SIC 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH ADD R1 R2 gt R1 15H R2 08H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02 03H ADD 01H 02H gt Register 01H 2BH register 02H ADD 01H 25H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET S3P80C5 C80C5 C80C8 AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src The sou
194. tional priority relationship between for interrupt levels 2 3 and 4 IPR 3 defines the possible subgroup B relationships IPR 2 controls interrupt group B In the S3P80C5 C80C5 C80C8 implementation interrupt levels 2 and 3 are not used Therefore IPR 2 and IPR 3 settings are not evaluated as IRQ4 is the only remaining level in the group 0 controls the relative priority setting of IRQO and IRQM interrupts 5 12 ELECTRONICS S3P80C5 C80C5 C80C8 INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W Group priority D7 D4 D1 0 IRQO gt IRQ1 1 IRQ1 gt IRQO 0 Undefined Group 1 gt gt 0 IRQ4 0 gt gt 1 4 1 B gt A gt C Subgroup Bins 0 gt gt 0 IRQ4 1 C gt B gt A 1 IRQ4 0 gt gt Group Cine 1 Undefined 0 IRQ6 IRQ7 1 IRQ6 IRQ7 Subgroup 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 NOTE In this device interrupt structure only levels IRQO IRQ1 IRQ4 IRQ6 IRQ7 are used Settings for group subgroup B which control relative priorities for levels IRQ2 IRQ3 and IRQS are therefore not evaluated Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE S3P80C5 C80C5 C80C8 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Eac
195. to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to the either of the two 8 byte slices in the working register block you can define the working register area very flexibly to support program requirements 8 PROGRAMMING Setting the Register Pointers SRP 70H RPO 70H RP1 gt 78H SRP1 48H RPO nochange 48H SRPO 0A0H RPO nochange CLR RPO RPO nochange LD RP1 0F8H RPO nochange OF8H Register File Contains 32 8 Byte Slices 00001XXX 8 Byte Slice 16 Byte EE Contiguous Working 00000 XxX xX 8 Byte Slice Register block RPO Figure 2 6 Contiguous 16 Byte Working Register Block ELECTRONICS 2 9 ADDRESS SPACES S3P80C5 C80C5 C80C8 8 Byte Slice Register File 16 Byte Contains 32 Contiguous 11110 8 Byte Slices working Register block RPO 00000 8 Byte Slice RP1 Figure 2 7 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses 80H through 85H contains the values 10H 11H 12H 13H 14H and 15 respectively SRPO 80H RPO 80H ADD RO R1 RO gt RO ADC RO R2
196. total of 19 bit programmable pins e Eight input pins for external interrupts Carrier Frequency Generator 8 bit counter with auto reload function and one shot or repeat control Counter A Back up mode e When Vpp is lower than yp the chip enters Back up mode to block oscillation and reduce the current consumption 1 2 S3P80C5 C80C5 C80C8 Timers and Timer Counters One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function e 8 bit timer counter Timer 0 with two operating modes Interval mode and PWM mode 16 bit timer counter with one operating modes Interval mode Low Voltage Detect Circuit e Low voltage detect for reset or Back up mode Low level detect voltage S3C80C5 C80C8 1 90 V 200 mV Auto Reset Function e Reset occurs when stop mode is released by PO e When a falling edge is detected at Port 0 during Stop mode system reset occurs Operating Temperature Range 40 C to 85 C Operating Voltage Range Package Type e 24 pin SOP SDIP ELECTRONICS 3 80 5 80 5 80 8 BLOCK DIAGRAM 8 bit Timer Counter 16 bit Timer Counter ELECTRONICS 0 0 0 7 0 4 1 0 1 7 Port O INTR Internal Bus Port I O and Interrupt Control SAM87RI CPU 256 Byte 19 KOVE OM Register File Figure 1 1 Block Diagram PRODUCT OVERVIEW P2 0 TOPWM P2 1 REM P2 2 Carrier Gene
197. ull up Resistor Enable Register E7H Set 1 Bit Identifier 8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 7 Pull up Resistor Enable Bit Enable pull up resistor 1 Disable pull up resistor 6 0 6 Pull up Resistor Enable Bit Enable pull up resistor 1 Disable pull up resistor 5 0 5 Pull up Resistor Enable Bit Enable pull up resistor 1 Disable pull up resistor 4 0 4 Pull up Resistor Enable Bit Enable pull up resistor 1 Disable pull up resistor 3 0 3 Pull up Resistor Enable Bit Enable pull up resistor 1 Disable pull up resistor 2 P0 2 Pull up Resistor Enable Bit Enable pull up resistor 1 Disable pull up resistor PO Pull up Resistor Enable Bit Enable pull up resistor 1 Disable pull up resistor 0 0 0 Pull up Resistor Enable Enable pull up resistor 1 Disable pull up resistor 4 18 ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS P1CONH Port 1 Control Register High Byte EAH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 1 7 Mode Selection Bits 0 0 C Mosinputmode 0 1 Open drain output mode _1 0 Push pull output mode 5 4 P1 6 Mode Selection Bits Fo o i 71129 3 2 1
198. upt Enable interrupt 2 Counter A Start Bit Stop counter A 1 Start counter A Counter Mode Selection Bit One shot mode 1 Repeating mode 0 Counter A Output flip flop Control Bit Flip flop Low level T FF Low Flip flop High level T FF High 4 6 ELECTRONICS 3 80 5 80 5 80 8 CONTROL REGISTERS CLKCON System Clock Control Register D4H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Oscillator IRQ Wake up Function Enable Bit Not used for S3P80C5 C80C5 C80C8 6 5 Main Oscillator Stop Control Bits Not used for S3P80C5 C80C5 C80C8 4 3 CPU Clock System Clock Selection Bits 1 CICI EJES EC 2 0 Subsystem Clock Selection Bit 2 1 1 invalid setting for 53 80 5 80 5 80 8 Other value Select main system clock NOTES 1 After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 2 These selection bits are required only for systems that have a main clock and a subsystem clock The S3P80C5 C80C5 C80C8 uses only the main oscillator clock circuit For this reason the setting 101B is invalid ELECTRONICS 4 7 CONTROL REGISTERS S3P80C5 C80C5 C80C8 EMT external Memory Timing Register note FEH Set 1 RESET Value 0 1 1 1 1 1 0 Read Write R
199. you must write TOCON 1 to 1 To detect a match interrupt pending condition the application program polls 0 When a 1 is detected a timer 0 match interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a to the timer 0 interrupt pending bit TOCON O ELECTRONICS 10 3 BASIC TIMER and TIMER 0 10 4 S3P80C5 C80C5 C80C8 Timer 0 Control Register TOCON D2H Set 1 R W Timer 0 input clock selection bits Timer 0 match interrupt pending bit 00 fosc 4096 0 No interrupt pending 01 fosc 256 0 Clear pending bit write 10 fosc 8 1 Interrupt is pending 11 External clock P2 1 TOCK Timer 0 match interrupt enable bit 0 Disable interrupt Timer 0 operating mode selection bits 1 Enable interrupt 00 Interval mode 01 Overflow mode OVF interrupt can occur 10 Overflow mode OVF interrupt can occur Timer 0 overflow interrupt enable bit 11 2 PWM mode OVF interrupt can occur 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 0 counter clear bit 0 No effect 1 Clear the timer 0 counter when write Figure 10 2 Timer 0 Control Register TOCON ELECTRONICS 3 80 5 80 5 80 8 BASIC TIMER AND TIMER 0 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts IRQO Vectors and The timer 0 module can generate two interrupts the timer 0 overflow interrupt TOOVF and t

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