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A13 user manual v1.2 20130108

1. D p e 31 vo vo ur vi v2 va us vs viz viz vis vis ura via wis vis o 63 o a la es vn J a oe 15 16 UVI1 a a gt vo vo fun vi ve v vit une viz funa fvia una vis uns vis o 31 63 o lt gt pi ei an gt e gt UV00 UV02 UV03 lies 2 E Tile Based Planar Mode Y component The mapping of Y component is the same in YUV422 YUV420 and YUV411 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 291 Allwinner Technology CO Ltd A13 vo vi v2 vs va vs ve x7 ys yo vio vir via vis vis vis p ZZ E D 16 31 o 4 p je r EE gt ka La D ban je gt Dis ss a U or V component The mapping of V component is the same as U component YUV422 uo ul u2 U3 U4 us u6 u7 YUV420
2. A13 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POO POI P02 P03 P04 POS P06 PO7 P08 POO P10 Pll P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mono or Internal Frame Buffer 2 Bpp Or Palette 2 Bpp Mode FBF 0001 PS 00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14 P13 P12 Pll P10 P09 P08 P07 P06 P05 P04 P03 P02 POI POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 PS 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P12 P13 P14 P15 P08 P09 P10 Pll P04 POS P06 P07 POO PO1 P02 P03 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 PS 10 Bit 31 30 29 28 27 26 25 24 23 2 21 20 19 18 17 16 P03 P02 POI POO P07 P06 P05 P04 P11 P10 P09 P08 P15 P14 P13 P12 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 11 Bit 31 30 29 28 27 26 25 24 23 022 21 20 19 18 17 16 POO PO1 P02 P03 P04 P05 P06 P07 P08 P09 P10 Pll P12 P13 P14 P15 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mono 4 bpp or palette 4 bpp mode FBF 0010 PS 00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P07 P06 POS P04 P03 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 Bit A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 330 Ou 7 Allw
3. 13 4 23 Interrupt Fast Forcing Register 0 Default 0x00000000 Offset 0x70 Register Name INTC FORCE REGO Read Wr Default 2 Bit Description ite Hex INT_FFO Enables the fast forcing feature on the corresponding interrupt source 31 0 0 No effect 31 0 W 0x0 f EA 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 13 4 24 Interrupt Fast Forcing Register 1 Default 0x00000000 Offset 0x74 Register Name INTC_FORCE_REG1 Read Wr Default Bit Description ite Hex INT FFI Enables the fast forcing feature on the corresponding interrupt source 63 32 0 No effect 31 0 W 0x0 D 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 13 4 25 Interrupt Fast Forcing Register 2 Default 0x00000000 Offset 0x78 Register Name INTC_FORCE_REG2 Read Wr Default a Bit Description ite Hex INT_FF2 Enables the fast forcing feature on the corresponding interrupt source 95 64 0 No effect 31 0 W 0x0 L 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 13 4 26 Interrupt Source Priority 0 Register Default 0x00000000 Offset 0x80 Register Name INTC_SRC_PRIO_REGO Read Wr Default SR Bit i Description ite Hex IRQ
4. Interrupt Source SRC Vector FIQ Description 58 0x00E8 59 Ox00EC 60 0x00FO 61 Ox00F4 62 0x00F8 63 Ox00FC 64 0x100 65 0x104 PLE on non secure transfers interrupt PLE PERFMU 66 0x108 PLE on FA transfer interrupt PLE error interrupt Performance monitor interrupt Timer 4 67 0x010C Timer 4 interrupt Timer 5 68 0x0110 Timer 5 interrupt GPU GP 69 0x0114 GPU GPMMU 70 0x0118 GPU PPO 71 Ox011C GPU PPMMUO 72 0x0120 GPU PMU 73 0x0124 GPU RSVO 74 0x0128 GPU RSV1 75 0x012C GPU RSV2 76 0x0130 GPU RSV3 77 0x0134 GPU RSV4 78 0x0138 GPU RSV5 79 0x013C GPU RSV6 80 0x0140 81 0x0144 Sync timer 0 82 0x0148 Sync timer 1 83 Ox014C 13 3 Interrupt Register List Module Name Base Address INTC 0x01C20400 Register Name Offset Description INTC VECTOR REG 0x0000 Interrupt Vector INTC BASE ADDR REG 0x0004 Interrupt Base Address INC PROTEC REG 0x0008 Interrupt Protection A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 112 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 INTC NMI CTRL REG 0x000C Interrupt Control INTC IRQ PEND REGO 0x0010 Interrupt IRQ Pending 0 Status INTC IRQ PEND REGI 0x0014 Interrupt IRQ Pending 1 Statu
5. 28 25 R W Ox8 24 20 R W 0x10 19 R W 0x0 18 R W 0x1 PLL5 OUT EXT DIV P 17 16 R W 0x0 PLLS Output External Divider P The range is 1 2 4 8 15 13 R W 0x4 PLL5_FACTOR_N PLL5 Factor N Factor 0 N 0 12 8 R W 0x12 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 R W 0x1 aah LDO Enable 6 PLL5 FACTOR K 5 4 R W 0x0 PLLS Factor K K Factor 1 The range is from 1 to 4 3 2 R W 0x0 PLL5_FACTOR_M1 PLLS Factor M1 PLL5 FACTOR M 1 0 R W 0x0 PLL5 Factor M M Factor 1 The range is from 1 to 4 6 4 8 PLL5 Tuning Default 0x14880000 Offset 0x24 Register Name PLL5_TUN_REG Read Wr Default D Bit Description ite Hex 31 0 6 4 9 PLL6 Default 0x21009931 Offset 0x28 Register Name PLL6_CFG_REG Read Wr Default o Bit Description ite Hex PLL6_Enable 0 Disable 1 Enable 31 R W 0x0 Output 24MHz N K M 2 Note the output 24MHz N K clock must be in the range of 240MHz 3GHz if the bypass is disabled A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 60 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Its default is 1200MHz PLL6 BYPASS EN PLL6 Output Bypass Enable 0 Disable 1 Enable If the bypass is enabled the PLL6 output is 24MHz 30 R W 0x0 29 13 PLL6_FACTOR_N PLL6 Factor N Factor 0 N 0 12 8 R W 0x19 Factor 1 N 1 Factor 2 N 2 Fac
6. Offset 0x118 Register Name DEFE CHO VERTPHASE1 REG Read Wr Default SC Bit i Description ite Hex 31 20 PHASE 19 0 R W 0x0 Y G component initial phase in vertical for bottom field complement This value equals to initial phase a 27 5 43 DEFE CH1 INSIZE REG Offset 0x200 Register Name DEFE CH1 INSIZE REG Bit po SEH Description ite Hex 31 29 IN_HEIGHT 28 16 R W 0x0 Input image U R component height Input image height The value of these bits add 1 15 13 IN_WIDTH 12 0 R W 0x0 Input image U R component width The image width The value of these bits add 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 310 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 When line buffer result selection is original data the maximum width is 2048 27 5 44 DEFE CHL OUTSIZE REG Offset 0x204 Register Name DEFE CH1 OUTSIZE REG Bit ES ER Description ite Hex 31 29 OUT_HEIGHT 28 16 R W 0x0 Output layer U R component height The output layer height The value of these bits add 1 15 13 OUT_WIDTH Output layer U R component width 12 0 R W 0x0 The output layer width The value of these bits add 1 When line buffer result selection is horizontal filtered result the maximum width is 2048 27 5 45 DEFE_CH1_HORZFACT_REG Offse
7. A13 0x01C2 3C00 0x01C2 3FFF 1K 0x01C2 4000 0x01C2 43FF 1K 0x01C2 4400 0x01C2 47FF IK 0x01C2 4800 0x01C2 4BFF IK 0x01C2 4C00 0x01C2 4FFF IK TP 0x01C2 5000 0x01C2 53FF IK PMU 0x01C2 5400 0x01C2 57FF IK 0x01C2 5800 0x01C2 5BFF IK 0x01C2 5C00 0x01C2 SFFF 1K 0x01C2 6000 0x01C2 63FF 1K 0x01C2 6400 0x01C2 67FF IK 0x01C2 6800 0x01C2 6BFF 1K 0x01C2 6C00 0x01C2 6FFF 1K 0x01C2 7000 0x01C2 73FF IK 0x01C2 7400 0x01C2 77FF IK 0x01C2 7800 0x01C2 7BFF IK 0x01C2 7C00 0x01C2 7FFF IK 0x01C2 8000 0x01C2 83FF IK UART I 0x01C2 8400 0x01C2 87FF IK 0x01C2 8800 0x01C2 8BFF 1K UART 3 0x01C2 8C00 0x01C2 8FFF IK 0x01C2 9000 0x01C2 93FF IK 0x01C2 9400 0x01C2 97FF IK 0x01C2 9800 0x01C2 9BFF IK 0x01C2 9C00 0x01C2 9FFF 1K 0x01C2 A000 0x01C2 A3FF IK 0x01C2 A300 0x01C2 A7FF IK 0x01C2 A800 0x01C2 ABFF IK TWIO 0x01C2 AC00 0x01C2 AFFF IK TWI I 0x01C2 B000 0x01C2 B3FF IK 0x01C2 B400 0x01C2 B7FF IK 0x01C2 B800 0x01C2 BBFF IK 0x01C2 BC00 0x01C2 BFFF IK 0x01C2 C000 0x01C2 C3FF IK 0x01C2 C400 0x01C2 C7FF IK 0x01C2 C800 0x01C2 CBFF IK 0x01C2 CCO00 0x01C2 CFFF 1K 0x01C3 0000 0x01C3 FFFF 64K Mali 400 0x01C4 0000 0x01C4 FFFF 64K Sync Timer 0x01C6 0000 0x01C6 OFFF 4K SRAM C 0x01D0 0000 0x01 DF FFFF Module SRAM A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013
8. Indication NO and master has tried to register write to the Line Control Register while the UART is busy USR 0 is set to one 19 4 7 UART FIFO Control Register Register Name UART FCR Offset 0x08 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 RT RCVR Trigger This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated In auto flow control mode it is used to determine when the rts_n signal is de asserted It also determines when the dma_rx_req_n signal is asserted in certain modes of operation 00 1 character in the FIFO 01 FIFO full 10 FIFO full 7 6 W 0 11 FIFO 2 less than full TFT TX Empty Trigger Writes have no effect when THRE MODE USER Disabled This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active It also determines when the dma tx req n signal is asserted when in certain modes of operation 00 FIFO empty 01 2 characters in the FIFO 10 FIFO 144 full 5 4 W 0 11 FIFO full DMAM DMA Mode 0 Mode 0 3 W 0 1 Mode 1 XFIFOR XMIT FIFO Reset This resets the control portion of the transmit FIFO and treats the FIFO as empty This also de asserts the DMA TX request 2 W 0 It is self clearing It is not necessary to clear this bit RFIFOR 1 W 0 RCVR FIFO Reset A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 190 Ja
9. Offset 0x098 Register Name TCONI basic timing register 1 Read Wr Default Bit Description ite Hex 31 27 LS_XO 27 16 R W 0 saan width is LS XO 1 15 12 LS YO 11 0 R W 0 width is LS_YO 1 Note this version LS_YO TCONI YI 29 3 23 TCONI1 BASIC2 REG Offset 0x09C Register Name TCONI basic timing register2 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 359 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Read Wr Default i Bit i Description ite Hex 31 27 TCONI1 XO 27 16 R W 0 AE width is TCON1_XO 1 15 12 TCONI YO 11 0 R W 0 ER height is TCON1_YO 1 29 3 24 TCON1 BASIC3 REG Offset OxOAO Register Name TCONI basic timing register3 Bit EE Ser Description ite Hex 31 28 HT 28 16 R W 0 horizontal total time Thcycle HT 1 Thdclk 15 12 HBP 11 0 R W 0 horizontal back porch Thbp HBP 1 Thdclk 29 3 25 TCONI BASIC4 REG Offset Ox0A4 Register Name TCONI basic timing register4 Bit EG D Description ite Hex 31 28 VT 28 16 R W 0 horizontal total time in HD line Tvt VT 2 Th 15 12 VBP 11 0 R W 0 horizontal back porch in HD line Tvbp VBP 1 Th 29 3 26 TCON1 BASIC5 REG Offset Ox0A8 Register Name TCON1 basic timing register5 Read Wr Defa
10. X Figure 25 1 TP Typical Application Circuit A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 260 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 25 3 Clock Tree and ADC Time 25 3 1 Clock Tree PRESCALER 00 2 HOSC24M 01 3 10 6 11 1 CLK IN AUDIO PLL Figure 25 2 TP Clock Tree 25 3 2 A D Convertion Time When the clock source is 24MHz and the prescaler value is 6 total 12 bit conversion time is CLK_IN 24MHz 6 4MHz Conversion Time 1 4MH7 13Cycles 3 25us Touch acquire time divider is 16 TACQ 16 16 1 4us 64us FS_TIME Based on TACQ and Touch Mode When touch is in dual and pressure measurement mode TACQ is the FS_TIME must be no less than 6 TACQ Conversion Time FS_TIME gt M TACQ Conversion Time Conyersion Time L PATA DATA Gg X2 DATA Lg Y2 DATA Lg Z1 DATAL Z2 DAT a FS TIME p gt Figure 25 3 Dual Touch And Pressure Measurement a DATE YI DATA pg X2 DAT Ar 2 DATA lt _ gt FS_TIME r gt A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 261 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Figure25 4 Dual Touch No Pressure Measurement Co
11. A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 45 Ou 7 Allwinner Technology CO Ltd A13 1 Enable 30 R W 0x0 SPD_DET_MODE Speed Detect Mode 0 single mode 1 continuous mode 29 28 R W 0x0 SPD_DET_SPDUP_FACTOR Speed Detect Speed Up Factor Set these bits to non zero value can speed up the scan operation 00 lowest 11 fastest 27 17 16 0x0 SPD_DET_SCN_FIN Speed Detect Scan Finished 0 no effect 1 scan finished 15 8 0x0 SPD_DET_FACTORI Speed Detect Factor 1 This number indicates the delay length equivalent to input clock period x2 7 0 0x0 SPD DET FACTORO Speed Detect Factor 0 This number indicates the delay length equivalent to input clock period x1 5 3 39 PMU Speed Factor Register 1 Offset OxE4 Register Name PMU_SPEED_FACTOR_REG1 Bit Read Wr ite Default Hex Description 31 R W 0x0 SPD_DET_EN Speed Detect Enable 0 Disable 1 Enable 30 R W 0x0 SPD_DET_MODE Speed Detect Mode 0 single mode 1 continuous mode 29 28 R W 0x0 SPD_DET_SPDUP_FACTOR Speed Detect Speed Up Factor Set these bits to non zero value can speed up the scan operation 00 lowest 11 fastest 27 17 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Ri
12. 12 R W 0x0 Gating AHB Clock for DE BE 0 mask 1 pass 11 R W 0x0 10 9 CSI_AHB_GATING 8 R W 0x0 Gating AHB Clock for CSI 0 mask 1 pass 7 5 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 66 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 LCD AHB GATING 4 R W 0x0 Gating AHB Clock for LCD 0 mask 1 pass 3 2 R W 0x0 VE_AHB_GATING 0 R W 0x0 Gating AHB Clock for VE 0 mask 1 pass 6 4 19 APBO Module Clock Gating Default 0x00000000 Offset 0x68 Register Name APBO_GATING_REG Read W Default I Bit Description rite Hex 31 11 10 R W 0x0 9 7 IR_APB_GATING 6 R W 0x0 Gating APB Clock for IR 0 mask 1 pass PIO_APB_GATING 5 R W 0x0 Gating APB Clock for PIO 0 mask 1 pass 4 3 R W 0x0 2 1 R W 0x0 CODEC_APB_GATING Gating APB Clock for Audio CODEC 0 mask 1 pass 0 R W 0x0 6 4 20 APB1 Module Clock Gating Default 0x00000000 Offset Ox6C Register Name APB1_GATING_REG Bit gene Pl Description rite Hex 31 24 23 22 21 20 UART3 APB GATING Gating APB Clock for UART3 0 mask 1 pass 19 R W 0x0 18 R W 0x0 UART1_APB_GATING Gating APB Clock for UART1 0 mask 1 pass 17 R W
13. W LESSER NFC_ALE A le 18 gt a t9 gt NFC 10 D Data 0 f Data n 1 te Figure 15 7 Write Data to Flash Cycle NFC_CLE NFC_CE INFC_WE A i t14 NFC_RE A NFC_ALE A o D r NFC_RB NFC_IOx _ cmd d 0 X d 1 d n 1 Figure15 8 Waiting R B Ready Diagram A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 155 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 NFC CLE NFC CEH NFC WE L t17 gt NFC_RE NFC_ALE en On Wee er on Beer er We Weer Wer We NFC_RB NFC 10x cmd d 0 d 1 EA d n 1 Figure15 9 WE High to RE Low Timing Diagram NFC CLE NFC CES NFC WE a t18 NFC DES NFC ALE NFC_RB NFC_IOx d 0 d0 Xa n 1 05h coli col2 EOh Figure15 10 RE High to WE Low Timing Diagram NFC_CLE NFC_CE T19 gt NFC_WE NFC_RE NFC_ALE NFC_RB NFC_IOx addr2 X addr3 d 0 di d 2 X d n 1 Figure15 11 Address to Data Loading Timing Diagram Timing Cycle List ID Parameter Timing Notes A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 156 Jau 8 2013 Ou Allwinner Techno
14. 13 4 12 Interrupt Select Register 1 Default 0x00000000 Offset 0x34 Register Name INTC_SEL_REG1 Read Wr Default SR Bit j Description ite Hex INT_SRC_TYPE1 Interrupt Source 63 32 irq type select 0 IRQ 1 FIQ 31 0 R W 0x0 13 4 13 Interrupt Select Register 2 Default 0x00000000 Offset 0x38 Register Name INTC_SEL_REG2 Read Wr Default _ Bit Description ite Hex INT_SRC_TYPE2 Interrupt Source 95 64 irq type select 0 IRQ 1 FIQ 31 0 R W 0x0 13 4 14 Interrupt Enable Register 0 Default 0x00000000 Offset 0x40 Register Name INTC_EN_REGO Bit Read Wr Default Description A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 116 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 ite Hex 0x0 INT_SRC_ENO Interrupt Source 31 0 Enable Bits 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 13 4 15 Interrupt Enable Register 1 Default 0x00000000 Offset 0x44 Register Name INTC_EN_REG1 Read Wr Default SC Bit Description ite Hex INT SRC ENI Interrupt Source 63 32 Enable Bits 31 0 R W 0x0 E Sonde 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 13 4 16 Interrupt Enable Register 2 Default 0x00000000 Offset 0x48 Regi
15. A13 Interrupt Source SRC Vector FIQ Description 19 0x004C 20 0x0050 21 0x0054 Timer 0 22 0x0058 Timer port 0 Timer 1 23 0x005C Timer port 1 Timer 2 Alarm WD 24 0x0060 Timer 2 Alarm Watchdog Timer 3 25 0x0064 Timer 3 interrupt 26 0x0068 DMA 27 0x006C DMA channel interrupt PIO 28 0x0070 PIO interrupt Touch Panel 29 0x0074 Touch Panel interrupt Audio Codec 30 0x0078 Analog Audio Codec interrupt LRADC 31 0x007C LRADC interrupt SD MMC 0 32 0x0080 SD MMC Host Controller 0 interrupt SD MMC 1 33 0x0084 SD MMC Host Controller 1 interrupt SD MMC 2 34 0x0088 SD MMC Host Controller 2 interrupt i 35 0x008C 36 0x0090 NAND 37 0x0094 NAND Flash Controller NFC interrupt USB OTG 38 0x0098 USB OTG wakeup connect disconnect interrupt USB EHCI 39 0x009C USB EHCI wakeup connect disconnect interrupt USB OHCI 40 0x00A0 USB OHCI wakeup connect disconnect interrupt 41 Ox00A4 CSI 42 0x00A8 CSI interrupt 43 Ox00AC LCD Controller 44 0x00BO LCD Controller interrupt 45 0x00B4 46 0x00B8 DE FE DE BE 47 0x00BC DE FE DE BE interrupt 48 0x00C0 PMU 49 Ox00C4 PMU interrupt 50 0x00C8 51 0x00CC 52 0x00D0 VE 53 0x00D4 VE interrupt SS 54 0x00D8 Security System interrupt 55 0x00DC 56 0x00E0 57 Ox00E4 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 111 Ou 7 Allwinner Technology CO Ltd A13
16. Ou 7 Allwinner Technology CO Ltd A13 15 10 9 0 R W 0 Kg Tvbp VBP 1 Thsync 29 3 12 TCONO BASIC3 REG Offset 0x054 Register Name TCONO basic timing register3 Read Wr Default aan Bit Description ite Hex 31 22 HSPW 25 16 R W 0 Thspw HSPW 1 Tdclk Note HT gt HSPW 1 15 10 VSPW 9 0 R W 0 Tvspw VSPW 1 Thsync Note VT 2 gt VSPW 1 29 3 13 TCONO HV IF REG Offset 0x058 Register Name TCONO hv panel interface register Bit REN Ge Description ite Hex HV_Mode 31 R W 0 0 24bit parallel mode 1 8bit serial mode Serial_Mode 30 R W 0 0 8bit 3cycle RGB serial mode RGB888 1 8bit 2cycle YUV serial mode CCIR656 29 28 RGB888 SMO Serial RGB888 mode Output sequence at odd lines of the panel line 1 3 5 Liss 27 26 R W 0 00 R G B 01 B R G 10 G B R 11 R G B RGB888_SM1 Serial RGB888 mode Output sequence at even lines of the panel line 2 4 6 8 25 24 R W 0 00 R G B 01 B R G 10 G B R A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 355 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 11 R G B 23 22 R W YUV SM serial YUV mode Output sequence 2 pixel pair of every scan line 00 YUYV 01 YVYU 10 UYVY 11 VYUY 21 20 R W YUV EAV SAV F line delay 0 F toggle right af
17. Offset 0x90 Register Name DEFE_CSC_COEF20_REG Read Wr Default or Bit Description ite Hex 31 13 COEF 12 0 R W 0x0 the V B coefficient the value equals to coefficient 2 27 5 31 DEFE_CSC_COEF21_REG Offset 0x94 Register Name DEFE_CSC_COEF21_REG Read Wr Default Bit Description ite Hex 31 13 COEF 12 0 R W 0x0 the V B coefficient the value equals to coefficient 2 27 5 32 DEFE CSC COEF22 REG Offset 0x98 Register Name DEFE_CSC_COEF22_REG Read Wr Default a Bit Description ite Hex 31 13 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 307 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 COEF 12 0 the V B coefficient the value equals to coefficient 2 27 5 33 DEFE CSC COEF23 REG Offset 0x9C Register Name DEPE CSC COEF23 REG Read Wr Default aan Bit Description ite Hex 31 14 CONT 13 00 R W 0x0 the V B constant the value equals to coefficient 2 27 5 34 DEFE WB LINESTRD EN REG Offset OxDO Register Name DEFE_WB_LINESTRD_EN_REG Read Wr Default S Bit i Description ite Hex 31 1 EN Write back line stride enable 0 R W 0x0 0 disable 1 enable 27 5 35 DEFE WB LINESTRDO REG Offset 0xD4 Register Name DEFE WB LINESTRDO RE
18. 150 14 4 10 Dedicated DMA Byte Counter Register N 0 7 sessessesseeeesreeseerrerrerresrrsrrerrerrnere 150 14 4 11 Dedicated DMA Parameter Register 150 15 NAND Flash Controller NFC cccsssscssssssscssssscsesssscccessnsccsssssscssssssccsssssscssssssscssssssccsesesscssessnscssesess 151 15 1 a 151 15 2 NFC Block Diagram eege 152 15 3 NEC Timing Di gramynasnasennsspasvnmevemsdseinninsdrinnsnsiineseksdinivvuievvrr 152 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 9 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 154 NFC Operation Guide ee EEGENEN EES AE E 157 16 SD3 0 Controller scsccscsscsscsssssscssccscsssssssscsssssssssssscosssssssssssesssssscsssscossssssssessosssssscssessosssessessossonsoes 160 16 1 a EEN 160 16 2 SD3 0 Timing Diagram as ee a cs 160 17 Two Wire Interface secssesscncssesssesscosscoscoesscessvesecesedesecosssebecesedessdesedesesesevesedesevasesesedesedesedesedesevesedesevesavesevesss 162 17 1 O EE 162 12 FVII Time AT EE 162 17 3 TWI Controller Register List 022 163 17 4 TWI Controller Register Description iii 163 17 4 1 TWI Slave Address Register E 163 17 4 2 TWI Extend Address Register 164 17 4 3 TWI Data e ET 164 17 4 4 FE es EEE cece 164 17 4 5 TWI EE 166 17 4 6 TY ole Mats E 167 17 4 7 TWI Soft Reset E 168 17 4 8 TWI Enhance Feature Register A 168 17 4 9 TWI Line Control Register a eataiactsnconcccnsc
19. 7 0 R RBR Receiver Buffer Register Data byte received on the serial input port sin in UART mode or the serial infrared input sir_in in infrared mode The data in this register is valid only if the Data Ready DR bit in the Line Status Register LCR is set If in FIFO mode and FIFOs are enabled FCR 0 set to one this register accesses the head of the receive FIFO If the receive FIFO is full and this register is not read before the next data character arrives the data already in the FIFO is preserved but all incoming data are lost and an overrun error occurs 19 4 2 UART Transmit Holding Register Register Name UART THR Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 THR Transmit Holding Register Data to be transmitted on the serial output port sout in UART mode or the serial infrared output sir_out_n in infrared mode Data should only be written to the THR when the THR Empty THRE bit LSR 5 is set If in FIFO mode and FIFOs are enabled FCR 0 1 and THRE is set 16 number of characters of data may be written to the THR before the FIFO is full Any attempt to write data when the FIFO is full results the 7 0 W 0 write data lost 19 4 3 UART Divisor Latch Low Register Register Name UART DLL Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 A13 Use
20. 31 4 6 Security System Interrupt Control Status Register Register Name SS_ICSR Offset 0x48 Default Value 0x0000 0000 Bit Read Write Default Description 31 11 RX FIFO Empty Pending bit 0 No pending 1 RX FIFO Empty pending 10 R W 0 Notes Write 1 to clear or automatically clear if interrupt condition fails 9 TX FIFO Data Available Pending bit 0 No TX FIFO pending 1 TX FIFO pending R W 0 Notes Write 1 to clear or automatically clear if interrupt condition fails 7 5 DRQ Enable 0 Disable DRQ CPU polling mode 4 R W 0 1 Enable DRQ DMA mode RX FIFO Empty Interrupt Enable 0 Disable 1 Enable Notes If it is set to 1 when the number of empty room is no smaller than gt the preset threshold the interrupt is triggered and the 2 R W 0 correspond flag is set TX FIFO Data Available Interrupt Enable 0 Disable 1 Enable Notes If it is set to 1 when available data number is no smaller than gt the preset threshold the interrupt is triggered and the correspond 0 R W 0 flag is set 31 4 7 Security System Message Digest n Register Register Name SS_MD n Offset Ox4C 4 n Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 377 Jau 8 2013 Ou 7 Al
21. PB2 Select 000 Input 001 Output 010 PWM 011 100 101 10 8 R W 0 110 EINT16 111 7 PB1 Select 000 Input 001 Output 010 TWIO SDA Ol 1 6 4 R W 0 100 101 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 384 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 110 11 3 PBO Select 000 Input 001 Output 010 TWIO SCK Ol 1 100 101 2 0 R W 0 110 111 33 4 2 PB Configure Register 1 Register Name PB CFG1 Offset 0x28 Default Value 0x0000 0000 Bit Read Write Default Description 31 PB 15 Select 000 Input 001 Output 010 TWIL SCK O1 1 100 101 30 28 R W 0 110 11 27 26 24 R W 0 23 22 20 R W 0 19 18 16 R W 0 15 14 12 R W 0 11 PB 10 Select 000 Input 001 Output 010 SPI2_CSI 011 100 101 10 8 R W 0 110 EINT24 111 7 6 4 R W 0 3 2 0 R W 0 33 4 3 PB Configure Register 2 Offset 0x2C Register Name PB_CFG2 Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 385 Ou 7 Allwinner Technology CO Ltd A13 31 20 19 18 16 R
22. X OFFSETO 4 0 R W 0x0 beg RE The x offset of the top left point in the first tile 27 5 13 DEFE LINESTRDO REG Offset 0x40 Register Name DEFE_LINESTRDO_REG Read Wr Default E Bit Description ite Hex LINE_STRIDE In tile based type The stride length is the distance from the start of the end line in one tile to the 31 0 R W 0x0 ree ue ee start of the first line in next tile here next tile is in vertical direction In non tile based type The stride length is the distance from the start of one line to the start of the A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 299 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 next line 27 5 14 DEFE LINESTRD1 REG Offset 0x44 Register Name DEFE_LINESTRD1_REG Bit KE De Description ite Hex LINE STRIDE In tile based type The stride length is the distance from the start of the end line in one tile to the 31 0 R W 0x0 start of the first line in next tile here next tile is in vertical direction In non tile based type The stride length is the distance from the start of one line to the start of the next line 27 5 15 DEFE_LINESTRD2_REG Offset 0x48 Register Name DEFE_LINESTRD2_REG Bit AN ue Description ite Hex LINE_STRIDE In tile based type The stride length is the distance from the start of the end line in one tile to the
23. 0x0 IRQ45_PRIO IRQ 45 Priority Set priority level for IRQ bit 45 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority Copyright 2013 Allwinner Technology All Rights Reserved 125 Jau 8 2013 7 Allwinner Technology CO Ltd Offset 0x88 Register Name INTC SRC PRIO REG A13 25 24 R W 0x0 IRQ44_PRIO IRQ 44 Priority Set priority level for IRQ bit 44 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 23 22 R W 0x0 IRQ43_PRIO IRQ 43 Priority Set priority level for IRQ bit 43 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 21 20 R W 0x0 IRQ42_PRIO IRQ 42 Priority Set priority level for IRQ bit 42 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 19 18 R W 0x0 IRQ41_PRIO IRQ 41 Priority Set priority level for IRQ bit 41 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 17 16 R W 0x0 IRQ40_PRIO IRQ 40 Priority Set priority level for IRQ bit 40 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 1
24. 11 0 R W 0x5DB AVS_CNT0_D A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 100 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Divisor N for AVS Counter0 The number N is from 1 to 0x7ff The zero value is reserved The internal 33 bits counter engine will maintain another 12 bits counter The 12 bits counter is used for counting the cycle number of one 24Mhz clock When the 12 bits counter reaches gt N the divisor value the internal 33 bits counter register will increase 1 and the 12 bits counter will reset to zero and restart again Notes It can be configured by software at any time 11 3 24 Watchdog Control Register Offset 0x90 Register Name WDOG CTRL REG Read Wr Default L Bit Description ite Hex 31 13 KEY_FIELD 12 1 R W 0x333 I WDOG_RESTART 0 R W D Watchdog Restart 0 No effect 1 Restart the Watchdog 11 3 25 Watchdog Mode Register Default 0x00000000 Offset 0x94 Register Name WDOG MODE REG Bit Read Wr ite Default Hex Description 31 R W 0 WDOG TEST MODE 0 normal mode 1 test mode 30 7 6 3 R W 0x0 WDOG_INTV_VALUE Watchdog Interval Value Watchdog clock source is OSC24M If the OSC24M is turned off the watchdog will not work 0000 0 5sec 0001 1sec 0010 2sec 0011 3sec 0100 4sec 0101 Ssec
25. Full duplex synchronous serial interface Configurable Master Slave 8x64 FIFO for data transmit and receive Configurable Polarity and phase of the Chip Select SPI SS and SPI Clock SPI SCLK Support Dedicated DMA 18 2 SPI Timing Diagram The SPI master uses the SPI SCLK signal to transfer data in and out of the shift register Data is clocked using any one of four programmable clock phase and polarity combinations During Phase 0 Polarity 0 and Phase 1 Polarity 1 operations output data changes on the falling clock edge and input data is shifted in on the rising edge During Phase 1 Polarity 0 and Phase 0 Polarity 1 operations output data changes on the rising edges of the clock and is shifted in on falling edges The POL defines the signal polarity when SPI_SCLK is in idle state The SPI_SCLK is high level when POL is 1 and it is low level when POL is 0 The PHA decides whether the leading edge of SPI_SCLK is used to setup or sample data The leading edge is used to setup data when PHA is 1 and to sample data when PHA is 0 The four modes are listed below SPI Mode POL PHA Leading Edge Trailing Edge 0 0 0 Rising Sample Falling Setup 1 0 1 Rising Setup Falling Sample 2 1 0 Falling Sample Rising Setup 3 1 1 Failing Setup Rising Sample A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 171 Jau 8 2013 Ou 7 Allw
26. GW 7 Allwinner Technology CO Ltd A13 14 DMA Controller 14 1 Overview There are two kinds of DMA in the chip One is Normal DMA NDMA with 8 channels and the other is Dedicated DMA DDMA with 8 channels For NDMA only one channel can be active and the sequence is in accordance with the priority level For DDMA at most 8 channels can be active at the same time if their source or destination does not conflict 14 2 DMA Description DMA can support 8 bit 16 bit 32 bit data width The data width of Source and Destination can be different but the address should be aligned 14 3 DMA Register List Module Name Base Address DMA 0x01C02000 Register Name Offset Description DMA IRQ EN REG 0x0000 DMA IRQ Enable DMA IRQ PEND STAS REG 0x0004 DMA IRQ Pending Status Normal DMA Configuration NDMA CTRL REG 0x 100 N 0x20 N 0 1 2 3 4 5 6 7 NDMA SRC ADDR REG Ox 100 N 0x20 4 Normal DMA Source Address NDMA DEST ADDR REG Ox100 N 0x20 8 Normal DMA Destination Address NDMA_BC_REG Ox 100 N 0x20 C Normal DMA Byte Counter Dedicated DMA Configuration DDMA_CFG_REG 0x300 N 0x20 N 0 1 253 4 5 6 7 Dedicated DMA Source DDMA_SRC_ADDR_REG 0x300 N 0x20 4 Start Address Dedicated DMA Destination DDMA_DEST_ADDR_REG 0x300 N 0x20 8 Start Address DDMA BC REG 0x300 N 0x20 C Dedicated DMA Byte Counter DDMA PARA REG 0x300 N 0x20 0x18 Dedicated DMA Parameter 14 4 DMA Register
27. Register Name PG_DRVO Offset OxEC Default Value 0x0555 5555 Bit Read Write Default Description 31 28 PG n Multi Driving Select n 0 13 2i 1 2i 00 Level 0 01 Level 1 1 0 13 R W Ox1 10 Level 2 11 Level 3 33 4 52 PG Multi Driving Register 1 Register Name PG_DRV1 Offset OxFO Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 53 PG Pull Register 0 Register Name PG_PULLO Offset OxF4 Default Value 0x0000 0000 Bit Read Write Default Description 31 28 PG n Pull up down Select n 0 13 21 1 2i 00 Pull up down disable O1 Pull up 1 0 13 R W 0x0 10 Pull down 11 Reserved 33 4 54 PG Pull Register 1 Register Name PG_PULL1 Offset OxF8 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 405 Ow Allwinner Technology CO Ltd A13 33 4 55 PIO Interrupt Configure Register 0 Register Name PIO INT CFGO Offset 0x200 Default Value 0x0000 0000 Bit Read Write Default Description External INTn Mode n 0 7 0x0 Positive Edge Ox1 Negative Edge 0x2 High Level 0x3 Low Level 41 3 41 0x4 Double Edge Positive Negative 1 0 7 R W 0 Others Reserved 33 4 56 PIO Interrupt Configure Re
28. 61 if the signal is less than lt sixty one sample duration it is taken as noise and discarded 1 0 R W SCS Sample Clock Select for CIR 0 CIR sample_clk is ir_clk 64 1 CIR sample_clk is ir_clk 128 2 CIR sample_clk is ir_clk 256 3 CIR sample_clk is ir_clk 512 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 205 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 21 USB OTG Controller 21 1 Overview The USB OTG is dual role controller supporting Host and device functions It can also be configured as a Host only or Device only controller full compliant with the USB 2 0 Specification The USB OTG can support high speed HS 480 Mbps full speed FS 12 Mbps and low speed LS 1 5 Mbps transfers in Host mode support high speed HS 480 Mbps and full speed FS 12 Mbps in Device mode The USB2 0 OTG controller SIE features 64 Byte Endpoint 0 for Control Transfer Support up to 5 User Configurable Endpoints for Bulk Isochronous Control and Interrupt bi directional transfers Support High Bandwidth Isochronous amp Interrupt transfers Support point to point and point to multipoint transfer in both Host and Peripheral mode 21 2 USB OTG Timing Diagram Please refer USB2 0 Specification A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 206 Jau 8 2013 Ou Allwinner Technology CO Ltd A
29. PC11 Select 000 Input 001 Output 010 NDQ3 011 SDC2_D3 100 101 14 12 R W 0 110 111 11 10 8 R W 0 PC10 Select A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 389 Ou 7 Allwinner Technology CO Ltd A13 000 Input 001 Output 010 NDQ2 011 SDC2 D2 100 101 110 111 7 PC9 Select 000 Input 001 Output 010 NDQI 011 SDC2_D1 100 101 6 4 R W 0 110 111 i PC8 Select 000 Input 001 Output 010 NDQO 011 SDC2 DO 100 101 2 0 R W 0 110 111 33 4 12 PC Configure Register 2 Register Name PC CFG2 Offset 0x50 Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 PC19 Select 000 Input 001 Output 010 NDQS 011 100 UART3_RTS 101 14 12 R W 0 110 111 11 10 8 R W 0 7 6 4 R W 0 3 2 0 R W 0 33 4 13 PC Configure Register 3 Register Name PC_CFG3 Offset 0x54 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 390 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 33 4 14 PC Data Register Register Name PC DAT Offset 0x58 Default Value 0x0000 0000 B
30. 33 4 29 PE Configure Register Register Name PE_CFG1 Offset 0x94 Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 PE11 Select 000 Input 001 Output 010 011 CSL D7 100 UART1 RX 101 14 12 R W 0 110 111 11 PE10 Select 000 Input 001 Output 010 011 CSI_D6 100 UART1_TX 101 10 8 R W 0 110 111 7 PE9 Select 000 Input 001 Output 010 011 CSI DS 6 4 R W 0 100 SDC2_CLK 101 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 398 Ou 7 Allwinner Technology CO Ltd A13 110 111 3 PE8 Select 000 Input 001 Output 010 011 CSI_D4 100 SDC2 CMD 101 2 0 R W 0 110 111 33 4 30 PE Configure Register 2 Register Name PE_CFG2 Offset 0x98 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 31 PE Configure Register 3 Register Name PE_CFG3 Offset 0x9C Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 32 PE Data Register Register Name PE_DAT Offset Ox AO Default Value 0x0000 0000 Bit Read Write Default Description 31 28 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the correspondi
31. A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 113 Ou Allwinner Technology CO Ltd A13 ite Hex VECTOR ADDR 31 2 R 0x0 This register present the vector address for the interrupt currently active on the CPU IRQ input ZERO 1 0 R 0x0 ore Always return zero to this field 13 4 2 Interrupt Base Address Register Default 0x00000000 Offset 0x04 Register Name INTC BASE ADDR REG Read Wr Default GER Bit Description ite Hex BASE_ADDR 31 2 R W 0x0 S e This bit field holds the upper 30 bits of the base address of the vector table ZERO 1 0 R 0x0 Re Always write zero to this bit field 13 4 3 Interrupt Protection Register Default 0x00000000 Offset 0x08 Register Name INC_PROTEC_REG 8 Read Wr Default ee Bit Description ite Hex 31 1 PROTECT_EN Enables or disables protected register access 0 disable protection mode 1 enable protection mode 0 R W 0x0 SE i If enabled only privileged mode access can access the interrupt controller registers If disabled both user mode and privileged mode can access the registers This register can only be accessed in privileged mode 13 4 4 NMI Interrupt Control Register Default 0x00000000 Offset 0x0C Register Name INTC_NMIIL CTRL REG Read Wr Default Ka Bit Description ite Hex 3
32. A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 391 GW 7 Allwinner Technology CO Ltd A13 1 0 3 00 Pull up down disable O1 Pull up 10 Pull down 11 Reserved 33 4 19 PD Configure Register 0 Register Name PD CFGO Offset Ox6C Default Value 0x0000 0000 Bit Read Write Default Description 31 PD7 Select 000 Input 001 Output 010 LCD_D7 011 100 101 30 28 R W 0 110 111 27 PD6 Select 000 Input 001 Output 010 LCD_D6 011 100 101 26 24 R W 0 110 111 23 PD5 Select 000 Input 001 Output 010 LCD D5 Ol 1 100 101 22 20 R W 0 110 111 19 PD4 Select 000 Input 001 Output 010 LCD_D4 011 100 101 18 16 R W 0 110 111 15 PD3 Select 000 Input 001 Output 010 LCD_D3 011 100 101 14 12 R W 0 110 111 11 PD2 Select 000 Input 001 Output 10 8 R W 0 010 LCD_D2 011 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 392 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 100 101 110 111 7 6 4 R W 0 3 2 0 R W 0 33 4 20 PD Configure Register 1 Register Name PD_CFG1 Offset 0x70 Default Value 0x0000_0000 Bit Read Write Default Description 31
33. IRQ60 PRIO IRQ 60 Priority Set priority level for IRQ bit 60 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 25 24 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 128 7 Allwinner Technology CO Ltd Offset 0x8C Register Name INTC_SRC_PRIO_REG3 A13 Level3 Ox1 level 3 highest priority 23 22 R W 0x0 IRQ59_PRIO IRQ 59 Priority Set priority level for IRQ bit 59 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 21 20 R W 0x0 IRQ58_PRIO IRQ 58 Priority Set priority level for IRQ bit 58 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 19 18 R W 0x0 IRQ57_PRIO IRQ 57 Priority Set priority level for IRQ bit 57 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 17 16 R W 0x0 IRQ56_PRIO IRQ 56 Priority Set priority level for IRQ bit 56 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 15 14 R W 0x0 IRQ55_PRIO IRQ 55 Priority Set priority level for IRQ bit 55 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3
34. PD15 Select 000 Input 001 Output 010 LCD_D15 011 100 101 30 28 R W 0 110 111 27 PD 14 Select 000 Input 001 Output 010 LCD_D14 011 100 101 26 24 R W 0 110 111 23 PD13 Select 000 Input 001 Output 010 LCD_D13 011 100 101 22 20 R W 0 110 111 19 PD12 Select 000 Input 001 Output 010 LCD_D12 011 100 101 18 16 R W 0 110 111 15 PD11 Select 000 Input 001 Output 010 LCD_D11 Ol 1 100 101 14 12 R W 0 110 111 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 393 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 11 PD10 Select 000 Input 001 Output 010 LCD D10 Ol 1 100 101 10 8 R W 0 110 111 7 6 4 R W 0 3 2 0 R W 0 33 4 21 PD Configure Register 2 Register Name PD_CFG2 Offset 0x74 Default Value 0x0000 0000 Bit Read Write Default Description 31 PD23 Select 000 Input 001 Output 010 LCD_D23 011 100 101 30 28 R W 0 110 111 27 PD22 Select 000 Input 001 Output 010 LCD_D22 011 100 101 26 24 R W 0 110 111 23 PD21 Select 000 Input 001 Output 010 LCD D21 Ol 1 100 101 22 20 R W 0 110 111 19 PD20 Select 000 Input 001 Output 010 LCD_D20 011 100 101 18 16
35. SIN SOUT S Stop gt 3 16 Bit Time gt 3 16 Bit Time SIR_OUT gt 3 16 Bit Time SIR IN Figure 19 2 Serial IrDA Data Format 19 3 UART Register List There are 2 UART controllers one with TX and RX only the other with TX RX RTS and CTS Module Name Base Address UARTI 0x01C28400 UART3 0x01C28C00 Register Name Offset Description UART RBR 0x00 UART Receive Buffer Register UART_THR 0x00 UART Transmit Holding Register UART_DLL 0x00 UART Divisor Latch Low Register UART_DLH 0x04 UART Divisor Latch High Register UART_IER 0x04 UART Interrupt Enable Register UART_IIR 0x08 UART Interrupt Identity Register UART_FCR 0x08 UART FIFO Control Register UART LCR 0x0C UART Line Control Register UART MCR 0x10 UART Modem Control Register UART_LSR 0x14 UART Line Status Register UART MSR 0x18 UART Modem Status Register UART_SCH Ox1C UART Scratch Register UART_USR Ox7C UART Status Register UART TFL 0x80 UART Transmit FIFO Level UART RFL 0x84 UART RFL UART HALT OxA4 UART Halt TX Register 19 4 UART Register Description 19 4 1 UART Receiver Buffer Register Offset 0x00 Register Name UART RBR A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Default Value 0x0000 0000 Bit Read Write Default Description 31 8
36. 11 3 ASYNC Timer Register Description 11 3 1 ASYNC Timer IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name ASYNC TMR IRQ EN REG Bit ME ER Description ite Hex 31 9 WDOG_INT_EN 8 R W 0x0 Watchdog Interrupt Enable 0 No effect 1 watchdog Interval Value reached interrupt enable 7 6 TMRS_INT_EN 5 R W 0x0 Timer 5 Interrupt Enable 0 No effect 1 Timer 5 Interval Value reached interrupt enable TMR4_INT_EN 4 R W 0x0 Timer 4 Interrupt Enable 0 No effect 1 Timer 4 Interval Value reached interrupt enable TMR3_INT_EN 3 R W 0x0 Timer 3 Interrupt Enable 0 No effect 1 Timer 3 Interval Value reached interrupt enable TMR2_INT_EN 2 R W 0x0 Timer 2 Interrupt Enable 0 No effect 1 Timer 2 Interval Value reached interrupt enable TMR1_INT_EN 1 R W 0x0 Timer 1 Interrupt Enable 0 No effect 1 Timer 1 Interval Value reached interrupt enable TMRO_INT_EN 0 R W 0x0 Timer 0 Interrupt Enable 0 No effect 1 Timer 0 Interval Value reached interrupt enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 89 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 11 3 2 ASYNC Timer IRQ Status Register Default 0x00000000 Offset 0x04 Register Name ASYNC TMR IRQ STAS REG Bit NG peu Description ite Hex 31 9 WDOG_IRQ PEND 8
37. 119 13 4 27 Interrupt Source Priority 1 Register Default OsOO0OO0O0O00 122 13 4 28 Interrupt Source Priority 2 Register Default OsOOOO0O0O00 125 13 4 29 Interrupt Source Priority 3 Register Default OsOOOO0O0O00 128 13 4 30 Interrupt Source Priority 4 Register Default OsOOOOO00O0 131 13 4 31 Interrupt Source Priority 5 Register Default OsOOOOO00O0 133 14 DMA Controller E 137 14 1 OVERVIEW E 137 142 DMA Description uivaisrsmriien itte hass adnbadeebendeendakn bas beknda ekke bas bkndnskkekn best anis ns 137 14 3 DMA Register EE 137 14 45 DMA Resister EE ae Lik eee sete cna eee 137 14 4 1 DMA IRQ Enable Register Default 0x00000000 rrrrrnrnrrnnrnnrnrverrnrnnrrnrerrnnnernn 137 14 4 2 DMA IRQ Pending Status Register Default 0Ox00000000 140 14 4 3 Normal DMA Configuration Register Default 0x00000000 N 0 7 2e 143 14 4 4 Normal DMA Source Address Register Default OxOO0O0O0O000 146 14 4 5 Normal DMA Destination Address Register Default Ox00000000 146 14 4 6 Normal DMA Byte Counter Register Default 0x00000000 ee eeeeeeeereeeees 146 14 4 7 Dedicated DMA Configuration Register Default 0x00000000 ranrrrnvrnnvernnrnenn 146 14 4 8 Dedicated DMA Source Start Address Register N 0 7 149 14 4 9 Dedicated DMA Destination Start Address Register N 0 7
38. 2013 Allwinner Technology All Rights Reserved 76 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Special Clock 1 Source Select 0 Special Clock 2 1 Special Clock 2 divide by 2 10 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 35 CSI Clock Default 0x00000000 Offset 0x134 Register Name CSI_CFG_REG Read Wr Default Bit f Description ite Hex SCLK_GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M CSI_RST 30 R W 0x0 CSI Reset 0 reset valid 1 reset invalid 29 27 CLK SRC SEL Clock Source Select 000 OSC24M 001 PLL3 1X 010 PLL7 1X 26 24 R W 0x0 0l1 100 101 PLL3 2X 110 PLL7 2X 111 23 18 17 16 15 5 CLK_DIV_RATIO_M 4 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 36 VE Clock Default 0x00000000 Offset 0x13C Register Name VE_CFG_REG Read Wr Default Bit A Description ite Hex A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved TT Jau 8 2013 Ou Allwinner Technology CO Ltd A13 SCLK GATING Gating the Special clock for VE 0 mask 1 pa
39. Ou 7 Allwinner Technology CO Ltd A13 DE FE 0x01E0 0000 0x01E1 FFFF 128K 0x01E2 0000 0x01E3 FFFF 128K DE_BE 0x01E6 0000 0x01E6 FFFF 64K IEP 0x01E7 0000 0x01E7 FFFF 64K 0x01E4 0000 0x01E5 FFFF 128K 0x01E8 0000 0x01E9 FFFF 128K 0x01EA 0000 0x01EB FFFF 128K 0x3F50 0000 0x3F50 FFFF 64K DDR II DDR II 0x4000 0000 0xBFFF FFFF 2G BROM OxFFFF 0000 0xFFFF 7FFF 32K A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 30 Ou Allwinner Technology CO Ltd A13 4 Boot System 4 1 Overview With one 32KB ROM the A13 supports five boot methods The system can boot sequencially from NAND Flash SPI NOR Flash SD Card and USB However if the external boot select pin BSP which is pulled up by an internal 50K resistor in normal state is checked by boot code to be on low level state after system power on the system will directly jump to boot from USB 4 2 Boot Diagram Power e state of BSP Yes pinis 0 No SDCO PF port boot operation SDCO Boot Success lt g NAND Flash boot operation CEO FC Boot Yes Success Ah SDC2 PC port boot operation No SDC2 Boo Success lt g No SPIO PC port boot operation SPI Nor Flas i Yes Boot Success No boot OK run other firmware USB b
40. PWMO_BYPASS PWM CHO bypass enable If the bit is set to 1 PWMO s output is OSC24MHz 0 disable 1 enable R W 0x0 PWM CHO PUL START PWM Channel 0 pulse output start 0 no effect 1 output 1 pulse The pulse width should be according to the period 0 register 15 0 and the pulse state should be according to the active state After the pulse is finished the bit will be cleared automatically R W 0x0 PWM_CHANNELO_MODE 0 cycle mode 1 pulse mode R W 0x0 SCLK CHO GATING Gating the Special Clock for PWMO 0 mask 1 pass R W 0x0 PWM CHO ACT STA PWM Channel 0 Active State 0 Low Level 1 High Level R W 0x0 PWM CHO EN PWM Channel 0 Enable 0 Disable 1 Enable 3 0 R W 0x0 PWM CHO PRESCAL PWM Channel 0 Prescalar These bits should be setting before the PWM Channel 0 clock gate on 0000 120 0001 180 0010 240 0011 360 0100 480 O101 0110 0111 1000 12k 1001 24k 1010 36k 1011 48k 1100 72k 1101 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 86 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1110 LILL 1 10 3 2 PWM Channel 0 Period Register Offset 0x204 Register Name PWM CHO PERIOD REG Read Wr Default Geck Bit Description ite Hex PWM_ENT_CYC Number of the entire cycles in the PW
41. R W 0 1 Enable 33 4 60 PIO Interrupt Status Register Offset 0x214 Register Name PIO INT STATUS Default Value 0x0000 0000 Bit Read Write Default Description External INTn Pending Bit n 0 31 0 No IRQ pending n 1 IRQ pending n 0 31 R W 0 Write 1 to clear 33 4 61 PIO Interrupt Debounce Register Register Name PIO_INT_DEB Offset 0x218 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 Debounce Clock Pre scale n 6 4 R W 0 The selected clock source is prescaled by 2 3 1 PIO Interrupt Clock Select 0 32KHz 0 R W 0 1 24MHz A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 407 Jau 8 2013 Allwinner Technology CO Ltd A13 34 Declaration This A13 user manual is the original work and copyrighted property of Allwinner Technology Allwinner Reproduction in whole or in part must obtain the written approval of Allwinner and give clear acknowledgement to the copyright owner The information furnished by Allwinner is believed to be accurate and reliable Allwinner reserves the right to make changes in circuit design and or specifications at any time without notice Allwinner does not assume any responsibility and liability for its use Nor for any infringements of patents or other rights of the third parties which may result from its use No license
42. Read Wr Default SC Bit Description ite Hex 31 18 CPU_CLK_SRC_SEL CPU Clock Source Select 00 32KHz OSC Internal 17 16 R W Ox1 01 OSC24M 10 PLLI 11 200MHz source from the PLL6 If the clock source is changed at most to wait for 8 present running clock A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 63 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 cycles 15 10 APBO CLK RATIO APBO Clock divide ratio APBO clock source is AHB2 clock 00 2 01 2 10 4 11 8 9 8 R W 0x0 AHB_CLK_SRC_SEL 00 AXI 7 6 R W 0x0 01 CPUCLK 10 PLL6 2 11 AHB_CLK_DIV_RATIO AHB Clock divide ratio AHB clock source is AXI Clock 5 4 R W 0x1 00 1 01 2 10 4 11 8 3 2 AXI_CLK_DIV_RATIO AXI Clock divide ratio AXI Clock source is CPU clock 1 0 R W 0x0 00 1 01 2 10 3 11 4 6 4 15 APB1 Clock Divide Ratio Default 0x00000000 Offset 0x58 Register Name APB1_CLK_DIV_REG Read W Default PEN Bit i Description rite Hex 31 26 APB1_CLK_SRC_SEL APB1 Clock Source Select 00 OSC24M 01 PLL6 set to 1 2GHz 10 32KHz 11 This clock is used for some special module apbclk TWI UART and SCR Because these modules need special clock rate even if the apbclk changes 25 24 R W 0x0 A13 User Manual V
43. Support direct display and write back to memory 27 2 DEFE Block Diagram HO wg Register file 4 Output d r gt sae gt CSC m gt Se display DMAC Figure 27 1 DEFE Block Diagram 27 3 DEFE Description DEFE supports scaling or resizing of planar or interleaved video component data Resizing or scaling the image means generating a new image that is larger or smaller than the original The new image will have a larger or smaller number of pixels in the horizontal and or vertical directions than the original image Filtering provides image enhancement and scaler provides high quality 4 tap in horizontal and 4 tap in vertical filtering A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 286 Jau 8 2013 Allwinner Technology CO Ltd A13 of YUV or RGB data 27 3 1 Re Sampling Up sampling is the process of inserting new data samples between original data samples to increase the sampling rate Down sampling is the process of reducing the sampling rate by removing or throwing away original data samples In order to generate the output pixels one first needs to relate the output grid to the input grid Scaling is a pixel transformation in which an array of output pixels is generated from an array of input pixels The value of each pixel on the output pixel grid is calculated from the values
44. V G component coefficient G V B component coefficient B V constant Ou Allwinner Technology CO Ltd A13 Line TIR Line KKK D gt Re BARK BAKKA RJ BAKKA RSR REX ATA AA X T O yl X Y Sample O UV CbCr Sample YUVIYCDCr 4 4 4 formatting YUVKCOCE ee formatting Line XX XX X Line EX KAKA KA O O O O DER XX XX B X XK OO KA 7 2e 2 B X Xe x O O O O RA AA B X KB KAKA x Y Sample O UV CbCr Sample x Y Sample O UV CbCr Sample YCbCr 4 2 0 formatting YCbCr 4 1 1 formatting 27 3 7 Image Data Memory Mapping The DEFE not only supports the sequence non tile based format input data but also the tile based format input data The tile based format data is valid for YUV422 YUV420 and YUV411 when input data mode is planar or UV combined mode In different conditions the tile based format memory mapping can refer to the following Tile Based UV Combined Mode Y component mapping The mapping of Y component is the same in YUV422 YUV420 and YUV411 UV component mapping YUV422 AW Allwinner Technology CO Ltd A13 uo vo ut vi u2 v2 u3 vs ua va us vs ue ve u7 v7 us vs us uz vi2 ui3 vi3 Via uis vis
45. bit can be set to I In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note 1 If the clock source is External CLKIN the interval value register is not used the current value register is an up counter that counting from 0 2 The time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 15 ASYNC Timer 4 Interval Value Register Offset 0x54 Register Name ASYNC TMR4 INTV VALUE REG Read Wr Default a Bit Description ite Hex TMR4_INTV_VALUE Timer 4 Interval Value 31 0 R W D Note the value setting should consider the system clock and the timer clock source 11 3 16 ASYNC Timer 4 Current Value Register Offset 0x58 Register Name ASYNC TMR4 CURNT VALUE REG Read Wr Default Bit f Description ite Hex TMR4_CUR_VALUE Timer 4 Current Value 31 0 R W D Note 1 Timer current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 2 Before the timer 4 is enabled its current value register needs to be written with zero 11 3 17 ASYNC Timer 5 Control
46. 0 No effect 1 Pending Set 1 to the bit will clear 22 R W 0x0 DDMA3_HF_IRQ_PEND Dedicated DMA 3 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 21 R W 0x0 DDMA2_END_IRQ_PEND Dedicated DMA 2 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 20 R W 0x0 DDMA2_HF_IRQ_PEND Dedicated DMA 2 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 19 R W 0x0 DDMA1_END_IRQ_PEND Dedicated DMA 1 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 18 R W 0x0 DDMA1_HF_IRQ_PEND Dedicated DMA 1 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 17 R W 0x0 DDMA0_END_IRQ_PEND Dedicated DMA 0 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 16 R W 0x0 DDMA0_HF_IRQ_PEND Dedicated DMA 0 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 15 R W 0x0 NDMA7_END_IRQ_ PEND Normal DMA 7 End Transfer Interrupt Pending Set 1 to the bit will clear it A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 141 Ou 7 Allwinner Technology CO Ltd A13 0 No effect 1 Pend
47. 01 4 6ms 10 8 12ms 11 16 24ms 1 0 R W 0x0 23 4 10 DAC TX Counter Register Offset 0x30 Register Name AC_DAC_CNT Bit Read Write Default Description TX_CNT TX Sample Counter The audio sample number of sending into TXFIFO When one sample is put into TXFIFO by DMA or by host IO the TX sample counter register increases by one The TX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should count on base of this initial value 31 0 R W 0x0 Notes It is used for Audio Video Synchronization 23 4 11 ADC RX Counter Register Offset 0x34 Register Name AC_ADC_CNT Bit Read Write Default Description RX_CNT RX Sample Counter The audio sample number of writing into RXFIFO When one sample is 31 0 R W 0x0 written by Digital Audio Engine the RX sample counter register A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 252 Jau 8 2013 Allwinner Technology CO Ltd A13 increases by one The RX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should count on base of this initial value Notes It is used for Audio Video Synchronization A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 253 Jau 8 2013 Ou Allwinner Tec
48. 0110 6sec 0111 8sec 1000 10sec 1001 12sec 1010 14sec A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 101 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1011 16sec 1100 1101 1110 1111 0x0 WDOG_RST_EN Watchdog Reset Enable 0 No effect on the resets 1 Enables the Watchdog to activate the system reset 0x0 WDOG_EN Watchdog Enable 0 No effect 1 Enable the Watchdog 11 3 26 64 bit Counter Low Register Default 0x00000000 Offset OxA4 Register Name COUNTER64_LOW_REG Read Wr Default o Bit f Description ite Hex CONT64_LO 31 0 R W 0x0 64 bit Counter 31 0 11 3 27 64 bit Counter High Register Default 0x00000000 Offset OxA8 Register Name COUNTER64_HI_REG Read Wr Default SC Bit Description ite Hex CONT64_HI 31 0 R W 0x0 64 bit Counter 63 32 11 3 28 64 bit Counter Control Register Default 0x00000000 Offset OxAO Register Name COUNTER64_CTRL_REG Read Wr Default Ge Bit Description ite Hex 31 3 CONT64_CLK_SRC_SEL 64 bit Counter Clock Source Select 2 R W 0x0 0 OSC24M 1 PLL6 6 CONT64_RLATCH_EN 64 bit Counter Read Latch Enable 1 R W 0x0 ZE Sek 0 no effect 1 to latch the 64 bit Counter to the Low Hi registers and it will change to zero after the regi
49. Default Bit Description ite Hex 31 24 STMR1_INTV_VALUE_HI 23 0 R W x Sync Timer 1 Interval Value 55 32 Note the interval value register is a 56 bit register When read or write the interval value the Low register should be read or write first And the High register should be written after the Low register 12 3 11 Sync Timer 1 Current Value Low Register Offset 0x3C Register Name SYNC_TMR1_CURNT_LOW_REG Read Wr Default 2 Bit Description ite Hex STMR1_CUR_VALUE_LOW 31 0 R W x i Sync Timer 1 Current Value 31 0 12 3 12 Sync Timer 1 Current Value High Register Offset 0x40 Register Name SYNC TMR1 CURNT HI REG Read Wr Default WW Bit Description ite Hex 31 24 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 108 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 STMR1 CUR VALUE HI Sync Timer 1 Current Value 55 32 23 0 Note Timer 0 current value is a 56 bit down counter from interval value to 0 The current value register is a 56 bit register When read or write the current value the Low register should be read or written first A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 109 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 13 Interrupt Controller 13 1 Overview The interrupt controller featur
50. Offset 0x044 Register Name TCONO data clock register A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 353 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Read Wr Default Bit Description ite Hex 31 R W 0 TCONO_Dclk_En 30 6 TCONO Delk Div Tdclk Tsclk DCLKDIV 6 0 R W 0 Note L if dclk1 amp dclk2 used DCLKDIV gt 6 2 if delk only DCLKDIV gt 4 29 3 9 TCONO BASICO_REG Offset 0x048 Register Name TCONO basic timing register0 Read Wr Default L Bit Description ite Hex 31 27 TCONO_X 26 16 R W 0 er Panel width is X 1 15 11 TCONO_Y 10 0 R W 0 Gerbe Panel height is Y 1 29 3 10 TCONO BASIC1 REG Offset 0x04C Register Name TCONO basic timing register 1 Read Wr Default SSC Bit Description ite Hex 31 28 HT Thcycle HT 1 Tdclk 27 16 R W 0 Note 1 parallel HT gt HBP 1 X 1 2 2 serial 1 HT gt HBP 1 X 1 3 2 3 serial 2 HT gt HBP 1 X 1 3 2 2 15 10 29 3 11 TCONO BASIC2 REG Offset 0x050 Register Name TCONO basic timing register2 Read Wr Default sch Bit Description ite Hex 31 21 VT 27 16 R W 0 TVT VT 2 Thsync Note VT 2 gt VBP 1 Y 1 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 354
51. Reserved DBS output buffer selected status 0 Selected output buffer A 1 Selected output buffer B DBE Double buffer mode enable 0 disable 1 enable If the double buffer mode is disabled the buffer A will be always selected by CSI module A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 280 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 26 4 9 CSI Status Register Register Name CSI STA REG Offset Address 0X002C Default Value 0X00000000 8 Read Wri Default SC Bit Description te Hex LUM_STAT_VALUE luminance statistical value 31 08 When frame done interrupt flag come value is ready and will last until next frame done For raw data value G gt gt 1 R G gt gt 8 For yuv422 value Y gt gt 8 VIDEO_CAP_ON Video capture in progress Indicates the CSI is capturing video image data multiple frames The bit is set at the start of the first frame after enabling video capture When software disables video capture it clears itself after the last pixel of the current frame is captured STILL_CPT_ON Still capture in progress Indicates the CSI is capturing still image data single frame The bit is set at the start of the first frame after enabling still frame capture It is self cleared after the last pixel of the first frame is captured For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end and the other fram
52. 11 25 24 R W 0x0 23 18 CLK_DIV_RATIO_N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 28 SPR Clock Default 0x00000000 Offset OxA8 Register Name SPI2_SCLK_CFG_REG Read Wr Default E Bit Description ite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLL5 11 25 24 R W 0x0 23 18 CLK DIV RATIO M 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 72 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 29 IR Clock Default 0x00000000 Offset OxBO Register Name IR SCLK CFG REG Read Wr Default aan Bit Description ite Hex SCLK_GATING Gating Special Cloc
53. 11 23 18 CLK DIV RATIO N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 26 SPIO Clock Default 0x00000000 Offset OxAO Register Name SPI 0 SCLK CFG REG Bit EEN Description ite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 25 24 R W 0x0 ee i 01 PLL6 10 PLLS 11 23 18 CLK DIV RATIO N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 27 SPI Clock Default 0x00000000 Offset OxA4 Register Name SPI1_SCLK_CFG_REG Bit Read Wr Default Description A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 71 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 ite Hex SCLK GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLL5
54. 17 16 15 4 2 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 40 MBUS Clock Control Default 0x00000000 Offset 0x15C Register Name MBUS_SCLK_CFG_REG Bit E SE Description ite Hex MBUS_SCLK_GATING Gating Clock for MBUS Max Clock 300MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON MBUS_CLOCK Clock Source Divider N Divider M 30 26 MBUS_SCLK_SRC Clock Source Select 25 24 R W 0x0 i ania 01 PLL6 10 PLL5 11 Reserved 23 18 MBUS_SCLK_RATIO_N 17 16 R W 0x0 Clock Pre divide Ratio N The select clock source is pre divided by 2 N The divider is 1 2 4 8 15 4 3 0 R W 0x0 MBUS_SCLK_RATIO_M A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 79 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Clock Divide Ratio M The divided clock is divided by M 1 The divider is from I to 16 6 4 41 IEP Clock Control Default 0x00000000 Offset 0x160 Register Name IEP SCLK CFG REG Read Wr ite Bit Default Hex Description 31 R W 0x0 IEP_SCLK_GATING Gating Clock for IEP Max Clock 300MHz 0 Clock is OFF 1 Clock is ON IEP CLOCK BE Clock 30 R W 0x0 IEP_RST IEP Reset 0 reset valid 1 reset invalid 29 0 A13 User Manual V1 2 Copyri
55. 31 00 R W o Luminance statistics data 30 2 15 Luminance Histogram Statistics Counter Recording Register Offset 0X0060 0X007C Register Name IMGEHC_LHSCNT_REG Read Wri Default ae Bit Description te Hex LH_CNT_DATA 31 00 R W vedk Luminance statistics data YUV to RGB conversion algorithm formula R R Y component coefficient Y R U component coefficient U R V component coefficient V R constant G G Y component coefficient Y G U component coefficient U G V component coefficient V G constant B B Y component coefficient Y B U component coefficient U B V component coefficient V B constant A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 369 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 30 2 16 CSC Y G Coefficient Register Offset G Y component 0X00C0 R U component 0X00C4 B V component 0X00C8 Read Wri Default a Bit Description te Hex Register Name IMGEHC_CSCYGCOFF_REG Oxda7 CSC_YG_COFF Ox le6f the Y G coefficient Ox cbf the value equals to coefficient 2 30 2 17 CSC Y G Constant Register Offset OXOOCC Register Name IMGEHC_CSCYGCON_REG Read Wri Default Sc Bit Description te Hex 31 14 CSC_YG_CON 13 00 R W the Y G constant the value equals to coefficient 2 30 2 18 CSC U R Coefficient Register Offset G Y component 0X00D0 R U componen
56. A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 4 Jau 8 2013 7 Allwinner Technology CO Ltd A13 5 3 18 PMU VF Table Register 2 eege EE EES ni 40 5 3 19 PMU VF Table Register EE 41 5 3 20 PMU VF Table R gister ss etches 41 5 3 21 PMU VF Table E 41 5 3 22 PMU VF Table Register dE 41 5 3 23 PMU VF Table Register 7 iii 41 5 3 24 PMU VF Table Register eessen 42 5 3 25 PMU VF Table Register E 42 5 3 26 PMU VF Table Register 10 iii 42 5 3 27 PMU VF Table Register 11 42 5 3 28 PMU VF Table Register Tasse EES 43 5 3 29 PMU VF Table Register 1S E 43 5 3 30 PMU VF Table Register E 43 5 3 31 PMU VF Table Register 15 iii 43 5 3 32 PMU VF Table Register 16 cs0cne ie eit tie 43 5 3 33 PMU VF Table Register ARS a ne 44 5 3 34 PMU VF Table Register 18 25 5045 e ee AEN ee neha asasan anaana aaea 44 5 3 35 PMU VF Table Valid Register 44 5 3 36 PMU VF Table Index Register 45 5 3 37 PMU VF Table Range Register sr 45 5 3 38 PMU Speed Factor Register OS ec dees acme 45 5 3 39 PMU Speed Factor Regelen 46 5 3 40 PMU Speed Factor Register Lausanne 47 5 3 41 CPU Idle Counter Low Register Default OxvOO0O0O0D000 48 5 3 42 CPU Idle Counter High Register Default 0x00000000 rrrrrrvrrenrnrrrrrnrrrrrerrnnnernn 48 5 3 43 CPU Idle Control Register Default OsO00O0O000O0 48 5 3 44 CPU Idle Status Register Default 0x00000000 rrrrrnrnrrrnverrnrverrn
57. DMA Direct Memory Access A feature of modern computers that allow certain hardware subsystems within the computer to independently of the CPU access system memory PWM Pulse Width Modulation A commonly used technique for controlling power to inertial electrical devices made practical electronic by modern power switches Audio Codec Audio Codec A computer program implementing an algorithm that compresses and decompresses digital audio data according to a given audio file format or streaming media audio format 10 SD 3 0 Security Digital 3 0 A non volatile memory card format developed by the SD Card Association for use in portable devices 11 USB OTG USB On The Go dual role controller which supports both is full compliant with the On The Go Supplement Host and device functions and A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou Allwinner Technology CO Ltd A13 to the USB 2 0 Specification Revision 1 0a 12 EHCI Enhanced Host Controller a high speed controller standard that is Interface publicly specified A register level interface that enables a host controller for USB or FireWire hardware to 13 OHCI Open Host Controller Interface A communicate with a host controller driver in software 14 TP Touch Panel A Human Machine Interactive Interface Low Resolution Analog t
58. EHCI Current Asynchronous List Address Register A 218 22 5 12 EHCI Configure Flag Register cc ccecc SN RS SN EE En 219 22 5 13 EHCI Port Status and Control Register eseu 219 22 6 Eeler 224 22 6 1 H R vision Register seen anna tante ten then 224 22 6 2 1650 go Br nt 224 22 6 3 HcCommandStatus Register L nnanmnmenienneineeiveinhnjele jaja 226 22 6 4 HclnterruptStatus gr es EEE EE EE EEE EEE 227 22 6 5 HcinterruptEnable Register 228 22 6 6 HcinterruptDisable Register 229 22 6 7 HeHGCCA REGISTE EE 230 22 6 8 lee eet ee E 230 22 6 9 HcControlHeadED EE 230 22 6 10 JHeContrelCurrentED Registe esscr eege 231 22 6 11 HcBulkHeadED Register sis 231 22 6 12 HcBulkCurrentED Register sci tecnscunsiesectendsanstanteestenatanadnncdanadanndensdanntacstancienstundtuadiieds 232 22 6 13 HcDoneHead Register sisi 232 22 6 14 HeFmint rval Register 4 agnns ant asset etc abata nets 232 22 6 15 HcFmRemaining Register 233 22 6 16 HcFmNumber Register iii 233 22 6 17 Elektriker 234 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 12 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 22 6 18 HcLSThreshold R gser Lameraeaaaakeasennennasninteinnbemnniinemieik 234 22 6 19 HcRhDescriptorA Register AAA 234 22 6 20 HcRhDescriptorB Register 236 22 6 21 HeRhStatus Registera RES 236 22 6 22 HcRhPortStatus e EE 237 22 7 USB Host Special Requirement
59. Jau 8 2013 Ou 7 Allwinner Technology CO Ltd 01 16 bit 10 32 bit 11 A13 NDMA SRC BST LEN DMA Source Burst Length 00 1 01 4 10 8 11 8 7 R W 0x0 6 NDMA_SRC_ADDR_TYPE Normal DMA Source Address Type 0 Increment 1 No Change 5 R W 0x0 NDMA_SRC_DRQ_TYPE Normal DMA Source DRQ Type 00000 IR RX 00001 00010 00011 00100 00101 00110 00111 01000 01001 UARTI RX 01010 01011 UART3 RX 01100 01101 01110 O1111 S mn 4 0 R W 0x0 10000 10001 10010 10011 Audio Codec A D 10100 10101 SRAM range 10111 11001 10110 TP A D 11000 SPI RX SDRAM SPIO RX A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 145 Ou 7 Allwinner Technology CO Ltd A13 11010 SPR RX 11011 USB EP1 11100 USB EP2 11101 USB EP3 11110 USB EP4 11111 USB EP5 14 4 4 Normal DMA Source Address Register Default 0x00000000 Offset 0x 100 N 0x20 0x4 N 0 1 52 3 4 5 6 7 Register Name NDMA_SRC_ADDR_REG Read Wr Default So Bit Description ite Hex NDMA_SRC_ADDR 31 0 R W x Normal DMA Source Address 14 4 5 Normal DMA Destination Address Register Default 0x00000000 Offset 0x 100 N 0x20 0x8 N 0 1 2 3 4 5 6 7 Register Name NDMA DEST A
60. SE Bit Description te Hex 8 bits unsigned intensity coefficient data Ga few fo 2316 mw 0 Sits unsigned intensity coefficient data Ee 15 08 8 bits unsigned intensity coefficient data A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 371 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 07 00 RW In 8 bits unsigned intensity coefficient data 30 2 24 DRC Luminance Gain Coefficient Offset 0X0200 0X03FC Register Name IMGEHC_DRCLGCOFF Read Wri Default SC Bit Description te Hex 16bits luminance gain coefficient unsigned data The high 5 bits is the integer part The low 11 bits is the decimal part 16bits luminance gain coefficient unsigned data The high 5 bits is the integer part The low 11 bits is the decimal part A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 372 Jau 8 2013 GW Allwinner Technology CO Ltd A13 31 Security System SS 31 1 Overview The Security System SS is one encrypt decrypt function accelerator suitable for a variety of applications It supports both encryption and decryption and several modes Besides both CPU mode and DMA method are supported for different applications It features Support AES DES 3DES SHA 1 MD5 Support ECB CBC CNT modes for AES DES 3DES 128 bits 192 bits and 256 bits key size for AES 160 bits hardware PRNG with 192 bits seed Support 32 wo
61. SRAM CFG REGI Bit Me PEL Description ite Hex 31 R W 0x0 30 18 17 R W 0x0 16 R W 0x0 15 14 R W 0x0 13 SRAM_C3_MAP SRAM C3 map config 12 R W Ox1 0 map to CPU BIST 1 map to ISP 11 6 SRAM A3 A4 MAP SRAM Area A3 A4 Configuration by AHB 5 4 R W 0x0 00 map to CPU DMA 01 10 11 3 1 SRAM_D_MAP SRAM D Area Config 0 R W 0x0 0 map to CPU DMA 1 map to USB OTG A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 82 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 8 CPU Control 8 1 CPU Register List Module Name Base Address CPU CTL 0x01C23400 Register Name Offset Description CPU CTRL REG 0x0020 CPU Control Register 8 2 CPU Control Register Description 8 2 1 CPU Control Register Default 0x00000002 Offset 0x20 Register Name CPU_CTRL_REG Read Wr Default SE Bit Description ite Hex 31 9 l CPU_ID 8 R W 0x0 CPU ID Option 7 2 R W 0x1 CP15_WRITE_DISABLE Disable write access to certain CP15 registers 0 R W 0x0 0 enable 1 disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 83 Jau 8 2013 Allwinner Technology CO Ltd A13 9 SDRAM Controller 9 1 Overview The SDRAM Controller DRAMC provides a simple flexible burst optimized interface to all
62. gistermmn svevet 202 20 3 3 CIR Receiver FIFO FEST 202 20 3 4 CIR Receiver Interrupt Control Register 202 20 3 5 CIR Receiver Status Register aces ee Ne 203 20 3 6 CIR Configure e EE 204 21 USB OTG Controller ccccccccssccsscesscescecscesscesscesscessceascesscesscesscesscessceascesscesscesscesscesscesscesscesscesscensoes 206 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 11 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 2k VEE 0 EE 206 21 2 USB OTG Timing Dagtramt ege eegne 206 22 USB Host Controller sicticscicss caiscasscencsasssassdavssaseceussasevedssededavsceseveisseNeteussesevedssadesavesesevetsseveravedededatesevesesseas 207 22 1 OV LVIEW cited coin eee ne eee de eed ed A ee 207 22 2 USB Host Block Didra airis eeEkEAE tens case s acs ete 5 fede etaten aat in tenants 207 22 3 USB Host Timing Egeter 207 224 AUSBHOSCRERISEE PAST EEE EE AE A EE E ERA 208 22 5 BHCIRe sister DEScripuon enge eege 209 22 5 1 EHCI Identification E ET 209 22 5 2 EHCI Host Interface Version Number Register 209 22 5 3 EHCI Host Control Structural Parameter Register 209 22 5 4 EHCI Host Control Capability Parameter Register 210 22 5 5 EHCI Companion Port Route Descriptions 211 22 5 6 EHCI USB Command Te E 212 22 5 7 elei 215 22 5 8 EHCI USB Interrupt Enable PETER 217 22 5 9 EHCI Frame Index e EE 217 22 5 10 EHCI Periodic Frame List Base Address Register 218 22 5 11
63. 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 13 4 31 Interrupt Source Priority 5 Register Default 0x00000000 Offset 0x94 Register Name INTC_SRC_PRIO_REGS A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 133 Jau 8 2013 Ou Allwinner Technology CO Ltd Offset 0x94 Register Name INTC_SRC_PRIO_REGS A13 Read Wr ite Bit Default Hex Description 31 30 R W 0x0 IRQ95_PRIO IRQ 95 Priority Set priority level for IRQ bit 95 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 29 28 R W 0x0 IRQ94_PRIO IRQ 94 Priority Set priority level for IRQ bit 94 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 27 26 R W 0x0 IRQ93_PRIO IRQ 93 Priority Set priority level for IRQ bit 93 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 25 24 R W 0x0 IRQ92_PRIO IRQ 92 Priority Set priority level for IRQ bit 92 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 23 22 R W 0x0 IRQ91_PRIO IRQ 91 Priority Set priority level for IRQ bit 91 Level0 0x0
64. 0x0 Vertical tap0 coefficient The value equals to coefficient 2 27 5 52 DEFE CH1 HORZCOEFO REGN N 0 31 Offset 0x600 N 4 Register Name DEFE CH1 HORZCOEFO REGN Bit FE ome Description ite Hex TAP3 31 24 R W 0x0 Horizontal tap3 coefficient The value equals to coefficient 2 TAP2 23 16 R W 0x0 Horizontal tap2 coefficient The value equals to coefficient 2 TAP1 15 8 R W 0x0 Horizontal tap1 coefficient The value equals to coefficient 2 TAPO 7 0 R W 0x0 Horizontal tap0 coefficient The value equals to coefficient 2 27 5 53 DEFE CH1 VERTCOEF REGN N 0 31 Offset 0x700 N 4 Register Name DEPE CH1 VERTCOEF REGN Read Wr Default sch Bit Description ite Hex A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 313 Ou Allwinner Technology CO Ltd 31 24 R W 0x0 TAP3 Vertical tap3 coefficient The value equals to coefficient 2 A13 23 16 R W 0x0 TAP2 Vertical tap2 coefficient The value equals to coefficient 2 15 8 R W 0x0 TAP1 Vertical tap1 coefficient The value equals to coefficient 2 7 0 R W 0x0 TAPO Vertical tap0 coefficient The value equals to coefficient 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 314 GW Allwinner Technology CO Ltd A13 28 Display Engine Back End DEBE 28 1 Ov
65. 0x1 level 3 highest priority 13 12 R W 0x0 IRQ54_PRIO IRQ 54 Priority Set priority level for IRQ bit 54 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 7 Allwinner Technology CO Ltd Offset 0x8C Register Name INTC_SRC_PRIO_REG3 A13 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 11 10 R W 0x0 IRQ53_PRIO IRQ 53 Priority Set priority level for IRQ bit 53 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 9 8 R W 0x0 IRQ52_PRIO IRQ 52 Priority Set priority level for IRQ bit 52 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 7 6 R W 0x0 IRQ51_PRIO IRQ 51 Priority Set priority level for IRQ bit 51 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 5 4 R W 0x0 IRQ50_PRIO IRQ 50 Priority Set priority level for IRQ bit 50 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 3 2 R W 0x0 IRQ49_PRIO IRQ 49 Priority Set priority level for IRQ bit 49 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level
66. 1 TXFIFO is underrun 13 R W TO TXFIFO Overflow This bit is set when the TXFIFO overflows Writing 1 to this bit clears it 0 TXFIFO is not overflowed 1 TXFIFO is overflowed 12 R W TXFIFO 3 4 empty This bit is set if the TXFIFO is more than 3 4 empty Writing 1 to this bit clears it 11 R W TXFIFO 1 4 empty This bit is set if the TXFIFO is more than 1 4 empty Writing 1 to this bit clears it 10 R W TF TXFIFO Full This bit is set when the TXFIFO is full Writing 1 to this bit clears it 0 TXFIFO is not Full 1 TXFIFO is Full R W THE TXFIFO Half empty This bit is set if the TXFIFO is more than half empty Writing 1 to this bit clears it 0 TXFIFO holds more than half words 1 TXFIFO holds half or fewer words R W TE TXFIFO Empty This bit is set if the TXFIFO is empty Writing I to this bit clears it 0 TXFIFO contains one or more words 1 TXFIFO is empty R W RU RXFIFO Underrun When set this bit indicates that RXFIFO has underrun Writing 1 to this bit clears it R W RO RXFIFO Overflow When set this bit indicates that RXFIFO has overflowed Writing 1 to this bit clears it 0 RXFIFO is available 1 RXFIFO has overflowed R W RXFIFO 3 4 Full A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 178 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 This bi
67. 10 1 a E 85 10 2 A NEE 85 10 3 PWM Register Description sista nn et enr ne 85 10 3 1 PWM Control Register Default 0x00000000 rrrrrrrrrrnrnnrrnrnnrrrvrrrnrnerrnrerrrnnerennnn 85 10 3 2 PWM Channel 0 Period Register 87 11 Asynchronic Timer s eeeseseseennesnnennneenneenneennennnennnennnennneennennnennnesnnennnennnennnennneennennnennnennnesnnennnennnennneenneenneenneeen 88 EDEN NN 88 1125 ASYNC Timer Register List aure 88 11 3 ASYNC Timer Register Description ewnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnennnnnnnnnnnsnnneee 89 11 3 1 ASYNC Timer IRQ Enable Register Default 0x00000000 rrrrrrrnrnrrrnrnrrrnverrnnnernn 89 11 3 2 ASYNC Timer IRQ Status Register Default Ox 0O00O0D000 90 11 3 3 ASYNC Timer 0 Control Register Default OxvDOOO0OOD4A 90 11 3 4 ASYNC Timer 0 Interval Value Register 91 11 3 5 ASYNC Timer 9 Current Value Register ncn tee ee 92 11 3 6 ASYNC Timer 1 Control Register Default OsDOOO0OO04 92 11 3 7 ASYNC Timer 1 Interval Value Register cescesseeseceeeseesseeseaeeeeetseeteaeeeneeeeees 93 11 3 8 ASYNC Timer 1 Current Value Register e ceescesseeceeeeeseeeseeseaeeeseesseessaeeeseeesaees 93 11 3 9 ASYNC Timer 2 Control Register Default OsvDOOO0OOD4 93 11 3 10 ASYNC Timer 2 Interval Value Register ss 94 11 3 11 ASYNC Timer 2 Curren
68. 101 18 16 R W 0 110 EINT12 111 15 PG11 Select 000 Input 001 Output 010 SPIL MOSI 011 UART3 CIS 100 101 14 12 R W 0 110 EINT11 111 11 PG10 Select 000 Input 001 Output 010 SPIL CLK 011 UART3 RX 100 101 10 8 R W 0 110 EINT10 111 7 PG9 Select 000 Input 001 Output 010 SPI1_CSO 011 UART3_TX 100 101 6 4 R W 0 110 EINT9 111 3 2 0 R W 0 33 4 48 PG Configure Register 2 Register Name PG_CFG2 Offset OxEO Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 49 PG Configure Register 3 Register Name PG_CFG3 Offset OxE4 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 404 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 33 4 50 PG Data Register Register Name PG DAT Offset OxE8 Default Value 0x0000 0000 Bit Read Write Default Description 31 28 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If 27 0 R W 0 the port is configured as functional pin the undefined value will be read 33 4 51 PG Multi Driving Register 0
69. 18 Priority Set priority level for IRQ bit 18 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Offset 0x84 Register Name INTC SRC PRIO REGI Level3 Ox1 level 3 highest priority 3 2 R W 0x0 IRQ17_PRIO IRQ 17 Priority Set priority level for IRQ bit 17 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 1 0 R W 0x0 IRQ16_PRIO IRQ 16 Priority Set priority level for IRQ bit 16 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 13 4 28 Interrupt Source Priority 2 Register Default 0x00000000 Offset 0x88 Register Name INTC_SRC_PRIO_REG2 Read Wr ite Bit Default Hex Description 31 30 R W 0x0 IRQ47_PRIO IRQ 47 Priority Set priority level for IRQ bit 47 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 29 28 R W 0x0 IRQ46_PRIO IRQ 46 Priority Set priority level for IRQ bit 46 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 27 26 R W A13 User Manual V1 2
70. 2 R W 0 1 1 5 stop bits when DLS LCR 1 0 is zero else 2 stop bit DLS Data Length Select It is writeable only when UART is not busy USR 0 is zero and always readable This is used to select the number of data bits per character that the peripheral transmits and receives The number of bit that may be selected areas follows 00 5 bits O1 6 bits 10 7 bits 1 0 R W 0 11 8 bits 19 4 9 UART Modem Control Register Register Name UART MCR Offset 0x10 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 SIRE SIR Mode Enable 0 IrDA SIR Mode disabled 6 R W 0 1 IrDA SIR Mode enabled AFCE Auto Flow Control Enable When FIFOs are enabled and the Auto Flow Control Enable AFCE bit 5 R W 0 is set Auto Flow Control features are enabled A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 192 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 0 Auto Flow Control Mode disabled 1 Auto Flow Control Mode enabled LOOP Loop Back Mode 0 Normal Mode 1 Loop Back Mode This is used to put the UART into a diagnostic mode for test purposes If operating in UART mode SIR MODE Enabled or not active MCR 6 set to zero data on the sout line is held high while serial data output is looped back to the sin line internally In this mode all the interrupts are fully functional Also i
71. 3 14 ASYNC Timer 4 Control Register Default 0x00000004 Offset 0x50 Register Name ASYNC_TMR4_CTRL_REG Bit Read Wr ite Default Hex Description 31 8 R W 0x0 TMR4_MODE Timer4 mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically 6 4 R W 0x0 TMR4_CLK_PRESCALE Select the pre scale of timer 4 clock source 000 1 001 2 010 4 O11 8 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMR4 CLK SRC Timer 4 Clock Source 00 01 OSC24M 10 External CLKINO 11 R W 0x0 TMR4_RELOAD Timer 4 Reload 0 No effect 1 Reload timer 0 Interval value After the bit is set it can not be written again before it s cleared automatically R W 0x0 TMR4_EN Timer 4 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 96 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 0 the current value counter will pause At least wait for 2 Tcylces the start
72. 4 The pointer is advanced to the next ED after serving the present one HC will continue processing the list from where it left off in the last Frame When it reaches the end of the Control list HC checks the ControlListFilled of in HcCommandStatus If set it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit If not set it does nothing HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared When set HCD only reads the instantaneous value of this register Initially this is set to zero to indicate the end of the Control list 3 0 R R 0x0 CCED 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED bit 0 to bit 3 must be zero in this field 22 6 11 HcBulkHeadED Register Offset 0x428 Register Name HcBulkHeadED BHED Default Value 0x0 Read Write Bit HCD HC Default Description BHED 31 4 The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list HC traverses the Bulk list starting with the HcBulkHeadED pointer The content is loaded from HCCA 31 4 R W R 0x0 during the initialization of HC BHED 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the 3 0 R R 0x0
73. 422 0001 planar YUV 420 0100 planar YUV 422 UV combined 0101 planar YUV 420 UV combined 1000 MB YUV 422 1001 MB YUV 420 un fr CECR FIELD SEL Field selection Applies to CCIR656 interface only 00 start capturing with field odd 11 10 R W 01 start capturing with field even 10 start capturing with either field 11 reserved DATA_SEQ Input data sequence only valid for YUV422 mode 00 YUYV 09 08 R W 2 01 YVYU 10 UYVY 11 VYUY VSYNC_POL Vref polarity 02 R W 0 negative 1 positive This register is not applied to CCIR656 interface or few fo Jee A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 278 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Href polarity 0 negative 1 positive This register is not applied to CCIR656 interface PCLK_POL Data clock type 0 active in falling edge 1 active in rising edge 26 4 3 CSI Capture Control Register Register Name CSI CPT CTRL REG Offset Address 0X0008 Default Value 0X00000000 Read Wri Default arr JE Teens te Hex VIDEO CAP CTRL Video capture control Capture the video image data stream 0 Disable video capture If video capture is in progress the CSI stops capturing image data at the end of the current frame and all of the current frame data is written to output FIFO 1 Enable video capture The CSI starts capturing image data at the start of the next frame STILL CAP C
74. 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Default Value 0x0000 0002 Bit Read Write Default Description 31 13 12 R W DRS Divide Rate Select Master Mode Only 0 Select Clock Divide Rate I 1 Select Clock Divide Rate 2 11 8 R W CDRI Clock Divide Rate 1 Master Mode Only This field selects the baud rate of the SPI_SCLK based on a division of the AHB_CLK These bits allow SPI to synchronize with different external SPI devices The max frequency is one quarter of AHB_CLK The divide ratio is determined according to the following table using the equation 24 n 1 The SPI SCLK is determined according to the following equation SPI_CLK AHB_CLK 24 n 1 7 0 R W 0x2 CDR2 Clock Divide Rate 2 Master Mode Only The SPI_SCLK is determined according to the following equation SPI_CLK AHB_CLK 2 n 1 18 4 9 SPI Burst Counter Register Offset 0x20 Register Name SPI_BC Default Value 0x0000 0000 Bit Read Write Default Description 31 24 23 0 R W BC Burst Counter In master mode this field specifies the total burst number when SMC is 1 0 0 burst 1 I burst N N bursts 18 4 10 SPI Transmit Counter Register Register Name SPI TC Offset 0x24 Default Value 0x0000 0000 Bit Read Write Default Description 31 24
75. 8 bit width RX FIFO the MSB bit is used to record the polarity of the receiving CIR signal The high level is represented as 1 and the low level is represented as 0 and the rest 7 bits are used for the length of RLC The maximum length is 128 If the duration of one level high or low is more than 128 another byte is used Since there are always some noises in the air a threshold can be set to filter the noises to reduce system loading and improve system stability 20 2 CIR Register List Module Name Base Address CIR 0x01C21800 Register Name Offset Description CIR_CTL 0x00 CIR Control Register CIR_RXCTL 0x10 CIR Receiver Configure Register CIR_RXFIFO 0x20 CIR Receiver FIFO Register CIR_RXINT 0x2C CIR Receiver Interrupt Control Register CIR_RXSTA 0x30 CIR Receiver Status Register CIR_CONFIG 0x34 CIR Configure Register 20 3 CIR Regsiter Description 20 3 1 CIR Control Register Register Name CIR_CTL Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 9 CGPO General Program Output GPO Control in CIR mode for TX Pin 8 R W 0 0 Low level A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 201 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 High level 7 6 5 4 R W CIR ENABLE 00 10 11 CIR mode enable 3 2 R W RXEN Receiver Bloc
76. A Not possible because the median filter size is always larger than the averaging window size Table25 3 Median Averaging Filters MAVF Example In this example MED1 MEDO 11 and AVG1 AVGO 10 the median filter has a window size of 16 This means that 16 measurements are taken and arranged in descending order in a temporary array The averaging window size in this example is 8 The output is the average of the middle eight values of the 16 measurements taken with the median filter A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 267 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 12 BIT MEDIAN AVERAGING FIFO SAR ADC FILTER FILTER 16 Measurements Average Of Middle Converted Results Arranged 8 Values 2 1 1 3 2 2 5 3 3 1 4 4 6 5 5 A 7 6 6 9 7 7 8 8 8 16 A 0 9 9 2 10 10 1 1 1 5 12 12 y 3 13 13 4 14 14 6 15 15 4 16 y 16 Figure 25 14 Median and Averaging Filter Example 25 5 TP Register List Module Name Base Address TP 0x01C25000 Register Name Offset Description TP_CTRLO 0x00 TP Control Register0 TP_CTRL1 0x04 TP Control Register1 TP Pressure Measurement and touch sensitive Control TP_CTRL2 0x08 Register TP_CTRL3 0x0
77. A13 5 3 41 CPU Idle Counter Low Register Default 0x00000000 Offset OXFO Register Name CPU_IDLE_CNT_LOW_REG Read Wr Default Bit Description ite Hex CPU_IDLE_CNT_LO CPU Idle Counter 31 0 This counter clock source is 24MHz If CPU is in idle state the counter will 31 0 R W 0x0 count up in the clock of 24MHz Any write to this register will clear this register and the CPU idle counter high register 5 3 42 CPU Idle Counter High Register Default 0x00000000 Offset OxF4 Register Name CPU_IDLE_CNT_HIGH_REG Read Wr Default aan Bit Description ite Hex CPU_IDLE_CNT_HI CPU Idle Counter 63 32 31 0 R W 0x0 Any write to this register will clear this register and the CPU idle counter low register 5 3 43 CPU Idle Control Register Default 0x00000000 Offset OxF8 Register Name CPU_IDLE_COUNTER_CTRL_REG Read Wr Default Bit Description ite Hex 31 8 CPU IDLE AUTO SWTH EN CPU idle enter exit clk auto switch enable 0 disable 1 enable 7 R W 0x0 If the CPU enter the idle mode and this bit is set the ccu will auto switch the CPU clock divide ratio to 8 If the CPU exit the idle mode and this bit is set the ccu will auto switch the CPU clock divide ratio from 8 to 1 with 4 steps 6 3 CPU_IDLE_CNT_EN CPU idle counter enable 2 R W 0x0 0 disable 1 enable CPU
78. CO Ltd A13 0 16 bits 1 24 bits 5 ADC_DRQ_EN ADC FIFO Data Available DRQ Enable 0 Disable 1 Enable 4 R W 0x0 ADC_IRQ_EN ADC FIFO Data Available IRQ Enable 0 Disable 1 Enable 3 R W 0x0 2 ADC OVERRUN IRQ EN ADC FIFO Over Run IRQ Enable 0 Disable 1 Enable 1 R W 0x0 ADC_FIFO_FLUSH 0 R W 0x0 ADC FIFO Flush Write 1 to flush TX FIFO self clear to 0 23 4 7 ADC FIFO Status Register Offset 0x20 Register Name AC_ADC_FIFOS Bit Read Write Default Description 31 24 RXA 23 R x0 RX FIFO Available 0 No available data in RX FIFO 1 More than one sample in RX FIFO gt 1 word 22 14 RXA_CNT 13 8 R 0x0 RX FIFO Available Sample Word Counter 7 4 RXA INT RX FIFO Data Available Pending Interrupt 0 No Pending IRQ 3 R W 0x0 1 Data Available Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 2 RXO_INT 1 R W 0x0 RX FIFO Overrun Pending Interrupt 0 No Pending IRQ A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 249 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 FIFO Overrun Pending IRQ Write 1 to clear this interrupt 0 23 4 8 ADC RX DATA Register Register Name AC_ADC_RXDATA Offset 0x24 Default Val
79. Configure Register 2 n from 0 to 6 Pn_CFG3 n 0x24 0x0C Port n Configure Register 3 n from 0 to 6 Pn_DAT n 0x24 0x10 Port n Data Register n from 0 to 6 Pn_DRVO n 0x24 0x14 Port n Multi Driving Register 0 n from 0 to 6 Pn_DRV1 n 0x24 0x18 Port n Multi Driving Register 1 n from 0 to 6 Pn_PULO n 0x24 0x1C Port n Pull Register 0 n from 0 to 6 Pn PULI n 0x24 0x20 Port n Pull Register 1 n from 0 to 6 PIO INT CFGO 0x200 PIO Interrrupt Configure Register 0 PIO INT CFGI1 0x204 PIO Interrrupt Configure Register 1 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 383 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 PIO INT CFG2 0x208 PIO Interrrupt Configure Register 2 PIO INT CFG3 0x20C PIO Interrrupt Configure Register 3 PIO INT CTL 0x210 PIO Interrupt Control Register PIO INT STA 0x214 PIO Interrupt Status Register PIO INT DEB 0x218 PIO Interrupt Debounce Register 33 4 Port Register Description 33 4 1 PB Configure Register 0 Register Name PB CFGO Offset 0x24 Default Value 0x0000 0000 Bit Read Write Default Description 31 30 28 R W 0 27 26 24 R W 0 23 22 20 R W 0 19 PB4 Select 000 Input 001 Output 010 IR RX 011 100 101 18 16 R W 0 110 EINT18 111 15 PB3 Select 000 Input 001 Output 010 IR_TX 011 100 101 14 12 R W 0 110 EINT17 111 11
80. Control SYNC TMRO INTV LO REG 0x0014 Timer 0 Interval Value Low SYNC TMRO INTV HI REG 0x0018 Timer 0 Interval Value High SYNC TMRO CURNT LO REG 0x001C Timer O Current Value Low SYNC TMRO CURNT HI REG 0x0020 Timer 0 Current Value High SYNC TMRI1 CTRL REG 0x0030 Timer 1 Control SYNC TMRI1 INTV LO REG 0x0034 Timer 1 Interval Value Low SYNC TMRI1 INTV HI REG 0x0038 Timer 1 Interval Value High SYNC TMRI1 CURNT LO REG 0x003C Timer 1 Current Value Low SYNC_TMRI_CURNT HI REG 0x0040 Timer 1 Current Value High 12 3 Sync Timer Register Description 12 3 1 Sync Timer IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name SYNC TMR IRQ EN REG Read Wr Default 2 Bit Description ite Hex 31 2 STMR1_INT_EN Sync Timer 1 Interrupt Enable 1 R W 0x0 0 No effect 1 Timer 1 Interval Value reached interrupt enable STMRO_INT_EN Sync Timer 0 Interrupt Enable 0 R W 0x0 0 No effect 1 Timer 0 Interval Value reached interrupt enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 104 Ou 7 Allwinner Technology CO Ltd A13 12 3 2 Sync Timer IRQ Status Register Default 0x00000000 Offset 0x04 Register Name SYNC TMR IRQ STAS REG Bit Read Wr ite Default Hex Description 31 2 R W 0x0 STMR1_IRQ_PEND Sync Timer 1 IRQ Pending Set 1 to the bit will clear
81. DEBE_OCBCOEF_REG Ox9F0 0x9F8 DEBE output color B coefficient register DEBE_OCBCONS_REG Ox9FC DEBE output color B constant register Memories 0x4400 0x47FF Gamma table 0x4800 0x4BFF DE HWC pattern memory block 0x4C00 0x4FFF DE HWC color palette table 0x5000 0x53FF PipeO palette table 0x5400 0x57FF Pipel palette table 28 5 DEBE Register Description 28 5 1 DEBE Mode Control Register Offset 0x800 Register Name DEBE MODCTL REG Read Wri Default Se Bit Description te Hex LINE_SEL Start top bottom line selection in interlace mode ITLMOD_EN Interlace mode enable LAY3_EN Layer3 Enable Disable 0 Disabled 1 Enabled LAY2_EN Layer2 Enable Disable 0 Disabled A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 320 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 Enabled LAY1 EN Layerl Enable Disable 0 Disabled 1 Enabled LAYO0 EN Layer0 Enable Disable 0 Disabled 1 Enabled Normal output channel Start amp Reset control 0 reset DEBE EN DEBE enable disable 0 disable 28 5 2 DE Back Color Control Register Offset 0x804 Register Name DEBE BACKCOLOR REG Read Wri Default SE Bit Description te Hex map BK_RED R W UDF Red Red screen background color value BK_GREEN F Green Green screen background color value BK_BLUE UDF Blue Blue screen background color value 28 5 3 DE Back Display Size S
82. DRAM direct or DEFE by setting dedicated Layer video channel selection bit in DE layer Attribute control register In other work modes the layer data source also comes from internal frame buffer In the same pipe the highest layer pixel data can pass A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 318 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 28 4 DEBE Register list Module name Base address DEBE 0x01e60000 Register name Offset Description DEBE_MODCTL_REG 0x800 DEBE mode control register DEBE BACKCOLOR REG 0x804 DE back color control register DEBE DISSIZE REG 0x808 DE back display size setting register DEBE LAYSIZE REG 0x810 0x81C DE layer size register DEBE LAYCOOR REG 0x820 0x82C DE layer coordinate control register DEBE LAYLINEWIDTH REG 0x840 0x84C DE layer frame buffer line width register DEBE LAYFB L32ADD REG 0x850 0x85C DE layer frame buffer low 32 bit address register DE layer frame buffer high 4 bit address DEBE LAYFB H4ADD REG 0x860 register DEBE_REGBUFFCTL_REG 0x870 DE Register buffer control register DEBE CKMAX REG 0x880 DE color key MAX register DEBE CKMIN REG 0x884 DE color key MIN register DEBE CKCFG REG 0x888 DE color key configuration register DEBE ATTCTL REGO 0x890 0x89C DE layer attribute control register0 DEBE ATTCTL REGI Ox8A0 Ox8AC DE lay
83. Description 26 4 1 CSI Enable Register Name CSI EN REG Default Value 0X00000000 Offset 0X0000 Read Default He Bit Description Write x 31 01 Reserved EN CSI Enable 00 R W 0 0 Reset and disable 1 Enable 26 4 2 CSI Configuration Register Register Name CSI CFG REG Offset Address 0X0004 Default Value 0X00000000 Description Reserved IN FMT Input data format 000 RAW stream 010 CCIR656 O11 YUV422 others reserved OUT FMT Output data format When the input format is set RAW stream 0000 pass through When the input format is set CCIR656 interface 0000 field planar YCbCr 422 0001 field planar YCbCr 420 0010 frame planar YCbCr 420 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 277 Jau 8 2013 OM winner Technology CO Ltd A13 0011 frame planar YCbCr 422 0100 field planar YCbCr 422 UV combined 0101 field planar YCbCr 420 UV combined 0110 frame planar YCbCr 420 UV combined 0111 frame planar YCbCr 422 UV combined 1111 interlaced interleaved YCbCr422 In this mode capturing interlaced input and output the interlaced fields from individual ports Field 1 data will be written to FIFOO output buffer and field 2 data will be written to FIFO1 output buffer 1000 field MB YCbCr 422 1001 field MB YCbCr 420 1010 frame MB YCbCr 420 1011 frame MB YCbCr 422 When the input format is set YUV422 0000 planar YUV
84. Description Receive Data In 8 bits SPI bus width this register can be accessed in byte half word or word unit by AHB In byte accessing method if there are words in RXFIFO the top word is returned and the RXFIFO depth is decreased by 1 In half word accessing method the two SPI bursts are returned and the RXFIFO depth decreases by 2 In word accessing method the four SPI 31 0 R 0 bursts are returned and the RXFIFO depth decreases by 4 18 4 2 SPI TX Data Register Register Name SPI TXDATA Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 W 0 Transmit Data 18 4 3 SPI Control Register Register Name SPI CTL Offset 0x08 Default Value 0x0002 001C Bit Read Write Default Description 31 20 Master Sample Data Control Set this bit to 1 to make the internal read sample point with a delay of half cycle of SPI_CLK It is used in high speed read operation to reduce 19 R W 0 the error caused by the time delay of SPI_CLK propagating between master and slave 1 delay internal read sample point 0 normal operation do not delay internal read sample point Transmit Pause Enable 18 R W 0 In master mode it is used to control transmit state machine to stop smart burst sending when RX FIFO is full 1 stop transmit data when RXFIFO full A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 173 Jau 8 20
85. Driving Register 1 Register Name PB DRV1 Offset 0x3C Default Value 0x0000 0155 Bit Read Write Default Description 31 10 PB n Multi Driving Select n 16 20 21 1 21 00 Level 0 01 Level 1 1 0 4 R W Ox1 10 Level 2 11 Level 3 33 4 8 PB Pull Register 0 Register Name PB PULLO Offset 0x40 Default Value 0x0000 0000 Bit Read Write Default Description PB n Pull up down Select n 0 15 21 1 2i 00 Pull up down disable 01 Pull up 1 0 15 R W 0x0 10 Pull down 11 Reserved 33 4 9 PB Pull Register 1 Register Name PB_PULL1 Offset 0x44 Default Value 0x0000 0000 Bit Read Write Default Description 31 10 PB n Pull up down Select n 16 20 21 1 2i 00 Pull up down disable 01 Pull up enable 1 0 4 R W 0x0 10 Pull down 11 Reserved 33 4 10 PC Configure Register 0 Register Name PC_CFGO Offset 0x48 Default Value 0x0000 0000 Bit Read Write Default Description 31 PC7 Select 30 28 R W 0 000 Input 001 Output A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 387 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 010 NRB1 011 SDC2_CLK 100 101 110 111 27 PC6 Select 000 Input 001 Output 010 NRBO 011 SDC2_CMD 100 101 26 24 R W 0 110
86. ERBFI Enable Received Data Available Interrupt This is used to enable disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt if in FIFO mode and FIFOs enabled These are the second highest priority interrupts 0 Disable 0 R W 0 1 Enable 19 4 6 UART Interrupt Identity Register Register Name UART_IIR Offset 0x08 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 FEFLAG FIFOs Enable Flag This is used to indicate whether the FIFOs are enabled or disabled 00 Disable 7 6 R 0 11 Enable 5 4 IID Interrupt ID 3 0 R Ox1 This indicates the highest priority pending interrupt which can be one of A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 188 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 the following types 0000 modem status 0001 no interrupt pending 0010 THR empty 0100 received data available 0110 receiver line status 0111 busy detect 1100 character timeout Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt Interrupt Priority Interrupt Type Interrupt Source Interrupt Reset ID Level 0001 None None Receiver Line Overrun parity framing errors Reading the line status 0110 Highest i Status or break interrupt re
87. Fill Data Control Register TCONI1 FILL BEGINO REG 0x0304 TCONI Fill Data Begin Register0 TCONI FILL ENDO REG 0x0308 TCONI Fill Data End RegisterO A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 349 Ou 7 Allwinner Technology CO Ltd A13 TCONI1 FILL DATAO REG 0x030C TCONI Fill Data Value RegisterO TCONI FILL BEGIN REG 0x0310 TCONI Fill Data Begin Register1 TCONI FILL END1 REG 0x0314 TCONI Fill Data End Register 1 TCONI FILL_DATA1 REG 0x0318 TCONI Fill Data Value Register 1 TCONI FILL BEGIN2 REG 0x031C TCONI Fill Data Begin Register2 TCONI1 FILL END REG 0x0320 TCONI Fill Data End Register2 TCONI1 FILL DATA REG 0x0324 TCONI Fill Data Value Register2 TCONI GAMMA TABLE REG 0x400 0x7FF TCONI Gama Table Register 29 3 LCD TV Timing Controller Register Description 29 3 1 TCON GCTL REG Offset 0x000 Register Name TCON global control register Read Wr Default o Bit Description ite Hex TCON_En 0 disable 31 R W 0 1 enable When it s disabled the module will be reset to idle state TCON_Gamma_En 30 R W 0 0 disable 1 enable 29 1 IO Map Sel 0 TCONO 0 R W 0 1 TCON1 Note This bit determines which IO_INV IO_TRI is valid 29 3 2 TCON GINTO REG Offset 0x004 Register Name TCON global interrupt register0 Bit anes TN Description ite Hex TCONO_Vb_Int_
88. Frame List Rollover bit in the USBSTS register is 1 the host controller will issue an interrupt The interrupt is 3 R W 0 acknowledged by software clearing the Frame List Rollover bit Port Change Interrupt Enable When this bit is 1 and the Port Chang Detect bit in the USBSTS register is 1 the host controller will issue an interrupt The interrupt is 2 R W 0 acknowledged by software clearing the Port Chang Detect bit USB Error Interrupt Enable When this bit is 1 and the USBERRINT bit in the USBSTS register is 1 the host controller will issue an interrupt at the next interrupt threshold 1 R W 0 The interrupt is acknowledged by software clearing the USBERRINT bit USB Interrupt Enable When this bit is 1 and the USBINT bit in the USBSTS register is 1 the host controller will issue an interrupt at the next interrupt threshold 0 R W 0 The interrupt is acknowledged by software clearing the USBINT bit 22 5 9 EHCI Frame Index Register Register Name FRINDEX Offset Ox1c Default Value 0x00000000 Bit Read Write Default Description Reserved 31 14 0 These bits are reserved and should be zero Frame Index 13 0 R W 0 The value in this register increment at the end of each time frame A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 217 Jau 8 2013 7 Allwinner Technology CO Ltd A13 e g micro frame Bits N 3 are used for the Frame List current index It Me
89. Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 15 0 R R W 0x0 FrameNumber This is incremented when HcFmRemaining is re loaded It will be rolled over to 0x0 after OxOffff When entering the USBOPERATIONAL state this will be incremented automatically The content will be written to HCCA after HC has incremented the FrameNumber at each frame boundary and sent a SOF but before HC reads the first ED in that Frame After writing to HCCA HC will set the StartofFrame in HclnterruptStatus 22 6 17 HcPeriodicStart Register Offset 0x440 Register Name HcPeriodicStatus Default Value 0x0 Read Write Bit HCD HC Default Description 31 14 Reserved 13 0 R W R 0x0 PeriodicStart After hardware reset this field is cleared This is then set by HCD during the HC initialization The value is calculated roughly as 10 off from HcFmInterval A typical value will be 0x2A3F When HcFmRemaining reaches the value specified processing of the periodic lists will have priority over Control Bulk processing HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress 22 6 18 HcLSThreshold Register Offset 0x444 Register Name HcLSThreshold Default Value 0x0628 Read Write Bit HCD HC Default Description 31 12 Reserved LSThreshold This field conta
90. PCED bit 0 to bit 3 must be zero in this field A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 231 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 22 6 12 HcBulkCurrent ED Register Offset 0x42c Register Name HcBulkCurrentED BCED Default Value 0x00 Bit Read Write HCD HC Default Description R W R W 0x0 BulkCurrentED 31 4 This is advanced to the next ED after the HC has served the present one HC continues processing the list from where it left off in the last Frame When it reaches the end of the Bulk list HC checks the ControlListFilled of HcControl If set it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit If it is not set it does nothing HCD is only allowed to modify this register when the BulkListEnable of HcControl is cleared When set the HCD only reads the instantaneous value of this register This is initially set to zero to indicate the end of the Bulk list 3 0 R R 0x0 BulkCurrentED 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED through bit 0 to bit 3 must be zero in this field 22 6 13 HcDoneHead Register Offset 0x430 Register Name HcDoneHead Default Value 0x00 Bit Read Write HCD HC Default Description R W 0x0 Hc
91. Read Write Default Description 31 0 R W 0 Initialization Vector IV n Input Value n 0 3 31 4 4 Security System Counter n Register Offset 0x34 4 n Register Name SS_CNT n Default Value 0x0000 0000 Bit Read Write Default Description 31 0 R W 0 Counter mode preload Counter Input Value n 0 3 31 4 5 Security System FIFO Control Status Register Register Name SS_FCSR Offset 0x44 Default Value 0x6000_OFOF Bit Read Write Default Description 31 RX FIFO Empty 0 No room for new word in RX FIFO 30 R Ox 1 More than one room for new word in RX FIFO gt 1 word 29 24 R 0x20 RX FIFO Empty Space Word Counter 23 TX FIFO Data Available Flag 0 No available data in TX FIFO 22 R 0 1 More than one data in TX FIFO gt 1 word 21 16 R 0 TX FIFO Available Word Counter 15 13 RX FIFO Empty Trigger Level Interrupt and DMA request trigger level for RXFIFO normal condition Trigger Level RXTL 1 12 8 R W OxF Notes RX FIFO is used for input the data T5 4 0 R W OxF TX FIFO Trigger Level A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 376 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Interrupt and DMA request trigger level for TXFIFO normal condition Trigger Level TXTL I Notes TX FIFO is used to output the result data
92. Resume 1 Resume detected driven on port 0 No resume K state detected driven on port Default value 0 This functionality defined for manipulating this bit depends on the value of the Suspend bit For example if the port is not suspend and software transitions this bit to a one then the effects on the bus are undefined Software sets this bit to a 1 drive resume signaling The Host Controller sets this bit to a 1 if a J to K transition is detected while the port is in the Suspend state When this bit transitions to a one because a J to K transition is detected the Port Change Detect bit in the USBSTS register is also set to a one If software sets this bit to a one the host controller must not set the Port Change Detect bit Note that when the EHCI controller owns the port the resume sequence follows the defined sequence documented in the USB Specification Revision 2 0 The resume signaling Full speed K is driven on the port as long as this remains a one Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed Writing a zero from one causes the port to return high speed mode forcing the bus below the port into a high speed idle This bit will remain a one until the port has switched to high speed idle The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero 6 R W This field is zero
93. Rights Reserved 338 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 G B component coefficient B G constant B B R component coefficient R B G component coefficient G B B component coefficient B B constant 28 5 31 DEBE Output Color R Coefficient Register Offset R component 0x9D0 Register Name DEBE OCRCOEF REG G component 0x9D4 B component 0x9D8 Read Wri Default SC Bit Description te Hex OC_RCOEF the R coefficient the value equals to coefficient 2 28 5 32 DEBE Output Color R Constant Register Offset 0x9DC Register Name DEBE_OCRCONS_REG Read Wri Default i Bit Description te Hex OC_RCONS the R constant the value equals to coefficient 2 28 5 33 DEBE Output Color G Coefficient Register Offset R component 0x9E0 Register Name DEBE_OCGCOEF_REG G component 0x9E4 B component 0x9E8 Read Wri Default Bit Description te Hex OC_GCOEF the G coefficient the value equals to coefficient 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 339 Jau 8 2013 Ou Allwinner Technology CO Ltd 28 5 34 Offset Ox9EC Read Wri A13 DEBE Output Color G Constant Register Register Name DEBE OCGCONS REG Default Hex OC_GCONS the G constant the value equals to coefficient 2 28 5 35 Offset G Y component 0x9FO R U component 0x9F4 Register Name D
94. SLAX 7 0 17 43 TWI Data Register Register Name 2 WIRE DATA Offset 0x08 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 7 0 R W 0 Data byte for transmitting or receiving 17 44 TWI Control Register Register Name TWI_CNTR Offset OxOC Default Value 0x0000 0000 Bit Read Write Default Description 31 8 INT_EN Interrupt Enable 1 b0 The interrupt line always low 7 R W 0 1 b1 The interrupt line will go high when INT FLAG is set 6 R W 0 BUS_EN A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 164 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 two wire bus Enable 1 b0 The two wire bus inputs ISDA ISCL are ignored and the 2 Wire Controller will not respond to any address on the bus 1 b1 The TWI will respond to calls to its slave address and to the general call address if the GCE bit in the ADDR register is set Notes In master operation mode this bit should be set to 1 R W M_STA Master Mode Start When M_STA is set to 1 TWI controller enters master mode and will transmit a START condition on the bus when the bus is free If the M STA bit is set to 1 when the 2 Wire Controller is already in master mode and one or more bytes have been transmitted then a repeated START condition will be sent If the M STA bit is set to 1 when
95. SPI Chip Select Signal A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 182 GW Allwinner Technology CO Ltd A13 18 5 2 SPI Module Clock Source and Frequency The SPI module uses two clock sources AHB CLK and SPI CLK The SPI SCLK can in the range from 3KHz to 100MHz and AHB_CLK gt 2x SPI SCLK Clock Name Description Requirement AHB Bus Clock as the clock source of SPI AHB CLK AHB CLK gt 2xSPI SCLK module SPI CLK SPI Serial Input Clock A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 183 Ou Allwinner Technology CO Ltd A13 19 Universal Asynchronous Receiver Transmitter Interface 19 1 Overview The Universal Asynchronous Receiver Transmitter Interface UART is used for serial communication with a peripheral modem data carrier equipment DCE or data set Data is written from a master CPU over the APB bus to the UART and it is converted to serial form and transmitted to the destination device Serial data is also received by the UART and stored for the master CPU to read back The UART contains registers to control the character length baud rate parity generation checking and interrupt generation Although there is only one interrupt output signal from the UART there are several prioritized interrupt types responsible for its assertion Eac
96. TCONO IO TRI REG 0x008C TCONO IO Control Register TCONI1 CTL REG 0x0090 TCONI Control Register TCONI1 BASICO REG 0x0094 TCONI Basic Timing RegisterO TCONI1 BASIC1 REG 0x0098 TCONI Basic Timing Register 1 TCONI1 BASIC2 REG 0x009C TCONI Basic Timing Register2 TCONI1 BASIC3 REG 0x00A0 TCONI Basic Timing Register3 TCON1_BASIC4 REG 0x00A4 TCONI Basic Timing Register4 TCONI1 BASICS REG 0x00A8 TCONI Basic Timing Register5 TCONI1 IO POL REG Ox00F0 TCONI IO Polarity Register TCON1_IO_TRI_ REG 0x00F4 TCONI IO Control Register TCON_CEU_CTL_REG 0x0100 TCON CEU Control Register TCON CEU COEFO REG 0x0110 TCON CEU Coefficient RegisterO TCON_CEU_COEF1_REG 0x0114 TCON CEU Coefficient Register TCON CEU COEF2 REG 0x0118 TCON CEU Coefficient Register2 TCON_CEU_COEF3_REG 0x011C TCON CEU Coefficient Register3 TCON_CEU_COEF4_REG 0x0120 TCON CEU Coefficient Register4 TCON CEU COEF5 REG 0x0124 TCON CEU Coefficient Register5 TCON_CEU_COEF6_REG 0x0128 TCON CEU Coefficient Register6 TCON_CEU_COEF7_REG 0x012C TCON CEU Coefficient Register7 TCON_CEU_COEF8_REG 0x0130 TCON CEU Coefficient Register8 TCON_CEU_COEF9_REG 0x0134 TCON CEU Coefficient Register9 TCON_CEU_COEF10_REG 0x0138 TCON CEU Coefficient Register10 TCON_CEU_COEF11_REG 0x013C TCON CEU Coefficient Register11 TCON_CEU_COEF12_ REG 0x0140 TCON CEU Coefficient Register12 TCON_CEU_COEF13_REG 0x0144 TCON CEU Coefficient Register13 TCON_CEU_COEF14_REG 0x0148 TCON CEU Coefficient Register14 TCON1_ FILL CTL REG 0x0300 TCONI
97. This bit indicates the registers for the next frame has been configured This bit will be set when configuration ready bit is set and this bit will be cleared when a new frame process begins WB_STATUS Write back process status 0 write back end or write back disable 1 R 0x0 1 write back in process This flag indicates that a full frame has not been written back to memory The bit will be set when write back enable bit is set and be cleared when write back process ends FRM_BUSY Frame busy 0 R 0x0 This flag indicates that the frame is being processed The bit will be set when frame process reset amp start is set and be cleared when frame process is reset or disabled 27 5 22 DEFE_CSC_COEF00_REG Offset 0x70 Register Name DEFE_CSC_COEF00_REG Bit Mr ER Description ite Hex 31 13 COEF 12 0 R W 0x0 the Y G coefficient the value equals to coefficient 2 27 5 23 DEFE_CSC_COEF01_REG Offset 0x74 Register Name DEFE_CSC_COEF01_REG Bit es PER Description ite Hex 31 13 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 305 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd COEF the Y G coefficient the value equals to coefficient 2 12 0 A13 27 5 24 DEFE CSC COEFO2 REG Offset 0x78 Register Name DEPE CSC COEFO02 REG Read Wr Default aan Bit Description ite Hex 31 13 COEF 12 0 R W 0x0 the Y G coefficient the valu
98. Undefined Bit Read Write Default Description Link Pointer LP This field contains the address of the next asynchronous queue head to be executed 315 R W These bits correspond to memory address signals 31 5 respectively Reserved 4 0 These bits are reserved and their value has no effect on operation A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 218 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Bits in this field cannot be modified by system software and will always return a zero when read Note Write must be DWord Writes 22 5 12 EHCI Configure Flag Register Register Name CONFIGFLAG Offset 0x50 Default Value 0x00000000 Bit Read Write Default Description Reserved 31 1 0 These bits are reserved and should be set to zero Configure Flag CF Host software sets this bit as the last action in its process of configuring the Host Controller This bit controls the default port routing control logic as follow Value Meaning 0 Port routing control logic default routs each port to an implementation dependent classic host controller 1 Port routing control logic default routs all ports to this host controller 0 R W 0 The default value of this field is 0 Note This register is not use in the normal implementation 22 5 13 EHCI Port Status and Control Register Register Nam
99. User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 41 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 ite Hex 31 11 CPU_MAX_FREQ_ 105 10 0 R W D CPU max frequency if cpuvdd 1 05v unit MHz This register can only be written if the DVFS function is disabled 5 3 24 PMU VF Table Register 8 Offset OxAO Register Name PMU_VF_TABLE_REG8 Read Wr Default Bit Description ite Hex 31 11 CPU_MAX_FREQ_ 110 10 0 R W D CPU max frequency if cpuvdd 1 1v unit MHz This register can only be written if the DVFS function is disabled 5 3 25 PMU VF Table Register 9 Offset OxA4 Register Name PMU_VF_TABLE_REG9 Read Wr Default a Bit i Description ite Hex 31 11 CPU MAX FREQ 115 10 0 R W D CPU max frequency if cpuvdd 1 15v unit MHz This register can only be written if the DVFS function is disabled 5 3 26 PMU VF Table Register 10 Offset OxA8 Register Name PMU VF TABLE REG10 8 Read Wr Default SR Bit Description ite Hex 31 11 CPU MAX FREQ 120 10 0 R W D CPU max frequency if cpuvdd 1 2v unit MHz This register can only be written if the DVFS function is disabled 5 3 27 PMU VF Table Register 11 Offset OxAC Register Name PMU VF TABLE REGI 1 Read Wr Default Bit Description ite Hex
100. Vertical Size Setting A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 284 Allwinner Technology CO Ltd A13 je n clocks m clocks hsyne _ i if i L active data f __ CALC active in rising pet AAA RER AAA AAA A AAA horizontal start clock n horizontal active clocks length m Horizontal Size Setting and Pixel Clock Timing Href positive A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 285 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 21 Display Engine Front End DEFE 27 1 Overview The Display Engine Front End DEFE performs image capture driver video graphic scale format conversion and color space conversion It is composed of DMA controller input controller scaler color space conversion and output controller as show in figure 27 1 The DEFE features Output scan type interlace progressive Input format YUV444 YUV422 YUV420 YUV411 RGB Direct display output format RGB Write back output format RGB YUV444 YUV420 YUV422 YUV411 3 channel scaling pipelines for scaling up down Programmable source image size from 8x4 to 8192x8192 resolution Programmable destination image size from 8x4 to 8192x8192 resolution 4 tap scale filter in horizontal and vertical direction 32 Programmable coefficients for each tap Color space conversion between YUV and RGB
101. W 0 15 14 12 R W 0 11 PB 18 Select 000 Input 001 Output 010 TWI2_SDA 011 100 101 10 8 R W 0 110 111 7 PB17 Select 000 Input 001 Output 010 TWI2_SCK 011 100 101 6 4 R W 0 110 111 PB 16 Select 000 Input 001 Output 010 TWIL SDA Ol 1 100 101 2 0 R W 0 110 111 33 4 4 PB Configure Register 3 Register Name PB_CFG3 Offset 0x30 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 5 PB Data Register Register Name PB_DAT Offset 0x34 Default Value 0x0000 0000 Bit Read Write Default Description 31 24 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If 23 0 R W 0 the port is configured as functional pin the undefined value will be read A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 386 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 33 4 6 PB Multi Driving Register 0 Register Name PB DRVO Offset 0x38 Default Value 0x5555 5555 Bit Read Write Default Description PB n Multi Driving Select n 0 15 2i 1 2i 00 Level 0 01 Level 1 1 0 15 R W Ox1 10 Level 2 11 Level 3 33 4 7 PB Multi
102. WTC 23 0 R W 0 Write Transmit Counter In master mode this field specifies the burst number that should be sent A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 181 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 to TXFIFO before automatically sending dummy burst when SMC is 1 For saving bus bandwidth the dummy burst all zero bits or all one bits is sent by SPI Controller automatically 0 0 burst 1 I burst N N bursts 18 4 11 SPI FIFO Status Register Offset 0x28 Register Name SPI FIFO STA Default Value 0x0000 0000 Bit Read Write Default Description 31 25 22 16 R 0x0 TXFIFO Counter These bits indicate the number of words in TXFIFO 0 0 byte in TXFIFO 1 1 byte in TXFIFO 63 63 bytes in TXFIFO 64 64 bytes in TXFIFO 15 7 6 0 R 0x0 RXFIFO Counter These bits indicate the number of words in RXFIFO 0 0 byte in RXFIFO 1 1 byte in RXFIFO 63 63 bytes in RXFIFO 64 64 bytes in RXFIFO 18 5 SPI Special Requirement 18 5 1 SPI Pin List The direction of SPI pin is different in two work modes Master Mode and Slave Mode Port Name Width Direction M Direction S Description SPI_SCLK 1 OUT IN SPI Clock SPI MOSI 1 OUT IN SPI Master Output Slave Input Data Signal SPI MISO 1 IN OUT SPI Master Input Slave Output Data Signal SPI_CS 1 0 2 OUT IN
103. a high speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule Valid value are Ox1 to Ox3 Software must not write a zero to this bit when Park Mode Enable is a one as it will result in undefined behavior R W Light Host Controller Reset OPTIONAL This control bit is not required If implemented it allows the driver to reset the EHCI controller without affecting the state of the ports or relationship to the companion host controllers For example the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero retaining port ownership relationships A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it si safe for software to re initialize the host controller A host software read of this bit as a one indicates the Light Host R W Interrupt on Async Advance Doorbell This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule Soft Ware must write a I to this bit to ring the doorbell When the host controller has evicted all appropriate cached schedule State it sets the Interrupt on Async Advance status bit in the USBSTS if the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold The host controller set
104. aca acs inches hace beet ester ean tata nn 386 33 4 5 PB BE EE 386 33 4 6 PB Multi Driving Register 0 EE 387 33 4 7 PB Multi Driving Register 1 us scien ankaa aaa eects 387 33 4 8 LEUR Ee ET EE 387 33 4 9 PB PUll Te EC EE 387 33 4 10 PC Configure Register QE RSR 387 9411 PG Configure E EE 389 33 4 12 PC Configure Register 2 252 5 eset eee 390 33 4 13 PC Configure RENE da en en titan 390 33 444 ee E E 391 234 15 PG Mult Driving Register Dese ees 391 33 4 16 PC Male Register dE crs eee cree pects enc ee cect cee ed 391 TN PM 391 300106 PC Pull Register less te ele 391 35419 PD Configure Register Ones ee nn 392 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 20 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 33 4 20 33 4 21 33 4 22 33 4 23 33 4 24 33 4 25 33 4 26 33 4 27 33 4 28 33 4 29 33 4 30 33 4 31 33 4 32 33 4 33 33 4 34 33 4 35 33 4 36 33 4 37 33 4 38 33 4 39 33 4 40 33 4 41 33 4 42 33 4 43 33 4 44 33 4 45 33 4 46 33 4 47 33 4 48 33 4 49 33 4 50 33 4 51 33 4 52 33 4 53 33 4 54 33 4 55 33 4 56 33 4 57 33 4 58 33 4 59 33 4 60 33 4 61 PO Keiler Register WEE 393 PD Configure e 394 PD Configure Register dns NRA ANSE iioii 395 PD Data Re E E 396 PD Multi Driving Register O0 us 396 PD Multi Driving Register 1 396 PD Pull R gister Heger eee dad eed ne nantes te ieee 396 PD Pull Register lassmaan
105. adds a TD to an ED in the Control list When HC begins to process the head of the Control list it checks CLF As long as ControlListFilled is 0 HC will not start processing the Control list If CF is 1 HC will start processing the Control list and will set ControlListFilled to 0 If HC finds a TD on the list then HC will set ControlListFilled to 1 causing the Control list processing to continue If no TD is found on the Control list and if the HCD does not set ControlListFilled then ControlListFilled will still be 0 when HC completes processing the Control list and Control list processing will 1 R W R W 0x0 stop HostControllerReset This bit is by HCD to initiate a software reset of HC Regardless of the functional state of HC it moves to the USBSuspend state in which most of the operational registers are reset except those stated otherwise e g the InteruptRouting field of HcControl and no Host bus accesses are allowed This bit is cleared by HC upon the completion of the reset operation The reset operation must be completed within 10 ms This bit when set should not cause a reset to the Root Hub and no subsequent 0 R W R E 0x0 reset signaling should be asserted to its downstream ports 22 6 4 HcInterruptStatus Register Register Name HcInterruptStatus Offset 0x40c Default Value 0x00 Read Write Bit HCD HC Default Description 31 7 0x0 Reserved RootHubStatusChange 0x0 This bit
106. bit is set the state of TWI_SDA is controlled by the value of bit 1 0 disable TWI_SDA line control mode 0 R W 0 1 enable TWI_SDA line control mode 17 4 10 TWI DVFS Control Register Register Name TWI DVFSCR Offset 0x24 Default Value 0x0000 0000 Bit Read Write Default Description 31 2 CPU and DVFS BUSY set priority select 0 CPU has higher priority 2 R W 0 1 DVFS has higher priority 1 R W 0 CPU Busy set 0 R W 0 DVFS Busy set Notes This register is only implemented in TWIO 17 5 TWI Controller Special Requirement 17 5 1 TWI Pin List Port Name Width Direction Description TWLSCL 1 IN OUT TWI Clock line TWI SDA 1 IN OUT TWI Serial Data line 17 5 2 TWI Controller Operation There are four operation modes on the two wire bus which dictates the communications method Master Transmit Master Receive Slave Transmit and Slave Receive In general CPU host controls TWI by writing commands and data to its registers The TWI interrupts the CPU host for the attention each time a byte transfer is done or a START STOP condition is detected The CPU host can also poll the status register for current status if the interrupt mechanism is not disabled by the CPU host When the CPU host wants to start a bus transfer it initiates a bus START to enter the master mode by setting IM_STA bit in the 2WIRE_CNTR register to high before it must be low The TWI will a
107. bottom field 27 5 10 DEFE_TB_OFF0_REG Offset 0x30 Register Name DEFE_TB_OFFO_REG Read Wr Default _ Bit Description ite Hex 31 21 X_OFFSET1 20 16 R W 0x0 ee The x offset of the bottom right point in the end tile 15 13 Y_OFFSETO 12 8 R W 0x0 hu Er The y offset of the top left point in the first tile 7 5 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 298 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 X OFFSETO 4 0 R W 0x0 are are The x offset of the top left point in the first tile 27 5 11 DEFE TB_OFF1 REG Offset 0x34 Register Name DEFE_TB_OFF1_REG Read Wr Default Ge Bit Description ite Hex 31 21 X_OFFSET1 20 16 R W 0x0 ee The x offset of the bottom right point in the end tile 15 13 Y_OFFSETO 12 8 R W 0x0 oe ONE The y offset of the top left point in the first tile 7 5 X OFFSETO 4 0 R W 0x0 bid er The x offset of the top left point in the first tile 27 5 12 DEFE TB OFF2 REG Offset 0x38 Register Name DEFE TB OFF2 REG Read Wr Default SC Bit f Description ite Hex 31 21 X_OFFSET1 20 16 R W 0x0 Ee The x offset of the bottom right point in the end tile 15 13 Y_OFFSETO 12 8 R W 0x0 Sg EE The y offset of the top left point in the first tile 7 5
108. can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note 1 If the clock source is External CLKIN the interval value register is not used the current value register is an up counter that counting from 0 2 The time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 18 ASYNC Timer 5 Interval Value Register Offset 0x64 Register Name ASYNC TMR5 INTV VALUE REG Bit Read Wr Default Description A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 98 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 ite Hex TMR5 INTV VALUE Timer 5 Interval Value 31 0 R W D Note the value setting should consider the system clock and the timer clock source 11 3 19 ASYNC Timer 5 Current Value Register Offset 0x68 Register Name ASYNC_TMR5_CURNT_VALUE_REG Read Wr Default a Bit Description ite Hex TMRS_CUR_VALUE Timer 5 Current Value 31 0 R W x Note 1 Timer 1 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 2 Before timer 5 is enabled i
109. clear it 8 5 0x0 VOLT_DET_FIN_IRQ_PEND Voltage Detect Finished IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it 0x0 DVFS_CLK_SWT_FIN_IRQ_PEND DVFS Clock Switch Operation Finished IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it 0x0 DVFS_VOLT_CHANGE_FIN_PEND DVFS Voltage Change Finished Pending 0 No effect 1 Pending Set one to this bit will clear it 0x0 DVFS SPD DET FIN IRQ PEND DVES Speed Detect Finished IRQ Pending A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 37 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd 0 No effect 1 Pending Set one to this bit will clear it A13 DVFS FIN IRQ PEND DVFS Finished IRQ Pending 0 R W 0x0 0 No effect 1 Pending Set one to this bit will clear it 5 3 10 PMU Status Register Offset 0x48 Register Name PMU_STATUS_REG Read Wr Default aos Bit A Description ite Hex 31 1 DVFS_BUSY DVFS Busy 0 R W 0x0 0 no effect 1 DVFS is busy 5 3 11 PMU CPUVDD DCDC Control Register Address Default 0x00000023 Offset 0x4C Register Name PMU CPUVDD CTRL REG ADDR Read Wr Default SES Bit Description ite Hex 31 8 l CPUVDD_CTRL_REG_ADDR 7 0 R W 0x23 PMU CPUVDD DCDC Con
110. component 0x964 B V component 0x968 Read Wri Default SCH Bit Description te Hex S DR IYUV URCOEF 12 0 R W UDF the U R coefficient the value equals to coefficient 2 28 5 27 DEBE U R Constant Register Offset 0x96C Register Name DEBE URCONS REG Wri Default Description te Hex C 13 0 Register Name DEBE_URCOEF_REG TYUV_URCONS 13 0 R W UDF the U R constant the value equals to coefficient 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 337 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 28 5 28 DEBE V B Coefficient Register Offset G Y component 0x970 R U component 0x974 B V component 0x978 Read Wri Default a Description Hex IYUV VBCOEF the V B coefficient the value equals to coefficient 2 Register Name DEBE VBCOEF REG 10 28 5 29 DEBE V B Constant Register Offset 0x97C TYUV_VBCONS the V B constant the value equals to coefficient 2 28 5 30 DEBE Output Color Control Register Offset 0x9C0 Bit OC_EN Color control module enable control 0 disable 1 enable Color correction conversion algorithm formula R R R component coefficient R R G component coefficient G R B component coefficient B R constant Ge G R component coefficient R G G component coefficient G A13 User Manual V1 2 Copyright 2013 Allwinner Technology All
111. corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled R W 0x0 ADCO_ALRDY_HOLD_PENDING ADC 0 Already Hold Pending Bit When hold key pull down and pull the general key down if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled R W 0x0 ADC0_HOLDKEY_PENDING ADC 0 Hold Key pending Bit When Hold key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 NO IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled R W 0x0 ADCO_KEYDOWN_PENDING ADC 0 Key Down IRQ Pending Bit When General key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing to the bit will clear it and its corresponding interrupt if the A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 258 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 interrupt is enabled 0 R W 0x0 ADC0_DATA_PENDING ADC 0 Data IRQ Pending Bit 0 No IRQ 1 IRQ Pending Notes Wri
112. disable feature Support one SD Verson1 0 to 3 0 or MMC Verson3 3 to 4 3 or CE ATA device Support hardware CRC generation and error detection Support programmable baud rate Support host pull up control Support SDIO interrupts in 1 bit and 4 bit modes Support SDIO suspend and resume operation Support SDIO read wait Support block size of 1 to 65535 bytes Support descriptor based internal DMA controller Internal 16x32 bit 64 bytes total FIFO for data transfer Support 3 3 V IO pad 16 2 SD3 0 Timing Diagram Please refer to relative Specifications listed below Physical Layer Specification Ver3 00 Final 2009 04 16 SDIO Specification Ver2 00 Consumer Electronics Advanced Transport Architecture CE ATA version 1 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 160 Jau 8 2013 Allwinner Technology CO Ltd A13 Multimedia Cards MMC version 4 2 JEDEC Standard JESD84 44 Embedded Multimedia Card eMMC Card Product Standard A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 161 Jau 8 2013 Allwinner Technology CO Ltd A13 17 Two Wire Interface 17 1 Overview This Two Wire Interface TWI controller is an interface between CPU host and the serial 2 Wire bus which supports all standard 2 Wire transfer including Slave and Master The communication to the 2 Wire bus is carried out on a byte wise basis using interrupt
113. divided by m 1 The divider is from 1 to 16 6 4 33 DE FE Clock Default 0x00000000 Offset 0x10C Register Name FE_CFG_REG Read Wr Default DN Bit Description ite Hex SCLK_GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 75 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 FE RST 30 R W 0x0 DE FE Reset 0 reset valid 1 reset invalid 29 26 CLK SRC SEL Clock Source Select 00 PLL3 25 24 R W 0x0 01 PLL7 10 PLL5 11 23 18 17 16 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 34 LCD CH1 Clock Default 0x00000000 Offset 0x12C Register Name LCD_CH1_CFG_REG Bit E Gg Description ite Hex SCLK2_GATING Gating Special Clock 2 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock 2 Special Clock 2 Source Divider M 30 26 SCLK2_SRC_SEL Special Clock 2 Source Select 00 PLL3 1X 25 24 R W 0x0 01 PLL7 1X 10 PLL3 2X 11 PLL7 2X 23 18 17 16 R W 0x0 SCLK1_GATING Gating Special Clock 1 15 0 Clock is OFF 1 Clock is ON This special clock 1 Special Clock 1 Source 14 12 11 R W 0x0 SCLK1_SRC_SEL A13 User Manual V1 2 Copyright
114. hardware reset but does not alter it upon a software reset Remote wakeup signaling of the host system is host bus specific and is 9 R W R W 0x0 not described in this specification InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus If clear all interrupt are routed to the normal host bus interrupt mechanism If set interrupts are routed to the System Management Interrupt HCD clears this bit upon a hardware reset but it does not alter this bit upon a software reset HCD uses this 8 R W R 0x0 bit as a tag to indicate the ownership of HC HostControllerFunctionalState for USB 7 6 R W EW 0x0 00b USBReset A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 224 Jau 8 2013 7 Allwinner Technology CO Ltd A13 01b USBResume 10b USBOperational 11b USBSuspend A transition to USBOperational from another state causes SOF generation to begin I ms later HCD may determine whether HC has begun sending SOFs by reading the StartoFrame field of HclnterruptStatus This field may be changed by HC only when in the USBSUSPEND state HC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port HC enters USBSUSPEND after a software reset whereas it enters USBRESET after a hardware reset The latter also resets the Root Hub and asserts subsequent
115. industy standard double data rate II DDR2 ordinary SDRAM and Double data rate III DDR3 ordinary SDRAM It supports up to a 512MB memory address space The DRAMC automatically handles memory management initialization and refresh operations It gives the host CPU a simple command interface hiding details of the required address page and burst handling procedures All memory parameters are runtime configurable including timing memory setting SDRAM type and Extended Mode Register settings The DRAMC includes following features Support DDR2 SDRAM and DDR3 SDRAM Support different memory device power voltage of 1 5V and 1 8V Support DDR2 3 SDRAM of clock frequency up to DDR1066 Support memory capacity up to 512MB 15 address lines and 3 bank address lines Data IO size can up to 16 bit for DDR2 and DDR3 Automatically generate initialization and refresh sequences Runtime configurable parameters setting for application flexibility Clock frequency can be chosen for different applications Priority of transferring through multiple ports is programmable Support random read or write operation A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 84 Jau 8 2013 GW 7 Allwinner Technology CO Ltd A13 10 Pulse Width Modulator PWM 10 1 Overview The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its programmable registers Each channel has a dedicated int
116. is set when the content of HcRhStatus or the content of any of 6 R W R W 0x1 HcRhPortStatus NumberofDownstreamPort has changed FrameNumberOverflow This bit is set when the MSb of HcFmNumber bit 15 changes value from 0 to 1 or from 1 to 0 and after HccaFrameNumber has been 5 R W R W 0x0 updated UnrecoverableError This bit is set when HC detects a system error not related to USB HC should not proceed with any processing nor signaling before the system 4 R W R W 0x0 error has been corrected HCD clears this bit after HC has been reset A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 227 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 R W R W 0x0 ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling It is the transition from no resume signaling to resume signaling causing this bit to be set This bit is not set when HCD sets the USBRseume state R W R W 0x0 StartofFrame This bit is set by HC at each start of frame and after the update of HccaFrameNumber HC also generates a SOF token at the same time R W R W 0x0 WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead Further updates of the HccaDoneHead will not occur until this bit has been cleared HCD should only clear this bit after it has saved the content of HccaDoneHea
117. it 0 No effect 1 Pending timer 1 interval value is reached R W 0x0 STMRO_IRQ_ PEND Sync Timer 0 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 0 interval value is reached 12 3 3 Sync Timer 0 Control Register Default 0x00000004 Offset 0x10 Register Name SYNC_TMRO_CTRL_REG Bit Read Wr ite Default Hex Description 31 R W 0x0 SYNC TMRO TEST Sync timer0 test mode In test mode the low register should be set to 0x1 the high register will down count The counter needs to be reloaded 0 normal mode 1 test mode 30 8 R W 0x0 STMRO_MODE Sync Timer0 mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically Timer 0 Clock Source is fixed to AHBCLK 6 4 R W 0x0 STMRO_CLK_ Select the pre scale of the sync timer 0 clock source 000 1 001 2 010 4 011 8 100 16 101 110 111 3 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 105 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 STMRO RELOAD 1 R W 0x0 Sync Timer 0 Reload 0 No effect 1 Reload timer 0 Interval value STMRO_EN Sync Timer 0 Enabl
118. j sample n 1 NFC_RE d hns NFC_ALE A a H 0 gt NFC_RB A NFC_IOx Data 0 A Data n 1 Figure 15 2 Conventional Serial Access Cycle Diagram SAMO NFC_CLE A se Dr NEE NFC_CE A NFC_WE NFC_RE NFC_ALE sa H 0 gt NFC_RB A NFC_IOx Data o Data n 1 A13 User Manual V1 2 Figure 15 3 EDO Type Serial Access after Read Cycle SAM1 Copyright 2013 Allwinner Technology All Rights Reserved 153 Jau 8 2013 Allwinner Technology CO Ltd A13 NFC CLE A a Dr NFC_CE A NFC_WE A NFC_RE f TN Lamm NFC_ALE A w D e NFC_RB A NFC 1Ox Data X ffatain 1 Figure 15 4 Extending EDO Type Serial Access Mode SAM2 w a Dn NFC_CLE 13 a Mu NFC_CE KE E NFC_WE NFC_RE a Un VAN NFC_ALE a t8 gt lt t9 gt NFC x D COMMAND K A13 User Manual V1 2 Figure 15 5 Command Latch Cycle Copyright O 2013 Allwinner Technology All Rights Reserved 154 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 at gt NFC CLE A WEE NFC_CE A NFC_WE NR NFC RE A WEE la ah NFC ALE le t8 gt a t9 gt NFC JC D Addr 0 f Addr n 1 GG Figure 15 6 Address Latch Cycle bn a t2 s NFC_CLE e a LES En NFC_CE t15 4 t5 gt a t6 NFC_WE NFC_RE A
119. level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 21 20 R W 0x0 IRQ90_PRIO IRQ 90 Priority Set priority level for IRQ bit 90 Level0 0x0 level 0 lowest priority A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Offset 0x94 Register Name INTC_SRC_PRIO_REGS Levell 0x1 level 1 Level 0x1 level 2 Level3 0x1 level 3 highest priority IRQ89_PRIO IRQ 89 Priority Set priority level for IRQ bit 89 19 18 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ88 PRIO IRQ 88 Priority Set priority level for IRQ bit 88 17 16 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority IRQ87 RPIO IRQ 87 Priority Set priority level for IRQ bit 87 15 14 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority IRQ86 RPIO IRQ 86 Priority Set priority level for IRQ bit 86 13 12 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ85 PRIO IRQ 85 Priority Set priority level for IRQ bit 85 11 10 R W 0x0 Level0 0x0
120. lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 27 26 R W 0x0 IRQ29_PRIO A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 122 7 Allwinner Technology CO Ltd Offset 0x84 Register Name INTC SRC PRIO REGI A13 IRQ 29 Priority Set priority level for IRQ bit 29 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 25 24 R W 0x0 IRQ28_PRIO IRQ 28 Priority Set priority level for IRQ bit 28 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 23 22 R W 0x0 IRQ27_PRIO IRQ 27 Priority Set priority level for IRQ bit 27 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 21 20 R W 0x0 IRQ26_PRIO IRQ 26 Priority Set priority level for IRQ bit 26 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 19 18 R W 0x0 IRQ25_PRIO IRQ 25 Priority Set priority level for IRQ bit 25 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 17 16 R W 0x0 IRQ24_PRIO IRQ 24 Priority Set prior
121. nis tee ea 241 23 Audio Cod t visccsessiaiscasssasscasssadssasssacssadssadesasssosssasssadesesssasesadedesesesssasesasssavesasssaseda ssetesesssasssals evesatssosesaseies 242 23d RE 242 282 Adio Codec Block KEE RE 242 23 34 A dio Codec Register LAS bet ict neo ened shhh nie aa i iiS 243 23 4 Audio Codec Register Description 0 0 0 0 i ill lien 243 23 4 1 DAC Digital Part Control Red cecal acetates ecaretelatenattdetereeadeeensdecadenses 243 23 4 2 DAC PIECH 243 23 4 3 DAG FIFO Status Register scsnnon nai 245 23 4 4 DAC GE EE EEE NENNE 246 23 4 5 DAC Analog Control e EE 246 23 4 6 EE 248 23 4 7 ADC FIFO Status Register ccc ieee 249 23 4 8 AD ARA DATA Eet better 250 23 4 9 ADC Analog Control Register 250 23 4 10 DAC TX Counter Fester 252 23 4 11 ADC RX Counter eelere ie 252 24 LRADC O I I A A T E A E 254 24 1 EE 254 24 2 Principle Of Ee 254 24 2 1 Block Diagram EEE 254 24 2 2 Hold Key and General Key Function Introductton 254 24 3 ERADC Re sister Degetwtott sates aceite sete iets ate ieee ate ee ee eene enee 255 24 3 1 LRADC Control KEE 255 24 3 2 LRADC Interrupt Control Register sus entnete 256 24 3 3 LRADC Interrupt Status Register Rie nnnnndihehahdhahani 257 24 3 4 LRADC Data 0 Reise 259 24 3 5 LRADC Data 1 BEE 259 25 Touch Panel Controller TPC seecssseccssoocssooccsosoceseooceseoecscsocssosoccsssocsssoocsssocssosocssssecssssecsssoecsssocssssoesssse 260 25 1 OVELVIEW sr E E eee 260 25 2
122. part of the horizontal scaling ratio the horizontal scaling ratio input width output width FACTOR_FRAC 15 0 R W 0x0 The fractional part of the horizontal scaling ratio the horizontal scaling ratio input width output width 27 5 39 DEFE CHO VERTFACT REG Offset Ox 10C Register Name DEFE CHO VERTFACT REG Read Wr Default SS Bit Description ite Hex 31 24 FACTOR_INT 23 16 R W 0x0 The integer part of the vertical scaling ratio the vertical scaling ratio input height output height FACTOR_FRAC 15 0 R W 0x0 f The fractional part of the vertical scaling ratio A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 309 7 Allwinner Technology CO Ltd A13 the vertical scaling ratio input height output height 27 5 40 DEFE CHO HORZPHASE REG Offset Ox 110 Register Name DEFE CHO HORZPHASE REG Read Wr Default a Bit Description ite Hex 31 20 PHASE 19 0 R W 0x0 Y G component initial phase in horizontal complement This value equals to initial phase a 27 5 41 DEFE CHO VERTPHASEO REG Offset 0x114 Register Name DEFE CHO VERTPHASEO REG Read Wr Default P Bit i Description ite Hex 31 20 PHASE 19 0 R W 0x0 Y G component initial phase in vertical for top field complement This value equals to initial phase a 27 5 42 DEFE CHO VERTPHASE1 REG
123. ports for multi functional input out pins They are Port B PB 10input output port Port C PC 17 input output port Port D PD 22 input output port Port E PE 12 input output port Port F PF 6 input output port Port G PG 9 input output port These ports can be easily configured by software for various system configurations 33 2 Port Configuration Table oe Function Select KN C SS ago awns mae maer was EE we Laag sense ae smax A EC A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 381 Jau 8 2013 GW 7 Allwinner Technology CO Ltd Se SC SS NDS SES NDQ7 Se i Le SS Ss 11 SS Pip KH CSI PCLK CSI MCLK CSL Di SDC2_D1 CSI_D2 SDC2_D2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 382 Q Y Allwinner Technology CO Ltd A13 SDCO Di P P P P P PE7 PES PE9 PFO PFI J PF2 PF3 PF4 PF5 b G0 G1 G2 G3 G4 G9 P Note The PEO PE1 PE2 and PG0 1 2 are for input only UARTI TX P G G G G G G G G G 33 3 Port Register List Module Name Base Address PIO 0x01C20800 Register Name Offset Description Pn CFGO n 0x24 0x00 Port n Configure Register 0 n from 0 to 6 Pn_CFG1 n 0x24 0x04 Port n Configure Register 1 n from 0 to 6 Pn_CFG2 n 0x24 0x08 Port n
124. range of 0 255 15 8 CEU Coef Range Max 7 0 R W 0 unsigned 8bit value range of 0 255 29 3 31 TCONI FILL CTL REG Offset 0x300 Register Name TCONI fill data control register Read Wr Default Bit Description ite Hex TCON1_Fill_En 31 R W 0 0 bypass 1 enable 30 0 29 3 32 TCONI FILL BEGIN REG Offset 0x304 0x310 0x31C Register Name TCONI fill data begin register Read Wr Default SES Bit j Description ite Hex 31 24 23 0 R W 0 Fill Begin 29 3 33 TCONI1 FILL END REG Offset 0x308 0x314 0x320 Register Name TCONI fill data end register Read Wr Default Le Bit f Description ite Hex 31 24 23 0 R W 0 Fill End 29 3 34 TCONI FILL DATA REG Offset 0x30C 0x318 0x324 Register Name TCONI fill data value register Read Wr Default Bit Description ite Hex 31 24 23 0 R W 0 Fill_ Value A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 363 Ou 7 Allwinner Technology CO Ltd A13 30 Image Enhancement Processor IEP 30 1 Overview The Image Enhancement Processor IEP is capable of adjusting the dynamic range of pictures according to statistics 30 2 IEP Register Description 30 2 1 General Control Register Offset 0X0000 Register Name IMGEHC_GNECTL_REG Read Wri Default o Bit Description te Hex BIST_EN BIST enable Work mode selection If bit O of the register is set ZERO
125. reset signaling to downstream ports R W 0x0 BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame If cleared by HCD processing of the Bulk list does not occur after the next SOF HC checks this bit whenever it determines to process the list When disabled HCD may modify the list If HcBulkCurrentED is pointing to an ED to be removed HCD must advance the pointer by updating HcBulkCurrentED before re enabling processing of the list R W 0x0 ControlListEnable This bit is set to enable the processing of the Control list in the next Frame If cleared by HCD processing of the Control list does not occur after the next SOF HC must check this bit whenever it determines to process the list When disabled HCD may modify the list If HcControlCurrentED is pointing to an ED to be removed HCD must advance the pointer by updating HcControlCurrentED before re enabling processing of the list R W 0x0 IsochronousEnable This bit is used by HCD to enable disable processing of isochronous EDs While processing the periodic list in a Frame HC checks the status of this bit when it finds an Isochronous ED F 1 If set enabled HC continues processing the EDs If cleared disabled HC halts processing of the periodic list which now contains only isochronous EDs and begins processing the Bulk Control lists Setting this bit is guaranteed to take effect in the next Frame not the c
126. the U V data are not combined channeO 1 2 refer to the Y U V data channel respectively and if the U V data are combined the channel refers to the Y channel and the channel 1 refers to the U V combined channel and the channel will be inactive In interleaved mode the channel refers to UYVY or VYUY YUYV or YVYU depending on the configuration the channell and channel2 will be inactive Source Pixel Rows Target Pixel A13 2 2 Y HD Xl PR a m m 1 Hl Note Interleaved YUV data only YUV422 and YUV444 format is valid 27 3 5 version data for write back to memory Conversion algorithm formula R R Y component coefficient Y R U component coefficient U R V component coefficient V R constant G G Y component coefficient Y G U component coefficient U G V component coefficient V G constant B B Y component coefficient Y B U component coefficient U B V component coefficient V B constant 27 3 6 DEFE Source Input Formats CSC Color Space Conversion Description YUV RGB conversion is used to generate an RGB version data of the image for display or RGB YUV Y Y R component coefficient R Y G component coefficient G Y B component coefficient B Y constant U U R component coefficient R U G component coefficient G U B component coefficient B U constant V V R component coefficient R
127. the following setting will be ignored 00 Output FIFO mode 01 De flicker mode 0 disabled the module and the whole module will be by passed 1 enable 30 2 2 DRC Size Setting Register Offset 0X0004 Register Name IMGEHC_DRCSIZE_REG Read Wri Default Bit Description te Hex DRC HEIGHT 27 16 R W Display height The real display height The value of these bits 1 DRC_WIDTH 11 00 R W e Display width A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 364 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 The real display width The value of these bits 1 30 2 3 DRC Control Ro Offset 0X0010 Register Name IMGEHC_DRCCTL_REG n Name IMGEHC_DRCCTL_REG Read Wri Default Description DRC_WIN_EN Output window function enable 0 disable Only valid when DRC_DB_EN bit is set If the bit is set when the SYNC signal is coming the all double buffered DRC registers will be loaded and the loading is done the bit will be cleared automatically DRC_DB_EN DRC double buffer function enable control 0 disable 1 enable LGC Luminance Gain Coefficient 30 2 4 DRC External LGC Start Address Register Offset 0X0014 Register Name IMGEHC_DRCLGC_STAADD_REG Read Wri Default aan Bit Description te Hex DRC_LGC_STAADD 31 00 R W Start address in byte Double buffered register of DRC double buffer function is controlled by DRC_DB_EN and DRC_DBRDY_CTL b
128. tile based type The address is the start address of the first line 27 5 7 DEFE_BUF_ADDR1_REG Offset 0x24 Register Name DEFE_BUF_ADDR1_REG Read Wr Default SSC Bit Description ite Hex BUF_ADDR DEFE frame buffer address In tile based type 31 0 R W 0x0 AEN The address is the start address of the line in the first tile used to generate output frame In non tile based type A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 297 Jau 8 2013 7 Allwinner Technology CO Ltd A13 The address is the start address of the first line 27 5 8 DEFE BUF ADDR2 REG Offset 0x28 Register Name DEFE_BUF_ADDR2_REG Read Wr Default sch Bit Description ite Hex BUF_ADDR DEFE frame buffer address In tile based type 31 0 R W 0x0 The address is the start address of the line in the first tile used to generate output frame In non tile based type The address is the start address of the first line 27 5 9 DEFE_FIELD_CTRL_REG Offset 0x2C Register Name DEFE_FIELD_CTRL_REG Read Wr Default Bit Description ite Hex 31 13 FIELD_LOOP_MOD 12 R W 0x0 Field loop mode 0 the last field 1 the full frame 11 VALID_FIELD_CNT 10 8 R W 0x0 Valid field counter bit the valid value this value 1 FIELD_CNT 7 0 R W 0x0 Field counter each bit specify a field to display 0 top field 1
129. to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortResetStatus but instead sets ConnectStatusChange This informs the driver that it attempted to reset a disconnected port R W R W 0x0 read PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per port basis If per port overcurrent reporting is not supported this bit is set to 0 If cleared all power operations are normal for this port If set an overcurrent condition exists on this port This bit always reflects the overcurrent input signal 0 no overcurrent condition 1 overcurrent condition detected write ClearSuspendStatus The HCD writes a 1 to initiate a resume Writing a 0 has no effect A resume is initiated only if PortSuspendStatus is set R W R W 0x0 read PortSuspendStatus This bit indicates the port is suspended or in the resume sequence It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval This bit cannot be set if CurrentConnectStatus is cleared This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the USBRESUME state If an upstream resume is in progress it should propagate to the HC 0 port is not suspended 1 port is
130. undefined if Port Power is zero Reserved This bit is reserved for future use and should return a value of zero when read R W Port Reset 1 Port is in Reset 0 Port is not in Reset Default value 0 When software writes a one to this bit from a zero the bus reset sequence as defined in the USB Specification Revision 2 0 is started Software writes a zero to this bit to terminate the bus reset sequence Software must keep this bit at a one long enough to ensure the reset sequence as specified in the USB Specification Revision 2 0 completes Notes when software writes this bit to a one it must also write a zero to the Port Enable bit Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero The bit status will not read as a zero until after the reset has completed If the port is in high speed mode after reset is complete the host controller will automatically enable this port e g set the Port Enable bit to a one A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero For example if the port detects that the attached device is high speed during reset then the host controller must have the port in the enabled state with 2ms of software writing this bit to a zero The HC Halted bit in the USBSTS register should be a zero before software attempts to use this bit Th
131. use to halt transmissions for testing so that the transmit 0 R W 0 FIFO can be filled by the master when FIFOs are implemented and A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 199 Jau 8 2013 GW Allwinner Techno logy CO Ltd A13 enabled 0 Halt TX disabled 1 Halt TX enabled Note If FIFOs are not enabled the setting of the halt TX register has no effect on operation 19 5 UART Special Re 19 5 1 IrDA Inverted Signals quirement When the UART is working in IrDA mode MCR 6 1 if HALT 4 is set to 1 the signal is inverted before transferring to pin SOUT and if HALT S is set to 1 the signal is inverted after receiving from pin SIN A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 200 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 20 CIR Interface 20 1 Overview The CIR features Full physical layer implementation Support CIR for remote control or wireless keyboard Dual 8x16 bit FIFO for data transfer Programmable FIFO thresholds Support Interrupt and DMA CIR receiver is implemented in hardware to save CPU resource It samples the input signals on the programble frequency and records these samples into RX FIFO when one CIR signal is found on the air The CIR receiver uses Run Length Code RLC to encode pulse width and the encoded data is buffered in a 64 levels and
132. value 01b 512 elements 2048byts 10b 256 elements 1024bytes For resource constrained condition 11b reserved The default value is 00b R W Host Controller Reset This control bit is used by software to reset the host controller The effects of this on Root Hub registers are similar to a Chip Hardware Reset When software writes a one to this bit the Host Controller resets its internal pipelines timers counters state machines etc to their initial value Any transaction currently in progress on USB is immediately terminated A USB reset is not driven on downstream ports All operational registers including port registers and port state machines are set to their initial values Port ownership reverts to the companion host controller s Software must reinitialize the host controller as described in Section 4 1 of the CHEI Specification in order to return the host controller to an operational state This bit is set to zero by the Host Controller when the reset process is complete Software cannot terminate the reset process early by writing a zero to this register Software should not set this bit to a one when the HC Halted bit in the USBSTS register is a zero Attempting to reset an actively running host controller will result in undefined behavior A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 214 Jau 8 2013 Ou Allwinner Technolo
133. 0 19 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 57 Ou 7 Allwinner Technology CO Ltd A13 18 17 R W 0x0 16 0 R W 0x0 6 4 5 PLL3 Video Default 0x0010D063 Offset 0x10 Register Name PLL3_CFG_REG Read Wr Default a Bit Description ite Hex PLL3_Enable 0 Disable 1 Enable 31 R W 0x0 In the integer mode The PLL3 output 3MHz M In the fractional mode the PLL3 output is select by bit 14 The PLL3 output range is 27MHz 381MHz 30 27 26 24 R W 0x0 23 21 20 16 R W 0x10 PLL3_MODE_SEL 15 R W Ox1 PLL3 mode select 0 fractional mode 1 integer mode PLL3 FUNC SET 14 R W 0x1 PLL3 fractional setting 0 270MHz 1 297MHz 13 12 8 R W 0x10 7 PLL3_FACTOR_M 6 0 R W 0x63 PLL3 Factor M The range is from 9 to 127 6 4 6 PLL4 VE Default 0x21081000 Offset 0x18 Register Name PLL4 CFG REG Read Wr Default o Bit f Description ite Hex PLIA Enable 0 Disable 1 Enable The PLL4 output 24MHz N K M P 31 R W 0x0 The PLL4 output is for the VE Note the output 24MHz N K clock must be in the range of 240MHz 2GHz if the bypass is disabled PLL4_OUT_BYPASS_EN 30 R W 0x0 PLLA Output Bypass Enable 0 Disable 1 Enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserve
134. 00 31 5KHz 01 32KHz 10 32 5KHz 11 33KHz 18 17 R W 0x0 WAVE_BOT Wave Bottom 16 0 R W 0x0 6 4 12 PLL5 Tuning2 Default 0x00000000 Offset 0x3C Register Name PLL5 TUN2 REG Read Wr Default i Bit Description ite Hex SIG_DELT_PAT_EN Sigma delta pattern enable 31 R W 0x0 SPR_FREQ_MODE Spread Frequency Mode 00 DC 0 01 DC 1 10 Triangular 30 29 R W 0x0 11 awmode WAVE_STEP Wave step 28 20 R W 0x0 19 FREQ Frequency 18 17 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 62 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 00 31 5KHz 01 32KHz 10 32 5KHz 11 33KHz WAVE BOT Wave Bottom 16 0 R W 0x0 6 4 13 OSC24M Default 0x00138013 Offset 0x50 Register Name OSC24M_CFG_REG Read Wr Default AS Bit A Description ite Hex 31 24 R W 0x0 23 18 PLL_IN_PWR_SEL 17 R W Ox1 PLL Input Power Select 0 2 5v 1 3 3v LDO EN 16 R W Ox1 LDO Enable 0 Disable 1 Enable PLL BIAS EN PLL Bias Enable 15 R W Ox1 0 disable 1 enable 14 2 OSC24M_GSM 1 R W Ox1 OSC24M GSM OSC24M EN 0 R W Ox1 OSC24M Enable 0 Disable 1 Enable 6 4 14 CPU AHB APBO Clock Ratio Default 0x00010010 Offset 0x54 Register Name CPU AHB APBO CFG REG
135. 0x0 16 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 67 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 15 8 WE CH SIISSJSSISS ISIS zo ln o ln ISIS SIISSISISISS ISIS TWI2_APB_GATING Gating APB Clock for TWI2 0 mask 1 pass E 0x0 TWI1_APB_GATING 1 R W 0x0 Gating APB Clock for TWI1 0 mask 1 pass TWIO APB GATING Gating APB Clock for TWIO 0 mask 1 pass 0 R W 0x0 6 4 21 NAND Clock Default 0x00000000 Offset 0x80 Register Name NAND_SCLK_CFG_REG Read Wr Default a Bit Description ite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLL5 11 25 24 R W 0x0 23 18 CLK_DIV_RATIO_N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 Note In application the module clock frequency always switches off 6 4 22 SDO Clock Default 0x00000000 Offset 0x88 Register Name SDO_SCLK_CFG_REG A13 User Manual V1 2 Co
136. 0x00000000 Offset 0x20 Register Name INTC_FIQ_PEND_REGO Read Wr Default 2 Bit Description ite Hex INT FIQ SRC PENDO Interrupt FIQ Source 31 0 Pending Clear Bit 31 0 R 0x0 or d 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 9 Interrupt FIQ Pending Clear Register 1 Default 0x00000000 Offset 0x24 Register Name INTC_FIQ_PEND_REG1 Read Wr Default SS Bit Description ite Hex INT FIQ SRC PENDI Interrupt Source 63 32 Pending Clear Bit 31 0 R 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 115 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 10 Interrupt FIQ Pending Clear Register 2 Default 0x00000000 Offset 0x28 Register Name INTC_FIQ_PEND_REG2 Read Wr Default as Bit Description ite Hex INT FIQ SRC PEND2 Interrupt Source 95 64 Pending Clear Bit 31 0 R 0x0 T f 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 11 Interrupt Select Register 0 Default 0x00000000 Offset 0x30 Register Name INTC_SEL_REGO Read Wr Default L Bit f Description ite Hex INT_SRC_TYPEO Interrupt Source 31 0 irq type select 0 IRQ 1 FIQ 31 0 R W 0x0
137. 0x100 Register Name DRAM_SCLK_CFG_REG Read Wr Default aS Bit Description ite Hex IEP_DCLK_GATING 31 R W 0x0 Gating DRAM Clock for IEP 0 mask 1 pass 30 ACE_DCLK_GATING 29 R W 0x0 Gating DRAM Clock for ACE 0 mask 1 pass 28 27 BE_DCLK_GATING 26 R W 0x0 Gating DRAM Clock for DE_BE 0 mask 1 pass FE_DCLK_GATING 25 R W 0x0 Gating DRAM Clock for DE_FE 0 mask 1 pass 24 23 16 15 14 7 6 5 R W 0x0 4 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 74 Jau 8 2013 N 7 Allwinner Technology CO Ltd A13 3 R W 0x0 2 CSI_DCLK_GATING 1 R W 0x0 Gating DRAM Clock for CSI 0 mask 1 pass VE_DCLK_GATING 0 R W 0x0 Gating DRAM Clock for VE 0 mask 1 pass 6 4 32 DE BE Clock Default 0x00000000 Offset 0x 104 Register Name BE CFG REG Read Wr Default nae Bit Description ite Hex SCLK_GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M BE_RST 30 R W 0x0 DE BE Reset 0 reset valid 1 reset invalid 29 26 CLK SRC SEL Clock Source Select 25 24 R W 0x0 a 01 PLL7 10 PLL5 11 23 18 17 16 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is
138. 1 to clear this bit Writing a 0 has no effect 0 port reset is not complete 1 port reset is complete 19 R W R W 0x0 PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per port basis This bit is set when Root Hub changes the PortOverCurrentIndicator bit The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 no change in PortOverCurrentIndicator 1 PortOverCurrentIndicator has changed 18 R W R W 0x0 PortSuspendStatusChange This bit is set when the full resume sequence has been completed This sequence includes the 20 s resume pulse LS EOP and 3 ms resychronization delay The HCD writes a 1 to clear this bit Writing a 0 has no effect This bit is also cleared when ResetStatusChange is set 0 resume is not completed 1 resume completed 17 R W R W 0x0 PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared Changes from HCD writes do not set this bit The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 no change in PortEnableStatus 1 change in PortEnableStatus 16 R W R W 0x0 ConnectStatusChange This bit is set whenever a connect or disconnect event occurs The HCD writes a 1 to clear this bit Writing a 0 has no ef
139. 1 2 NMI_SRC_TYPE External NMI Interrupt Source Type 00 Low level sensitive 1 0 R W 0x0 01 Negative edge trigged 10 High level sensitive 11 Positive edge sensitive A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 114 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 13 4 5 Interrupt IRQ Pending Register 0 Default 0x00000000 Offset 0x 10 Register Name INTC IRQ PEND REGO Read Wr Default a Bit f Description ite Hex INT_IRQ_SRC_PENDO Interrupt IRQ Source 31 0 Pending Clear Bit 31 0 R 0x0 BIE i 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 6 Interrupt IRQ Pending Register 1 Default 0x00000000 Offset 0x 14 Register Name INTC_PEND_REG1 Read Wr Default ae Bit Description ite Hex INT IRQ SRC PENDI Interrupt IRQ Source 63 32 Pending Clear Bit 31 0 R 0x0 DE i s 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 13 4 7 Interrupt IRQ Pending Register 2 Default 0x00000000 Offset 0x18 Register Name INTC_PEND_REG2 Read Wr Default oe Bit Description ite Hex INT IRQ SRC PEND2 Interrupt IRQ Source 95 64 Pending Clear Bit 0 Corresponding interrupt is not pending 31 0 R 0x0 1 Corresponding interrupt is pending 13 4 8 Interrupt FIQ Pending Clear Register 0 Default
140. 1 2 Copyright 2013 Allwinner Technology All Rights Reserved 64 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 23 18 CLK RAT N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 5 CLK_RAT_M 4 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 16 AXI Module Clock Gating Default 0x00000000 Offset 0x5C Register Name AXI_GATING_REG Read W Default E Bit Description rite Hex 31 1 DRAM_AXI_GATING Gating AXI Clock for SDRAM 0 mask 1 pass 0 R W 0x0 6 4 17 AHB Module Clock Gating Register 0 Default 0x00000000 Offset 0x60 Register Name AHB_GATING_REGO Read W Default ae Bit i Description rite Hex 31 29 STIMER_AHB_GATING 28 R W 0x0 Gating AHB Clock for Sync timer 0 mask 1 pass 27 26 R W 0x0 25 23 SPI2_AHB_GATING 22 R W 0x0 Gating AHB Clock for SPI2 0 mask 1 pass SPI1_AHB_GATING 21 R W 0x0 Gating AHB Clock for SPI1 0 mask 1 pass SPIO AHB GATING 20 R W 0x0 Gating AHB Clock for SPIO 0 mask 1 pass 19 18 R W 0x0 17 R W 0x0 16 15 SDRAM_AHB_GATING 14 R W 0x0 i Gating AHB Clock for SDRAM 0 mask 1 pass NAND AHB GATING 13 R W 0x0 Gating AHB Cl
141. 11 gt 10 gt 01 gt 00 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 326 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 When more than 2 layers are enabled the priority value of each layer must be different so designers must keep the condition If more than 1 layers select the same pipe in the overlapping area only the pixel of highest priority layer can pass the pipe to blender1 Setting 2 or more layers YUV channel mode is illegal so programmers should confirm it LAY_VDOEN Layer video channel selection enable control 0 disable Normally one layer can not be set both video channel and YUV channel mode If both 2 mode are set the layer will work in video channel mode and YUV channel mode will be ignored so programmers should confirm it Setting 2 or more layers video channel mode is illegal and programmers should confirm it LAY_GLBALPHAEN Alpha Enable 0 Disabled the alpha value of this register 1 Enabled the alpha value of this register for the layer 28 5 14 DE Layer Attribute Control Register Offset Layer0 Ox8A0 Layerl 0x8A4 Register Name DEBE_ATTCTL_REG1 Layer2 0x8A8 Layer3 Ox8AC Read Wri Default SC Bit Description te Hex 31 16 LAY_HSCAFCT 15 14 R W Setting the internal frame buffer scaling factor only valid in internal frame buffer mode A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 327 Ja
142. 111 23 PCS Select 000 Input 001 Output 010 NRE 011 100 101 22 20 R W 0 110 111 19 PC4 Select 000 Input 001 Output 010 NCEO 011 100 101 18 16 R W 0 110 111 15 PC3 Select 000 Input 001 Output 010 NCE1 011 SPIO_CSO 100 101 14 12 R W 0 110 111 11 PC2 Select 000 Input 001 Output 010 NCLE 011 SPIO_CLK 100 101 10 8 R W 0 110 111 7 PC1 Select 000 Input 001 Output 010 NALE 011 SPIO_MISO 100 101 6 4 R W 0 110 111 3 2 0 R W 0 PCO Select A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 388 Ou 7 Allwinner Technology CO Ltd A13 000 Input 001 Output 010 NWE 011 SPIO MOSI 100 101 110 111 33 4 11 PC Configure Register 1 Register Name PC_CFG1 Offset 0x4C Default Value 0x0000 0000 Bit Read Write Default Description 31 PC15 Select 000 Input 001 Output 010 NDQ7 011 SDC2_D7 100 101 30 28 R W 0 110 11 27 PC14 Select 000 Input 001 Output 010 NDQ6 011 SDC2_D6 100 101 26 24 R W 0 110 111 23 PC13 Select 000 Input 001 Output 010 NDQ5 011 SDC2_D5 100 101 22 20 R W 0 110 111 19 PC12 Select 000 Input 001 Output 010 NDQ4 011 SDC2_D4 100 101 18 16 R W 0 110 111 15
143. 13 Ou Allwinner Technology CO Ltd A13 0 normal operation ignore RXFIFO status 17 R W SS LEVEL When control SS signal manually SPI CTRL REG SS CTRL 1 set this bit to 1 or 0 to control the level of SS signal 1 set SS to high 0 set SS to low 16 R W SS CTRL SS Output Mode Select Usually controller sends SS signal automatically with data together When this bit is set to 1 software must manually write SPI CTRL REG SS LEVEL bit 17 to 1 or O to control the level of SS signal 1 manual output SS 0 automatic output SS 15 R W Discard Hash Burst DHB In master mode it controls whether discarding unused SPI bursts when SMC is 1 0 Receiving all SPI bursts in BC period 1 Discard unused SPI bursts only fetching the SPI bursts during dummy burst period The bursts number is specified by WTC 14 R W DDB Dummy Burst Type 0 The bit value of dummy SPI burst is zero 1 The bit value of dummy SPI burst is one 13 12 R W SS SPI Chip Select Select one of four external SPI Master Slave Devices 00 SPI_SSO will be asserted 01 SPI_SS1 will be asserted 10 SPI_SS2 will be asserted 11 SPI_SS3 will be asserted Notes These two bits can t be configured for SPI1 Engine 11 R W RPSM Rapids Mode Select Select Rapids operation mode for high speed read 0 Normal read mode 1 Rapids read mode 10
144. 13 Ou 7 Allwinner Technology CO Ltd A13 1 Enable R W TXFIFO Empty DMA Request Enable 0 Disable 1 Enable RXFIFO 3 4 Full DMA Request Enable This bit enables disables the RXFIFO 3 4 Full DMA Request 0 Disable 1 Enable RXFIFO 1 4 Full DMA Request Enable This bit enables disables the RXFIFO 1 4 Full DMA Request 0 Disable 1 Enable RXFIFO Full DMA Request Enable This bit enables disables the RXFIFO Half Full DMA Request 0 Disable 1 Enable RXFIFO Half Full DMA Request Enable This bit enables disables the RXFIFO Half Full DMA Request 0 Disable 1 Enable 0 R W RXFIFO Ready Request Enable This bit enables disables the RXFIFO Ready DMA Request when one or more than one words in RXFIFO 0 Disable 1 Enable 18 4 7 SPI Wait Clock Register Offset 0x18 Register Name SPI WAIT Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 0 R W WCC Wait Clock Counter In Master mode These bits control the number of wait states to be inserted in data transfers The SPI module counts SPI_SCLK by WCC for delaying next word data transfer 0 No wait states inserted N N SPI SCLK wait states inserted 18 4 8 SPI Clock Control Register Offset Ox1C Register Name SPI CCTL A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 180 Jau
145. 13 22 USB Host Controller 22 1 Overview USB Host Controller is fully compliant with the USB 2 0 specification Enhanced Host Controller Interface EHCI Specification Revision 1 0 and the Open Host Controller Interface OHCI Specification Release 1 0a The controller supports high speed 480 Mbps transfers 40 times faster than USB 1 1 full speed mode using an EHCI Host Controller as well as full and low speeds through one or more integrated OHCI Host Controllers It features Include an internal DMA Controller for data transfer with memory Comply with Enhanced Host Controller Interface EHCI Specification Version 1 0 and the Open Host Controller Interface OHCD Specification Version 1 0a Support High Speed HS 480 Mbps Full Speed FS 12 Mbps and Low Speed LS 1 5 Mbps Device Support only one USB Root Port shared between EHCI and OHCI 22 2 USB Host Block Diagram The USB host controller System Level block diagram is showed below a USB HCI EHCI n 7 A AHB l S Slave Q UTNTES ee USB Port gt E S 2 A e Loi OHCI A me gt ee Y DRAM Memory Figure22 1 USB Host Block Diagram 22 3 USB Host Timing Diagram Please refer USB2 0 Specification Enhanced Host Controller Interface EHCI Specification Version 1 0 and A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reser
146. 15_PRIO IRQ 15 Priority 31 30 R W 0x0 Set priority level for IRQ bit 15 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 119 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Offset 0x80 Register Name INTC SRC PRIO REGO Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ14 PRIO IRQ 14 Priority Set priority level for IRQ bit 14 29 28 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ13 PRIO IRQ 13 Priority Set priority level for IRQ bit 13 27 26 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ12 PRIO IRQ 12 Priority Set priority level for IRQ bit 12 25 24 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ11 PRIO IRQ 11 Priority Set priority level for IRQ bit 11 23 22 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ10 PRIO IRQ 10 Priority Set priority level for IRQ bit 10 21 20 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority IRQ9 PRIO IR
147. 16 DE HWC Coordinate Control Register 332 28 5 17 DE HWC Frame Buffer Format Register 332 28 5 18 DEBE Write Back Control Register en 333 28 5 19 DEBE Write Back Address Register AAA 334 28 5 20 DEBE Write Back Buffer Line Width Register 334 28 5 21 DEBE Input YUV Channel Control Register A 334 28 5 22 DEBE YUV Channel Frame Buffer Address Heolster 335 28 5 23 DEBE YUV Channel Buffer Line Width Register escesseeseeeeeseeeseeteeeeeseeees 336 28 5 24 DEBE Y G Coefficient Regser E 336 28 5 25 DEBE Y G Constant R OT 337 28 5 26 DEBE UA Coefficient et 337 20527 DEBE UR Constant RER sr 337 28 5 28 DEBE VB Coefficient eeben Ee eene DES 338 28 5 29 DEBE V B Constant Reise un nn re 338 28 5 30 DEBE Output Color Control R gis Rennes 338 28 5 31 DEBE Output Color R Coefficient Register veve 339 28 5 32 DEBE Output Color R Constant Register us 339 28 5 33 DEBE Output Color G Coefficient Register 339 28 5 34 DEBE Output Color G Constant Register 340 28 5 35 DEBE Output Color B Coefficient Register 340 28 5 36 DEBE Output Color B Constant Register minimum nu nivni 340 28 5 37 DE HWG Pattern Memory BlOGK sscssiisncscccscnsianctenctenctnnsdnnsdanedenctansdcned anntandsanctundieaceess 340 28 5 38 DE HWC Palette Tables NN 341 28 5 39 Palette Mod see n ebe add 342 A13 User Manual V1 2 Copyright 2013 Allwinner Technology A
148. 1C0 AFFF 0x01C0 B000 0x01C0 BFFF LCD 0x01C0 C000 0x01C0 CFFF 4K 0x01C0 D000 0x01CO DFFF 4K VE 0x01C0 E000 0x01C0 EFFF 4K SD MMC 0 0x01C0 F000 0x01CO0 FFFF 4K SD MMC 1 0x01C1 0000 0x01C1 OFFF 4K SD MMC 2 0x01C1 1000 0x01C1 1FFF 4K 0x01C1 2000 0x01C1 2FFF 4K USB OTG 0x01C1 3000 0x01C1 3FFF 4K USB HCI 0x01C1 4000 0x01C1 4FFF 4K SS 0x01C1 5000 0x01C1 5FFF 4K d 0x01C1 6000 0x01C1 6FFF SPI 2 0x01C1 7000 0x01C1 7FFF 4K 0x01C1 8000 0x01C1 8FFF 4K 0x01C1 9000 0x01C1 9FFF 4K 0x01C1 A000 0x01C1 AFFF 4K 0x01C1 B000 0x01C1 BFFF 4K 0x01C1 C000 0x01C1 CFFF 4K 0x01C1 D000 0x01C1 DFFF 4K 0x01C1 E000 0x01C1 EFFF 4K 0x01C1 F000 0x01C1 FFFF 4K CCM 0x01C2 0000 0x01C2 03FF IK INTC 0x01C2 0400 0x01C2 O7FF 1K PIO 0x01C2 0800 0x01C2 OBFF 1K Timer 0x01C2 0C00 0x01C2 OFFF 1K 0x01C2 1000 0x01C2 13FF IK 0x01C2 1400 0x01C2 17FF IK IR 0x01C2 1800 0x01C2 1BFF IK 0x01C2 1C00 0x01C2 1FFF IK 0x01C2 2000 0x01C2 23FF IK 0x01C2 2400 0x01C2 27FF IK LRADC 0x01C2 2800 0x01C2 2BFF IK AD DA 0x01C2 2C00 0x01C2 2FFF IK 0x01C2 3000 0x01C2 33FF CPU Control 0x01C2 3400 0x01C2 37FF IK SID 0x01C2 3800 0x01C2 3BFF IK A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd
149. 2 0x1 level 2 Level3 0x1 level 3 highest priority 1 0 R W 0x0 IRQ48_PRIO IRQ 48 Priority Set priority level for IRQ bit 48 Level0 0x0 level 0 lowest priority A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Offset 0x8C Register Name INTC_SRC_PRIO_REG3 Levell 0x1 level 1 Level 0x1 level 2 Level3 0x1 level 3 highest priority 13 4 30 Interrupt Source Priority 4 Register Default 0x00000000 Offset 0x90 Register Name INTC_SRC_PRIO_REG4 Read Wr ite Bit Default Hex Description 31 30 R W 0x0 IRQ79_PRIO IRQ 79 Priority Set priority level for IRQ bit 79 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 29 28 R W 0x0 IRQ78_PRIO IRQ 78 Priority Set priority level for IRQ bit 78 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 27 26 R W 0x0 IRQ77_PRIO IRQ 77 Priority Set priority level for IRQ bit 77 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 25 24 R W 0x0 IRQ76_PRIO IRQ 76 Priority Set priority level for IRQ bit 76 Level0 0x0 level 0 lowest priority Levell Ox1 l
150. 2 n The divider is 1 2 4 8 15 4 CLK DIV RATIO M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 24 SD2 Clock Default 0x00000000 Offset 0x90 Register Name SD2_SCLK_CFG_REG Read Wr Default ae Bit Description ite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 25 24 R W 0x0 EE 01 PLL6 10 PLLS 11 7 23 18 CLK_DIV_RATIO_N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 25 SS Clock Default 0x00000000 Offset 0x9C Register Name SS_SCLK_CFG_REG Read Wr Default SC Bit Description ite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 70 Ou 7 Allwinner Technology CO Ltd A13 Clock Source Select 00 OSC24M 01 PLL6 10 PLL5
151. 286 21 2 DEFE Block Dia Sram ssoi niana nine dede NEESS 286 21 3 RE RR e le 286 27 3 1 Ee 287 27 3 2 Eg ra case 287 27 3 3 ae et et cee ee ee eee eect 288 27 3 4 Mu 4 a E 289 27 3 5 CSC Color Space Conversion Description 289 27 3 6 DEFE Surte Input Formats see 289 27 3 7 Image Data Memory Mapping 290 21 4 DEFE Register Listerine Te dende 293 2150 DEFE Ee EE 295 27 5 1 DEFE al aia Serer rn rere en nT teeter me errno nmr ee Tt ree 295 27 5 2 EE EE 295 27 5 3 DEFE BYPASS Eee 296 27 5 4 DEFE_AGTH_SEL_REG eee 296 27 5 5 DEFE LINT COTRU RES 297 27 5 6 DEFE EE EE 297 27 5 7 DEFE BUF ADDR FE SR RE CR 297 27 5 8 DEFE_BUF_ADDR2_REG EE 298 27 5 9 DEFE AFIELD CTRL RES etes 298 75107 DEFE TB OFFO EE 298 27501 DEFE WE Eege 299 27 5 12 MERETE PE ee nrn 299 27 5 13 DEER LINE STROO REG vats iicastunciasnsenidanctqnaiqentenntnantaesbanndensienntneainentuddunabendtanidacl 299 27514 DERE LINE REG 300 275 158 DEFE LINESTRD2 REG svekke 300 27 5 16 ERE NAT REN en 300 275 17 DEFE MER Even 302 21 518 BERRE OP FT PE Su nn ee Ne 302 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 15 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 27519 DEFE INT EN REG epee ee en eebe 303 750 DEFE INT_STATUS RE sioria nonias oniani 304 tel DEFE STATUS Eeer 304 27522 DEFE CSC GOEFOO REG wack nA 305 27 5 23 EEE 305 27 5 24 DERE Ek COEFOR REG em ee eee eee 306 27 5 25 DEFE CSC COEB
152. 3 34 Declaration A13 User Manual V 1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 22 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 1 A13 Introduction 1 1 Features CPU ARM Cortex A8 Core 32KB I Cache 32KB D Cache 256KB L2 Cache Using NEON for video audio and graphic workloads eases the burden of supporting more dedicated accelerators across the SoC and enables the system to support the standards of tomorrow RCT JAVA Accelerations to optimize just in time JIT and dynamitic adaptive compilation DAC and reduces memory footprint up to three times GPU 3D Graphic Engine Support Open GL ES 1 1 2 0 and Open VG 1 1 VPU Video Decoding FULL HD gt Support all popular video formats including VP6 8 AVS H 264 H 263 MPEG 1 2 4 etc gt Support 1920 1080 30fps in all formats Video Encoding gt Support encoding in H 264 MP format gt Upto 1920 1080 30fps Display Processing Ability Four moveable and size adjustable layers Support multi format image input Support image enhancement processor Support Alpha blending anti flicker Support Hardware cursor Support output color correction luminance hue saturation etc Display Output Ability A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 23 Jau 8 2013 Allwinner Technology CO Ltd A13 Flexible LCD interface CPU Sync RGB I
153. 3 highest priority 3 2 R W 0x0 IRQ33_PRIO IRQ 33 Priority Set priority level for IRQ bit 33 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Offset 0x88 Register Name INTC_SRC_PRIO_REG2 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority IRQ32 PRIO IRQ 32 Priority Set priority level for IRQ bit 32 1 0 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 13 4 29 Interrupt Source Priority 3 Register Default 0x00000000 Offset 0x8C Register Name INTC_SRC_PRIO_REG3 Read Wr Default Bit Description ite Hex IRQ63 PRIO IRQ 63 Priority Set priority level for IRQ bit 63 31 30 R W 0x0 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level 0x1 level 2 Level3 0x1 level 3 highest priority IRQ62_PRIO IRQ 62 Priority Set priority level for IRQ bit 62 29 28 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ61 PRIO IRQ 61 Priority Set priority level for IRQ bit 61 27 26 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority
154. 3 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 148 Jau 8 2013 Ou Allwinner Technology CO Ltd 0x0 Linear Mode Ox1 IO Mode 0x2 Horizontal Page Mode 0x3 Vertical Page Mode A13 DDMA SRC DRQ TYPE Dedicated DMA Source DRQ Type 0x0 SRAM memory 0x1 SDRAM memory 0x2 0x3 NAND Flash Controller NFC 0x4 USBO Ox5 0x6 Ox7 0x8 0x9 SPI RX OxA OxB Security System RX OxC OxD OxE OxF Ox10 Ox11 0x12 Ox13 0x14 Ox15 Ox16 Ox17 Ox18 0x19 Ox1A Ox1B SPIO RX Ox1C Ox1D SPR RX Ox1E Ox1F 4 0 R W 0x0 14 4 8 Dedicated DMA Source Start Address Register N 0 7 Offset 0x300 N 0x20 0x4 Register Name DDMA_SRC_ADDR_REG N 0 1 52 3 4 5 6 7 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd Read Wr Default ite Hex Bit Description A13 DDMA SRC START ADDR Dedicated DMA Source Start Address 31 0 R W x 14 4 9 Dedicated DMA Destination Start Address Register N 0 7 Offset 0x300 N 0x20 0x8 N 0 1 2 3 4 5 6 7 Register Name DDMA_DEST_ADDR_REG Read Wr Default Bit i Description ite Hex DDMA_DST_START_ADDR 31 0 R W x a Dedicated DMA Destination Start Address 14 4 10 D
155. 31 0 R W 0x0 start of the first line in next tile here next tile is in vertical direction In non tile based type The stride length is the distance from the start of one line to the start of the next line 27 5 16 DEFE_INPUT_FMT_REG Offset 0x4C Register Name DEFE_INPUT_FMT_REG Bit E Pu Description ite Hex 31 17 BYTE SEQ Input data byte sequence selection 16 R W 0x0 0 P3P2P1P0 word 1 POP1P2P3 word 15 13 SCAN_MOD Scanning Mode selection 12 R W 0x0 0 non interlace 1 interlace 11 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 300 Jau 8 2013 Ou Allwinner Technology CO Ltd DATA_MOD Input data mode selection 000 non tile based planar data 001 interleaved data 010 non tile based UV combined data 100 tile based planar data 110 tile based UV combined data other reserved 10 8 R W 0x0 A13 7 DATA_FMT Input component data format In non tile based planar data mode 000 YUV 4 4 4 001 YUV 4 2 2 010 YUV 4 2 0 O11 YUV 4 1 1 100 CSI RGB data 101 RGB888 Other Reserved In interleaved data mode 000 YUV 4 4 4 001 YUV 4 2 2 101 ARGB8888 Other reserved 6 4 R W 0x0 In non tile based UV combined data mode 001 YUV 4 2 2 010 YUV 4 2 0 011 YUV 4 1 1 Other reserved In tile based planar data mode 001 YUV 4 2 2 010 YUV 4 2 0 011 YUV 4 1 1 Other Reserved In tile based UV combined data
156. 31 11 CPU MAX FREQ 125 10 0 R W D CPU max frequency if cpuvdd 1 25v unit MHz This register can only be written if the DVFS function is disabled A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 42 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 5 3 28 PMU VF Table Register 12 Offset OxBO Register Name PMU_VF_TABLE_REG12 Read Wr Default er Bit Description ite Hex 31 11 CPU_MAX_FREQ_ 130 10 0 R W x CPU max frequency if cpuvdd 1 3v unit MHz This register can only be written if the DVFS function is disabled 5 3 29 PMU VF Table Register 13 Offset 0xB4 Register Name PMU VF TABLE REG13 Read Wr Default aa Bit Description ite Hex 31 11 l CPU_MAX_FREQ_ 135 10 0 R W D CPU max frequency if cpuvdd 1 35v unit MHz This register can only be written if the DVFS function is disabled 5 3 30 PMU VF Table Register 14 Offset OxB8 Register Name PMU VF TABLE REG14 Read Wr Default a Bit Description ite Hex 31 11 l CPU_MAX_FREQ_140 10 0 R W x CPU max frequency if cpuvdd 1 4v unit MHz This register can only be written if the DVFS function is disabled 5 3 31 PMU VF Table Register 15 Offset OxBC Register Name PMU VF TABLE REG15 Read Wr Default aan Bit Description ite Hex 31 11 l CPU_M
157. 359 29 3 22 POON BASIGL REG xi 359 25 323 TCON BASIC2 REG vira aa ha kakene ae 359 RC PE e 360 NN PN NN 360 20326 CONT BASICS REG used 360 295327 TCONI 1O POL REG siene 361 29 3 28 TCONI IO TEAMLREGS inaina ainan aa kanakana aaa Eonia nannies 361 CONS EE 362 20330 POON CEU COEF REG cio NN NN ee 362 29 3 31 TOON FILL CTL REG SSSR SR RP 363 293 32 TCONI FILL TR ee ec eels dean dct tee eee 363 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 18 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 9350 TCONI FILE END REG ener ere ere ere nee eee eee eee ene eee ee eer 363 29 3 34 TCON I_ FILL DATA EN mee re ne rene er ere er ee eee ee ee ee er eee eee ee eee 363 30 Image Enhancement Processor IEP ciccscisscscsssscsssessssescsnsecesccesesssesnssssseseseccsvenssseseseasscssaesssnsssrasesesensesns 364 SOL TONN 364 30 2 JEP Register Description atic irae ikie re ae einen eee intents ee nee eevee 364 30 2 1 General Control Register E 364 30 2 2 DRC Size Setting Register eege 364 30 2 3 DRG Gontrol Register eege 365 30 2 4 DRC External LGC Start Address Register esccesceseeeseeeseeseeeeeseeeseeseaeeeaeeens 365 30 2 5 DRC NN 365 30 2 6 DRC Window Position Registero EE 366 30 2 7 DRC Window Position Register vc 2cn ee N 366 30 2 8 DRC Write Back Control Register shine 367 30 2 9 DRC Write Back Address Register 2222 stunt non nn nt etaient lets 367 30 2 10 DRC Wr
158. 5 Security System FIFO Control Status Register c ccccsccecssceeeeceeeeseeessteeeseees 376 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 19 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 31 4 6 Security System Interrupt Control Status Register 377 31 4 7 Security System Message Digest n Register 377 31 4 8 Security System AX FIFO Register 5 Re 378 31 4 9 Security System TX FIFO Register sea IR Rs nn 378 31 5 Security System Clock Requirement mmmmrnvvvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnennnnnn 378 32 Security ID ssccssscsscscesssscssescsscscsctcectsestsccsssstssstsesssecsssstcsstseacs cnsesssesssesssssesssscssssescsssssesssssssesssescsssccsaesssccsaeczs 379 Diss ONE 379 322 security ID Register List ER ce a ee 379 32 3 Security ID Register Descriptions cccccssssesessscsecscsnasstasscesscaccnassdasssesssscsnassdasssesesscsvassvassscesenees 379 32 3 1 SID R a Sy 0 Registeren ae aane as 379 32 3 2 SID Root Key Re 379 32 3 3 SID Root E 379 32 3 4 SID Root e 380 32 3 5 SID Program Control Register ccc ec ee ee nasa 380 33 Ke OO e IT E 381 33 12 OVERVIEW ES nn en eo ee E een Sie ea eens 381 33 2 Port Contreuration ET EE 381 33 3 Port Register List ste ies Tiered Eege 383 3524 der GELEET eege EE 384 33 4 1 PB Configure SR 384 33 4 2 PE Configure Register E 385 33 4 3 PB Ree 385 33 4 4 PB Configure Register once nts
159. 5 14 R W 0x0 IRQ39_PRIO IRQ 39 Priority Set priority level for IRQ bit 39 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou Allwinner Technology CO Ltd Offset 0x88 Register Name INTC_SRC_PRIO_REG2 A13 Level3 Ox1 level 3 highest priority 13 12 R W 0x0 IRQ38_PRIO IRQ 38 Priority Set priority level for IRQ bit 38 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 11 10 R W 0x0 IRQ37_PRIO IRQ 37 Priority Set priority level for IRQ bit 37 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 9 8 R W 0x0 IRQ36_PRIO IRQ 36 Priority Set priority level for IRQ bit 36 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 7 6 R W 0x0 IRQ35_PRIO IRQ 35 Priority Set priority level for IRQ bit 35 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 5 4 R W 0x0 IRQ34_PRIO IRQ 34 Priority Set priority level for IRQ bit 34 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level
160. 8 13 Interrupt OG I EE EM ss ite 110 Bu HOV CLV NN 110 13 2 Toterrupt Sourceuunsansr re re 110 13 3 Interrupt Register ET 112 13 4 Interrupt Register Description wsiisis5 525 icssinnsass ines tetsnnksasb vice ste ANNERES 113 13 4 1 Interrupt Vector Register Default 0x00000000 ornrrrnnnnnrrrnnnrnnrrnnnrrnrrnnnrrnrrnnnrenn 113 13 4 2 Interrupt Base Address Register Default 0x00000000 ranvrnrenvrnnnnrnnrnnrnnnnvnnnenn 114 13 4 3 Interrupt Protection Register Default 0x00000000 errrnvrvennrnnrrnnnrnnrrnnnrrnrrnnnrenn 114 13 4 4 NMI Interrupt Control Register Default 0x00000000 sseesseeseseseeeeerrereeeeee 114 13 4 5 Interrupt IRQ Pending Register 0 Default OsO0OO00O000 115 13 4 6 Interrupt IRQ Pending Register 1 Default OsO0OO00O000 115 13 4 7 Interrupt IRQ Pending Register 2 Default 0Ox00000000 115 13 4 8 Interrupt FIQ Pending Clear Register 0 Default 0x00000000 eee 115 13 4 9 Interrupt FIQ Pending Clear Register 1 Default 0x00000000 eee eeeeeeee 115 13 4 10 Interrupt FIQ Pending Clear Register 2 Default 0x00000000 arvrnnvvrrnrnnnvnnnnnn 116 13 4 11 Interrupt Select Register 0 Default 0x00000000 eee eeeeeeeeeeeteeeeeeeeeneeteeeetaee 116 13 4 12 Interrupt Select Register 1 Default 0x00000000 ee eee cece eeeeeeeeeeeeeeeeeeeeeneeeaes 116 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserv
161. 8 6 4 39 Mali 400 Clock Register Default 0x00000000 rrrerrnrnrrnnrnrrrnverrnnnrrrnrnnrrnverrnnnerenn 78 6 4 40 MBUS Clock Control Default 0x00000000 rrrrnnrerrnrnrrnnvnnrrnverrnnrerrnrnnrrnrerennnernn 79 6 4 41 IEP Clock Control Default 0x00000000 rrnrrrrrnrnrrrrverrnrnnrrnrnnrrnverrnnerrnrerrrnnerennnn 80 Ta System Control sssesisscciecedesssesdsevesescevessecstesshecessestacegsssteesdcaotedscasstesstossvecseassuocstasesecscavaucestecsessesvstecsseosesused 81 TON cece eee eee ee ese pee ee vee eeen 81 1 2 System Control Register Fist eA bek debuten 81 7 3 System Control Register Description sisi 81 7 3 1 SRAM Configuration Register 0 Default OX7FFFFFFF sessies 81 7 3 2 SRAM Configuration Register 1 Default 0Ox00001000 82 6 CPU COMI ME 83 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 6 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 8 1 CPU Register List nu nese tidas Sak be asa et vane sate bach kane bibid ie 83 8 2 CPU Control Register Descriptions e nn aE eae 83 8 2 1 CPU Control Register Default OxO0OO00O0O02 83 9 SDRAM COmtrole rises sisisccscdecsssssdsecsedsttsoustecssassvodesccatdstessantesesenscssnseeadskosensentesssucsedunccasobonscssessosswsesateaeses 84 OL e 84 10 Pulse Width Modulator PWMhu ucneiiesstssennsissnsnssensakenskskanensssnsanendrsnansanenskanedennsnensnsnensntekenesnnenekeenens 85
162. 8 17 16 P07 P06 P05 P04 P03 P02 POI POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 8bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3 P2 Pl PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Offset DE on chip SRAM block 0x4000 0x57FF Read Wri Default E Bit Description te Hex Internal frame buffer pixel pattern 31 00 R W UDF Specify the color displayed for each of the internal frame buffer pixels 28 5 41 Internal Frame Buffer Mode Palette Table Address Pipe0 0x5000 0x53FF Pipe palette table Pipe1 0x5400 0x57FF Read Wri Default 2 Bit Description te Hex A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 343 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Alpha value The following figure shows the RAM array used for internal frame buffer mode and the corresponding colors output Output color On chip SRAM array 2bpp mode a2 R2 G2 B2 Internal frame buffer bit7 bit0 av RO Go BO Palette table 3 2 0 2 oi R2 G2 B2 Color0 ao RO GO BO D a3 R3 G3 B3 Color1 a1 RI G1 B1 a2 Ri G2 B2 1 3 2 E oi R2 G2 B 3 3 0 1 a3 R3 G3 B3 Color254 Q 254 R254 G254 B254 al Ri GU BI Color255 255 R255 G255 B255 On chip SRAM for internal 1 RI 1 B1 frame buffer g i ao RO GO BO a3 R3 G3 B3 a3 R3 G3 B3 28 5 42 Gam
163. 8 bits 01 192 bits 10 256 bits 9 8 R W 0 11 Reserved SS Operation Direction 0 Encryption 7 R W 0 1 Decryption SS Method 000 AES 001 DES 010 Triple DES 3DES 011 SHA 1 100 MD5 101 PRNG 6 4 R W 0 Others Reserved SHA 1 MD5 Data End bit Write 1 to tell SHA 1 MD5 engine that the text data ends If there is some data in FIFO the engine will fetch these data and process them After finishing message digest this bit is cleared to 0 by hardware and message digest can be read out from digest registers 2 R W 0 Notes It is only used for SHA 1 MD5 engine PRNG start bit In PRNG one shot mode write 1 to start PRNG After generating one 1 R W 0 group random data 5 words this bit is cleared to 0 by hardware SS Enable A disable on this bit overrides any other block and flushes all FIFOs 0 R W 0 0 Disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 375 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 Enable 31 4 2 Security System Key n Register Offset 0x04 4 n Register Name SS_KEY n Default Value 0x0000 0000 Bit Read Write Default Description 31 0 R W 0 Key n Input Value n 0 7 PRNG Seed n n 0 5 31 4 3 Security System IV n Register Offset 0x24 4 n Register Name SS IV n Default Value 0x0000 0000 Bit
164. AX IX X I AY Y Y I if AX or AY great than threshold as a dual touch thus as a single touch MEASURE X Position O X Y AW TOUCH MW MW ed lt X POSITION AAN JM O x MEASURE v X Position Figure25 11 Dual Touch X Position Measurements 25 4 6 Touch Pressure Measurement The pressure applied to the touch screen by a pen or finger to filter unavailable can also be also be measurement with the controller using some simple calculations The contact resistance between the X and Y plates is measured providing a good indication of the size of the depressed area and therefore the applied pressure The area of the spot that is touched is proportional to the size of the object touching it The size of this resistance Riouch can be calculated using two different methods First Method The first method requires the user to know the total resistance of the X plate tablet RX Three touch screen conversions are required measurement of the X position XPOSITION Y input measurement of the X input with the excitation voltage applied to Y and X Z1 measurement and measurement of the Y input with the excitation voltage applied to Y and X Z2 measurement These three measurements are illustrated in Figure 4 The controller have two special ADC channel settings that configure the X and Y switches for the Z1 and Z2 measurements and store the results in the Z1 and Z2 result re
165. AX_FREQ_145 10 0 R W x CPU max frequency if cpuvdd 1 45v unit MHz This register can only be written if the DVFS function is disabled 5 3 32 PMU VF Table Register 16 Offset OxCO Register Name PMU VF TABLE REG16 Read Wr Default a Bit Description ite Hex 31 11 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 43 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 CPU MAX FREQ 150 10 0 CPU max frequency if cpuvdd 1 5v unit MHz This register can only be written if the DVFS function is disabled 5 3 33 PMU VF Table Register 17 Offset OxC4 Register Name PMU VF TABLE REG17 Read Wr Default Bit Description ite Hex 31 11 CPU MAX FREQ 155 10 0 R W D CPU max frequency if cpuvdd 1 55v unit MHz This register can only be written if the DVFS function is disabled 5 3 34 PMU VF Table Register 18 Offset USCH Register Name PMU VF TABLE REG18 Read Wr Default S Bit i Description ite Hex 31 11 CPU_MAX_FREQ_ 160 10 0 R W D CPU max frequency if cpuvdd 1 6v unit MHz This register can only be written if the DVFS function is disabled 5 3 35 PMU VF Table Valid Register Offset OxCC Register Name PMU_VF_TABLE_VALID_REG Read Wr Default SE Bit Description ite Hex 31 16 R W 0x0 15 6 VF_TABLE_18_VALID PMU V F Ta
166. Allwinner Technology All Rights Reserved 90 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 001 2 010 4 O11 8 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMRO CLK SRC Timer 0 Clock Source 00 01 OSC24M 10 PLL6 6 11 0x0 TMRO_RELOAD Timer 0 Reload 0 No effect 1 Reload timer 0 Interval value After the bit is set it can not be written again before it s cleared automatically 0x0 TMRO_EN Timer 0 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcycles the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note Time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 4 ASYNC Timer 0 Interval Value Register Offset 0x14 Register Name ASYNC_TMRO_INTV_VALUE_REG Read Wr Default Bit Description ite Hex TMRO_INTV_VALUE 31 0 R W x Timer 0 In
167. B Y Cb Cr output to memory Pass raw data direct to memory All data transmit timing can be adjusted by software Luminance statistical value 26 2 CSI Block Diagram FIFO 2 i PCLK CSI HS FIFO 1 Control VS Module DMA System BUS CS Data 7 0 Figure 26 1 CSI Block Diagram 26 3 CSI Register List Module Name Base Address CSI 0x01C00900 Register Name Offset Description CSI EN REG 0x0000 CSI Enable Register CSI_CFG_REG 0x0004 CSI Configuration Register CSI CPT CTRL REG 0x0008 CSI Capture Control Register CSI FIFOO BUF A ADDR REG 0x0010 CSI FIFOO Buffer A Register CSI FIFO0 BUF B ADDR REG 0x0014 CSI FIFOO Buffer B Register CSI FIFO1 BUF A ADDR REG 0x0018 CSI FIFO1 Buffer A Register CSI FIFO1 BUF B ADDR REG 0x001C CSI FIFO1 Buffer B Register CSI BUF CTRL REG 0x0028 CSI Buffer Contrl Register A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 276 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 CSI STA REG 0x002C CSI Status Register CSL INT EN REG 0x0030 CSI Interrupt Enable Register CSI INT STA REG 0x0034 CSI Interrupt Status Register CSI WIN CTRL W REG 0x0040 CSI Window Width Control Register CSI WIN CTRL H REG 0x0044 CSI Window Height Control Register CSI BUF LEN REG 0x0048 CSI Buffer Length Register 26 4 CSI Register
168. B1 Clock Divide Ratio Default OsOOO00O0O00 64 6 4 16 AXI Module Clock Gating Default Ox00000000 65 6 4 17 AHB Module Clock Gating Register 0 Default OsO0O0OO0O0O0O0D 65 6 4 18 AHB Module Clock Gating Register 1 Default OsOO0OOO0O0O0 66 6 4 19 APBO Module Clock Gating Default 0x00000000 rrnrrrrenrnrrnnrrrrnrnrrrnrnnrrrrerrnnnernn 67 6 4 20 APB1 Module Clock Gating Default 0x00000000 rrnrrrrrnvnrrnnvenennnrrrnrnnrrnrerrnnnernn 67 6 4 21 NAND Clock Default 0x00000000 VU 68 6 4 22 SDO Clock Default 0x00000000 UV 68 6 4 23 SD1 Clock Default 0x00000000 vs 69 6 4 24 SD2 Clock Default 0x00000000 VU 70 6 4 25 SS Clock Default OsOOOO0O0O0O0 enee 70 6 4 26 SPIO Clock Default OxvOOOOOO00 enere 71 6 4 27 SPI1 Clock Default OxOO0O0O0O000 ennen 71 6 4 28 SPI2 Clock Default OxOO0O0O0O000 72 6 4 29 IR Clock Default OsO0O0OO00O0O0 nnee 73 6 4 30 USB Clock Default Ox00000000 Us 13 6 4 31 DRAM CLK Default 0x00000000 nne 74 6 4 32 DE BE Clock Default 0x00000000 ssis sssrin nas 75 6 4 33 DE FE Clock Default OxOOO0O0OO0O0 nee 75 6 4 34 LCD CH1 Clock Default 0x00000000 rrnrrrrnrnnrnvenenrnrrrnrnnrrnrerrnnnerrnnnrrrnnerrnnnernnn 76 6 4 35 CSI Clock Default 0x00000000 4 77 6 4 36 VE Clock Default OsOOOO0O0O0O0 eneee 77 6 4 37 Audio Codec Clock Default OxO0O0O0O0O0O00 78 6 4 38 AVS Clock Default 0x00000000 Us 7
169. C SHA1 MD5 Message Digest 0 PRNG Daat SS_MD1 0x50 SHA1 MD5 Message Digest 1 PRNG Daa SS_MD2 0x54 SHA1 MD5 Message Digest 2 PRNG Data2 SS_MD3 0x58 SHA1 MD5 Message Digest 3 PRNG Data3 SS_MD4 0x5C SHA1 MD5 Message Digest 4 PRNG Data4 SS_RXFIFO 0x200 RX FIFO input port SS_TXFIFO 0x204 TX FIFO output port 31 4 Security System Register Description 31 4 1 Security System Control Register Register Name SS_CTL Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 28 AES DES 3DES key select 0 Select input SS KEYx Normal Mode 1 Select SID RKEYx from Security ID 2 Reserved 3 10 Select internal Key n n from 0 to 7 27 24 R W 0 Others Reserved 18 16 R D Reserved PRNG generator mode 0 One shot mode 15 R W 0 1 Continue mode IV Steady of SHA 1 MDS constants 0 Constants 14 R W 0 1 Arbitrary IV A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 374 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Notes It is only used for SHA 1 MD5 engine If the number of IV word is beyond of 4 Counter 0 register is used for IV4 SS Operation Mode 00 Electronic Code Book ECB mode 01 Cipher Block Chaining CBC mode 10 Counter CNT mode 13 12 R W 0 11 Reserved Counter Width for CNT Mode 00 16 bits Counter 01 32 bits Counter 10 64 bits Counter 11 10 R W 0 11 Reserved Key Size for AES 00 12
170. D n Pull up down Select n 16 27 21 1 2i 00 Pull up down disable 01 Pull up enable G 0 11 R W 0x0 10 Pull down 11 Reserved 33 4 28 PE Configure Register 0 Register Name PE CFGO Offset 0x90 Default Value 0x0000 0000 Bit Read Write Default Description 31 PE7 Select 000 Input 001 Output 010 011 CSL D3 100 SDC2 D3 101 30 28 R W 0 110 111 27 PE6 Select 000 Input 001 Output 010 011 CSI_D2 100 SDC2_D2 101 26 24 R W 0 110 111 23 PES Select 000 Input 001 Output 010 011 CSI D1 100 SDC2 Di 101 22 20 R W 0 110 111 19 PE4 Select 000 Input 001 Output 010 011 CSI_DO 100 SDC2 DO 101 18 16 R W 0 110 111 15 PE3 Select 000 Input 001 Output 010 011 CSL VSYNC 100 SP MISO 101 14 12 R W 0 110 111 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 397 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 11 PE2 Select 000 Input 001 Reserved 010 011 CSI HSYNC 100 SPI2_MOSI 101 10 8 R W 0 110 111 7 PE1 Select 000 Input 001 Reserved 010 011 CSI MCLK 100 SPI2_CLK 101 6 4 R W 0 110 EINT15 111 PEO Select 000 Input 001 Reserved 010 011 CSL PCLK 100 SPI2_CSO 101 2 0 R W 0 110 EINT14 111
171. DDR REG Read Wr Default SC Bit Description ite Hex NDMA_DST_ADDR 31 0 R W x Normal DMA Destination Address 14 4 6 Normal DMA Byte Counter Register Default 0x00000000 Offset 0x 100 N 0x20 0xC N 0 1 2 3 4 5 6 7 Register Name NDMA BC REG Read Wr Default Sa Bit i Description ite Hex 31 24 NDMA BC 23 0 R W x Normal DMA Byte Counter Note If ByteCounter 0 DMA will transfer no byte The maximum value is 128k 14 4 7 Dedicated DMA Configuration Register Default 0x00000000 Offset 0x300 N 0x20 N 0 1 2 3 4 5 6 7 Register Name DDMA CFG REG Read Default Bit Description Write Hex DDMA_LOAD DMA Loading 31 R W 0x0 If set to 1 DMA will start and load the DMA registers to the shadow registers The bit will hold on until the DMA finishes It will be cleared automatically A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 146 Ou 7 Allwinner Technology CO Ltd A13 Set 0 to the bit will stop the corresponding DMA channel and reset its state machine 30 0x0 DDMA_BSY_STA DMA Busy Status 0 DMA idle 1 DMA busy 29 R W 0x0 DDMA CONTI MODE EN DMA Continuous Mode Enable 0 Disable 1 Enable 28 27 26 25 R W 0x0 DDMA_DST_DATA_WIDTH DMA Destination Data Width 00 8
172. D_STATUS 10 R W 0x0 Register ready load interrupt status LINE_STATUS 9 R W 0x0 RR Line interrupt status 8 WB_STATUS 7 R W 0x0 Write back end interrupt status 6 0 27 5 21 DEFE_STATUS_REG Offset 0x68 Register Name DEFE_STATUS_REG Read Wr Default 2 Bit Description ite Hex 31 29 LINE_ON_SYNC 28 16 R 0x0 Line number when sync reached WB_ERR_SYNC 15 R W 0x0 Sync reach flag when capture in process WB_ERR_LOSEDATA 14 R W 0x0 Lose data flag when capture in process 13 WB_ERR_STATUS write back error status 12 R 0x0 0 valid write back 1 un valid write back This bit is cleared through writing 0 to reset start bit in frame control register COEF_ACCESS_STATUS Fir coef access status 0 scaler module can access fir coef RAM 11 R 0x0 1 CPU can access fir coef ram This bit must be 1 before CPU accesses fir coef RAM When this bit is 1 scaler module will fetch 0x00004000 from RAM 10 6 LCD_FIELD 5 R 0x0 LCD field status 0 top field A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 304 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 bottom field DRAM STATUS Access dram status 4 R 0x0 0 idle 1 busy This flag indicates whether DEFE is accessing dram 3 CFG_PENDING Register configuration pending 0 no pending 2 R 0x0 1 configuration pending
173. Description 14 4 1 DMA IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name DMA IRQ EN REG Bit Read Wr Default Description A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 137 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd ite Hex A13 31 R W 0x0 DDMA7_END_IRQ_EN Dedicated DMA 7 End Transfer Interrupt Enable 0 Disable 1 Enable 30 R W 0x0 DDMA7_HF_IRQ EN Dedicated DMA 7 Half Transfer Interrupt Enable 0 Disable 1 Enable 29 R W 0x0 DDMA6 END IRQ EN Dedicated DMA 6 End Transfer Interrupt Enable 0 Disable 1 Enable 28 R W 0x0 DDMA6_HF_IRQ EN Dedicated DMA 6 Half Transfer Interrupt Enable 0 Disable 1 Enable 27 R W 0x0 DDMA5 END IRQ EN Dedicated DMA 5 End Transfer Interrupt Enable 0 Disable 1 Enable 26 R W 0x0 DDMAS_HF_IRQ EN Dedicated DMA 5 Half Transfer Interrupt Enable 0 Disable 1 Enable 23 R W 0x0 DDMA4 END IRQ EN Dedicated DMA 4 End Transfer Interrupt Enable 0 Disable 1 Enable 24 R W 0x0 DDMA4 HF IRQ EN Dedicated DMA 4 Half Transfer Interrupt Enable 0 Disable 1 Enable 23 R W 0x0 DDMA3 END IRQ EN Dedicated DMA 3 End Transfer Interrupt Enable 0 Disable 1 Enable 22 R W 0x0 DDMA3_HF_IRQ EN Dedicated DMA 3 Half Transfer Interrup
174. DoneHead 31 4 When a TD is completed HC writes the content of HcDoneHead to the NextTD field of the TD HC then overwrites the content of HcDoneHead with the address of this TD This is set to zero whenever HC writes the content of this register to HCCA It also sets the WritebackDoneHead of HclnterruptStatus 3 0 R R 0x0 HcDoneHead 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED bit 0 to bit 3 must be zero in this field 22 6 14 HcFmInterval Register Offset 0x434 Register Name HcFmInterval Register Default Value 0x2EDF Read Write Bit HCD HC Default Description A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 232 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 FramelntervalToggler 31 R W R 0x0 HCD toggles this bit whenever it loads a new value to Framelnterval FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling 30 16 R W R 0x0 overrun The field value is calculated by the HCD 15 14 0x0 Reserved Framelnterval This specifies the int
175. EBE OCBCOEF REG B V component 0x9F8 Read Wri Default Description te Hex OC BCOEF the B coefficient DEBE Output Color B Coefficient Register the value equals to coefficient 2 28 5 36 Offset Ox9FC DEBE Output Color B Constant Register Register Name DEBE_OCBCONS_REG OC_BCONS the B constant the value equals to coefficient 2 28 5 37 DE HWC Pattern Memory Block Function 1bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 Pll P1O POO P08 PO7 PO6 POS P04 PO3 PO2 POI POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 2bpp Bit A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 340 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 31 30 29 28 27 26 25 24 023 22 21 20 19 18 17 16 P15 P14 P13 P12 P11 P10 P09 P08 P07 P06 POS P04 P03 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 4bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P07 P06 P05 P04 P03 P02 POI POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 8bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3 P2 Pl PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Offset DE HW cursor patte
176. EFE will start a new frame process 15 12 11 R W 0x0 OUT_CTRL DEFE output control 0 enable DEFE output to DEBE 1 disable DEFE output to DEBE If DEFE write back function is enabled DEFE output to DEBE isn t A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 295 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 recommended 10 3 R W 0x0 WB_EN Write back enable 0 Disable 1 Enable If output to DEBE is enabled the writing back process will start when write back enable bit is set and a new frame processing begins The bit will be self cleared when writing back frame process starts R W 0x0 REG_RDY_EN Register ready enable 0 not ready 1 registers configuration ready Just as filter coefficients configuration in order to ensure the display to be correct the correlative display configuration registers are buffered too and programmers also can change the value of correlative registers in any time When the registers setting is finished the programmer should set the bit if the new configuration is needed in next scaling frame When the new frame starts the bit will also be self cleared 27 5 3 DEFE_BYPASS_REG Offset 0x8 Register Name DEFE_BYPASS_REG Bit Read Wr ite Default Hex Description 31 2 R W 0x0 CSC_BYPASS
177. EL1 26 16 R W 0x0 AXICLK level 1 15 11 AXI_CLK_LEVELO 10 0 R W 0x0 AXICLK level 0 5 3 5 PMU AXI Clock Range Register1 Offset 0x24 Register Name PMU_AXI_AUTO_SWT_REG1 8 Read Wr Default DN Bit Description ite Hex 31 27 AXI_CLK_LEVE3 26 16 R W 0x0 AXICLK level 3 15 11 AXI_CLK_LEVEL2 10 0 R W 0x0 AXICLK level 2 5 3 6 PMU DVFS Control Register 3 Offset 0x18 Register Name PMU_DVFS_CTRL_REG3 Read Wr Default SSC Bit Description ite Hex 31 0 5 3 7 PMU DVFS TimeOut Control Register Default 0x00000027 Offset Ox1C Register Name PMU_DVFS_TIMEOUT_CTRL_REG Read Wr Default Bit Description ite Hex 31 6 DVFS_TIMEOUT 5 0 R W 0x27 DVES operate on TWI timeout cycles in TWI peripheral clock 0 1 cycle A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 35 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Ox3F 64 cycles 5 3 8 PMU IRQ En Register Offset 0x40 Register Name PMU IRQ EN REG Read Wr Default SS Bit Description ite Hex 31 13 VOLT DET ERR IRQ EN Voltage Detect Error IRQ Enable 12 R W 0x0 0 Disable 1 Enable DVFS_CLK_SWTH_ERR_IRQ_EN DVFS Clock Switch Operation Error IRQ Enable 11 R W 0x0 0 Disable 1 Enable DVFS_VOLT_CHANGE_ERR_EN DVFS Voltage Change Error Enable 10 R W 0x0 0 Disable 1 Enable DVFS SPD DET ERR IRQ EN DVES Speed Detect Error
178. EUS Ee 306 27526 DEPE CSO GOEFIO0 RE Guss 306 2795 27 DEFE CSG GEL REG eee 306 27 5 28 DEFE CSC COEF 2 RE ananas ententes 307 21520 DEFE CSC GOEFIS REG SE 307 27530 DEFE CSC COEF2ZO REG uddannet 307 eV DEFE CSC CEPT REG E 307 52 DEFE CSO COEF22 EN 307 271533 DEFE CSC GOEF29 REG rao el 308 27534 DEFE WB LINESTRD_EN REG vasse 308 27 5 35 DEFE WB LINESTRDO REG E 308 27506 DEFE CHO INSIZE RER ne ne nn nn tdistsietd 308 fic DEFE CHO OUISIZE REG nce 309 27538 DEFE CHO HORZFACT REG sure kake 309 27 5 39 DEFE CO ER TNT PES 2 309 27 5 40 DEFE CHO HORZPHASE REG saseccstissctatietincctnsctanetecuteunteiutasnteschecntoastasctaistatetadatedel 310 27 5 41 DERE GHO CEET 310 27542 DEFE CHO VERTPHASEN D S asteesusseueseesegeekesee eege 310 ere DEFE CHI INSIZE RE 2 es rele 310 27 5 44 DEFE CH OUTSIZE REG wsiscccscansitsnsisundtenctancidenctancisenntanddasudand snsdcnddanetendtendtundtuncteds 311 21 93 49 DERE CH1 HORZFACT REG jn 311 27 5 46 DEFE CH1 VERTFACT REG ss nad ha han ib 311 27 5 47 DERE GL NORTE RER 312 27 5 48 DERE CHIN BERS ee Era 312 27 5 49 DEPE CHI VERTPHASET JEE 312 27 5 50 DEFE CHO HORZCO EFO REGN N 0 31 Lanka 312 27 5 51 DEFE GHO VERTCOEF REGN NAOSN nine enden ebe EE 313 27 5 52 DEFE Cl HORZCOEFO REGN N 0 291 acecccedacnicedecnsncelacanettdetusnssdetienidetatenies 313 27 5 53 DERE CHI VERTCOEFP REGN N 0 eege ee 313 28 Display Engine Back End DEBE eevoovvvevveneenssnnennennennesnnvnnennennsv
179. En 31 R W 0 0 disable 1 enable TCON1_Vb_Int_En 30 R W 0 0 disable 1 enable TCONO_Line_Int_En 29 R W 0 0 disable 1 enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 350 Ou 7 Allwinner Technology CO Ltd A13 TCONI Line Int En 28 R W 0 0 disable 1 enable 27 16 TCONO_Vb_Int_Flag 15 R W 0 Asserted during vertical no display period every frame Write 0 to clear it TCON1_Vb_Int_Flag 14 R W 0 Asserted during vertical no display period every frame Write 0 to clear it TCONO Line Int Flag 13 R W 0 trigger when SYO matches the current TCONO scan line Write 0 to clear it TCON1_Line_Int_Flag 12 R W 0 trigger when SY1 matches the current TCONI scan line Write 0 to clear it 11 0 29 3 3 TCON GINT1 REG Offset 0x008 Register Name TCON global interrupt register 1 Bit er PN Description ite Hex 31 27 TCONO_Line_Int_Num scan line for TCONO line trigger including inactive lines 26 16 R W 0 ive f Setting it for the specified line for trigger0 Note SYO is writable only when LINE_TRGO is disabled 15 11 TCONI1 Line Int Num scan line for TCONI line trigger including inactive lines 10 0 R W 0 Setting it for the specified line for trigger 1 Note SY 1 is writable only when LINE TRGI is disabled 29 3 4 TCONO FRM CTL REG Offset 0x010 Re
180. FE Channel 0 Horizontal Factor Register DEFE CHO VERTFACT REG 0x010C DEFE Channel 0 Vertical factor Register DEFE CHO HORZPHASE REG 0x0110 DEFE Channel 0 Horizontal Initial Phase Register DEFE CHO VERTPHASEO REG 0x0114 DEFE Channel 0 Vertical Initial Phase 0 Register DEFE CHO VERTPHASEI REG 0x0118 DEFE Channel 0 Vertical Initial Phase 1 Register DEFE CH1 INSIZE REG 0x0200 DEFE Channel 1 Input Size Register DEFE CH1 OUTSIZE REG 0x0204 DEFE Channel 1 Output Size Register DEFE CH HORZFACT REG 0x0208 DEFE Channel 1 Horizontal Factor Register DEFE CHI VERTFACT REG 0x020C DEFE Channel 1 Vertical factor Register DEFE CH1l HORZPHASE REG 0x0210 DEFE Channel 1 Horizontal Initial Phase Register DEFE CH1 VERTPHASEO REG 0x0214 DEFE Channel 1 Vertical Initial Phase 0 Register DEFE CH1 VERTPHASEI REG 0x0218 DEFE Channel 1 Vertical Initial Phase 1 Register DEFE Channel 0 Horizontal Filter Coefficient Register DEFE CHO HORZCOEF REGN 0x0400 N 4 N 0 31 __ DEFE Channel 0 Vertical Filter Coefficient Register DEFE CHO VERTCOEF REGN 0x0500 N 4 N 0 31 DEFE Channel 1 Horizontal Filter Coefficient Register DEFE CH1 HORZCOEF REGN 0x0600 N 4 N 0 31 DEFE Channel 1 Vertical Filter Coefficient Register DEFE_CH1_VERTCOEF_REGN _ 0x0700 N 4 N 0 31 Note Registers 0x0008 0x0218 except status registers are double buffered when a new frame process starts and the buffered register configuration ready bit in frame process control register is set the val
181. FO Register Name DEBE WBCTL REG Read Wri Default SC Bit Description te Hex WB_EFLAG Error flag 0 1 write back error WB_STATUS Write back process status 0 write back end or write back disable 1 write back in process This flag indicates that a full frame has not been written back to memory The bit will be set when write back enable bit is set and be cleared when write back process ends A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 333 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 WB WOC Write back only control 0 disable the write back only control the normal channel data of back end will transfer to LCD TV controller too 1 enable the write back only function and the all output data will bypass the LCD TV controller WB EN Write back enable 0 Disable 1 Enable If normal channel of back end is selected by LCD TV controller write back only function is disabled the writing back process will start when write back enable bit is set and a new frame processing begins The bit will be cleared when the new writing back frame starts to process 28 5 19 DEBE Write Back Address Register Offset Ox8F4 Register Name DEBE WBADD REG 8 Read Wri Default Bit Description te Hex WB_ADD 31 0 R W UDF i The start address of write back data in WORD 28 5 20 DEBE Write Back Buffer Line Width Register Offset 0x8F8 Register Name DEBE WBLINEWID
182. G Read Wr Default ER Bit Description ite Hex LINE_STRD 31 0 R W 0x0 d Ch3 write back line stride 27 5 36 DEFE CHO INSIZE REG Offset 0x 100 Register Name DEFE CHO INSIZE REG Read Wr Default Bit Description ite Hex 31 29 IN_HEIGHT 28 16 R W 0x0 Input image Y G component height Input image height The value of these bits add 1 15 13 IN_WIDTH 12 0 R W 0x0 Input image Y G component width A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 308 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 The value of these bits add I When line buffer result selection is original data the maximum width is 2048 The image width 27 5 37 DEFE CHO OUTSIZE REG Offset 0x104 Register Name DEFE CHO OUTSIZE REG Bit ane pene Description ite Hex 31 29 OUT_HEIGHT 28 16 R W 0x0 Output layer Y G component height The output layer height The value of these bits add 1 15 13 OUT_WIDTH Output layer Y G component width 12 0 R W 0x0 The output layer width The value of these bits add 1 When line buffer result selection is horizontal filtered result the maximum width is 2048 27 5 38 DEFE CHO HORZFACT REG Offset 0x108 Register Name DEFE CHO HORZFACT REG Bit EE ER Description ite Hex 31 24 FACTOR_INT 23 16 R W 0x0 The integer
183. G 0x0038 PLL1 Tuning2 PLL5 TUN2 REG 0x003C PLLS Tuning2 0x004C OSC24M_CFG_REG 0x0050 OSC24M control CPU_AHB_APBO_CFG_REG 0x0054 CPU AHB And APBO Divide Ratio APBI CLK DIV REG 0x0058 APB1 Clock Divider AXI_GATING_REG 0x005C AXI Module Clock Gating AHB_GATING_REGO 0x0060 AHB Module Clock Gating 0 AHB_GATING_REGI1 0x0064 AHB Module Clock Gating 1 APBO GATING REG 0x0068 APBO Module Clock Gating APB1 GATING REG 0x006C APB1 Module Clock Gating NAND SCLK CFG REG 0x0080 Nand Flash Clock 0x0084 SDO SCLK CFG REG 0x0088 SDO Clock SD1 SCLK CFG REG 0x008C SD1 Clock SD2 SCLK CFG REG 0x0090 SD2 Clock 0x0094 0x0098 SS SCLK CFG REG 0x009C Security System Clock SPI0 SCLK CFG REG Ox00A0 SPIO Clock SPI 1_SCLK_CFG_REG Ox00A4 SPI1 Clock SPI2 SCLK CFG REG 0x00A8 SPI Clock Ox00AC i IR_SCLK_CFG_REG 0x00BO IR Clock 0x00B4 0x00B8 0x00BC A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 54 Ou 7 Allwinner Technology CO Ltd A13 0x00C0 0x00C4 0x00C8 0x00CC l 0x00D0 0x00D4 DRAM_SCLK_CFG_REG 0x0100 DRAM Clock BE_CFG_REG 0x0104 Display Engine Backend Clock 0x0108 FE_CFG_REG 0x010C Display Engine Front End Clock 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 0x0128 LCD_CH1_CFG_REG 0x012C LCD Chann
184. GW 7 Allwinner Technology CO Ltd A13 User Manual V1 2 2013 01 08 Ou 7 Allwinner Technology CO Ltd A13 Revision History Version Date Author Description V1 0 2012 04 16 Initial version V1 1 2012 10 25 Modify SDRAM NAND module descriptions V1 2 2013 1 8 Modify nand usb otg sd3 0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 1 Jau 8 2013 GW Allwinner Technology CO Ltd A13 Technical Items NO Abbreviation Full Name Description A processor core designed by ARM 1 ARM Cortex A8 ARM Cortex A8 Holdings implementing the ARM v7 instruction set architecture Mali 400 Mali 400 A 2D 3D graphic processor unit designed by ARM Holdings SDRAM Synchronous Dynamic Random Access Memory Dynamic random access memory DRAM that is synchronized with the system bus PWM Pulse Width Modulator A commonly used technique for controlling power to inertial electrical devices made practical electronic by modern power switches SPI Serial Peripheral Interface A synchronous serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame UART Universal Asynchronous Receiver Transmitter used for serial communication with a peripheral modem data carrier equipment DCE or data set
185. IN REG 0x005C PMU 32khz CPUVDD Minimum Value PMU VF TABLE REGO 0x0080 CPU speed max if the vddepu 0 70v PMU VF TABLE REGI 0x0084 CPU speed max if the vddepu 0 75v PMU VF TABLE REG2 0x0088 CPU speed max if the vddepu 0 80v PMU VF TABLE REG3 0x008C CPU speed max if the vddepu 0 85v PMU VF TABLE REG4 0x0090 CPU speed max if the vddepu 0 90v PMU VF TABLE REG5 0x0094 CPU speed max if the vddepu 0 95v PMU VF TABLE REG6 0x0098 CPU speed max if the vddepu 1 00v PMU VF TABLE _REG7 0x009C CPU speed max if the vddepu 1 05v A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 32 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 PMU VF TABLE REG8 Ox00A0 CPU speed max if the vddcpu 1 10v PMU_VF_TABLE_REG9 Ox00A4 CPU speed max if the vddcpu 1 15v PMU VF TABLE REG10 0x00A8 CPU speed max if the vddepu 1 20v PMU VF TABLE REGI 1 Ox00AC CPU speed max if the vddcpu 1 25v PMU_VF_TABLE_REG12 0x00BO CPU speed max if the vddepu 1 30v PMU VF TABLE REG13 0x00B4 CPU speed max if the vddepu 1 35v PMU VF TABLE REG 14 0x00B8 CPU speed max if the vddepu 1 40v PMU VF TABLE REG 15 0x00BC CPU speed max if the vddepu 1 45v PMU VF TABLE REG16 Ox00C0 CPU speed max if the vddcpu 1 50v PMU VF TABLE _REG17 Ox00C4 CPU speed max if the vddcpu 1 55v PMU_VF_TABLE_REG18 0x00C8 CPU speed max if the vddepu 1 60v PMU VF TABLE VALID REG Ox00CC PMUVf Table Valid Control PMU_
186. IRQ Enable 9 R W 0x0 0 Disable 1 Enable 8 5 VOLT_DET_FIN_IRQ_EN Voltage Detect Finished IRQ Enable 4 R W 0x0 0 Disable 1 Enable DVFS_CLK_SWT_FIN_IRQ_EN DVFS Clock Switch Operation Finished IRQ Enable 3 R W 0x0 0 Disable 1 Enable DVFS VOLT CHANGE FIN EN DVFS Voltage Change Finished Enable 2 R W 0x0 0 Disable 1 Enable DVFS SPD DET FIN IRQ EN 1 R W 0x0 DVFS Speed Detect Finished IRQ Enable 0 Disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 36 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd 1 Enable A13 0x0 DVFS FIN IRQ EN DVFS Finished IRQ Enable 0 Disable 1 Enable 5 3 9 PMU IRQ Status Register Offset 0x44 Register Name PMU IRQ STATUS REG Read Wr ite Bit Default Hex Description 31 13 12 R W 0x0 VOLT_DET_ERR_IRQ_PEND Voltage Detect Error IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it 11 R W 0x0 DVFS_CLK_SWT_ERR_IRQ_PEND DVES Clock Switch Operation Error IRQ Pending 0 No effect 1 Pending Set one to this bit will clear it 10 R W 0x0 DVFS_VOLT_CHANGE_ERR_PEND DVFS Voltage Change Error Pending 0 No effect 1 Pending Set one to this bit will clear it 0x0 DVFS_SPD_DET_ERR_IRQ_PEND DVFS Speed Detect Error IRQ Pending 0 No effect 1 Pending Set one to this bit will
187. Jau 8 2013 GW Allwinner Technology CO Ltd A13 2 Pin Description 2 1 Pin Placement Table Refer to A13 Datasheet for details 2 2 Pin Detail Description Refer to A13 Datasheet for details A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 26 Jau 8 2013 SS Allwinner Technology CO Ltd 3 Architecture 3 1 Functional Block Diagram aa A13 CPU Cotex A8 Figure3 1 Functional Block Diagram 3 2 Memory Mapping Module Address Size Bytes SRAM A1 0x0000 0000 0x0000 3FFF 16K SRAM A2 0x0000 4000 0x0000 7FFF 16K SRAM A3 0x0000 8000 0x0000 B3FF 13K SRAM A4 0x0000 B400 0x0000 B FFF 3K SRAM NAND 2K SRAM D 0x0001 0000 0x0001 OFFF 4K SRAM Controller 0x01C0 0000 0x01C0 OFFF 4K DRAM Controller 0x01C0 1000 0x01C0 1 FFF 4K DMA 0x01C0 2000 0x01C0 2FFF 4K NFC 0x01C0 3000 0x01C0 3FFF 4K 0x01C0 4000 0x01C0 4FFF 4K SPI O 0x01C0 5000 0x01C0 5FFF 4K A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 SPI 1 0x01C0 6000 0x01CO 6FFF 4K 0x01C0 7000 0x01CO 7FFF 4K 0x01C0 8000 0x01CO 8FFF 4K CSI 0x01C0 9000 0x01CO 9FFF 4K 0x01C0 A000 0x0
188. LUS_UP_DEBOUCE_EN Stylus Up De bounce Function Select 0 Disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 269 Jau 8 2013 Q Allwinner Technology CO Ltd A13 0x0 1 Enable TOUCH_PAN_CALI EN Touch Panel Calibration 1 start Calibration it is clear to 0 after calibration 0x0 0x0 TP_DUAL_EN Touch Panel Double Point Enable 0 Disable 1 Enable TP_MODE_EN Tp Mode Function Enable 0 Disable 1 Enable Ox1 CET BEBE 2 0 0x0 TP_ADC_SELECT Touch Panel and ADC Select 0 TP 1 ADC ADC_CHAN_SELECT Analog input channel Select In Normal mode 000 X1 channel 001 X2 Channel 010 Y1 Channel 011 Y2 Channel 1xx 4 channel robin round FIFO Access Mode based on this setting Selecting one channel FIFO will access that channel data Selecting four channels FIFO will access each channel data in successive turn first is X1 data 25 6 3 TP Control Register 2 Offset 0x08 Register Name TP_CNT2 Bit Read Wr Default Description ite Hex 31 28 R W 0x8 TP_SENSITIVE_ADJUST Internal Pull up Resistor Control 0000 least sensitive 0011 1111 most sensitive Note Used to adjust sensitivity of pen down detection 27 26 R W 0x0 TP_MODE_SELECT A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 270 Jau 8 2013 Ou 7 Allwinner Technology CO L
189. M M 1 16 PLL7x2 OSC24M PLL3x1 LCD CHI CLK2 LCD CH1 CLK1 CLK OUT CLK IN M M 1 2 PLL7x1 CSI CLK CLK_OUT CLK_IN M M 1 32 PLL3x2 PLL7x2 PLL4 PLL2 VE CLK VE CLK OUT OSC24M AUDIOCODEC CLK OSC24M AVS CLK AVS CLK OUT PLL6 MBUS CLK Max 300MHz CLK_OUT CLK_IN M N M 1 16 N 1 2 4 8 MBUS CLK OUT gt PLL5 CSI CLK OUT Lk p AUDIOCODEC CLK OUT E 6 3 CCM Register List Figure6 3 Bus Clock Generation Part 2 Module Name Base Address CCM 0x01C20000 Register Name Offset Description A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 53 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 PLLI CFG REG 0x0000 PLL1 Control PLL1_TUN_REG 0x0004 PLL1 Tuning PLL2 CFG REG 0x0008 PLL2 Control PLL2 TUN REG 0x000C PLL2 Tuning PLL3 CFG REG 0x0010 PLL3 Control 0x0014 PLL4 CFG REG 0x0018 PLL4 Control 0x001C PLL5 CFG REG 0x0020 PLL5 Control PLL5 TUN REG 0x0024 PLLS Tuning PLL6 CFG REG 0x0028 PLL6 Control 0x002C PLL6 Tuning PLL7_CFG_REG 0x0030 0x0034 PLL1_TUN2_RE
190. M clock 0 1 cycle 31 16 R W D 1 2 cycles N N 1 cycles PWM_ACT_CYC Number of the active cycles in the PWM clock 0 0 cycle 15 0 R W x 1 1 cycles N N cycles Note the active cycles should be no larger than the period cycles A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 87 Jau 8 2013 N 7 Allwinner Technology CO Ltd A13 11 Asynchronic Timer 11 1 Overview The chip implements 6 async timers Timer 0 1 2 can take their inputs from the PLL6 6 or OSC24M They provide the operating system s scheduler interrupt It is designed to offer maximum accuracy and efficient management even for systems with long or short response time They provide 32 bit programmable overflow counter and work in auto reload mode or no reload mode The watch dog is used to resume controller operation by generating a general reset or an interrupt request when it is disturbed by malfunctions such as noise sand system errors It features a down counter that allows a watchdog period of up to 16 seconds Timer 3 is used for OS to generate a periodic interrupt 11 2 ASYNC Timer Register List Module Name Base Address ASYNC Timer 0x01C20C00 Register Name Offset Description ASYNC TMR IRQ EN REG 0x0000 Timer IRQ Enable ASYNC TMR IRQ STAS REG 0x0004 Timer Status ASYNC TMRO CTRL REG 0x0010 Timer 0 Con
191. NGTH The value in these bits indicates an offset to add to register base to find 7 0 R 0x10 the beginning of the Operational Register Space 22 5 2 EHCI Host Interface Version Number Register Register Name HCIVERSION Offset 0x02 Default Value 0x0100 Bit Read Write Default Description HCIVERSION This is a 16 bits register containing a BCD encoding of the EHCI revision number supported by this host controller The most significant byte of this register represents a major revision and the least significant 15 0 R 0x0100 byte is the minor revision 22 5 3 EHCI Host Control Structural Parameter Register Register Name HCSPARAMS Offset 0x04 Default Value Implementation Dependent Bit Read Write Default Description Reserved 31 24 0 These bits are reserved and should be set to zero Debug Port Number This register identifies which of the host controller ports is the debug port The value is the port number one based of the debug port 23 20 R 0 This field will always be 0 19 16 0 Reserved A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 209 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 These bits are reserved and should be set to zero Number of Companion Controller N CC This field indicates the number of companion controllers associated with this USB2 0 host controlle
192. NT 0x34 ADC RX FIFO Counter Register 23 4 Audio Codec Register Description 23 4 1 DAC Digital Part Control Register Offset 0x00 Register Name AC_DAC_DPC Bit Read Write Default Description EN_DA DAC Digital Part Enable 31 R W 0x0 0 Disable 1 Enable 30 29 28 25 24 23 19 18 17 12 11 0 23 4 2 DAC FIFO Control Register Offset 0x4 Register Name AC_DAC_FIFOC Bit Read Write Default Description DAC FS 31 29 R W 0x0 Sample Rate of DAC 000 48KHz A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 243 Ou 7 Allwinner Technology CO Ltd A13 010 24KHz 100 12KHz 110 192KHz 001 32KHz 011 16KHz 101 8KHz 111 96KHz 44 1KHz 22 05KHz 11 025KHz can be supported by Audio PLL Configure Bit FIR Version 28 R W R W 0 64 Tap FIR 1 32 Tap FIR 27 SEND_LASAT Audio sample select when TX FIFO under run 26 R W 0x0 0 Sending zero 1 Sending last audio sample 25 For 24 bits transmitted audio sample 0 FIFO_I 23 0 TXDATA 31 8 1 Reserved 24 R W 0x0 e For 16 bits transmitted audio sample 0 FIFO 1 23 0 TXDATA 31 16 8 b0 1 FIFO 1 23 0 TXDATA 15 0 8 b0 23 DAC_DRQ_CLR_CNT When TX FIFO available room less than or equal N DRQ Request will be d
193. Note Timer current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 11 3 12 ASYNC Timer 3 Control Register Default 0x00000000 Offset 0x40 Register Name ASYNC_TMR3_CTRL_REG i Read Wr Default E Bit Description ite Hex 31 8 TMR3_CLK_SRC Timer 3 Clock Source O internal 32k 1 OSC24M 7 R W 0x0 6 5 TMR3_MODE Timer 3 mode 0 Continuous mode When reaches the internal value the timer will not be 4 R W 0x0 disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically TMR3_CLK_PRESCALE Select the pre scale of timer 3 clock source 00 16 01 32 10 64 11 1 3 2 R W 0x0 1 TMR3 EN 0 R W 0x0 Timer 3 Enable 0 Disable 1 Enable Note the time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 13 ASYNC Timer 3 Interval Value Offset 0x44 Register Name ASYNC_TMR3_INTV_VALUE_REG Bit Read Wr Default Description A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 95 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 ite Hex R W X TMR3_INTV_VALUE Timer 3 Interval Value 11
194. O0 Output Tri En 1 disable 0 enable 27 0 R W OxFFFF FF Data Output Tri En TCONI output port D 23 0 output enable with independent bit control Is disable Os enable 29 3 29 TCON CEU CTL REG Offset 0x100 Register Name TCON CEU control register Read Wr Default WM Bit Description ite Hex CEU_en 31 R W 0 0 bypass 1 enable 30 0 29 3 30 TCON_CEU_COEF_REG Offset 0x110 118 0x 120 0x128 0x130 0x138 Register Name TCON CEU multiplier coefficient register Read Wr Default Bit Description ite Hex 31 13 CEU_Coef_Mul_ Value 12 0 R W 0 E signed 13bit value range of 16 16 Offset x11C 0x12C 0x13C Register Name TCON CEU add coefficient register Read Wr Default SC Bit Description ite Hex 31 19 CEU_Coef_Add_Value 18 0 R W 0 signed 19bit value range of 16384 16384 Offset 0x140 0x144 0x148 Register Name TCON CEU range coefficient register Read Wr Default SS Bit Description ite Hex 31 24 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 362 Ou 7 Allwinner Technology CO Ltd A13 CEU Coef Range Min 23 16 R W 0 unsigned 8bit value
195. PG Configure Register 0 Offset 0xD8 Register Name PG CFGO Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 402 Ou 7 Allwinner Technology CO Ltd A13 31 30 28 R W 0 27 26 24 R W 0 23 22 20 R W 0 19 PG4 Select 000 Input 001 Output 010 SDC1 CLK Ol 1 100 UART1 RX 101 18 16 R W 0 110 EINT4 111 15 PG3 Select 000 Input 001 Output 010 SDC1_CMD 011 100 UART1_TX 101 14 12 R W 0 110 EINT3 111 11 PG2 Select 000 Input 001 Reserved 010 011 100 101 10 8 R W 0 110 EINT2 111 7 PG1 Select 000 Input 001 Reserved 010 011 100 101 6 4 R W 0 110 EINT1 111 PGO Select 000 Input 001 Reserved 010 011 100 101 2 0 R W 0 110 EINTO 111 33 4 47 PG Configure Register 1 Register Name PG_CFG1 Offset OxDC Default Value 0x0000 0000 Bit Read Write Default Description A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 403 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 31 24 23 22 20 R W 0 19 PG12 Select 000 Input 001 Output 010 SPIL MISO 011 UART3 RTS 100
196. PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 The bytes sequence is ARGB PS 10 11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 The bytes sequence is BGRA 28 5 16 DE HWC Coordinate Control Register Offset 0x8D8 Register Name DEBE HWCCTL REG Read Wri Default i Bit Description te Hex HWC_YCOOR 31 16 R W UDF i Hardware cursor Y coordinate HWC XCOOR 15 0 R W UDF Hardware cursor X coordinate 28 5 17 DE HWC Frame Buffer Format Register Offset Ox8EO Register Name DEBE HWCFBCTL REG Read Wri Default VERE Bit Description te Hex HWC YCOOROFF Y coordinate offset 31 24 R W UDF The hardware cursor is 32 32 2 bpp pattern this value represent the start position of the cursor in Y coordinate HWC_XCOOROFF 23 16 R W UDF X coordinate offset A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 332 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 The hardware cursor is 32 32 2 bpp pattern this value represent the start position of the cursor in X coordinate HWC_YSIZE Y size control 00 32pixels per line 01 64pixels per line Other reserved HWC_XSIZE X size control 00 32pixels per row 01 64pixels per row Other reserved HWC_FBFMT Pixels format control 00 1bpp 01 2bpp 10 4bpp 11 8bpp 28 5 18 DEBE Write Back Control Register Offset Ox8
197. Q 9 Priority Set priority level for IRQ bit 9 Level0 0x0 level 0 lowest priority 19 18 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 120 Jau 8 2013 Ou Allwinner Technology CO Ltd Offset 0x80 Register Name INTC_SRC_PRIO_REGO A13 Levell 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 17 16 R W 0x0 IRQ8_PRIO IRQ 8 Priority Set priority level for IRQ bit 8 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 15 14 R W 0x0 IRQ7_PRIO IRQ 7 Priority Set priority level for IRQ bit 7 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 13 12 R W 0x0 IRQ6_PRIO IRQ 6 Priority Set priority level for IRQ bit 6 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 11 10 R W 0x0 IRQ5_PRIO IRQ 5 Priority Set priority level for IRQ bit 5 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 9 8 R W 0x0 IRQ4_PRIO IRQ 4 Priority Set priority level for IRQ 4 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 7 6 R
198. R W XCH Exchange Burst In master mode it is used to start to SPI burst when SMC bit is set to 1 0 Idle 1 Initiates exchange After finishing the SPI bursts transfer specified by A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 174 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 BC this bit is cleared to zero by SPI Controller RXFIFO Reset Write 1 to reset the control portion of the receiver FIFO and treats the FIFO as empty 9 R W It is self clearing It is not necessary to clear this bit TXFIFO Reset Write 1 to reset the control portion of the transmit FIFO and treats the FIFO as empty 8 R W It is self clearing It is not necessary to clear this bit SSCTL In master mode this bit selects the output wave form for the SPI_SSx signal 0 SPI_SSx remains asserted between SPI bursts 7 R W 1 Negate SPI_SSx between SPI bursts LMTF LSB MSB Transfer First select 0 MSB first 6 R W 1 LSB first DMAM DMA mode control 0 normal dma 5 R W 1 dedicate dma SSPOL SPI Chip Select Signal Polarity Control 0 Active high polarity 0 Idle 4 R W 1 Active low polarity 1 Idle POL SPI Clock Polarity Control 0 Active high polarity 0 Idle 3 R W 1 Active low polarity 1 Idle PHA SPI Clock Data Phase Control 0 Phase 0 Leading edge for sample data 2 R W 1 Phase 1 Leading edge for setup data MODE SPI Fu
199. R W 0 110 111 15 14 12 R W 0 PD19 Select A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 394 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 000 Input 001 Output 010 LCD D19 Ol 1 100 101 110 111 11 PD18 Select 000 Input 001 Output 010 LCD_D18 011 100 101 10 8 R W 0 110 111 7 6 4 R W 0 3 2 0 R W 0 33 4 22 PD Configure Register 3 Register Name PD_CFG3 Offset 0x78 Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 PD27 Select 000 Input 001 Output 010 LCD_VSYNC 011 100 101 14 12 R W 0 110 111 11 PD26 Select 000 Input 001 Output 010 LCD_HSYNC 011 100 101 10 8 R W 0 110 11 7 PD25 Select 000 Input 001 Output 010 LCD_DE 011 100 101 6 4 R W 0 110 11 PD24 Select 2 0 R W 0 000 Input 001 Output A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 395 Ou 7 Allwinner Technology CO Ltd A13 010 LCD CLK Ol 1 100 101 110 111 33 4 23 PD Data Register Register Name PD DAT Offset 0x7C Default Value 0x0000 0000 Bit Read Write Default Description 31 28 If the port is configured as input the corresponding bit i
200. R W 0x0 Watchdog IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending Watchdog counter value is reached 7 6 TMR5_IRQ_PEND 5 R W 0x0 Timer 5 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 5 counter value is reached TMR4 IRQ PEND 4 R W 0x0 Timer 4 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 4 counter value is reached TMR3_IRQ_PEND 3 R W 0x0 Timer 3 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 3 counter value is reached TMR2_IRQ_PEND 2 R W 0x0 Timer 2 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 2 counter value is reached TMR1_IRQ PEND 1 R W 0x0 Timer 1 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 1 interval value is reached TMRO IRQ PEND 0 R W 0x0 Timer 0 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 0 interval value is reached 11 3 3 ASYNC Timer 0 Control Register Default 0x00000004 Offset 0x10 Register Name ASYNC_TMRO_CTRL_REG Bit Fl re Description ite Hex 31 8 TMRO MODE Timer0 mode 0 Continuous mode When reaches the internal value the timer will not be 7 R W 0x0 disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically TMRO_CLK_PRES 6 4 R W 0x0 Select the pre scale of timer 0 clock source 000 1 A13 User Manual V1 2 Copyright 2013
201. RBR is overwritten In the FIFO mode an overrun error occurs when the FIFO is full and a new character arrives at the receiver The data in the FIFO is retained and the 1 R data in the receive shift register is lost A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 195 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 0 no overrun error 1 overrun error Reading the LSR clears the OE bit R DR Data Ready This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO 0 no data ready 1 data ready This bit is cleared when the RBR is read in non FIFO mode or when the receiver FIFO is empty in FIFO mode 19 4 11 UART Modem Status Register Offset 0x18 Register Name UART MSR Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DCD Line State of Data Carrier Detect This is used to indicate the current state of the modem control line ded n This bit is the complement of ded n When the Data Carrier Detect input dcd_n is asserted it is an indication that the carrier has been detected by the modem or data set 0 ded n input is de asserted logic 1 1 ded n input is asserted logic 0 RI Line State of Ring Indicator This is used to indicate the current state of the modem control line ri n This bit is the complement of ri n When the Ring I
202. RQ_PEND Dedicated DMA 7 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 30 R W 0x0 DDMA7_HF_IRQ_PEND Dedicated DMA 7 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 29 R W 0x0 DDMA6_END_IRQ_PEND Dedicated DMA 6 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 28 R W 0x0 DDMA6_HF_IRQ_PEND Dedicated DMA 6 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 27 R W 0x0 DDMA5 END IRQ PEND Dedicated DMA 5 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 26 R W 0x0 DDMA5 HF IRQ PEND Dedicated DMA 5 Half Transfer Interrupt Pending Set I to the bit will clear it 0 No effect 1 Pending A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 140 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 25 R W 0x0 DDMA4_END_IRQ_PEND Dedicated DMA 4 End Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 24 R W 0x0 DDMA4_HF_IRQ_PEND Dedicated DMA 4 Half Transfer Interrupt Pending it 0 No effect 1 Pending Set 1 to the bit will clear 23 R W 0x0 DDMA3_END_IRQ_PEND Dedicated DMA 3 End Transfer Interrupt Pending it
203. R_REG Offset 0x064 Register Name TCONO cpu panel write data register Read Wr Default a Bit Description ite Hex 31 0 Data_Wr 23 0 W 0 e data write on 8080 bus launch a write operation on 8080 bus 29 3 16 TCONO_ CPU _RDO_ REG Offset 0x068 Register Name TCONO cpu panel read data register0 Read Wr Default a Bit Description ite Hex 31 24 Data RO 23 0 R i data read on 8080 bus launch a new read operation on 8080 bus 29 3 17 TCONO CPU RD1 REG Offset 0x06C Register Name TCONO cpu panel read data register 1 Read Wr Default o Bit f Description ite Hex 31 24 Data Rd1 23 0 R e data read on 8080 bus without a new read operation on 8080 bus 29 3 18 TCONO IO POL REG Offset 0x088 Register Name TCONO IO polarity register Read Wr Default ae Bit Description ite Hex 31 30 DCLK_Sel 29 28 R W 0 00 used DCLKO normal phase offset A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 357 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 01 used DCLK1 1 3 phase offset 10 used DCLK2 2 3 phase offset 11 reserved 27 R W 103_Inv 0 not invert 1 invert 26 R W 102 Inv 0 not invert 1 invert 25 R W IO1 Inv 0 not invert 1 invert 24 R W IOO_Inv 0 not invert 1 invert 23 0 R W Data_Inv TCONO output port D 23 0 polarity control with independ
204. Register Default 0x00000004 Offset 0x60 Register Name ASYNC TMR5 CTRL REG 8 Read Wr Default aan Bit i Description ite Hex 31 8 TMR5 MODE Timer5 mode 0 Continuous mode When reaches the internal value the timer will not be 7 R W 0x0 disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 97 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 TMR5 CLK PRESCALE Select the pre scale of timer 5 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 6 4 R W 0x0 TMR5_CLK_SRC Timer 5 Clock Source 00 01 OSC24M 10 External CLKIN1 11 3 2 R W 0x1 TMR5_RELOAD Timer 5 Reload 1 R W 0x0 0 No effect 1 Reload timer 0 Interval value After the bit is set it can not be written again before it s cleared automatically TMR5_EN Timer 5 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to j i ES 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register
205. Reserved Ox3FFF 0x4000 Reserved 0x43FF 0x4400 Gamma Table 0x47FF 0x4800 HWC Memory Ox4BFF DE 0x4C00 HWC Palette Table Ox4FFF 0x5000 PIPEO Palette Table 0x53FF 0x5400 PIPE 1 Palette Table 0x57FF 0x5800 Reserved OxFFFF A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 346 Jau 8 2013 Allwinner Technology CO Ltd A13 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 347 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 29 LCD TV Timing Controller 29 1 LCD TV Timing Controller Block Diagram MAX 700MHz CONTROL LOGIC F RGB DMA OUTO Async FIFOI EURE 2u SE M HV TIMING OUT2 a ee A To FIFO Flag BASIC CPU TIMING DE S t DE hag GENERATOR ae S GEN TIMING OUT1 CEU Gamma Async FIFO2 gt GE Figure 29 1 LCD TV Timing Controller Block Diagram 29 2 LCD TV Timing Controller Register List Module Name Base Address TCON 0x01C0C000 Register Name Offset Description TCON GCTL REG 0x0000 TCON Global Control Register TCON GINTO REG 0x0004 TCON Global Interrupt Register0 TCON_GINT1_REG 0x0008 TCON Global Interrupt Register TCONO_FRM_CTL_REG 0x0010 TCON FRM Cont
206. See details in the following table CLK Domain Module Speed Range Description OSC24M Most Clock Generator 24MHz Root clock for most of the chip RC_OSC Timer key 32KHz Source for the timer CPU32_clk CPU32 2K 1200M Divided from CPU32_clk or OSC24M AHB clk AHB Devices 8K 276M Divided from CPU32_clk APB clk Peripheral 0 5K 138M Divided from AHB dk SDRAM clk SDRAM 0 400MHz Sourced from the PLL USB_clk USB 480MHz Sourced from the PLL Audio_clk A D D A ee Sourced from the PLL 22 5792MHz A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 50 Jau 8 2013 Allwinner Technology CO Ltd 6 2 Clock Tree Diagram PLL 1 240MHz 2GHz OUT 24MHz N K M P N 0 31 K 1 4 M 1 4 P 1 2 4 8 PLL 2 OUT 22 5792MHz 24 576MHz PLL 3 27MHz 381MHz OUT 3MHz M Integer mode OUT 270MHz 297MHz Fractional M 9 127 A13 User Manual V1 2 PLL 4 240MHz 2GHz OUT 24MHz N K M P N 0 31 K 1 4 M 1 4 P 1 2 4 8 PLL 5 240MHz 2GHz OUT 24MHz N K M OUT 24MHz N K P N 0 31 K 1 4 M 1 4 P 1 2 4 8 PLL 6 Fixed To 1 2GHZ A13 PLLIOUT PLL2OUT PLL3OUT y PLL 7 27MHz 38 1 MHz OUT 3MHz M Integer mode OUT 270MHz7 297MHz Fractional M 9 127 Figure 6 1 Clock Generation from PLL Outputs Copyright 2013 Allwinner Technology All Right
207. TH REG Read Wri Default ae Bit Description te Hex WB_LINEWIDTH 31 0 R W UDF 3 et Write back image buffer line width in bits 28 5 21 DEBE Input YUV Channel Control Register Offset 0x920 Register Name DEBE_TYUVCTL_REG Read Wri Default Bit i Description e Hex IYUV_FBFMT Input data format 000 planar YUV 411 UDF 001 planar YUV 422 010 planar YUV 444 011 interleaved YUV 422 14 12 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 334 Jau 8 2013 GW 7 Allwinner Technology CO Ltd A13 100 interleaved YUV 444 Other illegal 11 10 IYUV_FBPS Pixel sequence In planar data format mode 00 Y3Y2Y1Y0 01 YOY1Y2Y3 the other 2 components are same Other illegal In interleaved YUV 422 data format mode 00 UYVY O1 YUYV 10 VYUY 11 YVYU In interleaved YUV 444 data format mode 00 AYUV 01 VUYA Other illegal Source Data Input Data Ports Input buffer channel Planar YUV Interleaved YUV Channel YUV Channel I Channel2 28 5 22 DEBE YUV Channel Frame Buffer Address Register Offset Channel 0 0x930 Register Name DEBE_TYUVADD_REG Channel 1 0x934 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 335 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Channel 2 0x938 Read Wri Default i Bit Description te Hex IYUV ADD Buffer Address Frame buffer addres
208. TRL Still capture control Capture a single still image frame 0 Disable still capture 1 Enable still capture The CSI module starts capturing image data at the start of the next frame The CSI module captures only one frame of image data This bit is self cleared and always reads as a 0 26 4 4 CSI FIFOO Buffer A Register Register Name CSI FIFOO0 BUF ADDR REG Offset Address 0X0010 Default Value 0X00000000 Read Wri Default Ss wn ER Ins te Hex FIFOO_BUF_A 31 00 R W FIFOO output buffer A address 26 4 5 CSI FIFOO Buffer B Register Offset Address 0X0014 Register Name CSI_FIFOO_BUF_B_ADDR_REG A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 279 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Wri Default Description te Hex FIFOO_BUF_B R W FIFOO output buffer B address 26 4 6 CSI FIFO1 Buffer A Register Register Name CSI_FIFO1_BUF_A_ADDR_REG Default Value 0X00000000 Read Wri Default rae te Hex FIFO1_BUF_A R W FIFO1 output buffer A address 26 4 7 CSI FIFO1 Buffer B Register Register Name CSI FIFO1 BUF B ADDR REG Offset Address OX001C Default Value 0X00000000 Offset Address 0X0018 Read Wri Default Bit Description te Hex FIFO1_BUF_B 31 00 R W FIFO1 output buffer B address 26 4 8 CSI Buffer Control Register Register Name CSI BUF CTRL REG Offset Address 0X0028 Default Value 0X00000000 Description Hex
209. Typical Application Circuit EE 260 25 3 Clock Tree and ADC Time sistema ee en nent 261 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 13 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 25 3 1 CIDER IGG eek ciel ee etek 261 25 3 2 A D Convertion Time EEE ENN 261 25 4 Principle of RTE E 262 25 4 1 MVS P SE lee exces sac ee cea ec coe ede fee eee eee ees eee a ae een tees eee 262 25 4 2 ETNE iiaiai aana Daaah r aada anrik n aara EnaA 263 25 4 3 Differential Mode stete aa aaa a tee i are ibe 263 25 4 4 Single Touch Detection aici 264 25 4 5 Dual Touch Detection EE 264 25 4 6 Touch Pressure Measurement 265 25 4 7 Pen Down Detection with Programmable Sensitivity esseeseeeeeeeeeereerr ereenn 266 25 4 8 Median and Averaging Filter sise 266 29 9 IP Register LAS EE 268 25 6 TP Register Description EE 268 25 6 1 MP Control Register Ox co oe ae rae been cae 268 25 6 2 TP control Register 1 269 25 6 3 TP Control Register See 270 25 6 4 Median Filler Control Heeler eieiei eieiei 271 25 6 5 TP Interrupt amp FIFO Control Register 271 25 6 6 TP Interrupt amp FIFO Ee 272 25 6 7 TP Temperature Period Register 273 25 6 8 GOmmon Data EE 274 25 6 9 IP Data LEE 274 25 6 10 TP Port IO Configure Register Luse 274 25 611 TP Port Data Register irosit orisni eire edo irre enal 275 26 CMOS Sensor Interface CSI eeesssssscsceeessssscceccesesssocccceesessoscccceese
210. UFF LEN 12 00 R W 0x280 Buffer Length Buffer length of a line Unit is byte A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 283 Jau 8 2013 Ou Allwinner Technology CO Ltd 26 5 CCIR656 Format 26 5 1 Header Data Bit Definition A13 Data Bit First Word 0xFF Second Word 0x00 Third Word 0x00 Fourth Word CS D 7 MSB CS D 6 CS D 5 CS D 4 CS D 3 CS D 2 CS D 1 p p pjm la rs CS D 0 O D O oD OoD o o o O D O oD oD o o o 26 5 2 CCIR656 Header Decode Decode wi Lu wi N ian ge gt Field 1 start of active video SAV Field 1 end of active video EAV Field 1 SAV digital blanking Field 1 EAV digital blanking Field 2 SAV Field 2 EAV Field 2 SAV digital blanking Field 2 EAV digital blanking j j j ejololojl o lolo lool v le lraie ltaleirale E o m m 1 ol o o Oro io rio o oD lm OI o mor nm 26 6 CSI Timing Diagram vsync n framey n 1 frame hsyne f Po active data 4 firstline data gt s last line data Vref Positive Href Positive ven ff ff nframe ff n 1 frame hsyne ff H ken negen lines _ gt M FLAT vertical stat line n vertical active line length m
211. VF_TABLE_INDEX_REG 0x00D0 PMU Vf Table Index PMU_VF_TABLE_RANGE_REG 0x00D4 PMU Vf Table Range PMU SPEED FACTOR REGO 0x00E0 PMU Speed Factor Register 0 PMU SPEED FACTOR REGI Ox00E4 PMU Speed Factor Register 1 PMU SPEED FACTOR REG2 0x00E8 PMU Speed Factor Register 2 CPU IDLE CNT LOW REG Ox00F0 CPU Idle Counter Low CPU_IDLE_CNT_HIGH_REG Ox00F4 CPU Idle Counter High CPU_IDLE_COUNTER_CTRL_REG 0x00F8 CPU Idle Counter Control CPU IDLE STATUS REG 0x00FC CPU Idle Status Register 5 3 PMU Register Description 5 3 1 PMU DVFS Control Register 0 Offset 0x00 Register Name PMU_DVFS_CTRL_REGO 8 Read Wr Default SC Bit Description ite Hex 31 18 DVFS_MODE_SEL DVFS Mode Select 00 mode 0 17 16 R W 0x0 01 mode 1 10 mode 2 11 AXI_DIV_AUTO_SWITCH 15 R W 0x0 AXICLK auto switch enable 0 Disable 1 Enable 14 13 VOLT CHANGE MODE 12 R W 0x0 Voltage Change Mode A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 33 Ou 7 Allwinner Technology CO Ltd 0 normal mode 1 maximum mode 11 9 CLK_CHANGE_SM_MODE Clock Change Smooth Mode 8 R W 0x0 a 0 Divide mode 1 Gating mode SM_EN 7 R W 0x0 Smooth enable 0 Disable 1 Enable CLK_SWTH_EN 6 R W 0x0 Clock switch enable 0 Disable 1 Enable VOLT_CHANGE_EN 5 R W 0x0 Voltage change enable 0 Disable 1 Enable SPD_DET
212. W 0x0 IRQ3_PRIO IRQ 3 Priority Set priority level for IRQ bit 3 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Offset 0x80 Register Name INTC SRC PRIO REGO Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority IRQ2_PRIO IRQ 2 Priority Set priority level for IRQ bit 2 5 4 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ1_PRIO IRQ I Priority Set priority level for IRQ bit 1 3 2 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 1 0 Programs the priority level for all sources except FIQ source source 0 The priority level ranges from O lowest to 7 highest 13 4 27 Interrupt Source Priority 1 Register Default 0x00000000 Offset 0x84 Register Name INTC SRC PRIO REGI Read Wr Default L Bit Description ite Hex IRQ31_PRIO IRQ 31 Priority Set priority level for IRQ bit 31 31 30 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority IRQ30 PRIO IRQ 30 Priority Set priority level for IRQ bit 30 29 28 R W 0x0 Level0 0x0 level 0
213. YUV411 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 292 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 27 4 DEFE Register List Module Name Base Address DEFEO 0x01E00000 Register Name Offset Description DEFE_EN_REG 0x0000 DEFE Module Enable Register DEFE_FRM_CTRL_REG 0x0004 DEFE Frame Process Control Register DEFE BYPASS REG 0x0008 DEFE CSC By Pass Register DEFE AGTH SEL REG 0x000C DEFE Algorithm Selection Register DEFE LINT CTRL REG 0x0010 DEFE Line Interrupt Control Register DEFE BUF ADDRO REG 0x0020 DEFE Input Channel 0 Buffer Address Register DEFE BUF ADDRI1 REG 0x0024 DEFE Input Channel 1 Buffer Address Register DEFE BUF ADDRI REG 0x0028 DEFE Input Channel 2 Buffer Address Register DEFE FIELD CTRL REG 0x002C DEFE Field Sequence Register DEFE TB OFFO REG 0x0030 DEFE Channel 0 Tile Based Offset Register DEFE TB OFF1 REG 0x0034 DEFE Channel Tile Based Offset Register DEFE TB OFF2 REG 0x0038 DEFE Channel 2 Tile Based Offset Register DEFE LINESTRDO REG 0x0040 DEFE Channel 0 Line Stride Register DEFE LINESTRDI REG 0x0044 DEFE Channel 1 Line Stride Register DEFE LINESTRD 2 REG 0x0048 DEFE Channel 2 Line Stride Register DEFE INPUT FMT REG 0x004C DEFE Input Format Register DEFE WB ADDRO REG 0x0050 DEFE Channel 3 Write Back Address Register DEFE OUTPUT FMT REG 0x005C DEFE O
214. _EN 4 R W 0x0 Speed detect enable 0 Disable 1 Enable 3 1 DVFS_EN PMU DVFS Enable 0 Disable 1 Enable 0 R W 0x0 5 3 2 PMU DVFS Control Register 1 Default 0x00001010 Offset 0x04 Register Name PMU_DVFS_CTRL_REG1 Read Wr Default ae Bit Description ite Hex 31 24 PLL_STAB_TIME 23 8 R W 0x10 PLL stable time SM_INTV_VALUE Smooth interval value 7 0 R W 0x10 5 3 3 PMU DVES Control Register 2 Offset OxOC Register Name PMU_DVFS_CTRL_REG2 Read Wr Default Bit Description ite Hex 31 1 VOLT_SET_EN 0 R W 0x0 Voltage Set Enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 It will be auto cleared after the voltage setting command is sent successfully Set this bit to 1 will start the voltage setting set the CPUVDD register value to the external PMU IC through the TWI interface Note This bit can not be set to one if the VoltageChangeEnable bit in the DVFS Ctrl register 0 is set to 1 5 3 4 PMU AXI Clock Range Register0 Offset 0x20 Register Name PMU_AXI_AUTO_SWT_REGO Read Wr Default SS Bit Description ite Hex 31 27 AXI_CLK_LEV
215. _EN CSC by pass enable 0 CSC enable 1 CSC will be by passed Actually in order to ensure the module working to be correct this bit only can be set when input data format is the same as output data format both YUV or both RGB 27 5 4 DEFE_AGTH_SEL_REG Offset OxC Register Name DEFE_AGTH_SEL_REG Bit Read Wr ite Default Hex Description R W 0x0 LINEBUF_AGTH A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 296 Ou 7 Allwinner Technology CO Ltd A13 DEFE line buffer algorithm select 0 horizontal filtered result 1 original data 7 0 27 5 5 DEFE_LINT_CTRL_REG Offset 0x10 Register Name DEFE_LINT_CTRL_REG Read Wr Default L Bit Description ite Hex 31 28 27 16 R 0x0 CURRENT_LINE FIELD_SEL Field select 15 R W 0x0 0 each field 1 end field field counter in reg0x2c 14 13 TRIG_LINE 12 0 R W 0x0 oe Trigger line number of line interrupt 27 5 6 DEFE BUF ADDRO REG Offset 0x20 Register Name DEFE_BUF_ADDRO_REG Read Wr Default PNS Bit f Description ite Hex BUF_ADDR DEFE frame buffer address In tile based type 31 0 R W 0x0 The address is the start address of the line in the first tile used to generate output frame In non
216. _IDLE_RL_EN CPU idle Counter Read Latch Enable 1 R W 0x0 i eee 0 no effect 1 to latch the idle Counter to the Low Hi registers and it will change to zero after the registers are latched 0 R W 0x0 CPU_IDLE_CNT_CLR_EN A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 48 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 CPU idle Counter Clear Enable 0 no effect 1 to clear the idle Counter Low Hi registers and it will change to zero after the registers are cleared 5 3 44 CPU Idle Status Register Default 0x00000000 Offset OxFC Register Name CPU IDLE STATUS REG Read Wr Default aa Bit Description ite Hex 31 1 CPU_IDLE_STA CPU idle exit finished pending 0 R W 0x0 0 no effect 1 idle exit finished Set 1 to this bit will clear it A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 49 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 6 Clock Control Module CCM 6 1 Overview The Clock Control Module CCM is made up of 7 PLLs a Main Oscillator and an on chip RC Oscillator The 24 MHz crystal is mandatory and to generate input clock source for PLLs and main digital blocks In order to provide high performance low power consumption and user friendly interfaces the chip includes several clock domains CPU clock AHB clock APB clock and special clock
217. _KEY_IRQ Ka Control Logic gt ADC REF ER I 25 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 254 Jau 8 2013 GW 7 Allwinner Technology CO Ltd A13 24 3 LRADC Register Description 24 3 1 LRADC Control Register Offset 0x04 Register Name LRADC INTC Bit Read W Default Description rite Hex 31 16 12 R W 0x0 ADC1 KEYUP IRQ EN ADC 1 Key Up IRQ Enable 0 Disable 1 Enable 11 R W 0x0 ADC1_ALRDY_HOLD_IRQ_EN ADC 1 Already Hold Key IRQ Enable 0 Disable 1 Enable 10 R W 0x0 ADC 1 Hold Key IRQ Enable 0 Disable 1 Enable 9 R W 0x0 ADC1 KEYIRQ EN ADC 1 Key IRQ Enable 0 Disable 1 Enable 8 R W 0x0 ADC1_DATA_IRQ_EN ADC 1 DATA IRQ Enable 0 Disable 1 Enable T 5 4 R W 0x0 ADCO KEYUP IRQ EN ADC 0 Key Up IRQ Enable 0 Disable 1 Enable 3 R W 0x0 ADCO_ALRDY_HOLD_IRQ_EN ADC 0 Already Hold IRQ Enable 0 Disable 1 Enable 2 R W 0x0 ADCO HOLD IRQ EN ADC 0 Hold Key IRQ Enable 0 Disable 1 Enable 1 R W 0x0 ADCO KEYDOWN EN ADC 0 Key Down Enable A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 255 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd 0 Disable 1 Enable A13 0 R W 0x0 ADCO_DATA_IRQ_EN ADC 0 Data IRQ Enable 0 Disable 1 Enable 24 3 2 LRADC Interrupt Control Register Offset 0x04 Register Na
218. ability Parameter Register Register Name HCCPARAMS Offset 0x08 Default Value Implementation Dependent Bit Read Write Default Description Reserved 31 16 0 These bits are reserved and should be set to zero EHCI Extended Capabilities Pointer EECP This optional field indicates the existence of a capabilities list A value of 15 18 R 0 00b indicates no extended capabilities are implemented A non zero A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 210 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 value in this register indicates the offset in PCI configuration space of the first EHCI extended capabiliby The pointer value must be 40h or greater if implemented to maintain to consistency of the PCI header defined for this calss of device The value of this field is always 00b Isochronous Scheduling Threshold This field indicates relative to the current position of the executing host controller where software can reliably update the isochronous schedule When bit 7 is zero the value of the least significant 3 bits indicates the number of micro frames a host controller can hold a set of isochronous data structures one or more before flushing the state When bit 7 is a one then host software assumes the host controller may cache an 7 4 R isochronous data structure for an entire frame Reserved 3 R 0 These bits are reserved and shou
219. able 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note Time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 10 ASYNC Timer 2 Interval Value Register Offset 0x34 Register Name ASYNC_TMR2_INTV_VALUE_REG Read Wr Default SA Bit Description ite Hex TMR2_INTV_VALUE 31 0 R W x Timer 2 Interval Value Note The value setting should consider the system clock and the timer clock source A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 94 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 11 3 11 ASYNC Timer 2 Current Value Register Offset 0x38 Register Name ASYNC_TMR2_CURNT_VALUE_REG Read Wr Default Bit Description ite Hex TMR2_CUR_VALUE Timer 2 Current Value 31 0 R W x
220. ad Port Owner This bit unconditionally goes to a Ob when the Configured bit in the CONFIGFLAG register makes a Ob to 1b transition This bit unconditionally goes to 1b whenever the Configured bit is zero System software uses this field to release ownership of the port to selected host controller in the event that the attached device is not a high speed device Software writes a one to this bit when the attached device is not a high speed device A one in this bit means that a companion host controller owns and controls the port 13 R W Default Value 1b Reserved These bits are reserved for future use and should return a value of zero 12 when read Line Status These bits reflect the current logical levels of the D bitll and D bit10 signal lines These bits are used for detection of low speed USB devices prior to port reset and enable sequence This read only field is valid only when the port enable bit is zero and the current connect status bit is set to a one The encoding of the bits are Bit 11 10 USB State Interpretation 00b SEO Not Low speed device perform EHCI reset 10b J state Not Low speed device perform EHCI reset O1b K state Low speed device release ownership of 11 10 R port A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 220 Jau 8 2013 7 Allwinner Technology CO Ltd A13 11b Undefined Not Low speed device perform EHCI reset This value of this field is
221. ame IMGEHC WBLINEWIDTH REG Read Wri Default Description WB LINEWIDTH 31 0 R W f aa Write back image buffer line width in BYTE 30 2 11 Luminance Histogram Control Register Offset 0X0030 Register Name IMGEHC_LHC_REG Read Wri Default Description 0 Current frame case 1 Average case LH_REC_CLR If the bit is set all of the luminance statistics recording registers will be cleared and the bit will self clear when the recording registers is cleared 30 2 12 Luminance Histogram Threshold Setting Register 0 Offset 0X0034 Register Name IMGEHC_LHT_REGO Read Wri Default a Bit Description te Hex LH_THRES_VAL4 31 24 R W 0x80 Step4 threshold value LH_THRES_VAL3 23 16 R W 0x60 Step3 threshold value LH_THRES_VAL2 15 08 R W 0x40 Step2 threshold value LH THRES VALI 07 00 R W 0x20 Step1 threshold value 30 2 13 Luminance Histogram Threshold Setting Register 1 Offset 0X0038 Register Name IMGEHC_LHT_REG1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 368 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Step7 threshold value LH_THRES_VAL6 LH THRES VALS When set IMGEHC LHT REGO and IMGEHC LHT REGI make sure that THRES VALI lt THRES VAL2 lt lt THRES VALT 30 2 14 Luminance Histogram Statistics Lum Recording Register Offset 0X0040 0X005C Register Name IMGEHC_LHSLUM_REG Read Wri Default a Bit Description te Hex LH_LUM_DATA
222. ample Word Counter 0x0 TP_IDLE_FLG Touch Panel Idle Flag 0 idle 1 not idle 0x0 TP_UP_PENDING Touch Panel Last Touch Stylus Up IRQ Pending bit 0 No IRQ 1 IRQ Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 0x0 TP_DOWN_PENDING Touch Panel First Touch Stylus Down IRQ Pending bit 0 No IRQ 1 IRQ Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 25 6 7 TP Temperature Period Register Offset 0x18 Register Name TP_TPR Bit Read Wr Default Description ite Hex 31 16 16 R W 0x0 TEMP EN Temperature enable 15 0 R W 0x0 TEMP_PER Temperature Period 4096 Tclk_in A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 273 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 25 6 8 Common Data Register Offset Ox1c Register Name TP CDAT Bit Read Wr Default Description ite Hex Default 0x0000 0000 31 12 11 0 R W 0x0 TP_CDAT TP Common Data 25 6 9 TP Data Register Offset 0x24 Register Name TP_DATA Bit Read Wr Default Description ite Hex 31 12 11 0 R 0x0 25 6 10 TP Port IO Configure Register Offset 0x28 Register Name TP_IO_CONFIG Bit Read Wr Default Description
223. and active MCR 6 set to one the sir_out_n line is continuously pulsed When in Loopback Mode the break condition is internally looped back R W 0 to the receiver and the sir_out_n line is forced low 3 EPS Even Parity Select It is writeable only when UART is not busy USR 0 is zero and always writable readable This is used to select between even and odd parity when parity is enabled PEN set to one 0 Odd Parity 4 R W 0 1 Even Parity A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 191 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 PEN Parity Enable It is writeable only when UART is not busy USR 0 is zero and always readable This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively 0 parity disabled 3 R W 0 1 parity enabled STOP Number of stop bits It is writeable only when UART is not busy USR 0 is zero and always readable This is used to select the number of stop bits per character that the peripheral transmits and receives If set to zero one stop bit is transmitted in the serial data If set to one and the data bits are set to 5 LCR 1 0 set to zero one and a half stop bits is transmitted Otherwise two stop bits are transmitted Note that regardless of the number of stop bits selected the receiver checks only the first stop bit 0 1 stop bit
224. ans that each location of the frame list is accessed 8 times frames or Micro frames before moving to the next index The following illustrates Values of N based on the value of the Frame List Size field in the USBCMD register USBCMD Frame List Size Number Elements N 00b 1024 12 O1b 512 11 10b 256 10 11b Reserved Note This register must be written as a DWord Byte writes produce undefined results 22 5 10 EHCI Periodic Frame List Base Address Register Register Name PERIODICLISTBASE Offset 0x24 Default Value Undefined Bit Read Write Default Description Base Address These bits correspond to memory address signals 31 12 respectively This register contains the beginning address of the Periodic Frame List in the system memory System software loads this register prior to starting the schedule execution by the Host Controller The memory structure referenced by this physical memory pointer is assumed to be 4 K byte aligned The contents of this register are combined with the Frame Index Register FRINDEX to enable the Host Controller to step through the Periodic 31 12 R W Frame List in sequence Reserved Must be written as 0x0 during runtime the values of these bits are 11 0 undefined Note Writes must be Dword Writes 22 5 11 EHCI Current Asynchronous List Address Register Register Name ASYNCLISTADDR Offset 0x28 Default Value
225. attribute control register1 01 00 PS pixels sequence Mono or Internal Frame Buffer 1 Bpp Or Palette 1 Bpp Mode FBF 0000 PS 00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 Pll P1O POO P08 PO7 PO6 POS P04 PO3 PO2 POI POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P24 P25 P26 P27 P28 P29 P30 P31 P16 P17 P18 P19 P20 P21 P22 P23 P08 POO P10 Pll P12 P13 P14 P15 POO POI PO2 PO3 PO4 POS P06 P07 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO7 P06 POS P04 P03 PO2 PO1 POO P15 P14 P13 P12 Pll P10 POO PO8 P23 P22 P21 P20 P19 P18 P17 P16 P31 P30 P29 P28 P27 P26 P25 P24 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 11 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 329 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd
226. bit 01 16 bit 10 32 bit 11 24 23 R W 0x0 DDMA_DST_BST_LEN DMA Destination Burst Length 00 1 01 4 10 8 11 22 21 R W 0x0 DDMA_ADDR_MODE DMA Destination Address Mode DMA Source Address Mode 0x0 Linear Mode 0x1 IO Mode 0x2 Horizontal Page Mode 0x3 Vertical Page Mode 20 16 R W 0x0 DDMA_DST_DRQ_SEL Dedicated DMA Destination DRQ Type 0x0 SRAM memory 0x1 SDRAM memory 0x2 0x3 NAND Flash Controller NFC 0x4 USBO 0x5 0x6 0x7 0x8 SPI TX 0x9 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 147 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 OxA Security System TX OxB OxC OxD OxE TCONO OXF 0x10 Ox11 0x12 Ox13 Ox14 Ox15 Ox16 Ox17 Ox18 0x19 Ox1A SPIO TX Ox1B Ox1C SPR TX Ox1D Ox1E Ox1F BC MODE SEL BC mode select 15 R W 0x0 0 normal mode the value read back equals to the value that is written 1 remain mode the value read back equals to the remain counter to be transferred 14 11 DDMA_SRC_DATA_WIDTH DMA Source Data Width 00 8 bit 01 16 bit 10 32 bit 11 10 9 R W 0x0 DDMA_SRC_BST_LEN DMA Source Burst Length 00 1 01 4 10 8 11 8 7 R W 0x0 DDMA_SRC_ADDR_MODE DMA Source Address Mode 6 5 R W 0x0 A1
227. ble Register 18 valid 5 R W Ox1 0 valid 1 invalid VF_TABLE_17_VALID PMU V F Table Register 17 valid 4 R W Ox1 0 valid 1 invalid VF TABLE 16 VALID PMU V F Table Register 16 valid 3 R W 0x1 f 0 valid 1 invalid VF TABLE 15 VALID 2 R W Ox1 f PMU V F Table Register 15 valid A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 44 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 valid 1 invalid VF TABLE 14 VALD PMU V F Table Register 14 valid 1 R W 0x0 0 valid 1 invalid VF_TABLE_13_VALID PMU V F Table Register 13 valid 0 R W 0x0 0 valid 1 invalid 5 3 36 PMU VF Table Index Register Offset OxDO Register Name PMU_VF_TABLE_INDEX_REG Read Wr Default Bit Description ite Hex 31 2 VF_TABLE_IDX PMU V F Table Index 00 1 0 R W 0x0 Ol 10 11 5 3 37 PMU VF Table Range Register Offset OxD4 Register Name PMU VF TABLE RANGE REG Read Wr Default SECH Bit Description ite Hex 31 24 VF TABLE RNG2 23 16 R W 0x0 PMU V F Table Range 2 VF_TABLE_RNGI 15 8 R W 0x0 PMU V F Table Range 1 VF_TABLE_RNGO 7 0 R W 0x0 PMU V F Table Range 0 5 3 38 PMU Speed Factor Register 0 Offset OxEO Register Name PMU_SPEED_FACTOR_REGO Read Wr Default Bit Description ite Hex SPD_DET_EN 31 R W 0x0 Speed Detect Enable 0 Disable
228. c Median filter Controller Register TP_INT_FIFOC 0x10 TP Interrupt FIFO Control Register TP_INT_FIFOS 0x14 TP Interrupt FIFO Status Register TP_TPR 0x18 TP Temperature Period Register TP_DATA 0x20 TP Data Register 25 6 TP Register Description 25 6 1 TP Control Register 0 Offset 0x00 Default Hex OxF Description ADC_FIRST_DLY Register Name TP_CTRL ADC First Convert Delay setting A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 268 AW A Y Allwinner Technology CO Ltd A13 Based on ADC First Convert Delay Mode select 1 D N LA ADC_FIRST_DLY_MODE ADC First Convert Delay Mode Select 0 CLK_IN 16 1 CLK_IN 16 256 ADC_CLK_SELECT ADC Clock Source Select 0 HOSC 24MHZ 1 Audio PLL R W 0x0 21 20 R W 0x0 R W 19 16 E 0x0 15 0 R W 0x0 ADC_CLK_DIVIDER ADC Clock Divider CLK_IN 00 CLK 2 01 CLK 3 10 CLK 6 11 CLK 1 In TP mode these two bits must set 1x FS_DIV ADC Sample Frequency Divider 0000 CLK_IN 2 20 n 0001 CLK_IN 2 20 n 0010 CLK_IN 2 20 n 1111 CLK_IN 32 T_ACQ Touch panel ADC acquire time CLK_IN 16 N 25 6 2 TP control Register 1 Offset 0x04 Register Name TP_CTRL1 Read Default Description Write Hex R W 0x0 STYLUS_UP_DEBOUNCE Stylus Up De bounce Time setting 0x00 0 Oxff 2N CLK_IN 16 256 9 R W 0x0 STY
229. ch implemented port is A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 211 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 mapped This field is a 15 element nibble array each 4 bit is one array element Each array location corresponds one to one with a physical port provided by the host controller e g PORTROUTE 0 corresponds to the first PORTSC port PORTROUTE 1 to the second PORTSC port etc The value of each element indicates to which of the companion host controllers this port is routed Only the first N PORTS elements have valid information A value of zero indicates that the port is routed to the lowest numbered function companion host controller A value of one indicates that the port is routed to the next lowest numbered function companion host controller and so on 22 5 6 EHCI USB Command Register Offset 0x10 Register Name USBCMD Default Value 0x00080000 0x00080B00 if Asynchronous Schedule Park Capability is a one Bit Read Write Default Description 31 24 Reserved These bits are reserved and should be set to zero 23 16 R W 0x08 Interrupt Threshold Control The value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts The only valid values are defined below Value Minimum Interrupt Interval 0x00 Reserved 0x01 1 micro
230. condition or by host software Note that the bit status does not change until the port state actually changes There may be a delay in disabling or enabling a port due to other host controller and bus events When the port is disabled downstream propagation of data is blocked on this port except for reset The default value of this field is 0 This field is zero if Port Power is zero R WC Connect Status Change 1 Change in Current Connect Status 0 No change Default 0 Indicates a change has occurred in the port s Current Connect Status The host controller sets this bit for all changes to the port device connect status even if system software has not cleared an existing connect status change For example the insertion status changes twice before system software has cleared the changed condition hub hardware will be setting an already set bit Software sets this bit to 0 by writing a I to it This field is zero if Port Power is zero 0 R 0 Current Connect Status Device is present on port when the value of this field is a one and no device is present on port when the value of this field is a zero This value reflects the current state of the port and may not correspond directly to the event that caused the Connect Status Change Bit 1 to be set This field is zero if Port Power zero Note This register is only reset by hardware or in response to a host controller reset A13 User Ma
231. d R W R W 0x0 SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be Incremented 22 6 5 HcInterruptEnable Register Offset 0x410 Register Name HcInterruptEnable Register Default Value 0x0 Read Write Bit HCD HC Default Description MasterInterruptEnable A 0 writtern to this field is ignored by HC A 1 written to this field enables interrupt generation due to events specified in the other bits of 31 R W R 0x0 this register This is used by HCD as Master Interrupt Enable 30 7 0x0 Reserved RootHubStatusChange Interrupt Enable 0 Ignore 6 R W R 0x0 1 Enable interrupt generation due to Root Hub Status Change FrameNumberOverflow Interrupt Enable 0 Ignore 1 Enable interrupt generation due to Frame Number Over Flow 5 R W R 0x0 UnrecoverableError Interrupt Enable 0 Ignore 4 R W IR 0x0 1 Enable interrupt generation due to Unrecoverable Error ResumeDetected Interrupt Enable 3 R W R 0x0 0 Ignore A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 228 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 Enable interrupt generation due to Resu
232. d 40 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 This register can only be written if the DVFS function is disabled 5 3 19 PMU VF Table Register 3 Offset Ox8C Register Name PMU_VF_TABLE_REG3 Bit DO Po Description ite Hex 31 11 CPU MAX FREQ 085 10 0 R W D CPU max frequency if cpuvdd 0 85v unit MHz This register can only be written if the DVFS function is disabled 5 3 20 PMU VF Table Register 4 Offset 0x90 Register Name PMU_VF_TABLE_REG4 Bit eee eee Description ite Hex 31 11 CPU MAX FREQ 090 10 0 R W D CPU max frequency if vddepu 0 9v unit MHz This register can only be written if the DVFS function is disabled 5 3 21 PMU VF Table Register 5 Offset 0x94 Register Name PMU VF TABLE REG5 Bit TAN Description ite Hex 31 11 CPU MAX FREQ 095 10 0 R W D CPU max frequency if cpuvdd 0 95v unit MHz This register can only be written if the DVFS function is disabled 5 3 22 PMU VF Table Register 6 Offset 0x98 Register Name PMU_VF_TABLE_REG6 Bit poe Co Description ite Hex 31 11 CPU_MAX_FREQ_ 100 10 0 R W D CPU max frequency if cpuvdd 1 0v unit MHz This register can only be written if the DVFS function is disabled 5 3 23 PMU VF Table Register 7 Offset 0x9C Register Name PMU_VF_TABLE_REG7 Bit Read Wr Default Description A13
233. d 58 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 If the bypass is enabled the PLLA output is 24MHz 29 25 R W 0x10 24 20 R W 0x10 19 R W 0x1 18 l PLL4_OUT_EXT_DIV_P 17 16 R W 0x0 PLL4 Output external divider P The range is 1 2 4 8 15 13 PLL4_FACTOR_N PLL4 Factor N Factor 0 N 0 12 8 R W 0x10 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 6 l PLL4_FACTOR_K 5 4 R W 0x0 PLL4 Factor K K Factor 1 The range is from I to 4 3 2 Is PLL4_FACTOR_M 1 0 R W 0x0 PLL4 Factor M M Factor 1 The range is from 1 to 4 6 4 7 PLL5 DDR Default 0x11049280 Offset 0x20 Register Name PLL5_CFG_REG Read Wr Default WM Bit Description ite Hex PLL5 Enable 0 Disable 1 Enable The PLLS output for DDR 24MHz N K M 31 R W 0x0 The PLLS output for other module 24MHz N K P The PLLS output is for the DDR Note the output 24MHz N K clock must be in the range of 240MHz 2GHz if the bypass is disabled PLL5 OUT BYPASS EN PLLS Output Bypass Enable 30 R W 0x0 0 Disable 1 Enable If the bypass is enabled the PLL6 output is 24MHz DDR_CLK_OUT_EN 29 R W 0x0 DDR clock output en A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 59 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13
234. e 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 0 R W 0x0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time 12 3 4 Sync Timer 0 Interval Value Low Register Offset 0x14 Register Name SYNC_TMRO_INTV_LO_REG Read Wr Default GE Bit Description ite Hex STMRO_INTV_VALUE_LO 31 0 R W x Sync Timer 0 Interval Value 31 0 12 3 5 Sync Timer 0 Interval Value High Register Offset 0x18 Register Name SYNC_TMRO_INTV_HI_REG Read Wr Default xf Bit Description ite Hex 31 24 STMRO_INTV_VALUE_HI 23 0 R W x Sync Timer 0 Interval Value 55 32 Note the interval value register is a 56 bit register When read or write the interval value the Low register should be read or write first And the High register should be written after the Low register 12 3 6 Sync Timer 0 Current Value Lo Register Offset Ox1C Register Name SYNC TMRO CURNT LOW REG Read Wr Default Bit Descripti
235. e PORTSC Default Value 0x00002000 w PPC set to one 0x00003000 w PPC set to Offset 0x54 a zero Bit Read Write Default Description Reserved These bits are reserved for future use and should return a value of zero 31 22 0 when read Wake on Disconnect Enable WKDSCNNT E Writing this bit to a one enables the port to be sensitive to device disconnects as wake up events This field is zero if Port Power is zero 21 R W 0 The default value in this field is 0 Wake on Connect Enable WKCNNT E Writing this bit to a one enable the port to be sensitive to device connects as wake up events This field is zero if Port Power is zero 20 R W 0 The default value in this field is 0 Port Test Control 19 16 R W 0 The value in this field specifies the test mode of the port The encoding A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 219 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 of the test mode bits are as follow Bits Test Mode 0000b The port is NOT operating in a test mode 0001b Test J STATE 0010b Test K STATE 0011b Test SEO NAK 0100b Test Packet 0101b Test FORCE ENABLE 0110b 1111b Reserved The default value in this field is 0000b Reserved These bits are reserved for future use and should return a value of zero 15 14 R W when re
236. e Function Select 0 Disable 1 Enable 12 8 R W OxF TP_FIFO_TRIG_LEVEL TP FIFO Data Available Trigger Level Interrupt and DMA request trigger level for TP or Auxiliary ADC Trigger Level TXTL 1 7 R W 0x0 TP_DATA_DRQ_EN TP FIFO Data Available DRQ Enable 0 Disable 1 Enable 6 5 R W 0x0 TP_FIFO_FLUSH TP FIFO Flush Write 1 to flush TX FIFO self clear to 0 3 2 1 R W 0x0 TP UP IRQ EN Touch Panel Last Touch Stylus Up IRQ Enable 0 Disable 1 Enable 0 R W 0x0 TP_DOWN_IRQ EN Touch Panel First Touch Stylus Down IRQ Enable 0 Disable 1 Enable 25 6 6 TP Interrupt amp FIFO Status Register Offset 0x14 Register Name TP_FIFOCS Bit Read Wr Default Description ite Hex 31 19 18 R W 0x0 17 R W 0x0 FIFO_OVERRUN_PENDING TP FIFO Over Run IRQ pending A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 272 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 No Pending IRQ 1 FIFO Overrun Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 16 R W 0x0 FIFO_DATA_PENDING TP FIFO Data Available pending Bit 0 NO Pending IRQ 1 FIFO Available Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 15 13 12 8 R 0x0 RXA_CNT TP FIFO available S
237. e asserted N is defined here 22 21 R W 0x0 000 IRQ DRQ Deasserted when WLEVEL gt TXTL 01 4 10 8 11 16 20 15 TX FIFO Empty Trigger Level TXTL 6 0 14 8 R W 0x10 Interrupt and DMA request trigger level for TX FIFO normal condition IRQ DRQ Generated when WLEVEL lt TXTL ADDA_LOOP_EN 7 R W 0x0 ADDA loop Enable adda 0 Disable 1 Enable DAC_MONO_EN 6 R W 0x0 DAC Mono Enable 0 Stereo 64 levels FIFO A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 244 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 mono 128 levels FIFO When enabled L amp R channel send same data TX SAMPLE BITS Transmitting Audio Sample Resolution 0 16 bits 1 24 bits 5 R W 0x0 DAC_DRQ_EN DAC FIFO Empty DRQ Enable 0 Disable 1 Enable 4 R W 0x0 DAC IRQ EN DAC FIFO Empty IRQ Enable 0 Disable 1 Enable 3 R W 0x0 FIFO UNDERRUN IRQ EN DAC FIFO Under Run IRQ Enable 0 Disable 1 Enable 2 R W 0x0 FIFO_OVERRUN_IRQ_EN DAC FIFO Over Run IRQ Enable 0 Disable 1 Enable 1 R W 0x0 FIFO_FLUSH 0 R W 0x0 DAC FIFO Flush Write 1 to flush TX FIFO self clear to 0 23 4 3 DAC FIFO Status Register Offset Ox8 Register Name AC_DAC_FIFOS Bit Read Write Default Description 31 24 TX_EMPTY TX FIFO Empty 23 R Ox1 0 No room for new sample in TX FIFO 1 More
238. e end means filed end 26 4 10 CSI Interrupt Enable Register Register Name CSI INT EN REG Offset Address 0X0030 Default Value 0X00000000 Read Wri Default i jan JE Pcs O te Hex VSYNC_FLAG vsync flag The bit is set when vsync come And at this time load the buffer address for the coming frame So after this irq comes change the buffer address could only affect next frame HB_OF Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 281 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 PRT ERR Protection error Indicates a protection error has been detected Applies only when the 656 protocol is selected FIFOO_OF 03 R W FIFO1 overflow The bit is set when the FIFO 1 overflows FIFOO overflow 02 R W The bit is set when the FIFO 0 overflows FRM_DONE Frame done Indicates the CSI finishes capturing an image frame Applied to video capture mode The bit is set after each completed frame capturing data is written to buffer as long as video capture remains enabled CPT_DONE Capture done Indicates the CSI has completed capturing the image data For still capture the bit is set when one frame data has been written to For video capture the bit is set when the last frame has been written to buffer after video capture is disabled For CCIR656 interface if the output format is fra
239. e equals to coefficient 2 27 5 25 DEFE CSC COEFO3 REG Offset 0x7C Register Name DEFE_CSC_COEF03_REG Read Wr Default SC Bit i Description ite Hex 31 14 CONT 13 0 R W 0x0 the Y G constant the value equals to coefficient 2 27 5 26 _DEFE_CSC_COEF10_REG Offset 0x80 Register Name DEFE_CSC_COEF10_REG Read Wr Default SE Bit Description ite Hex 31 13 COEF 12 0 R W 0x0 the U R coefficient the value equals to coefficient 2 27 5 27 DEFE_CSC_COEF11_REG Offset 0x84 Register Name DEFE_CSC_COEF11_REG 8 Read Wr Default oo Bit Description ite Hex 31 13 COEF 12 0 R W 0x0 the U R coefficient the value equals to coefficient 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 27 5 28 DEFE CSC COEFI2 REG Offset 0x88 Register Name DEFE_CSC_COEF12_REG Read Wr Default o Bit f Description ite Hex 31 13 COEF 12 0 R W 0x0 the U R coefficient the value equals to coefficient 2 27 5 29 DEFE CSC COEF13 REG Offset Ox8C Register Name DEFE_CSC_COEF13_REG Read Wr Default L Bit Description ite Hex 31 14 d CONT 13 00 R W 0x0 the U R constant the value equals to coefficient 2 27 5 30 DEFE CSC COEF20 REG
240. e error interrupt occurred also had its IOC bit set both This bit and USBINT bit are set R WC USB Interrupt USBINT The Host Controller sets this bit to a one on the completion of a USB transaction which results in the retirement of a Transfer Descriptor that had its IOC bit set The Host Controller also sets this bit to 1 when a short packet is detected actual number of bytes received was less than the expected number of A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 216 Jau 8 2013 7 Allwinner Technology CO Ltd A13 bytes 22 58 EHCI USB Interrupt Enable Register Register Name USBINTR Offset 0x18 Default Value 0x00000000 Bit Read Write Default Description Reserved 31 6 0 These bits are reserved and should be zero Interrupt on Async Advance Enable When this bit is 1 and the Interrupt on Async Advance bit in the USBSTS register is 1 the host controller will issue an interrupt at the next interrupt threshold The interrupt is acknowledged by software 5 R W 0 clearing the Interrupt on Async Advance bit Host System Error Enable When this bit is 1 and the Host System Error Status bit in the USBSTS register is 1 the host controller will issue an interrupt The interrupt is 4 R W 0 acknowledged by software clearing the Host System Error bit Frame List Rollover Enable When this bit is 1 and the
241. e host controller may hold Port Reset asserted to a one when the HC Halted bit is a one This field is zero if Port Power is zero R W Suspend Port Enabled Bit and Suspend bit of this register define the port states as follows Bits Port Enables Port State Suspend Ox Disable 10 Enable 11 Suspend When in suspend state downstream propagation of data is blocked on this port except for port reset The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1 In the suspend state the port is sensitive to resume detection Not that the bit status does not change until the port is suspend A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 221 Jau 8 2013 AW Allwinner Technology CO Ltd A13 and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB A write of zero to this bit is ignored by the host controller The host controller will unconditionally set this bit to a zero when Software sets the Force Port Resume bit to a zero from a one 2 Software sets the Port Reset bit to a one from a zero If host software sets this bit to a one when the port is not enabled i e Port enabled bit is a zero the results are undefined This field is zero if Port Power is zero The default value in this field is 0 Force Port
242. e of the sync timer 1 clock source 000 1 001 2 010 4 O11 8 100 16 101 110 111 6 4 R W 0x0 3 2 STMR1_RELOAD 1 R W 0x0 Sync Timer 1 Reload 0 No effect 1 Reload timer 1 Interval value A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 107 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 STMRI EN Sync Timer 1 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 R W 0x0 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time 12 3 9 Sync Timer 1 Interval Value Low Register Offset 0x34 Register Name SYNC TMRI1 INTV LOW REG Read Wr Default ae Bit Description ite Hex STMR1_INTV_VALUE_LOW 31 0 R W x Sync Timer Interval Value 31 0 12 3 10 Sync Timer 1 Interval Value High Register Offset 0x38 Register Name SYNC_TMRI_INTV_HI REG Read Wr
243. ead of MSR 1 change on ctsdsr n since last read of MSR Reading the MSR clears the DCTS bit In Loopback Mode MCR 4 1 DCTS reflects changes on MCR 1 RTS Note If the DCTS bit is not set and the cts n signal is asserted low and a reset occurs software or otherwise the DCTS bit is set when the reset is removed if the cts n signal remains asserted 19 4 12 UART Scratch Register Register Name UART SCH Offset Ox1C Default Value 0x0000 0000 Bit Read Write Default Description 31 8 Scratch Register This register is used by programmers as a temporary storage space It has 7 0 R W 0 no defined purpose in the UART 19 4 13 UART Status Register Register Name UART USR Offset 0x7C Default Value 0x0000 0006 Bit Read Write Default Description 31 5 RFF Receive FIFO Full This is used to indicate that the receive FIFO is completely full 0 Receive FIFO not full 1 Receive FIFO Full 4 R 0 This bit is cleared when the RX FIFO is no longer full RFNE Receive FIFO Not Empty This is used to indicate that the receive FIFO contains one or more entries 0 Receive FIFO is empty 1 Receive FIFO is not empty 3 R 0 This bit is cleared when the RX FIFO is empty TFE Transmit FIFO Empty This is used to indicate that the transmit FIFO is completely empty 0 Transmit FIFO is not empty 1 Transmit FIFO is empty 2 R 1 This bit is clear
244. ed 8 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 13 4 13 Interrupt Select Register 2 Default 0x00000000 rasrrrnrrnnvnnnnrnrnrnnnvnnnnrrrnrnrrvnnrnnne 116 13 4 14 Interrupt Enable Register O Default 0x00000000 rrrrnrvnrnvrnnrnvrnnnnrnnrnnrnrenvrnrrnnnn 116 13 4 15 Interrupt Enable Register 1 Default 0x00000000 eerrrnrrrnnnrrnrrennrnnrrnnnrrnrrnnnnrnnnn 117 13 4 16 Interrupt Enable Register 2 Default 0x00000000 rerrnnvrvvnnnnnrrnnnnnnrrnnnrnnrrnnnnennnn 117 13 4 17 Interrupt Mask Register 0 Default Ox00000000 117 13 4 18 Interrupt Mask Register 1 Default Ox00000000 117 13 4 19 Interrupt Mask Register 2 Default Ox00000000 118 13 4 20 Interrupt Response Register 0 Default 0x00000000 eee eeeeeeeeeteneeeeeneeeeeeee 118 13 4 21 Interrupt Response Register 1 Default 0x00000000 eee eeeeeteteeereneeeeeeee 118 13 4 22 Interrupt Response Register 2 Default 0x00000000 ee eee eeeeeeteneeeeeneeeeeee 118 13 4 23 Interrupt Fast Forcing Register 0 Default 0x00000000 eee eeeeeeeeteeeeeeee 119 13 4 24 Interrupt Fast Forcing Register 1 Default 0x00000000 eee eeeeeeteneeeeeeee 119 13 4 25 Interrupt Fast Forcing Register 2 Default 0x00000000 ee eee eeteeeeeteeeeeeee 119 13 4 26 Interrupt Source Priority 0 Register Default Ox00000000
245. ed when the TX FIFO is no longer empty A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 198 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 TFNF Transmit FIFO Not Full This is used to indicate that the transmit FIFO is not full 0 Transmit FIFO is full 1 Transmit FIFO is not full 1 R 1 This bit is cleared when the TX FIFO is full BUSY UART Busy Bit 0 Idle or inactive 0 R 0 1 Busy 19 4 14 UART Transmit FIFO Level Register Register Name UART TFL Offset 0x80 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 Transmit FIFO Level 6 0 R 0 This indicates the number of data entries in the transmit FIFO 19 4 15 UART Receive FIFO Level Register Register Name UART RFL Offset 0x84 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 Receive FIFO Level 6 0 R 0 This indicates the number of data entries in the receive FIFO 19 4 16 UART Halt TX Register Register Name UART HALT Offset OxA4 Default Value 0x0000 0000 Bit Read Write Default Description 31 6 SIR Receiver Pulse Polarity Invert 0 Not invert receiver signal 5 R W 0 1 Invert receiver signal SIR Transmit Pulse Polarity Invert 0 Not invert transmit pulse R W 0 1 Invert transmit pulse 3 1 Halt TX This register is
246. edicated DMA Byte Counter Register N 0 7 Offset 0x300 N 0x20 0Xc Register Name DDMA_BC_REG N 0 1 2 3 4 5 6 7 Read Wr Default Bit Description ite Hex 31 25 DDMA BC 24 0 R W x Dedicated DMA Byte Counter Note If ByteCounter 0 DMA will transfer no byte The maximum value is 0x 1000000 14 4 11 Dedicated DMA Parameter Register Offset 0x300 N 0x20 0x18 Register Name DDMA_PARA_REG N 0 1 2 3 4 5 6 7 Read Wr Default Bi Bit Description ite Hex DEST DATA BLK SIZE Destination Data Block Size n 31 24 R W 0x0 DEST_WAIT_CLK_CYC Destination Wait Clock Cycles n 23 16 R W 0x0 SRC_DATA_BLK_SIZE Source Data Block Size n 15 8 R W 0x0 SRC_WAIT_CLK_CYC Source Wait Clock Cycles n 7 0 R W x Note If the counter is N the value is N 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 150 Allwinner Technology CO Ltd A13 15 NAND Flash Controller NFC 15 1 Overview The NFC supports all NAND MLC flash memory available in the market and new types can be supported by software re configuration as well It can support 2 NAND flash with 3 3 V voltage supply There are 2 separate chip select lines CE to connect up to 2 flash chips with2 R B signals The On the fly error correction code ECC is built in NFC to enhance reliability BCH is
247. een and the PENIRQ output goes low because of the current path through the panel to GND initiating an interrupt to the processor During the measurement cycle for X Y and Z position the X input is disconnected from the PENIRQ pull down transistor to eliminate any pull up resistor leakage current from flowing through the touch screen thus causing no errors AVCC Y Rro Control Logic L ME High when X or Y driver is on y High when X or Y driver is on Figure 25 13 Example of Pen touch Interrupt via Pen Down IRQ 25 4 8 Median and Averaging Filter As explained in the Touch Screen Principles section touch screens are composed of two resistive layers normally placed over an LCD screen Because these layers are in close proximity to the LCD screen noise can be coupled from the screen onto these resistive layers causing errors in the touch screen positional measurements The controller contain a filtering block to process the data and discard the spurious noise before sending the information to the host The purpose of this block is not only the suppression of noise the on chip filtering also greatly reduces the host processing loading The processing function consists of two filters that are applied to the converted results the median filter and the averaging filter The median filter suppresses the isolated out of range noise and sets the number of measurements to be taken These measure
248. egister Name PMU_32KHZ_CPUVDD_MIN_REG Bit EE Pu Description ite Hex 31 8 2 CPUVDD_32KHZ_MIN_VALUE PMU CPUVDD Default Value 7 0 R W Oxc 0x00 0 70v 0x02 0 75v 0x04 0 80v A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 39 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0x06 0 85v 0x08 0 90v Ox0A 0 95v Ox0C 1 00v Ox0E 1 05v 0x10 1 10v 0x12 1 15v 0x14 1 20v Ox16 1 25v 0x18 1 30v OxlA 1 35v Ox1C 1 40v Ox1E 1 45v 0x20 1 50v 0x22 1 55v 0x24 1 60v 5 3 16 PMU VF Table Register 0 Offset 0x80 Register Name PMU VF TABLE REGO Bit EE Geer Description ite Hex 31 11 CPU_MAX_FREQ_070 10 0 R W D CPU max frequency if cpuvdd 0 7v unit MHz This register can only be written if the DVFS function is disabled 5 3 17 PMU VF Table Register 1 Offset 0x84 Register Name PMU VF TABLE REGI Bit E Ce Description ite Hex 31 11 CPU_MAX_FREQ_075 10 0 R W D CPU max frequency if cpuvdd 0 75v unit MHz This register can only be written if the DVFS function is disabled 5 3 18 PMU VF Table Register 2 Offset 0x88 Register Name PMU_VF_TABLE_REG2 Bit EE SC Description ite Hex 31 11 CPU MAX FREQ 080 10 0 R W x CPU max frequency if cpuvdd 0 8v unit MHz A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserve
249. egister Name TWI_EFR Offset Ox1C Default Value 0x0000 0000 Bit Read Write Default Description 31 2 Data Byte follow Read Command Control No Data Byte to be written after read command Only 1 byte data to be written after read command 2 bytes data can be written after read command 0 1 R W 0 3 bytes data can be written after read command 17 49 TWI Line Control Register Register Name TWI_LCR Offset 0x20 Default Value 0x0000 003a Bit Read Write Default Description 31 6 Current state of TWI_SCL 0 low 5 R 1 1 high Current state of TWI_SDA 0 low 4 R 1 1 high TWI_SCL line state control bit When line control mode is enabled bit 2 set value of this bit decide the output level of TWI_SCL 0 output low level 3 R W 1 1 output high level TWI_SCL line state control enable When this bit is set the state of TWI SCL is controlled by the value of bit 3 0 disable TWI_SCL line control mode 2 R W 0 1 enable TWI_SCL line control mode 1 R W 1 TWI SDA line state control bit A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 168 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 When line control mode is enabled bit 0 set value of this bit decides the output level of TWI SDA 0 output low level 1 output high level TWI SDA line state control enable When this
250. el Enable 0 Disable 1 Enable 29 0x0 MIXEN Analog Output Mixer Enable 0 Disable 1 Enable 28 27 26 Ox1 25 23 0x3 22 20 0x3 MICG MIC gain stage to output mixer Gain Control From 4 5dB to 6dB 1 5dB step default is 0dB A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 246 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 19 R W 0x0 18 R W 0x0 17 R W 0x0 16 R W 0x0 LDACLMIXS Left DAC to left output mixer Mute 15 R W 0x0 0 Mute 1 Not mute RDACRMIXS Right DAC to right output mixer Mute 14 R W 0x0 0 Mute 1 Not mute LDACRMIXS Left DAC to right output mixer Mute 13 R W 0x0 0 Mute 1 Not mute MIC LS MIC to output mixer left channel mute 12 R W 0x0 0 mute 1 Not mute MIC RS MIC to output mixer right channel mute 11 R W 0x0 0 mute 1 Not mute 10 R W 0x0 9 R W 0x0 DACPAS DAC to PA Mute 8 R W 0x0 0 Mute 1 Not mute MIXPAS Output Mixer to PA mute 7 R W 0x0 0 Mute 1 Not mute PAMUTE All input source to PA mute including Output mixer and Internal DAC 6 R W 0x0 0 Mute 1 Not mute PAVOL 5 0 R W 0x0 PA Volume Control PAVOL Total 64 level from 0dB to 62dB 1dB step mute when 000000 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 247 Jau 8 2013 Ow Allwinner Technolog
251. elect 000 Input 001 Output 010 SDCO_D2 011 100 101 22 20 R W Ox4 110 111 19 PF4 Select 000 Input 001 Output 010 SDCO D3 Ol 1 100 101 18 16 R W 0x0 110 111 15 PF3 Select 000 Input 001 Output 010 SDCO_CMD 011 14 12 R W Ox4 100 101 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 400 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 110 111 11 PF2 Select 000 Input 001 Output 010 SDCO_CLK 011 100 101 10 8 R W 0 110 111 7 PF1 Select 000 Input 001 Output 010 SDCO_DO 011 100 101 6 4 R W Ox4 110 111 PFO Select 000 Input 001 Output 010 SDCO_D1 011 100 101 2 0 R W Ox4 110 111 33 4 38 PF Configure Register 1 Register Name PF_CFG1 Offset OxB8 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 39 PF Configure Register 2 Register Name PF_CFG2 Offset OxBC Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 40 PF Configure Register 3 Register Name PF_CFG3 Offset OxCO Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 41 PF Data Register Register Name PF_DAT Offset OxC4 Default Value 0x0000 0000 A13 User Manual V1 2 Cop
252. ell Clock 0x0130 CSI_CFG_REG 0x0134 CSI Clock 0x0138 VE_CFG_REG 0x013C Video Engine Clock AUDIO_CODEC_SCLK_CFG_REG 0x0140 Audio Codec Gating Special Clock AVS_SCLK_CFG_REG 0x0144 AVS Gating Special Clock 0x0148 0x014C 0x0150 MALI CLOCK CFG REG 0x0154 Mali400 Gating Special Clock 0x0158 MBUS SCLK CFG REG 0x015C MBUS Gating Clock IEP SCLK CFG REG 0x0160 IEP Gating Clock 6 4 CCM Register Description 64 1 PLL1 Core Default 0x21005000 Offset 0x00 Register Name PLL1 CFG REG Read Wr Default a Bit Description ite Hex PLL1_Enable 31 R W 0x0 0 Disable 1 Enable The PLL1 output 24MHz N K M P A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 55 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 The PLL1 output is for the CORECLK Note the output 24MHz N K clock must be in the range of 240MHz 2GHz if the bypass is disabled Its default is 384MHz 30 18 PLL1 OUT EXT DIVP 17 16 R W 0x0 PLL1 Output external divider P The range is 1 2 4 8 15 13 l PLL1_FACTOR_N PLLI Factor N Factor 0 N 0 12 8 R W 0x10 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 6 PLL1_FACTOR_K 5 4 R W 0x0 PLLI1 Factor K K Factor 1 The range is from 1 to 4 3 R W 0x0 2 R W 0x0 PLL1 FACTOR M 1 0 R W 0x0 PLLI1 Fact
253. ence there is no voltage drop in Ry or Ry Due to the ratiometric measurement method the supply voltage does not affect measurement accuracy The voltage references VREF and VREF are taken from after the matrix switches so that any voltage drop in these switches has no effect on the ADC measurement Y co ordinate measurements are similar to X co ordinate measurements with the X and Y plates interchanged In Single Touch mode only need to test X Y signal X POSITION We NNN TOUCH M N X POSITION ei ms S gt Figure25 10 Single Touch X Position Measurement 25 4 5 Dual Touch Detection The principle of operation is illustrated below For an X co ordinate measurement the X pin is internally switched to AVCC and X to GND The X plate becomes a potential divider and the voltage at the point of contact is proportional to its X co ordinate This voltage is measured on the Y and Y which carry no current hence there is no voltage drop in Ry or Ry Due to the ratiometric measurement method the supply voltage A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 264 Jau 8 2013 AW Allwinner Technology CO Ltd A13 does not affect measurement accuracy The voltage references VREF and VREF are taken from after the matrix switches so that any voltage drop in these switches has no effect on the ADC measurement the controller will need to test X X Y Y and record
254. ens cnstinnstaantandtonatanstanctendtanadanddanndenddanddendandbare 168 17 4 10 TWI DVFS el dee RE 169 17 5 TWI Controller Special Requirement sisi 169 17 5 1 DIN 169 17 5 2 ZEIEN urdu 169 18 Serial Periphral Interfaces scscicccssscsssosssscsscsssosesssnsscscsrssesecasessvessvacesssessostuesessosssodesaseacssotscesessseonvesedaseaeses 171 18 1 1 0 5 EE 171 18 2 SPI imine Diagramme M din KEEN NEE Eege dee 171 18 3 SPI Register LIST nt anna names eee sient ee 172 IC e RER e e 173 18 4 1 SPI PR 173 18 4 2 SPI TA Data Register a ei AS SC PE AC NC 173 18 4 3 SPI Control e 173 18 4 4 SPI Interrupt Control Register a ce cece eet ec cence 176 18 4 5 SPI Interrupt Status E 177 18 4 6 SPI DMA Control EE 179 18 4 7 SPI Wait Clock e EE 180 18 4 8 SPI Clock Control Register nus nn nn 180 18 4 9 PEN TEN 181 18 4 10 SPI Transmit Counter Register ccc ett cet nee 181 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 10 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 18 4 11 SPI FFO Status ASG Paean nena ena 182 18 5 e RER UE 182 18 5 1 SPI Pin LS as 182 18 5 2 SPI Module Clock Source and Frequency 2 cesc ies desscesscnse cee decs dedscctcceees 183 19 Universal Asynchronous Receiver Transmitter Interface ses 184 19 1 10 E 184 19 2 UART Timing RE 184 19 3 UART Register EE 185 194 UART Register Dest enee 185 19 4 1 UART Receiver Buff
255. ent bit control Os normal polarity 1s invert the specify output 29 3 19 TCONO IO TRI REG Offset 0x08C Register Name TCONO IO control register Bit Read Wr ite Default Hex Description 31 28 27 R W 103_Output_Tri_En 1 disable 0 enable 26 R W 102_Output_Tri_En 1 disable 0 enable 25 R W IO1 Output Tri En 1 disable 0 enable 24 R W IO0 Output Tri En 1 disable 0 enable 23 0 R W OxFFFF FF Data Output Tri En TCONO output port D 23 0 output enable with independent bit control Is disable Os enable A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 358 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 29 3 20 TCONI CTL REG Offset 0x090 Register Name TCONI control register Read Wr Default 2 Bit Description ite Hex TCONI_En 31 R W 0 0 disable 1 enable 30 21 Interlace_En 20 R W 0 O disable l enable 19 9 Start Delay 8 4 R W 0 eat This is for DE and DE2 29 3 21 TCONI BASICO_REG Offset 0x094 Register Name TCONI basic timing register0 Read Wr Default Bit Description ite Hex 31 27 TCONI1 XI 27 16 R W 0 ae source width is X 1 15 12 TCONI_YI 11 0 R W 0 fone sel source height is Y 1 29 3 22 TCONI1 BASIC1 REG
256. er Name IR_CIR Offset 0x34 Default Value 0x0000 1828 Bit Read Write Default Description 31 16 ITHR Idle Threshold for CIR The Receiver uses it to decide whether the CIR command has been received If there is no CIR signal on the air the receiver is staying in IDLE status One active pulse will bring the receiver from IDLE status to Receiving status After the CIR is end the inputting signal will keep the specified level high or low level for a long time The receiver can use this idle signal duration to decide that it has received the CIR command The corresponding flag is asserted If the corresponding interrupt is enabled the interrupt line is asserted to CPU When the duration of signal keeps one status high or low level for the specified duration ITHR 1 128 sample_clk this means that the 15 8 R W Ox18 previous CIR command has been finished NTHR Noise Threshold for CIR When the duration of signal pulse high or low level is less than NTHR the pulse is taken as noise and should be discarded by hardware 0 all samples are recorded into RX FIFO 1 If the signal is only one sample duration it is taken as noise and discarded 2 If the signal is less than lt two sample duration it is taken as noise and discarded 72 R W Oxa A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 204 Jau 8 2013 Ou Allwinner Technology CO Ltd A13
257. er Register 185 19 4 2 UART Transmit Holding Register 186 19 4 3 UART Divisor Latch Low Register 186 19 4 4 UART Divisor Latch High Register 187 19 4 5 UART Interrupt Enable Register 187 19 4 6 UART Interrupt Identity Register 188 19 4 7 UART FIFO Control R GIE 190 19 4 8 UART Line Control Register cfc cee ee 191 19 4 9 UART Modem Control Register sicciciccniciieses ee eee tiens 192 19 4 10 UART Line Status Register a aa acaba canta ca eae ced cede eetadaladsladaliusladabacabeteactiadts 194 19 4 11 UART Modem Status Register sentntntantentetesanen ens 196 19 4 12 UART Scratch Det 198 19 4 13 UART Status leger Luske ae abbed 198 19 4 14 UART Transmit FIFO Level Register 199 19 4 15 UART Receive FFO Level Register Lurer 199 19 416 UART Halt TX Register see 199 1953 UART Special Requirements 5 55555554555454155415554555555545 5555 REESE 200 19 5 1 IrDA Inverted Ee 200 20 CUR Interface ssisccssesssnsssasssnsssnsssnsssnsssnsssnsssnassnsssntssnsssnsssusssusssnsssesssnsssuassuasseassussseassuassessansesesssnssausesessscteses 201 DUDS OV CL VNC Wyn cass cscs ae ne D nee 201 20 2 CIR Resister List aeaa AR AR nana 201 20 3 CIR Regsit r DescriptiOniiecsissetcisscccoinstewedconnssesinvsewetcondesetenseceaastenesasusessetacenenatanseserdicesenededdsdes 201 20 3 1 GR Gore Register ua 201 20 3 2 GIR Receiver Configure R
258. er attribute control register1 DEBE_HWCCTL_REG 0x8D8 DE HWC coordinate control register DEBE HWCFBCTL REG Ox8E0 DE HWC frame buffer format register DEBE_WBCTL_REG Ox8FO DEBE write back control register DEBE_WBADD_REG Ox8F4 DEBE write back address register DEBE_WBLINEWIDTH_REG Ox8F8 DEBE write back buffer line width register DEBE IYUVCTL REG 0x920 DEBE input YUV channel control register DEBE IYUVADD REG 0x930 0x938 DEBE YUV channel frame buffer address register DEBE IYUVLINEWIDTH REG 0x940 0x948 DEBE YUV channel buffer line width register DEBE YGCOEF REG 0x950 0x958 DEBE Y G coefficient register DEBE YGCONS REG 0x95C DEBE Y G constant register DEBE_URCOEF_REG 0x960 0x968 DEBE UR coefficient register DEBE_URCONS_REG 0x96C DEBE UR constant register DEBE VBCOEF REG 0x970 0x978 DEBE V B coefficient register DEBE VBCONS REG 0x97C DEBE V B constant register DEBE OCCTL REG 0x9C0 DEBE output color control register DEBE OCRCOEF REG 0x9D0 0x9D8 DEBE output color R coefficient register A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 319 Ou 7 Allwinner Technology CO Ltd A13 DEBE OCRCONS REG Ox9DC DEBE output color R constant register DEBE_OCGCOEF_REG Ox9E0 0x9E8 DEBE output color G coefficient register DEBE_OCGCONS_REG Ox9EC DEBE output color G constant register
259. ernal 16 bit up counter If the counter reaches the value stored in the channel period register it resets At the beginning of a count period cycle the PWMOUT is set to activate state and count from 0x0000 The PWM divider divides the clock 24MHz by 1 4096 according to the pre scalar bits in the PWM control register In PWM cycle mode the output will be a square waveform the frequency is set to the period register In PWM pulse mode the output will be a positive pulse or a negative pulse 10 2 PWM Register List Module Name Base Address PWM 0x01C20C00 Register Name Offset Description PWM CTRL REG 0x0200 PWM Control Register PWM CHO PERIOD REG 0x0204 PWM Channel 0 Period Register 10 3 PWM Register Description 10 3 1 PWM Control Register Default 0x00000000 Offset 0x200 Register Name PWM CTRL REG Read Wr Default aa Bit Description ite Hex 31 30 29 R W 0x0 PWMO RDY PWM0 period register ready 28 R W 0x0 i a 0 PWMDO period register is ready to write 1 PWMO period register is busy 27 25 24 R W 0x0 23 R W 0x0 22 R W 0x0 21 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 85 Jau 8 2013 GW 7 Allwinner Technology CO Ltd A13 20 R W 0x0 19 R W 0x0 18 15 R W 0x0 14 10 R W 0x0
260. erval between two consecutive SOFs in bit times The nominal value is set to be 11 999 HCD should store the current value of this field before resetting HC By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value HCD may choose to restore 13 0 R W R Ox2edf the stored value upon the completion of the Reset sequence 22 6 15 HcFmRemaining Register Register Name HcFmRemaining Offset 0x438 Default Value 0x0 Read Write Bit HCD HC Default Description FrameRemaining Toggle This bit is loaded from the FramelntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0 This bit is used by HCD for the 31 R R W 0x0 synchronization between Framelnterval and FrameRemaining 30 14 0x0 Geen FramRemaining This counter is decremented at each bit time When it reaches zero it is reset by loading the Framelnterval value specified in HcFmInterval at the next bit time boundary When entering the USBOPERATIONAL state HC re loads the content with the Framelnterval of HcFmInterval and 13 0 R RW 0x0 uses the updated value from the next SOF 22 6 16 HcFmNumber Register Register Name HcFmNumber Offset 0x43c Default Value 0x0 Read Write Bit HCD HC Default Description 31 16 Reserved A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 233
261. erview The Display Engine Back End DEBE features 4 moveable amp size adjustable layers Layer size up to 8192 8192 pixels Support Alpha blending Support color key Support write back function Support 1 2 4 8 bpp mono palette Support 16 24 32 bpp color external frame buffer 5 6 5 1 5 5 5 0 8 8 8 8 8 8 8 8 8 8 4 4 4 4 Support on chip SRAM gt 256 entry 32 bpp palette gt 1 2 4 8 bpp internal frame buffer gt support Gamma correction gt gt gt gt gt gt Support hardware cursor gt 32 32 8 bpp gt 64 64 2 bpp gt 64 32 4 bpp gt 32 64 4 bpp Support YUV input channel Output color correction A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 315 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 28 2 DEBE Block Diagram AHB BUS Intelligent Ext DMA Controller On Chip Frame SRAM H W Cursor pattern buffer Normal YUV Palette Gamma Internal frame buffer Controller i DEFE DEBE 7 LCD Controller PIPE 1 FIFO Alpha Alpha Color Blender 1 Blender 0 Correction TV Encoder PIPE 0 FIFO Write back channel Figure 33 1 Display Engine Block Diagram 28 3 DEBE Description 28 3 1 Alpha Blending Alpha blending is a convex combination of two colors allowing for transparency effects in compu
262. es Control the nIRQ and FIQ of a RISC Processor Support 96 interrupt sources 4 Level Priority Controller External Sources of Edge sensitive or Level sensitive Since the 4 level Priority Controller allows users to define the priority of each interrupt source so higher priority interrupts can be serviced even if a lower priority interrupt is being treated 13 2 Interrupt Source The interrupt source 0 is always located at FIQ The interrupt sources 1 to 63 are located at System Interrupt and user peripheral Interrupt Source SRC Vector FIQ Description External Non Mask Interrupt External NMI 0 0x0000 YES OM or battery VDD VDDIO VDD18 VDD25 brownout detect 1 0x0004 UART I 2 0x0008 UART I interrupt 3 0x000C UART 3 4 0x0010 UART 3 interrupt IR 5 0x0014 IR 0 interrupt 6 0x0018 TWIO 7 Ox001C TWI 0 interrupt TWI 1 8 0x0020 TWI I interrupt TWI2 9 0x0024 TWI 2 interrupt SPI O 10 0x0028 SPI 0 interrupt SPI 1 11 0x002C SPI 1 interrupt SPI 2 12 0x0030 SPI 2 interrupt 13 0x0034 14 0x0038 15 0x003C 16 0x0040 17 0x0044 18 0x0048 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 110 Ou 7 Allwinner Technology CO Ltd
263. etting Register Offset 0x808 Register Name DEBE_DISSIZE_REG Read Wri Default Nr Bit Description te Hex DF DIS HEIGHT 31 16 R W U Display height A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 321 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 The real display height The value of these bits add 1 DIS WIDTH Display width The real display width The value of these bits add 1 28 5 4 DE Layer Size Register Offset Layer 0 0x810 Layer 1 0x814 Register Name DEBE LAYSIZE REG Layer 2 0x818 Layer 3 0x81C Read Wri Default DN Bit Description te Hex LAY_HEIGHT 28 16 R W UDF Layer Height The Layer Height The value of these bits add 1 LAY_WIDTH 12 0 R W UDF Layer Width The Layer Width The value of these bits add 1 28 5 5 DE Layer Coordinate Control Register Offset Layer 0 0x820 Layer 1 0x824 Register Name DEBE_LAYCOOR_REG Layer 2 0x828 Layer 3 0x82C Read Wri Default SC Bit Description te Hex LAY_YCOOR Y coordinate 31 16 R W UDF Y is the left top y coordinate of layer on screen in pixels The Y represents the two s complement LAY_XCOOR X coordinate 15 0 R W UDF X is left top x coordinate of the layer on screen in pixels The X represents the two s complement Setting the layer0 layer3 the coordinate left top on screen control information A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rig
264. evel 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 11 10 R W 0x0 IRQ69_PRIO IRQ 69 Priority Set priority level for IRQ bit 69 Level0 0x0 level 0 lowest priority A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Offset 0x90 Register Name INTC_SRC_PRIO_REG4 Levell 0x1 level 1 Level 0x1 level 2 Level3 0x1 level 3 highest priority IRQ68 PRIO IRQ 68 Priority Set priority level for IRQ bit 68 9 8 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ67_PRIO IRQ 67 Priority Set priority level for IRQ bit 67 7 6 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority IRQ66 PRIO IRQ 66 Priority Set priority level for IRQ bit 66 5 4 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ65 PRIO IRQ 65 Priority Set priority level for IRQ bit 65 32 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority IRQ64 PRIO IRQ 64 Priority Set priority level for IRQ bit 64 1 0 R W 0x0 Level0 0x0 level
265. evel 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 23 22 R W A13 User Manual V1 2 0x0 IRQ75_PRIO IRQ 75 Priority Set priority level for IRQ bit 75 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Copyright 2013 Allwinner Technology All Rights Reserved 131 Jau 8 2013 Ou Allwinner Technology CO Ltd Offset 0x90 Register Name INTC_SRC_PRIO_REG4 A13 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 21 20 R W 0x0 IRQ74_PRIO IRQ 74 Priority Set priority level for IRQ bit 74 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 19 18 R W 0x0 IRQ73_PRIO IRQ 73 Priority Set priority level for IRQ bit 73 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 17 16 R W 0x0 IRQ72_PRIO IRQ 72 Priority Set priority level for IRQ bit 72 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 15 14 R W 0x0 IRQ71_PRIO IRQ 71 Priority Set priority level for IRQ bit 71 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 13 12 R W 0x0 IRQ70_PRIO IRQ 70 Priority Set priority level for IRQ bit 70 Level0 0x0 l
266. fect 1 Reload timer 1 Interval value After the bit is set it can not be written again before it s cleared automatically R W 0x0 TMRI_EN A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 92 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Timer 1 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note Time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 11 3 7 ASYNC Timer 1 Interval Value Register Offset 0x24 Register Name ASYNC_TMR1_INTV_VALUE_REG Read Wr Default _ Bit f Description ite Hex TMR1_INTV_VALUE 31 0 R W x Timer 1 Interval Value Note The value setting should consider the system clock and the timer clock source 11 3 8 ASYNC Timer 1 Current Value Re
267. fect If CurrentConnectStatus is cleared when a SetPortReset SetPortEnable or SetPortSuspend write occurs this bit is set to force the driver to re evaluate the connection status since these writes should not occur if the port is disconnected 0 no change in PortEnableStatus 1 change in PortEnableStatus Note If the DeviceRemovable NDP bit is set this bit is set only after a Root Hub reset to inform the system that the device is attached 15 10 0x0 Reserved A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 238 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 read LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port When set a Low Speed device is attached to this port When cleared a Full Speed device is attached to this port This field is valid only when the CurrentConnectStatus is set 0 full speed device attached 1 low speed device attached write ClearPortPower The HCD clears the PortPowerStatus bit by writing a 1 to this bit 9 R W R W l Writing a 0 has no effect read PortPowerStatus This bit reflects the port s power status irrelevant of the type of power switching implemented This bit is cleared if an overcurrent condition is detected HCD sets this bit by writing SetPortPower or SetGl
268. frame 0x02 2 micro frame 0x04 4 micro frame 0x08 8 micro frame default equates to 1 ms 0x10 16 micro frame 2ms 0x20 32 micro frame 4ms 0x40 64 micro frame 8ms Any other value in this register yields undefined results The default value in this field is 0x08 Software modifications to this bit while HC Halted bit equals to zero results in undefined behavior 15 12 Reserved These bits are reserved and should be set to zero 11 R W or R Asynchronous Schedule Park Mode Enable OPTIONAL If the Asynchronous Park Capability bit in the HCCPARAMS register is a one then this bit defaults to a 1 and is R W Otherwise the bit must be a zero and is Read Only Software uses this bit to enable or disable Park A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 212 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 mode When this bit is one Park mode is enabled When this bit is zero Park mode is disabled 10 Reserved These bits are reserved and should be set to zero 9 8 R W or R Asynchronous Schedule Park Mode Count OPTIONAL Asynchronous Park Capability bit in the HCCPARAMS register is a one Then this field defaults to 0x3 and is WIR Otherwise it defaults to zero and is R It contains a count of the number of successive transactions the host controller is allowed to execute from
269. ge signal is sent back When the slave receiver doesn t acknowledge the slave address because of resource deficiency the SDA will be left high for master to generate a STOP condition to abort the transfer When the slave receiver acknowledges the slave address but not ready to receive more during a data transfer A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 162 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 the SDA will be left high for the master to generate a STOP condition to abort the transfer The following diagram provides an illustration to the relation between SDA signal line and SCL signal line on the 2 Wire serial bus PDA A L i ete 4 SCL Figure 17 1 TWI Timing Diagram 17 3 TWI Controller Register List Module Name Base Address TWIO 0x01C2AC00 TWII 0x01C2B000 TWD 0x01C2B400 Register Name Offset Description TWI_ADDR 0x0000 TWI Slave address TWL XADDR 0x0004 TWI Extended slave address TWI DATA 0x0008 TWI Data byte TWICNTR 0x000C TWI Control register TWL STAT 0x0010 TWI Status register TWI CCR 0x0014 TWI Clock control register TWI SRST 0x0018 TWI Software reset TWI_EFR Ox001C TWI Enhance Feature register TWI_ LCR 0x0020 TWI Line Control register 17 4 TWI Controller Register Description 17 4 1 TWI Slave Address Register Register Name TWI_ADDR Offse
270. ght 2013 Allwinner Technology All Rights Reserved 80 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 7 System Control 7 1 Overview The chip embeds a high speed SRAM which is split into five areas Its Memory Mapping is detailed in the following table Area Address Size Bytes Al 0x00000000 0x00003FFF 16K A2 0x00004000 0x00007FFF 16K A3 0x00008000 0x0000B3FF 13K A4 0x0000B400 0x0000BFFF 3K C1 0x01D00000 0x01D7FFFF VE C3 0x01DC0000 0x01DCFFFF ISP NAND 2K D USB 0x00010000 0x00010FFF 4K CPU I Cache 32K CPU D Cache 32K CPU L2 Cache 128K 7 2 System Control Register List Module Name Base Address SRAM 0x01C00000 Register Name Offset Description SRAM CFG REGO 0x0000 SRAM Configuration SRAM CFG REGI 0x0004 SRAM Control 7 3 System Control Register Description 7 3 1 SRAM Configuration Register 0 Default 0x7FFFFFFF Offset 0x00 Register Name SRAM_CFG_REGO Read Default H E Bit Description Write ex 31 SRAM_C1_MAP SRAM Area C1 50K Bytes Configuration by AHB 0 map to CPU DMA 1 map to VE 30 0 R W Ox JETT A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 81 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 7 3 2 SRAM Configuration Register 1 Default 0x00001000 Offset 0x04 Register Name
271. ghts Reserved 46 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 SPD DET SCN FIN Speed Detect Scan Finished 16 R 0x0 0 no effect 1 scan finished SPD DET FACTORI 15 8 R 0x0 Speed Detect Factor 1 This number indicates the delay length equivalent to input clock period x2 SPD DET FACTORO 7 0 R 0x0 Speed Detect Factor 0 This number indicates the delay length equivalent to input clock period x1 5 3 40 PMU Speed Factor Register 2 Offset OxE8 Register Name PMU_SPEED_FACTOR_REG2 Read Wr Default aa Bit Description ite Hex SPD_DET_EN Speed Detect Enable 31 R W 0x0 0 Disable 1 Enable SPD_DET_MODE Speed Detect Mode 30 R W 0x0 0 single mode 1 continuous mode SPD_DET_SPDUP_FACTOR Speed Detect Speed Up Factor Set these bits to non zero value can speed up the scan operation 00 lowest 29 28 R W 0x0 11 fastest 21 17 SPD_DET_SCN_FIN Speed Detect Scan Finished 16 R 0x0 0 no effect 1 scan finished SPD DET FACTORI 15 8 R 0x0 Speed Detect Factor 1 This number indicates the delay length equivalent to input clock period x2 SPD_DET_FACTORO 7 0 R 0x0 Speed Detect Factor 0 This number indicates the delay length equivalent to input clock period x1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 47 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd
272. gister Offset 0x28 Register Name ASYNC_TMR1_CURNT_VALUE_REG 8 Read Wr Default DN Bit Description ite Hex TMRI CUR VALUE 31 0 R W D Timer 1 Current Value Note Timer 1 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 11 3 9 ASYNC Timer 2 Control Register Default 0x00000004 Offset 0x30 Register Name ASYNC_TMR2_CTRL_REG 8 Read Wr Default aan Bit Description ite Hex 31 8 TMR2_EN Timer2 mode 0 Continuous mode When reaches the internal value the timer will not be 7 R W 0x0 disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 93 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 6 4 R W 0x0 TMR2_CLK_PRESCALE Select the pre scale of timer 2 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 3 2 R W 0x1 TMR2_CLK_SRC Timer 2 Clock Source 00 01 OSC24M 1x 0x0 TMR2_RELOAD Timer 2 Reload 0 No effect 1 Reload timer 2 Interval value After the bit is set it can not be written again before it s cleared automatically 0x0 TMR2_EN Timer 2 En
273. gister Reading the receiver buffer Receiver data available register non FIFO mode or non FIFO mode or FIFOs Received Data FIFOs disabled or the FIFO 0100 Second 8 disabled or RCVR FIFO trigger l Available drops below the trigger level level reached FIFO mode and FIFO mode and FIFOs FIFOs enabled enabled No characters in or out of the Character RCVR FIFO during the last 4 f Reading the receiver buffer 1100 Second Timeout character times and there is at Sp Indication least Icharacter in it during ae This time Reading the IIR register if p source of interrupt or Transmitter holding register pe writing into THR FIFOs or Transmit empty Program THRE Mode THRE Mode not selected or 0010 Third Holding Register disabled or XMIT FIFO at or A disabled or XMIT FIFO Empty below threshold Program above threshold FIFOs and THRE Mode enabled THRE Mode selected and enabled Clear to send or data set ready or ring indicator or data carrier detect Note that if auto flow Reading the Modem status 0000 Fourth Modem Status control mode is enabled a Register change in CTS that is DCTS set does not cause an interrupt 0111 Fifth Busy Detect UART_16550_COMPATIBLE Reading the UART status A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 189 Jau 8 2013 Ou Allwinner Technology CO Ltd A13
274. gister 1 Register Name PIO INT CFGI1 Offset 0x204 Default Value 0x0000 0000 Bit Read Write Default Description External INTn Mode n 8 15 0x0 Positive Edge Ox1 Negative Edge 0x2 High Level 0x3 Low Level 41 3 41 0x4 Double Edge Positive Negative 1 0 7 R W 0 Others Reserved 33 4 57 PIO Interrupt Configure Register 2 Register Name PIO INT CFG2 Offset 0x208 Default Value 0x0000 0000 Bit Read Write Default Description External INTn Mode n 16 23 0x0 Positive Edge Ox1 Negative Edge 0x2 High Level 0x3 Low Level 41 3 41 0x4 Double Edge Positive Negative 1 0 7 R W 0 Others Reserved 33 4 58 PIO Interrupt Configure Register 3 Register Name PIO INT CFG3 Offset 0x20C Default Value 0x0000 0000 Bit Read Write Default Description 41 3 41 R W 0 External INTn Mode n 24 31 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 406 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 i 0 7 0x0 Positive Edge Ox1 Negative Edge 0x2 High Level 0x3 Low Level 0x4 Double Edge Positive Negative Others Reserved 33 4 59 PIO Interrupt Control Register Offset 0x210 Register Name PIO_INT_CTL Default Value 0x0000 0000 Bit Read Write Default Description External INTn Enable n 0 31 n 0 Disable n 0 31
275. gister Name TCON FRM control register Read Wr Default Bit Description ite Hex TCONO_Frm_En 31 R W 0 O disable 1 enable 30 12 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 351 Ou 7 Allwinner Technology CO Ltd A13 TCONO Frm Mode R 6 R W 0 0 6bit frm output 1 Sbit frm output TCONO_Frm_Mode_G 5 R W 0 0 6bit frm output 1 Sbit frm output TCONO_Frm_Mode_B 4 R W 0 0 6bit frm output 1 5bit frm output TCONO Frm Test 00 FRM 1 0 R W 0 01 half 5 6bit half FRM 10 half 8bit half FRM 11 half 8bit half 5 6bit 29 3 5 TCONO FRM SEED REG Offset 0x014 0x01C Register Name TCON FRM pixel seed register Read Wr Default aa Bit Description ite Hex 31 25 Pixel_Seed_Value Note avoid set it to 0 24 0 R W 0 Offset 0x020 0x028 Register Name TCON FRM line seed register Read Wr Default Bit Description ite Hex 31 25 Line_Seed_Value Note avoid set it to 0 12 0 R W 0 29 3 6 TCONO FRM TAB REG Offset 0x02C 0x038 Register Name TCON FRM table register i Read Wr Default SS Bit f Description ite Hex 127 0 R W 0 Frm_Table_Value 29 3 7 TCON0_CTL_REG Offset 0x040 Register Name TCONO control register Read Wr Default SC Bit Description ite Hex 31 R W 0 TCONO_E
276. gisters The touch resistance RTOUCH can then be calculated using the following equation Rroucx RxpLaATE X Xposrtion 4096 x Z2 Z1 1 1 MEASURE MEASURE X POSITION ZI POSITION A Y 7 GO X O OD x Y OX OY TOUCH i TOUCH CN Sp ziposition 72 POSITION X POSITION Ne i e Z 3 F Ox ov ox Oy OX AGE O T Z2 POSITION Figure25 12 Pressure Measurement Block Diagram A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 265 Jau 8 2013 Allwinner Technology CO Ltd A13 Second Method The second method requires the user to know the resistance of the X plate and Y plate tablets Three touch screen conversions are required a measurement of the X position Xposrrion the Y position Yposrrion and the Z1 position The following equation also calculates the touch resistance Rroucu Rroucu Rxprate X Xposrrion 4096 x 4096 Z1 1 Ryprare 1 Yposrrion 4096 2 25 4 7 Pen Down Detection with Programmable Sensitivity Pen down detection is used as an interrupt to the host RirQ is an internal pull up resistor with a programmable value of 6 96 kQ default 48kQ The PENIRQ output is pulled high by an internal pull up the Y driver is on and connected to GND and the PENIRQ output is connected to the X input When the panel is touched the X input is pulled to ground through the touch scr
277. gure Xoo ar d Xoo SS Xo Xo Mirroring data TO ny US TA Start of a line New data position New data position p d bh End of a column Mirroring data Yn The scaler uses a 16 bit integer and a16 bit fractional value for the X and Y increment values This allows a fractional value resolution of 1 64K Only the most significant 5 bits of the fractional value are used by the filter coefficient RAMs 27 3 3 Scaling Filter New pixels are generated by interpolation or filtering of the original pixels Interpolation is the weighted average of the input pixels adjacent to the output pixel Filtering extends interpolation to include input pixels beyond the input pair adjacent to the output pixel The number of pixels used to generate the output defines the filter type Interpolation is a 2 tap filter A tap is equivalent to an original un scaled pixel of data A 4 tap filter would use the two pixels to the left and the two pixels to the right of the output pixel Following is the scaling algorithm A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 288 Jau 8 2013 Ou Allwinner Technology CO Ltd Source Pixel Columns ke 1 1 eg eg k 1 ke AET l ef oO 18 Zil Le ke 11 L ei 1 Loe et eg LET eo 27 3 4 Input Data Channel DEFE supports planar or interleaved video component data inputting via 3 input channels channelO channel1 and channel In planar mode if
278. gy CO Ltd A13 Run Stop When set to a 1 the Host Controller proceeds with execution of the schedule When set to 0 the Host Controller completes the current and any actively pipelined transactions on the USB and then halts The Host Controller must halt within 16 micro frames after software clears this bit The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state Software must not write a one to this field unless the Host Controller is in the Halt State 0 R W 0 The default value is 0x0 22 5 7 EHCI USB Status Register Register Name USBSTS Offset 0x14 Default Value 0x00001000 Bit Read Write Default Description Reserved 31 16 0 These bits are reserved and should be set to zero Asynchronous Schedule Status The bit reports the current real status of Asynchronous Schedule If this bit is a zero then the status of the Asynchronous Schedule is disabled If this bit is a one then the status of the Asynchronous Schedule is enabled The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register When this bit and the Asynchronous Schedule Enable bit are the same value the Asynchronous 15 R 0 Schedule is either enabled 1 or disabled 0 Periodic Schedule Status The bit reports the current real status
279. h of the interrupt types can be separately enabled disabled with the control registers The UART has 16450 and 16550 modes of operation which are compatible with a range of standard software drivers In 16550 mode transmit and receive operations are both buffered by FIFOs In 16450 mode these FIFOs are disabled The UART supports word lengths from five to eight bits an optional parity bit and 1 1 5 or 2 stop bits and is fully programmable by an AMBA APB CPU interface A 16 bit programmable baud rate generator and an 8 bit scratch register are included together with separate transmit and receive FIFOs Fight modem control lines and a diagnostic loop back mode are provided Interrupts can be generated for a range of TX Buffer FIFO RX Buffer FIFO Modem Status and Line Status conditions The UART includes the following features Compatible with industry standard 16550 UARTs 64 Bytes Transmit and receive data FIFOs DMA controller interface Software Hardware Flow Control Programmable Transmit Holding Register Empty interrupt Interrupt support for FIFOs Status Change 19 2 UART Timing Diagram One Character Bit Time TX RX Serial Data S Data bits 5 8 P S1 1 5 2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 184 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd Figure 19 1 UART Serial Data Format A13 Data Bits Bit Time
280. has been processed HCD may read the content in determining which ED is currently being processed at the time of reading 3 0 R R 0x0 PCED 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED through bit 0 to bit 3 must be zero in this field 22 6 9 HcControlHeadED Register Register Name HcControlHeadED CHED Offset 0x420 Default Value 0x0 Read Write Bit HCD HC Default Description EHCD 31 4 The HcControlHeadED register contains the physical address of the first 31 4 R W R 0x0 Endpoint Descriptor of the Control list HC traverse the Control list A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 230 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 starting with the HcControlHeadED pointer The content is loaded from HCCA during the initialization of HC 3 0 R R 0x0 EHCD 3 0 Because the general TD length is 16 bytes the memory structure for the TD must be aligned to a 16 byte boundary So the lower bits in the PCED through bit 0 to bit 3 must be zero in this field 22 6 10 HcControlCurrentED Register Offset 0x424 Register Name HcControlCurrentED CCED Default Value 0x0 Read Write Bit HCD HC Default Description R W R W 0x0 CCED 31
281. hnology CO Ltd A13 24 LRADC 24 1 Overview LRADC is 6 bit resolution and can work up to maximum conversion rate of 250Hz It features Support APB 32 bit bus width Support interrupt Support hold key and general key Support single key and continue key mode 6 bit resolution Voltage input range between 0 to 2V Sample rate up to 250Hz 24 2 Principle of operation 24 2 1 Block Diagram The LRADC converted data can by accessed by interrupt and polling method If software can t access the last converted data instantly the new converted data would update the old one at new sampling data 24 2 2 Hold Key and General Key Function Introduction When ADC_IN Signal change from ADC_REF to 2 3 ADC_REF Level A the comparator24 send first interrupt to control logic When ADC IN Signal changes from 2 3 ADC_REF to certain level Program can set the comparator25 give second interrupt If the control Logic get the first interrupt In a certain time range program can set doesn t get second interrupt it will send hold key interrupt to the host If the control Logic get the first interrupt In a certain time range program can set get second interrupt it will send key down interrupt to the host If the control logic only get the second interrupt doesn t get the first interrupt it will send already hold interrupt to the host ADC_REF 24 je KEY DOWN IRQ gt JL 28 HOLD
282. hts Reserved 322 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 28 5 6 DE Layer Frame Buffer Line Width Register Offset Layer 0 0x840 Layer 1 0x844 Register Name DEBE LAYLINEWIDTH REG Layer 2 0x848 Layer 3 0x84C Read Wri Default o Bit Description te Hex LAY_LINEWIDTH 31 0 R W UDF EE Layer frame buffer line width in bits Note If the layer is selected by video channel or YUV channel the setting of this register will be ignored 28 5 7 DE Layer Frame Buffer Low 32 Bit Address Register Offset Layer 0 0x850 Layer 1 0x854 Register Name DEBE LAYFB L32ADD REG Layer 2 0x858 Layer 3 0x85C Read Wri Default o Bit Description te Hex LAYFB_L32ADD 31 0 R W UDF Buffer start Address Layer Frame start Buffer Address in bit Note If the layer is selected by video channel or YUV channel the setting of this register will be ignored 28 5 8 DE Layer Frame Buffer High 4 Bit Address Register Offset 0x860 Register Name DEBE_LAYFB_H4ADD_REG Read Wri Default i Bit Description te Hex LAY3FB_H4ADD 27 24 R W UDF Layer3 Layer Frame Buffer Address in bit LAY2FB_H4ADD 19 16 R W UDF Layer2 Layer Frame Buffer Address in bit A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 323 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Layerl Layer Frame Buffer Address in bit LAYOFB_H4ADD Layer0 Layer Frame Buffer Address in bit No
283. ial clock freq 16 divisor Note that with the Divisor Latch Registers DLL and DLH set to zero the baud clock is disabled and no serial communications occur Also once the DLH is set at least 8 clock cycles of the slowest UART clock 7 0 R W 0 should be allowed to pass before transmitting or receiving data 19 4 5 UART Interrupt Enable Register Register Name UART IER Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 PTIME Programmable THRE Interrupt Mode Enable This is used to enable disable the generation of THRE Interrupt 7 R W 0 Disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 187 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 Enable 6 4 EDSSI Enable Modem Status Interrupt This is used to enable disable the generation of Modem Status Interrupt This is the fourth highest priority interrupt 0 Disable 3 R W 0 1 Enable ELSI Enable Receiver Line Status Interrupt This is used to enable disable the generation of Receiver Line Status Interrupt This is the highest priority interrupt 0 Disable 2 R W 0 1 Enable ETBEI Enable Transmit Holding Register Empty Interrupt This is used to enable disable the generation of Transmitter Holding Register Empty Interrupt This is the third highest priority interrupt 0 Disable 1 R W 0 1 Enable
284. ical for top field complement This value equals to initial phase 2 6 27 5 49 DEFE_CH1_VERTPHASE1_REG Offset 0x218 Register Name DEFE_CH1_VERTPHASE1_REG Bit KE Fe Description ite Hex 31 20 PHASE 19 0 R W 0x0 U R component initial phase in vertical for bottom field complement This value equals to initial phase 2 27 5 50 DEFE CHO HORZCOEFO REGN N 0 31 Offset 0x400 N 4 Register Name DEFE CHO HORZCOEFO REGN Read Wr Default Bit Description ite Hex TAP3 31 24 R W 0x0 Horizontal tap3 coefficient The value equals to coefficient 2 TAP2 23 16 R W 0x0 Horizontal tap2 coefficient The value equals to coefficient 2 TAPI 15 8 R W 0x0 Horizontal tap coefficient The value equals to coefficient 2 7 0 R W 0x0 TAPO A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 312 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Horizontal opt coefficient The value equals to coefficient 2 27 5 51 DEFE_CH0_VERTCOEF_REGN N 0 31 Offset 0x500 N 4 Register Name DEFE CHO VERTCOEF REGN Read Wr Default Ge Bit Description ite Hex TAP3 31 24 R W 0x0 Vertical tap3 coefficient The value equals to coefficient 2 TAP2 23 16 R W 0x0 Vertical tap2 coefficient The value equals to coefficient 2 TAP1 15 8 R W 0x0 Vertical tap1 coefficient The value equals to coefficient 2 TAPO 7 0 R W
285. if Port Power is zero Over current Change Default 0 This bit gets set to a one when there is a change to Over current Active Software clears this bit by writing a one to this bit 5 R WC position Over current Active 0 This port does not have an over current condition 1 This port currently has an over current condition This bit will automatically transition from a one to a zero when the over current condition is 4 R removed A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 222 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 The default value of this bit is 0 R WC Port Enable Disable Change Default 0 1 Port enabled disabled status has changed 0 No change For the root hub this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point See Chapter 11 of the USB Specification for the definition of a Port Error Software clears this bit by writing a to it This field is zero if Port Power is zero R W Port Enabled Disabled 1 Enable 0 Disable Ports can only be enabled by the host controller as a part of the reset and enable Software cannot enable a port by writing a one to this field The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high speed device Ports can be disabled by either a fault condition disconnect event or other fault
286. implemented to detect and correct up to 64 bits error per 512 or 1024 bytes data The on chip ECC and parity checking circuitry of NFC frees CPU for other tasks The ECC function can be disabled by software The data can be transferred by DMA or by CPU memory mapped IO method The NFC provides automatic timing control to read or write external Flash The NFC maintains the proper relativity for CLE CE and ALE control signal lines Three kinds of modes are supported for serial read access Mode 0 is the conventional serial access Mode 1 for EDO type and Mode 2 is for extension EDO type In addition NFC can monitor the status of R B signal line Block management and wear leveling management are implemented in software The NFC features Support SLC MLC TLC flash and EF NAND memory Software configure seed to randomize engine Software configure method for adaptability to a variety of system and memory types Support 8 bit Data Bus Width Support 1024 2048 4096 8192 16384 bytes size per page Support 3 3 V voltage supply Flash Upto 2 flash chips which are controlled by NFC CExtt Support Conventional and EDO serial access method for serial reading Flash On the fly BCH error correction code which correcting up to 64 bits per 512 or 1024 bytes Corrected Error bits number information report ECC automatic disable function for all Oxff data NEC status information is reported by its registers Support interr
287. ing NDMA7 HF IRQ PEND 14 R W 0x0 Normal DMA 7 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA6_END_IRQ_PEND 13 R W 0x0 Normal DMA 6 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA6_HF_IRQ_PEND 12 R W 0x0 Normal DMA 6 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA5 END IRQ PEND 11 R W 0x0 Normal DMA 5 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA5 HF IRQ PEND 10 R W 0x0 Normal DMA 5 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA4_END_IRQ_PEND 9 R W 0x0 Normal DMA 4 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA4_HF_IRQ_PEND 8 R W 0x0 Normal DMA 4 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA3_END_IRQ_PEND 7 R W 0x0 Normal DMA 3 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA3_HF_IRQ_PEND 6 R W 0x0 Normal DMA 3 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA2_END_IRQ_PEND 5 R W 0x0 Normal DMA 2 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA2_HF_IRQ_PEND 4 R W 0x0 Normal DMA 2 Half Transfer Interrupt Pend
288. ing Set 1 to the bit will clear it 0 No effect 1 Pending NDMA1_END_IRQ_PEND 3 R W 0x0 Normal DMA 1 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMA1_HF_IRQ_PEND 2 R W 0x0 Normal DMA 1 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending NDMAO_END_IRQ_PEND Normal DMA 0 End Transfer Interrupt Pending Set 1 to the bit will clear it 1 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 142 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 No effect 1 Pending NDMAO HF IRQ PEND 0 R W 0x0 Normal DMA 0 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 14 4 3 Normal DMA Configuration Register Default 0x00000000 N 0 7 Offset 0x 100 N 0x20 N 0 1 2 3 4 5 6 7 Register Name NDMA CTRL REG Bit Read Wri te Default Hex Description 31 0x0 NDMA_LOAD DMA Loading If set to 1 DMA will start and load the DMA registers to the shadow registers The bit will hold on until the DMA finishes It will be cleared automatically Set 0 to the bit will reset the corresponding DMA channel 30 0x0 NDMA_CONTI_EN DMA Continuous Mode Enable 0 Disable 1 Enable 29 27 0x0 NDMA_WAIT_STATE DMA Wait State 0 wait for 0 DMA clock to request 7
289. inner Technology CO Ltd A13 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P06 P07 P04 P05 P02 P03 POO PO1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POI POO P03 P02 P05 P04 P07 P06 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POO POI P02 P03 P04 P05 P06 P07 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mono 8 bpp mode or palette 8 bpp mode FBF 0011 PS 00 11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3 P2 P1 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 PS 01 10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO P1 P2 P3 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Color 16 bpp mode FBF 0100 or 0101 or 0110 or 0111 or 1000 PS 00 Bit 31 30 29 28 27 26 25 24 23 2 21 20 19 18 17 16 P1 PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 331 Ou 7 Allwinner Technology CO Ltd A13 PO Pl 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 10 11 Invalid Color 24 bpp or 32 bpp mode FBF 1001 or 1010 PS 00 01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
290. inner Technology CO Ltd A13 SPI SCLK Mode 0 SPI SCLK Mode 2 SPI MOSI X SPI MISO X A SPI SS Sample MOSI MISO pin I I l Phase 0 Figure18 1 SPI Phase 0 Timing Diagram SPI SCLK Mode 1 SPI SCLK Mode 3 SPI MOSI SPI MISO0 XT y y A SPISS Sample MOSI MISO pin I i fl l l I Phase 1 Figure 18 2 SPI Phase 1 Timing Diagram 18 3 SPI Register List Module Name Base Address SPIO 0x01C05000 SPI 0x01C06000 SPI2 0x01C17000 Register Name Offset Description SPI RXDATA 0x00 SPI RX Data Register SPI TXDATA 0x04 SPI TX Data Register SPL CTL 0x08 SPI Control Register SPI INTCTL Ox0C SPI Interrupt Control Register SPL ST 0x10 SPI Status Register SPI_DMACTL 0x14 SPI DMA Control Register A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 172 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 SPI WAIT 0x18 SPI Wait Clock Counter Register SPI CCTL Ox1C SPI Clock Rate Control Register SPI BC 0x20 SPI Burst Counter Register SPI_TC 0x24 Spi Transmit Counter Register SPI FIFO STA 0x28 SPI FIFO Status Register 18 4 SPI Register Description 18 4 1 SPI RX Data Register Register Name SPI RXDATA Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default
291. ins a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction The transaction is started only if FrameRemaining 3 this field The value is calculated by 11 0 R W R 0x0628 HCD with the consideration of transmission and setup overhead 22 6 19 HcRhDescriptorA Register Register Name HcRhDescriptorA Offset 0x448 Default Value Read Write Bit HCD HC Default Description A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 234 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 31 24 R W 0x2 PowerOnToPowerGoodTime POTPGT This byte specifies the duration HCD has to wait before accessing a powered on port of the Root Hub It is implementation specific The unit of time is 2 ms The duration is calculated as POTPGT 2ms 23 13 Reserved 12 R W NoOverCurrentProtection This bit describes how the overcurrent status for the Root Hub ports are reported When this bit is cleared the OverCurrentProtectionMode field specifies global or per port reporting 0 Over current status is reported collectively for all downstream ports 1 No overcurrent protection supported 11 R W OverCurrentProtectionMode This bit describes how the overcurrent status for the Root Hub ports are reported At reset these fields should reflect the same mode as PowerSwitchingMode Thi
292. is cleared when the CPU writes to the TX Holding Register If the FIFOs are enabled this bit is set to 1 whenever the TX FIFO is 5 R 1 empty and it is cleared when at least one byte is written to the TX FIFO BI Break Interrupt This is used to indicate the detection of a break sequence on the serial input data If in UART mode SIR MODE Disabled it is set whenever the serial input sin is held in a logic 0 state for longer than the sum of start time data bits parity stop bits If in infrared mode SIR MODE Enabled it is set whenever the serial input sir_in is continuously pulsed to logic 0 for longer than the 4 R 0 sum of start time data bits parity stop bits A break condition on A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 194 Jau 8 2013 Allwinner Technology CO Ltd A13 serial input causes one and only one character consisting of all zeros to be received by the UART In the FIFO mode the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO Reading the LSR clears the BI bit In the non FIFO mode the BI indication occurs immediately and persists until the LSR is read FE Framing Error This is used to indicate the occurrence of a framing error in the receiver A framing error occurs when the receiver does not detect a valid STOP bit in
293. is granted by implication or otherwise under any patent or patent rights of Allwinner This user manual neither states nor implies warranty of any kind including fitness for any particular application A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 408 Jau 8 2013
294. it Read Write Default Description 31 24 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If 23 0 R W 0 the port is configured as functional pin the undefined value will be read 33 4 15 PC Multi Driving Register 0 Register Name PC_DRVO Offset 0x5C Default Value 0x5555 5555 Bit Read Write Default Description PC n Multi Driving Select n 0 15 2i 1 2i 00 Level 0 01 Level 1 1 0 15 R W Ox1 10 Level 2 11 Level 3 33 4 16 PC Multi Driving Register 1 Register Name PC DRV1 Offset 0x60 Default Value 0x0000 0055 Bit Read Write Default Description 31 8 PC n Multi Driving Select n 16 19 2i 1 2i 00 Level 0 01 Level 1 i 0 3 R W Ox1 10 Level 2 11 Level 3 33 4 17 PC Pull Register 0 Register Name PC PULLO Offset 0x64 Default Value 0x0000 5140 Bit Read Write Default Description PC n Pull up down Select n 0 15 21 1 2i 00 Pull up down disable O1 Pull up 1 0 15 R W 0x0000_5140 10 Pull down 11 Reserved 33 4 18 PC Pull Register 1 Register Name PC PULLI Offset 0x68 Default Value 0x0000 0016 Bit Read Write Default Description 31 8 2i 1 2i1 R W 0x16 PC n Pull up down Select n 16 19
295. ite Back Buffer Line Width Register 368 30 2 11 Luminance Histogram Control Register 368 30 2 12 Luminance Histogram Threshold Setting Register 0 368 30 2 13 Luminance Histogram Threshold Setting Register 1 368 30 2 14 Luminance Histogram Statistics Lum Recording Register eeeeeeeeeeeeeeeee 369 30 2 15 Luminance Histogram Statistics Counter Recording Register eeeeeeeeeeeeeeee 369 30216 CSC Y G Coefficient Eise ENER 370 30 2 17 CSC Y G Constant E 370 30218 CSC U R Coefficient Register zseeggieguegeiegereggiegezeggiugegec egetegie egegteegeggegeeg degegeggeg 370 30 2 19 CSC UR Constant eege 370 30 2 20 CSC V B Coefficient Register ana 371 30 2 21 CSC V B Constant Register ata ec ee eateries deca Sneed ceed 371 30 2 22 DRC Spatial Coefficient Sn 371 30 2 23 DRC Intensity Coefficient vend 371 30 2 24 DRC Luminance Gain Coefficient eessen 372 SL Security System SS scssssscisccssadessscosestcsscessenseasesssossotscassascodsantesssdboeseudesessbosnaseacesssosstuessesssesasuascersbooscstassees 373 ILL a TEE 373 31 2 Security System Block Diagram ssrsrrrrrrirrrrrrr rnrn rnrn EEEIEE ETETEA 373 31 3 Security System Register List sic net 373 31 4 Security System Register Description 374 31 4 1 Security System Control Register ssc 374 31 4 2 Security System Key n Register ek 376 31 4 3 Security System IV n Register unnarennet deta es dee ees ee enacts 376 31 4 4 Security System e E ale EE 376 31 4
296. ite Hex 31 15 14 12 R W 0x2 TY_N_SELECT TY_N Port Function Select 000 Input 001 Output 010 TP_YN 011 100 101 110 111 11 10 8 R W 0x2 TY_P_SELECT TY_P Port Function Select 000 Input 001 Output 010 TP_YP 011 100 101 110 111 6 4 R W 0x2 TX_N_SELECT TX_P Port Function Select 000 Input 001 Output 010 TP_XP 011 100 101 110 111 3 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 274 Ou 7 Allwinner Technology CO Ltd A13 2 0 R W 0x2 TX_P_SELECT TX_P Port Function Select 000 Input 001 Output 010 TP_XP O11 100 101 110 111 25 6 11 TP Port Data Register Offset Ox2c Register Name TP_PORT_DATA Bit Read Wr Default Description ite Hex 31 12 3 0 R W 0x0 TP_PORT_DATA TP Port Data Value TP_XP TP_XN TP_YP TP_YN A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 275 Ou Allwinner Technology CO Ltd A13 26 CMOS Sensor Interface CSD 26 1 Overview The CMOS Sensor Interface CSI features 8 bit input data Support CCIR656 protocol for NTSC and PAL 3 parallel data paths for image stream parsing Support Received data double buffer Parsing bayer data into planar R G B output to memory Parsing interlaced data into planar or M
297. its 30 2 5 DRC Setting Register Offset 0X0018 Register Name IMGEHC_DRC_SET_REG Read Wri Default Description DRC_GAIN_AUTOLOAD_DIS Only valid when the module is enabled and MOD is DRC mode or the bit is ignored A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 365 Jau 8 2013 GW OM winner Technology CO Ltd A13 If the auto load function is enabled the DRC luminance gain coefficient will be auto loaded from the external appointed memory address when the SYNC signal LCD SYNC signal is coming otherwise ignore the auto load function About the calculating way of the external appointed memory address refer to the DRC external LGC start address register 0 Enable the auto load function 1 Disable the auto load function Ea EE DRC LGC ABSLUMPERVAL 15 08 0x80 Abs luminance percent value elle DRC_ADJUST_EN O1 R W 0x00 0 disable 1 enable DRC_LGC_ABSLUMSHF Abs luminance shift bits R W 0x00 0 shift 8bits 1 shift 9bits Note Double buffered register of DRC double buffer function is controlled by DRC_DB_EN and DRC_DBRDY_CTL bits 30 2 6 DRC Window Position Register0 Offset 0X001C Register Name IMGEHC_DRC_WP_REGO Read Wri Default BE Bit Description te Hex DRC_WIN_TOP 27 16 R W Window Top position Top position is the left top y coordinate of display window in pixels DRC_WIN_LEFT 11 00 R W Window Left position Left position is lef
298. its 0 No effect 31 0 R W 0x0 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 13 4 20 Interrupt Response Register 0 Default 0x00000000 Offset 0x60 Register Name INTC_RESP_REGO Read Wr Default SC Bit Description ite Hex INT RESPO Interrupt Source 31 0 response bit 31 0 R W 0x0 Ee e If the corresponding bit is set the interrupt with the lower or the same priority level is masked 13 4 21 Interrupt Response Register 1 Default 0x00000000 Offset 0x64 Register Name INTC RESP REGI Read Wr Default a Bit Description ite Hex INT RESPI Interrupt Source 63 32 response bit 31 0 R W 0x0 f KS a If the corresponding bit is set the interrupt with the lower or the same priority level is masked 13 4 22 Interrupt Response Register 2 Default 0x00000000 Offset 0x68 Register Name INTC_RESP_REG2 Read Wr Default ae Bit Description ite Hex INT RESP2 Interrupt Source 95 64 response bit 31 0 R W 0x0 eer face If the corresponding bit is set the interrupt with the lower or the same priority level is masked A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 118 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13
299. ity level for IRQ bit 24 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 7 Allwinner Technology CO Ltd Offset 0x84 Register Name INTC SRC PRIO REGI A13 15 14 R W 0x0 IRQ23_PRIO IRQ 23 Priority Set priority level for IRQ bit 23 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 13 12 R W 0x0 IRQ22_PRIO IRQ 22 Priority Set priority level for IRQ bit 22 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 11 10 R W 0x0 IRQ21_PRIO IRQ 21 Priority Set priority level for IRQ bit 21 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 9 8 R W 0x0 IRQ20_PRIO IRQ 20 Priority Set priority level for IRQ bit 20 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 7 6 R W 0x0 IRQ19_PRIO IRQ 19 Priority Set priority level for IRQ bit 19 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 5 4 R W 0x0 IRQ18_PRIO IRQ
300. k Enable 0 Disable 1 Enable R W GEN Global Enable A disable on this bit overrides any other block or channel enables and flushes all FIFOs 0 Disable 1 Enable 20 3 2 CIR Receiver Configure Register Register Name IR RXCTL Offset 0x10 Default Value 0x0000 0000 Bit Read Write Default Description 31 3 RPPI Receiver Pulse Polarity Invert 0 Not invert receiver signal 2 R W 1 1 Invert receiver signal 1 0 20 3 3 CIR Receiver FIFO Register Register Name IR RXFIFO Offset 0x20 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 7 0 R 0 Receiver Byte FIFO 20 3 4 CIR Receiver Interrupt Control Register Register Name IR RXINT Offset 0x2C Default Value 0x0000 0000 Bit Read Write Default Description 31 12 11 6 R W 0 RAL A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 202 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 RX FIFO Available Received Byte Level for interrupt and DMA request TRIGGER LEVEL RAL 1 DRQ_EN RX FIFO DMA Enable 0 Disable 1 Enable When set to 1 the Receiver FIFO DRQ is asserted if reaching RAL The DRQ is de asserted when condition fails R W RAI_EN RX FIFO Available Interrupt Enable 0 Disable 1 Enable When set to 1 the Receiver FIFO IRQ i
301. k Max Clock 100MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 00 OSC24M 25 24 R W 0x0 01 PLL6 10 PLLS 11 23 18 CLK_DIV_RATIO 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 The divider is 1 2 4 8 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 30 USB Clock Default 0x00000000 Offset OxCC Register Name USBPHY_CFG_REG Read Wr Default SC Bit Description ite Hex 31 10 USBPHY1 CLK GATING Gating Special Clock for USB PHY1 9 R W 0x0 0 Clock is OFF 1 Clock is ON USBPHY0_CLK_GATING 8 R W 0x0 Gating Special Clock for USB PHYO 0 Clock is OFF A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 73 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 Clock is ON 7 OHCI SCLK_GATING Gating Special Clock for OHCI 0 Clock is OFF 1 Clock is ON 6 R W 0x0 NN wo EI KKK KKK USBPHY1 RST CTRL USB PHY1 Reset Control 0 Reset valid 1 Reset invalid 1 R W 0x0 USBPHYO RST CTRL USB PHYO Reset Control 0 Reset valid 1 Reset invalid 0 R W 0x0 6 4 31 DRAM CLK Default 0x00000000 Offset
302. ld be set to zero Asynchronous Schedule Park Capability If this bit is set to a one then the host controller supports the park feature for high speed queue heads in the Asynchronous Schedule The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule 2 R Park Mode Count fields in the USBCMD register Programmable Frame List Flag If this bit is set to a zero then system software must use a frame list length of 1024 elements with this host controller The USBCMD register Frame List Size field is a read only register and should be set to zero If set to 1 then system software can specify and use the frame list in the USBCMD register Frame List Size field to cofigure the host controller The frame list must always aligned on a 4K page boundary This 1 R requirement ensures that the frame list is always physically contiguous Reserved These bits are reserved for future use and should return a value of zero 0 R 0 when read 22 5 5 EHCI Companion Port Route Description Register Name HCSP PORTROUTE Offset OxOC Default Value UNDEFINED Bit Read Write Default Description HCSP PORTROUTE This optional field is valid only if Port Routing Rules field in HCSPARAMS register is set to a one This field is used to allow a host controller implementation to explicitly 31 0 R describe to which companion host controller ea
303. level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority IRQ84 PRIO 9 8 R W 0x0 IRQ 84 Priority Set priority level for IRQ bit 84 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 135 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Offset 0x94 Register Name INTC_SRC_PRIO_REGS Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority IRQ83 PRIO IRQ 83 Priority Set priority level for IRQ bit 83 7 6 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority IRQ82 PRIO IRQ 82 Priority Set priority level for IRQ bit 82 5 4 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority IRQ81 PRIO IRQ 81 Priority Set priority level for IRQ bit 81 32 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority IRQ80 PRIO IRQ 80 Priority Set priority level for IRQ bit 80 1 0 R W 0x0 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 136 Jau 8 2013
304. ll Rights Reserved 17 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 28 5 40 Internal Frame Butfer Mode eege 343 28 5 41 Internal Frame Buffer Mode Palette Table Luucuemmninnsniksinnkninsinninnibnninnitink e 343 28 5 42 Gamma Correction MO RER ESS SR SE nettes 344 28 0 Display Engine Memory Mapping sssusa synina anaa ana aeaa aaa iE aaea 346 29 LCD TV Timing Controller secevevvevnvevnnevnnevnnevnnevnneennevnnevnnennnesnnennnesnnennnennnesnnesnnesnnennnennnennnesnnesnnennneeen 348 29 1 LCD TV Timing Controller Block Diagram sis 348 29 2 LCD TV Timing Controller Register Listrier 348 29 3 LCD TV Timing Controller Register Description is 350 29 3 1 TETEN he 350 29 3 2 TCON GINTO RER a e a a a a EEES 350 29 3 3 TCON GINT RE E 351 29 3 4 TED FRM CTE o nerd ee ne eee ere eer ere 351 29 3 5 LES EI FRU SEEN REG 352 29 3 6 TONG FRML TAB REG sce 352 29 3 7 TCONG CTL REG esse abbeden hadet 352 29 3 8 MD PE 353 29 3 9 TVEN 354 29310 TCONO BASIC I REG vassere eet tk 354 29311 TOONO BASIC REG ved 354 29 312 TCONO BASICS REG eat hie eta fastere ened laseketaln knekke nntenktedkteretnsnian 355 TCONO HV PE 355 2934 POCONO CPU IP REG usa 356 25515 TCONG CPU WR REESEN 357 29 3 16 TCONO_CPU_RDO_REG reegen 357 29 3 17 TCONO CPU NE NE 357 29 318 TCONO IO Ga ra aa ae a a a e a a aa e a eaa 357 25310 TCONO 1O TRI E 358 29320 FCO CAL REG E 359 29 3 21 TOM ee PE ate attests eee teen tee ae mee
305. logy CO Ltd A13 Tl NFC_CLE setup time T T2 NFC_CLE hold time T T3 NFC_CE setup time T T4 NFC_CE hold time T T5 NFC WER pulse width T T6 NFC_WE hold time T T7 NFC_ALE setup time T T8 Data setup time T T9 Data hold time T T10 Ready to NFC_RE low 3T T11 NFC_ALE hold time T T12 NFC REf pulse width T T13 NFC REf hold time T T14 Read cycle time 2T T15 Write cycle time 2T T16 NFC_WE high to tWB Specified by timing configure R B busy register NFC_TIMING_CFG T17 NFC WER high to tWHR Specified by timing configure NFC_RE low register NFC TIMING CFG T18 NFC REf high to RHW Specified by timing configure NFC_WE low register NFC TIMING CFG T19 Address to Data tADL Specified by timing configure Loading time register NFC TIMING CFG Notes T is the clock period duration of NFC CLK x2 15 4 NFC Operation Guide t Data Output Serial Access Figure15 12 Page Read Command Diagram A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 157 An Allwinner Technology CO Ltd A13 Ke Ee son KA Co Add1 Col Add2 Row Add1 Row Add2X Row Add3 ey d SerialData 1 up to m Byte Input Command Column Address Row Address Serial Input Program Command Figure 15 13 Page Program Diagra
306. lor Key Theory Block In display engine the process of color key will be done in Alpha Blender1 block Only 2 channels can process color key at the same coordinate of screen If both channels are set into color key mode the higher priority channel will match another channel See the following diagram A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 317 Jau 8 2013 Allwinner Technology CO Ltd A13 Layer A Layer B A Screen Back Ground Color Matching Area The alpha value of layer A AV_a The alpha value of layer A AV_b The RGB value of layer A R_a G_a B_a The RGB value of layer B R_b G_b B_b The RGB value of Background color R_bg G_bg B_bg In none matching area As same as normal alpha blending process In matching area If priority of layer A gt priority of layer B Layer A color key setting status True Layer B color key setting status True or false Color key selection Layer A match layer B R R_a AV_a R_bg 1 AV_a G G_a AV_a G_bg 1 AV_a B B_a AV_a B_bg 1 AV_a If priority of layer A gt priority of layer B Layer A color key setting status False Layer B color key setting status True Color key selection Layer B match layer A R R_b AV_b R_bg 1 AV_b G G_b AV_b G_bg 1 AV_b B B_b AV_b B_bg 1 AV_b 28 3 3 PIPE There are 2 normal pipes in the engine pipe 0 and pipel In normal mode the dedicated layer will get the data from system
307. lue OxXXXX_XXXX Bit Read Write Default Description 31 0 R D Securiy root key 31 0 32 3 2 SID Root Key 1 Register Register Name SID_RKEY1 Offset 0x04 Default Value OXXXXX_XXXX Bit Read Write Default Description 31 0 R D Security root key 63 32 32 3 3 SID Root Key 2 Register Register Name SID_RKEY2 Offset 0x08 Default Value 0OxXXXX XXXX Bit Read Write Default Description 31 0 R D Security root key 95 64 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 379 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 32 3 4 SID Root Key 3 Register Register Name SID RKEY3 Offset OxOc Default Value OXXXXX_XXXX Bit Read Write Default Description 31 0 R D Security root key 127 96 32 3 5 SID Program Control Register Register Name SID_PCTL Offset 0x44 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 Program index 7 4 R W 0 The index value of 32 bits electrical fuses hardware macrocell 3 1 Software program start Write 1 to start software program and automatically clear to 0 after 0 R W 0 program A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 380 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 33 Port Controller 33 1 Overview The chip has 7
308. lwinner Technology CO Ltd A13 31 0 R 0 SHA1 MD5 Message digest MD n for SHA1 MD5 n 0 4 31 4 8 Security System RX FIFO Register Offset 0x200 Register Name SS RX Default Value 0x0000 0000 Bit Read Write Default Description 31 0 W 0 32 bits RX FIFO for Input 31 4 9 Security System TX FIFO Register Offset 0x204 Register Name SS_TX Default Value 0x0000 0000 Bit Read Write Default Description 31 0 R 0 32 bits TX FIFO for Output 31 5 Security System Clock Requirement Clock Name Description Requirement ahb_clk AHB bus clock gt 24MHz ss_clk SS serial clock lt 150MHz A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 378 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 32 Security ID 32 1 Overview There is one on chip 128 bit EFUS for security application It can also be used as root key or for other purposes It features 128 bit electrical fuses for root key 32 2 Security ID Register List Module Name Base Address SID 0x01c23800 Register Name Offset Description SID_RKEYO 0x00 Root Key 31 0 SID_RKEY1 0x04 Root Key 63 32 SID_RKEY2 0x08 Root Key 95 64 SID_RKEY3 Ox0Oc Root Key 127 96 32 3 Security ID Register Description 32 3 1 SID Root Key 0 Register Register Name SID_RKEYO Offset 0x00 Default Va
309. m Ox TI LT A AANA DD UU k OU U fraps sor L L EEE oon Address 5Cycle 20h ro 100 oon Data Output Serial Access Figure15 14 EF NAND Page Read Diagram CLE ALE VOx SV OS NBA AE ES om Yen sel acd2 Row ett X Row Add2 GE 30h 1 X col Add2 Column Address Row Address lumn Address S A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 158 Jau 8 2013 Allwinner Technology CO Ltd A13 Figure15 15 Interleave Page Read Diagram A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 159 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 16 SD3 0 Controller 16 1 Overview The SD3 0 controller can be configured as a Secure Digital Multimedia Card controller which simultaneously supports Secure Digital memory SD Memo UHS 1 Card Secure Digital I O SDIO Multimedia Cards MMC eMMC Card and Consumer Electronics Advanced Transport Architecture CE ATA The SD3 0 controller features Support Secure Digital memory protocol commands up to SD3 0 Support Secure Digital I O protocol commands Support Multimedia Card protocol commands up to MMC4 3 Support CE ATA digital protocol commands Support eMMC boot operation and alternative boot operation Support Command Completion signal and interrupt to host processor and Command Completion Signal
310. ma Correction Mode Offset DE on chip SRAM block 0x4400 0x47FF Read Wri Default Bit Description te Hex 31 24 R W UDF Alpha channel intensity 23 16 R W UDF Red channel intensity 15 08 R W UDF Green channel intensity 07 00 R W UDF Blue channel intensity In gamma correction mode the RAM array is used for gamma correction each pixel s alpha red green and blue color component is treated as an index into the SRAM array The corresponding Alpha red green or blue channel intensity value at that index is used in the actual color The following figure shows the RAM array used for gamma correction and the corresponding colors output A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 344 Jau 8 2013 CT Allwinner Technology CO Ltd A13 On chip SRAM array Inputting external red frame buffer data ao RO Go Bo utput color al R1 G1 B1 D 5 R38 G133 B28 0254 R254 G254 B254 0255 R255 G255 B255 On chip SRAM for gamma correction A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 345 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 28 6 Display Engine Memory Mapping Base Address BEO 0x01e60000 Offset 0x0000 Reserved 0x07FF 0x0800 Registers OxODFF 0x0E00
311. mage Input Ability CMOS sensor interface CSI Memory 16 bit SDRAM controller gt Support DDR2 SDRAM and DDR3 SDRAM up to 533MHz gt Memory Capacity up to 512MB 8 bit NAND Flash Controller with 2 CE and 2 RB signals gt Support SLC MLC TLC DDR NAND gt 64 bit ECC Peripherals One USB 2 0 OTG controller for general application and one USB EHCI OHCI controller for host application Three high speed memory controllers supporting SD version 3 0 and eMMC version 4 3 One UART with only TX RX and one UART with RTS CTS Three SPI controllers Three Two Wire Interfaces IR controller supporting CIR remoter ob LRADC for line control Internal 4 wire touch panel controller with pressure sensor and 2 point touch Internal 24 bit Audio Codec for 2 Ch headphone and 1 Ch microphone e PWM controller System 8 Ch normal DMA and 8 Ch dedicated DMA Internal 48K SRAM on chip 6 asynchronic timers 2 synchronic timers 1 watchdog and 2 AVS counters A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 24 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Security Security System Support DES 3DES AES encryption and decryption Support SHA 1 MD5 message digest Support 160 bit hardware PRNG with 192 bit seed 128 bit EFUSE chip ID Package eLQFP176 package A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 25
312. me LRADC_INTC Bit Read Wr Default Description ite Hex 31 16 12 R W 0x0 ADC1_KEYUP_IRQ_EN ADC 1 Key Up IRQ Enable 0 Disable 1 Enable 11 R W 0x0 ADC1_ALRDY_HOLD_IRQ_EN ADC 1 Already Hold Key IRQ Enable 0 Disable 1 Enable 10 R W 0x0 ADC 1 Hold Key IRQ Enable 0 Disable 1 Enable 9 R W 0x0 ADC1_KEYIRQ_EN ADC 1 Key IRQ Enable 0 Disable 1 Enable 8 R W 0x0 ADC1 DATA IRQ EN ADC 1 DATA IRQ Enable 0 Disable 1 Enable 13 4 R W 0x0 ADCO_KEYUP_IRQ_EN ADC 0 Key Up IRQ Enable 0 Disable 1 Enable 3 R W 0x0 ADCO_ALRDY_HOLD_IRQ_EN ADC 0 Already Hold IRQ Enable 0 Disable 1 Enable 2 R W 0x0 ADCO HOLD IRQ EN ADC 0 Hold Key IRQ Enable A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 Disable 1 Enable R W 0x0 ADCO KEYDOWN EN ADC 0 Key Down Enable 0 Disable 1 Enable R W 0x0 ADCO_DATA_IRQ_EN ADC 0 Data IRQ Enable 0 Disable 1 Enable 24 3 3 LRADC Interrupt Status Register Offset 0x08 Register Name LRADC_INT Bit Read Wr ite Default Hex Description 31 8 12 0x0 ADC1_KEYUP_PENDING ADC 1 Key up pending Bit When general key pull up it the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is e
313. me Detected StartofFrame Interrupt Enable 0 Ignore 2 R W IR 0x0 1 Enable interrupt generation due to Start of Flame WritebackDoneHead Interrupt Enable 0 Ignore 1 R W IR 0x0 1 Enable interrupt generation due to Write back Done Head SchedulingOverrun Interrupt Enable 0 Ignore 0 R W R 0x0 1 Enable interrupt generation due to Scheduling Overrun 22 6 6 HcInterruptDisable Register Register Name HcInterruptDisable Register Offset 0x414 Default Value 0x0 Read Write Bit HCD HC Default Description MasterInterruptEnable A written 0 to this field is ignored by HC A 1 written to this field disables interrupt generation due events specified in the other bits of this 31 R W R 0x0 register This field is set after a hardware or software reset 30 7 0x00 Reserved RootHubStatusChange Interrupt Disable 0 Ignore 6 R W R 0x0 1 Disable interrupt generation due to Root Hub Status Change FrameNumberOverflow Interrupt Disable 0 Ignore 5 R W R 0x0 1 Disable interrupt generation due to Frame Number Over Flow UnrecoverableError Interrupt Disable 0 Ignore 4 R W IR 0x0 1 Disable interrupt generation due to Unrecoverable Error ResumeDetected Interrupt Disable 0 Ignore 3 R W R 0x0 1 Disable interrupt generation due to Resume Detected StartofFrame Interrupt Disable 0 Ignore 2 R W IR 0x0 1 Disable interrupt generation due t
314. me planar YCbCr 420 mode the frame end means the field2 end and the other frame end means field end 26 4 11 CSI Interrupt Status Register Register Name CSI INT STA REG Offset Address 0X0034 Default Value 0X00000000 Read Wri Default Nkr een O te Hex VSYNC FLAG 07 R W vsync flag HB_OF R W Hblank FIFO overflow PRT_ERR Protection error ap ees aaas FIFO1 OF 03 R W FIFO1 overflow A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 282 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 FIFOO0 OF FIFOO overflow FRM DONE 01 R W CPT_DONE R W 26 4 12 CSI Window Width Control Register Register Name CSI_WIN_CTRL_W_REG Offset Address 0X0040 Default Value 0X00000000 Read Wri Default Description Reserved Reserved R W ACTIVE_START Horizontal pixel clock start Pixel data is valid from this clock 26 4 13 CSI Window Height Control Register Register Name CSI WIN CTRL H REG Offset Address 0X0044 Default Value 0X00000000 Read Wri Default Bit Description te Hex 31 29 Reserved ACTIVE LEN 28 16 R W Ox1E0 Wee ee Vertical line length Valid line number of a frame ACTIVE START 12 00 R W DEN Vertical line start data is valid from this line 26 4 14 CSI Buffer Length Register Register Name CSI BUF LEN REG Offset 0X0048 Default Value 0X00000000 Read Wri Default 2 Bit Description te Hex 31 13 Reserved B
315. ments are arranged in a temporary array where the first value is the smallest measurement and the last value is the largest measurement Bit1 and BO in Control Register MED 1 MEDO set the window of the median filter and therefore the number of measurements taken MEDI MEDO Median Filter Size A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 266 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 4 m ba ke Ol 16 Table25 1 Median Filter Size The averaging filter size determines the number of values to average BitS and Bit4 in Control Register 3 AVG1 AVG0 set the average to 2 3 4 or 8 samples Only the final averaged result is written into the result FIFO register AVG1 AVGO Averaging Filter Size 0 0 2 0 1 3 1 0 4 1 1 8 Table25 2 Averaging Filter Size When Bit4 of Control Register 3 is set 0 and Median Averaging Filter mode is disabled only one measurement is transferred to the register map The number specified with the MED1 and MEDO settings must be greater than or equal to the number specified with the AVG1 and AVGO settings If both settings specify the same number the median filter is switched off Setting Function M A Median filter is disabled output is the average of A converted results M gt A Output is the average of the middle values from the array of M measurements M lt
316. mode 001 YUV 4 2 2 010 YUV 4 2 0 011 YUV 4 1 1 Other reserved 3 2 1 0 R W 0x0 DATA_PS A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 301 Ou 7 Allwinner Technology CO Ltd Pixel sequence In interleaved YUV422 data mode 00 YIVOYOUO 01 VOY1U0YO 10 YIUOYOVO 11 UOY1VOYO In interleaved YU V444 data mode 00 VUYA 01 AYUV Other reserved In UV combined data mode UV component 00 VIU1V0U0 01 UIVIUOVO Other reserved In interleaved ARGB8888 data mode 00 BGRA 01 ARGB Other reserved A13 27 5 17 DEFE WB ADDRO REG Offset 0x50 Register Name DEFE_WB_ADDRO_REG Read Wr Default SSC Bit Description ite Hex WB_ADDR 31 0 R W 0x0 Write back address setting for scaled data 27 5 18 DEFE_OUTPUT_FMT_REG Offset 0x5C Register Name DEFE_OUTPUT_FMT_REG Read Wr Default sch Bit Description ite Hex 31 18 WB_Ch_Sel Write back channel select chsel 0 1 Ch3 17 16 R W 0 2 Ch4 3 Ch5 Other reserved 15 9 BYTE_SEQ 8 R W 0x0 Output data byte sequence selection 0 P3P2P1PO word A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 POP1P2P3 word For ARGB when this bit is 0 the byte sequence is BGRA and when
317. mtnnmnm nnntnnnmaunananiinniinidnanmanun n ns 396 PE Configure Register 0 geen mere er ere Er ery Rete nT wea enn nt eet Weer tere tre eee reer terrae Ter 397 PE Configure Register EEE NE 398 due HE 399 PE Configure Register S 34nci cies 399 PE ae FROGS UC seca sas sees a ences lee de ec ees ee cece es 399 PE Multi Driving Register 0 EE 399 PE Multi Driving Register Tsunami etant then 399 PE Pull Register Ow unnarennet 400 PE PUINRSGISIOT E 400 PF Configure Register Lee 400 PF Configure Register cscs 401 PF Configure e EE 401 PF Configure Register GE 401 PE Date Register ersen desi 401 PF Multi Driving Register Oz nent e a a ne erase EN Ee 402 PF Multi Driving Register Tasei nana 402 PE UR E EE 402 PF Pull Regist r EE 402 PG Configure Register 0 sc 402 PG Configure Register 1 ee 403 PG Config re FN 404 P S OMS 404 PG Data Register cnc ae 405 PG M lti Driving Register Vassverk 405 PG Multi Driving Register ME 405 PG a ed E E E 405 PG Pull Register Ass nn NN NS 405 PIO Interrupt Configure Register E 406 PIO Interrupt Configure Register le 406 PIO Interrupt Configure Register 2 eine 406 PIO Interrupt Configure Rester ene 406 PIO Interrupt Control Register usa ee tere eee 407 PIO Interrupt Status TE 407 PIO Interrupt Debounce Register sarsanitententennantmensenanendneantanentnttenttess 407 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 21 Jau 8 2013 Ou Allwinner Technology CO Ltd A1
318. n A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 352 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 disable 1 enable Note It executes at the beginning of the first blank line of TCONO timing 30 26 TCONO_IF 00 HV Sync DE 25 24 R W 0 01 8080 T F 10 TTL I F 11 reserved TCONO_RG_Swap 23 R W 0 0 default 1 swap RED and BLUE data at FIFO1 TCONO Test Value 22 R W 0 O all Os l all 1s TCONO_FIFO1_Rst 21 R W 0 Write 1 and then 0 at this bit will reset FIFO 1 Note holding time must be more than 1 DCLK TCONO_Interlace_En O disable l enable NOTE this flag is valid only when TCONO EN 1 20 R W 0 19 9 TCONO_State_Delay 8 4 R W 0 STA delay NOTE valid only when TCONO_EN 1 3 2 TCONO_SRC_SEL 00 DE CH1 FIFO1 enable 01 DE CH2 FIFO1 enable 10 DMA 565 input FIFO1 enable 11 Test intput FIFO1 disable 1 0 R W 0 Note These bits are sampled only at the beginning of the first blank line of TCONO timing Generally when input source changes it will change at the beginning of the first blank line of TCONO timing When FIFO and FIFO2 select the same source and FIFO2 is enabled it executes at the beginning of the first blank line of TV timing Also TCONO timing generator will reset to the beginning of the first blank line 29 3 8 TCONO DCLK REG
319. n a scheduling overrun is detected even if SchedulingOverrun in HclnterruptStatus has already been set This is used by HCD to monitor 17 16 R R W 0x0 any persistent scheduling problem 15 4 0x0 Reserved OwershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC When set HC will set the OwnershipChange field in HcInterruptStatus After the changeover this bit is cleared and remains so until the next 3 R W R W 0x0 request from OS HCD BulklListFilled This bit is used to indicate whether there are any TDs on the Bulk list It is set by HCD whenever it adds a TD to an ED in the Bulk list When HC begins to process the head of the Bulk list it checks BLF As long as BulkListFilled is 0 HC will not start processing the Bulk list If BulkListFilled is 1 HC will start processing the Bulk list and will set BF to 0 If HC finds a TD on the list then HC will set BulkListFilled to 1 2 R W R W 0x0 causing the Bulk list processing to continue If no TD is found on the A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 226 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Bulk list and if HCD does not set BulkListFilled then BulkListFilled will still be 0 when HC completes processing the Bulk list and Bulk list processing will stop ControlListFilled This bit is used to indicate whether there are any TDs on the Control list It is set by HCD whenever it
320. n loopback mode the modem control inputs dsr_n cts_n ri_n ded n are disconnected and the modem control outputs dtr_n rts_n outl n out2_n are looped back to the inputs internally If operating in infrared mode SIR MODE Enabled AND active MCR 6 set to one data on the sir_out_n line is held low while serial data output is inverted and looped back to the 4 R W sir_in line 3 2 RTS Request to Send This is used to directly control the Request to Send rts_n output The Request To Send rts_n output is used to inform the modem or data set that the UART is ready to exchange data When Auto RTS Flow Control is not enabled MCR 5 set to zero the rts_n signal is set low by programming MCR 1 RTS to a highIn Auto Flow Control AFCE_MODE Enabled and active MCR 5 set to one and FIFOs enable FCR 0 set to one the rts_n output is controlled in the same way but is also gated with the receiver FIFO threshold trigger rts_n is inactive high when above the threshold The rts_n signal is de asserted when MCR 1 is set low 0 rts_n de asserted logic 1 1 rts_n asserted logic 0 Note that in Loopback mode MCR 4 set to one the rts_n output is held inactive high while the value of this location is internally looped 1 R W back to an input DTR Data Terminal Ready This is used to directly control the Data Terminal Ready dtr_n output The value written to this location is inverted and driven out on dtr_n 0 R W 0 dt
321. nable 11 R W 0x0 ADC1_ALRDY_HOLD_PENDING ADC 1 Already Hold Pending Bit When hold key pull down and pull the general key down if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled 10 R W 0x0 ADC1_HOLDKEY_PENDING ADC 1 Hold Key pending Bit When Hold key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 NO IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable R W 0x0 ADC1_KEYDOWN_IRQ_PENDING ADC 1 Key Down IRQ Pending Bit When General key pull down the status bit is set and the interrupt line is set A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 251 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled R W 0x0 ADC1 DATA IRQ PENDING ADC 1 Data IRQ Pending Bit 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled R W 0x0 ADCO_KEYUP_PENDING ADC 0 Key up pending Bit When general key pull up it the
322. nable 0 Disable 1 Enable NDMA4_END_IRQ_EN 9 R W 0x0 Normal DMA 4 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA4_HF_IRQ_EN 8 R W 0x0 Normal DMA 4 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA3_END_IRQ_EN 7 R W 0x0 Normal DMA 3 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA3_HF_IRQ_EN 6 R W 0x0 Normal DMA 3 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA2_END_IRQ_EN 5 R W 0x0 Normal DMA 2 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA2_HF_IRQ_EN Normal DMA 2 Half Transfer Interrupt Enable 4 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 139 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 Disable 1 Enable R W 0x0 NDMA1_END_IRQ_EN Normal DMA 1 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA1_HF_IRQ_EN Normal DMA 1 Half Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMAO_END_IRQ_EN Normal DMA 0 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMAO_HF_IRQ_EN Normal DMA 0 Half Transfer Interrupt Enable 0 Disable 1 Enable 14 4 2 DMA IRQ Pending Status Register Default 0x00000000 Offset 0x04 Register Name DMA IRQ PEND STAS REG Bit Read Wr ite Default Hex Description 31 R W 0x0 DDMA7_END_I
323. nction Mode Select 0 Slave Mode 1 R W 1 Master Mode EN SPI Module Enable Control 0 Disable 0 R W 1 Enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 175 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 18 4 4 SPI Interrupt Control Register Register Name SPI INTCTL Offset OxOC Default Value 0x0000 0000 Bit Read Write Default Description 31 18 SSI Interrupt Enable Chip Select Signal SSx from valid state to invalid state 0 Disable 17 R W 0 1 Enable Transfer Completed Interrupt Enable 0 Disable 16 R W 0 1 Enable 15 TXFIFO under run Interrupt Enable 0 Disable 14 R W 0 1 Enable TX FIFO Overflow Interrupt Enable 0 Disable 13 R W 0 1 Enable TX FIFO 3 4 Empty Interrrupt Enable 0 Disable 12 R W 0 1 Enable TX FIFO 1 4 Empty Interrrupt Enable 0 Disable 11 R W 0 1 Enable TX FIFO Full Interrupt Enable 0 Disable 10 R W 0 1 Enable TX FIFO Half Empty Interrupt Enable 0 Disable 9 R W 0 1 Enable TX FIFO Empty Interrupt Enable 0 Disable 8 R W 0 1 Enable 7 RXFIFO under run Interrupt Enable 0 Disable 6 R W 0 1 Enable RX FIFO Overflow Interrupt Enable 0 Disable 5 R W 0 1 Enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 176 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 R W RXFIFO 3 4 F
324. ndicator input ri_n is asserted it is an indication that a telephone ringing signal has been received by the modem or data set 0 ri n input is de asserted logic 1 1 ri_n input is asserted logic 0 DSR Line State of Data Set Ready This is used to indicate the current state of the modem control line dsr_n This bit is the complement of dsr_n When the Data Set Ready input dsr_n is asserted it is an indication that the modem or data set is ready to establish communications with UART 0 dsr_n input is de asserted logic 1 1 dsr_n input is asserted logic 0 In Loopback Mode MCR 4 set to one DSR is the same as MCR 0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 196 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 DTR CTS Line State of Clear To Send This is used to indicate the current state of the modem control line cts n This bit is the complement of cts n When the Clear to Send input cts n is asserted it is an indication that the modem or data set is ready to exchange data with UART 0 cts_n input is de asserted logic 1 1 cts_n input is asserted logic 0 4 R In Loopback Mode MCR 4 1 CTS is the same as MCR 1 RTS DDCD Delta Data Carrier Detect This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read 0 no change on ded n since last read of MSR 1 cha
325. ner Technology All Rights Reserved 235 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 7 0 0x01 NumberDownstreamPorts These bits specify the number of downstream ports supported by the Root Hub It is implementation specific The minimum number of ports is 1 22 6 20 HcRhDescriptorB Register Offset 0x44c Register Name HcRhDescriptorB Register Default Value Read Write Bit HCD HC Default Description 31 16 R W 0x0 PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set When set the port s power state is only affected by per port power control Set ClearPortPower When cleared the port is controlled by the global power switch Set ClearGlobalPower If the device is configured to global switching mode PowerSwitchingMode 0 this field is not valid BitO Reserved Bitl Ganged power mask on Port 1 Bit2 Ganged power mask on Port 2 Bit15 Ganged power mask on Port 15 15 0 R W R 0x0 DeviceRemovable Each bit is dedicated to a port of the Root Hub When cleared the attached device is removable When set the attached device is not removable Bit0 Reserved Bitl Device attached to Port 1 Bit2 Device attached to Port 2 Bit15 Device attached to Port 15 22 6 21 HcRhStatus Registe
326. ng bit The read bit value is the value setup by software If 27 0 R W 0 the port is configured as functional pin the undefined value will be read 33 4 33 PE Multi Driving Register 0 Register Name PE_DRVO Offset OxA4 Default Value 0x0055 5555 Bit Read Write Default Description 31 24 PE n Multi Driving Select n 0 11 2i 1 2i 00 Level 0 01 Level 1 G 0 11 R W Ox 10 Level 2 11 Level 3 33 4 34 PE Multi Driving Register 1 Offset OxA8 Register Name PE_DRV1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 399 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 35 PE Pull Register 0 Register Name PE_PULLO Offset OxAC Default Value 0x0000 0000 Bit Read Write Default Description 31 24 PE n Pull up down Select n 0 11 21 1 2i 00 Pull up down disable 01 Pull up 1 0 11 R W 0x0 10 Pull down 11 Reserved 33 4 36 PE Pull Register 1 Register Name PE_PULL1 Offset OxBO Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 37 PF Configure Register 0 Register Name PF_CFGO Offset OxB4 Default Value 0x0040_4044 Bit Read Write Default Description 31 24 23 PF5 S
327. nge on ded n since last read of MSR Reading the MSR clears the DDCD bit Note If the DDCD bit is not set and the dcd_n signal is asserted low and a reset occurs software or otherwise then the DDCD bit is set 3 R when the reset is removed if the dcd_n signal remains asserted TERI Trailing Edge Ring Indicator This is used to indicate that a change on the input ri_n from an active low to an inactive high state has occurred since the last time the MSR is read 0 no change on ri_n since last read of MSR 1 change on ri_n since last read of MSR 2 R Reading the MSR clears the TERI bit DDSR Delta Data Set Ready This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read 0 no change on dsr_n since last read of MSR 1 change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit In Loopback Mode MCR 4 1 DDSR reflects changes on MCR 0 DTR Note If the DDSR bit is not set and the dsr_n signal is asserted low and a reset occurs software or otherwise the DDSR bit is set when the reset 1 R is removed if the dsr_n signal remains asserted DCTS Delta Clear to Send 0 R This is used to indicate that the modem control line cts_n has changed A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 197 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 since the last time the MSR was read 0 no change on ctsdsr n since last r
328. nnected Port read CurrentConnectStatus This bit reflects the current state of the downstream port 0 No device connected 1 Device connected write ClearPortEnable The HCD writes a 1 to clear the PortEnableStatus bit Writing 0 has no effect The CurrentConnectStatus is not affected by any write Note This bit is always read as 1 when the attached device is 0 R W R W_ 0x0 non removable DviceRemoveable NumberDownstreamPort 22 7 USB Host Special Requirement Name Description HCLK System clock provided by AHB bus clock This clock needs to be gt 30MHz CLK60M Clock from PHY for HS SIE is constant to be 60MHz CLK48M Clock from PLL for FS LS SIE is constant to be 48MHz A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 241 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 23 Audio Codec 23 1 Overview The embedded Audio Codec is a high quality stereo audio codec with headphone amplifier It features On chip 24 bit DAC for play back On chip 24 bit ADC for recorder Support analog digital volume control Support 48K and 44 1K sample family Support 192K and 96K sample Support Microphone recorder Stereo headphone amplifier that can be operated in capless headphone mode Support Virtual Ground to automatically change to True Ground to protect headphone amplifier and make functi
329. nnenneenssnnennennennennnsenenneenssnnennennennssnneenee 315 28 1 e EE 315 28 2 DEBE Block Tetange ees Nee SN DEE SN DEE EE DEE E DEE tenet acne 316 28 3 DEBE Deepen 316 28 3 1 ein Une PRE ee a ai ata aii a 316 28 3 2 CO 317 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 16 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 28 3 3 EEE ER 318 28 4 DEBE Register Stirner tavstbesteyetdeccasevevsueeehdeccanesevsteceisectesebbevneechineeevebbeties tes 319 285 DEBE Register Desenpun EE iaaa eaea aeaa aaia aaia K eaaa 320 28 5 1 DEBE Mode Control ROGISI r 2 2 neutres 320 28 5 2 DE Back Color Control Register geseet 321 28 5 3 DE Back Display Size Setting Register um anrsenmvmmevnvemvhevmr 321 28 5 4 BE EET cic te eene 322 28 5 5 DE Layer Coordinate Control Register 322 28 5 6 DE Layer Frame Buffer Line Width Register 323 28 5 7 DE Layer Frame Buffer Low 32 Bit Address Register AAA 323 28 5 8 DE Layer Frame Buffer High 4 Bit Address Register 323 28 5 9 DE Register Buffer Control Regist er Leavvsasmnmmnmen vi mv 324 28 5 10 DE Color Key MAX Register ees 324 28 5 11 DE Color Key MIN Register huden 325 28 5 12 DE Color Key Configuration Register ss 325 28 5 13 DE Layer Attribute Control RegisterO 325 28 5 14 DE Layer Attribute Control Register ss 327 28 5 15 Pixels Sequence Table nuavqsssn snaue ken 329 28 5
330. nsmitted ACK not received 0x28 Data byte transmitted in master mode ACK received 0x30 Data byte transmitted in master mode ACK not received 0x38 Arbitration lost in address or data byte 0x40 Address Read bit transmitted ACK received 0x48 Address Read bit transmitted ACK not received 0x50 Data byte received in master mode ACK transmitted 0x58 Data byte received in master mode not ACK transmitted 0x60 Slave address Write bit received ACK transmitted 0x68 Arbitration lost in address as master slave address Write bit received ACK transmitted A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 166 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 0x70 General Call address received ACK transmitted 0x78 Arbitration lost in address as master General Call address received ACK transmitted 0x80 Data byte received after slave address received ACK transmitted 0x88 Data byte received after slave address received not ACK transmitted 0x90 Data byte received after General Call received ACK transmitted 0x98 Data byte received after General Call received not ACK transmitted OxA0 STOP or repeated START condition received in slave mode OxA8 Slave address Read bit received ACK transmitted OxBO Arbitration lost in address as master slave address Read bit received ACK transmitted OxB8 Data byte transmitted in slave mode ACK received OxCO Data b
331. nual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 223 Jau 8 2013 7 Allwinner Technology CO Ltd A13 22 6 OHCI Register Description 22 6 1 HcRevision Register Register Name HcRevision Offset 0x400 Default Value 0x10 Read Write Bit HCD HC Default Description 31 8 0x00 Reserved Revision This read only field contains the BCD representation of the version of the HCI specification that is implemented by this HC For example a value of 0x11 corresponds to version 1 1 All of the HC implementations 7 0 R R 0x10 that are compliant with this specification will have a value of 0x10 22 6 2 HcControl Register Register Name HcRevision Offset 0x404 Default Value 0x0 Read Write Description Bit HCD HC Default 31 11 0x00 Reserved Remote WakeupEnable This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling When this bit is set and the ResumeDetected bit in HcInterruptStatus is set a remote wakeup is signaled to the host system Setting this bit has no impact on the 10 R W R 0x0 generation of hardware interrupt Remote WakeupConnected This bit indicates whether HC supports remote wakeup signaling If remote wakeup is supported and used by the system it is the responsibility of system firmware to set this bit during POST HC clear the bit upon a
332. nversion Time PEN SEN eZ DATA DATA FS_TIME Figure25 5 Single Touch and Pressure Measurement Conversion Time MA PES DATA as I DATA past lt gt FS_TIME Figure25 6 Single Touch No Pressure Measurement Mode Conversion Time EDDA PES PEN FS TIME Figure25 7 General ADC Mode 25 4 Principle of Operation 25 4 1 The Basic Principle The controller is a typical type of successive approximation ADC SAR ADC contains a sample hold analog to digital conversion serial data output functions The analog inputs X X Y Y via control register enter the ADC ADC can be configured as single ended or differential mode Selecting Aux ADC or temperature should be configured for single ended mode as a touch screen application it should be configured A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 262 Jau 8 2013 Allwinner Technology CO Ltd A13 as a differential mode which can effectively eliminate the parasitic resistance of the driver switch and external interference caused by measurement error and impact conversion accuracy 25 4 2 Single ended Mode When the TP Control Register 0 Bit12 ADC Mode Select is high the controller is in the measurement mode of AUX Temp the internal ADC reference voltage source is the single ended mode using the AVCC reference source a
333. o Digital A module which can transfer analog signal 15 LRADC ene Converter to digital signal The hardware block that interfaces with different image sensor interfaces and 16 CSI CMOS Sensor Interface provides a standard output that can be used for subsequent image processing A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Table of Contents Revision History cei sseces cscs sec ctasedevsecesetevcetiasechsteusvecediuseceoscesvscedivseesatessenesdzucededbcvsucestaucedvaceesucesaueedescevscustessseseews 1 Technical Items eeeseseveenvevnneenneenneennennneenneennennnennnennnennnennneennennnennnennnennnennnesnnennnennneennennneennennnennneennennnennneenneennennneeee 2 1 A13 Introduction eseceseevevnnevnneenneennennnennnennnennnennnennnennnennnennnennnennnennneennennnennnennnennnennneennennnennneenneenneenneenneeen 23 LE Fenes 23 2 Pin DeSCriptaOms sesssesssesssasssesisesssesssosssesssosesesssosesesssesesesssosesesssosesesesosesessseseseseseseseassnsesesesesesesssesesesesesesesssoses 26 Deals Po PENNEN 26 2 2 Pin Detail Description wisisesescseve cave oinaan inaianei EEE aai iaaa Eat 26 3 Architecture sesssessvesnnesnnennnennnennnennnennnennnennnennnennnennnnnnnnnnnennnnnnnennnennnennnennnennnnnnnennnennnennnennnennnennnennnennnennsenesee 27 3 1 Functional Block Diagram eene nibh nite RS vin a bs tnt ete eme t ete benne nt 27 32 Mem
334. o Start of Flame WritebackDoneHead Interrupt Disable 0 Ignore R W R 0x0 1 Disable interrupt generation due to Write back Done Head 0 R w R 0x0 SchedulingOverrun Interrupt Disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 229 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 Ignore 1 Disable interrupt generation due to Scheduling Overrun 22 6 7 HcHCCA Register Register Name HcHCCA Offset 0x418 Default Value 0x0 Read Write Bit HCD HC Default Description HCCA 31 8 This is the base address of the Host Controller Communication Area This area is used to hold the control structures and the Interrupt table that 31 8 R W IR 0x0 are accessed by both the Host Controller and the Host Controller Driver HCCA 7 0 The alignment restriction in HCHCCA register is evaluated by examining the number of zeros in the lower order bits The minimum alignment is 7 0 R R 0x0 256 bytes therefore bits 0 through 7 must always return 0 when read 22 6 8 HcPeriodCurrentED Register Offset Ox41c Register Name HcPeriodCurrentED PCED Default Value 0x0 Read Write Bit HCD HC Default Description R W 0x0 PCED 31 4 This is used by HC to point to the head of one of the Periodec list which will be processed in the current Frame The content of this register is updated by HC after a periodic ED
335. obalPower HCD clears this bit by writing ClearPortPower or ClearGlobalPower Which power control switches are enabled is determined by PowerSwitchingMode and PortPortControlMask NumberDownstreamPort In global switching mode PowerSwitchingMode 0 only Set ClearGlobalPower controls this bit In per port power switching PowerSwitchingMode 1 if the PortPowerControlMask NDP bit for the port is set only Set ClearPortPower commands are enabled If the mask is not set only Set ClearGlobalPower commands are enabled When port power is disabled CurrentConnectStatus PortEnableStatus PortSuspendStatus and PortResetStatus should be reset 0 port power is off 1 port power is on write SetPortPower The HCD writes a 1 to set the PortPowerStatus bit Writing a 0 has no effect R W R W Oxi Note This bit is always read as 1b if power switching is not supported 13 0x0 Reserved read PortResetStatus When this bit is set by writing to SetPortReset port reset signaling is asserted When reset is completed this bit is cleared when PortResetStatusChange is set This bit cannot be set if CurrentConnectStatus is cleared 0 port reset signal is not active 1 port reset signal is active 4 R W R W 0x0 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 239 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 write SetPortReset The HCD sets the port reset signaling by writing a 1
336. ock for NAND 0 mask 1 pass A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 65 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 12 R W 0x0 11 SD2_AHB_GATING 10 R W 0x0 Gating AHB Clock for SD MMC2 0 mask 1 pass SDI AHB GATING 9 R W 0x0 Gating AHB Clock for SD MMC1 0 mask 1 pass SDO_AHB_GATING 8 R W 0x0 Gating AHB Clock for SD MMCO 0 mask 1 pass BIST_AHB_GATING 7 R W 0x0 Gating AHB Clock for BIST 0 mask 1 pass DMA_AHB_GATING 6 R W 0x0 Gating AHB Clock for DMA 0 mask 1 pass SS_AHB_GATING 5 R W 0x0 Gating AHB Clock for SS 0 mask 1 pass 4 3 OHCI AHB GATING 2 R W 0x0 Gating AHB Clock for USB OHCI 0 mask 1 pass EHCI_AHB_GATING 1 R W 0x0 Gating AHB Clock for USB EHCI 0 mask 1 pass USBOTG_AHB_GATING 0 R W 0x0 Gating AHB Clock for USB OTG 0 mask 1 pass 6 4 18 AHB Module Clock Gating Register 1 Default 0x00000000 Offset 0x64 Register Name AHB_GATING_REG1 Read W Default Le Bit Description rite Hex 31 21 20 R W 0x0 Gating AHB Clock for Mali 400 0 mask 1 pass IEP_AHB_GATING 19 R W 0x0 Gating AHB Clock for IEP 0 mask 1 pass 18 15 FE_AHB_GATING 14 R W 0x0 Gating AHB Clock for DE FE 0 mask 1 pass 13 BE_AHB_GATING
337. of its adjacent pixels on the input grid To find these adjacent pixels the output grid needs to be overlaid on the input grid and the starting pixels XOYO of the two grids are alignd To identify the adjacent input pixels for a given output pixel the output pixel X pixel number along the output line and Y pixel line number within window should be divided by their corresponding scaling factors Xout Xin horizontal scaling factor where horizontal scaling factor input length output length Yout Yin vertical scaling factor where vertical scaling factor input height output height Note that the resulting Xin and Yin values will be real numbers because the output pixels will usually fall between the input pixels The fractional portion indicates the fractional distance to the next pixel To calculate the output pixel value you use the value for the nearest pixel to the left and above and combine it with the value of the other adjacent pixel s For example horizontal interpolation uses the starting pixel to the left interpolated with the next pixel to the right with the fractional value used to determine the weighting for the interpolation 27 3 2 Quantizing The new position is forced to be at a location n 32 in H and V relative to the position of the original pixel grid Line O O TapO Tap1 Tap2 Tap3 Line n O O Tap1 0 7 15 23 31 Line n41 O SCH BER X Pixel Location s g Tap2 Es Line n 2 O O 3 Horizon
338. of the Periodic Schedule If this bit is a zero then the status of the Periodic Schedule is disabled If this bit is a one then the status of the Periodic Schedule is enabled The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register When this bit and the Periodic Schedule Enable bit are the same value the Periodic Schedule is either enabled 1 or 14 R 0 disabled 0 Reclamation This is a read only status bit which is used to detect an empty 13 R 0 asynchronous schedule HC Halted This bit is a zero whenever the Run Stop bit is a one The Host Controller Sets this bit to one after it has stopped executing as a result of the 12 R 1 Run Stop bit being set to 0 either by software or by the Host Controller A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 215 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 Hardware e g internal error The default value is 1 11 6 Reserved These bits are reserved and should be set to zero R WC Interrupt on Async Advance System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register This status bit indicates the assertion of that inter
339. on ite Hex STMRO_CUR_VALUE_LOW 31 0 R W D Sync Timer 0 Current Value 31 0 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 106 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 12 3 7 Sync Timer 0 Current Value Hi Register Offset 0x20 Register Name SYNC_TMRO_CURNT_HI_REG Read Wr Default 2 Bit Description ite Hex 31 24 STMRO_CUR_VALUE_HI 23 0 R W x Sync Timer 0 Current Value 55 32 Note 1 Timer 0 current value is a 56 bit down counter from interval value to 0 2 The current value register is a 56 bit register When read or write the current value the Low register should be read or write first 12 3 8 Sync Timer 1 Control Register Default 0x00000004 Offset 0x30 Register Name SYNC TMR1 CTRL REG Read Wr Default Bit Description ite Hex SYNC TMRI1 TEST Sync timer test mode In test mode the low register should be set to 0x1 the 31 R W 0x0 i high register will down count The counter needs to be reloaded 0 normal mode 1 test mode 30 8 STMR1_MODE Sync Timer mode 0 Continuous mode When reaches the internal value the timer will not be 7 R W 0x0 disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically Sync Timer 1 Clock Source is fixed to AHBCLK STMR1_CLK_SRC Select the pre scal
340. on work in normal mode 23 2 Audio Codec Block Diagram DDE PREGI J SS MICI o gt e gt MICOI HPCOM AI 32dB 35dB 38dB 41dB VMICEN 200 ohm VMIC NN gt 2 526V Pa D Pa SYSTEM ri BUS MICI O gt GNN When ADCIS 010 ADCINL ADCINR MICO1 When ADCIS 110 ADCINL MIXOUTL ADCINR MIXOUTR ADCG 4 5dB 3dB 1 5dB OdB 1 5dB 3dB 4 5dB 6dB 4 5dB 3dB 1 5dB 0dB 1 5dB 3dB 4 5dB 6dB gt MICOG LNOG STEREO am MICILS MICIRS PAEN PAVOL D PAMUTE MIXPAS DACMIXS HPOUTL R OG a DX 63 STEP VOLUME From OdB to 62dB MIXEN DACPAS Figure23 1 Audio Codec Block Diagram A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 242 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd 23 3 Audio Codec Register List A13 Module Name Base Address AC 0x01C22C00 Register Name Offset Description AC DAC DPC 0x00 DAC Digital Part Control Register AC DAC FIFOC 0x04 DAC FIFO Control Register AC DAC FIFOS 0x08 DAC FIFO Status Register AC DAC TXDATA Ox0C DAC TX Data Register AC DAC ACTL 0x10 DAC Analog Control Register AC_ADC_FIFOC Ox1C ADC FIFO Control Register AC ADC FIFOS 0x20 ADC FIFO Status Register AC ADC RXDATA 0x24 ADC RX Data Register AC ADC ACTL 0x28 ADC Analog Control Register AC DAC CNT 0x30 DAC TX FIFO Counter Register AC ADC C
341. ookup and the corresponding colors output On chip SRAM array Inputting external frame buffer data Output color av Ro Go BO 8bpp ar R1 G1 B1 e S a5 R5 Gs B5 3 5 38 133 28 m ae roles 038 R38 G38 B38 0433 R133 G133 B133 028 R28 G28 B28 see e 0254 R254 G254 B254 0255 R255 G255 B255 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 342 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 28 5 40 Internal Frame Buffer Mode In internal frame buffer mode the RAM array is used as an on chip frame buffer each pixel in the RAM array is used to select one of the palette 32 bit colors 1bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 Pll P1O POO P08 PO7 PO6 POS P04 PO3 PO2 POI POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 2bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14 P13 P12 Pll P10 P09 P08 P07 P06 POS P04 P03 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 4bpp Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 1
342. oot operation Figure 4 Boot Diagram A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 31 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 5 Power Management Unit PMU 5 1 Overview The Power Management Unit PMU aims to reduce dynamic power consumption and static leakage current to extend the life of batteries in end products This module is the central control module for CPU clock and power management signals in the device 5 2 PMU Register List Module Name Base Address PMU 0x01C25400 Register Name Offset Description PMU DVFS CTRL REGO 0x0000 PMU Control Register 0 PMU DVFS CTRL REGI 0x0004 PMU Control Register 1 0x0008 PMU DVFS CTRL REG2 0x000C PMU Control Register 2 0x0010 0x0014 PMU DVFS CTRL REG3 0x0018 PMU Control Register 3 PMU DVFS TIMEOUT CTRL REG Ox001C PMU Timeout Control Register PMU AXI AUTO SWT REGO 0x0020 PMU AXI Auto Switch CLK RegisterO PMU AXI AUTO SWT REGI 0x0024 PMU AXI Auto Switch CLK Register 1 PMU IRQ EN REG 0x0040 PMU IRQ Enable Register PMU IRQ STATUS REG 0x0044 PMU IRQ Status Register PMU STATUS REG 0x0048 PMU Status Register PMU CPUVDD CTRL REG ADDR 0x004C PMU CPUVDD Register Address PMU_TWI_ADDR_REG 0x0050 PMU TWI Address PMU CPUVDD VALUE REG 0x0054 PMU Cpuvdd Value PMU CPUVDD RAMP CTRL REG 0x0058 PMU CPUVDD Voltage Ramp Control PMU 32KHZ CPUVDD M
343. or M M Factor 1 The range is from 1 to 4 6 4 2 PLL1 Tuning Default 0x0A 101000 Offset 0x04 Register Name PLL1 TUN REG Bit sd Pr Description ite Hex 31 28 27 R W Ox1 26 R W 0x0 25 23 R W Ox4 22 16 R W 0x10 15 R W 0x0 14 8 R W 0x10 7 R W 0x0 6 0 R 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 56 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd 6 4 3 PLL2 Audio Default 0x08100010 A13 Offset 0x08 Register Name PLL2 CFG REG Read Wr Default RIRS Bit f Description ite Hex PLI 2 Enable 0 Disable 1 Enable The PLL2 is for Audio 31 R W 0x0 1X 48 N PreDiv PostDiv 2 not 50 duty 2X 48 N PreDiv 4 8X 4 50 duty 4X 48 N PreDiv 2 8X 2 50 duty 8X 48 N PreDiv not 50 duty PLL2 Output 24MHz N PLL2_PRE_DIV PLL2_POST_DIV 30 PLL2 POST DIV PLL2 post divider 3 0 29 26 R W 0x2 0000 Ox1 1111 0x10 25 21 R W 0x0 20 16 R W 0x10 15 PLI 2 Factor N PLL2 Factor N Factor 0 N 1 14 8 R W 0x0 Factor 1 N 1 Factor 0x7F N 0x7F 7 5 PLL2_PRE_DIV PLL2 pre divider 4 0 4 0 R W 0x10 00000 0x1 11111 0x20 6 4 4 PLL2 Tuning Default 0x00000000 Offset 0xOC Register Name PLL2_TUN_REG Read Wr Default SC Bit Description ite Hex 31 R W 0x0 30 29 R W 0x0 28 20 R W 0x
344. or polled handshaking This 2 Wire Controller can be operated in standard mode 100K bps or fast mode up to 400K bps Multiple Masters and 10 bit addressing Mode are supported for this specified application General Call Addressing is supported in Slave mode The 2 Wire Controller features Software programmable for Slave or Master Support Repeated START signal Support Multi master systems Support 10 bit addressing with 2 Wire bus Perform arbitration and clock synchronization Own address and General Call address detection Interrupt on address detection Support speed up to 400K bits s fast mode Support operation from a wide range of input clock frequencies 17 2 TWI Timing Diagram Data are always transferred 1 In unit of byte 8 bit 2 Each byte followed by an acknowledge bit 3 Unlimited number of byte in each data transfer 4 Data are transferred in serial with MSB first 5 The receiver will hold SCL low to force the transmitter to enter a wait state while it is waiting for responses from the microprocessor after every byte transfer Acknowledge is indispensible in data transfer and related acknowledge clock pulse is generated by the master After sending a byte the transmitter will release the SDA line and one of the following two cases will occur a The SDA is pulled down by the receiver and an acknowledge signal is sent back b The SDA is left high and a not acknowled
345. ory Mapping ss sa sase sive ccsien sdaatacsacesien ov eseuaestne vas da eena ea nE AAAA E NE AAE EAE ARA TEAR Raai 27 4 Boot System A E A E EA EEA EE A 31 ZE Overview RE EEN EEEEAEENNENENEAEENENENAEENENENEAEENEAENEAEENAEN ACEN 31 42 BootDiasriMi ennnen RPR 31 5 Power Management Unit PMU sscsisscistsccicicesissctzcestiedcestsedseocstetecsseccdseoceseccevestsdecesesedecsescescsesseucseoseessceer 32 SL DME L VIS W nan ne nn ta avec gd pn a ee anne eee 32 9 2 PMU REG ister Listessi eene reae enen eienaar 32 5 3 PMU Register Descuiption teisti TE 33 5 3 1 PMU DVFS Control Register ee 33 5 3 2 PMU DVFS Control Register 1 Default 0Ox00001010 34 5 3 3 PMU DVFS Control Register 2 EE 34 5 3 4 PMU AXI Clock Range Registero nement 35 5 3 5 PMU AXI Clock Range Register 2 uemienneennnunienieenimjehenibiadd 35 5 3 6 PMU DVFS Control Register SR 35 5 3 7 PMU DVFS TimeOut Control Register Default OxOO0OO002 35 5 3 8 Ge IERT reit EE 36 5 3 9 PMU IRQ Status Register att ac eee eege 37 5 3 10 PMU Status PSS 38 5 3 11 PMU CPUVDD DCDC Control Register Address Default 0x00000023 38 5 3 12 PMU TWI Address Default 0Ox00000068 38 5 3 13 PMU CPUVDD Value Default 0x00000016 VU 38 5 3 14 PMU CPUVDD Voltage Ramp Control in DM 39 5 3 15 PMU 32KHz CPUVDD Minimum Value Default Ox0000000C 39 5 3 16 PMU VF Table E RE 40 5 3 17 PMU VF Table EE hu 40
346. paused by setting AVS CNTO PS to 1 When it is paused the counter won t increase 11 3 22 AVS Counter 1 Register Default 0x00000000 Offset 0x88 Register Name AVS_CNT1_REG Read Default at Bit Description Write AVS CNTI Counter 1 for Audio Video Sync Application The high 32 bits of the internal 33 bits 90KHz counter register The initial value of the internal 33 bits counter register can be set by software The 31 0 R W 0x0 aor LSB bit of the 33 bits counter register should be zero when the initial value is updated It will count from the initial value The initial value can be updated at any time It can also be paused by setting AVS_CNT1_PS to 1 When it is paused the counter won t increase 11 3 23 AVS Counter Divisor Register Default 0x05DBO05DB Offset Ox8C Register Name AVS_CNT_DIVISOR_REG Bit SE ES Description Write 31 28 AVS_CNT1_D Divisor N for AVS Counter The number N is from 1 to 0x7ff The zero value is reserved The internal 33 bits counter engine will maintain another 12 bits counter 27 16 R W 0x5DB The 12 bits counter is used for counting the cycle number of one 24Mhz clock When the 12 bits counter reaches gt N the divisor value the internal 33 bits counter register will increase 1 and the 12 bits counter will reset to zero and restart again Notes It can be configured by software at any time 15 12
347. pt Enable Register O HelnterruptDisable 0x414 OHCI Interrupt Disable Register OHCI Memory Pointer Partition Register O_HcHCCA 0x418 OHCI HCCA Base O_HcPeriodCurrentED Ox41c OHCI Period Current ED Base O_HcControlHeadED 0x420 OHCI Control Head ED Base O_HcControlCurrentED 0x424 OHCI Control Current ED Base O_HcBulkHeadED 0x428 OHCI Bulk Head ED Base O HcBulkCurrentED Ox42c OHCI Bulk Current ED Base O_HcDoneHead 0x430 OHCI Done Head Base OHCI Frame Counter Partition Register O_HcFmInterval 0x434 OHCI Frame Interval Register A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 208 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 O HcFmRemaining 0x438 OHCI Frame Remaining Register O_HcFmNumber Ox43c OHCI Frame Number Register O HePerioddicStart 0x440 OHCI Periodic Start Register O_HcLSThreshold 0x444 OHCI LS Threshold Register OHCI Root Hub Partition Register O_HcRhDescriptorA 0x448 OHCI Root Hub Descriptor Register A O_HcRhDesriptorB Ox44c OHCI Root Hub Descriptor Register B O_HcRhStatus 0x450 OHCI Root Hub Status Register O_HcRhPortStatus 0x454 OHCI Root Hub Port Status Register 22 5 EHCI Register Description 22 5 1 EHCI Identification Register Register Name CAPLENGTH Offset 0x00 Default Value Implementation Dependent Bit Read Write Default Description CAPLE
348. pyright 2013 Allwinner Technology All Rights Reserved 68 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Bit E E Description ite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 25 24 RW 0x0 S 01 PLL6 10 PLL5 11 23 18 CLK_DIV_RATIO_N 17 16 R W 0x0 Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 CLK_DIV_RATIO_M 3 0 R W 0x0 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 23 SD1 Clock Default 0x00000000 Offset Ox8C Register Name SD1_SCLK_CFG_REG Bit oe pee Description ite Hex SCLK_GATING Gating Special Clock Max Clock 200MHz 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 CLK_SRC_SEL Clock Source Select 25 24 R W 0x0 ie 01 PLL6 10 PLL5 11 23 18 CLK DIV RATIO N 17 16 R W 0x0 S i Clock pre divide ratio n A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 69 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 The select clock source is pre divided by
349. r Register Name HcRhStatus Register Offset 0x450 Default Value Read Write Bit HCD HC Default Description write ClearRemoteWakeupEnable 31 W R 0 Write a 1 clears DeviceRemoteWakeupEnable Write a 0 has no effect 30 18 0x0 Reserved A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 236 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 OverCurrentIndicatorChang This bit is set by hardware when a change has occurred to the OverCurrentIndicator field of this register The HCD clears this bit by 17 R W R 0 writing a 1 Writing a 0 has no effect read LocalPowerStartusChange The Root Hub does not support the local power status features thus this bit is always read as 0 write SetGlobalPower In global power mode PowerSwitchingMode 0 this bit is written to 1 to turn on power to all ports clear PortPowerStatus In per port power mode it sets PortPowerStatus only on ports whose 16 R W R 0x0 PortPowerControlMask bit is not set Writing a 0 has no effect read DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt 0 ConnectStatusChange is not a remote wakeup event 1 ConnectStatusChange is a remote wakeup event write SetRemoteWakeupEnable Wri
350. r A zero in this field indicates there are no companion host controllers And a value larger than zero in this field indicates there are companion USB1 1 host controller s 15 12 R 0 This field will always be 0 Number of Port per Companion Controller N_PCC This field indicates the number of ports supported per companion host controller host controller It is used to indicate the port routing configuration to system software 11 8 R 0 This field will always fix with 0 Port Routing Rules This field indicates the method used by this implementation for how all ports are mapped to companion controllers The value of this field has the following interpretation Value Meaning The first N_PCC ports are routed to the lowest numbered 0 function companion host controller the next N_PCC port are routed to the next lowest function companion controller and so on i The port routing is explicitly enumerated by the first N_PORTS elements of the HCSP PORTTOUTE array 7 R 0 This field will always be 0 Reserved 6 4 0 These bits are reserved and should be set to zero N_PORTS This field specifies the number of physical downstream ports implemented on this host controller The value of this field determines how many port registers are addressable in the Operational Register Space Valid values are in the range of 0x1 to OxOf 3 0 R 1 This field is always 1 22 5 4 EHCI Host Control Cap
351. r Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 186 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 DLL Divisor Latch Low Lower 8 bits of a 16 bit read write Divisor Latch register that contains the baud rate divisor for the UART This register may only be accessed when the DLAB bit LCR 7 is set and the UART is not busy USR 0 is zero The output baud rate equals to the serial clock sclk frequency divided by sixteen times the value of the baud rate divisor as follows baud rate serial clock freq 16 divisor Note that with the Divisor Latch Registers DLL and DLH set to zero the baud clock is disabled and no serial communications occur Also once the DLL is set at least 8 clock cycles of the slowest UART clock 7 0 R W 0 should be allowed to pass before transmitting or receiving data 19 4 4 UART Divisor Latch High Register Register Name UART DLH Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DLH Divisor Latch High Upper 8 bits of a 16 bit read write Divisor Latch register that contains the baud rate divisor for the UART This register may only be accessed when the DLAB bit LCR 7 is set and the UART is not busy USR 0 is zero The output baud rate equals to the serial clock sclk frequency divided by sixteen times the value of the baud rate divisor as follows baud rate ser
352. r lt Color Max 11 match if Color gt Color Max or Color lt Color Min CKG MATCH Green Match Rule 00 always match O1 always match 10 match if Color Min lt Color lt Color Max 11 match if Color gt Color Max or Color lt Color Min CKB MATCH Blue Match Rule 00 always match O1 always match 10 match if Color Min lt Color lt Color Max 11 match if Color gt Color Max or Color lt Color Min 28 5 13 DE Layer Attribute Control Register0 Register Name DEBE ATTCTL REGO A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 325 Jau 8 2013 Ou Allwinner Technology CO Ltd Layer0 0x890 Layer1 0x894 Layer2 0x898 Layer3 0x89C Read Wri Default Description LAY_GLBALPHA Alpha value Alpha value is used for this layer LAY_WORKMOD Layer working mode selection 00 normal mode Non Index mode 01 palette mode Index mode 10 internal frame buffer mode 11 gamma correction Except the normal mode if the other working mode is selected the on chip SRAM will be enabled PREMUL 0 normal input layer 1 pre multiply input layer Other reserved CKEN Color key Mode 00 disabled color key 01 The layer color key matches another channel pixel data in Alpha Blender 1x Reserved Only 2 channels pixel data can get to Alpha Blender at the same screen coordinate LAY_PIPESEL Pipe Select 0 select Pipe 0 1 select Pipe 1 Priority The rule is
353. r_n de asserted logic 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 193 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 1 dtr_n asserted logic 0 The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications Note that in Loopback mode MCR 4 set to one the dtr_n output is held inactive high while the value of this location is internally looped back to an input 19 4 10 UART Line Status Register Register Name UART LSR Offset 0x14 Default Value 0x0000 0060 Bit Read Write Default Description 31 8 FIFOERR RX Data Error in FIFO When FIFOs are disabled this bit is always 0 When FIFOs are enabled this bit is set to I when there is at least one PE FE or BI in the RX FIFO It is cleared by a read from the LSR register provided there are no 7 R 0 subsequent errors in the FIFO TEMT Transmitter Empty If the FIFOs are disabled this bit is set to 1 whenever the TX Holding Register and the TX Shift Register are empty If the FIFOs are enabled this bit is set whenever the TX FIFO and the TX Shift Register are empty In both cases this bit is cleared when a byte is written to the TX 6 R 1 data channel THRE TX Holding Register Empty If the FIFOs are disabled this bit is set to 1 whenever the TX Holding Register is empty and ready to accept new data and it
354. rds RX FIFO and 32 words TX FIFO for high speed application Support CPU mode and DMA mode Support Interrupt 31 2 Security System Block Diagram ZN 32 words TE RXFIFO l AHB Bus SHA 1 DES Register AES MDS eem File SS PRNG 32 words Ba TX FIFO r Interrupt amp DMA KZ RX FIFO TX FIFO DRQ Y Y DR D DMA Figure31 1 Security System Block Diagram 31 3 Security System Register List Module Name Base Address SS 0x01C15000 Register Name Offset Description SS_CTL 0x00 Security Control Register SS KEYO 0x04 Security Input Key 0 PRNG Seed 0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 373 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 SS KFY1 0x08 Security Input Key 1 PRNG Seed I SS KEY7 0x20 Security Input Key 7 SS IVO 0x24 Security Initialization Vector 0 SS_IV1 0x28 Security Initialization Vector 1 SS_IV2 Ox2C Security Initialization Vector 2 SS_IV3 0x30 Security Initialization Vector 3 SS_CNTO 0x34 Security Preload Counter 0 SS_CNT1 0x38 Security Preload Counter 1 SS_CNT2 0x3C Security Preload Counter 2 SS_CNT3 0x40 Security Preload Counter 3 SS_FCSR 0x44 Security FIFO Control Status Register SS_ICSR 0x48 Security Interrupt Control Status Register SS_MDO Ox4
355. rn memory block 0x4800 0x4BFF Description te Hex Hardware cursor pixel pattern 31 00 R W UDF Specify the color displayed for each of the hardware cursor pixels 28 5 38 DE HWC Palette Table Offset DE HW palette table 0x4C00 0x4 FFF Description te Hex Bit Bit The following figure only with 2bpp mode shows the RAM array used for hardware cursor palette lookup and the corresponding colors output A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 341 Jau 8 2013 AW Allwinner Technology CO Ltd A13 Output color HWC Index memory array 2bpp mode a2 R2 G2 B2 HWC palette table bit7 bau a0 RO GO BO 3 2 0 2 ai R2 G2 Ba a3 R3 GO B3 Color0 av RO GO BO S Color1 al RI GU BI S oi R G2 B 1 3 2 2 2 R GO B 3 3 0 1 a3 R3 G3 B3 Color254 254 R254 G254 B254 i ai Rt o BI EE Hardware cursor index memory Color255 10 D al RI GI BI amp palette av RO GO BO a3 R3 GO B3 a3 R3 G3 B3 28 5 39 Palette Mode Offset Pipe0 0x5000 0x53FF Pipe palette color table SRAM block Pipe1 0x5400 0x57FF Read Wri Default Description te Hex In this mode RAM array is used for palette lookup table each pixel in the layer frame buffer is treated as an index into the RAM array to select the actual color The following figure shows the RAM array used for palette l
356. rnrrrrrerrrnrerrnnnernn 49 6 Clock Control Module CCM eesosssevvvveesesssennnvnneeeesesennnenvnnessnnssnnnnnnnneeenessnnnnnnnnessnnssnnnsnnnnesennss nnnsnnneeeeneee 50 GL OQVEIVIEW EE 50 6 2 Clock Tree Diagram stiras tainai ts ease Sebati cabs tone net nee eae eas Ss tement ana n etat net tata n etat kataia titine 51 63 CCM Register ist ST a a ns ee ea ns et ete ane Set ete ass other 53 GA COM Resistor IDGSCr e EE 55 6 4 1 PLL1 Core Default EE 55 6 4 2 PLL1 Tuning Default 0x0A101000 eer 56 6 4 3 Pie Audie Default 0x08 100010 avvente 57 6 4 4 PLL2 Tuning Default 0x00000000 2 2 nkinnnnhnhiihbihnainnnnhnheanands 57 6 4 5 PLL3 Video Default OXO0 MODO 58 6 4 6 PLL4 VE Default 021081000 eie 58 6 4 7 PLL5 DDR Default Dt 1 REENEN 59 6 4 8 PLUS Tuning Default 0x14880000 EE 60 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 5 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 6 4 9 PLL6 Default 0x21009931 rnnrnnennnnronrnnrnnverrnrnrrrnrnrrrnvrrrnnrrrnnenrrnnerrnnnerrnnenrrnnerrnnnn 60 6 4 10 PLL7 Default OxO0 1ODO6e2 nee 61 6 4 11 PLL1 Tuning2 Default 0x00000000 ina 62 6 4 12 PLL5 Tuning2 Default 0x00000000 rrnrrerenvrrrvnrnrrnnverrnnnrrrnrnrrrnrerrnnnerrnnerrrnnenrnnnn 62 6 4 13 OSC24M Default OsO0O 1 20012 63 6 4 14 CPU AHB APBO Clock Ratio Default 0x00010010 ssssssssssssessressrnsrrnerrreerrerrrnee 63 6 4 15 AP
357. rol Register TCONO_FRM_SEEDO_REG 0x0014 TCON FRM Seed Register0 TCONO FRM SEEDI REG 0x0018 TCON FRM Seed Register 1 TCONO FRM SEED 2 REG 0x001C TCON FRM Seed Register2 TCONO_FRM_SEED3_REG 0x0020 TCON FRM Seed Register3 TCONO_FRM_SEED4 REG 0x0024 TCON FRM Seed Register4 TCONO FRM SEEDS REG 0x0028 TCON FRM Seed Register5 TCONO FRM TABO REG 0x002C TCON FRM Table Register0 TCONO_FRM_TAB1 REG 0x0030 TCON FRM Table Register TCONO FRM TAB2 REG 0x0034 TCON FRM Table Register2 TCONO FRM TAB3 REG 0x0038 TCON FRM Table Register3 TCONO CTL REG 0x0040 TCONO Control Register A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 348 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 TCONO DCLK REG 0x0044 TCONO Data Clock Register TCONO BASICO REG 0x0048 TCONO Basic Timing Register0 TCONO BASIC1 REG 0x004C TCONO Basic Timing Register1 TCONO BASIC2 REG 0x0050 TCONO Basic Timing Register2 TCONO BASIC3 REG 0x0054 TCONO Basic Timing Register3 TCONO HV IF REG 0x0058 TCONO Hv Panel Interface Register TCONO CPU IF REG 0x0060 TCONO CPU Panel Interface Register TCONO_CPU_WR_REG 0x0064 TCONO CPU Panel Write Data Register TCONO_CPU_RDO_REG 0x0068 TCONO CPU Panel Read Data RegisterO TCONO_CPU_RD1_REG 0x006C TCONO CPU Panel Read Data Register1 TCONO IO POL REG 0x0088 TCONO IO Polarity Register
358. rrrnrrrrrnrnnrrnrnrrrnrerrnnnn 102 11 3 27 64 bit Counter High Register Default 0x00000000 ee eee eeeeeeeeeeeeeeeeeeeeeeeaes 102 11 3 28 64 bit Counter Control Register Default 0x00000000 rrrrrrnrvrrrnrnrrrnrnrrrnrerrnnnn 102 11 3 29 CPU Config Register Default Ox00000000 103 12 Synchromic KT 104 VL OM 104 12 2 Sync Timer Resister Lists 104 12 3 Sync Timer Register Descriptt OM ssisiccssccsesscsessssvassssnsecsassvesavecstendesessssavee cxastvausssdoecscnentesessessesses 104 12 3 1 Sync Timer IRQ Enable Register Default Ox00000000 104 12 3 2 Sync Timer IRQ Status Register Default 0x00000000 eee cece eeeeeeeeeeeeeeeees 105 12 3 3 Sync Timer 0 Control Register Default 0x00000004 eee eee eee eeteeeeeeeeeeteeees 105 12 3 4 Sync Timer 0 Interval Value Low Register Lumsk 106 12 3 5 Sync Timer 0 Interval Value High Register 106 12 3 6 Sync Timer 0 Current Value Lo Register 106 12 3 7 Sync Timer 0 Current Value Hi Register mum 107 12 3 8 Sync Timer 1 Control Register Default 0Ox00000004 sssssssnsssrnssrnesrnerresrrnernene 107 12 3 9 Syne Timer 1 Interval Value Low Regist r ss ssss stunt 108 12 3 10 Sync Timer 1 Interval Value High Register 2222 108 12 3 11 Sync Timer 1 Current Value Low Register 108 12 3 12 Sync Timer 1 Current Value High Register rnrnonrnnrnvnnnvvnnnnnnnvnnnrnnnnnnrnvnnnrnnnnnnnnnne 10
359. rupt source R WC Host System Error The Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module When this error occurs the Host Controller clears the Run Stop bit in the Command register to prevent further execution of the scheduled TDs R WC Frame List Rollover The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero The exact value at which the rollover occurs depends on the frame list size For example if the frame list size is 1024 the Frame Index Register rolls over every time FRINDEX 13 toggles Similarly if the size is 512 the Host Controller sets this bit to a one every time FRINDEX 12 toggles R WC Port Change Detect The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J K transition detected on a suspended port This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port s Port Owner bit R WC USB Error Interrupt USBERRINT The Host Controller sets this bit to 1 when completion of USB transaction results in an error condition e g error counter underflow If the TD on which th
360. s INTC IRQ PEND REG2 0x0018 Interrupt IRQ Pending 2 Status 0x001C INTC FIQ PEND REGO 0x0020 Interrupt FIQ Pending 0 Status INTC FIQ PEND REGI 0x0024 Interrupt FIQ Pending 1 Status INTC FIQ PEND REG2 0x0028 Interrupt FIQ Pending 2 Status 0x002C INTC SEL REGO 0x0030 Interrupt Select 0 INTC SEL REGI 0x0034 Interrupt Select 1 INTC_SEL_REG2 0x0038 Interrupt Select 2 0x003C INTC EN REGO 0x0040 Interrupt Enable 0 INTC EN REGI 0x0044 Interrupt Enable 1 INTC_EN_REG2 0x0048 Interrupt Enable 2 0x004C INTC_MASK_REGO 0x0050 Interrupt Mask 0 INTC MASK REGI 0x0054 Interrupt Mask 1 INTC_MASK_REG2 0x0058 Interrupt Mask 2 0x005C INTC RESP REGO 0x0060 Interrupt Response 0 INTC RESP REGI 0x0064 Interrupt Response 1 INTC_RESP_REG2 0x0068 Interrupt Response 2 0x006C INTC FORCE REGO 0x0070 Interrupt Fast Forcing 0 INTC FORCE REGI 0x0074 Interrupt Fast Forcing 1 INTC FORCE REG2 0x0078 Interrupt Fast Forcing 2 0x007C INTC SRC PRIO REGO 0x0080 Interrupt Source Priority 0 INTC SRC PRIO REGI 0x0084 Interrupt Source Priority 1 INTC_SRC_PRIO_REG2 0x0088 Interrupt Source Priority 2 INTC SRC PRIO REG3 0x008C Interrupt Source Priority 3 INTC SRC PRIO REG4 0x0090 Interrupt Source Priority 4 INTC SRC PRIO REGS 0x0094 Interrupt Source Priority 5 13 4 Interrupt Register Description 13 4 1 Interrupt Vector Register Default 0x00000000 Offset 0x00 Register Name INTC_VECTOR_REG Bit Read Wr Default Description
361. s Reserved Jau 8 2013 51 PLL4OUT PLLSOUT PLL6OUT PLL7OUT Allwinner Technology CO Ltd A13 32KHZ Divider Divider Divider 00 1 00 1 00 2 01 2 01 2 01 2 OSC24M 10 3 10 4 10 4 11 4 11 8 11 8 GUCK j AXI CLK i AHB CLK i APBO CLK PLLI PLL6 6 OSC24M APB1 CLK er gt CLK_OUT CLK_IN M N AEB LCLE OUT ees M 1 32 N 1 2 4 8 32KHZ NAND CLK NAND CLK OUT OSC24M SD0 1 2 CLK SD0 1 2 CLK OUT SS CLK SS CLK OUT SPI0 1 2 CLK PLL6 gt Fe CLK_OUT CLK INMM N M 1 16 SPI0 1 2 CLK OUT PLLS N 1 2 4 8 IR CLK OUT mig gt CLK_OUT CLK_IN N je N 1 2 4 8 EE USB CLK OUT USB PLL gt gt PLL3 DE BE FE CLK DE BE FE CLK OUT PLL7 gt CLK_OUT CLK_IN M gt M 1 16 BE CLK OUT PLL5 p IEP CLK c p PLL3x1 LCD CH0 CLK ee 8 LCD CHO CLK ER gt CLK_OUT CLK_IN PLL3x2 PLL7x2 Figure 6 2 Bus Clock Generation Part 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 52 Jau 8 2013 AW Allwinner Technology CO Ltd A13 PLL3x1 PLL7x1 PLL3x2 LCD CH1 CLK2 CLK OUT CLK IN
362. s asserted if reaching RAL The IRQ is de asserted when condition fails RPEI_EN Receiver Packet End Interrupt Enable 0 Disable 1 Enable 0 R W ROL EN Receiver FIFO Overrun Interrupt Enable 0 Disable 1 Enable 20 3 5 CIR Receiver Status Register Register Name IR RXSTA Offset 0x30 Default Value 0x0000 0000 Bit Read Write Default Description 31 13 RAC RX FIFO Available Counter 0 No available data in RX FIFO 1 1 byte available data in RX FIFO 2 2 byte available data in RX FIFO 12 6 R 0 64 64 byte available data in RX FIFO 5 RA RX FIFO Available 0 RX FIFO not available according its level 1 RX FIFO available according its level 4 R W 0 This bit is cleared by writing a 1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 203 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 32 RPE Receiver Packet End Flag 0 STO was not detected In CIR mode one CIR symbol is receiving or not detected 1 STO field or packet abort symbol 7 b0000 000 and 8 b0000 0000 for MIR and FIR is detected In CIR mode one CIR symbol is received 1 R W 0 This bit is cleared by writing a 1 ROI Receiver FIFO Overrun 0 Receiver FIFO not overrun 1 Receiver FIFO overrun 0 R W 0 This bit is cleared by writing a 1 20 3 6 CIR Configure Register Regist
363. s field is valid only if the NoOverCurrentProtection field is cleared 0 Over current status is reported collectively for all downstream ports 1 Over current status is reported on per port basis 10 0x0 Device Type This bit specifies that the Root Hub is not a compound device The Root Hub is not permitted to be a compound device This field should always read write 0 R W PowerSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled It is implementation specific This field is only valid when the NoPowerSwitching field is cleared 0 All ports are powered at the same time 1 Each port is powered individually This mode allows port power to be controlled by either the global switch or per port switch If the PortPowerControlMask bit is set the port responds only to port power commands Set ClearPortPower If the port mask is cleared then the port is controlled only by the global power switch Set ClearGlobalPower R W NoPowerSwithcing These bits are used to specify whether power switching is supported or ports are always powered It is implementation specific When this bit is cleared the PowerSwitchingMode specifies global or per port switching 0 Ports are power switched 1 Ports are always powered on when the HC is powered on A13 User Manual V1 2 Copyright 2013 Allwin
364. s in BYTE 28 5 23 DEBE YUV Channel Buffer Line Width Register Offset Channel 0 0x940 Channel 1 0x944 Channel 2 0x948 Read Wri Default SC Bit Description te Hex IYUV LINEWIDTH Line width Register Name DEBE IYUVLINEWIDTH REG The width is the distance from the start of one line to the start of the next Description in bits YUV to RGB conversion algorithm formula R R Y component coefficient Y R U component coefficient U R V component coefficient V R constant G G Y component coefficient Y G U component coefficient U G V component coefficient V G constant B B Y component coefficient Y B U component coefficient U B V component coefficient V B constant 28 5 24 DEBE Y G Coefficient Register Register Name DEBE_YGCOEF_REG A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 336 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 G Y component 0x950 R U component 0x954 B V component 0x958 Bit Description t e Hex IYUV YGCOEF R W UDF the Y G coefficient the value equals to coefficient 2 28 5 25 DEBE Y G Constant Register Offset 0x95C Register Name DEBE_YGCONS_REG N Read Wri Default Bit Description e R W Hex IYUV YGCONS UDF the Y G constant the value equals to coefficient 2 28 5 26 DEBE U R Coefficient Register Offset G Y component 0x960 R U
365. s the ADC reference voltage application of the principle of single ended mode shown in Figure 28 8 H SE a gt IN REF AV AM Converter gt IN L N REF S Ps E Figure 25 8 Simplified Diagram of Single Ended Reference 25 4 3 Differential Mode When the TP Control Register 0 Bit12 ADC Mode Select is low the controller is in the measurement mode of X Y Z the internal ADC reference voltage source is the differential mode shown in Figure 28 9 The advantage of differential mode REF and REF input directly to the Y Y which can eliminate measurement error because of the switch on resistance The disadvantage is that both the ample or conversion process the driver needs to be on relative to single ended mode the power consumption increases A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 263 Jau 8 2013 Allwinner Technology CO Ltd A13 AVCC REF IN REF Converter REF WAV Figure25 9 Simplified Diagram of Differential Reference 25 4 4 Single Touch Detection The principle of operation is illustrated below For an X co ordinate measurement the X pin is internally switched to AVCC and X to GND The X plate becomes a potential divider and the voltage at the point of contact is proportional to its X co ordinate This voltage is measured on the Y which carry no current h
366. s the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If 27 0 R W 0 the port is configured as functional pin the undefined value will be read 33 4 24 PD Multi Driving Register 0 Register Name PD DRVO Offset 0x80 Default Value 0x5555 5555 Bit Read Write Default Description PD n Multi Driving Select n 0 15 2i 1 2i 00 Level 0 01 Level 1 1 0 15 R W Ox1 10 Level 2 11 Level 3 33 4 25 PD Multi Driving Register 1 Register Name PD_DRV1 Offset 0x84 Default Value 0x0055 5555 Bit Read Write Default Description 31 24 PD n Multi Driving Select n 16 27 2i 1 2i 00 Level 0 01 Level 1 G 0 11 R W Ox 10 Level 2 11 Level 3 33 4 26 PD Pull Register 0 Register Name PD_PULLO Offset 0x88 Default Value 0x0000 0000 Bit Read Write Default Description PD n Pull up down Select n 0 15 21 1 2i 00 Pull up down disable 01 Pull up 1 0 15 R W 0x0 10 Pull down 11 Reserved 33 4 27 PD Pull Register 1 Offset Ox8C Register Name PD_PULL1 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 396 Ou 7 Allwinner Technology CO Ltd A13 Default Value 0x0000 0000 Bit Read Write Default Description 31 24 P
367. s this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one Software should not write a one to this bit when the asynchronous schedule is disabled Doing so will yield undefined results R W Asynchronous Schedule Enable This bit controls whether the host controller skips processing the Asynchronous Schedule Values mean Bit Value Meaning 0 Do not process the Asynchronous Schedule A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 213 Jau 8 2013 7 Allwinner Technology CO Ltd A13 1 Use the ASYNLISTADDR register to access the Asynchronous Schedule The default value of this field is Ob R W Periodic Schedule Enable This bit controls whether the host controller skips processing the Periodic Schedule Values mean Bit Value Meaning 0 Do not process the Periodic Schedule 1 Use the PERIODICLISTBASE register to access the Periodic Schedule The default value of this field is Ob 3 2 R W or R Frame List Size This field is R W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one This field specifies the size of the Frame list The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index Values mean Bits Meaning 00b 1024 elements 4096bytes Default
368. select FMINR 010 left and right channel both select MIC1 gain stage output 011 left and right channel both select MIC2 gain stage output 100 left select MIC1 gain stage output amp right select MIC2 gain stage output 101 left and right both select MIC1 gain stage plus MIC2 gain stage output 110 left select output mixer L amp right select output Mixer right 111 left select LINEINL or LINEINL LINEINR depending on LNRDF bit 16 right select MIC1 gain stage 16 R W 0x0 LNRDF Line in r function define 0 Line in right channel which is independent of line in left channel 1 negative input of line in left channel for fully differential application 15 13 R W 0x4 LNPREG Line in pre amplifier Gain Control From 12dB to 9dB 3dB step default is 0dB 12 R W 0x0 MICINEN Micloutn enable 0 disable 1 enable 11 9 Ox1 DITHER ADC dither on off control A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 251 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 dither off 1 dither on 7 6 R W Ox1 PA_EN PA Enable 0 disable 1 enable 4 R W 0x0 DDE Headphone direct drive enable DDE 0 disable 1 enable 3 R W Ox1 COMPTEN HPCOM output protection enable 2 R W Ox1 0 protection disable 1 protection enable PTDBS HPCOM protect de bounce time setting 00 2 3ms
369. ss 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock is PLL4 25 24 30 20 19 16 15 1 VE_RST 0 R W 0x0 VE Reset 0 reset valid 1 reset invalid 6 4 37 Audio Codec Clock Default 0x00000000 Offset 0x140 Register Name AUDIO CODEC SCLK CFG REG Bit ou PERL Description ite Hex SCLK_GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock PLL2 output 30 0 6 4 38 AVS Clock Default 0x00000000 Offset 0x144 Register Name AVS_SCLK_CFG_REG Read Wr Default 2 Bit Description ite Hex SCLK_GATING Gating Special Clock 31 R W 0x0 0 Clock is OFF 1 Clock is ON This special clock OSC24M 30 0 6 4 39 Mali 400 Clock Register Default 0x00000000 Offset 0x154 Register Name MALI CLOCK CFG REG Read Wr Default sch Bit Description ite Hex SCLK_GATING 31 R W 0x0 Gating Special Clock Max Clock 381MHz 0 Clock is OFF A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 78 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 Clock is ON This special clock Clock Source Divider M MALI400 RST 30 R W 0x0 Mali400 Reset 0 reset valid 1 reset invalid 29 27 CLK_SRC_SEL Clock Source Select 000 PLL3 1X 26 24 R W 0x0 001 PLL4 010 PLL5 011 PLL7 1X 100 PLL7 2X 23 18
370. ssert INT line and INT_FLAG to indicate a completion for the START condition and each consequent byte transfer At each interrupt the micro processor needs to check the 2WIRE_STAT register for current status A transfer has to be concluded with STOP condition by setting M_STP bit high In Slave Mode the TWI also constantly samples the bus and look for its own slave address during addressing cycles Once a match is found it is addressed and interrupts the CPU host with the corresponding status Upon A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 169 Jau 8 2013 Allwinner Technology CO Ltd A13 request the CPU host should read the status read write 2WIRE DATA data register and set the 2WIRE CNTR control register After each byte transfer a slave device always halt the operation of remote master by holding the next low pulse on SCL line until the microprocessor responds to the status of previous byte transfer or START condition A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 170 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 18 Serial Periphral Interface 18 1 Overview The Serial Peripheral Interface SPI allows rapid data communication with less software interrupts The SPI module contains one 8x64 receiver buffer RXFIFO and one 8x64 transmit buffer TXFIFO It can work in two modes Master mode and Slave mode It features
371. ssoccceeeesssosocceesesssscocccessesssccceceesssssecceese 276 26 1 OVERVIEW a aa a a a a eter a conne aE 276 26 2 CST BlOCK DIET EE 276 26 3 CST Register List se iinne eieren r eran E E Ee E E EESE ESE ESE 276 26 4 CSI Register Description ne erence iina tieden i kaadin iani Kasdiena Eaten 277 26 4 1 ETEN 277 26 4 2 CSI Configuration e E 277 26 4 3 CSI Capture Control e EE 279 26 4 4 CSI FIFOO0 Buffer A FSU man a cs aba cake en ne 2 ne 279 26 4 5 CSI PIF OO Buffer B EE uanisesnmmtnitnstmeoieidamnianinndeetendeddeddanddnsdde 279 26 4 6 CSI FIFO1 Buffer eege 280 26 4 7 CSI FIFO1 Buffer B RSOIStSrss ste Late setae 280 26 4 8 CSI Buffer Control E EG 280 26 4 9 SEE EU RQ ENE 281 26 4 10 CSI Interrupt Enable Beete 281 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 14 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 26 4 11 CSI Interrupt Status Register E 282 26 4 12 CSI Window Width Control F GISISE ee 283 26 4 13 CSI Window Height Control RSS MSN NE 283 26 4 14 CSI Buffer Length Register ss cn 283 265 LER GT 284 26 5 1 Header Data Bit Definit OM sssri e eaa aeaa aaah 284 26 5 2 CCIRG56 Header Decode sisi 284 26 6 CST Timing Did Sra sniene cost essies cd enateuses sien deeg gege caches sieedd sandendbanstendes 284 27 Display Engine Front End DEFE eeeseeeveeeveenneenneenneenneenneenneennennnesnneenneenneennesnnennnesnnesnneennesnneenneenneenneeen 286 E DE ee TE
372. ster Name INTC_EN_REG2 Read Wr Default o Bit Description ite Hex INT_SRC_EN2 Interrupt Source 95 64 Enable Bits 31 0 R W 0x0 SE 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 13 4 17 Interrupt Mask Register 0 Default 0x00000000 Offset 0x50 Register Name INTC MASK REGO Read Wr ite Bit Default Hex Description 0x0 INT_MASKO Interrupt Source 31 0 Mask Bits 0 No effect 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 13 4 18 Interrupt Mask Register 1 Default 0x00000000 Offset 0x54 Register Name INTC_MASK_REG1 8 Read Wr Default DN Bit Description ite Hex INT_MASKI1 31 0 R W 0x0 Interrupt Source 63 32 Mask Bits 0 No effect A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 117 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 13 4 19 Interrupt Mask Register 2 Default 0x00000000 Offset 0x58 Register Name INTC_MASK_REG2 Read Wr Default L Bit Description ite Hex INT MASK2 Interrupt Source 95 64 Mask B
373. sters are latched 0 R W 0x0 CONT64_CLR_EN A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 102 Jau 8 2013 7 Allwinner Technology CO Ltd A13 64 bit Counter Clear Enable 0 no effect 1 to clear the 64 bit Counter Low Hi registers and it will change to zero after the registers are cleared 11 3 29 CPU Config Register Default 0x00000000 Offset 0x13C Register Name CPU_CFG_REG Read Wr Default aan Bit Description ite Hex 31 2 L1_INVALID_RST_EN Enable L1 data cache invalidation at reset 1 R W 0x0 For L1 data cache the cycles are up to 512 CPU clock cycles 0 enable 1 disable L2_INVALID_RST_EN Enable L2 data cache invalidation at reset 0 R W 0x0 For L1 data cache the cycles are up to 1024 CPU clock cycles 0 enable 1 disable Note the bit 1 0 can be set to 0 by software A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 103 Jau 8 2013 GW Allwinner Technology CO Ltd A13 12 Synchronic Timer 12 1 Overview The chip implements 2 sync timers for high speed counter 12 2 Sync Timer Register List Module Name Base Address Sync Timer 0x01C60000 Register Name Offset Description SYNC TMR IRQ EN REG 0x0000 Timer IRQ Enable SYNC TMR IRQ STAS REG 0x0004 Timer Status SYNC TMRO CTRL REG 0x0010 Timer 0
374. suspended write SetPortSuspend The HCD sets the PortSuspendStatus bit by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortSuspendStatus instead it sets ConnectStatusChange This informs the driver that it attempted to suspend a disconnected port R W R W 0x0 read PortEnableStatus This bit indicates whether the port is enabled or disabled The Root Hub may clear this bit when an overcurrent condition disconnect event switched off power or operational bus error such as babble is detected This change also causes PortEnabledStatusChange to be set HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable This bit cannot be set when CurrentConnectStatus is cleared This bit is also set if not already at the completion of a port reset when ResetStatusChange is set or port suspend when A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 240 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 SuspendStatusChange is set 0 port is disabled 1 port is enabled write SetPortEnable The HCD sets PortEnableStatus by writing a 1 Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortEnableStatus and sets ConnectStatusChange instead This informs the driver that it attempts to enable a disco
375. t 0X00D4 B V component 0X00D8 Read Wri Default ae Bit Description te Hex 31 13 CSC_UR_COFF the U R coefficient the value equals to coefficient 2 Register Name IMGEHC_CSCURCOFF_REG 30 2 19 CSC U R Constant Register Offset OXOODC Register Name IMGEHC_CSCURCON_REG Read Wri Default D Bit Description te Hex A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 370 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 the U R constant the value equals to coefficient 2 30 2 20 CSC V B Coefficient Register Offset G Y component 0X00E0 R U component OXO0E4 B V component 0X00E8 Read Wri Default a Bit Description te Hex Register Name IMGEHC_CSCVBCOFF_REG CSC_VB_COFF the V B coefficient the value equals to coefficient 2 30 2 21 CSC V B Constant Register Offset OXOOEC Register Name IMGEHC_CSCVBCON_REG Read Wri Default SS Bit Description te Hex CSC_VB_CON 13 00 R W Ox2eb1 the V B constant the value equals to coefficient 2 30 2 22 DRC Spatial Coefficient Offset OXOOFO OXOOF8 Register Name IMGEHC_DRCSPACOFF Read Wri Default o Bit Description te Hex sap p E as mw Ir ET spanat cote daa 1508 mw 0 Sits unsigned spatial coecen daa 00 Rw 0 bis unsigned spatial coefficient data 30 2 23 DRC Intensity Coefficient Offset 0X0100 OXO1FC Register Name IMGEHC_DRCINTCOFF Read Wri Default
376. t 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 SLA Slave address 7 bit addressing SLA6 SLA5 SLA4 SLA3 SLA2 SLAI SLAO T 1 R W 0 10 bit addressing A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 163 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 1 1 1 1 0 SLAX 9 8 GCE General call address enable 0 Disable 0 R W 0 1 Enable Note For 7 bit addressing SLA6 SLAO is the 7 bit address of TWI in slave mode When TWI receives this address after a START condition it will generate an interrupt and enter slave mode SLA6 corresponds to the first bit received from the two wire bus If GCE is set to 1 the TWI will also recognize the general call address 00h For 10 bit addressing When the address received starts with 11110b the TWI recognizes this as the first part of a 10 bit address and if the next two bits match ADDR 2 1 i e SLAX9 and SLAX8 of the device s extended address it sends an ACK The device does not generate an interrupt at this point If the next byte of the address matches the XADDR register SLAX7 SLAXO the TWI generates an interrupt and goes into slave mode 17 42 TWI Extend Address Register Register Name TWI_XADDR Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 SLAX Extend Slave Address 7 0 R W 0
377. t 0x208 Register Name DEFE_CH1_HORZFACT_REG Bit ee Pen Description ite Hex 31 24 FACTOR_INT 23 16 R W 0x0 The integer part of the horizontal scaling ratio the horizontal scaling ratio input width output width FACTOR_FRAC 15 0 R W 0x0 The fractional part of the horizontal scaling ratio the horizontal scaling ratio input width output width 27 5 46 DEFE_CH1_VERTFACT_REG Offset 0x20C Register Name DEFE_CH1_VERTFACT_REG Read Wr Default Bit Description ite Hex 31 24 FACTOR_INT 23 16 R W 0x0 The integer part of the vertical scaling ratio the vertical scaling ratio input height output height FACTOR_FRAC 15 0 R W 0x0 The fractional part of the vertical scaling ratio the vertical scaling ratio input height output height A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 311 Ou 7 Allwinner Technology CO Ltd A13 27 5 47 DEFE CH1 HORZPHASE REG Offset 0x210 Register Name DEFE CH1 HORZPHASE REG Bit Mr Po Description ite Hex 31 20 PHASE 19 0 R W 0x0 U R component initial phase in horizontal complement This value equals to initial phase a 27 5 48 DEFE_CH1_VERTPHASE0_REG Offset 0x214 Register Name DEFE_CH1_VERTPHASEO_REG Bit D re Description ite Hex 31 20 PHASE 19 0 R W 0x0 U R component initial phase in vert
378. t Enable 0 Disable 1 Enable 21 R W 0x0 DDMA2 END IRQ EN Dedicated DMA 2 End Transfer Interrupt Enable 0 Disable 1 Enable 20 R W 0x0 DDMA2_HF_IRQ EN Dedicated DMA 2 Half Transfer Interrupt Enable 0 Disable 1 Enable 19 R W 0x0 DDMA1 END IRQ EN Dedicated DMA 1 End Transfer Interrupt Enable 0 Disable 1 Enable 18 R W 0x0 DDMA1_HF_IRQ EN Dedicated DMA 1 Half Transfer Interrupt Enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 138 Ou 7 Allwinner Technology CO Ltd 0 Disable 1 Enable A13 DDMAO END IRQ EN 17 R W 0x0 Dedicated DMA 0 End Transfer Interrupt Enable 0 Disable 1 Enable DDMA0_HF_IRQ_EN 16 R W 0x0 Dedicated DMA 0 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA7_END_IRQ_EN 15 R W 0x0 Normal DMA 7 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA7_HF_IRQ_EN 14 R W 0x0 Normal DMA 7 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA6_END_IRQ_EN 13 R W 0x0 Normal DMA 6 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA6_HF_IRQ_EN 12 R W 0x0 Normal DMA 6 Half Transfer Interrupt Enable 0 Disable 1 Enable NDMA5 END IRQ EN 11 R W 0x0 Normal DMA 5 End Transfer Interrupt Enable 0 Disable 1 Enable NDMA5_HF_IRQ_EN 10 R W 0x0 Normal DMA 5 Half Transfer Interrupt E
379. t Value Register ss 95 11 3 12 ASYNC Timer 3 Control Register Default OxvOO00OO000 95 11 3 13 ASYNG Timer 3 Interval Valens con a 95 11 3 14 ASYNC Timer 4 Control Register Default OxvOOOO0OO04 96 11 3 15 ASYNC Timer 4 Interval Value Register ccesseeseesseseeeeeseeeseeeeaeeeseesseeteaeeeaeeees 97 11 3 16 ASYNC Timer 4 Current Value Register rrrrnrnnnrnvnnnrvnnnnnnnvnnnrnnnrnnnnvnnnrnnnrnnrnnnnnreenn 97 11 3 17 ASYNC Timer 5 Control Register Default OxvOOOO0OO04 97 11 3 18 ASYNC Timer 5 Interval Value Register 98 11 3 19 ASYNC Timer 5 Current Value Register eccesceessesscesseeeeseeseeeseaeeeeesseeseaeeeeeens 99 11 3 20 AVS Counter Control Register Default 0x00000000 rrrnrrrrrrvrrrnrnnrrnrnrrrnrrrrnnnernn 99 11 3 21 AVS Counter 0 Register Default Ox00000000 ssssssnsssressrrsrrrsrrrnrrrnerrnnrrnnrerene 100 11 3 22 AVS Counter 1 Register Default Ox00000000 sssssssnessressrnssrnnrrrnrresrrnsrensrreee 100 11 3 23 AVS Counter Divisor Register Default OxvOPDDBORIDD 100 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 7 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 11 3 24 Watchdog Control e 101 11 3 25 Watchdog Mode Register Default Ox00000000 101 11 3 26 64 bit Counter Low Register Default 0x00000000 rrrrrnr
380. t is set when the RXFIFO is 3 4 full Writing 1 to this bit clears it 0 Not 3 4 Full 1 3 4 Full R W RXFIFO 1 4 Full This bit is set when the RXFIFO is 1 4 full Writing 1 to this bit clears it 0 Not 1 4 Full 1 1 4 Full R W RF RXFIFO Full This bit is set when the RXFIFO is full Writing 1 to this bit clears it 0 Not Full 1 Full R W RHF RXFIFO Half Full This bit is set if the RXFIFO is half full gt 4 words in RXFIFO Writing 1 to this bit clears it 0 Less than 4 words are stored in RXFIFO 1 Four or more words are available in RXFIFO R W RR RXFIFO Ready This bit is set any time there is one or more words stored in RXFIFO gt 1 words Writing I to this bit clears it 0 No valid data in RXFIFO 1 More than 1 word in RXFIFO 18 4 6 SPI DMA Control Register Register Name SPI DMACTL Offset 0x14 Default Value 0x0000 0000 Bit Read Write Default Description 31 13 TXFIFO3 4 Empty DMA Request Enable 0 Disable 12 R W 0 1 Enable TXFIFO 1 4 Empty DMA Request Enable 0 Disable 11 R W 0 1 Enable TXFIFO Not Full DMA Request Enable When enabled if more than one free room for burst DMA request is asserted otherwise it s de asserted 0 Disable 10 R W 0 1 Enable TXFIFO Half Empty DMA Request Enable 9 R W 0 0 Disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 179 Jau 8 20
381. t top x coordinate of display window in pixels 30 2 7 DRC Window Position Register Offset 0X0020 Register Name IMGEHC_DRC_ WP REGI Read Wri Default a Bit Description te Hex e few fo EE A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 366 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 DRC WIN RIGHT Window Right position Right position is the right bottom x coordinate of display window in pixels 30 2 8 DRC Write Back Control Register Offset 0X0024 Register Name IMGEHC_WBCTL_REGO Read Wri Default E Bit Description te Hex WB_STATUS Write back process status 0 write back end or write back disable 1 write back in process WB_FIELD Write back field setting for de flicker 0 top field 1 bottom field Write back only control 0 disable the write back only control the data will transfer to LCD controller too 1 enable the write back only control the data won t transfer to LCD controller Write back enable 0 disable 1 enable The bit will be cleared when write back ends 30 2 9 DRC Write Back Address Register Offset 0X0028 Register Name IMGEHC_WBADD_REG A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 367 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 30 2 10 DRC Write Back Buffer Line Width Pee a Offset 0X002c Register Name IMGEHC WBLINEWIDTH REG ss s s sidY N
382. tal quantizing Tap3 Line n3 O O Vertical quantizing The relation between each output pixel location the input pixel grid is X location of output pixel XO of input line output pixel number X Scale Factor Y location of output pixel YO of input window output line number Y scale factor The X and Y locations may not be integer values which depend on the scale factor The resulting X and Y pixel locations can be separated into an integer and a fractional part The integer part of the X and Y location A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 287 Jau 8 2013 Allwinner Technology CO Ltd A13 selects the pixel and line number closest to the output pixel respectively The fractional part gives the fractional distance of the output pixel to the next X and Y input pixel values These fractional parts are the and D values shown in scaling algorithm diagram To perform scaling the X and Y locations of the output pixel relating to the input pixel grid must be generated This includes both the integer part to locate the adjacent pixels and the fractional part to choose the filter coefficients which generate the output value from the adjacent pixels This could be done by generating the output pixel X and Y numbers and dividing each by its associated scale factor A line may start and or end at the edge of the input image In this case you should use mirroring data shown in follow fi
383. td A13 TP Mode Select 00 FIFO store X Y data with Z filter 01 FIFO store X Y AX AY data with Z filter 10 FIFO store X Y X2 Y2 data with Z filter 11 Debug Mode FIFO store X1 Y1 X2 Y2 Z1 Z2 data 25 24 R W 0x0 PRE_MEA_EN TP Pressure Measurement Enable Control 0 Disable 1 Enable 23 0 R W OxFFF PRE_MEA_THRE_CNT TP Pressure Measurement threshold Control Notes 0x000000 least sensitive OxFFFFFF most sensitive Note used to adjust sensitivity of touch 25 6 4 Median Filter Control Register Offset OxOc Register Name TP_CTRL3 Bit Read Wr ite Default Hex Description R W 0x0 FILTER_EN Filter Enable 0 Disable 1 Enable 1 0 R W 0x1 FILTER_TYPE Filter Type 00 4 2 01 5 3 10 8 4 11 16 8 25 6 5 TP Interrupt amp FIFO Control Register Offset 0x10 Register Name TP_INT Bit Read Wr Default Description ite Hex 0x0000_0F00 31 19 18 R W 0x0 17 R W 0x0 TP OVERRUN IRQ EN TP FIFO Over Run IRQ Enable A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 271 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 Disable 1 Enable 16 R W 0x0 TP_DATA_IRQ_EN TP FIFO Data Available IRQ Enable 0 Disable 1 Enable 15 14 13 R W 0x0 TP_DATA_XY_CHANGE TP FIFO X Y Data interchang
384. te If the layer is selected by video channel or YUV channel the setting of this register will be ignored 28 5 9 DE Register Buffer Control Register Offset 0x870 Register Name DEBE REGBUFFCTL REG Description REGAUTOLOAD DIS Module registers loading auto mode disable control 0 registers auto loading mode 1 disable registers auto loading mode the registers will be loaded by writing 1 to bitO of this register REGLOADCTL Register load control When the Module registers loading auto mode disable control bit is set the registers will be loaded by writing 1 to the bit and the bit will be self cleared after the registers is loaded 28 5 10 DE Color Fr MAX Register Offset 0x880 0x880 Register Name DEBE_CKMAX_REG CKMAX_R Red Red color key max CKMAX_G Green Green color key max CKMAX_B Blue Blue color key max A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 324 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 28 5 11 DE Color Key MIN Register Offset 0x884 Register Name DEBE CKMIN REG Read Wri Default Description R R W Red Red color key min CKMIN G Green Green color key min CKMIN B Blue Blue color key min 28 5 12 DE Color Key Configuration Register Offset 0x888 Register Name DEBE CKCFG REG Default Description Hex CKR MATCH Red Match Rule 00 always match O1 always match 10 match if Color Min lt Colo
385. ter active video line 1 delay 2 line CCIR NTSC 2 delay 3 line CCIR PAL 3 reserved 19 0 29 3 14 TCONO CPU IF REG Offset 0x060 Register Name TCONO cpu panel interface register Bit Read Wr ite Default Hex Description 31 29 R W CPU_MOD 000 18bit 256K mode 001 16bit mode 010 16bit model 011 16bit mode2 100 16bit mode3 101 9bit mode 110 8bit 256K mode 111 8bit 65K mode 28 R W AUTO auto Transfer Mode If it s 1 all valid data during this frame is written to panel Note This bit is sampled by Vsync 27 R W FLUSH direct transfer mode If it s enabled FIFO1 is irrelevant to the HV timing and pixels data keeps being transferred unless the input FIFO is empty Data output rate control by DCLK 26 R W DA pin Al value in 8080 mode auto flash states 25 R W CA pin Al value in 8080 mode WR RD execute 24 R W VSYNC_Cs_Sel A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 356 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0 CS 1 VSYNC Wr_Flag 23 R 0 O write operation ends l write operation is pending Rd_Flag 22 R 0 O read operation ends l read operation is pending 21 0 29 3 15 _TCON0_CPU_W
386. ter graphics The value of alpha in the color code ranges from 0 0 to 1 0 where 0 0 represents a fully transparent color and 1 0 represents a fully opaque color In the display engine If setting the alpha register value ARV OB xxxxxxxx 8 bit value Then the alpha value AV ARV 256 Layer A Layer B Screen Back Ground Color Overlapping Area In the above diagram layer A and layer B are not in same channel The alpha value of layer A AV_a The alpha value of layer A AV_b The RGB value of layer A R_a G_a B_a Allwinner Technology CO Ltd A13 The RGB value of layer B R_b G_b B b The RGB value of Background color R_bg G_bg B_bg In the only layer A area R R_a AV_a R_bg 1 AV_a G Ga AV a G_bg 1 AV_a B B_a AV_a B_bg 1 AV_a In the only layer B area R R_b AV_b R bg 1 AV b G G b AV b G bg 1 AV bi B B b AV b B bg 1 AV bi In the overlapping area If the priority of layer A is higher than layer B R R_a AV_a Rb AV b R bg 1 AV_b 1 AV ai G G_a AV_a G b AV b G bg 1 AV_b 1 AV ai B B_a AV_a Bb AV b B bg 1 AV b 1 AV ai If the priority of layer A is lower than layer B R R_a AV a R bg 1 AV_a 1 AV b R b AV b G G a AV a G bg 1 AV_a 1 AV b G_b AV_b B B_a AV a B bg 1 AV a 1 AV b B b AV b 28 3 2 Color Key Matching Condition Input Color ca Output Color Ke Color Key Matching MUX l Co
387. terval Value Note The value setting should consider the system clock and the timer clock source A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 91 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 11 3 5 ASYNC Timer 0 Current Value Register Offset 0x18 Register Name ASYNC_TMRO_CURNT_VALUE_REG Read Wr Default Bit Description ite Hex TMRO_CUR_VALUE 31 0 R W 0x0 Timer 0 Current Value Note Timer 0 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerCIkSource pre scale 11 3 6 ASYNC Timer 1 Control Register Default 0x00000004 Offset 0x20 Register Name ASYNC TMR1 CTRL REG Bit Read Wr ite Default Hex Description 31 8 R W 0x0 TMR1_MODE Timer mode 0 Continuous mode When reaches the internal value the timer will not be disabled automatically 1 Single mode When reaches the internal value the timer will be disabled automatically 6 4 R W 0x0 TMR1_CLK_PRES Select the pre scale of timer 1 clock source 000 1 001 2 010 4 O11 8 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMR1_CLK_SRC Timer 1 Clock Source 00 01 OSC24M 10 PLL6 6 11 R W 0x0 TMR1_RELOAD Timer 1 Reload 0 No ef
388. than one room for new sample in TX FIFO gt 1 word TXE CNT 22 8 R 0x80 TX FIFO Empty Space Word Counter 7 4 TXE_INT TX FIFO Empty Pending Interrupt 3 R W Ox1 0 No Pending IRQ 1 FIFO Empty Pending Interrupt Write 1 to clear this interrupt or automatic clear if interrupt condition A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 245 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 fails R W 0x0 TXU_INT TX FIFO Under run Pending Interrupt 0 No Pending Interrupt 1 FIFO Under run Pending Interrupt Write 1 to clear this interrupt R W 0x0 TXO_INT TX FIFO Overrun Pending Interrupt 0 No Pending Interrupt 1 FIFO Overrun Pending Interrupt Write 1 to clear this interrupt 23 4 4 DAC TX DATA Register Offset OxC Register Name AC_DAC_TXDATA Bit Read Write Default Description 31 0 W 0x0 TX_DATA Transmitting left right channel sample data should be written this register one by one The left channel sample data is first and then the right channel sample 23 4 5 DAC Analog Control Register Offset 0x10 Register Name AC_DAC_ACTRL Bit R W Default Description 31 0x0 DACAREN Internal DAC Analog Right channel Enable 0 Disable 1 Enable 30 0x0 DACALEN Internal DAC Analog Left chann
389. the TWI is being accessed in slave mode the TWI will complete the data transfer in slave mode then enter master mode when the bus has been released The M_STA bit is cleared automatically after a START condition is sent writing a 0 to this bit has no effect R W M_STP Master Mode Stop If M_STP is set to 1 in master mode a STOP condition is transmitted on the two wire bus If the M_STP bit is set to 1 in slave mode the TWI will behave as if a STOP condition has been received but no STOP condition will be transmitted on the two wire bus If both M_STA and M_STP bits are set the TWI will first transmit the STOP condition if in master mode and then transmit the START condition The M_STP bit is cleared automatically writing a 0 to this bit has no effect R W INT_FLAG Interrupt Flag INT FLAG is automatically set to 1 when any of 28 out of the possible 29 states is entered see STAT Register below The only state that does not set INT_FLAG is state F8h If the INT_EN bit is set the interrupt line goes high when IFLG is set to 1 If the TWI is operating in slave mode data transfer is suspended when INT_FLAG is set and the low period of the two wire bus clock line SCL is stretched until 0 is written to INT_FLAG The 2 wire clock line is then released and the interrupt line goes low R W A_ACK Assert Acknowledge A13 User Manual V1 2 Cop
390. the received data In the FIFO mode since the framing error is associated with a character received it is revealed when the character with the framing error is at the top of the FIFO When a framing error occurs the UART tries to resynchronize It does this by assuming that the error occurs due to the start bit of the next character and then continues receiving the other bit i e data and or parity and stop It should be noted that the Framing Error FE bit LSR 3 is set if a break interrupt has occurred as indicated by Break Interrupt BI bit LSR 4 0 no framing error 1 framing error 3 R Reading the LSR clears the FE bit PE Parity Error This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable PEN bit LCR 3 is set In the FIFO mode since the parity error is associated with a character received it is revealed when the character with the parity error arrives at the top of the FIFO It should be noted that the Parity Error PE bit LSR 2 is set if a break interrupt has occurred as indicated by Break Interrupt BD bit LSR 4 0 no parity error 1 parity error 2 R Reading the LSR clears the PE bit OE Overrun Error This occurs if a new data character is received before the previous data is read In the non FIFO mode the OE bit is set when a new character arrives in the receiver before the previous character is read from the RBR When this happens the data in the
391. this bit is 1 the byte sequence is ARGB 7 5 0x0 SCAN_MOD Output interlace enable 0 disable 1 enable When output interlace enable scaler selects YUV initial phase according to LCD field signal 2 0 R W 0x0 DATA_FMT Data format 000 planar RGB888 conversion data format 001 interleaved BGRA8888 conversion data format A component always be pad Oxff 010 interleaved ARGB8888 conversion data format A component always be pad Oxff 100 planar YUV 444 101 planar YUV 420 only support YUV input and not interleaved mode 110 planar YUV 422 only support YUV input 111 planar YUV 411 only support YUV input Other reserved 27 5 19 DEFE_INT_EN_REG Offset 0x60 Register Name DEFE_INT_EN_REG Read Wr Default Bit Description ite Hex 31 11 REG_LOAD_EN 10 R W 0x0 Register ready load interrupt enable LINE_EN 9 R W 0x0 anf Line interrupt enable 8 WB_EN Write back end interrupt enable H R W 0x0 0 Disable 1 Enable 6 0 A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 303 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 27 5 20 DEFE INT STATUS REG Offset 0x64 Register Name DEFE INT STATUS REG Read Wr Default Bit Description ite Hex 31 11 REG_LOA
392. ting 1 to the bit will clear it and its corresponding interrupt if the interrupt is enabled 24 3 4 LRADC Data 0 Register Offset Ox0c Register Name LRADC_DATA Bit Read Wr Default Description ite Hex 31 6 5 0 R 0x0 LRADCO DATA LRADC 0 Data 24 3 5 LRADC Data 1 Register Offset 0x10 Register Name LRADC_DATA Bit Read Wr Default Description ite Hex 31 6 5 0 R 0x0 LRADC1 DATA LRADC 1 Data A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 259 Jau 8 2013 Allwinner Technology CO Ltd A13 25 Touch Panel Controller TPC 25 1 Overview The controller is a 4 wire resistive touch screen controller includes 12 bit resolution A D converter Especially it provides the ability of dual touch detection The controller through the implementation of the two A D conversion has been identified by the location of the screen of single touch in addition to measurable increase in pressure on the touch screen It features 12 bit SAR type A D converter 4 wire I F Dual touch detect Touch pressure measurement Support program set threshold Sampling frequency 2MHz max Single ended conversion of touch screen inputs and ratiometric conversion of touch screen inputs TACQ up to 262ms Median and averaging filter to reduce noise Pen down detection with programmable sensitivity Support X Y change function 25 2 Typical Application Circuit
393. ting a 1 sets DeviceRemoveWakeupEnable Writing a 0 has no 15 R W R 0x0 effect 14 2 Reserved OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented When set an overcurrent condition exists When cleared all power operations are normal 1 R R W 0x0 If per port overcurrent protection is implemented this bit is always 0 Read LocalPowerStatus When read this bit returns the LocalPowerStatus of the Root Hub The Root Hub does not support the local power status feature thus this bit is always read as 0 Write ClearGlobalPower When write this bit is operated as the ClearGlobalPower In global power mode PowerSwitchingMode 0 This bit is written to 1 to turn off power to all ports clear PortPowerStatus In per port power mode it clears PortPowerStatus only on ports whose PortPowerControlMask bit 0 R W R 0x0 is not set Writing a 0 has no effect 22 6 22 HcRhPortStatus Register Offset 0x454 Register Name HcRhPortStatus Default Value 0x100 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 237 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 Read Write Bit HCD HC Default Description 31 21 0x0 Reserved 20 R W R W 0x0 PortResetStatusChange This bit is set at the end of the 10 ms port reset signal The HCD writes a
394. tor 31 N 31 7 6 PLL6 damping factor control 1 0 PLL6_FACTOR_K 5 4 PLL6 Factor K K Factor 1 The range is from I to 4 3 2 PLL6_FACTOR_M 1 0 R W Ox1 PLL6 Factor M M Factor 1 The range is from I to 4 6 4 10 PLL7 Default 0x0010D063 Offset 0x30 Register Name PLL7_CFG_REG Read Wr Default e Bit Description ite Hex PLL7_Enable 0 Disable 1 Enable 31 R W 0x0 In the integer mode The PLL7 output 3MHz M In the fractional mode the PLL7 output is select by bit 14 The PLL7 output range is 27MHz 381MHz 30 16 PLL7_MODE_SEL 15 R W Ox1 PLL7 mode select 0 fractional mode 1 integer mode PLL7 FRAC SET 14 R W 0x1 PLL7 fractional setting 0 270MHz 1 297MHz 13 7 PLL7_FACTOR_M 6 0 R W 0x63 PLL7 Factor M The range is from 9 to 127 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 61 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd 6 4 11 PLL1 Tuning2 Default 0x00000000 A13 Offset 0x38 Register Name PLL1 TUN2 REG Read Wr Default i Bit Description ite Hex SIG_DELT_PAT_EN Sigma delta pattern enable 31 R W 0x0 SPR_FREQ_MODE Spread Frequency Mode 00 DC 0 01 DC 1 10 Triangular 30 29 R W 0x0 11 awmode WAVE_STEP Wave step 28 20 R W 0x0 19 FREQ Frequency
395. trol ASYNC TMRO INTV VALUE REG 0x0014 Timer 0 Interval Value ASYNC TMRO CURNT VALUE REG 0x0018 Timer 0 Current Value ASYNC_TMR1 CTRL REG 0x0020 Timer 1 Control ASYNC TMRI1 INTV VALUE REG 0x0024 Timer 1 Interval Value ASYNC TMRI CURNT VALUE REG 0x0028 Timer 1 Current Value ASYNC TMR2 CTRL REG 0x0030 Timer 2 Control ASYNC TMR2 INTV VALUE REG 0x0034 Timer 2 Interval Value ASYNC TMR2 CURNT VALUE REG 0x0038 Timer 2 Current Value ASYNC TMR3 CTRL REG 0x0040 Timer 3 Control ASYNC TMR3 INTV VALUE REG 0x0044 Timer 3 Interval Value ASYNC TMR4 CTRL REG 0x0050 Timer 4 Control ASYNC TMR4 INTV VALUE REG 0x0054 Timer 4 Interval Value ASYNC TMR4 CURNT VALUE REG 0x0058 Timer 4 Current Value ASYNC TMR5 CTRL REG 0x0060 Timer 5 Control ASYNC TMR5 INTV VALUE REG 0x0064 Timer 5 Interval Value A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 88 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 ASYNC TMR5 CURNT VALUE REG 0x0068 Timer 5 Current Value AVS CNT CTL REG 0x0080 AVS Control Register AVS CNTO REG 0x0084 AVS Counter 0 Register AVS CNT1 REG 0x0088 AVS Counter 1 Register AVS CNT DIVISOR REG 0x008C AVS Divisor WDOG CTRL REG 0x0090 Watchdog Control WDOG MODE REG 0x0094 Watchdog Mode COUNTER64 CTRL REG 0x00A0 64 bit Counter control COUNTER64_LOW_REG 0x00A4 64 bit Counter low COUNTER64_HI_REG 0x00A8 64 bit Counter high CPU CFG REG 0x0140 CPU configuration register
396. trol Register address 5 3 12 PMU TWI Address Default 0x00000068 Offset 0x50 Register Name PMU TWI ADDR REG Read Wr Default 2 Bit Description ite Hex 31 8 PMU_TWI_ADDR 7 0 R W 0x68 PMU TWI address set 5 3 13 PMU CPUVDD Value Default 0x00000016 Offset 0x54 Register Name PMU_CPUVDD_VALUE_REG Read Wr Default sch Bit Description ite Hex 31 8 fa CPUVDD DEFAULT 7 0 R W 0x16 PMU CPUVDD Default Value 0x00 0 70v A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 38 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 0x02 0 75v 0x04 0 80v 0x06 0 85v 0x08 0 90v Ox0A 0 95v Ox0C 1 00v OxOE 1 05v 0x10 1 10v 0x12 1 15v 0x14 1 20v 0x16 1 25v 0x18 1 30v Ox1A 1 35v Ox1C 1 40v Ox1E 1 45v 0x20 1 50v 0x22 1 55v 0x24 1 60v Note This register can be modified by PMU DVFS 5 3 14 PMU CPUVDD Voltage Ramp Control in DVM Offset 0x58 Register Name PMU_CPUVDD_RAMP_CTRL_REG Read Wr Default aa Bit f Description ite Hex 31 1 l CPUVDD VOLT RAMP CTRL CPUvdd voltage ramp control in DVM 0 R W 0x0 0 15 625us 1 31 25us Note If the cpuvdd voltage ramp control in the external PMU is changed by the CPU the CPU should also modify this to be the same in the PMU 5 3 15 PMU 32KHz CPUVDD Minimum Value Default 0x0000000C Offset 0x5C R
397. ts current value register needs to be written with zero 11 3 20 AVS Counter Control Register Default 0x00000000 Offset 0x80 Register Name AVS_CNT_CTL_REG Read B Bit Default Description Write 31 10 AVS_CNT1_PS Audio Video Sync Counter 1 Pause Control 9 R 0x0 0 Not pause 1 Pause Counter 1 AVS_CNTO_PS Audio Video Sync Counter 0 Pause Control 8 R W 0x0 0 Not pause 1 Pause Counter 0 7 2 AVS_CNT1_EN Audio Video Sync Counter 1 Enable Disable The counter source is 1 R W 0x0 OSC24M 0 Disable 1 Enable AVS CNTO EN Audio Video Sync Counter 1 Enable Disable The counter source is 0 R W 0x0 OSC24M 0 Disable 1 Enable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 99 Jau 8 2013 7 Allwinner Technology CO Ltd A13 11 3 21 AVS Counter 0 Register Default 0x00000000 Offset 0x84 Register Name AVS CNTO REG Read Default Bit Description Write AVS_CNTO Counter 0 for Audio Video Sync Application The high 32 bits of the internal 33 bits 90KHz counter register The initial value of the internal 33 bits counter register can be set by software The 31 0 R W 0x0 re LSB bit of the 33 bits counter register should be zero when the initial value is updated It will count from the initial value The initial value can be updated at any time It can also be
398. u 8 2013 Ou Allwinner Technology CO Ltd A13 This resets the control portion of the receive FIFO and treats the FIFO as empty This also de asserts the DMA RX request It is self clearing It is not necessary to clear this bit FIFOE Enable FIFOs This enables disables the transmit XMIT and receive RCVR FIFOs Whenever the value of this bit is changed both the XMIT and RCVR 0 W 0 controller portion of FIFOs is reset 19 4 8 UART Line Control Register Register Name UART LCR Offset OxOC Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DLAB Divisor Latch Access Bit It is writeable only when UART is not busy USR 0 is zero and always readable This bit is used to enable reading and writing of the Divisor Latch register DLL and DLH to set the baud rate of the UART This bit must be cleared after initial baud rate setup in order to access other registers 0 Select RX Buffer Register RBR TX Holding Register THR and Interrupt Enable Register IER 1 Select Divisor Latch LS Register DLL and Divisor Latch MS 7 R W 0 Register DLM BC Break Control Bit This is used to cause a break condition to be transmitted to the receiving device If set to one the serial output is forced to the spacing logic 0 state When not in Loopback Mode as determined by MCR 4 the sout line is forced low until the Break bit is cleared If SIR MODE Enabled
399. u 8 2013 Ou 7 Allwinner Technology CO Ltd A13 SH Height scale factor 00 no scaling 01 2 10 4 11 Reserved LAY WSCAFCT Setting the internal frame buffer scaling factor only valid in internal frame buffer mode SW Width scale factor 00 no scaling 01 2 10 4 11 Reserved LAY FBFMT Frame buffer format Normal mode data format 0000 mono 1 bpp 0001 mono 2 bpp 0010 mono 4 bpp 0011 mono 8 bpp 0100 color 16 bpp R 6 G 5 B 5 0101 color 16 bpp R 5 G 6 B 5 0110 color 16 bpp R 5 G 5 B 6 0111 color 16 bpp Alpha 1 R 5 G 5 B 5 1000 color 16 bpp R 5 G 5 B 5 Alpha 1 1001 color 24 bpp Padding 8 R 8 G 8 B 8 1010 color 32 bpp Alpha 8 R 8 G 8 B 8 1011 color 24 bpp R 8 G 8 B 8 1100 color 16 bpp Alpha 4 R 4 G 4 B 4 1101 color 16 bpp R 4 G 4 B 4 Alpha 4 Other Reserved Palette Mode data format In palette mode the data of external frame buffer is regarded as pattern 0000 1 bpp 0001 2 bpp 0010 4 bpp 0011 8 bpp other Reserved A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 328 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 B R channel swap 0 RGB Follow the bit 11 8 RGB 1 BGR Swap the B R channel in the data format LAY_FBPS PS Pixels Sequence See the follow table Pixels Sequence 28 5 15 Pixels Sequence Table DE layer attribute control register 11 08 FBF frame buffer format DE layer
400. ue 0x0000 0000 Bit Read Write Default Description RX_DATA RX Sample Host can get one sample by reading this register The left channel sample 31 0 R 0x0 data is first and then the right channel sample 23 4 9 ADC Analog Control Register Offset 0x28 Register Name AC_PA_ADC_ACTRL Bit R W Default Description 31 R W 0x0 ADCREN ADC Right Channel Enable 0 Disable 1 Enable 30 R W 0x0 ADCLEN ADC Left Channel Enable 0 Disable 1 Enable 29 R W 0x0 PREGIEN MIC1 pre amplifier Enable 0 Disable 1 Enable 28 R W 0x0 PREG2EN MIC2 pre amplifier Enable 0 Disable 1 Enable 27 R W 0x0 VMICEN VMIC pin voltage enable 0 disable 1 enable PREGI MIC1 pre amplifier Gain Control 00 0dB 01 35dB 10 38dB 11 41dB 26 25 R W 0x2 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 250 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 24 23 R W 0x2 PREG2 MIC2 pre amplifier Gain Control 00 0dB 01 35dB 10 38dB 11 41dB 22 20 R W 0x3 ADCG ADC Input Gain Control 000 4 5dB 001 3dB 010 1 5dB 011 0dB 100 1 5dB 101 3dB 110 4 5dB 111 6dB 19 17 R W 0x2 ADCIS ADC input source select 000 left select LINEINL right select LINEINR or both select LINEINL LINEINR depending on LNRDF bit 16 001 left channel select FMINL amp right channel
401. ue of corresponding internal configuration register will be refreshed by this register and programmers always can t read the value of corresponding internal register A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 294 Ou 7 Allwinner Technology CO Ltd A13 27 5 27 5 1 DEFE Register Description DEFE_EN_REG Offset 0x0 Register Name DEFE_EN_REG Bit Read Wr ite Default Hex Description 31 1 R W 0x0 EN DEFE enable 0 Disable 1 Enable When DEFE enable bit is disabled the clock of DEFE module will be disabled If this bit transits from 0 to 1 the frame process control register and the interrupt enable register will be initialized to default value and the state machine of the module is reset 27 5 2 DEFE_FRM_CTRL_REG Offset 0x4 Register Name DEFE_FRM_CTRL_REG Bit Read Wr ite Default Hex Description 31 24 23 R W COEF_ACCESS_CTRL Fir coef ram access control 0 CPU doesn t access fir coef ram 1 CPU will access fir coef ram This bit will be set to 1 before CPU accesses fir coef ram 22 17 16 R W 0x0 FRM_START Frame start amp reset control 0 reset 1 start If the bit is written to zero the whole state machine and data paths of DEFE module will be reset When the bit is written to 1 D
402. ull Interrupt Enable 0 Disable 1 Enable R W RX FIFO 1 4 Full Interrupt Enable 0 Disable 1 Enable R W RX FIFO Full Interrupt Enable 0 Disable 1 Enable R W RX FIFO Half Full Interrupt Enable 0 Disable 1 Enable R W RX FIFO Ready Interrupt Enable 0 Disable 1 Enable 18 4 5 SPI Interrupt Status Register Register Name SPI INT STA Offset 0x10 Default Value 0x0000 1B00 Bit Read Write Default Description Clear interrupt busy flag 0 clearing interrupt is done 31 R 0 1 clearing interrupt is busy 30 24 23 20 19 18 SSI SS Invalid Interrupt When SSI is 1 it indicates that SS has changed from valid state to 17 R W 0 invalid state Writing 1 to this bit clears it TC Transfer Completed In master mode when SMC is 1 it indicates that all bursts specified by BC have been exchanged In other condition When set this bit indicates that all the data in TXFIFO has been loaded in the Shift register and the Shift register has shifted out all the bits Writing 1 to this bit clears it 0 Busy 16 R W 0 1 Transfer Completed 15 TU TXFIFO under run 14 R W 0 This bit is set when if the TXFIFO is underrun Writing 1 to this bit A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 177 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 clears it 0 TXFIFO is not underrun
403. ult SS Bit Description ite Hex 31 26 25 16 R W 0 HSPW A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 360 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 horizontal Sync Pulse Width in dclk Thspw HSPW 1 Tdclk Note HT gt HSPW 1 15 10 VSPW vertical Sync Pulse Width in lines 9 0 R W 0 Tvspw VSPW 1 Th Note VT 2 gt VSPW 1 29 3 27 TCONI IO POL REG Offset OxOFO Register Name TCONI IO polarity register Bit oe pee Description ite Hex 31 28 103 Inv 27 R W 0 0 not invert 1 invert 102 Inv 26 R W 0 0 not invert 1 invert IO1_Inv 25 R W 0 0 not invert 1 invert IOO_Inv 24 R W 0 0 not invert 1 invert Data_Inv TCON1 output port D 23 0 polarity control with independent bit 23 0 R W 0 control Os normal polarity 1s invert the specify output 29 3 28 TCONI IO TRI REG Offset OxOF4 Register Name TCONI IO control register Read Wr Default ne Bit Description ite Hex 31 28 103_Output_Tri_En 27 R W 1 1 disable 0 enable 102_Output_Tri_En 26 R W 1 S 1 disable A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 361 Ou 7 Allwinner Technology CO Ltd A13 0 enable 25 R W IO1 Output Tri En 1 disable 0 enable 24 R W I
404. upt One Command FIFO Support external DMA for data transfer A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 151 Jau 8 2013 GW Allwinner Technology CO Ltd A13 Two 256x32 bit RAM for Pipeline Procession Support SDR DDR and Toggle 1 0 NAND 15 2 NFC Block Diagram AHB Slave I F i i Command DMA amp INT FIFO Register FIFO Control Control File FIFO FIFO User Data RAMO RAMI ahb_clk 256x32 256x32 8x32 domain Syne 4 H H nfc_clk domain Normal Spare Batch Command Command Command ECC Control II NAND Flash Basic Operation rita vo CE 1 0 CLE ALE WE RE RB 1 0 DO 7 0 DI 7 0 Figure 15 1 NFC Block Diagram 15 3 NFC Timing Diagram Typically there are two kinds of serial access method One is the conventional method that fetches data at the rise edge of NFC_RE signal line and the other is EDO type that fetches data at the next fall edge of NFC REf signal line A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 152 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 NFC CLE A zs Dr pA NFC CE S A NFC_WE A 4 t14 w sample 0
405. urrent Frame R W 0x0 PeriodicListEnable This bit is set to enable the processing of periodic list in the next Frame If cleared by HCD processing of the periodic list does not occur after the next SOF HC must check this bit before it starts processing the list A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 225 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 1 0 R W R 0x0 ControlBulkServiceRatio This specifies the service ratio between Control and Bulk EDs Before processing any of the nonperiodic lists HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed in determining whether to continue serving another Control ED or switching to Bulk EDs The internal count will be retained when crossing the frame boundary In case of reset HCD is responsible for restoring this value CBSR No of Control EDs Over Bulk EDs Served 0 1 1 1 2 1 2 3 1 3 4 1 The default value is 0x0 22 6 3 HcCommandStatus Register Register Name HcCommandStatus Offset 0x408 Default Value 0x0 Read Write Bit HCD HC Default Description 31 18 0x0 Reserved SchedulingOverrunCount These bits are incremented on each scheduling overrun error It is initialized to 00b and wraps around at 11b This will be incremented whe
406. utput Format Register DEFE INT EN REG 0x0060 DEFE Interrupt Enable Register DEFE INT STATUS REG 0x0064 DEFE Interrupt Status Register DEFE STATUS REG 0x0068 DEFE Status Register DEFE CSC COEFO0 REG 0x0070 DEFE CSC Coefficient 00 Register A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved Jau 8 2013 293 Ou Allwinner Technology CO Ltd A13 DEFE CSC COEFOI REG 0x0074 DEFE CSC Coefficient 01 Register DEFE CSC COEFO02 REG 0x0078 DEFE CSC Coefficient 02 Register DEFE CSC COEFO03 REG 0x007C DEFE CSC Coefficient 03 Register DEFE CSC COEFIO REG 0x0080 DEFE CSC Coefficient 10 Register DEFE CSC COEFI1 REG 0x0084 DEFE CSC Coefficient 11 Register DEFE CSC COEFI2 REG 0x0088 DEFE CSC Coefficient 12 Register DEFE CSC COEFI3 REG 0x008C DEFE CSC Coefficient 13 Register DEFE CSC COEF20 REG 0x0090 DEFE CSC Coefficient 20 Register DEFE CSC COEF21 REG 0x0094 DEFE CSC Coefficient 21 Register DEFE CSC COEF22 REG 0x0098 DEFE CSC Coefficient 22 Register DEFE CSC COEF23 REG 0x009C DEFE CSC Coefficient 23 Register DEFE WB LINESTRD EN REG 0x00D0 DEFE Write Back Line Stride Enable Register DEFE_WB_ LINESTRDO REG 0x00D4 DEFE Write Back Channel 3 Line Stride Register DEFE CHO INSIZE REG 0x0100 DEFE Channel 0 Input Size Register DEFE CHO OUTSIZE REG 0x0104 DEFE Channel 0 Output Size Register DEFE CHO HORZFACT REG 0x0108 DE
407. ved 207 Jau 8 2013 Ou 7 Allwinner Technology CO Ltd A13 the Open Host Controller Interface OHCI Specification Version 1 0a 22 4 USB Host Register List Module Name Base Address USB HCIO 0x01C14000 Register Name Offset Description EHCI Capability Register E_CAPLENGTH 0x000 EHCI Capability register Length Register E_HCIVERSION 0x002 EHCI Host Interface Version Number Register E HCSPARAMS 0x004 EHCI Host Control Structural Parameter Register E HCCPARAMS 0x008 EHCI Host Control Capability Parameter Register E HCSPPORTROUTE Ox00c EHCI Companion Port Route Description EHCI Operational Register E_USBCMD 0x010 EHCI USB Command Register E_USBSTS 0x014 EHCI USB Status Register E USBINTR 0x018 EHCI USB Interrupt Enable Register E FRINDEX OxO1c EHCI USB Frame Index Register E CTRLDSSEGMENT 0x020 EHCI 4G Segment Selector Register E PERIODICLISTBASE 0x024 EHCI Frame List Base Address Register E ASYNCLISTADDR 0x028 EHCI Next Asynchronous List Address Register E CONFIGFLAG 0x050 EHCI Configured Flag Register E PORTSC 0x054 EHCI Port Status Control Register OHCI Control and Status Partition Register O_HcRevision 0x400 OHCI Revision Register O_HcControl 0x404 OHCI Control Register O_HcCommandStatus 0x408 OHCI Command Status Register O HelnterruptStatus Ox40c OHCI Interrupt Status Register O HelInterruptEnable 0x410 OHCI Interru
408. wait for 2 n 1 DMA clock to request 26 25 0x0 NDMA_DST_DATA_WIDTH Normal DMA Destination Data Width 00 8 bit 01 16 bit 10 32 bit 11 24 23 0x0 NDMA_DST_BST_LEN DMA Destination Burst Length 00 1 01 4 10 8 11 22 21 0x0 NDMA_DST_ADDR_TYPE Normal DMA Destination Address Type 0 Increment 1 No Change 20 16 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 143 Jau 8 2013 0x0 NDMA_DST_DRQ_TYPE 7 Allwinner Technology CO Ltd A13 Normal DMA Destination DRQ Type 00000 IR TX 00001 00010 00011 00100 00101 00110 00111 01000 01001 UARTI TX 01010 01011 UART3 TX 01100 01101 01110 O1111 wna na EE 10000 10001 10010 10011 Audio Codec D A 10100 10101 SRAM range 10110 SDRAM 10111 11000 SPIO TX 11001 SPIL TX 11010 SPR TX 11011 USB EP1 11100 USB EP2 11101 USB EP3 11110 USB EP4 11111 USB EP5 BC MODE SEL BC mode select 15 R W 0x0 0 normal mode the value read back equals to the value that is written 1 remain mode the value read back equals to the remain counter to be transferred 14 10 NDMA_SRC_DATA_WIDTH 10 9 R W 0x0 Normal DMA Source Data Width 00 8 bit A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 144
409. y CO Ltd A13 23 4 6 ADC FIFO Control Register Offset Ox1C Register Name AC ADC FIFOC Bit Read Write Default Description ADFS Sample Rate of ADC 000 48KHz 010 24KHz 100 12KHz 110 Reserved 001 32KHz 011 16KHz 101 8KHz 111 Reserved 31 29 R W 0x0 EN_AD ADC Digital Part Enable en_ad 0 Disable 1 Enable 28 R W 0x0 27 25 RX_FIFO_MODE RX FIFO Output Mode Mode 0 1 0 Expanding 0 at LSB of TX FIFO register 1 Expanding received sample sign bit at MSB of TX FIFO register For 24 bits received audio sample Mode 0 RXDATA 31 0 FIFO_O 23 0 8 hO Mode 1 Reserved For 16 bits received audio sample Mode 0 RXDATA 31 0 FIFO_O 23 8 16 h0 Mode 1 RXDATA 31 0 16 FIFO_O 23 FIFO_O 23 8 24 R W 0x0 23 13 RX_FIFO_TRG_LEVEL RX FIFO Trigger Level RXTL 4 0 Interrupt and DMA request trigger level for TX FIFO normal condition IRQ DRQ Generated when WLEVEL gt RXTL 4 0 Note WLEVEL represents the number of valid samples in the RX FIFO 12 8 R W OxF ADC MONO EN ADC Mono Enable 7 R W 0x0 0 Stereo 16 levels FIFO 1 mono 32 levels FIFO When set to 1 Only left channel samples are recorded RX_SAMPLE BITS Receiving Audio Sample Resolution 6 R W 0x0 A13 User Manual V1 2 Copyright 2013 Allwinner Technology All Rights Reserved 248 Jau 8 2013 Ou 7 Allwinner Technology
410. yright 2013 Allwinner Technology All Rights Reserved Jau 8 2013 401 Ou 7 Allwinner Technology CO Ltd A13 Bit Read Write Default Description 31 28 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If 27 0 R W 0 the port is configured as functional pin the undefined value will be read 33 4 42 PF Multi Driving Register 0 Register Name PF_DRVO Offset OxC8 Default Value 0x0000 0155 Bit Read Write Default Description 31 10 PF n Multi Driving Select n 0 5 2i 1 2i 00 Level 0 01 Level 1 1 0 5 R W Ox1 10 Level 2 11 Level 3 33 4 43 PF Multi Driving Register 1 Register Name PF_DRV1 Offset OxCC Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 44 PF Pull Register 0 Register Name PF_PULLO Offset OxDO Default Value 0x0000 0000 Bit Read Write Default Description 31 10 PF n Pull up down Select n 0 5 21 1 2i 00 Pull up down disable O1 Pull up 1 0 5 R W 0x0 10 Pull down 11 Reserved 33 4 45 PF Pull Register 1 Register Name PF_PULL1 Offset 0xD4 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 33 4 46
411. yright 2013 Allwinner Technology All Rights Reserved 165 Jau 8 2013 Ou Allwinner Technology CO Ltd A13 When A_ACK is set to 1 an Acknowledge low level on SDA will be sent during the acknowledge clock pulse on the two wire bus if 1 Either the whole of a matching 7 bit slave address or the first or the second byte of a matching 10 bit slave address has been received 2 The general call address has been received and the GCE bit in the ADDR register is set to 1 3 A data byte has been received in master or slave mode When A ACK is 0 a Not Acknowledge high level on SDA will be sent when a data byte is received in master or slave mode If A ACK is cleared to 0 in slave transmitter mode the byte in the DATA register is assumed to be the last byte After this byte is transmitted the TWI will enter state C8h then return to the idle state status code F8h when INT_FLAG is cleared The TWI will not respond as a slave unless A_ACK is set 1 0 17 4 5 TWI Status Register Offset 0x10 Register Name TWI_STAT Default Value 0x0000 00F8 Bit Read Write Default Description 31 8 7 0 OxF8 Status Information Byte Code Status 0x00 Bus error 0x08 START condition transmitted 0x10 Repeated START condition transmitted 0x18 Address Write bit transmitted ACK received 0x20 Address Write bit tra
412. yte transmitted in slave mode ACK not received USCH Last byte transmitted in slave mode ACK received Us DU Second Address byte Write bit transmitted ACK received OxD8 Second Address byte Write bit transmitted ACK not received OxF8 No relevant status information INT_FLAG 0 Others Reserved 17 4 6 TWI Clock Register Register Name TWI_CCR Offset 0x14 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 6 3 R W 0 CLK_M CLK_N The two wire bus is sampled by the TWI at the frequency defined by FO Fsamp F 0 Fin 2 CLK_N The TWI OSCL output frequency in master mode is F1 10 F1 FO CLK M 1 Foscl F1 10 Fin 24CLK_N CLK_M 1 10 For Example Fin 48Mhz APB clock input For 400kHz full speed 2Wire CLK_N 2 CLK_M 2 FO 48M 212 12Mhz F1 F0 10 2 1 0 4Mhz For 100Khz standard speed 2Wire CLK_N 2 CLK_M 11 2 0 R W 0 F0 48M 2 2 12Mhz F1 F0 10 11 1 0 1Mhz A13 User Manual V1 2 Copyright O 2013 Allwinner Technology All Rights Reserved 167 Jau 8 2013 GW 7 Allwinner Technology CO Ltd A13 17 4 7 TWI Soft Reset Register Register Name TWI_SRST Offset 0x18 Default Value 0x0000 0000 Bit Read Write Default Description 31 1 Soft Reset Write 1 to this bit to reset the TWI and clear to 0 when complete Soft 0 R W 0 Reset operation 17 4 8 TWI Enhance Feature Register R

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