QB-70F3534-PD QB-70F3532-PD
Contents
1. 02 2tENESAS Table of Contents tte Te e BEE 7 IR ng al HE 11 BIBOINLELIIIPMCEC Ee 11 U 12 1 1 Elte VE E 12 1 2 SYSTEM SpecifiCation 1i Lire censes stes Le suec ua sand sudapueadeces sued uis estem sans sacs soessacrsqcusaue 13 1 3 Adapters Connectors eniro de eee eerie tede eie e ne adeb ase ice ies a saetedeeeeded 14 1 4 Package Contents e noie cente sane cocns sens stacbacassces sens ss s sanc nante nasa in cna seed satvenestacesieesaene 15 2 lt S tuUp PrOCCOUNG e 16 2 4 Installation ot Software tools nire c nita coenae icai coc vengo saca nd c vacua adc sis aea e ep addu ce aa contin 16 KSC ed c 16 2 3 Connection of System occaecat rota esu ctrnr esae bUSE aman cur sous isa sa cupa E Ya nc ds ddl Samo Eege 17 2 4 Start the Software To0o 5 eiii NEESS CO uou SE ASE CE VEN Na dirada VC EEN 18 2 5 Sh t down tee H 19 3 Differences between Target Device and POD ccc eecceseseeeeeeeeseeeeeeeeeeeeeeeeneeeeeeeneeeeeseaee 20 3 1 Electrical Tu 20 3 1 1 Electrical differences on power pins eene n nenne nnnnt inen 20 SEEMS E 20 3 1 3 Electrical differences on port ins 21 3 2 Functions not emulated by real chip on the POD essere enne nnne nnne 21 3 2 1 RAM conte2. 3 MB capacity Internal RAM 256KB Internal Video RAM 8 MB None External memory None vRAM i f Program execution Real time execution function Available functions Non real time execution function Available Step execution in source level depends on debugger Event functions Detection of execution Pre execution 4 points only for break function Post execution 8 points Detection of access 6 points Pass counter 12 bits Sequential 4 steps Modification when running Available Break functions Hardware break 4 Available Software break 96 Available Other Trace full break forced break timer overflow break Trace functions Trace data types Branch source PC branch destination PC access data access address R W status time stamp DMA access data DMA access address DMA R W status DMA transfer count DMA channel number Trace events Delay trigger section qualify Memory capacity 512K frames Other Trace full stop Time measurement Measurement clock 200 MHz functions Measurement objects Beginning through end of program execution Start event through end event 6 sections Maximum measurement time Approximately 195 hours When using measurement dedicated clock divided by 32 Minimum resolution 5 ns Measurement results Execution time Start through end of execution Maximum minimum average pass count between events Other Timer overflow break function 1 point Other fu
3. 70F3534 PD The QB 70F3532 PD emulates the uPD70F3532 device For using profiling function on other devices this POD could be used refer to chapter 3 too 1 1 Hardware Specifications Table 1 2 Target specifications Parameter Specifications Target system CVDD MCVDD 1 1 to 1 3V Interface Voltage ExVDD AVDD OSCVDD SMVDD REGxVDD 2 7 to 5 5V RVDD BxVDD FVDD DVDD 3 0 or 3 6V Maximum operating frequency 160 MHz Capability of main clock oscillator 4 to 20MHz 2x Ring internal oscillator 8MHz amp 240kHz typ Sub external oscillator 32kHz typ Main external oscillator 4MHz typ Operating temperature range 0 to 40 C No condensation Storage temperature range 15 to 60 C No condensation External dimensions 55 mm x 55 mm Power Consumption Supplied by IECUBE2 part of the IECUBE2 power consumption Supply from target system approx device power consumption or less Weight Approx 40g Host Interface Control i f to IECUBE2 Figure 1 1 Description of IECUBE2 POD Preliminary User s Manual EEDT CD 0423 02 12 1 2 System Specification 2tENESAS This section shows the QB 70F3534 PD QB 70F3532 PD system specifications For the usage of the debugging function refer to the documentation of the debugger Parameter Specification Emulation memory Internal FLASH
4. is disabled The WDT macro clears WDTA counter to 0x0000 when you write RUN WDTE OxAC during break 3 2 4 2 Reset Controller RESF The RESF SFR is cleared by software reset and on initial startup as well as by a target reset 3 2 4 3 Clock Monitor CLMA The CLMA can be triggered in two different ways a The CLMA can be triggered by removing the target clock X1 This can be done by removing the clock board under the plastic lid of the emulator However it is strongly suggest not to remove the clock board for this feature We recommend using solution b instead b The CLMA can be triggered by SFR write If the CLMA is triggered i e the main clock fails during break the reset will be generated just after restarting from break The CLM will continue to operate in peripheral break mode 3 2 4 4 Peripheral macros will operate during peripheral break when retry registers are accessed The peripheral clock will run for a few cycles when peripheral break is enabled and an SFR requiring RETRY is accessed in break mode Because of this all peripheral macros will operate for these few cycles An access to a SFR can occur by the SFR window a watch window or the TCL console 3 2 4 5 iRAM content The content of the iRAM will be unchanged after a RESET Target Power off on This behavior may differ than on the target device In the target device the contents of the iRAM may change to that contents before a RESET Power off on Prelimi
5. product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics s
6. time make sure that IECUBE2 and the target system are not on Preliminary User s Manual EEDT CD 0423 02 17 RENESAS 6 Turn on IECUBE2 At this time make sure that the target system is not on When the power is turned on the System and POD LED turn on If these LEDs blink or remain off IECUBE2 might be faulty Remark When the power is turned on for the first time Plug and Play starts and sets up the USB driver Continue setup according to the wizard 7 Turn on the target system After the power is on the TARGET LED turns on If the LED remains off connectors might be connected poorly the emulation POD cable might be broken or voltage might not be correctly applied to the power supply pins of the micro controller such as VDD Figure 2 3 Turn on system o E a Tum on switch see s When the power is turned on the After the power is on the SYSTEM and POD LEDs tum on TARGET LED tums on 2 4 Start the Software Tool After the above procedure the system starts up For downloading and debugging a program by using the GHS MULTI generic debugger please make sure that you have establish a USB connection between the host and the IECUBE2 emulation environment For doing so please specify the following command string within the first line of your debugger script file rc file Example Stand alone mode without connected target connect 850eserv2 iecube e2 ip C GHS v850e df dfxxxx 800 id ffffffffffffffff
7. 44 NESAS Preliminary User s Manual QB 70F3534 PD QB 70F3532 PD IECUBE2 POD s for V850E2 Dx4 Hardware Target Devices uPD70F3522 uPD70F3532 uPD70F3523 uPD70F3535 uPD70F3524 uPD70F3536 uPD70F3525 uPD70F3537 uPD70F3526 Document No EEDT CD 0423 02 Date Published April 2010 Renesas Electronics Europe GmbH 2tENESAS To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http Awww renesas com inquiry Preliminary User s Manual EEDT CD 0423 02 2tENESAS Notice 1 10 11 12 All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information t
8. CD 0423 02 24 2tENESAS 3 3 Cautions 3 3 1 Data flash read access The data flash read access is only 32 bit GHS memview 3 3 2 Data flash read access The iRAM ECC error occurs when accessing unused areas This is same behavior as on device In case of power down iRAM content will not be deleted and ECC error will not occur may be different from device 3 3 3 Reset issued by the debugger A reset issued by the debugger e g target rst will behave the same way as power cycling the device Le the status SFRs RESF and SRESF will be cleared 3 3 4 Reset during break mode A reset applied to the target RESETZ pin will not be handled if the debugger is in break mode The reset will be lost unless it is held active until the application starts to run again 3 3 5 Flash The flash lifetime for data and code flash on the POD as it is real chip based is the same as on device The User program is downloaded to the flash memory of the device mounted on POD However it is recommended to download the application program at the beginning of a debug session in order to guarantee proper operation In case of repair of a POD the Flash contents will be cleared during repair 3 3 6 FLMDO during TRESETZ active If target TFLMDO is clamped to High level during TRESETZ the POD will not be functionable 3 3 7 AHB time out during memview The AHB time out is set to unlimited because of GFX issue ETAWRL 0x0000 If you debug th
9. CE Connector i Sockets Target Connector Sold separately for each device gt Exchange Adapter gege A GAderier Refer to POD manual for detail Target System 0 Connecting POD and IECUBE2 main Remove top cover of the POD using a screw driver for the four screws Plug the cable connector onto the POD connector CN1 Observe the direction Mount the top cover with the four screws 1 Soldering Target Connector Mount the target connector onto the target board For details about how to do so refer to the document supplied with the connector 2 Connecting ICE Connector Plug the ICE connector to the target connector For details about how to do so refer to the document supplied with the connector 3 Connecting Exchange Adapter Note the position of pin 1 positioned at the cut corner and connect the exchange adapter to the ICE connector 144QFP only or to the target connector 408BGA or 352BGA only 4 Connecting POD and target system Plug the POD to the exchange adapter Be careful not to excessively bend the cable Caution Do not put any pressure on the small devices on the POD on PCB top and bottom side They may be damaged in that case To remove the exchange adapter use the stick included within the IECUBE2 package to gradually pull up the sides of the adapter refer to IECUBE2 User s Manual 5 Connecting to the IECUBE2 the USB cable and AC adapter Connect the USB cable and power supply adapter At this
10. EFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is r
11. Table 1 1 Target devices subject of emulation ccecceceeeeeeeeeeeeeeeeeeneeeeaeeeteaeeeeeaeeseaeeeseaeeeseeeeseaeessaneesaes 12 Table 1 2 Target specifications sess nennen nnne nennen menn 12 Table 3 1 Memory interface pins on POD 23 Preliminary User s Manual EEDT CD 0423 02 11 1 General 2tENESAS Each POD is part of an in circuit emulator system for emulating the target devices shown below Hardware and software can be debugged efficiently in the development of systems in which the target device is used This manual describes basic setup procedures hardware specifications system specifications and how to set switches For the whole system both User s Manual s this and the IECUBE2 User s manual are mandatory Table 1 1 Target devices subject of emulation Device Nick Package Frequency Internal flash Internal vRAM POD name memory RAM MHz kB kB kB uPD70F3522 DJ4 QFP144 80 256 24 QB 70F3534 PD pyPD70F3523 DJ4 QFP144 80 512 48 i QB 70F3534 PD pyPD70F3524 DJ4 QFP144 120 1024 96 E QB 70F3534 PD uPD70F3525 DJ4 QFP144 120 2048 192 QB 70F3534 PD yuPD70F3526 DJ4 QFP144 120 3072 256 QB 70F3534 PD pPD70F3532 DN4 H BGA352 160 3072 128 vRAM i f QB 70F3532 PD pPD70F3535 DP4 H BGA408 160 3072 256 3072 QB 70F3534 PD pPD70F3536 DP4 H BGA408 160 3072 256 5120 QB 70F3534 PD pPD70F3537 DP4 H BGA408 160 3072 256 8192 QB
12. a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics Preliminary User s Manual EEDT CD 0423 02 2tENESAS Regional Information Some information contained in this document may vary from country to country Before using any RENESAS product in your application please contact the RENESAS office in your country to obtain a list of authorized representatives and distributors They will verify H Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications forthird party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country Renesas E
13. e below sequence and have a memory window memview GHS with eDRAM contents open the debugger will loose connection as soon as you set the memory controller into idle state Preliminary User s Manual EEDT CD 0423 02 25 2tENESAS do PROTCMDS 0x000000A5 write A5 fixed value to protection command register GSSDICTRL 0x00000001 write desired value to destination GSSDICTRL OxFFFFFFFE write bit wise inversion to destination make sure to close the debugger memory window here GSSDICTRL 0x00000001 write desired value to destination while _PROTS5ERR 1 check error state while GSSDICTRL 3 wait for idle request acknowledge 3 3 8 Single stepping entry of standby modes Summary Debugger might loose connection and in most cases it is able to resume operation after system wake up Furthermore by temporary i e in a debugger data window masking the normally unmasked debugger wake up flag it is possible to debug the deep stop sequence Set the debugger connection timeout to be long enough for another wake up event to occur Additional Info The connection loss is not influenced by any data or memory window Disabling debugger wake up for ISO10nly does not prevent the connection loss issue and still and does not solve the debugging of the deep stop sequence for ISOO And additionally after debugger wake up the system is not really operational as the ISO1 is still disabled Details Case 1 WUFHO bi
14. ecommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions 5 POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation o
15. entry sequence For ISO1 no problem For ISOO after completing the last write command of the protected sequence that sets the ISO into deep stop the debugger can t set the breakpoint for the next instruction and might loose connection It is not influenced by any open data or memory window The debugger looses connection to the target and tries to reconnect After a while connection timeout period it shows a dialogue box asking if you want to continue waiting or terminate the connection If you choose to continue and Preliminary User s Manual EEDT CD 0423 02 26 34 NESAS generate a valid wake up event the debugger resumes operation at the expected entry point reset vector This was a bit different for the umbrella device as far as remember There a resume of operation did not work b Stepping over deep stop entry sequence The DS mode is reached as expected In the debugger command window it shows Target CPU status 0x8 HARDWARE STOP Wake up by debugger of course does not work for ISOO and ISO1 An attempt to set a breakpoint or a click on the debugger stop button leads to connection loss as described above If you generate a valid wake up event before the connection timeout occurs the debugger resumes operation at the expected entry point reset vector After the dialogue box occurrence connection timeout the debugger cannot resume after wake up But it is still able to reset the target Case 4 WUFHO bit set WUFH1 b
16. epaired by the customer e lfitwas dropped broken or given another strong shock e Use at overvoltage use outside guaranteed temperature range storing outside guaranteed temperature range e f power was turned on while the AC adapter interface cable or connection to the target system was in an unsatisfactory state e If the cable of the AC adapter the interface cable the target cable or the like was bent or pulled excessively e f an AC adapter other than the supplied product was used e fthe product got wet e If the product and target system were connected while a potential difference existed between the GND of the product and the GND of the target system e f a connector or cable was connected or disconnected while power was being supplied to the product e f an excessive load was applied to a connector or cable e If the product is used or stored in an environment where an electrostatic or electrical noise is likely to occur 2 Safety precautions e f used for a long time the product may become hot 50 to 60 C Be careful of high temperature burns and other dangers due to the product becoming hot e Be careful of electrical shock There is a danger of electrical shock if the product is used as described above in 1 1 Circumstances not covered by product guarantee e The AC adapter supplied with the product is exclusively for this product so do not use it with other products Preliminary User s Manual EEDT CD 0423
17. ering logic circuits and microcontrollers This manual describes the basic setup procedures and how to set switches to understand the overall functions and usages of the IECUBE2 POD s Read this manual in the order of the CONTENTS To know the manipulations command functions and other software related settings of the IECUBE2 POD s See the user s manual of the debugger supplied with the IECUBE2 POD s to be used Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Prefix indicating power of 2 address space memory capacity K kilo 210 1 024 M mega 2 1 024 The meanings of the terms used in this manual are described in the table below Term Meaning Target device This is the device to be emulated Target system This is the system to be debugged system provided by the user This includes the target program and the hardware provided by the user IECUBE2 Generic name for Renesas Electronics high performance compact in circuit emulator POD This is IECUBE2 peripheral to interface with the target system Preliminary User s Manual EEDT CD 0423 02 Related Documents Trademarks 2tENESAS Please use the following documents in combination with this manual The related documents listed below
18. f internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Preliminary User s Manual EEDT CD 0423 02 2tENESAS Introduction Readers Purpose Organization How to Read This Manual Conventions Terminology 2tENESAS This manual is intended for users who wish to perform debugging using the IECUBE2 POD s The readers of this manual are assumed to be familiar with the device functions and usage and to have knowledge of debuggers This manual is intended to give users an understanding of the basic specifications and correct usage of the IECUBE2 POD s This manual is divided into the following sections e General e Setup procedure e Settings at product shipment e Notes e Optional functions It is assumed that the readers of this manual have general knowledge in the fields of electrical engine
19. ffffffff Target mode with connected target connect 850eserv2 iecube e2 ip C GHS v850e df dfxxxx 800 tc id ffffffffffffffffffffffff Please note when df ip and environment variable DEVICE FILE IEPATH are specified simultaneously the device file and the directory specified by df and ip are given to priority For details about debugging procedures see the document supplied with the software tool Preliminary User s Manual EEDT CD 0423 02 18 RENESAS 2 5 Shut down procedure Shut down the system according to the procedure below Note that shutting down the system incorrectly might damage IECUBE2 1 Exit the software tool Remark Observe the power down sequence i en GE target system Do not power down POD if target is still powered 3 Turn off IECUBE2 Preliminary User s Manual EEDT CD 0423 02 19 2tENESAS 3 Differences between Target Device and POD This chapter explains the differences on using the POD to the V850E2 Dx4 devices There are other User s Manuals important covering the specific description of the devices the Core Architecture and the IECUBE2 Refer to these versions or check for current version Hardware UM V850E2 Dx4 U20018EE0V3UMOO Architecture UM V850E2 Dx4 U17135EJ1V1UMO00 Customer Notification CN V850E2 Dx4 Customer Notification EEDT OP 0044 for QB 70F3534 PD Customer Notification EEDT OP 0046 for QB 70F3532 PD Note Download the documents from the Renesas
20. g but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics
21. hall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as
22. idered to be on when 2 7V The Target LED turns on when target power is over this threshold value Preliminary User s Manual EEDT CD 0423 02 20 2tENESAS 3 1 3 Electrical differences on port pins The electrical characteristics of the port pins may differ between tool and device This is valid for all pins due to the usage of target connectors ea adapter and additional PCB wiring for each signal pin 3 1 3 1 Electrical differences on ADC pins As any of the analogue input signals and the reference voltage is connected via target connectors ea adapter additional PCB wiring and internal switches on the POD for Vref the converted values may differ between tool and device 3 1 3 2 Electrical differences on RSDS pins As these signals are not routed as different pairs on the POD PCB the signal may differ between tool and device 3 1 3 3 Electrical differences on other pins IC FLMDO has a 12k1 pull down and may have different input characteristics PO 1 FLMD1 has a 100k pull down QB 70F3532 only and may have different input characteristics RESETZ is emulated with similar circuit may have different input characteristics PWGD is emulated with similar circuit may have different input characteristics WAKE is emulated with similar circuit may have different input characteristics X1 X2 and XT1 XT2 are not connected to target 3 2 Functions not emulated by real chip on the POD The emulation tool is based on real chip base All
23. it cleared wake up by debugger disabled for ISOO and enabled for ISO1 This case is not used 3 3 9 Not supported functions The following functions are not supported by the POD OCD Boundary Scan FP5 programming Preliminary User s Manual EEDT CD 0423 02 27
24. lectronics website http www renesas com Preliminary User s Manual EEDT CD 0423 02 2tENESAS Warning amp Caution This equipment complies with the EMC protection requirements WARNING This is a Class A EN 55022 2006 A1 2007 equipment This equipment can cause radio frequency noise when used in the residential area In such cases the user operator of the equipment may be required to take appropriate countermeasures under his responsibility EEDT ST 001 20 CAUTION This equipment should be handled like a CMOS semiconductor device The user must take all precautions to avoid build up of static electricity while working with this equipment All test and measurement tool including the workbench must be grounded The user operator must be grounded using the wrist strap The connectors and or device pins should not be touched with bare hands EEDT ST 004 10 For customers in the European Union only Redemption of Waste Electrical and Electronic Equipment WEEE in accordance with legal regulations applicable in the European Union only This equipment including all accessories is not intended for household use After use the equipment cannot be disposed of as household waste Renesas Electronics Europe GmbH offers to take back the equipment All you need to do is register at http www renesas eu weee Preliminary User s Manual EEDT CD 0423 02 Notes for CMOS Devices 1 VOLTAGE APPLICATION WAV
25. may include preliminary versions However preliminary versions are not marked as such Documents Related to Development Tools User s Manuals Document Name Document Number Preliminary User s Manual IECUBE2 POD for V850E2 Dx4 This manual User s Manual Preliminary IECUBE2 main QB V850E2 In ZUD CD 10 0092 Circuit Emulator actual Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing etc Green Hills the Green Hills logo CodeBalance GMART GSTART INTEGRITY and MULTI are registered trademarks of Green Hills Software Inc AdaMULTI EventAnalyzer G Cover GHnet GHnetLite Green Hills Probe Integrate ISIM PathAnalyzer Quick Start ResourceAnalyzer Safety Critical Products Slingshot SuperTrace Probe TimeMachine and TotalDeveloper are trademarks of Green Hills Software Inc Windows and Windows Vista are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of International Business Machines Corporation All other company product or service names mentioned in this documentation may be trademarks or service marks of their respective owners Preliminary User s Manual EEDT CD 0423 02 2tENESAS Guarantee amp Safety precautions 1 Circumstances not covered by product guarantee e fthe product was disassembled altered or r
26. nary User s Manual EEDT CD 0423 02 22 2tENESAS 3 2 5 Target Memory emulation concept QB 70F3532 PD only The emulation of the external memory interface device UPD70F3532 only is substituted on POD This memory interface is not connected to the target application The memory interface to the target is clamped at an inactive level with a 10k pull down The software may differ for the setup of the memory controller Port SDRAM signal Termination P22 0 10k pull up P22 6 3 DQN 3 0 10k pull down P26 12 0 A 12 0 10k pull down Table 3 1 Memory interface pins on POD 3 2 5 4 Memory usage The memory can be used either for application usage or for profiling depending on the device subject of emulation and the requirements It can be used both for code and for data The profiling memory can be used by software profiling tools to store information collected during run time No hardware support for profiling is implemented in this tool substitute optional uPD70F3535 DP4 H BGA408 3MB 61MB 23MB uPD70F3532 DN4 H BGA352 0 64MB 64MB reduced by the amount of target memory 3 2 5 2 Memory map The profiling RAM will be located in an area that is usually used for HSFI1 interface for devices supporting this feature The HSFI1 interface usually is located in the area from OxF400 0000 0xF77F FFFF 56MB To be able to access the profiling memory this area is reduced according to the following table DJ4 de
27. nctions Open break function peripheral break function mask function _RESET internal reset Note QB 70F3534 PD QB 70F3532 PD Preliminary User s Manual EEDT CD 0423 02 13 RENESAS 1 3 Adapters Connectors The following adapters and connectors are necessary to connect the POD to the target system These adapters and sockets are sold separately Exchange adapter _ QB 144GJ EA 60T QB 408F1 EA 61T___ foB 852F1 EA 60T Emulator connector QB 144GJ YQ 01T Target connector QB 144GJ NQ 01T BSSOCKET408 QB 352F1 NQ 01T Note Products of Tokyo Eletech Corporation http www tetc co jp Figure 1 2 Description of Target Connection Details ITT Figure 1 3 Target Connection Details Height Preliminary User s Manual EEDT CD 0423 02 14 2tENESAS 1 4 Package Contents The packaged items might vary depending on the region in which the product is purchased Therefore confirm that the items in the attached packing list are included Refer to the actual Package Contents List PCL for the Products supplied with the IECUBE2 POD s Preliminary User s Manual EEDT CD 0423 02 15 stENESAS 2 Setup Procedure This chapter explains the IECUBE2 setup procedure Setup can be completed by performing installation setup in the order in which it appears in this chapter 1 Installation of Software tools 2 Clock Setting 3 Connection of System 4 Turn on IECUBE2 6 Start the
28. notifications of the real device applies for the POD too For this information refer to the customer notification of the device For functions which are not emulated by the real chip on the POD discrete circuits are used to emulate these functions For these functions the behavior may differ The following listed functions are emulated may differ from tool to the target devices 3 2 14 RAM contents during deep stop When entering deep stop 1 2V are not removed RAM content will remain unchanged 3 2 2 RESET function The Reset signal is emulated with an additional circuit The input is sampled in every 200ns After that true RUN will happen but IECUBE2 needs hundreds of ms delay than on target device 3 2 3 POC function POC function is emulated with an additional circuit The period of POC Power On Clear is longer than on a target device because the emulation chip is also reset The emulator reconfigures the setting for debugging e g breakpoint after POC Parts of trace data before POC Power On Clear may be lost because the emulation chip is also reset The trace data FIFO in emulation chip is cleared in case of a POC Preliminary User s Manual EEDT CD 0423 02 21 2tENESAS 3 2 4 WAKE PWGD function Wake and PWGD function is emulated with an additional circuit The generation time may differ than on the target device 3 2 4 1 Watchdog timer WDTA During break mode the WDTA is always stopped even if peripheral break
29. nts during deep stop EEN 21 3 2 2 RESET function 21 cM exse 21 3 244 WAKE PWGD ee EE 22 3 2 5 Target Memory emulation concept QB 70F3532 PD on 23 33 CAUS c a 25 3 31 Data flash read RTE 25 CR CEET NEE 25 3 3 3 Reset issued by the debugger AEN 25 3 3 4 Reset during break mode trente tnt Renten hr Rn E Re EXER CR AAt araea ee RARE PARERE 25 BIBS FAS e ace 25 3 3 6 FLMDO during TRESETZ active nien center eet ordeo deed rece itr a De nian ra eda E vec aun 25 3 38 7 AHB time out during MeMVIEW reet erennnrret etre Kadena anean sinn 25 3 3 8 Single stepping entry of standby modes enne enne 26 3 3 9 Not supported functions ek eese decis etui pe oko ne Lun Ere aa ara a baaaie aba onda ed nee abd gue 27 Preliminary User s Manual EEDT CD 0423 02 10 2tENESAS List of Figures Figure 1 1 Description of IECUBE2 POD 12 Figure 1 2 Description of Target Connection Details AAA 14 Figure 1 3 Target Connection Details Height AAA 14 Figure 2 1 COCK SOLU A M 16 Figure 2 2 System setup cccccceececeeeeeeeeeeeeeaeeeceneeeeeeeeeeaeeecaeeseaeeeseaeeesaeeesaneeseaneeseaeeeceeseeaeeseeeeeseeeeeeaeeens 17 Figure 2 3 T mM ON EE 18 List of Tables
30. o be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military includin
31. software tools Remark Observe the power up sequence Do not power on target if POD is not powered 2 1 Installation of Software tools Before setting up hardware install the necessary software tools For details about how to do so see the documents supplied with the software tools 2 2 Clock Settings The main clock is generated by the oscillator in the emulation POD In case using the default frequency of the crystal the setting is not required to be changed In case of customer specific frequency modification is necessary see following procedures Caution This product does not support clock input from target Sublock is fixed to 32 768kHz 1 Open the emulation POD cover as shown below Figure 2 1 Clock setup 23456789 To remove the socket use a tool such as a preaision serewdriver 2 Mount the resonator and capacitors onto the parts board in the emulation POD 3 Close the emulation POD cover Factory setting 4MHz crystal is mounted upon shipment Preliminary User s Manual EEDT CD 0423 02 16 2tENESAS 2 3 Connection of System This section describes how to mount and connect components including connectors Mount the target connector onto the target board For details about how to do so see the document supplied with the connector For details and setup about IECUBE2 refer to the IECUBE2 User s Manual Figure 2 2 System setup USB Cable Host Machine IECUBE2 Main IECUBE2 I
32. t cleared WUFH1 bit set wake up by debugger enabled only for ISOO 8 Stepping through deep stop entry sequence For ISO1 no problem For ISOO as expected immediate wake up after DS entry in the debugger window you see the status HARDWARE STOP but in fact there is no DS entry as the software just continues without going through reset The debugger does not lose connection independent from any memory or data windows open b Stepping over deep stop entry sequence The DS mode is reached as expected Wake up by debugger works for ISOO ISO1 remains stopped The debugger does not looses connection independent from any memory or data windows open Case 2 WUFHO bit cleared WUFH1 bit cleared wake up by debugger enabled for ISOO and ISO1 a Stepping through deep stop entry sequence For ISO1 as expected no standby so the software remains in a while loop waiting for the ISO1 to report stand by mode For ISOO no DS entry attempt the software waits for ISO1 The debugger does not crash or lose connection independent from any memory or data windows open b Stepping over deep stop entry sequence The DS mode is reached as expected Target CPU status 0x8 HARDWARE STOP Wake up by debugger works for ISOO and ISO1 The debugger does not crash or looses connection independent from any memory or data windows open Case 3 WUFHO bit set WUFH1 bit set wake up by debugger disabled for ISOO and ISO1 8 Stepping through deep stop
33. vices remain all their features they just gain the profiling memory foe J I Leen JI oe Less type size DRAM area mem size mem area Pe de OxF77F FFFF eDRAM OxF7FF FFFF DN4 H Se 0 64MB OxF400 0000 0 64MB OxF400 0000 SDRAM OxF7FF FFFF OxF7FF FFFF DP4 H profiling 32MB OxF400 0000 OxF780 0000 32MB OxF600 0000 OxF5FF FFFF only OxF7FF FFFF OxF7FF FFFF Preliminary User s Manual EEDT CD 0423 02 23 2tENESAS 3 2 5 3 Available memory The amount of external available memory is 64MB It is implemented as SDR single data rate SDRAM synchronous dynamic random access memory The selected RAM device has the following characteristics Feature eDRAM LEHUA Substitution RAM IS42532160A 75BL 6 Column address width bits 9 A10 is auto precharge Max frequency tck MHz 126 120 5 dithering Same 133MHz is supported but not required Suitable for SSCG Yes Same Same 8192 64ms more often is no problem Same supported but not required Same supported but not required Same Refresh command timing tRC CLKs CAS latency tRCD CLKs Same and 2 20ns Command period tRP CLKs 20ns Same interleaved also supported but not required Same supported but not required Same more features supported but not required Modetimng MRD CCL Ks Same supported but not required For setup refer to Hardware UM V850E2 Dx4 chapter 37 Preliminary User s Manual EEDT
34. web site Renesas Electronics website http www renesas com 3 1 Electrical differences The following listed electrical characteristics may differ from tool to the devices 3 1 1 Electrical differences on power pins The current load on all power pins may differ between tool and device This is valid for all power pins due to the usage of target connectors ea adapter additional PCB wiring and internal switches on the POD Power groups are handled different on POD side For example power is supplied statically internal Internal static supply for Core Flash Oscillator and eDRAM power Internal supply for EOVDD and REGCVDD in case of target voltage is less 3 0V All other power pins will be supplied from target All VSS pins are short circuited inside the tool to a common ground plane REGOVSS is used to detect the target hardware and is not connected to ground but to a weak pull up resistor Connect it to ground on the target hardware as usual Internal supply for EOVDD and REGCVDD is less than on target side Due to the usage of schottky diodes for these power on the POD the supplied device part is approx 0 2V less than on target side Ports PO JPO Wake output levels are approx 0 2V lower than on device LVI effective levels are approx 0 2V higher than on device POC effective levels are approx 0 2V higher than on device VLVF not supported 3 1 2 Target power on REGOVDD is used for target power on detection It is cons
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