ADSP-21061 EZ-KIT Lite Reference Manual
Contents
1. amp RESET THEN sreg STATEO WHEN Sreg FB STATEO H sreg FB STATE1 sreg FB STATE2 sreg FB STATE3 sreg FB STATE4 H sreg FB STATES H sreg FB STATEG H sreg FB STATE7 H sreg FB STATES H sreg FB STATE9 H sreg FB STATE10 H sreg FB STATE11 H sreg FB STATE12 H sreg FB STATE13 sreg FB STATE14 H sreg FB STATE15 H sreg FB STATE16 H sreg FB STATE17 H sreg FB STATE18 H sreg FB STATE19 amp RESET THEN sreg STATEO State diagram sreg State STATEO 1 IF RESET THEN STATEO ELSE IF SEL THEN 5 1 58 IF SEL State 5 1 THEN STATEO 1 RESET THEN STATEO ELSE IF 0 THEN STATE2 State STATE2 1 RESET THEN STATEO ELSE IF SEL amp RD amp WR 4 IF SEL THEN STATEO IF ISEL amp IRD amp WR IF SEL amp WR amp RD State STATE3 0 RESET THEN STATEO ELSE IF 0 THEN 5 4 state STATE4 0 RESET THEN STATEO ELSE IF 0 THEN STATES State 5 5 0 RESET THEN STATEO ELSE IF 0 THEN 5 6 State 5 0 RESET THEN STATEO ELSE IF 0 THEN STATE7 State STATE7 0 RESET THEN STATEO ELSE IF 0 THEN STATE14 State STATES 0 RESET THEN STATEO ELSE IF 10 THEN2. Js Input 1 EZ KIT LITE S3 Reset ANALOG DEVICES DC Auxiliary Power Supply DC Power Supply Connector Solder Points Figure 2 1 Hardware Connections to the ADSP 21061 EZ KIT Lite 2 6 1 Serial Port RS 232 Connector P1 is female 9 pin D Sub connector used to communicate with a host computer using RS 232 signal levels and asynchronous serial protocols The supplied cable provides a straight through connection from the DCE port on the EZ KIT Lite to the DTE port on your PC The DCD DTR and DSR signals are connected on the EZ KIT Lite board 16 Table 2 3 Serial Port Pin Descriptions 2 Transmit Data output Receive Data input 4 DTR Signal Ground DSR Request to Send input Clear to Send output Not Connected 2 6 2 Stereo Audio Output The Stereo Audio Output Jack connects to the left L and right R LINE OUTPUT pins of the AD1847 codec Use standard audio cables with 1 8 inch 3 5mm stereo plugs to connect these signals to a set of amplified speakers 2 6 3 Stereo Audio Input The Stereo Audio Input jack connects directiv to the left L and right R LINE 1 INPUT pins of the AD1847 codec Use standard audio cables with 1 8 inch 3 5mm stereo plugs to supply these inputs with line level signals You can also connect a microphone level signal by changing the Input Source Selector Jumpers See section 2 6 4 DC Power Supply Connector The power supply connector is u
3. Figure 5 5 Line Level Input Audio Factory Default JP8 LHJJO MIC Line Figure 5 6 Microphone Level Input Audio 5 3 2 Boot Control Jumper Block These jumpers control three of the ADSP 21061 SHARC processor s pins EBOOT JP5 LBOOT JP6 and IDO JP7 The first two define the processor s boot mode according to the following table Table 5 1 Boot Mode Selection Mode JPS JP6 EPROM OUT IN Host Port IN IN Link Port IN OUT The ADSP 21061 EZ KIT Lite is shipped with EPROM boot mode selected by default The pins at location JP6 are shorted on the circuit board The IDO pin determines the ADSP 21061 SHARC processor s multiprocessor ID If JP7 is shorted the multiprocessor ID number is 000 If JP7 is left open the factory shipped default the multiprocessor ID number is 001 5 3 3 EPROM Settings Jumper Block These four jumpers 1 JP4 define the size of EPROM that you have installed in the boot PROM socket The ADSP 21061 EZ KIT Lite is shipped with 27C010 selected by default The pins at locations JP2 and JP3 are shorted on the circuit board 37 Table 5 2 EPROM Jumper Selection Chart 07 JPI JP2 JP3 JP4 27 256 32K x 8 OUT IN OUT IN 27C512 64K x 8 OUT IN IN OUT 27C010 128K x 8 OUT IN IN OUT 27C020 256 x 8 IN OUT IN OUT 27C040 512K x 8 IN OUT IN OUT 27 080 1M x 8 IN OUT IN OUT 5
4. sse 19 EZ KIT Lite License Installation 15 EZ KIT Lite package contents 12 EZ KIT Lite Software Installation 15 EZ KIT Lite System Architecture 8 EZ Lite default settings seen 15 F Filter 29 Bla QS eb e RE 18 H Halt loop 4 See RE ER Rt 21 Hardware 2 2 16 Hardware Installation pe 14 1 T O Devices ioannes 18 IMASK register neniru 19 Information More about Analog Devices Inc Products dro i sna 8 Input Source Selector sss 37 Installation EZ KIT Lite License 15 Installation EZ KIT Lite Software 15 Installation 14 Installation 14 Internal Loop acK 6 20 Internal Memory 40 einn Op ante 41 JTAG COnneCtot c torte 35 Jump 24 eer RS 36 K Kernel C d eet 24 Kernel Compatibility esses 40 L Layout board i 33 LED PoWer uns A 34 34 License EZ KIT Lite Installation 15 Loading Programs 26 Location of Configuration Jumpers 36 M Major
5. eun 4096 53 81M ec W SITE L 3 A ANDY 4 sjy uo PBS 50 1 jo 8 1995 HOS Xd J0129uU0 Dupa 317 23 08VH5 Peyojndodun s40328uuo2 2594 eloN 91201 18045 51 UX 23 0 5 op OEXZUQH payojndod asp 5 2 2594 ILON Sc 53 i 11 pes ROS Kd suus SJOMHIE 4661 01 493 uon 9300 54 LX 23 OUVHS eni 5 n i 5 Mer JAW KIT LITE Number Rev Caps Page Rev 1 Date Mon Feb 19 1997 Drawn by BittWare SHARC EZ o E 55 12 Filename PX SCH Sheet 12 of 8 3 PAL Equations Equations used to program the 16v8 PAL device U3 PSTATE ABL ABEL code created by Visual Software Solution s StateCAD Version 3 00 Thu Feb 06 09 23 40 1997 MODULE PSTATE DECLARATIONS clock name CLK PIN 1 Input variables RD PIN 6 RESET PIN 3 SEL PIN 5 WR PIN 4 ROE PIN 11 Output variables ACK PIN 12 ISTYPE com Logic variables UARTRST PIN 18 ISTYPE com State variables SVO 1
6. 33 Manual Contents 9 NEO 27 Memory 23 39 Monitor program components h lt loo e re repere 21 Monitor Program Operation nn 21 Multiprocessor Memory Space 40 P POST ere cent 20 Power LED is senk tme tc etes 34 Power Removal 36 Power Supply DC Connector 17 Power Up 35 Pushbutton Switches sss 34 R Register Write assesses 20 Registers aussen Rer 27 Remove power cessere 36 Resetting the EZ KIT Lite Board 27 Resistor Pull ups es 43 Restricted Memory 24 Run time header sss 24 8 Schematics 43 Serial Port RS 232 16 Serial Ports ied 20 Settings menu eie ied 42 Settings Configurable sss 15 Software Installation EZ KIT Lite 15 Source IMPULS issa retener nee e 30 SPORT Termination sse 43 Stepping inerte deer ares 27 Stereo Audio Input 17 Stereo Audio 17 Support Customer or seeen einne ei 9 Support Technical pe 9 Switches pushbutton sss 34 System Architecture EZ KIT Lite 8 T Techn
7. directory paths are based on default installation 4 4 2 Primes Demo This program calculates the first twenty prime numbers When the calculation 1s completed you can view the results in the Expressions window Open an Expressions window from View 7 Debug Window 7 Expressions Click inside the Expressions window so it is active and type the word primes inside the window Then hit enter Now expand the primes by clicking on the plus sign next to the word primes Expressions H primes 1722 101 0 00000002 1 0x00000003 2 0x00000005 3 0x00000007 4 0x0000000b 5 0x0000000d 6 0 00000011 7 0 00000013 8 0x00000017 9 0x0000001d 10 0 00000014 11 0 00000025 12 0 00000029 13 0x0000002b 14 0 0000002 15 0x00000035 16 0x0000003b 17 0x0000003d 18 0 00000043 13 0x00000047 Figure 4 6 Expressions Window for Primes Demo The C source code for this program is located in the Program Files Analog Devices VisualDSP 21k EZ KITs ADSP 21061 Demos primes directory 4 4 3 Peter Gunn Demo This program demonstrates the Karplus Strong algorithm for simulating the sound of a plucked string The ADSP 21061 SHARC processor uses the algorithm to generate digital audio samples according to data that specifies the notes to be played The audio samples are transmitted to the AD1847 codec over a serial port The codec converts the data to an analog signal that drives the output device The
8. 4 2 Starting the VisualDSP Debugger After the VisualDSP software and license have been installed click the Windows Start menu Select Programs gt VisualDSP gt Debugger from the Start menu From the Session menu choose New Session The New Session dialog box appears Configure the debug session as shown in Figure 4 1 and click OK Target Selection Processor Platform JEZ KIT Lite Target name faDsP 21 061 EZ KIT Lite EZ KIT 2106 Cancel Figure 4 1 Target Selection Dialog A Target Message dialog box appears 25 Target Message N Hit Reset button on board Figure 4 2 Target Message Press the Reset button on the EZ KIT Lite evaluation board After 5 seconds all the LEDs light up and then all of them turn off except the POWER LED Ensure that all LEDs turn off except for the POWER LED before you click OK During this delay the POST test verifies operation of the UART After the LEDs go dark a message box opens with the message shown in Figure 4 3 Target N Communications Success Figure 4 3 Target Communications Status Message Box Click OK The initialization completes and the disassembly window opens The code in the disassembly window 1s the EZ KIT Lite monitor program 4 3 Debugger Operation with the ADSP 21061 EZ KIT Lite The VisualDSP Debugger Guide amp Reference contains most of the information you need to operate the VisualDSP debugger with your EZ
9. 4 UART The UART 04 and the line driver 05 provide the RS 232 interface used to communicate with the PC The PC16550D is similar to devices used in most PCs It has a programmable bit rate and has transmit and receive FIFO registers The UART is attached to the ADSP 21061 SHARC processor s external memory bus and is selected by 51 external memory bank 1 The UART can generate an interrupt to the ADSP 21061 SHARC processor on IRQ2 5 5 AD1847 The AD1847 codec U9 provides the stereo audio input A D and output D A interface It is connected to the ADSP 21061 SHARC processor via SPORTO This high speed synchronous serial port carries all of the data control and status information between the DSP and the codec 38 6 PROGRAMMING REFERENCE 6 1 Overview This chapter provides the technical details you need to write programs for the ADSP 21061 EZ KIT Lite One section focuses on memory models addresses and other resources for programs that run on the ADSP 21061 SHARC processor The other section focuses on the serial host interface so that you can write programs on the PC that talk directly to the monitor program running on the EZ KIT Lite board 6 2 DSP Programs This section describes the model for EZ KIT Lite DSP programs by focusing on the resources that are available to the ADSP 21061 SHARC processor These resources include the memory map the flags the interrupts and the serial ports Table 6 1 summarizes these
10. ISR or the Halt Loop is done in the command processing kernel This kernel parses the commands and executes the instructions If the instruction requires that data be sent back to the host the kernel initiates the response 3 3 Running Your Own Programs This section provides basic information needed to run your own programs on the ADSP 21061 EZ KIT Lite board Build these programs using the ADSP 21061 SHARC processor tools This information includes rules for using processor memory Although there are many ways to develop programs in VisualDSP all program evaluation within the environment include the following steps 1 Create a new project file 2 Set the target processor under Project Options 3 Add and edit project source files 4 Customize project build options 5 Build a debug version of the project 6 Debug project 7 Build a release version of the project By following these steps DSP projects build consistently and accurately with minimal project management The ADSP 2106x SHARC User s Manual provides detailed information on programming the processor and the VisualDSP manuals provide information on code development with the ADSP 21061 SHARC processor tools e Donotrun more than one ADSP 21061 EZ KIT Lite session at any one time You may run an EZ KIT Lite debug session and a simulator or you can run a JTAG ICE session and a simulator session at the same time e Before making any changes to the source code
11. KIT Lite evaluation board 4 3 1 Loading Programs Because you are loading programs to a hardware target through the serial port the load process takes more time than loading using the simulator Wait for the Load Complete message in the Output window before you attempt any debug activities 26 To load a program From the File menu choose Load The Open a Processor Program dialog box appears Navigate to the folder in which the DSP executable file resides The demos that are supplied with the EZ KIT Lite are located in C Program Files Analog Device VisualDSP 21k EZ KITS ADSP 21061 Demos NOTE All file directories assume a default installation Select the dxe file and click Open The file loads and the message Load Complete appears in the Output window when the load process has completed 4 3 2 Registers and Memory To see current values in registers use the F12 key or the Window gt Refresh command e Values may not be changed while a user program is running e current version of the VisualDSP debugger does not let you view hardware stack information 4 3 3 Setting Breakpoints and Stepping e Breakpoints set in the last three instructions of a DO loop are allowed but cause improper debugger operation e Breakpoints set after a delayed branch instruction and before the branch occurs cause improper debugger operation single step command steps through a delayed branch instruction and the last thre
12. Mode Selection 37 Boot PROM Asia a a i 34 Breakpoints 27 C Codec Programming 2 2 40 Com Port command pps 42 Command 22 Command Processing Kernel 21 Commands Ba d Rate oed ded etes 42 Com Port aie bb 42 Test Communications sese 42 Configurable EZ KIT Lite Settings 15 Configuration Minimum Requirements 13 Connector DC Power 17 Connector JTA Ginastera n an 35 Connectors Expansion 35 Contents Descriptions pe 9 Contents of EZ KIT Lite Package 12 Customer 9 D DC Power Supply Connector 17 Default Settings sse 15 Default Settings on the EZ Lite 15 Demonstration 25 Diagram ADSP 21061 EZ KIT Lite System 8 Documentation Related Products 10 erret PEE nes 39 eee EE 8 Electrostatic Discharge ESD 12 EPROM Settings 37 Expansion Port 35 Expressions 31 External Interrupts
13. STATES State 5 9 ISEL amp WR amp THEN STATE3 THEN STATE5 RD THEN 5 2 59 0 IF RESET ELSE IF 0 State 5 10 0 IF RESET ELSE IF 0 State 5 11 0 RESET ELSE IF 0 State 5 12 0 IF RESET ELSE IF 0 State STATE13 1 RESET ELSE IF 0 State 5 14 0 RESET ELSE IF 0 State 5 15 0 IF RESET ELSE IF 0 State 5 16 0 RESET ELSE IF 0 State 5 17 0 RESET ELSE IF 0 State 5 18 THEN STATEO THEN STATE10 THEN STATEO THEN STATE11 THEN STATEO THEN STATE12 THEN STATEO THEN STATE13 THEN STATEO THEN STATE19 THEN STATEO THEN 5 15 THEN STATEO THEN STATE16 THEN STATEO THEN STATE17 THEN STATEO THEN STATE18 60 1 IF RESET THEN STATEO ELSE IF 0 THEN STATE19 State 5 19 1 IF RESET THEN STATEO ELSE IF 0 THEN STATEO Logic Equations EQUATIONS UARTRST RESET END PSTATE 61 else UARTRST RESET UWR SV2 SV1 SVO SV 63 ISEL ISEL amp IRD amp WR STATES STATE3 SV 16 ACK SV 8 ACK STATE6 5 4 SV 17 ACK SV 9 ACK STATE7 STATES SV 18 ACK SV 10 ACK STATE14 STATE9 SV 19 ACK SV 11 ACK STATE1
14. an interrupt to the DSP This lets you manually cause this interrupt when executing a program IRQ2 is shared with the UART and IRQO is brought out to the expansion connector See Flags section in Chapter 3 for more information on interfacing to the pushbutton switches from DSP programs 5 2 4 User LEDs There are four LEDs on the ADSP 21061 EZ KIT Lite board Your DSP program can control them to indicate certain conditions in the software or to provide feedback The LEDs are controlled by processor FLAG outputs of the DSP and are labeled according to the flag that enables them 5 2 4 1 Power LED The Power LED when on indicates that 5 VDC used by the DSP and digital circuitry is present 34 5 2 5 Expansion Port Connectors There are seven expansion connector sites that provide the signals for adding optional custom hardware The interface contains the ADSP 21061 SHARC processor bus as well as six link ports a synchronous serial port interrupts flags and various control signals Pin 1 Pin 1 Ext Switch and LED Connectors Pin 1 1 0000000 1 Pin 1 Pin 1 Figure 5 2 Expansion Port Connectors 5 2 6 JTAG Connector Emulator Port The JTAG header Figure 5 2 1s the connecting point for the JTAG emulator probe Note that one pin is missing Pin 3 to provide keying The Pin 3 socket in the mating connector has a plug inserted at that location The ADSP 21061 EZ KIT Lite b
15. baud rate of 115200 with 8 data bits 1 stop bit and no parity If you want to change this rate change it after the POST is complete by using the Settings Baud Rate command from the menu bar Note that setting the baud rate to a lower number can significantly slow the board s response to all debug activities 3 2 3 Monitor Program Operation The Monitor runs on the EZ KIT Lite board as part of the DSP executable and provides the ability to download debug and run user programs The Monitor uses VisualDSP as the interface Using the EZ KIT Lite as a target allows you to operate the board remotely On initial power up of the EZ KIT Lite board the original monitor is booted from the EPROM to the target board Once you start the EZ KIT Lite debug session using VisualDSP this monitor downloads a new monitor from your PC onto the target board The new monitor communicates to the target dll through the serial port There are three main components of the new monitor program e Halt loop UART ISR e Command Processing Kernel The monitor program idles in the Halt loop when it 15 not running user code While there you can read write memory read write registers download programs set breakpoints change the UART s baud rate and single step through code To enter the halt loop from your code you must halt user code either with a breakpoint or a halt instruction At this point the halt loop polls the UART With every character re
16. conditions requiring attention however the IRQ2 signal will not transition to the inactive state and then back to the active state Therefore the ADSP 21061 SHARC processor s interrupt controller must treat IRQ2 as a level sensitive signal Bit 2 IRQ2E in the MODE2 register must remain cleared 41 7 REFERENCE 7 1 OVERVIEW This chapter is a reference for VisualDSP Because the debugger is dynamic menu selections commands and dialog boxes change depending on the target being used This chapter provides information on all of the menu selections commands and dialog boxes when the target is the ADSP 21061 EZ KIT Lite evaluation board For all other commands see the VisualDSP Guide amp Reference Manual Note that grayed out commands are unavailable with this target 7 2 SETTINGS MENU COMMANDS of the commands that pertain to the EZ KIT Lite board are contained in the Settings and Demo menus The Settings menu provides access to the following commands Settings Tools Window Help Test Communications Breakpoints Alt F9 Gene Interrupts Streanis Preferences Baud Rate Comm Port v Enable Stdio Support Figure 7 1 Settings Menu Commands 7 2 1 Test Communications Tests the PC to ADSP 21061 EZ KIT Lite communications Responses are Communications Success or various error messages sent to the Output window In most cases resetting the ADSP 21061 EZ KIT Lite re establishes communication 7 2 2 Baud Rat
17. demonstration starts with a talk through program with the Input Source set to Codec and the Filter range set to None The AD1847 codec digitizes the analog input signal and transmits the data to the ADSP 21061 SHARC processor s serial port The ADSP 21061 SHARC processor reads data from the serial port and retransmits the data back to the codec The codec converts the data to an analog signal that drives the output device The sample rate for the digital data is 8 kHz You may change the filter range and source without changing the code To change the filter range 1 From the Memory menu choose Two Column A two column window appears 2 Right click inside the Memory window and click Go 3 From the Go To Address dialog box click Browse 4 From the Browse Symbol dialog box double click on the symbol filter In the Memory window you will now be at the address for filter 28 Data DM Memory Hexadecimal filter 024025 00000000 source 024026 00000000 xmit ptr 024027 00000000 Bl xmit count 024028 00000000 cmd blk 024023 00000000 00000000 00000000 02402C 00000000 00000000 00000000 Figure 4 4 Memory Window for Symbol Filter The address that filter represents 15 right under the symbol name In this case it is address 0x24025 5 6 Change the value at this location to Table 4 1 Bandpass Filter Demo Filter Ranges Value 2 Filter Addres
18. eni 44 AT jo 9945 HOS Xd SJOMHIG UMDJQ 2661 BL 493 VON 9100 9 5 9021 5348 YLOHTZ 21 12391 23 Ovir 32123 9001 53 DUJ91X9 JO 9JD POJJDJSUI JOU BID TIP GLF 310N gn ETLOS E 18150 45 jo 1995 HOS Xd SOMBIE 1661 L 993 VON 9100 J9JJNE 3201 3 J9quunN UX 23 OUYHS op 84909 zuWQy peJejjnq eseu 310N n XXXDZZ1V au uer Ea ee A 25 50715841 wets S SIUL 301 gt 72 2V dd Jesn Aq payipow aq O I S901 JJUJO 559220 U PJDOQ PU uo eq 3ou 9dr Ld p400 uo JUL 91oN uonoejes POW 1008 JIVHS 46 21 jo 19845 HOS Xd SLUDUSJJ 9JDMHIH Aq UMDJO 4661 01 493 VON 9700 eub d QNO 241 JOPISULOS 680 eui UO 945 eut 31ON v 9on 6197 3910 11553010 47 466 0 493 9100 23 28VHS AT Jo S 19945 HOS Xd ADMHIE 9vu 2105 031 oor ANA 22 914 TWU 20105 AAA 2 ane va 2
19. in VisualDSP clear all breakpoints and close all Editor windows Then make the changes rebuild the program and reload it in VisualDSP 22 e If you are creating a C C program use the 060 hdr asm file supplied with the demo programs This file reserves the IRQ2 interrupt vector table for the UART 3 3 1 ADSP 21061 SHARC Processor Memory Map The ADSP 21061 SHARC processor has 1M of internal SRAM that can be used for program or data storage The configuration of on chip SRAM is detailed in the ADSP 2106x SHARC User s Manual Table 3 2 shows the memory map of the ADSP 21061 EZ KIT Lite The IMDWO bit in the SYSCON register must be set to 1 to keep communication with the host This bit determines whether data accesses made to internal memory block 0 are 40 bit three column accesses set 1 32 bit two column accesses cleared 0 The monitor program requires three column data accesses to memory block 0 On reset restart and halt the debug monitor kernel forces IMDWO to 1 and IMDWI to 0 but user code should also set these bits to ensure that it operates in the same way on both the simulator and the EZ KIT Lite board These settings affect data accesses only not instruction fetches Block 0 resides in three column memory If you are storing data in block 0 it must be in three column format Table 3 2 Memory Map 7 peres pm NOTE Use caution when accessing the boot EPROM The EPROM chip select 5 has the sam
20. separate CD ROM To install the EZ KIT Lite software 1 Ensure VisualDSP has been installed 2 Close VisualDSP and all Windows applications The install will not work correctly if any VisualDSP applications are running 3 Insert the EZ KIT Lite CD into the CD ROM drive The setup will automatically start Follow the installation wizard by choosing the appropriate options 4 When the setup has completed reboot the machine if necessary 2 5 4 1 Default Settings After you have installed the board and utility software your PC and EZ KIT Lite have the default settings shown in Table 2 2 You can change these settings through the Settings menu in the debugger Table 2 2 User Configurable EZ KIT Lite Settings Selection Pefault Setting COM Port COM 1 The VisualDSP debugger comes with complete on line help file and Adobe pdf files of all manuals 15 2 e You can use the context help button to get help on any command or icon Or e Highlight a command and press For help on commands and dialog boxes click from the toolbar Help gt Help Topics to get to the Debugger Help file 2 6 Hardware Connections Figure 2 1 highlights the external hardware connections to the ADSP 21061 EZ KIT Lite The following sections describe each of the connections Serial Port RS232 Connector JTAG Emulator Connector Stereo Audio ut Output i Stereo Audio
21. 3 ISTYPE reg SV1 PIN 14 ISTYPE reg SV2 19 ISTYPE reg URD 16 ISTYPE reg USEL PIN 17 ISTYPE reg UWR PIN 15 ISTYPE reg Vectors DECLARATIONS 5 1 USEL URD UWR SV2 SV1 SVO 56 State Register assignment DECLARATIONS sreg SV0 SV1 SV2 URD USEL UWR EQUATIONS sreg clk CLK Isreg oe ROE ACK oe SEL DECLARATIONS STATEO 1 1 1 1 1 1 STATE1 0 0 0 1 0 1 STATE2 1 0 0 1 0 1 STATE3 0 0 0 0 0 1 STATE4 1 0 0 0 0 1 STATE5 0 0 0 1 0 01 STATE6 1 0 0 1 0 01 STATE7 0 1 0 1 0 01 STATE8 0 1 0 0 0 11 STATE9 1 1 0 0 0 11 5 10 0 0 1 0 0 11 5 11 1 0 1 0 0 11 STATEI22 0 1 1 0 0 11 STATE13 1 1 1 0 O 1 STATE14 1 1 0 1 0 0 STATEI5Z O 0 1 1 0 01 STATE16 1 0 1 1 0 0 STATE17 1 1 0 1 O 1 STATE18 0 0 1 1 0 1 STATE19 0 1 0 1 0 11 EQUATIONS WHEN 5 sreg FB STATE1 sreg FB STATE2 sreg FB STATE3 sreg FB STATE4 sreg FB STATE5 sreg FB STATE6 sreg FB STATE7 Sreg FB STATES sreg FB STATE9 sreg FB STATE10 sreg FB STATE11 db 57 sreg FB STATE12 sreg FB STATE13 sreg FB STATE14 sreg FB STATE15 sreg FB STATE16 sreg FB STATE17 sreg FB STATE18 sreg FB STATE19 db HH
22. 3 ZLY ZOV 4 19v 62105 dnm 22 84 197135 eec sir P 62105 031 MA a 22 LA eov vir P Jomod 82105 031 2 2 94 Jom0d gir 5 40151694 POJDA SJU esDejd 037 OUse xe UD dn 30 pesn 9524 suo ZIP SLP 939N eubjd GND 94 0 KjJDJIEKUA PUD sy SOBLWI 94 JO JUIS 1099 SUL 310N F AES 82 8 85 5 SS aw ___ ana aa oen LYA sa Zd 812608 1 NNO2 2Q 740129uu02 OG epi cud Jssn DU OG s DUJUUJ9 SUIDJUOD OSjD pJDOQ SUL 310N 48 i jo 9 19945 HOS Xd wou jj ADMHA Aq umpig 466 BL 493 UON apq 49quinN gt STI JO A IM Q io e 42 5 p 8 2 ZXNV Xnv 1 4171 mal gt gt sies 141 941 1 Te 49 el jo 4 19945 HOS Xd 9opjjeyu ojpny 23 5 og uo JOU 910 027 puo 6i 310 suadwunr ABV 52 34022 SE IZWSS
23. 5 STATE10 SV 20 ACK SV 12 ACK STATE16 SV 21 ACK STATE12 SV 14 ACK STATE18 SV 28 Page A0 RESET ISEL 8 WR RD STATE19 SV 26 Figure 8 1 State Diagram for PAL U3 62 APPENDIX RESTRICTIONS The following restrictions apply to release 2 0 of the ADSP 21061 EZ KIT Lite board For information on any ADSP 21061 silicon anomalies see the anomaly sheet that accompanied this product Breakpoints set in the last three instructions of a DO loop are allowed but cause your code to run incorrectly e Breakpoints set after a delayed branch instruction and before the branch occurs causes your code to run incorrectly mi e Using the single stepping function steps through a delayed branch instruction and the last three instructions of a DO loop host loses contact with the monitor while the user program is running if the user program disables the UART interrupt or changes the UART interrupt vector e host loses contact with the monitor while the program is running and in an ISR when nesting is turned off host loses contact with the monitor while the program is running and in the timer ISR provided the highest priority timer vector is used e This current version of the EZ KIT Lite software does not let you view hardware stack information Do not use the reset button while the debugger is open unless the debugger reques
24. ADSP 21061 EZ KIT Lite Reference Manual Part Number ADDS 21061 EZLITE Revision 2 0 May 2001 ANALOG DEVICES Notice Analog Devices Inc reserves the right to make changes to or to discontinue any product or service identified this publication without notice Analog Devices assumes no liability for Analog Devices applications assistance customer product design customer software performance or infringement of patents or services described herein In addition Analog Devices shall not be held liable for special collateral incidental or consequential damages in connection with or arising out of the furnishing performance or use of this product Analog Devices products are not intended for use in life support applications devices or systems Use of an Analog Devices product in such applications without the written consent of the Analog Devices officer is prohibited Users are restricted from copying modifying distributing reverse engineering and reverse assembling or reverse compiling the ADSP 21061 EZ KIT Lite operational software one copy may be made for back up purposes only No part of this document may be reproduced in any form without permission Trademarks and Service Mark Notice The Analog Devices logo ADSP 21061 SHARC the ADSP 21061 SHARC logo JTAG and EZ ICE are registered trademarks and EZ KIT Lite VisualDSP the VisualDSP logo TigerSHARC the TigerSHARC logo and the DSP Collaborative are tradem
25. al signal processor DSP The kit is shipped with an evaluation board and VisualDSP software The VisualDSP that comes with the kit will only operate with the evaluation board The complete version must be purchased separately Using the EZ KIT Lite with VisualDSP you can observe the ADSP 21061 DSP execute programs from on chip RAM interact with on board devices and communicate with other peripherals You can access the ADSP 21061 SHARC processor using a PC through a serial port or an optional JTAG In Circuit Emulator ICE The monitor program that runs on the EZ KIT Lite gives you access to the ADSP 21061 SHARC processor s internal memory space through the serial port By contrast the JTAG emulator allows the PC to perform in circuit emulation through the processor s JTAG interface The board s features include Analog Devices ADSP 21061 DSP running at 40 MHz Analog Devices AD1847 16 bit Stereo SoundPort codec e RS 232 interface Socketed EPROM User pushbuttons User programmable LEDs e Power supply regulation e Expansion connectors The EZ KIT Lite board is equipped with hardware that facilitates interactive demonstrations The pushbutton switches and user programmable LEDs provide user control and board status Additionally the AD1847 SoundPort codec provides access to an audio input selectable as line level or microphone and an audio output line level The board can run stand alone or can connect to t
26. arks of Analog Devices Inc Microsoft and Windows are registered trademarks and Windows NT is a trademark of Microsoft Corporation Adobe and Acrobat are trademarks of Adobe Systems Incorporated other brands and product names are trademarks or service marks of their respective owners Limited Warranty The ADSP 21061 EZ KIT Lite hardware is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer Copyright 2001 Analog Devices Inc All rights reserved Revision 2 0 May 2001 ADDS 21061 EZLITE ii TABLE OF CONTENTS LIST OF TABLES ABLE 2 1 PC MINIMUM CONFIGURATION ABLE 2 2 USER CONFIGURABLE EZ KIT LITE SETTINGS ABLE 2 3 SERIAL PORT PIN DESCRIPTIONS ABLE 3 1 FLAG SUMMARY ABLE 3 2 MEMORY MAP ABLE 3 3 RESTRICTED MEMORY SPACE ABLE 4 1 BANDPASS FILTER DEMO FILTER RANGES ABLE 4 2 BANDPASS FILTER DEMO SOURCE INPUTS ABLE 5 1 BOOT MODE SELECTION ABLE 5 2 EPROM JUMPER SELECTION CHART ABLE 6 1 SUMMARY OF EZ KIT ADSP 21061 SHARC PROCESSOR RESOURCES ABLE 8 1 ADSP 21061 EZ KIT LITE SCHEMATIC CONTENTS LIST OF FIGURES 1 INTRODUCTION 1 1 Introduction Thank you for purchasing the ADSP 21061 EZ KIT Lite evaluation kit The evaluation board is designed to be used in conjunction with the VisualDSP development environment and is based on the ADSP 21061 SHARC floating point digit
27. ater Pentium processor 166 MHz or faster Pentium processor 166 MHz or faster VGA Monitor and color video card VGA Monitor and color video card 2 button mouse 2 button mouse 100 MB available space 100 MB available space 32 MB RAM 32 MB RAM CD ROM CD ROM 2 4 VisualDSP ADSP 21061 EZ KIT Lite is shipped with the VisualDSP Integrated Development Environment IDE debugger and code generation tools VisualDSP is limited in functionality by the EZ KIT Lite serial number shipped with this product The EZ KIT Lite serial number restricts the VisualDSP debugger to connect only to the ADSP 21061 EZ KIT Lite evaluation board running the debug monitor via the serial port no emulation or simulation support Additionally the linker restricts you to only 2596 4k words of the ADSP 21061 SHARC processor s on chip program memory space If you purchase the full VisualDSP software suite you will obtain a new serial number from Analog Devices to lift the restrictions mentioned above The basic components that are shipped with VisualDSP are Integrated Development Environment IDE graphical interface for project management allowing you to set project options and access the code generation tools Debugger allows you to view the insides of the DSP and perform debug operations such as read write memory read write registers load programs run step halt and more SHARC Family Code Generation Tools C C compiler assem
28. back 3 2 1 2 External Interrupts The ADSP 21061 SHARC DSP has three external interrupt pins They are prioritized individually maskable IMASK register and can be configured to be edge sensitive or level sensitive bits in the MODE2 register At reset all external interrupts are level sensitive and masked Other relevant ADSP 21061 SHARC DSP registers are MODEI NESTM and IRPTEN bits IRPTL and IMASKP Two of the ADSP 21061 SHARC DSP s three external interrupt inputs are allocated on the ADSP 21061 EZ KIT Lite IRQO is not connected to any devices on the ADSP 21061 EZ KIT Lite however it is connected to one of the expansion connectors IRQI is connected to a pushbutton switch on the ADSP 21061 EZ KIT Lite board Pressing the pushbutton generates the interrupt IRQ2 is connected to the 16550 UART which can be programmed to generate an interrupt when it requires attention 19 3 2 1 3 Serial Ports The ADSP 21061 SHARC processor has two high speed synchronous serial ports SPORTS They can operate in point to point connection in full duplex mode with independent transmit and receive data lines and clocks or they can be wired together with multiple SPORTS to operate in a time division multiplexed TDM mode SPORTO is connected to the serial port on the AD1847 SoundPort codec This port is configured for multi channel TDM operation SPORTI is not connected to any devices on the ADSP 21061 EZ KIT Lite however it is c
29. bler run time libraries and linker loader simulator and PROM splitter Example Projects Both VisualDSP and the ADSP 21061 EZ KIT Lite are shipped with example projects and and Assembly source code that demonstrate various features of the tools and the ADSP 21061 DSP 2 5 Installation Procedures The following procedures are provided for the safe and effective use of the ADSP 21061 EZ KIT Lite evaluation board Follow these instructions in the order presented to ensure correct operation of your software and hardware 13 2 5 1 Installing the EZ KIT Lite Hardware The ADSP 21061 EZ KIT Lite board is designed to run outside the PC as a stand alone unit There is no need to remove the chassis from your computer To connect the EZ KIT Lite board 1 Remove the EZ KIT Lite board from the package Be careful when handling the board to avoid the discharge of static electricity which may damage some components 2 Connect the RS 232 cable to an available COM Port on the PC and the ADSP 21061 EZ KIT Lite evaluation board 3 Plug the provided 9V power supply into a 120 Volt AC receptacle and plug the connector at the other end of the cable into P2 on the evaluation board The FLAG3 and FLAG2 LEDs will start to toggle The POWER LED remains on If the LEDs do not light up check the power connections If you plug a pair of self powered computer speakers into the Jack J22 Output on the board you will be able to hear a tun
30. ceived from the UART the command processing kernel verifies whether a full command has been received If a command has been received the kernel processes the command otherwise control is returned to the halt loop to wait for more characters The only method of executing your code once the halt loop has been entered is to send a Run or Single Step command in the debugger The UART ISR is entered when user code 15 running but the host is still interacting with the board As the host sends bytes the UART ISR takes the data stream from the UART and builds the command Similar to the halt loop each character received is passed to the command processing kernel Unlike the halt loop the monitor returns to the user code immediately after the interrupt 1s serviced Be aware of the following restrictions to ensure correct board operation e f the user program disables the UART interrupt or changes the UART interrupt vector the host loses contact with the monitor while the user program is running 2 When nesting is turned off the host loses contact with the monitor while the program is running and in an ISR The host loses contact with the monitor while the program is running and in the timer ISR provided the highest priority timer vector is used The host cannot halt with the debugger s Debug Halt command if global IRQ enable 15 disabled IRPTEN bit however breakpoints work Command processing initiated from either the UART
31. demo is also contained in the boot PROM and executes when the power is first applied or when you press and release the RESET button The assembly source code for this program is located in the Program Files Analog Devices VisualDSP 21k EZ KITs ADSP 21061 Demos gunn directory 31 4 4 4 Blink Demo This simple program demonstrates how to use the ADSP 21061 SHARC processor s built in timer to toggle two LEDs on the EZ KIT Lite board The C source code for this program is located in the Program Files Analog Devices VisualDSP 2 1 k EZ KITs ADSP 21061 Demos blink directory 32 5 WORKING WITH EZ KIT LITE HARDWARE 5 1 Overview This chapter describes the hardware characteristics of the ADSP 21061 EZ KIT Lite board It includes a description of the board s major features and section that describes the user configurable items 5 2 Board Layout Figure 5 1 shows the layout of the ADSP 21061 EZ KIT Lite board which consists of a printed circuit board measuring 4 5 inches by 6 5 inches Figure 5 1 highlights the locations of the major components described in the following sections U4 PC16550D UART 2245 SHARC Processor Flag Input Switch EZ KIT LITE 7 ag Input Switci Power LED and User LEDs ADSP 21061 Digital Signal PROM 52 Processor NR Interrupt Switch S3 Reset 06 DEVICES Reset Switch Figure 5 1 Major Components of the ADSP 21061 EZ KIT Lite Rev 2 B
32. e To configure your board to take advantage of the audio capabilities of the demos 1 Plug a set of self powered computer speakers into Jack J22 on the board Turn on the speakers and set the volume to an adequate level 2 Connect the line out of an electronic audio device to Jack J23 Input on the board Set jumpers JP6 and to LINE This completes the hardware installation 2 5 2 Installing VisualDSP The EZ KIT Lite includes the latest evaluation version of VisualDSP for the ADSP 21061 SHARC DSP Family You must install this software prior to installing the EZ KIT Lite software Insert the VisualDSP CD ROM into the CD ROM drive This will bring up the CD browser Click on the Install VisualDSP option This will launch the setup wizard Follow this wizard with the on screen instructions 14 2 5 3 Installing the EZ KIT Lite License Before the VisualDSP software can be used you must install the license software To install the EZ KIT Lite license software follow these steps 1 VisualDSP has been installed 2 Insert the VisualDSP CD ROM into the CD ROM drive if it is not already in the drive 3 Once the browser appears select the Install License option 4 Follow the setup wizard instructions NOTE Ensure that you have the proper serial number which is located on the back of the CD sleeve 2 5 4 Installing the EZ KIT Lite Software The EZ KIT Lite utility software is supplied on a
33. e Sets up the baud rate of the current COM port and UART Choices are 9600 19200 38400 57600 and 115200 The default rate is 115200 Once change is made resetting is not needed for subsequent debug sessions NOTE Using a baud rate of 9600 causes the ADSP 21061 EZ KIT Lite to operate very slowly and can also cause it to hang 7 2 3 COM Port Selects a PC communications port for the ADSP 21061 EZ KIT Lite board Choices are COM 1 4 When changing the COM port it takes a second for the window to become active again 42 8 SCHEMATICS 8 1 Overview This chapter provides the design information used to build the ADSP 21061 EZ KIT Lite board The schematics are in section 8 2 The logic equations and state diagram for the 16V8 programmable logic device U3 are listed in section 8 3 8 2 Board Schematics The following pages provide complete electrical schematics for the ADSP 21061 EZ KIT Lite Rev 2 0 board Table 8 1 ADSP 21061 EZ KIT Lite Schematic Contents mr SHARC Processor Switches amp JTAG Header 2221 4 Clock Buffer UART amp UART Logic EG ko Jmdome MEE 3 5 Audio Interface puemuComeom Ps Link amp SPORT Termination External ADSP 21061 SHARC Signal Connectors HE EN 11 Resistor Pull ups poops s 48 9 50 51 52 53 55 56 57 58 43 399005 HIS xd SWDUSJIJ SJOMME q 4661 l 493 spa 40869901 2uVHS 49quinN Z3 OUVHS
34. e instructions of a DO loop e VisualDSP automatically inserts breakpoints at the function Main and at the exit instruction when the Settings gt Run To Main command is selected 4 3 4 Resetting the EZ KIT Lite Board You can reset the EZ KIT Lite board with the pushbutton switch on the board or with the Debug gt Reset command in VisualDSP Both methods clear and reset the chip s memory and debug information so you will need to reload any programs that were running The Debug gt Restart command resets the processor however the processor retains all debug information and memory contents e Do not use the reset pushbutton while the debugger is open unless the debugger requests you to press it 27 NOTE Ifa message in the VisualDSP debugger Output window requests you to reset board you must do the following to ensure proper download of the monitor from the PC 1 From Session menu choose Select Session 2 Select your Monitor Debug session 3 Follow on screen dialog boxes 4 4 Demonstration Program As described in the previous sections you can start the included EZ KIT Lite demonstration programs from the File menu or from toolbar buttons Each of the following sections describes what the demonstration programs do and how to run them 4 4 1 Bandpass Filter Demo This program demonstrates the effect of four bandpass filters against no filter on a codec input source or an internally generated noise source This
35. e limitations as MSO 5 larger than 128K x 8 have restricted access to their data below address 0x020000 and their data aliases to other memory locations The user program can access this data from these other locations 23 Table 3 3 shows currently used memory locations on the EZ KIT Lite board by the monitor You may not use these locations in programs Table 3 3 Restricted Memory Space Segment Description Memory Width Start End Name Block Address Address seg newrth Routine that 48 0x21974 0x21992 will overwrite old monitor s run time header rth with one from the new Monitor rsvd rth Run time 48 0x21993 0x21a12 header for new Monitor 8 seg post POST routine 4 0 21 13 0 21 52 of the Monitor seg rd Code o fas eg rsvd pmda PM Data of the 48 0x21dal 0 21 Monitor seg rsvd dmda DM Data of the 1 32 0x27ffd 0x27fff Monitor NOTE In order for your program to work properly your program must not overwrite any seg 5 memory location utilized by the monitor 24 4 DEMONSTRATION PROGRAMS 4 1 Overview This chapter describes how to load and run the demonstration programs supplied with the ADSP 21061 EZ KIT Lite board The demos are designed to run on the VisualDSP debugger supplied on a CD ROM that shipped with this product For detailed information on the debugger features and operation see the VisualDSP Debugger Guide amp Reference
36. ers Figure l 1 ADSP 21061 EZ KIT Lite Svstem Block Diagram In circuit emulation is achieved with a JTAG probe connected to the JTAG port The AD1847 SoundPort Stereo codec is accessed through a serial port that connects directly to the ADSP 21061 SHARC processor The ADSP 21061 EZ KIT Lite board has several sites for connectors allowing you to expand the board s capabilities These sites are not populated with connectors when you receive the board from Analog Devices 1 3 For More Information About Analog Devices Inc Products Analog Devices is accessible on the Internet at The DSP web page is directly accessible at www analog comydsp This page provides access to DSP specific technical information and documentation product overviews and product announcements 1 4 For Technical Customer Support You can reach our Customer Support group in the following ways Email questions to isptools support Qanalog com 1 5 Purpose of this Manual This manual shows how to install the evaluation board and software on the PC Also the manual provides guidelines for running user code on the ADSP 21061 SHARC processor 1 6 Intended Audience DSP programmers who are familiar with Analog Devices DSPs are the primary audience for this manual This manual assumes that the audience has a working knowledge of Analog Devices DSP architecture and DSP instruction set DSP programmers who are unfamiliar with Analog Devices DSPs ca
37. fines memory segments that are compatible with programs you write for the C C compiler and the assembler 6 2 1 2 Multiprocessor Memory Space The multiprocessor memory space MMS is consumed by ADSP 21061 SHARC processors connected to the external processor bus up to six as defined by the maximum cluster size ADSP 21061 SHARC processors appear in specific portions of the MMS according to their multiprocessor ID The default multiprocessor ID 1s one 001 for the ADSP 21061 SHARC processor You can change the ID to zero 000 with a jumper setting see section Since the ADSP 21061 EZ KIT Lite is a single processor board the only way to view other ADSP 21061 SHARC processors through the MMS is through the expansion connectors to your custom hardware 6 2 2 Stereo Audio Codec Programming The stereo audio interface built into the ADSP 21061 EZ KIT Lite is based on the AD1847 Stereo SoundPort codec You can find detailed programming information in the AD1847 data sheet The ADSP 21061 EZ KIT Lite uses SPORTO to communicate with the AD1847 s control and data interface The ADSP 21061 SHARC processor s FLAGO port controls the AD1847 s RESET and BM pins You can disable the codec by clearing FLAGO to zero 6 2 3 Kernel Compatibility When you write programs that run on the EZ KIT Lite board s ADSP 21061 SHARC processor there are certain programming restrictions you should consider to ensure that the on board kernel program continues t
38. he RS 232 port of the PC The EZ KIT Lite includes a monitor program stored on the original boot EPROM The monitor program lets you download execute and debug ADSP 21061 EZ KIT Lite programs By removing the socketed EPROM and replacing it with an EPROM containing code the board can run as a stand alone unit You can also connect an optional JTAG emulator to the ADSP 21061 EZ KIT Lite The emulator allows you to load programs start and stop program execution observe and alter registers and memory and perform other debugging operations JTAG emulators are available from Analog Devices and other third party resellers 1 2 EZ KIT Lite System Architecture Figure 1 1 is a block diagram of the ADSP 21061 EZ KIT Lite system You can access the ADSP 21061 SHARC processor from the PC through the RS 232 interface The boot PROM provides when the ADSP 21061 EZ KIT Lite is operating in stand alone mode and loads a kernel that manages the RS 232 interface Pushbutton Switches Flag Flag LEDs Power LED Power Connector l4 O Line in Stereo 4 MIC in Stereo Emulator Connector i External Link Connectors I funpopulated External Link Ports 2 External Processor pi Serial Port 1 ma 1 Connector 1 1 I Expansion Connector K 1 unpopulated l unpopulated Asvnchronous Serial Port Connector RS 232 Driv
39. he different I O devices on the ADSP 21061 EZ KIT Lite These are flags external interrupts and serial ports 3 24 1 Flags The ADSP 21061 SHARC processor has four I O flags that you can program as inputs or outputs Bits in the MODE2 register control the direction At reset all of the flags are configured as inputs Bits in the ASTAT register contain the value of each of the flag pins FLAGO controls the pin on the AD1847 codec Clearing FLAGO 0 holds the AD1847 in reset Setting FLAGO 1 releases RESET and restarts the AD1847 The programmer should configure FLAGO as an output and set high during program initialization FLAGO 15 also connected to LED D2 on the ADSP 21061 EZ KIT Lite LED D2 is lit when FLAGO is cleared 18 FLAG is connected to the pushbutton switch labeled FLAG1 SI and to LED D3 The programmer should configure FLAGI as an input during program initialization The DSP s FLAGI input value 15 0 and LED D3 will light when the pushbutton is depressed and the value is 1 when the pushbutton is released FLAG2 is connected to LED D4 The programmer should configure FLAG2 as an output during program initialization The LED D4 lights while FLAG2 is zero FLAG3 is connected to LED D6 The programmer should configure FLAG3 as an output during program initialization The LED D6 lights while FLAG3 is zero Table 3 1 Flag Summary FLAG USE FLAGI Pushbutton Input FLAGO 2 and 3 LED Feed
40. ical Support s tede de 9 Test 42 Test Communications command 42 Transmitted Loop 20 U dense gend en 38 UART Check Initialization 20 Internal Loop 20 register WiTlte ue nente s 20 UARTISR niese th hene 21 V VISUADSP ene NG 13 VisualDSP Debugger Starting 25 VisualDSP Installation 14 W Web page amp 65
41. n use this manual but should supplement this manual with the ADSP 2106x User s Manual and the VisualDSP tools manuals 1 7 Manual Contents Description This manual contains the following information Chapter 1 Introduction Provides manual overview and Analog Devices contact information Chapter 2 Getting Started Provides information needed to install the software and the ADSP 21061 EZ KIT Lite evaluation board Chapter 3 Using EZ KIT Lite Software Provides monitor level software information on how the EZ KIT Lite board operates with the installed software Chapter 4 Demonstration Programs Describes loading and running the demonstration programs supplied with the ADSP 21061 EZ KIT Lite board Chapter 5 Working with EZ KIT Lite Hardware Describes the hardware characteristics of the ADSP 21061 EZ KIT Lite board Chapter 6 Programming Reference Provides technical details needed when writing programs for the ADSP 21061 EZ KIT Lite Chapter 7 Reference This is a reference for VisualDSP and provides information on all of the menu selections commands and dialog boxes when the target is the ADSP 21061 EZ KIT Lite evaluation board Chapter 8 Schematics Provides design information used to build the ADSP 21061 EZ KIT Lite board APPENDIX Restrictions Provides restrictions that apply to release 2 0 of the ADSP 21061 EZ KIT Lite board 1 8 Documentation and Related Products For more info
42. o install your software and the ADSP 21061 EZ KIT Lite evaluation board Install your software and hardware in the order presented for correct operation This chapter also provides basic board information 2 2 Contents of Your EZ KIT Lite Package Your ADSP 21061 EZ KIT Lite should contain the following items If any item 18 missing contact the vendor from whom you purchased your EZ KIT Late The evaluation board contains ESD electrostatic discharge sensitive devices Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high energy DEVICE discharges Proper ESD precautions are recommended to avoid performance degradation or loss of functionality Unused boards should be stored in the protective shipping package ADSP 21061 EZ KIT Lite board e Power cable with 9V DC power supply e O pin RS 232 serial port cable e CD ROM containing EZ KIT Lite target dll files examples Help file and utilities e CD ROM with VisualDSP e CD ROM DSP Designer s Reference containing DSP documentation 2 3 PC Configuration For correct operation of the VisualDSP software and EZ KIT Lite demos your computer must have the minimum configuration shown below 12 Table 2 1 PC Minimum Configuration indows 95 98 2000 Windows 95b Windows 98 or Windows 2000 Windows NT release 4 0 Service Pack 3 or l
43. o operate If you violate any of these restrictions the kernel may become disabled or unstable 40 Avoid using kernel memory regions The kernel uses two regions of the ADSP 21061 SHARC processor s internal SRAM These regions are defined as separate segments in the EZ KIT Lite s Linker Description File 146 Avoid the UART Since the kernel uses the RS 232 interface to communicate with the host computer it must manage the UART chip The UART is accessed in external memory space within external memory bank 1 see Table 6 1 Your program can freely change the MSIZE setting in the SYSCON register potentially changing the base address of external memory bank 1 since the kernel recalculates the UART base address every time it needs to access the chip Do not interfere with the UART interrupt The kernel depends on the hardware interrupt signal IRQ2 to communicate with the UART There are several ways that your program can affect the kernel s ability to receive interrupts from the UART Do not disable interrupts globally or disable interrupt nesting Bit 12 IRPTEN and Bit 11 NESTM in the register must remain set Do not mask IRQ2 The IMASK register allows your program to enable or disable individual interrupts Bit 6 IRQ2I in the IMASK register must remain set Do not change IRQ2 s sensitivity The UART uses this interrupt signal to indicate multiple conditions If the kernel satisfies one condition there may be other
44. oard 5 2 1 ADSP 21061 SHARC Processor This is the ADSP 21061 SHARC processor which operates at 40 MHz The Pin 1 Index is located in the upper right corner 33 5 2 2 Boot PROM The boot PROM U7 provides 8 bit program storage that can be loaded by the ADSP 21061 SHARC processor at start up The socket mounted on this board is designed to accept EPROMs from 256K bits up to 8M bits Jumpers JP1 through JP4 provide the necessary adjustments required to accommodate the different sizes of EPROM When the ADSP 21061 SHARC processor is configured for PROM booting the first 256 instructions 1536 bytes are automatically loaded by the ADSP 21061 SHARC processor when reset is released The remaining program image must be loaded by the program that is installed in those first 256 instructions The Idr2 I k utility can do this for you Refer to the ADSP 2106x SHARC User s Manual for more information on program booting 5 2 3 User Pushbutton Switches For user input control there are eight pushbutton switches on the ADSP 21061 EZ KIT Lite board RESET FLAG 0 3 and IRQ 0 2 The RESET switch initiates a power on reset to the DSP There are no restrictions to when the switch can be used so do not press the switch unless you want a complete DSP reset The FLAGI switch toggles the status of a flag pin FLAGI to the DSP This lets you manually trigger the flag providing an event while executing software The IRQI switch sends
45. oard is shipped with two jumpers installed across Pins 7 amp 8 and 9 amp 10 Remove these jumpers before installing the JTAG probe When the JTAG probe is removed replace these jumpers to ensure that the ADSP 21061 SHARC processor initializes correctly on power up The proper power up sequence is 1 JTAG Emulator 2 ADSP 21061 EZ KIT Lite board 35 To remove power the sequence is 1 ADSP 21061 EZ KIT Lite board 2 JTAG Emulator Jumpers Figure 5 3 JTAG Connector with Jumpers Installed 5 3 Jumpers Figure 5 4 shows the locations of configuration jumpers on the ADSP 21061 EZ KIT Lite board These jumpers should be checked before using the board to ensure proper operation Each of the jumper selection blocks is described in the following sections __ 05 O ORDO X D EZ KIT LITE seringa 12 Input Source Selector EBOOT JP5 LBOOT JP6 OD ID JP7 S3 Reset CAMs DEVICES Boot Control EPROM Jumper Block Settings Jumper Block Figure 5 4 Location of Configuration Jumpers on the ADSP 21061 EZ KIT Lite Board Rev 2 0 36 5 3 1 Input Source Selector This pair of jumpers selects whether your input signal is standard line level or microphone level If you select microphone level the input signal is amplified before it is sampled by the AD1847 codec JP8 JOH IIL JP9 MIC Line
46. onnected to one of the expansion connectors 3 2 2 POST Routines POST Power On Self Test routines are a series of standard tests and initializations that the EZ KIT Lite performs on a power on reset 3 2 2 1 UART Check Initialization The UART check is performed in three stages Two of these stages are implemented in the POST The third is controlled by the host PC when it attempts to connect to the EZ KIT Lite These stages are Register Write This test confirms that the ADSP 21061 SHARC processor is capable of writing to and reading from a register in the UART Three patterns are written to and then read from a register in the UART and tested three patterns must be read back correctly to pass this test Internal Loop Back In this test 256 bytes are sent to and read from the UART This test checks the functionality of the UART connections from the ADSP 21061 SHARC processor up to and through the UART chip Transmitted Loop Back The last UART test is performed by the host after the POST is complete In this test the host sends the UART test protocol This protocol specifies the number of bytes that are transmitted to the EZ KIT Lite board and instructs the board to echo the byte stream back to the host This test determines whether the EZ KIT Lite board is set to the correct baud rate and verifies the external connections between the board and the host 20 On power up the EZ KIT Lite board defaults to a
47. resources as they are implemented on the EZ KIT Lite board Table 6 1 Summary of EZ KIT Lite ADSP 21061 SHARC Processor Resources MS Memory LAG IRQ Serial Port Select Expansion Connector LED D2 1847 Expansion Connector 1847 codec codec RESET 16550 UART From Pushbutton From Pushbutton Expansion Connector LED D3 T p4 From 16550 UART LED D6 6 2 1 Memory Map The ADSP 21061 SHARC processor memory model defines three main memory spaces Internal memory space addresses an ADSP 21061 SHARC processor s on chip dual ported SRAM Multiprocessor memory space addresses the on chip SRAM of other ADSP 21061 SHARC processors in the same cluster 1 e ADSP 21061 SHARC processors that share a common processor bus External memory space addresses other devices on the shared bus such as SRAM or DRAM 39 6 2 1 1 Internal Memory Space Since the ADSP 21061 EZ KIT Lite has no external memory you must store all code instructions and data in the built in SRAM The ADSP 21061 SHARC processor has one megabit of internal dual ported SRAM divided into two 512 kilobit blocks The blocks are designed so that you can configure regions of memory to be either 32 or 48 bits wide The ADSP 2106X SHARC User s Manual contains detailed information about the configuration and limitations of this on chip SRAM If you are writing programs to be loaded by the built in kernel you should be aware of how it uses memory The ldf file for the EZ KIT Lite de
48. rmation on the ADSP 21061 SHARC processor and the components of the ADSP 21061 EZ KIT Lite system see the following documents ADSP 21061 SHARC Processor Data Sheet ADSP 2106x SHARC User s Manual AD1847 Serial Port 16 Bit SoundPort Stereo Codec Data Sheet PC16550D Universal Asynchronous Receiver Transmitter with FIFOs Data Sheet National Semiconductor The ADSP 21061 family of processors is supported by a complete set of evaluation tools Software tools include the C C compiler assembler run time libraries linker loader simulator and PROM splitter See the following documents VisualDSP Getting Started Guide VisualDSP User s Guide for the ADSP 21xxx Family DSPs Assembler Manual for the ADSP 2 Ixxx Family DSPs C C Compiler amp Library Manual for the ADSP 21xxx Family DSPs Linker amp Utilities for the ADSP 21xxx Family DSPs Product Bulletin for the VisualDSP and the ADSP 21xxx Family DSPs 10 These documents found on the Analog Devices Technical Documentation web site at If you plan to use the EZ KIT Lite with the JTAG emulator refer to the documentation that accompanies the emulator Your software installation kit includes online Help as part of the Windows interface This Help file provides information about the ADSP 21061 EZ KIT Lite evaluation board and accompanying tools 11 2 GETTING STARTED 2 1 Overview This chapter provides you with the information you need t
49. s Filter Range 0x00000000 None 0x00000001 Pass 328 448 Hz 0x00000002 Pass 521 710 Hz 0x00000003 Pass 825 1125 Hz 0x00000004 Pass 1308 1783 Hz Hit run Note the filter will change To Change the source 1 2 From the Memory menu choose Two Column two column window appears Right click inside the Memory window and click Go To From the Go To Address dialog box click on Browse From the Browse Symbol dialog box double click on the symbol source In the Memory window you will now be at the address for the filter 29 Data DM Hexadecimal 024026 024027 024028 024029 02402C 02402F lu source 00000000 xmit ptr 00000000 xmit count 00000000 cmd blk x 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 rx buf Figure 4 5 Memory Window for Symbol Source The address that source represents is right under the symbol name In this case it is address 0x24026 Change the value at this location to Table 4 2 Bandpass Filter Demo Source Inputs Value Source Address Source 0x00000000 codec 0x00000001 Noise When you change the source to Noise the ADSP 21061 SHARC processor supplies a fabricated noise source Hit run NOTE Changes will occur The C source code for this program is located in the Program Files Analog Devices VisualDSP 21k EZ KITs ADSP 21061 Demos Bp directory NOTE
50. sed to supply DC voltages to the ADSP 21061 EZ KIT Lite board The DC power supply included with your board mates directly to this connector 17 3 USING THE EZ KIT LITE SOFTWARE 3 1 Overview The combination of the EZ KIT Lite board and the monitor software operate as a target for the VisualDSP debugger The debugger allows you to view the processor registers and memory and perform several debugging activities such as setting breakpoints stepping through code and plotting a range of memory If VisualDSP is not installed install it from the VisualDSP CD ROM that came with this product For more information refer to Chapter 2 section VisualDSP This chapter provides monitor level software information on how the EZ KIT Lite board operates with the installed software This chapter also provides information to help you run your own programs on the ADSP 21061 EZ KIT Lite board This information appears in the following sections e Standard Operation Describes the operation of the EZ KIT Lite board e Running You Own Programs Provides information about writing and running your own DSP executables that link with the monitor program to run on the EZ KIT Lite board 3 2 Standard Operation This section covers the standard operation of the EZ KIT Lite board It describes the I O capabilities of the on board components board power up and the on board monitor program 3 2 1 Devices This section describes t
51. ts you to This will cause the debugger to crash e The IMDWO bit in the SYSCON register must be set to I to keep communication with the host The IMDWO bit determines if data accesses made to block 0 are 48 bit three column accesses 1 or 32 bit two column accesses 0 The monitor program requires three column data accesses to memory block 0 If The IMDWO bit is set to 0 the monitor accesses incorrect memory locations within block 0 See ADSP 2106x User s Manual for further discussion of IMDWO e setting of IMDWO will have no effect on C programming as long as RND32 is not set for 40 bit floating point precision e Do not run more than one ADSP 21061 EZ KIT Lite session in the debugger at any one time You may run an EZ KIT Lite session and a simulator or ICE session at the same time or you can open two debugger interfaces to run more than one EZ KIT Lite session e User should not remove files 61 kernelformatDM32 hex and 61 kernelformatDM32 hex from their current location otherwise the new monitor will not be download to the target If this occurs there will no communication between the target board and the host 63 ADISAJS 38 Architecture EZ KIT Lite System 8 Audio Interface 43 B Baud Rate command 42 Board Layo t soeces geniin 33 Board Schematics sess 43 Boot Control Jumper Block 37 Boot
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