PC755BM8 [Preliminary]
Contents
1. Table 6 2 COP Pin Definitions Pins Signal Connection Special Notes 1 TDO TDO 2 QACK QACK App 2K pull down to ground Must be merged with on board QACK if any 3 TDI TDI 4 TRST TRST eu to ground Must be merged with on board QACK if any 5 RUN STOP No connect Used on 604e leave no connect for all other processors 6 VDD SENSE VDD App 2K pull up to OVpp for short circuit limiting protection only 7 TCK TCK 85 analyzerof 9 TMS TMS 10 N A 11 SRESET SRESET Merge with on board SRESET if any 12 N A 13 HRESET HRESET Merge with on board HRESET 14 N A Key location pin should be removed 15 CKSTP OUT CKSTP OUT App 10K pull up to OVDD 16 Ground Digital Ground Boundary scan testing is enabled through the JTAG interface signals The TRST signal is optional in the IEEE 1149 1 specification but is provided on all Power Architecture implementations While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals more reliable power on reset performance will be obtained if the TRST signal is asserted during power on reset Since the JTAG interface is also used for accessing the common on chip processor COP function of Power Architecture processors simply tying TRST to HRESET isn t practical The common on chip processor COP function of Power Architecture processors allows a remote com pute2. OOOOCGCOOOCOOGCOOQOCQ0 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary Table 5 1 Package Pinout Listing Signal Name Pin Number Active yo 2090 3 3 0 A 0 31 C16 4 013 F2 014 G1 015 22 D16 04 E13 G2 E15 H1 E16 H2 F13 J1 High IO _ F14 J2 F15 H3 F16 G13 K1 G15 K2 H16 1 J15 P1 L2 Low Input ABB K4 Low AP 0 3 C1 B4 B3 B2 High ARTRY J4 Low AVpp A10 2 0V 2 0V BG L1 Low Input BR B6 Low Output BVSEL OX6 B1 High Input GND 3 3V E1 Low Output CKSTP IN D8 Low Input CKSTP OUT A6 Low Output CLK OUT D7 Output DBB J14 Low DBG N1 Low Input DBDIS H15 Low Input DBWO G4 Low Input 2 1 sod DP 0 7 M2 L3 N2 L4 R1 P2 M4 R2 High DRTRY G16 Low Input GBL F1 Low C5 C12 E3 E6 E8 E9 E11 E14 F5 F7 F10 F12 G6 G8 G9 G11 H5 H7 GND H10 H12 J5 47 J10 J12 K6 K8 K9 K11 L5 L7 L10 L12 M3 M6 9 GND GND M11 M14 P5 P12 HRESET A7 Low Input INT B15 Low Input L1 TSTCLK D11 High Input L2 TSTCLK D12 High Input L2AVpp L11 2 0V 2 0V L20vpp 9 E10 E12 M12 G12 G14 K12 14 2 0V 3 3V L2VSEL 6X9 B5 High Input 12 3 3V LSSD MODE B10 Low I
3. Table3 1 Absolute Maximum Ratings Characteristic Symbol Maximum Value Unit Core supply voltage 0 3 to 2 5 V PLL supply voltage AVpp 0 3 to 2 5 V L2 DLL supply voltage L2AVpp 0 3 to 2 5 V Processor bus supply voltage 0 3 to 3 465 V L2 bus supply voltage 2 0 3 to 3 465 V Input voltage Processor bus 0 3 to 0 3V V L2 Bus Vin 0 3 to L2OVpp 0 3V V JTAG Signals Vin 0 3 to 3 6 V Storage temperature range Tsta 65 to 150 Notes 1 Functional and tested operating conditions are given Table 3 2 Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage to the device 2 Caution must not exceed OVpp or L2OVpp by more than 0 3V at any time including during power on reset 3 Caution L2OVpp OVpp must not exceed Vpp AVpp L2AVpp by more than 1 6V during normal operation this limit may be exceeded for a maximum of 20 ms during power on reset and power down sequences 4 Caution Vpp AVpp L2AVpp must not exceed L2OVpp OVpp by more than 0 4V during normal operation this limit may be exceeded for a maximum of 20 ms during power on reset and power down sequences 5 Vin may overshoot undershoot to a voltage and for a maximum duration as shown in Figure 3 1 0882D HIREL 04 09 e2v semiconductors SAS 200
4. 755 8 Preliminary 3 4 Recommended Operating Conditions Table 3 3 Recommended Operating Conditions Recommended Value 300 MHz 350 MHz Characteristic Symbol Min Max Unit Core supply voltage Vpp 1 9 2 10 V PLL supply voltage AVpp 1 9 2 10 V L2 DLL supply voltage L2AVpp 1 9 2 10 V 2 375 2 625 V Processor bus supply voltage 99 BVSEL 1 OVpp 3 135 3 465 V L2 bus supply voltage 6 L2VSEL 1 L20Vpp 3 135 3 465 V Processor bus Vin GND OVpp V Input voltage L2 Bus Vin GND L20Vpp V JTAG Signals Vin GND OVpp V Military temperature range 55 125 C Die junction temperature Industrial temperature 40 110 Notes 1 These are the recommended and tested operating conditions Proper device operation outside of these conditions is not guaranteed Revisions prior to Rev 2 8 Rev E offered different I O voltage support 2 0V nominal 2 5V nominal O12 3 3V nominal 3 5 12 Cache Control Register L2CR The L2 cache control register shown in Figure 3 2 is a supervisor level implementation specific SPR used to configure and operate the L2 cache It is cleared by hard reset or power on reset Figure 3 2 12 Cache Control Register L2CR L2WT L2DF L2CS L2PE L2DO L2CTI L2TS L2SL L2BYP 1210 L2DRO L2IP IL em 8 1234 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 31 Reserved 10 0882D HIREL 04 09 e2v semiconductors S
5. lKHOV X TS ABB DBB lt tKHARPZ gt lt Dow 1 KHOX VM Midpoint Voltage OVpp 2 Vi 2 Figure 4 3 AC Test Load OUTPUT Zo 500 OVpp 2 Figure 4 4 Mode Input Timing Diagram HRESET MXRH MODE SIGNALS VM Midpoint Voltage OVpp 2 17 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 4 2 3 IEEE 1149 1 AC Timing Specifications Table 4 4 provides the IEEE 1149 1 JTAG AC timing specifications as defined in Figure 4 5 Figure 4 6 Figure 4 7 and Figure 4 8 Table 4 4 JTAG AC Timing Specifications Independent of SYSCLK Parameter Symbol Min Max Unit TCK Frequency of operation 0 16 MHz TCK Cycle time freik 62 5 ns TCK Clock pulse width measured at 1 4V 31 ns TCK Rise and fall times tjr amp tje 0 2 ns TRST Assert time tTRST 25 ns Input Setup Times Boundary scan data 4 ns TMS TDI 0 Input Hold Times Boundary scan data toxJH 15 ns TMS TDI tiun 12 Valid Times Boundary scan data 4 ns TDO tiov 4 Output Hold Times Boundary scan data 25 ns TDO tiov 12 to output high impedance 9 Boundary scan data 3 19 ns TDO 107 3 9 Notes 1 Alloutputs are measured from the midpoint voltage of the falling rising edge of TCLK to the
6. 90 1 010 1 5 011 Reserved 100 2 Setting for PC755BM8 101 2 5 110 3 111 Reserved L2 RAM type Configures the L2 RAM interface for the type of synchronous SRAMs used 7 8 L2RAM Pipelined register register synchronous burst SRAMs that clock addresses in and clock data out The 755 8 does not burst data into the L2 cache it generates an address for each access 10 Pipelined register register synchronous burst SRAM Setting for PC755BM8 L2 data only Setting this bit enables data only operation in the L2 cache For this operation instruction transactions from the 9 L2D0 L1 instruction cache already cached in the L2 cache can hit in the L2 but new instruction transactions from the L1 instruction cache are treated as cache inhibited bypass L2 cache L2 checking done When both L2DO and 1210 are set the L2 cache is effectively locked cache misses do not cause new entries to be allocated but write hits use the L2 10 121 L2 global invalidate Setting 121 invalidates the L2 cache globally by clearing the L2 bits including status bits This bit must not be set while the L2 cache is enabled See Freescale User s manual for L2 Invalidation procedure L2 RAM control ZZ enable Setting L2CTL enables the automatic operation of the L2ZZ low power mode signal for cache RAMs 11 L2CTL Sleep mode is supported by the PC755BM8 While L2CTL is asserted 1277 asserts automatically when the device enters nap or sleep
7. Processor CPU Frequency L2 Frequency 300 150 MHz 350 175 MHz Unit Full on Mode Typical 9 4 1 4 6 Maximum 6 7 7 9 Ww Doze Mode Maximum 2 5 2 8 Mode Maximum 1700 1800 mW Sleep Mode Maximum 1200 1300 mW Sleep Mode PLL and DLL Disabled Maximum 500 500 mW Notes 1 These values apply for all valid 60x bus and L2 bus ratios The values do not include OVpp AVpp and L2AVpp suppling power power is system dependent but is typically lt 10 of Vpp power Worst case power consumption for 15 mW and L2AVpp 15 mW 2 Maximum power is measured at 2 1V while running an entirely cache resident contrived sequence of instructions which keep the execution units maximally busy 3 Typical power is an average value measured at Vp L2AVpp 2 0V L2OVpp 3 3V in a system executing typical applications and benchmark sequences 13 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 4 Electrical Characteristics 4 1 Static Characteristics Table 4 1 DC Electrical Specifications at Recommended Operating Conditions see Table 3 3 Nominal Bus Characteristic Voltage Symbol Min Max Unit Input high voltage all inputs except 2 5 Vin 1 6 L2 0 3 V SYSLCK 3 3 2 L2 0 3 V Input low voltage all inputs except 2 5 0 3 0 6 V SYSLCK 3 3 Vs 0 3 0 8 v 2
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9. 2V PC755BM8 RISC Microprocessor Multichip Package Datasheet Preliminary Specification Features e PC755BMB8 RISC Miprocessor Dedicated 1 megabyte SSRAM L2 Cache Configured as 128K x 72 21 mm x 25 mm 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency 350 MHz Maximum L2 Cache Frequency 175 MHz Maximum 60x Bus Frequency 66 MHz Description The PC755BMB8 multichip package is targeted for high performance space sensitive low power systems and supports the following power management features doze nap sleep and dynamic power management The PC755BM8 is offered in industrial and military temperature ranges and is well suited for embedded applications Screening This product is manufactured in full compliance with CBGA Up Screenings Based on e2v Standards Full Military Temperature Range T 55 4125 Industrial Temperature Range T 40 C 110 C OO OOOO OOOOOOOOOOOOOOO0 OOOOO0O0O0O00O0000000 Visit our website www e2v com for the latest version of the datasheet e2v semiconductors SAS 2009 0882D HIREL 04 09 iminary 755 8 Prel Block Diagram 1 PC755BM8 Microprocessor Block Diagram Figure 1 1 sng z 110 79 SvZOd 24 JON spel 27 49 01 U0D 21 1no 1589 21 sng 21 sng 1 2114 21 _ sng
10. centered header assembly often called a Berg header The connector typically has pin 14 removed as a connector key as shown in Figure 6 5 8 Definitions 8 1 Life Support Applications These products are not designed for use in life support appliances devices or systems where malfunc tion of these products can reasonably be expected to result in personal injury e2v customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnity e2v for any damages resulting from such improper use or sale 9 Document Revision History Table 9 1 provides a revision history for this hardware specification Table 9 1 Document Revision History Rev No Date Substantive Change s N h from Atmel to e2 D 06 2007 amec ange io mel to e2v Ordering information update C 09 2005 Ordering information changed Motorola changed to Freescale 10 Ordering Information 7558 8 nnn L E Part Multichip Temperatura Bus divider Revision Range Ty i 1 Identifier Package 12 cache density Package Core frequency be confirmed Level 300 300 MHz 150 T 55 125 C L2 cache L Any valid 9 Mbits 128K x 72 SSRAM 4 40 C 110 C 350 350 MHz 175 MHz PLL configuration L2 cache Notes 1 Foravailability of the different versions contact your local e2v sales office 2 The letter X in the part number
11. 5 1 8 0 3 V SYSCLK input high voltage 3 3 2 4 0 3 V 2 5 0 3 0 4 V SYSCLK input low voltage 3 3 0 3 0 4 V Input leak t 99 nput leakage current ln _ 18 Vin L20Vppy OVpp Hi Z off state leakage current 290 Vin L20Vpy OVpp 2 5 1 7 V Output high voltage lop 6 mA 3 3 Vou 2 4 V 2 5 VoL 0 45 V Output low voltage Io 6 mA 3 3 VoL 0 4 V Capacitance OV f 1 MHz 9 5 pF Notes 1 Nominal voltages See Table 3 3 for recommended operating conditions 2 For processor bus signals the reference is OVpp while L2OV pp is the reference for the L2 bus signals 3 Excludes test signals LSSD MODE L1 TSTCLK L2 TSTCLK and IEEE 1149 1 boundary scan JTAG signals 4 Capacitance is periodically sampled rather than 100 tested 5 The leakage is measured for nominal OVpp and Vpp or both and Vpp must vary in the same direction for example both OVpp and Vpp vary by either 5 or 5 14 0882D HIREL 04 09 e2v semiconductors SAS 2009 4 2 Dynamic Characteristics 755 8 Preliminary After fabrication parts are sorted by maximum processor core frequency as shown in Table 4 2 and tested for conformance to the AC specifications for that frequency These specifications are for 275 300 333 MHz processor core frequencies The processor core frequency is determined by the bus SYSCLK frequency and the se
12. data cache dL 1 Cache locking for both instruction and data caches selectable by group of ways Single cycle cache access Pseudo least recently used PLRU replacement Copy back or Write through data cache on a page by page basis Supports all Power Architecture memory coherency modes Non blocking instruction and data cache one outstanding miss under hits No snooping of instruction cache Memory Management Unit 128 entry 2 way set associative instruction TLB 128 entry 2 way set associative data TLB Hardware reload for TLBs Hardware or optional software tablewalk support amp instruction BATs and 8 data BATs 8 SPRGs for assistance with software tablewalks Virtual memory support for up to 4 hexabytes 272 of virtual memory Real memory support for up to 4 gigabytes 232 of physical memory Bus Interface Compatible with 60X processor interface 32 bit address bus 64 bit data bus 32 bit mode selectable Bus to core frequency multipliers of 2x 3x 3 5x 4x 4 5x 5 5 5x 6x 6 5x 7x 7 5 8x 10x supported Selectable interface voltages of 2 5V and 3 3V Parity checking on both address and data buses 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary Power Management Low power design with thermal requirements very similar to PC740 750 Selectable interface voltage of 1 8V 2 0V can reduce power in output buff
13. designates a Prototype product that has not been qualified by e2v Reliability of a PCX part number is not guaranteed and such part number shall not be used in Flight Hardware Product changes may still occur while shipping prototypes 30 0882D HIREL 04 09 e2v semiconductors SAS 2009 e2v How to reach us Home page www e2v com Sales offices Europe Regional sales office e2v Itd 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel 44 0 1245 493493 Fax 44 0 1245 492492 mailto enquiries 9 e2v com e2v sas 16 Burospace F 91572 Bi vres Cedex France Tel 33 0 16019 5500 Fax 33 0 16019 5529 mailto enquiries fr 9 e2v com e2v gmbh IndustriestraBe 29 82194 Gr benzell Germany Tel 49 0 8142 41057 0 Fax 49 0 8142 284547 mailto enquiries de 9 e2v com Americas e2v inc 520 White Plains Road Suite 450 Tarrytown NY 10591 USA Tel 1 914 592 6050 or 1 800 342 5338 Fax 1 914 592 5148 mailto enquiries na e2v com Asia Pacific e2v Itd 11 F Onfem Tower 29 Wyndham Street Central Hong Kong Tel 852 3679 364 8 9 Fax 852 3583 1084 mailto enquiries ap 9 e2v com Product Contact e2v Avenue de Rochepleine BP 123 38521 Saint Egr ve Cedex France Tel 33 0 4 76 58 30 00 Hotline mailto std hotline 9 e2v com Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequence
14. enters or sleep modes and automatically restart when exiting those modes including for snooping during nap mode It operates by asynchronously gating off the L2CLK OUT A B signals while in nap or sleep mode The L2ESYNC_OUT SYNC_IN path remains in operation keeping the DLL synchronized This bit is provided as a power saving alternative to the L2CTL bit and its corresponding ZZ pin which may not be useful for dynamic stopping restarting of the L2 interface from nap and sleep modes due to the relatively long recovery time from ZZ negation that the SRAM requires 22 L2CS L2 DLL rollover Setting this bit enables a potential rollover or actual rollover condition of the DLL to cause a checkstop for the processor A potential rollover condition occurs when the DLL is selecting the last tap of the delay line and thus may risk rolling over to the first tap with one adjustment while in the process of keeping synchronized Such a condition is improper operation for the DLL and while this condition is not expected it allows detection for added security This bit should be set when the DLL is first enabled set with the L2CLK bits to detect rollover during initial synchronization It could also be set when the L2 cache is enabled with L2E bit after the DLL has achieved its initial lock 23 L2DRO L2 DLL counter read only These bits indicate the current value of the DLL counter 0 to 127 They are asynchronously read when the
15. mode and negates automatically when the device exits nap or sleep mode This bit should not be set when the device is in nap mode and snooping is to be performed through deassertion of QACK L2 write through Setting L2WT selects write through mode rather than the default write back mode so all writes to the L2 12 L2WT cache also write through to the 60x bus For these writes the L2 cache entry is always marked as exclusive rather than modified This bit must never be asserted after the L2 cache has been enabled as previously modified lines can get remarked as exclusive during normal operation L2 test support Setting L2TS causes cache block pushes from the L1 data cache that result from dcbf and debst instructions to be written only into the L2 cache and marked valid rather than being written only to the 60x bus and marked invalid in the L2 L2TS cache in case of hit This bit allows a dcbz dcbf instruction sequence to be used with the L1 cache enabled to easily initialize 13 2 the L2 cache with any address and data information This bit also keeps dcbz instructions from being broadcast on the 60x and single beat cacheable store misses in the L2 from being written to the 60x bus 0 Setting for the L2 Test Support as this bit is reserved for tests 14 15 L2OH L2 output hold These bits configure output hold time for address data and control signals driven to the L2 data RAMs 00 Least Hold Time Setting for PC755BM8
16. to the power supply that a low voltage processor is present This sig nal is not a power supply pin To allow for future voltage changes provide the option to connect BVSEL and L2VSEL independently to either OVpp Selects 3 3V Interface or to GND Selects 2 0V Interface Uses of 15 existing no connects in 755 8 Internal pull up on die supplies power to the processor bus JTAG and all control signals except the L2 cache controls L2CE L2WE and 1272 L2OVpp supplies power to the L2 cache interface L2ADDR 0 16 L2DATA 0 63 L2DP 0 7 and L2SYNC OUT and the L2 control signals and the SSRAM power supplies and supplies power to the processor core and the PLL and DLL after filtering to become AVpp and L2AVpp respectively These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL L2VSEL pin configurations and the voltage supplied For actual rec ommended value of or supply voltages see Recommended Operating Conditions 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 8 Uses one of 20 existing Vpp pins PC755BMB no board level design changes are necessary For new designs of PC755BM8 refer to PLL power supply filtering 9 L2OVpp for future designs that will require 2 OV L2 cache power supply compatible with existing design using PC755BM8 10 To disable SSRAM TAP controllers without interfering with the
17. 000000 123456 7 8910111213141516 0 975 0 038 REF 23 0 80 0 032 Notes 1 Dimensions in millimeters and paranthetically in inches 2 A1 corner is designated with a ball missing the array 23 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 5 3 Clock Selection The PC755BM8 s PLL is configured by PLL_CFG 0 3 signals For a given SYSCLK bus frequency the PLL configuration signals set the internal CPU and VCO frequency of operation The PLL configura tion for the PC755BM8 is shown in Figure 6 2 for an example of frequencies Table 5 3 PC755BM8 Microprocessor PLL Configuration Example Bus to Core Frequency in MHz VCO Frequency in MHz Bus to Core Core to VCO Bus 33 Bus 50 Bus 66 Bus 75 Bus 80 Bus 100 PLL CFG 0 3 Multiplier Multiplier MHz MHz MHz MHz MHz MHz 200 0100 2x 2x B 400 200 225 240 300 1000 2 400 450 480 600 233 263 280 350 TOM Mex zi 466 525 560 700 200 266 300 320 Ax xi 5 400 533 600 640 E 225 300 338 360 d ADX 450 600 675 720 250 333 1011 5x 2x 500 666 1001 5 5 2 em 550 200 300 1101 6 2 400 600 amp 216 325 0101 6 5x 2 433 650 233 350 0010 7 2 466 700 250 0001 7 5 2 500 266 1100 8 2 533 333 0110 10x 2x 666
18. 11 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary Table 3 4 L2CR Bit Settings Continued Bit Name Function L2 DLL slow Setting L2SL increases the delay of each tap of the DLL delay line It is intended to increase the delay through 16 L2SL the DLL to accommodate slower L2 RAM bus frequencies 0 Setting for PC755BM8 because L2 RAM interface is operated above 100 MHz L2 differential clock This mode supports the differential clock requirements of late write SRAMs 17 L2DF 0 Setting for PC755BM8 because late write SRAMs not used 18 L2BYP L2 BE bypass is reserved 0 Setting for PC755BM8 19 20 Reserved These bits are implemented but not used keep at 0 for future compatibility L2 instruction only Setting this bit enables instruction only operation in the L2 cache For this operation data transactions from the L1 data cache already cached in the L2 cache can hit in the L2 including writes but new data transactions 21 1210 transactions that miss in the L2 from the L1 data cache are treated as cache inhibited bypass L2 cache L2 checking done When both L2DO and 1210 set the L2 cache is effectively locked cache misses do not cause new entries to be allocated but write hits use the L2 Note that this bit can be programmed dynamically L2 clock stop Setting this bit causes the L2 clocks to the SRAMs to automatically stop whenever the MPC755
19. 9 755 8 Preliminary Figure 3 1 Overshoot Undershoot Voltage Gnd Exceed 10 EN of tSYSCLK The PC755BM8 provides several I O voltages to support both compatibility with existing systems and migration to future systems The PC755BM68 core voltage must always be provided at nominal 2 0V see Table 3 3 for actual recommended core voltage Voltage to the L2 I Os and Processor Interface I Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3 2 The input voltage threshold for each bus is selected by sampling the state of the voltage select pins BVSEL and L2VSEL during operation These signals must remain stable during part operation and can not change The output voltage will swing from GND to the maximum voltage applied to the OV or L2OV pp power pins Table 3 2 Input Threshold Voltage Setting Processor Bus L2 Bus Part Revision BVSEL Signal L2VSEL Signal nterface Voltage Interface Voltage 0 0 Not Available Not Available 0 1 Not Available 2 5V 3 3V 1 0 2 5V 3 3V Not Available 1 1 2 5V 3 3V 2 5V 3 3V Notes 1 The input threshold settings above are different for all revisions prior to Rev 2 8 Rev E For more infor mation contact your local e2v sales office 2 Caution The input threshold selection must agree with the OV L2OV voltages supplied 0882D HIREL 04 09 e2v semiconductors SAS 2009
20. AS 2009 755 8 Preliminary The L2CR bits are described Table 3 4 Table 3 4 L2CR Bit Settings Bit Name Function L2 enable Enables L2 cache operation including snooping starting with the next transaction the L2 cache unit receives 0 L2E Before enabling the L2 cache the L2 clock must be configured through L2CR 2CLK and the L2 DLL must stabilize All other L2CR bits must be set appropriately The L2 cache may need to be invalidated globally 1 LOPE L2 data parity generation and checking enable Enables parity generation and checking for the L2 data RAM interface When disabled generated parity is always zeros L2 Parity is supported by PC755BM8 but is dependent on application 2 3 12512 L2 size Should be set according to the size of the L2 data RAMs used 11 1 Mbyte Setting for PC755BM8 L2 clock ratio core to L2 frequency divider Specifies the clock divider ratio based at the core clock frequency that the L2 data RAM interface is to operate at When these bits are cleared the L2 clock is stopped and the on chip DLL for the L2 interface is disabled For nonzero values the processor generates the L2 clock and the on chip DLL is enabled After the L2 clock ratio is chosen the DLL must stabilize before the L2 interface can be enabled The resulting L2 clock frequency cannot be slower than the clock frequency of the 60x bus interface 000 L2 clock and DLL disabled 4 6
21. B 0011 PLL off bypass PLL off SYSCLK clocks core circuitry directly 1x bus to core implied 1111 PLL off PLL off no core clocking occurs Notes 1 PLL_CFG 0 3 settings not listed are reserved 2 The sample bus to core frequencies shown are for reference only Some PLL configurations may select bus core or VCO frequencies which not useful not supported or not tested for by the PC755BM8 See Clock AC Specifications on page 15 for valid SYSCLK core and VCO frequencies 3 In PLL bypass mode the SYSCLK input signal clocks the internal processor directly the PLL is disabled and the bus mode is set for 1 1 mode operation This mode is intended for factory use and emulator tool use only Note The AC timing specifications given in this document do not apply in PLL bypass mode 4 In PLL off mode no clocking occurs inside the PC755BM8 regardless of the SYSCLK input 24 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 6 System Design Information PLL Power Supply Filtering The AVpp L2AVpp power signals are provided on the 755 8 to provide power to the clock gen eration phase locked loop and L2 cache delay locked loop respectively To ensure stability of the internal clock the power supplied to the input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL A circuit similar to the one shown in Figure 6 2 using surface mou
22. L2CR is read and as such should be read at least twice with the same value in case the value is asynchronously 24 30 L2CTR caught in transition These bits are intended to provide observability of where in the 128 bit delay chain the DLL is at any given time Generally the DLL operation should be considered at risk if it is found to be within a couple of taps of its beginning or end point tap O or tap 128 31 L2IP L2 global invalidate in progress read only See the Freescale user s manual for L2 Invalidation procedure 3 6 Power consideration 3 6 1 Power management The PC755BM68 provides four power modes selectable by setting the appropriate control bits in the MSR and HIDO registers The four power modes are as follows Full power This is the default power state of the PC755BM8 The PC755BM8B is fully powered and the internal functional units operate at the full processor clock speed If the dynamic power management mode is enabled functional units that are idle will automatically enter a low power state without affecting performance software execution or external hardware e Doze All the functional units of the PC755BMB8 are disabled except for the time base decrementer registers and the bus snooping logic When the processor is in doze mode an external asynchronous interrupt a system management interrupt a decrementer exception a hard or soft reset or machine check brings the PC755BM8 into the full power
23. accordance with MIL PRF 38535 19 0882D HIREL 04 09 e2v semiconductors SAS 2009 5 2 20 Handling PC755BM6 Preliminary MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge Input protection devices have been designed in the chip to minimize the effect of static buildup However the following handling practices are recommended Devices should be handled on benches with conductive and grounded surfaces Ground test equipment tools and operator Do not handle devices by the leads Store devices in conductive foam or carriers Avoid use of plastic rubber or silk in MOS areas Maintain relative humidity above 50 percent if practical Figure 5 1 X Pin Assignments Ball assignments of the 255 CBGA package as viewed from the top surface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D U Z Zr ODOCLOODOCCOOOQDCQ QOOOOGOCCOOUCQOCUOOD QOOOOOOUOGOOCOGCUOQ OOOOOOOOOOOOOOOO OOOOOQOCCOOOQO0COODO OOOOOOOOOOOOOOOO OQOOOOODUOQOGOOCOOLQUO e QOOOQOQOOUDCOQUODOLCO Side profile of the package to indicate the direction of the top surface view Substrate Assembly View X Underfill Encapsulant
24. d be connected to HRESET to select NO DRTRY mode Three test pins also require pull up resistors 1000 1 These pins are L1 TSTCLK L2 TSTCLK LS8SD MODE These signals are for factory use only and must be pulled up to OVpp for normal machine operation In addition CKSTP OUT is an open drain style output that requires a pull up resistor 1 5 if it is used by the system During inactive periods on the bus the address and transfer attributes may not be driven by any master and may therefore float in the high impedance state for rel atively long periods of time Since the processor must continually monitor these signals for snooping this float condition may cause additional power draw by the input receivers on the processor or by other receivers in the system These signals can be pulled up through weak 10 pull up resistors by the System or may be otherwise driven by the system during inactive periods of the bus to avoid this addi tional power draw but address bus pull up resistors are not neccessary for proper device operation The snooped address and transfer attribute inputs are A 0 31 AP 0 3 TT 0 4 TBST and GBL 27 0882D HIREL 04 09 e2v semiconductors SAS 2009 6 3 28 755 8 Preliminary The data bus input receivers are normally turned off when no read operation is progress and there fore do not require pull up resistors on the bus Other data bus receivers in th
25. de shift rotate arithmetic logical Fixed Point Unit 2 FXU2 shift rotate arithmetic logical Single cycle arithmetic shifts rotates logical Multiply and divide support multi cycle Early out multiply Floating point Unit and a 32 entry FPR File Support for IEEE 754 standard single and double precision floating point arithmetic Hardware support for divide Hardware support for denormalized numbers Single entry reservation station Supports non IEEE mode for time critical operations System Unit Executes CR logical instructions and miscellaneous system instructions Special register transfer instructions 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary Load Store Unit One cycle load or store cache access byte half word word double word Effective address generation Hits under misses one outstanding miss Single cycle unaligned access within double word boundary Alignment zero padding sign extend for integer register file Floating point internal format conversion alignment normalization Sequencing for load store multiples and string operations Store gathering Cache and TLB instructions Big and Little endian byte addressing supported Misaligned Little endian supported Level 1 Cache structure 32K 32 bytes line 8 way set associative instruction cache iL 1 32K 32 bytes line 8 way set associative
26. e system however may require pull ups or that those signals be otherwise driven by the system during inactive periods by the system The data bus signals are DH 0 31 DL 0 31 and DP 0 7 If 32 bit data bus mode is selected the input receivers of the unused data and parity bits will be disabled and their outputs will drive logic zeros when they would otherwise normally be driven For this mode these pins do not require pull up resistors and should be left unconnected by the system to minimize possible output switching If address or data parity is not used by the system and the respective parity checking is disabled through HIDO the input receivers for those pins are disabled and those pins do not require pull up resistors and should be left unconnected by the system If all parity generation is disabled through HIDO then all parity checking should also be disabled through HIDO and all parity pins may be left unconnected by the system JTAG Configuration Signals Figure 6 4 Suggested TRST Connection 755 From Target D HRESET Board Sources RACK 5 eo ACK TRST 2k 2 COP Header St Figure 6 5 Connector Diagram TOP VIEW Pins 10 12 and 14 are no connects Pin 14 is not physically present 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary
27. ers compared to 3 3V Three static power saving modes doze nap and sleep Dynamic power management Testability LSSD scan design 1149 1 JTAG interface Integrated Thermal Management Assist Unit On chip thermal sensor and control logic Thermal Management Interrupt for software regulation of junction temperature 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 1 2 Signal Description Figure 1 2 PC755BM8 Microprocessor Signal Groups SSRAM 1 L20Vpp Ui L2pin DATA FT SBd L2pin DATA iHe DQb SBc SBb L2pin DATA gt DQc SBa SW L2pin DATA ADSP ADV L2 CLK OUT A gt SES L2WE e gt SGW L2CE o gt gt SE ADSC SE3 0 16 LBO ZZ n s A0 16 SSRAM 2 Tur PC755M8 Uo 20 0 16 FT SBd 5 SBb gt SGW SBa gt 5 1 SW L2CLK OUT B gt ADSP ADV L2pin DATA Gf DQa SE2 L2pin_DATA SP DQb ADSC L2pin_DATA DQc SE3 L2pin DATA ie DQd LBO G ZZ L2ZZ 4 A 0882D HIREL 04 09 e2v semiconductors SAS 2009 Figure 1 3 ADDRESS ARBITRATION ADDRESS START ADDRESS BUS TRANSFER ATTRIBUTE ADDRESS TERMINATION DATA ARBITRATION DATA TRANSFER DATA TERMINATION e2v semiconductors SAS 2009 755 8 Preliminary PC755BM8 Micr
28. int of the signal in question to the midpoint of the rising edge of the input SYSCLK All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question All output timings assume a purely resistive load see Figure 4 3 Input and output timings are measured at the pin time of flight delays must be added for trace lengths vias and connectors in the system 2 The symbology used for timing specifications herein follows the pattern of t ignaiy state reference state fOr inputs and Lireterence state signaly state for outputs For example symbolizes the time input signals reach the valid state V relative to the SYSCLK reference K going to the high H state or input setup time And tkov symbolizes the time from SYSCLK K going highs until outputs are valid V or output valid time Input hold time can be read as the time that the input signal I went invalid X with respect to the rising clock edge KH note the position of the reference and its state for inputs and output hold time can be read as the time from the rising edge KH until the output went invalid OX For additional explanation of AC timing specifications in Freescale Power Architecture microprocessors see the appli cation note Understanding AC Timing Specifications for Power Architecture Microprocessors 3 The setup and hold time is with respect to the rising edge of HRESET
29. midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 500 load See Figure 4 5 Time of flight delays must be added for trace lengths vias and connectors in the system TRST is an asynchronous level sensitive signal The setup time is for test purposes only Non JTAG signal input timing with respect to TCK Non JTAG signal output timing with respect to TCK Guaranteed by design and characterization Figure 4 5 ALTERNATE AC Test Load for the JTAG Interface OUTPUT Zo 500 OVpp 2 500 Figure 4 6 JTAG Clock Input Timing Diagram TCLK VM Midpoint Voltage OVpp 2 18 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary Figure 4 7 TRST Timing Diagram TRST di VM C4 lmnsr VM Midpoint Voltage OVpp 2 Figure 4 8 Boundary Scan Timing Diagram VM L iDXJH DATA INPUTS DATA VALID BOUNDARY DATA OUTPUTS gt BOUNDARY TPUT DATA VALID DATA OUTPUTS iid VM Midpoint Voltage OVpp 2 Figure 4 9 Test Access Port Timing Diagram TCK VM d XJH TDI TMS DATA VALID lt OUTPUT TDO ATA TDO OUTPUT DATA VALID N VM Midpoint Voltage OVpp 2 5 Preparation for Delivery 5 1 Packaging Microcircuits are prepared for delivery in
30. normal operation of the devices STCK should be tied low GND to prevent clocking the devices 11 STDI and STMS are internally pulled up and may be left unconnected Upon power up the SSRAM devices will come up in a reset state which will not interfere with the operation of the device 12 Not supported on this version Table 5 2 Package Description Package Outline 21x25 mm Interconnects 255 16 x 16 ball array less one Pitch 1 27 mm Maximum Module Height 3 90 mm Ball Diameter 0 8 mm Figure 5 2 Package Dimensions 255 Ball Grid Array TOP VIEW 4 2525090 pi A 0 152 0 006 gt A1 Corner MAX EDSN 3 14 0 024 gt MAX 4 gt 3 04 0 119 MAX 21 21 0 835 D MAX D D D D D Y D D 4 D BOTTOM VIEW b 19 05 0 750 D 2 975 0 117 B gt 1 27 0 050 REF 2221 BSC p T ooooooooooooo i D R 000000000000000 0000000000000000 N O000000000000000 M O0000000000000000 L 0000000000000000 0000000000000000 010101010101010 010101010101010 19 05 0 750 H BSC p 4 0 64 0 070 0000000000000000 0 025 0 003 0000000000000000 000000000000000 D 600006060000000000 gt lt 2 20 0 087 60000060000000000 MAX B 600006060000000000 0000000
31. nput MCP C13 Low Input NC No Connect C3 C6 D5 D6 H4 A4 A5 A2 A3 OVpp C7 E5 G3 G5 K5 P7 P10 E07 M05 M07 M10 21 e2v semiconductors SAS 2009 0882D HIREL 04 09 755 8 Preliminary Table 5 1 Package Pinout Listing Continued Signal Name Pin Number Active yo 2 0V 3 3v PLL CFG 0 3 A8 B9 A9 09 High Input 03 Low Input QREQ J3 Low Output RSRV D1 Low Output SMI A16 Low Input SRESET B14 Low Input STCK B7 Input STDI C8 Input STDO J16 Output STMS B8 Input SYSCLK C9 Input 14 Low Input TBEN C2 High Input TBST A14 Low TCK C11 High Input TDI A11 High Input TDO A12 High Output TEA H13 Low Input TLBISYNC C4 Low Input Tus B11 High Input TRST C10 Low Input TS J13 Low TSIZ 0 2 A13 D10 B12 High Output TT 0 4 B13 A15 B16 C14 C15 High o WT D2 Low Output F6 F8 F11 G7 G10 H6 H8 H9 H11 J6 J8 49 J11 K7 K10 L6 L8 L9 2 0V 2 0V VOLTDET F3 Low Output Notes 1 These are test signals for factory use only and must be pulled up to OVpp for normal machine operation 22 OV pp inputs supply power to the drivers and Vpp inputs supply power to the processor core Internally tied to GND in the BGA package to indicate
32. ns are made along the length of the part In addition it is recommended that there be several bulk storage capacitors distributed around the PCB feeding the Vpp L2OVpp and OV vplanes to enable quick recharging of the smaller chip capacitors These bulk capacitors should have a low ESR equivalent series resistance rating to ensure the quick response time necessary They should also be connected to the power and ground planes through two vias to minimize inductance Suggested bulk capacitors 100 330 pF AVX TPS tantalum or Sanyo OSCON Connection Recommendations To ensure reliable operation it is highly recommended to connect unused inputs to an appropriate signal level through a resistor Unused active low inputs should be tied to OVpp Unused active high inputs should be connected to GND All NC no connect signals must remain unconnected Power and ground connections must be made to all external L2OVpp and GND pins of the 755 8 Output Buffer DC Impedance The PC755BM8 60x and L2 I O drivers are characterized over process voltage and temperature To measure Zp an external resistor is connected from the chip pad to L2 OVpp or GND Then the value of each resistor is varied until the pad voltage is L2 OV 2 See Figure 6 3 The output impedance is the average of two components the resistances of the pull up and pull down devices When Data is held low SW2 is closed SW1 is open and Ry is trimmed
33. nt capacitors with minimum Effective Series Inductance ESL is recommended Consistent with the recommendations of Dr Howard Johnson in High Speed Digital Design A Handbook of Black Magic Prentice Hall 1993 multiple small capacitors of equal value are recommended over a single large value capacitor The circuit should be placed as close as possible to the AV pin to minimize noise coupled from nearby circuits An identical but separate circuit should be placed as close as possible to the L2AV pin It is often possible to route directly from the capacitors to the pin which is on the periphery of the 360 BGA footprint without the inductance of vias The L2AVpp pin be more difficult to route but is pro portionately less critical Figure 6 1 PLL Power Supply Filter Circuit 100 AVpp or L2AVpp 2 2 uF 2 2 UF Low ESL Surface Mount Capacitors GND Power Supply Voltage Sequencing The notes in Figure 6 3 contain cautions about the sequencing of the external bus voltages and core voltage of the PC755BM8 when they are different These cautions are necessary for the long term reli ability of the part If they are violated the ESD Electrostatic Discharge protection diodes will be forward biased and excessive current can flow through these diodes If the system power supply design does not control the voltage sequencing the circuit of Figure 6 3 can be added to meet these requirements The MUR420 Sch
34. onippy 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 11 Major Features This section summarizes features of the PC755BM8 s implementation of the Power Architecture Major features of the PC755BM8 are as follows Branch Processing Unit Four instructions fetched per clock One branch processed per cycle plus resolving 2 speculations Up to 1 speculative stream in execution 1 additional speculative stream in fetch 512 entry branch history table BHT for dynamic prediction 64 entry 4 way set associative Branch Target Instruction Cache BTIC for eliminating branch delay slots Dispatch Unit Full hardware detection of dependencies resolved in the execution units Dispatch two instructions to six independent units system branch load store fixed point unit 1 fixed point unit 2 floating point Serialization control predispatch postdispatch execution serialization Decode Register file access Forwarding control Partial instruction decode Completion 6 entry completion buffer Instruction tracking and peak completion of two instructions per cycle Completion of instructions in program order while supporting out of order instruction execution completion serialization and all instruction flow changes Fixed Point Units FXUs that share 32 GPRs for Integer Operands Fixed Point Unit 1 FXU1 multiply divi
35. oprocessor Signal Groups continued JTAG COP L2Vpp L2AVpp L2ADDR 16 0 Le VSEL L2DATA 0 63 L2 CACHE L2DP 0 7 ADDRESS DATA TS L2WE gt L2 CACHE A 0 31 L2CLK OUT A B CLOCK CONTROL L2SYNC OUT L2SYNC 1272 TT 0 4 INT TBST SMI icto INTERRUPTS TS1Z 0 2 MCP RESET GBL SRESET WT HRESET CI CKSTP IN CKSTP OUT PC755M8 RSRV PROCESSOR TLBISYNC STATUS AACK QREQ ARTRY QACK DBG SYSCLK DBWO PLL_CFG 0 3 CLOCK CLK OUT CONTROL TEST INTERFACE Factory Test VOLTDET 0882D HIREL 04 09 755 8 Preliminary 2 Detailed Specification 2 1 Scope This drawing describes the specific requirements for the PC755BMB8 microprocessor in compliance with e2v standard screening 3 Applicable Documents 1 In accordance with MIL STD 883 Test methods and procedures for electronics 2 n accordance with MIL PRF 38535 appendix A General specifications for microcircuits 3 1 Requirements 3 1 1 General The microcircuits are in accordance with the applicable documents and as specified herein 3 2 Design and Construction 3 2 1 Terminal Connections Depending on the package the terminal connections are shown in Table 5 1 Table 3 1 and Figure 1 2 3 3 Absolute Maximum Rating
36. ottky diodes of Figure 6 3 control the maximum potential difference between the external bus and core power supplies on power up and the 1N5820 diodes regulate the maximum potential differ ence on power down Figure 6 2 Example Voltage Sequencing Circuit 3 3V 2 0V MURS320 MURS320 N 1N5820 IN 1N5820 e2v semiconductors SAS 2009 25 0882D HIREL 04 09 6 2 1 6 2 2 6 2 3 26 755 8 Preliminary Decoupling Recommendations Due to the 755 8 dynamic power management feature large address and data buses and high operating frequencies the PC755BMB8 can generate transient power surges and high frequency noise in its power supply especially while driving large capacitive loads This noise must be prevented from reaching other components in the 755 8 system and the 755 8 itself requires a clean tightly regulated source of power Therefore it is recommended that the system designer place at least one decoupling capacitor at each OVpp and L2OV pp pin of the 755 8 It is also recommended that these decoupling capacitors receive their power from separate L2 OVpp and GND power planes the PCB utilizing short traces to minimize inductance These capacitors should have a value of 0 01 uF or 0 1 uF Only ceramic SMT surface mount technol capacitors should be used to minimize lead inductance preferably 0508 or 0603 orientations where connectio
37. r system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The COP interface connects primarily through the JTAG port of the processor with some additional status monitoring signals The COP port requires the ability to indepen dently assert HRESET or TRST in order to fully control the processor If the target system has independent reset sources such as voltage monitors watchdog timers power supply failures or push button switches then the COP reset signals must be merged into these signals with logic The arrangement shown in Figure 6 4 allows the COP to independently assert HRESET or TRST while insuring that the target can drive HRESET as well The pull down resistor on TRST ensures that the JTAG scan chain is initialized during power on if a JTAG interface cable is not attached if it is it is responsible for driving TRST when needed The COP header shown in Figure 6 5 adds many benefits breakpoints watchpoints register and mem ory examination modification and other standard debugger features are possible through this interface and can be as inexpensive as an unpopulated footprint for a header to be added when needed 29 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary 7 System design information The COP interface has a standard header for connection to the target system based on the 0 025 square post 0 100
38. s measured at 0 4V to 1 4V 3 Timing is guaranteed by design and characterization 4 This represents total input jitter short term and long term combined and is guaranteed by design 5 Relock timing is guaranteed by design and characterization PLL relock time is the maximum amount of time required for PLL lock after a stable Vpp and SYSCLK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep mode Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power on reset sequence Figure 4 1 SYSCLK Input Timing Diagram SYSCLK tsyscLk e2v semiconductors SAS 2009 VM Midpoint Voltage OVpp 2 0882D HIREL 04 09 15 4 2 2 Processor Bus AC Specifications 755 8 Preliminary Table 4 3 provides the processor bus AC timing specifications for the PC755BM8 as defined in Figure 4 2 and Figure 4 4 Table 4 3 Processor Bus Mode Selection AC Timing Specifications At AVpp 2 0V 100 mV 55 T lt 125 C OVpp 3 3V 165 mV OVpp 1 8V 100 mV and OVpp 2 0V 100 mV Symbols Speed Grades Parameter Min Max Unit Mode select input setup to HRESET 4 0 6 7 8 levecLk HRESET to mode select input holg 9 9 97 0 ns Notes 1 Allinput specifications are measured from the midpo
39. s of any use thereof and also reserves the right to change the specification of goods without notice e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein e2v semiconductors SAS 2009 0882D HIREL 04 09
40. see Figure 4 3 4 This specification is for configuration mode select only Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re lock time during the power on reset sequence 5 S the period of the external clock SYSCLK in nanoseconds ns The numbers given in this table must be multiplied by the period of SYSCLK to compute the actual time duration in nanoseconds of the parameter in question 6 Mode select signals are BVSEL L2VSEL PLL CFG 0 3 7 Guaranteed by design and characterization 8 Bus mode select pins must remain stable during operation Changing the logic states of BVSEL or L2VSEL during operation will cause the bus mode voltage selection to change Changing the logic states of the PLL_CFG pins during operation will cause the PLL division ratio selection to change Both of these conditions are considered outside the specification and are not supported Once HRESET is negated the states of the bus mode selection pins must remain stable 16 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary Figure 4 2 Input Output Timing Diagram lt tIVKH gt r mns lt tKHOE ALL OUTPUTS lt tkHov kHox lt tkHoz Except TS ABB ARTRY DBB lKHABPZ gt KHOZ gt tKHOX PIN am
41. state The PC755BM8 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input SYSCLK so a transition to the full power state takes only a few processor clock cycles 12 0882D HIREL 04 09 e2v semiconductors SAS 2009 755 8 Preliminary Nap The nap mode further reduces power consumption by disabling bus snooping leaving only the time base register and the PLL in a powered state The PC755BM8 returns to the full power state upon receipt of an external asynchronous interrupt a system management interrupt a decrementer exception a hard or soft reset or a machine check input MCP A return to full power state from a nap state takes only a few processor clock cycles When the processor is in nap mode if QACK is negated the processor is put in doze mode to support snooping Sleep Sleep mode minimizes power consumption by disabling all internal functional units after which external system logic may disable the PPL and SUSCLK Returning the PC755BM8 to the full power state requires the enabling of the PPL and SYSCLK followed by the assertion of an external asynchronous interrupt a system management interrupt a hard or soft reset or a machine check input MCP signal after the time required to relock the PPL 3 6 2 Power Dissipation Table 3 5 Power Consumption AVpp 2 0 0 1V OVpp 3 3V 5 Voc GND 0 Voc 0 ST 105
42. ttings of the PLL CFG 0 3 signals Parts are sold by maximum processor core frequency 4 2 1 Clock AC Specifications Table 4 2 provides the clock AC timing specifications as defined in Table 3 1 Table 4 2 Clock AC Timing Specifications at Recommended Operating Conditions See Table 3 3 Maximum Processor Core Frequency 300 MHz 350 MHz Characteristic Symbol Min Max Min Max Unit Processor frequency foore 200 300 200 350 MHz VCO frequency 400 600 400 700 MHz SYSCLK frequency fsvscik 25 100 25 100 MHz SYSCLK cycle time tevscik 10 40 10 40 ns SYSCLK rise and fall time 6 dus tkr amp 1 m 1 ns SYSCLK duty cycle measured at 2 40 60 40 60 SYSCLK jitter 150 150 ps Internal relock 0 100 100 us Notes 1 Caution The SYSCLK frequency and PLL_CFG 0 3 settings must be chosen such that the resulting SYSCLK bus frequency CPU core frequency and PLL VCO frequency do not exceed their respec tive maximum or minimum operating frequencies Refer to the PLL_CFG 0 3 signal description in Table 5 3 for valid PLL_CFG 0 3 settings 2 Rise and fall times measurements are now specified in terms of slew rates rather than time to account for selectable I O bus interface levels The minimum slew rate of 1V ns is equivalent to a 2 ns maximum rise fall time measured at 0 4V and 2 4V or a rise fall time of 1 n
43. until the voltage at the pad equals L2 OV5 2 Ry then becomes the resistance of the pull down devices When Data is held high SW1 is closed SW2 is open and Rp is trimmed until the voltage at the pad equals 12 2 Rp then becomes the resistance of the pull up devices NO TAG describes the driver impedance measurement circuit described above 0882D HIREL 04 09 e2v semiconductors SAS 2009 6 2 4 Figure 6 3 755 8 Preliminary Driver Impedance Measurement Circuit L2 OVpp L2 0Vpp RN SW2 Pad Data SW1 Hp OGND Table 6 1 summarizes the signal impedance results The driver impedance values were characterized at 0 C 65 and 105 C The impedance increases with junction temperature and is relatively unaffected by bus voltage Table 6 1 Impedance Characteristics Vpp 2 0V OVpp 3 3V 0 105 C Impedance Processor Bus L2 Bus Symbol Unit RN 25 36 25 36 26 39 26 39 2 Pull up Resistor Requirements The 755 8 requires pull up resistors 1 5 on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the processor or other bus masters These pins are TS ABB AACK ARTRY DBB DBWO TA TEA and DBDIS DRTRY should also be connected to a pull up resistor 1 5 if it will be used by the system otherwise this signal shoul
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