PMC66-SIO4BXR-SPI User`s Manual
Contents
1. EER 12 3 1 CLOCK sneer eoe ti ered EEE ott disent te bat ea iet eite ate diete celeste 12 3 2 CHIP SEDECTS aethere teet eim hee nete eie e nre e eine 12 3 3 SPRIWORD SIZE d hata els il tastes Santee A 12 3 4 MASTER SPI CONTROLLER SETUPS dee vesci terere e eee Rr eere ee pt e tude cere ri 13 3 5 SIAVESPPhSETIUD c 13 CHAPTER 4 PCLINTEREA CR sciicesscsesasssescdccssavanceccesescecoastbsascesdesseastesnccenesdeseadeseasonsticastonesessaaseeecseseseesceseenscoasds 14 4 0 PCLINTERFACE REGISTERS aee Pike cree Gad cora eise 14 4 1 PET REGISTERS rn eI Tere E Respir 14 4 1 1 PCI CONFIGURATION REGISTERS cccccceessscecccececeesseaececececsessaaececececsenesaecesececeeneasaaeseesceesessaaeeeeececeensaaeeeeees 14 4 1 2 LOCAL CONFIGURATION REGISTERS ccsssessccccecsesessecececececsesseaececccecsensaaecececeeseneaaececececeeseaeseseesesenenseaeeeeees 15 4 1 3 RUNTIME REGISTERS eaa eee Pe rex e bise ere 15 4 1 4 REGISTERS ertt eerie pepe reir tee erre 15 CHAPTER 5 HARDWARE CONFIGURATION ee esee ee ee seen seen e stans etae setas etae stans etos esten setae etta 16 5 0 BOARD AV OUT eoo tetto iade deiude e tein RM c 16 5 1 0 9 Rte trie rb rere bet te E bee aspen te evi pe eU E PNE 17 5 2 th C2. D31 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D8 D7 D6 D5 D4 D3 D0 Unused Rx Status byte inserted in FIFO Timestamp 01 single external clock 10 single internal clock FPGA Reprogram field 01 Present 00 Not Present configurable fifo space 01 Rx Tx select Up to 32k deep FIFOs 1 FIFO Test Bit FW Feature Level Set at common code level 0x01 RS232 support Pin Source Change 0x02 Multi Protocol support 0x03 Common Internal External FIFO Support 0x04 FIFO Latched Underrun Overrun Level 0x05 Demand mode DMA Single Cycle for Tx 0x06 Single Cycle Dis updated Pin_Src 0x07 Rx Underrun Only Reset Status 0x08 Clock to 50Hz with 10Hz resolution 0x09 No Legacy Support No Clock Control Register 1 DMA Single Cycle Disable 1 Board Reset FIFO present bits 1 FIFO Size Counters present 1 FW ID complies with this standard Clock Oscillator 0 0 Fixed 0 1 ICD2053B 1 Osc 0x2 ICD2053B 4 Osc 0x3 CY22393 4 Osc Ox4 2 x CY22393 6 Osc 24
3. 1 1 2 SPARE IO DIFFERENTIAL RS422 00 cccccccssssecssssececessceceessssecsessececsesseceessesecsenseeecnesaeceesassecsesaeeecseseeesenenseeesnes 1 CHAPTER 2 LOCAL SPACE REGISTERG csscsssssssssssssscsssssssssssssssssssssssssssnssssscsssasssscessacseasssssssssassessasseassnssees 2 2 0 GSC FIRMWARE LOCAL SPACE REGISTERS sc cccsesseceesececessseeecsesaececseneecessaeeecsessececeeseecesseeecseaeeseseeaeeees 2 2 1 FIRMWARE REVISION LOCAL OFFSET 0X0000 c cccccccesssssscecececsessaececececeeseaeceeececeessaececeeeeseneaaseeeeeeeeenes 3 2 2 BOARD CONTROL LOCAL OFFSET OX0004 ccccsessecccececsessececcceceesensesecececeesesseaeeecececsesaaeceeccecsesssaseeeeeeeess 3 2 3 BOARD STATUS LOCAL OFFSET OXOO08 ccccccsessececececsesesececececeessseeecececeesessesececceseseseaeceesesesenseaeeeeeeesens 4 2 4 CHANNEL TX ALMOST FLAGS LOCAL OFFSET 0x0010 0x0020 0x0030 0x0040 5 2 5 CHANNEL RX ALMOST FLAGS LOCAL OFFSET 0x0014 0x0024 0x0034 0 0044 5 2 6 CHANNEL FIFO LOCAL OFFSET 0x0018 0x0028 0x0038 0 0048 5 2 7 CHANNEL CONTROL STATUS LOCAL OFFSET 0x001C 0x002C 0x003C 5 2 8 INTERRUPT REGISTERS 4 ere Ee Ted uere ec ua EE veas E eda ee OSEE 7 2 8 1 INTERRUPT CONTROL LOCAL OFFSET 0 0060
4. 8 2 8 2 INTERRUPT STATUS CLEAR LOCAL OFFSET OXO0064 cc c ccccccccessssscecececeesssneceeececeessaaeeeceeeceeseaseeceeeceeneaees 8 2 8 3 INTERRUPT EDGE LEVEL LOCAL OFFSET 0 0068 8 2 8 4 INTERRUPT HI LO LOCAL OFFSET OXOO6C c ccccceceesessscecececeesensececececseseaecesececeeseeaeceeeesesestsaeeeeceeenenegs 8 2 9 CHANNEL PIN SOURCE LOCAL OFFSET 0x0080 0x0084 0x0088 0x008C 9 2 10 CHANNEL PIN STATUS LOCAL OFFSET 0 0090 0x0094 0x0098 10 2 11 PROGRAMMABLE CLOCK REGISTERS LOCAL OFFSET 0X00A0 4 10 2 12 TX COUNT REGISTER LOCAL OFFSET OXOOB4 OxOOBS 10 2 13 FIFO COUNT REGISTER LOCAL OFFSET 0 0x00D4A 0 0008 0x00DC 10 2 14 FIFO SIZE REGISTER LOCAL OFFSET OXOOEA OxOOES OXOOEC 11 2 15 FW TYPE ID REGISTER LOCAL OFFSET OXOOFS8 esses eene 11 2 16 FEATURES REGISTER LOCAL OFFSET OXOOFC 11 CHAPTER 3 QUICKSTART GUIDE wiviissssssecosssssessscssonsonssscosasseesasensssenssesevedessesnnssednessenssssassceteoserseasesecdessnsondees 12 3 0 COVER VIEW 5s cL
5. PMC66 SIO4BXR BAE BIC board CHAPTER 5 HARDWARE CONFIGURATION 5 0 Board Layout The following figure is a drawing of the physical components of the PCI66 SIO4B Multi Protocol Xcvr Multi Protocol Xcvr Multi Protocol Xcvr Multi Protocol Xevr Figure 5 1 Board Layout Top Multi Protocol Xevr Multi Protocol Xevr Multi Protocol Xevr Multi Protocol Xevr Figure 5 2 Board Layout Bottom 5 1 Board ID Jumper 15 Jumper J5 allows the user to set the Board ID in the GSC Board Status Register See Section 2 1 3 This is useful to uniquely identify a board if more than one SIO4BXR card is in a system When the Board ID jumper is installed it will read 1 in the Board Status Register The Board Status Register bit will report 0 when the jumper 15 removed Refer to Figure 5 1 for Jumper J5 location 1 2 Board ID 1 Board ID 1 in Board Status Register DO 3 4 Board ID 2 Board ID 2 in
6. When a Chip Select is not enabled it will be driven to a high level Ideally one CS should be enabled per channel both Master and Slave In Master mode the chip selects are asserted at the beginning of the cycle one clock period prior to the start of the SPI word transfer and are asserted one clock after the word completes The time between words is set by the Gap Bit Count field of the TX Count Register D31 16 If the Gap value is set below 3 the CS will remain low between SPI word transfers The Gap field has no effect in Slave mode 33 SPI Word Size The SPI word size is set in the Transmit Bit Count field of the Tx Count Register D15 0 This value will define the number of consecutive bits in a SPI word This should be setup in both Master and Slave mode SPI data will be transmitted MSB first Therefore if the SPI size is greater than 8 bits the most significant byte should be written to the Tx FIFO first Likewise the Most Significant Byte will be received first in the RX FIFO For SPI word size greater than 8 bits the user will need to ensure the entire word is written to the Tx FIFO before the SPI is enabled Channel Control Status Register D25 Otherwise the SPI word may be broken into 8 bit segments if the Tx FIFO becomes empty 3 4 3 5 Master SPI Controller Setup Set Clock to 2x SPI clock frequency Set Pin Source Register Enable Transceiver D31 1 and Clk Idle 020 Set Channel Control Status Registe
7. 1 Test Mode FIFO Write to Rx FIFO FIFO Read from Tx FIFO D28 27 Reserved 26 24 LED D3 D1 z Turn on green LED DI D2 D3 D23 9 RESERVED D8 Rx FIFO Stop on Full 1 If Rx FIFO becomes full stop receiving data disable receiver D7 Demand Mode DMA Channel 1 Single Cycle Disable D6 4 Demand Mode DMA Channel 1 Request 000 Chl Rx 100 Chl Tx 010 Ch2 Rx 110 2 Ch2 Tx 001 2 Ch3 Rx 101 2 Ch3 Tx 011 Ch4 Rx 111 Ch4 Tx D3 Demand Mode DMA Channel 0 Single Cycle Disable D2 0 Demand Mode DMA Channel 0 Request 000 Chl Rx 100 Chl Tx 010 Ch2 Rx 110 2 Ch2 Tx 001 2 Ch3 Rx 101 2 Ch3 Tx 011 Ch4 Rx 111 Ch4 Tx 2 3 Board Status Local Offset 0x0008 The Board Status Register gives general overall status for a board The Board Jumpers 01 00 are physical jumpers which can be used to distinguish between boards if multiple SIO4 boards are present in a system D31 D6 RESERVED D5 D4 FIFO Size 112256K 03 00 Board Jumper 15 D3 Board 4 0 15 7 15 8 jumper installed D2 Board ID3 0 15 5 15 6 jumper installed D1 Board ID2 0 J5 3 J5 4 jumper installed D0 Board ID1 02J5 1 J5 2 jumper installed 2 4 Channel TX Almost Flags Local Offset 0 0010 0x0020 0x0030 0x0040 The Tx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs The Almost Full Empty Flags may be read as status bits in the Channel Control Status Register and are also edge triggered interrupt sources
8. Board Status Register D1 5 6 Board ID 3 Board ID 3 in Board Status Register D2 7 8 Board ID 4 Board ID 4 in Board Status Register D3 5 2 LEDs Six green LEDs D1 D2 D3 D4 D7 D8 are accessible via software Refer to Figure 5 2 for these LED locations Upon powerup these LEDs show the lower 6 bits of the Firmware Revision This provides a quick indication of the current installed firmware If any of the software LED bits is set Board Control Register D9 D4 these LEDs revert to being software driven 5 3 Interface Connector Pin DTE Signal DCE Signal Pin DTE Signal DCE Signal 1 Chl Spare 35 Ch3 Spare 2 Chl Spare 36 Ch3 Spare 3 Chl SPI CS3 37 Ch3 SPI CS3 4 Chl SPI CS3 38 Ch3 SPI CS3 5 Chl SPI CS2 39 Ch3 SPI CS2 6 Chl SPI CS2 40 Ch3 SPI CS2 7 Chl SPI CSI 4l Ch3 SPI CSI 8 Chl SPI CSI 42 Ch3 SPI CSI 9 Chl SPI 80 43 Ch3 SPI CSO 10 Chl SPI CSO 44 Ch3 SPI CSO an Chl SPI MISO 45 Ch3 SPI MISO Chl SPI MISO 46 Ch3 SPI MISO Chl SPI MOSI 47 Ch3 SPI MOSI Chl SPI MOSI 48 Ch3 SPI MOSI Chl SPI 49 Ch3 SPI 16 Chl SPI 50 Ch3 SPI 17 GND 51 GND 18 GND 32 GND 19 Ch2 SPI CS2 53 Ch4 SPI 52 20 Ch2 SPI 52 54 Ch4 SPI 52 21 Ch2 SPI CSI 35 Ch4 SPI CSI 22 Ch2 SPI CSI 56 Ch4 SPI CSI 23 Ch2 SPI CS0 57 Ch4 SPI CS0 24 C
9. I I ML PM 17 5 3 INTERFACE CONNEGTOR erede v ere nre ep e eet eere edere e obe teen cerunt teres eee pt ie eet 18 CHAPTER 6 ORDERING OPTIONS issssssssocssssssensssnnsonssssssersovsassnsssensesseasosensssnnsonsnessensssonasstesonsorseasesessssensonsses 19 6 0 ORDERING INFORMATION Ere E E TEC E UE E erre iR 19 6 1 INTBREACE CABLE eite ea terrx Ot disti a lad oia eai e e eia Cao 19 6 2 DEVICE DRIVERS eise Re menn Reisenden 19 CHAPTER 1 INTRODUCTION 1 0 General Description The PMC66 SI04BXR SPI is a custom modification to interface to a SPI device The PMC66 SI04BXR SPI board will provide the RS422 differential interface signals of a Master SPI Controller or a generic Slave SPI device 1 1 SPI Interface Differential RS422 SPI CLK Active High Master Output Slave Input Master clock used to transfer data Clock rate may be from 3MHz down to 25Hz Output Data will change on the falling edge of the clock and input data will be clocked on the rising edge SPI CS 3 0 Active Low Master Output Slave Input Four Chip select signals which can be are individually enabled This allows one Master Controller to interface more than one device The chip select will go low at the beginning of the SPI Word one clock period prior to data clocking and will remain asserted one clock after the SPI Word has completed SPI MOSI Active High Master Output Slave Input Master Out Slave In Data Data is clocked out MSB
10. PLL1 P Hi Setup6 0x00 0x55 PLL1 Setup 0x00 0x56 PLL1 P Lo 0 Setup 0x00 0x57 PLL1 Enable PLL1 P Hi Setup 0x00 0 58 Reserved Unused 0x00 22 APPENDIX B FIRMWARE REVISIONS FEATURES REGISTER Since 5104 boards can exist across multiple form factors and with various hardware features the firmware features registers attempt to help identify the exact version of a SIO4 board This appendix provides a more detailed breakdown of what the firmware and features registers and detail differences between the firmware revisions Firmware Register Local Offset 0x00 0xE2240B02 D31 16 HW Board Rev OxE224 D31 1 Features Register Present D30 1 Complies with this standard D29 1 66MHz PCI bus interface 0 33MHz PCI bus interface D28 1 64 bit PCI bus interface 0 32 bit bus interface D27 D24 Form Factor 0 Reserved 1 PCI 2 3 4 104 D23 D20 HW Board sub field of form factor 0 PMC SIO4AR 1 PMC SIO4BX 2 PMC66 SIO4BXR PMC66 SIO4BXR Rev D Std Firmware default Sync Firmware default Spi Firmware custom D19 D16 HW Board Rev lowest rev for firmware version 0 NR 1 A 2 B 3 C 4 D D15 8 Firmware Type ID 0x01 0x04 0x0B D7 0 Firmware Revision XX 0x00 Initial Rev Master Only 0x01 Integrate Slave Firmware Version 0x02 Fix Tx Stop On Empty add syncFF FlowThru Update clock programming 23 Feature Register Local Offset
11. first For a Master Controller the serial output data will change on the falling edge of the SPI clock For a Slave Interface the serial input data will be clocked in on the rising edge of the SPI clock SPI MISO Active High Master Input Slave Output Master In Slave Out Data Data is clocked in MSB first For a Master Controller the serial input data will be clocked in on the rising edge of the SPI clock For a Slave Interface the serial output data will change on the falling edge of the SPI clock 1 2 Spare IO Differential RS422 SPARE Active High Input Output The Spare signal is a general purpose IO signal that may be configured as an input or output As an input this signal can be used as an interrupt source CHAPTER 2 LOCAL SPACE REGISTERS 2 0 GSC Firmware Local Space Registers The PMC66 SIO4BXR SPI is accessed through two sets of registers PCI Registers and GSC Firmware Registers The GSC Firmware Registers referred to as Local Space Registers which provide the control status for the SIO4BXR SPI board are described below The PCI registers internal to the PLX 9056 PCI controller are discussed in Chapter 4 Offset Address Default Value Hex EXHOBXX 00000000 000001XX Ox000C Reserved O o J 00000000 00070007 00070007 000000XX 0000 00 00070007 00070007 000000XX 0000 00 00070007 00070007 000000XX 0000 00 00070007 00070007 000000XX 0000 00 0x0050 0x000C RES
12. has mirrored this data internal to the CLOCK RAM to allow the user to simply setup the data in the FPGA RAM and then command the on board logic to program the clock chip This isolates the user from the hardware serial interface to the chip For detailed CY22393 programming details please refer to the Cypress Semiconductor CY22393 dat sheet For the SIO4BXR a second programmable oscillator has been added to assure that each channel has a dedicated PLL The older SIO4BX uses 3 PLLs in a single CY22393 to generate all four clocks To implement this a second CLOCK RAM block was added CLOCK RAMI programs the first CY22393 using CLKA Ch1_Clk CLKB Ch2 CLKC Ch3 and CLOCK RAM2 programs the second CY22393 using CLKD Ch4 Since the original SIO4BX with a single CY22393 used CLKD for Ch4 the same code can be made to support both schemes by simply programming CLKD of the first CY22393 Each CLOCK RAM block is accessed through 2 registers Address Offset at local offset 0 and Data at local ffset at 0x00A4 CLOCK RAM1 or OxOOAC CLOCK RAM2 The user simply sets the RAM Address register to the appropriate offset then reads or writes the the RAM data The Programmable Osc Control Status register allows the user to program the CY22393 or setup the clock post dividers The GSC Local Programmable Clock Registers are defined as follows 0x00A0 RAM Address Register Defines the internal CLOCK RAM
13. 23 D0 Channel Clock Post Dividers The Control Word defines 4 fields for Channel Clock Post dividers These post dividers will further divide down the input clock from the programmable oscillator to provide for slow baud rates Each 4 bit field will allow a post divider of 2 n For example if the post divider value 0 the input clock is not post divided A value of 2 will provide a post divide of 4 2 2 This will allow for a post divide value of up to 32768 2 15 for each input clock Bit D7 of the Control word qualifies writes to the post divide registers This allows other bits in the command register to be set while the post divide values are maintained Channel Clock Measurement The Control Word defines 4 bits which will select one of the 4 channel clocks input clock post divide for a measurement This will allow the user feedback as to whether the programmable oscillator was programmed correctly To measure a clock select the clock to measure in the Control word and also clear Bit D6 to allow for readback of the result Read back the Status Word until D2 is set Status Word D31 D8 should contain a value representing 1 10 the measured clock frequency Value 10 2 Measured Frequency in MHz Keep in mind that this value will not be exactly the programmed frequency due to the 100ppm 0 0196 accuracy of the on board reference 21 The Internal RAM is defined as follows RAM Address 0x08 0x57 correspond directly to CY22393 regist
14. ERVED 00000000 00000000 FFFFFFFF FFFFFFFF 0x0070 0x00C o 00000020 00000020 00000020 00000020 000000XX 000000XX 000000XX 000000XX 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 wexecc p9 Reserved 00000000 00000000 00000000 0x00D8 Ox00F0 0x00F4 RESERVED Cd 00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0X0X0X0X 001979F4 2 1 Firmware Revision Local Offset 0x0000 The Firmware ID register provides version information about the firmware on the board This is useful for technical support to identify the firmware version 2 2 031 16 HW Board Rev OxE224 PMC66 SIO4BXR Rev D D15 8 Firmware Type ID SPI Firmware D7 0 Firmware Revision XX Firmware Version Board Control Local Offset 0x0004 The Board Control Register defines the general control functions for the board The main function in this register defines the Demand mode DMA channel requests D31 Board Reset 1 Reset all Local Registers and FIFOs to their default values Notes This bit will automatically clear to 0 following the board reset Board Reset will NOT reset programmable oscillator Following a Board Reset ResetInProgress bit D31 of the Board Status Register will remain set until the Board reset is complete D30 RESERVED Debug Test D29 FIFO Test 0 Normal Mode FIFO Write to Tx FIFO FIFO Read from Rx FIFO
15. PMC66 SIO4BXR SPI User s Manual RS422 Interface General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail techsupport 2generalstandards com Revision B PREFACE Revision History 1 Rev NR Apr 2012 Original Rev firmware 0 2 RevA Apr 2012 Add Master Slave selection firmware vB01 3 RevB May 2012 Add ProgClk Appendix misc cleanup firmware vB02 Additional copies of this manual or other General Standards Corporation literature may be obtained from General Standards Corporation 8302A Whitesburg Drive Huntsville Alabama 35802 Telephone 256 880 8787 Fax 256 880 8788 URL www generalstandards com The information in this document is subject to change without notice General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any l
16. address to read write 0x00A4 RAM Datal Register Provides access to the CLOCK RAMI pointed to by the RAM Addr Register 0x00A C RAM Data2 Register Provides access to the CLOCK RAM2 pointed to by the RAM Addr Register 0x00A8 Programmable Osc Control Status Register Provides control to write the contents of the CLOCK RAM to the CY22393 and setup additional post dividers for the input clocks Control Word Write Only DO Program Oscillator 1 Program contents of CLOCK RAM to 22393 Automatically resets to 0 D1 Measure Channel 1 Clock D2 Measure Channel 2 Clock D3 Measure Channel 3 Clock D4 Measure Channel 4 Clock 05 Reserved Unused D6 Status Word Readback Control 20 0 gt Status Word D31 D8 Measured Channel Value 1 gt Status Word D31 D8 Control Word D23 D0 D7 Post divider set 0 Ignore D23 D8 during Command Word Write 1 Set Channel Post Dividers from D23 D8 during Command Word Write D11 D8 Channel Post Divider D15 D12 Channel 2 Post Divider D19 D16 Channel 3 Post Divider D23 D20 Channel 4 Post Divider D31 D24 Reserved Unused Status Word Read Only DO Program Oscillator Done 0 Oscillator Programming in progress D1 Program Oscillator Error 1 Oscillator Programming Error has occurred D2 Clock Measurement complete 0 Clock Measurement in progress D7 D3 Reserved Unused D31 D8 If Command Word D6 0 Measured Channel Clock Value If Command Word D6 1 Control Word D
17. ers 0x00 0x05 Reserved Unused 0x00 0x06 Reserved OxD2 0x07 Reserved 0x08 0x08 Divisor Setup0 0x01 0x09 Divisor Setup1 0x01 CIKB Divisor SetupO 0 01 OxOB CIKB Divisor Setup1 0 01 Divisor 0 01 0 0 Divisor 0 01 Source Select 0x00 OxOF Bank Select 0x50 0x10 Drive Setting 0 55 0x11 PLL2 Q 0x00 0x12 PLL2 P Lo 0x00 0x13 PLL2 Enable PLL2 P Hi 0x00 0 14 PLL3 Q 0x00 0 15 PLL3 P Lo 0x00 0x16 PLL3 Enable PLL3 P Hi 0x00 0 17 OSC Setting 0x00 0x18 Reserved 0x00 0x19 Reserved 0x00 Ox1A Reserved OxE9 Ox1B Reserved 0x08 Ox1C Ox3F Reserved Unused 0x00 0x40 PLL1 Setup0 0x00 0 41 PLL1 P Lo 0 Setup0 0x00 0x41 PLL1 Enable PLL1 P Hi Setup0 0x00 0x43 PLL1 Q Setupl 0x00 0x44 P Lo 0 Setup1 0x00 0x45 PLL1 Enable PLL1 P Hi Setup1 0x00 0x46 PLL1 Setup2 0x00 0x47 P Lo 0 Setup2 0x00 0x48 PLL1 Enable PLL1 P Hi Setup2 0x00 0x49 PLL1 Setup3 0x00 Ox4A PLL1 P Lo 0 Setup3 0x00 Ox4B PLL1 Enable PLL1 P Hi Setup3 0x00 0 4 PLL1 Setup4 0x00 0 4 P Lo 0 Setup4 0x00 Ox4E PLL1 Enable PLL1 P Hi Setup4 0x00 Ox4F PLL1 Setup5 0x00 0x50 P Lo 0 Setup5 0x00 0x51 PLL1 Enable PLL1 P Hi Setup5 0x00 0x52 PLL1 Setup6 0x00 0x53 PLL1 P Lo 0 Setup6 0x00 0x54 PLL1 Enable
18. h2 SPI 50 58 Ch4 SPI 50 Ch2 SPI 59 Ch4 SPI Ch2 SPI MISO 60 Ch4 SPI MISO Ch2 SPI MOSI 61 Ch4 SPI MOSI Ch2 SPI MOSI 62 Ch4 SPI MOSI Ch2 SPI 63 Ch4 SPI 30 Ch2 SPI CIk 64 Ch4 SPI 31 2 SPI CS3 65 Ch4 SPI 5 32 Ch2 SPI 5 66 Ch4 SPI CS3 33 Ch2 Spare 67 Ch4 Spare 34 Ch2 Spare 68 Ch4 Spare The user interface connector for PCI66 SIOABXR is a SCSI type 68 pin connector female mounted to Table 5 1 RS422 Cable Pin Out the front edge of the board P3 Part Number Mating Connector TE Connectivity 787170 7 or 5787170 7 TE Connectivity 749621 7 or 749111 6 or equivalent CHAPTER 6 ORDERING OPTIONS 6 0 Ordering Information PMC66 SIO4BXR SPI Temperature Temperature Option Operating Temperature Range lt blank gt 0 to 70 Commercial I 40 to 85 Industrial Please consult our sales department with your application requirements to determine the correct ordering options quotes generalstandards com 6 1 Interface Cable General Standards Corporation can provide off the shelf or custom interface cables for the PMC66 SIO4BXR SPI board The standard cable is a non shielded twisted pair 68 conductor ribbon cable for increased noise immunity Several standard cable lengths are offered or the cable length can be custom ordered Versions of t
19. he cable are available with connectors on both ends or the cable may be ordered with a single connector to allow the user to adapt the other end for a specific application A standard cable is also available which will breakout the serial channels into four DB25 connectors Shielded cable options are also available Please consult our sales department for more information on cabling options and pricing 6 2 Device Drivers General Standards has developed many device drivers for the PMC66 SIO4BXR boards including VxWorks Windows Linux and LabView As new drivers are always being added please consult our website www generalstandards com or consult our sales department for a complete list of available drivers and pricing APPENDIX OSCILLATOR PROGRAMMING The 4 on baord clock frequencies are supplies two Cypress Semiconductor CY22393 Programmable Clock Generatosr In order to change the clock frequencies this chip must be reprogrammed This document supplies the information necessary to reprogram the on board clock frequencies GSC has developed routines to calculate and program the on board oscillator for a given set of frequencies so it should not be necessary for the user need the following information it is provided for documentation purposes Please contact GSC for help in setting up the on board oscillator The CY22393 contains several internal address which contain the programming information GSC
20. icense conveyed under any patent right of any rights of others General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No parts of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation Copyright 2012 General Standards Corporation RELATED PUBLICATIONS PLX PCI 9056 Data Book PLX Technology Inc 390 Potrero Avenue Sunnyvale CA 4085 408 774 3735 http www plxtech com EIA 422 A Electrical Characteristics of Balanced Voltage Digital Interface Circuits EIA order number EIA RS 422A EIA Standards and Publications can be purchased from GLOBAL ENGINEERING DOCUMENTS 15 Inverness Way East Englewood CO 80112 Phone 800 854 7179 http global ihs com PCI Local Bus Specification Revision 2 2 December 18 1998 Copies of PCI specifications available from PCI Special Interest Group NE 2575 Kathryn Street 17 Hillsboro OR 97124 http www pcisig com lo EYUUDEHENVUODUUO 1 1 0 GENERAL DESCRIPEION 3 Alisher eae ch te ia tied eei 1 1 1 SPI INTERFACE DIFFERENTIAL RS422
21. lear to 0 2 8 Interrupt Registers There are 32 on board interrupt sources in addition to PLX interrupts each of which may be individually enabled Four interrupt registers control the on board interrupts Interrupt Control Interrupt Status Interrupt Edge Level and Interrupt Hi Lo The Interrupt sources are IRQO Reserved X X IRQI Chl Tx FIFO Almost Empty Rising Edge Falling Edge IRQ2 Chl Rx FIFO Almost Full Rising Edge Falling Edge IRQ3 Chl RxSpare Rising Edge Falling Edge IRQ4 Reserved X X IRQ5 Ch2 Tx FIFO Almost Empty Rising Edge Falling Edge IRQ6 Ch2 Rx FIFO Almost Full Rising Edge Falling Edge IRQ7 Ch2 RxSpare Rising Edge Falling Edge IRQ8 Reserved X X IRQ9 Ch3 Tx FIFO Almost Empty Rising Edge Falling Edge IRQIO Ch3 Rx FIFO Almost Full Rising Edge Falling Edge IRQI1 Ch3 RxSpare Rising Edge Falling Edge IRQ12 Reserved X X IRQI3 Ch4 Tx FIFO Almost Empty Rising Edge Falling Edge IRQI4 Ch4 Rx FIFO Almost Full Rising Edge Falling Edge IRQI5 Ch4 RxSpare Rising Edge Falling Edge IRQ16 Chl Tx FIFO Empty Rising Edge Falling Edge IRQI7 Chl Tx FIFO Full Rising Edge Falling Edge IRQIS Chl FIFO Empty Rising Edge Falling Edge IRQI9 Chl Rx FIFO Full Rising Edge Falling Edge IRQ20 Ch2 Tx FIFO Empty Rising Edge Falling Edge IRQ21 Ch2 Tx FIFO Full Rising Edge Falling Edge IRQ22 Ch2 Rx FIFO Empty Rising Edge Falling Edge IRQ23 Ch2 Rx FIFO Fu
22. ll Rising Edge Falling Edge IRQ24 Ch3 Tx FIFO Empty Rising Edge Falling Edge IRQ25 Ch3 Tx FIFO Full Rising Edge Falling Edge IRQ26 Ch3 Rx FIFO Empty Rising Edge Falling Edge IRQ27 Ch3 Rx FIFO Full Rising Edge Falling Edge IRQ28 Ch4 Tx FIFO Empty Rising Edge Falling Edge IRQ29 Ch4 Tx FIFO Full Rising Edge Falling Edge IRQ30 Ch4 Rx FIFO Empty Rising Edge Falling Edge IRQ31 Ch4 Rx FIFO Full Rising Edge Falling Edge For all interrupt registers the IRQ source IRQ31 IRQO will correspond to the respective data bit D31 D0 of each register DO IRQO DI IRQI etc All FIFO interrupts are edge triggered active high This means that an interrupt will be asserted assuming it is enabled when a FIFO Flag transitions from FALSE to TRUE rising edge triggered or TRUE to FALSE falling edge For example If Tx FIFO Empty Interrupt is set for Rising Edge Triggered the interrupt will occur when the FIFO transitions from NOT EMPTY to EMPTY Likewise if Tx FIFO Empty Interrupt is set as Falling Edge Triggered the interrupt will occur when the FIFO transitions from EMPTY to NOT EMPTY Interrupt Sources share a single interrupt request back to Local Interrupt Input of the PCI9056 PLX chip This Local Interrupt input must be enabled in the PLX Interrupt Control Status Register to be recognized as a PCI interrupt source 2 8 1 Interrupt Control Local Offset 0x0060 The Interrupt Control register individually enables each interrupt
23. ly used in Master mode D15 0 Transmit Bit Count Indicates size of SPI word 2 13 FIFO Count Register Local Offset 0x00D0 0x00D4 0x00D8 0x00DC The FIFO Count Registers display the current number of words in each FIFO This value along with the FIFO Size Registers may be used to determine the amount of data which can be safely transferred without over running or under running the FIFOs D31 D16 Number of words in Rx FIFO D15 D0 Number of words in Tx FIFO 2 14 FIFO Size Register Local Offset 0 00 0 0x00E4 0x00E8 0x00EC The FIFO Size Registers display the sizes of the installed data FIFOs This value is calculated at power up This value along with the FIFO Count Registers may be used to determine the amount of data which can be safely transferred without over running or under running the FIFOs This value is fixed D31 D16 Size of installed Rx FIFO D15 D0 Size of installed Tx FIFO 2 15 FW Type ID Register Local Offset 0x00F8 This register allows boards to be designed with different functionality on each channel For example a board could contain two Standard SIO channels with Z16C30 and two Raw Synchronous channels Each byte corresponds to a channel This register is read only it reflects the implemented logic D31 D24 Channel 4 FW Type SPI D23 D16 Channel 3 FW Type SPI D15 D8 Channel 2 FW Type SPI D7 D0 Channel 1 FW Type SPI 2 16 Features Register Local Off
24. nterrupt when the TX FIFO becomes NOT Empty 2 9 The Channel Pin Source Register configures function of cable interface signals as well as controls transceiver protocols Channel Pin Source Local Offset 0x0080 0x0084 0x0088 0x008C 31 30 29 28 27 26 25 24 Cable Xcvr 0 Ext LB 0 Transceiver Protocol Mode Enable Test 0000 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 Int LB 00 CLK 0 Spare MISO MOSI CS 0 CLK Test Idle Src Test Src Test Src Test Src Test Src Pin Source Register D31 Cable Transceiver Enable 0 Transceivers Tri Stated 1 Transceivers Enabled D30 RESERVED D29 Ext LB Test External Loopback Test Mode 0 Normal Mode 1 External Master Loopback Test MISO MOST D28 RESERVED D27 24 Transceiver Protocol Mode 0000 RS422 RS485 D23 Int LB Test Internal Loopback Test Mode 0 Normal Mode 1 Internal Master Loopback Test MISO MOSI D22 21 RESERVED D20 CLK Idle State 0 returns low between SPI words 1 CLK remains high between SPI words D19 13 RESERVED D12 11 Spare Control 00 Disabled Tri state 01 Input 10 Output 0 11 Output 1 D10 9 MISO Test Normal Input 10 Output 0 11 Output 1 08 6 MOSI Test z Normal Output 110 Output 0 111 Output 1 D5 4 CSTest Normal Output 10 w CS Enabled Output 0 10 w CS Disabled Outp
25. r Master 0310 CS Enables D30 D27 and Tx Stop on Idle D26 Set Tx Count Register Gap and Tx Count SPI Word Size Load Data into Tx FIFO if Word Size gt 8 write Most Significant Byte first Enable SPI Channel Control Status Register D25 As data transmits MISO data received in Rx FIFO If Tx Stop on Idle Set Enable SPI will reset when TX FIFO empty Read data from Rx FIFO Rx FIFO Count will show number of bytes received Slave SPI Setup Set Pin Source Register Enable Transceiver D31 1 and Clk Idle 020 Set Channel Control Status Register Slave D31 1 CS Enables D30 D27 Set Stop On Rx FIFO Full in Board Control Register D8 Set Tx Count Register Tx Count SPI Word Size Load Data into Tx FIFO if Word Size gt 8 Most Significant Byte first Enable SPI Channel Control Status Register D25 Wait for SPI Controller to send data MOSI data received in Rx FIFO If Rx Stop on Full Set Enable SPI will reset when Rx FIFO full Read data from Rx FIFO Rx FIFO Count will show number of bytes received CHAPTER 4 PCI INTERFACE 4 0 PCI Interface Registers The PMC PCI interface is handled by a PCI9056 I O Accelerator from PLX Technology The PCI interface is compliant with the 5V 66MHz 32 bit PCI Specification 2 2 The PCI9056 provides dual DMA controllers for fast data transfers to and from the on board FIFOs Fast DMA burst accesses provide for a maximum burst throughput of 264 to the PCI interface To
26. rds drivers should verify the ID Sub ID information before attaching to this card These values are fixed via the Serial EEPROM load following a PCI Reset and cannot be changed by software Vendor ID Ox10B5 PLX Technology Device ID 0x9056 PCI9056 Sub Vendor ID Ox10B5 PLX Technology Sub Device ID 0x3198 GSC SIO4BXR The configuration registers also setup the PCI IO and Memory mapping for the SIO4BXR The PCI9056 is setup to use PCIBARO and PCIBARI to map the internal PLX registers into PCI Memory and IO space respectively PCIBAR2 will map the Local Space Registers into PCI memory space and PCIBAR3 is unused Typically the OS will configure the PCI configuration space For further information of the PCI configuration registers please consult the PLX Technology PCI9056 Manual 4 1 2 Local Configuration Registers The Local Configuration registers give information on the Local side implementation These include the required memory size The SIO4BXR memory size is initialized to 4k Bytes All other Local Registers initialize to the default values described in the PCI9056 Manual 41 3 Runtime Registers The Runtime registers consist of mailbox registers doorbell registers and a general purpose control register The mailbox and doorbell registers are not used and serve no purpose on the SIO4BXR other Runtime Registers initialize to the default values described in the PCI9056 Manual 4 1 4 DMA Registers is not used on
27. reduce CPU overhead during transfers the controller also implements Chained Scatter Gather as well as Demand Mode Since many features of the PCI9056 are not utilized in this design it is beyond the scope of this document to duplicate the PCI9056 User s Manual Only those features which will clarify areas specific to the PMC66 SIO4BXR are detailed here Please refer to the PCI9056 User s Manual See Related Publications for more detailed information Note that the BIOS configuration and software driver will handle most of the PCI9056 interface Unless the user is writing a device driver the details of this PCI Interface Chapter may be skipped 4 1 PCI Registers The PLX 9056 contains many registers many of which have no effect on SIO4BXR performance The following section attempts to filter the information from the PCI9056 manual to provide the necessary information for a SIO4BXR specific driver The SIO4BXR uses an on board serial EEPROM to initialize many of the PCI9056 registers after a PCI Reset This allows board specific information to be preconfigured correctly 4 1 1 PCI Configuration Registers The PCI Configuration Registers allow the PCI controller to identify and control the cards in a system PCI device identification is provided by the Vendor ID Device ID Addr 0x0000 and Sub Vendor ID Sub Device ID Registers 0 002 The following definitions are unique to the General Standards SIO4BXR boa
28. set 0x00FC The Features Register allows software to account for added features in the firmware versions Bits will be assigned as new features are added See Appendix B for more details D31 21 RESERVED D20 1 No Rx Status byte std only D19 D18 10 Internal Timestamp std only D17 D16 01 FPGA Reprogram field D15 D14 01 configurable FIFO space D13 1 FIFO Test Bit D12 1 FW Type Reg D11 8 Features Rev Level 0x9 BXR level D7 1 Demand Mode DMA Single Cycle Disable feature implemented D6 1 Board Reset D5 1 FIFO Counters Size D4 1 D3 0 Programmable Clock Configuration 0x4 Two CY22393 6 Oscillators CHAPTER 3 QUICKSTART GUIDE 3 0 Overview The SPI interface setup is fairly simple Only a few registers are required to interface to SPI devices 3 1 Clock The channel clock should be set to twice the SPI clock The driver should have a standard clock setup function to set the clock frequency This should only need to be setup for Master mode as the Slave will use the SPI clock from the cable The state of the clock between SPI words can be defined high or low Bit D20 of the Pin Status Register controls this CLK Idle State This bit needs to be setup for both Master and Slave 3 2 Chip Selects Each channel has 4 chip selects which can be individually enabled Chip selects can be individually enabled in the Channel Control Status Register D30 D27 If a single chip select is needed simply use CSO and set D27 1
29. source A 1 enables each interrupt source a 0 disables An interrupt source must be enabled for an interrupt to be generated 2 8 20 Interrupt Status Clear Local Offset 0x0064 The Interrupt Status Register shows the status of each respective interrupt source If an interrupt source is enabled in the Interrupt Control Register a 1 in the Interrupt Status Register indicates the respective interrupt has occurred The interrupt source will remain latched until the interrupt is cleared either by writing to the Interrupt Status Clear Register with a 1 in the respective interrupt bit position or the interrupt is disabled in Interrupt Control Register Clearing an interrupt which is not enabled or not asserted will have no effect 2 8 3 Interrupt Edge Level Local Offset 0x0068 The Interrupt Edge Register is an information only read only register This register can be used by a generic driver to determine if the interrupt source is edge or level triggered interrupt sources on the SIO4BXR SYNC are edge triggered 2 8 4 Interrupt Hi Lo Local Offset 0x006C The Interrupt Edge Register is an information only register which denotes all interrupt sources as edge triggered The Interrupt Hi Lo Register define each interrupt source as rising edge or falling edge For example a rising edge of the TX Empty source will generate an interrupt when the TX FIFO becomes empty Defining the source as falling edge will trigger an i
30. ter Slave 0 Channel will function as SPI Master Controller 1 Channel will function as SPI Slave Device D30 CS3 Enable D29 CS2 Enable D28 CS1 Enable D27 CSO Enable D26 Stop Tx on Empty 0 SPI will remain enabled D25 if Tx FIFO is empty 1 SPI will be disabled D25 0 if TX FIFO is empty 025 024 23 20 019 SPI Enable 0 SPI disabled 2 SPI enabled RESERVED LED Control Each Channel controls 2 LEDs on the back of the PCB See Section 5 3 for more detailed information about the LEDs RESERVED D18 8 Channel Status Bits 018 D17 D16 D15 D14 D13 D12 D11 D10 D8 D7 0 D7 D6 D5 D2 D1 DO Rx FIFO Underflow Tx FIFO Overflow Latched Rx FIFO Overflow Latched 1 Rx Data was lost due to Rx Overflow Note This bit is latched Write D16 1 to clear Rx FIFO Full Flag Lo 0 Rx FIFO Full Rx FIFO Almost Full Flag Lo 0 Rx FIFO Almost Full Rx FIFO Almost Empty Flag Lo 0 Rx FIFO Almost Empty Rx FIFO Empty Flag Lo 0 Rx FIFO Empty Tx FIFO Full Flag Lo 0 Tx FIFO Full Tx FIFO Almost Full Flag Lo 0 Tx FIFO Almost Full Tx FIFO Almost Empty Flag Lo 0 Tx FIFO Almost Empty Tx FIFO Empty Flag Lo 0 Tx FIFO Empty Channel Control Bits RESERVED Reset Channel Pulsed Note This value will automatically clear to 0 RESERVED Tx FIFO Reset Pulsed Note This value will automatically clear to 0 Rx FIFO Reset Pulsed Note This value will automatically c
31. to the Interrupt Register D31 16 TX Almost Full Flag Value Number of words from FIFO Full when the Almost Full Flag will be asserted i e FIFO contains FIFO Size Almost Full Value words or more D15 0 TX Almost Empty Flag Value Number of words from FIFO Empty when the Almost Empty Flag will be asserted 2 5 Channel Rx Almost Flags Local Offset 0x0014 0x0024 0x0034 0x0044 The Rx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs The Almost Full Empty Flags may be read as status bits in the Channel Control Status Register and are also edge triggered interrupt sources to the Interrupt Register D31 16 RX Almost Full Flag Value Number of words from FIFO Full when the Almost Full Flag will be asserted i e FIFO contains FIFO Size Almost Full Value words or more D15 0 RX Almost Empty Flag Value Number of words from FIFO Empty when the Almost Empty Flag will be asserted 2 6 Channel FIFO Local Offset 0 0018 0x0028 0x0038 0x0048 The Channel FIFO Register passes serial data to from the serial controller The same register is used to access both the Transmit FIFO writes and Receive FIFO reads D31 8 RESERVED D7 0 Channel FIFO Data 2 7 Channel Control Status Local Offset 0x001C 0x002C 0x003C 0x004C The Channel Control Status Register provides the reset functions and data transceiver enable controls and the FIFO Flag status for each channel D31 Mas
32. ut 1 11 w CS Enabled Output 1 11 w CS Disabled Output 0 D3 RESERVED D2 0 CLK Test Normal Input 10 Output 0 11 Output 1 2 10 Channel Pin Status Local Offset 0x0090 0x0094 0x0098 0x009C The Channel Pin Status Register allows the input state of all the IO pins to be monitored Output signals as well as inputs are included to aid in debug operation As the input signals are inputs from the cable the transceivers must be enabled before the Inputs are read Signals denoted Test are used in testing to monitor output drive input signals D31 D8 RESERVED D15 Spare Input D6 SPI MISO Input D5 SPI MOSI Input 04 CS3 Input D3 CS2 Input D2 CS1 Input D1 CSO Input DO SPI_CLK Input D7 Spare Output D6 SPI_MISO Output D5 SPI_MOSI Output D4 CS3 Output D3 CS2 Output D2 CS1 Output D1 CSO Output DO SPI_CLK Output 2 4 Programmable Clock Registers Local Offset 0x00A0 0x00A4 0x00A8 The Programmable Clock Registers allow the user to program the on board programmable oscillator and configure the channel clock post dividers As GSC should provide software routines to program the clock the user should have no need to access these registers See Section Appendix A for more information 2 12 Tx Count Register Local Offset 0x00B0 0x00B4 0x00B8 D31 16 Gap Bit Count Number of clocks between SPI words This can be used to ensure CS returns high between SPI words This field is on
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