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SN32F720 Series

1. BCLK 125 po SD msb 186 msb Isb msb BCLK Left WS Justified SD msb 155 msb sb msb BCLK Right WS Justified SD msb 155 msb lsb msb SONiX TECHNOLOGY LTD Page 145 Version 2 0 SON IX 14 5 2 125 FIFO OPERAION 14 5 2 1 MONO 8bit N 3 N 2 N 1 N N 7 N 6 N 5 4 16bit 1 N 3 N 2 24 bit N N 1 32 bit N 1 14 5 2 2 STEREO 8bit RIGHT 1 LEFT 1 RIGHT LEFT RIGHT 3 LEFT 3 RIGHT 2 LEFT 2 16bit RIGHT LEFT RIGHT 1 LEFT 1 24 bit LEFT RIGHT 32 bit LEFT RIGHT SONiX TECHNOLOGY CO LTD Page 146 SN32F720 Series 32 Bit Cortex M0 Micro Controller Version 2 0 N 7 1 SONIX Spy 14 6 123 REGISTERS Base Address 0 4001 000 14 6 1 125 Control register 12 CTRL Address Offset 0x00 Note START bit shall be set at last Bit Name 8121 Reserved CHLENGTH 4 0 Bit number of single channel CHLENGTH
2. RTC 0 0 TN 0 1 0 2 0 0 ALMCNT 0 1 0x2 Y 0x3 X 0 1 y 0x2 0 0 y 0x1 y 0x2 2 N v V A OxFFFFFFFD y OxFFFFFFFF 0x0 Cleared SW SONiX TECHNOLOGY CO LTD Page 94 Version 2 0 N 7 SONIX 10 4 BLOCK DIAGRAM EHS XTAL 128 ELS XTAL ILRC SRC SEL CLKSEL RTCEN SN32F720 Series 32 Bit Cortex M0 Micro Controller SECIE BEBE SECOND Interrupt RTC SECCNTV RTC SECCNT SECIF SECOND RTC ALMCNTV ALMIF RTC ALMCNT OVFIF SONiX TECHNOLOGY CO LTD Page 95 _ALMIE ALARM Interrupt OVFIE BE OVERFLOW Interrupt Version 2 0 7 1 SONIX 10 5 RTC REGISTERS Base Address 0x4001 2000 10 5 1 RTC Control register RTC_CTRL Address offset 0x00 Note RTCEN bit shall be set at last RTCEN RTC enable bit R W 0 Disable 1 Enable Reset SEC_CNT and ALM_CNT 10 5 2 RTC Clock Source Select register RTC_CLKS Address offset 0x04 Note SW shall disable RTC RTCEN 0 when changing the value of this register Reserved CR 3 RTC clock source selection HW will reset SEC_ CNT ALM_CNT when changing value 00 ILRC 01 ELS X TAL 10 Res
3. 80 64 BLOCK DIAGRAM o 81 8 5 TIMER OPERATION p Y 82 8 6 83 8 7 CTS2BNREGISTERS oon IDE dad u I ME ME IM 84 6 7 1 CT32Bn Timer Control register CT32Bn TMRCTRL n 0 1 94 8 7 2 CT32Bn Timer Counter register CI32Bn TC n 0 1 84 8 7 3 CT32Bn Count Control register CTI6Bn_CNTCTRL n 0 1 94 8 7 4 CT32Bn Match Control register CT32Bn_MCTRL N 0 1 65 SONiX TECHNOLOGY CO LTD Page 6 Version 2 0 N N SN32F720 Series 4 NS x 32 Bit Cortex M0 Micro Controller 8 7 5 CT32Bn Match register 0 3 CT32Bn_MRO 3 n 0 1 95 8 7 6 CT32Bn Capture Control register 32 CAPCTRL n 0 1 86 8 7 7 32 Capture 0 register 32 _ n 0 1 66 8 7 8 CT32Bn External Match register CT32Bn_EM n 0 1 86 8 7 9 CT32Bn PWM Control register CT32Bn_PWMCTRL n 0 1 87 8 7 10 CT32Bn Timer Raw
4. 110 12 52 MASTER RECEIVER MODE 110 12 59 ZARBIIRATION uita root tonat ibt bec 110 12568 uk u u un S yaa asia q 111 12 6 1 SLAVE TRANSMITTER MODE 111 1202 SLAVE RECEIVER axe 111 127 MONITOR 112 ui 112 127 2 LOSS OF ARBITRATION 112 12 PC REGISTERS 113 1284 n Control register I2Cn_CTRL 113 12 8 2 Status register I2Cn_STAT n 0 1 114 12 8 3 12 IX Data register 2 TXDATA n 0 1 115 12 8 4 12 RX Data register 2 RXDATA n 0 1 115 12 8 5 12 Slave Address 0 register I2Cn SLVADDRO n 0 1 115 12 8 6 12 Slave Address 1 3 register I2Cn SLVADDRI 3 0 1 115 12 6 7 I2C n SCL High Time register I2Cn_SCLHT n 0 1 115 12 8 8 I2CnSCL Low Time register I2Cn SCLLT n 0 1
5. 116 SONiX TECHNOLOGY CO LTD Page 8 Version 2 0 IN 7 SN32F720 Series NS x 32 Bit Cortex M0 Micro Controller 12 8 9 I2C n Timeout Control register IZCN_TOCTRL n 0 1 116 12 8 10 12 n Monitor Mode Control register IZCN_MMCTRL n 0 1 116 13 UNIVERSAL SYNCHRONOUS AND ASYNCHRONOUS SERIAL RECEIVER AND TRANSMITTER sasssssssessaseesesessssseesssessssssasssaesasesseesssssssessssessesesssssesssssssssesssssesssssse 117 OVERVIEW 117 E 117 13 3 PINDESCRIPTION 117 13 4 BLOCK DIAGRAM oc m 119 13 5 u ciate 120 13 51 RS 485 EIA 485 NORMAL MULTIDROP MODE NMM 120 13 5 2 RS 485 EIA 485 AUTO ADDRESS DETECTION AAD MODE 120 13 5 3 RS 485 EIA 485 AUTO DIRECTION CONTROL 120 13 54 RS485 EIA 485 DRIVER DELAY 120 13 5 59 RS485 EIA 485 OUTPUT INVERSION 121 13 560 RS485 EIA 485 FRAME STRUCTURE 121 136 BA
6. 24 2 2 1 OPERATION waqaq a d UR pun 24 224 SYSTICK USAGE HINTS AND TIPS 25 2 2 3 SYSTICK REGISTERS cieri 25 2 2 3 System Tick Timer Control and Status register SYSTICK 25 2 2 3 2 System Tick Timer Reload value register 5 5 25 2 2 8 3 System Tick Timer Current Value register SYSTICK VAL 26 2 2 3 4 System Tick Timer Calibration Value register SYST CALIB 26 2 3 NESTED VECTORED INTERRUPT CONTROLLER NV IC een einen nnn 27 2 3 1 INTERRUPT AND EXCEPTION VECTORS a 27 2 9 4 NVIG REGISTER T Mr P 28 2 3 2 1 IRQO 31 Interrupt Set Enable Register NVIC_ISER 28 2 3 2 2 TRQO 31 Interrupt Clear Enable Register NVIC eee 28 2 3 2 3 IRQO 31 Interrupt Set Pending Register NVIC_ISPR 28 2 3 2 4 0 31 Interrupt Clear Pending Register NVIC eee 28 2 3 2 5 IRQO 31 Interrupt Priority Register NVIC IPRn 150 7 29 2 49 APPLICATION INTERRUPT AND RESET CONTROL AIRC eere 29 23 COE OP TION FABLE 30 COREREGISTE
7. 19 7 7 1 CTI6Bn Timer Control register CT16Bn_TMRCTRL n 0 1 75 7 7 2 CT16Bn Timer Counter register CT TGBn TC n 0 1 75 7 7 3 16 Count Control register CTI6Bn_CNTCTRL n 0 1 75 7 7 4 CTI6Bn Match Control register 16 MCTRL n 0 1 76 7 7 5 16 Match register 0 3 CT16Bn_MRO 3 n 0 1 77 7 7 6 16 Capture Control register CTI6Bn_CAPCTRL n 0 1 77 7 7 7 CTI6Bn Capture 0 register 16 _ n 0 1 77 7 7 8 CTI6Bn External Match register CT16Bn EM n 0 1 77 7 7 9 CTI6Bn PWM Control register CT16Bn PWMCTRL n 0 1 78 7 7 10 16 Timer Raw Interrupt Status register 16 RIS n 0 1 79 7 711 CTI6Bn Timer Interrupt Clear register 6 IC n 0 1 79 8 32 BIT TIMER WITH CAPTURE FUNCTION 80 8 1 OVERVIEW 80 2 FEATURES u a 80 8 3 PIN DESCRIETION
8. 149 14 6 6 125 Interrupt Clear register I2S_IC eR 149 146 7 185 FIFO register 125 149 15 150 L OVERVIEW 150 15 2 EMBEDDED FLASH MEMIOGNRY E AREE 150 I3 eS 150 15 4 ORGANIZATION una aa nn una RR 151 15 35 READ mM m E 151 15 6 PROGRAMIJERASE 151 15 7 EMBEDDED BOOT LOADER 151 SONiX TECHNOLOGY CO LTD Page 10 Version 2 0 N 7 SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller 15 8 FLASH MEMORY CONTROLLER FMO 152 15 81 CODESECURITY CS T ONERE 152 4102 PROGRAM FLASH MEMORY aan 132 L30 ERASE e ere 153 15 8 3 1 PAGE ERASE uu umasa r H 153 15 832 153 15 9 READ PROTECTION uu u L bitch sm du RIP 153 FMC REGISTERS aE e 154 15 10 1 Flash Status register FLASH_STATUS 154 15 10 2 Fla
9. lame Description Attribute 312 Reseved Rl DL 3 0 Data length DL 3 0 1 0000 0001 Reversed 0010 data length 3 1110 data length 15 1111 data length 16 7 6 FRESET 1 0 SSP FSM and FIFO Reset bit 00 No effect 01 Reserved 10 Reserved 11 Reset finite state machine and FIFO BUF_BUSY 0 data in shift BUF is cleared 1 TX_FULL 0 RX EMPTY 1 RX FULL 0 and data in FIFO is cleared This bit will be cleared by HW automatically 5 Reserved 0 SPI 1 SSI Master Slave selection bit 0 Act as Master 1 Actas Slave Le Slave data output disable bit ONLY used in slave mode BEN 0 Enable slave data output 1 Disable slave data output MISO 0 0 Disable 1 Data input from data output 0 Disable 1 Enable 11 5 2 SSP n Control register 1 SSPn CTRL1 n 0 1 Address Offset 0x04 Bii Name Description 313 Reseved R O CPHA Clock phase for edge sampling R W 0 Data changes at clock falling edge latches at clock rising edge when CPOL 0 Data changes at clock rising edge latches at clock falling edge when CPOL 1 1 Data changes at clock rising edge latches at clock falling edge when CPOL 0 Data changes at clock falling edge latches at clock rising edge when CPOL 1 SONiX TECHNOLOGY CO LTD Page 104 Version 2 0 SON IX CPOL Clock polarity selection bit 0 SCK idles at Low level 1 SCK idles at High level
10. 60 5 3 2 GPIO Port n Mode register GPIOn n 0 1 2 3 60 5 3 3 GPIO Port n Configuration register CFG n 0 1 2 3 60 5 3 4 GPIO Port n Interrupt Sense register IS n 0 1 2 3 61 5 3 5 GPIO Port n Interrupt Both edge Sense register GPIOn IBS n 0 1 2 3 61 5 3 6 GPIO Port n Interrupt Event register n 0 1 2 3 62 5 3 7 GPIO Port n Interrupt Enable register GPIOn IE lt 01 2 3 62 5 3 6 GPIO Port n Raw Interrupt Status register GPIOn RIS lt 01 2 3 62 5 3 9 GPIO Port n Interrupt Clear register GPIOn IC n 0 1 2 3 62 5 3 10 GPIO Port n Bits Set Operation register GPIOn BSET lt 0 1 2 3 62 5 3 11 GPIO Port n Bits Clear Operation register GPIOn BCLR n 0 1 2 3 63 5 3 12 Port n Open Drain Control register ODCTRL n 0 1 2 3 63 10 CHANNEL ANALOG TO DIGITAL CONVERTOR ADO 65 6 1 OVERVIEW unos 65 6 2 ADC CONVERTING TIME lvi ek
11. USARTn_LC SONiX TECHNOLOGY CO LTD Page 119 Version 2 0 NI M 1 N N x 32 Bit 2 Honc 13 5 EIA 485 RS 485 MODES The RS 485 EIA 485 feature allows the USART to be configured as an addressable slave receiver The addressable slave receiver is one of multiple slaves receivers controlled by a single master The USART master transmitter will identify an address character by setting the parity 9th bit to 1 For data characters the parity bit is set to 0 Each USART slave receiver can be assigned a unique address The slave can be programmed to either manually or automatically reject data following an address which is not theirs In RS 485 mode PS bits in USARTn LC register shall be selected as forced 1 stick parity Address or forced stick 0 parity Data by SW In addition the word length shall be 8 bits by setting WLS bits in USARTn LC register to 11b by SW 13 5 1 RS 485 EIA 485 NORMAL MULTIDROP MODE Setting the NMMEN bit in USARTn RS485CTRL register enables this mode In this mode an address is detected when received byte causes the USART to set the parity error and generate an interrupt If the receiver is disabled 0 in USARTn RS485CTRL register any received data bytes will be ignored and will not be stored in the RXFIFO When an address byte is detected parity bit 1 it will be placed into the RXFIFO and a parity error PE Interrupt will be generated The processor c
12. Frequency from the PLLCLKSEL multiplexer Frequency of the Voltage Controlled Oscillator VCO 156 to 320 MHz Feikour Frequency of PLL output P System PLL post divider ratio controlled by PSEL bits in PLL control register SYSO PLLCTRL System PLL front divider ratio controlled by FSEL bits in PLL control register SYSO0 PLLCTRL M System PLL feedback divider ratio controlled by MSEL bits in PLL control register SYSO PLLCTRL vy v v v v v To select the appropriate values for M P and F it is recommended to follow these constraints 10MHz lt lt 25MHz 150MHz lt Fvco lt 330MHz 2 lt M lt 31 F 1 or2 P 6 8 10 12 or 14 duty 50 2 5 20MHz 30MHz 40MHz 50MHz 24MHz 36MHz 48MHz 32MHz 22MHz 24MHz 50MHz with jitter lt 500 ps OO orm SONiX TECHNOLOGY CO LTD Page 40 Version 2 0 ow SN32F720 Series S v NS 32 Bit Micro Controller 3 2 3 EXTERNAL CLOCK SOURCE 3 2 3 1 External High speed EHS Clock External high clock includes Crystal Ceramic modules The start up time of is longer The oscillator start up time decides reset time length 4MHz Crystal 4MHz Ceramic 3 2 3 CRYSTAL CERAMIC Crystal Ceramic devices are driven XIN XOUT pins For high normal low frequency the driving currents are different XIN CRYSTAL xou M U oH 20pF T 20pF VDD
13. will cause to be loaded with the contents of TC 0 Disable 1 Enable 8 7 7 CT32Bn Capture 0 register CT32Bn CAPO nz0 1 Address Offset 0x2C Each Capture register is associated with a device pin and may be loaded with the counter timer value when a specified event occurs on that pin The settings in the Capture Control register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges 31 0 CAPO 31 0 Timer counter capture vae o R 0 8 7 8 CT32Bn External Match register CT32Bn EM 0 1 Address Offset 0x30 The External Match register provides both control and status of the external match pins CT32Bn_PWMCTRL 3 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Reserved EMC3 1 0 Determines the functionality of 32 PWMS3 00 Do Nothing 01 CT32Bn PWNG pin is LOW 10 2 PWMS pin is HIGH 11 Toggle 2 PWMS pin SONiX TECHNOLOGY CO LTD Page 86 Version 2 0 N N 9 Y SN32F720 Series E 32 Bit Cortex M0 Micro Controller EMC2 1 0 Determines the functionality of CT32Bn_PWM2 00 Do Nothing 01 2 2 pin is LOW 10 2 2 pin is HIGH 11 Toggle 2 PWM e pin 7 6 1 1 0 Determines the functionality of CT32Bn_PWM1
14. 2252922 lt lt lt lt lt gt Z lt lt lt lt lt 0 CN N N N NAN a n SONiX TECHNOLOGY CO LTD Page 16 SN32F720 Series 32 Bit Cortex M0 Micro Controller P1 11 CLKOUT P1 10 CT16B1_PWM1 URTSO P1 9 CT16B1 PWMO USCLKO P1 8 CT16B1 CAPO UCTSO P1 7 UTXDO CT32BO0 1 P1 6 URXDO CT32BO0 PWMO P1 5 CT32BO P1 4 CT32B1_PWM3 DPDWAKEUP P1 3 CT32B1_PWM2 l2SWS P1 2 CT32B1_PWM1 l2SBCLK P1 1 CT32B1 PWMO I2ZSSDA 1 0 2 1 CAPO I2SMCLK Version 2 0 N N 7 SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller SN32F726J QFN 46 pins 42 ao 2 2995 ozuo zsggos z z E O s E lt F Eeg zkad sgaos 5 xxmJg3225223252326 5 Qu O Q O c gt gt gt gt D D 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P0 2 CT16BO CAPO SCL1M 9 32 P1 9 CT16B1 PWMO USCLKO P0 3 CT32B0_PWM2 SDA1 2 31 P1 8 CT16B1 CAPO UCTSO P0 4 SCLO 3 30 P1 7 UTXDO CT32BO PWMf1 P0 5 SDAO 4 29 P1 6 URXD0 CT32B0O_PWMO 0 6 5 5 SN32F726J 28 P1 5 CT32BO CAPO PO 7 SELO 6 27 P1 4 CT32B1 PWMS DPDWAKEUP P0 8 MISOO CT16BO 7 26 P1 3 CT32B1_PWM2 l2SWS P0 9 MOSIO CT16BO 1 8 25 P1 2 CT32B1 PWM1 I2SBCLK P0 10 SWCLK CT16BO 2 9 24 P1 1 CT32B1 PWMO I2
15. Resned clear enable x 0 to 11 0 No effect on Pn x 1 Clear Pn x 5 3 12 GPIO Port n Open Drain Control register GPIOn_ODCTRL n 0 1 2 3 Address offset 0x2C Several I Os have built in open drain function and must be set as output mode when enable open drain function Open drain external circuit is as following MCU1 MCU2 VG Pull up Resistor Open drain The external pull up resistor is necessary The digital output function of I O only supports sink current capability so the open drain output high is driven by pull up resistor and output low is sunken by MCU s pin hem Pn7OC n l P1 7 open drain control bit 0 Disable 1 Enable HW set P1 7 as output mode automatically n 0 2 3 Reserved Pn6OC 1 1 6 open drain control bit 0 Disable 1 Enable HW set P1 6 as output mode automatically n 0 2 3 Reserved 5 0 P0 5 open drain control 0 Disable 1 Enable HW set P0 5 as output mode automatically n 1 3 Reserved SONiX TECHNOLOGY CO LTD Page 63 Version 2 0 N WY SN32F720 Series SS Q NN 1 x 32 Bit Cortex M0 Micro Controller P0 4 open drain control bit 0 Disable 1 Enable HW set P0 4 as output mode automatically Reserved P0 3 open drain control bit 0 Disable 1 Enable HW set P0 3 as output mode automatically n 1 3 Reserved 4 0 P0 2 open drain control bit 0 Disable
16. FIFOUDFIEN FIFO underflow interrupt enable bit 0 Disable 1 Enable 14 6 5 125 Raw Interrupt Status register I2S_RIS Address Offset 0x10 FIFOTHIF FIFO threshold interrupt flag 0 No FIFO threshold interrupt 1 FIFO threshold triggered FIFOOVIF FIFO overflow interrupt flag 0 No FIFO overflow 1 FIFO overflow FIFO is full and still being written FIFOUDIF FIFO underflow interrupt flag 0 No FIFO underflow 1 FIFO underflow FIFO is empty and still being read 14 6 6 125 Interrupt Clear register 125 IC Address Offset 0x14 ENT 14 6 7 125 register 125 Address Offset 0x18 FIFOI31 0 8 x 32 bit FIFO Write Only if act Transmitter Read Only if act as Receiver SONiX TECHNOLOGY LTD Page 149 Version 2 0 N SN j SN32F720 Series N x 32 Bit Cortex M0 Micro Controller 1 5 FLASH 15 1 OVERVIEW The SN32F700 series MCU integrated device feature in system programmable ISP FLASH memory for convenient upgradeable code storage The FLASH memory may be programmed via the SONIX 32 bit MCU programming interface or by application code for maximum flexibility The SN32F700 series MCU provides security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH memory gt MCU is stalled during Flash program and erase operations although peripherals Timers I O PWM etc remain active
17. a future frame to this register when EUM TX FULL 2 0 in SSPn STAT register TX FIFO is not full If the TX FIFO was previously empty and the SSP controller is not busy on the bus transmission of the data will begin immediately Otherwise the data written SONiX TECHNOLOGY CO LTD Page 106 Version 2 0 N N 9 Y SN32F720 Series D D 32 Bit 0 Micro Controller to this register will be sent as soon as all previous data has been sent and received Read SW can read data from this register when RX_EMPTY 0 in SSPn STAT registe Rx FIFO is not empty When SW reads this register the SSP controller returns data from the least recent frame in the RX FIFO If the data length is less than 16 bit the data is right justified in this field with higher order bits filled with Os SONiX TECHNOLOGY LTD Page 107 Version 2 0 N j SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller 2 12 1 OVERVIEW 2 bus is bidirectional for inter IC control using only two wires Serial Clock Line SCL and Serial Data line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The 2 is a
18. 340 Reseved 00008 o ADC raw interrupt flag x 0109 0 Read interrupt on AINx PAN Write gt Write 0 to the corresponding bit will clear the bit and reset the Interrupt if the corresponding bit is set 1 Interrupt requirements met AINx ADC conversion SONiX TECHNOLOGY CO LTD Page 70 Version 2 0 N M 2F72 1 SONIX 7 16 WITH CAPTURE FUNCTION 71 OVERVIEW Each Counter timer is designed to count cycles of the peripheral clock PCLK an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt In PWM mode up to three match registers can be used to provide a single edge controlled PWM output on the match output pins 2 FEATURES 7 gt Two 16 bit counter timers gt Counter or timer operation Two 16 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt The timer value may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge gt Four 16 bit match registers that
19. If no NACK is sent the next byte may be transmitted immediately after the last guard bit If the NACK is sent the transmitter will retry sending the byte until successfully received or until the SCICTRL retry limit has been met Clock Next transfer or First retry d vite J bits vits Paring Veg ME M 4 P L L LI 2 Stop bits Extra guard The smart card must be set up with the following considerations e Program SYS1 PRST register so that the USART is not continuously reset Program USARTnPRE bits in SYS1 register for an initial USART frequency of 3 58 MHz f necessary program the USARTn DLM and USARTn DLL to 00 and 01 respectively to pass the USART clock through without division Program USARTn LC register for 8 bit characters parity enabled even parity Program USARTn SCICTRL register to enable the smart card feature with the desired options and HW enables a USART TXD function automatically Setup one or more timer s to provide timing as needed for ISO 7816 startup Program USARTnCLKEN bit in SYS1 AHBCLKEN register to enable the USART clock Thereafter SW should monitor card insertion handle activation wait for answer to reset as described in ISO7816 3 SONiX TECHNOLOGY CO LTD Page 128 Version 2 0 NI M N N Eu x 32 Bit 2 13 11 SYNCHRONOUS MODE The synchronous mode is sel
20. port input leakage current llekg I2C bus pins 0 2 0 3 P0 4 and 0 5 Vin Vdd 2 ua Output Voltage nm Standard port and RESET pins Vo Vdd 05V 5 mA High drive output pin Vdd 0 5V 12 20 mA P0 0 P0 5 1 6 1 8 E Low level output sink current Standard port and RESET pins Vss 0 5V 5 m ADC ADC Operating Voltage Vc 36 AINO AIN11 input voltage 0 v ADGreference Voltage Va 25 v ADCenabletime Ready tostartconvertaftersetADENB 1 __ 10 ws current consumption lec Vdd 33MADS O o S o aof wA ADC Clock Frequency Faoow Vdd 33V Wm ADC Conversion Cycle Time Fanon VDD 25V 36V wes SONiX TECHNOLOGY CO LTD Page 159 Version 2 0 I O High level output source current SON IX FLASH SN32F720 Series 32 Bit Cortex M0 Micro Controller ADC Sampling Rate Fiowe Vdd 33V 1 15 KHz Differential Nonlinearity DNL Vdd 3 eV AVREFH 24V integral Nonlinearity INL_ Vdd 3 6v AVREFH 24v NomissingCode _ Vdd 3 6v AVREFH 24v 12 ADC ofset Voltage veo _ j s l 8 mV Supply Voltage v _ Endurancetime Ta Erase Program O 2 Cycle Erase current les _ 25
21. 2 0 2 FLASH 8KB SRAM 2KB POWER REGULATOR CLOCK GENERATION Clocks AHB LITE BUS VCORE FLASH ROM BOOT LOADER 4KB POWER CONTROL SYSTEM FUNCTIONS Controls AHB TO APB BRIDGE WDT APB BUS RTC GPIO 12 bit SAR ADC 32 bit TIMER 0 with 4 PWM 32 bit TIMER 1 with 4 PWM 16 bit TIMER 0 with 3 PWM 16 bit TIMER 1 with 2 PWM SONiX TECHNOLOGY CO LTD Page 14 VDD 1 8V 3 6V RESET GPIO ports PIOO 0 11 PIO1 0 11 PIO2 0 9 0 8 AINO AIN9 CT32B0 PWM 3 0 CT32B0_CAPO CT32B1_PWM CT32B1 CAPO 16 0 PWM 16 0 CAPO CT16B1 PWM CT16B1 CAPO Version 2 0 3 0 2 0 1 0 SONIN SN32F720 Series 32 Bit Cortex M0 Micro Controller 1 3 CLOCK GENERATION BLOCK DIAGRAM AHB clock for AHB to APB bridge to AHB matrix to FCLK HCLK and System Timer to SYS and to PMU AHB clock for SSPO SSP0_PCLK SSPO SSPO Clock Prescaler 1 2 4 8 16 clock source register block AHB clock for SSP1 m PCLK x SSP1 SSP1 ord gt clock source register block WDTCLKEN PLLCLKout CLKOUT CLKOUT lt _ Prescaler 11 2 4 512 AHB clock for WDT WDT WDT_PCLK Clock Prescaler gt WBT 1 2 4 8 1
22. 66 6 3 ADCCONTROL NOTICE uuu 67 6 3 1 ADC SIGNAL P 67 6 3 2 ADC PROGRAM mM RE 67 SONiX TECHNOLOGY CO LTD Page 5 Version 2 0 IN 7 SN32F720 Series N N 32 Bit Cortex M0 Micro Controller 64 ADC CRC IU ior 67 6 5 ADC REGISTERS uu unta n u mM D aod cee 68 6 5 1 ADC Management register ADC_ADM a 68 6 5 2 ADC Data register _ADB1 05 380 esasaqasasqakaqaqasanaasasqasshassasqpasasaqasqqassaapayassqsayhapassaassasa 68 6 5 3 Port 2 Control register ADC_P2CON 69 6 5 4 ADC Interrupt Enable register ADC_IE a 70 6 5 5 ADC Raw Interrupt Status register ADC_RIS 70 7 16 BIT TIMER WITH CAPTURE FUNCTION 71 7 1 OVERVIEW vL tune tsi Su 71 2 FEATURES aan 71 7 3 PIN DESCRIPTION 71 LA BLOCKDIAGRAM HEUTE 72 7 5 TIMER OPERATION c 73 7 6 PWM Zum E Ge 74 du CTI6BNREGISTERS C
23. 7 7 8 CT16Bn External Match register CT16Bn EM nz0 1 Address Offset 0x30 The External Match register provides both control and status of CT16Bn_PWM 1 0 If the match outputs are SONiX TECHNOLOGY CO LTD Page 77 Version 2 0 SON IX configured PWM output the function of the external match registers is determined the PWM rules Bit Name 31 10 Reserved EMC2 1 0 Determines the functionality of CT16Bn_PWM2 00 Do Nothing 01 CT16Bn_PWM2 pin is LOW 10 CT16Bn PWMe pin is HIGH 11 Toggle CT16Bn PWM e pin EMC1 1 0 Determines the functionality of CT16Bn_PWM1 00 Do Nothing 01 CT16Bn_PWM1 pin is LOW 10 CT16Bn_PWM1 pin is HIGH 11 Toggle CT16Bn_PWM1 Reseved and also drive the state of 16 PWM 2 output and also drive the state of CT16Bn_PWM1 output and also drive the state of CT16Bn PWMO output 7 7 9 CT16Bn PWM Control register 16 PWMCTRL nz0 1 Address Offset 0x34 EMCO 1 0 Determines the functionality of 16 PWMO 00 Do Nothing 01 16 PWMO pin is LOW 10 CT16Bn PWMO pin is HIGH 11 Toggle CT16Bn PWMO The PWM Control register is used to configure the match outputs as PWM outputs Each match output can be in dependently set to perform either as PWM output or as match output whose function is controlled by CT16Bn EM register For each timer a maximum of three single edge controlled PWM outputs can be selected on the CT16Bn PWM
24. I Load data Private Peripheral SYSTICK_VAL Bus 24 bit down counter clock Ref clock CLKSOURCE Fix to 1 SYSTICK_CTRL COUNTFLAG TICKINT gt SysTick interrupt gt When SysTick timer is enabled the timer counts down from the current value SYST VAL to zero reloads to the value in the SysTick Reload Value Register SYST_LOAD on the next clock edge then decrements on subsequent clocks When the counter transitions to zero the COUNTFLAG status bit is set to 1 The COUNTFLAG bit clears on reads Note When the processor is halted for debugging the counter does not decrease SONiX TECHNOLOGY CO LTD Page 24 Version 2 0 N SN32F720 Series S Q x 32 Bit Cortex M0 Micro Controller 2 2 2 SYSTICK USAGE HINTS AND TIPS The interrupt controller clock updates the SysTick counter Some implementations stop this clock signal for low power mode If this happens the SysTick counter stops Ensure SW uses word accesses to access the SysTick registers The SysTick counter reload and current value are not initialized by HW This means the correct initialization sequence for the SysTick counter is 1 Program the reload value in SYSTICK_LOAD register 2 Clear the current value by writing any value to SYSTICK_VAL register 3 Program the Control and Status SYSTICK_CTRL register 2 2 3 SYSTICK REGISTERS 2 2 3 1 System Tick Timer Contr
25. I2SBCLK 125 Bit Clock pin P1 3 Port 1 3 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CT32B1_PWM2 PWM output 2 for CT32B1 I2SWS 125 Word Select pin 1 4 Port 1 4 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function CT32B1_PWM3 CT32B1 PWM output 3 DPDWAKEUP Deep power down mode wake up pin P1 5 Port 1 5 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CT32B0_CAP0 CT32B0 Capture input 0 P1 6 Port 1 6 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode URXDO USARTO Receiver input pin 2 0 PWMO CT32B0 PWM output 0 P1 7 Port 1 7 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode UTXDO USARTO Transmitter output pin 2 0 PWM1 CT32B0 PWM output 1 P1 8 Port 1 8 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CT16B1 CT16B1 Capture input 0 UCTSO USARTO Clear To Send input pin P1 9 Port 1 9 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CT16B1 PWMO CT16B1 PWM output 0 USCLKO USARTO Clock pin P1 10 Port 1 10 bi direction pin Schmitt trigg
26. lb DER DR NU TEE nU 103 113 SSP REGISTERS ca pA Dp Loc OM asd 104 12 SSP n Control register 0 SSPn_CTRLO n 0 1 104 11 5 2 55 n Control register I 55 _ 1 1 n 0 1 104 1153 SSP n Clock Divider register SSPn_CLKDIV n 0 1 105 1154 SSP n Status register SSPn_STAT n 0 I 105 11 352 SSP n Interrupt Enable register SSPn_IE n 0 1 105 11 5 6 88 n Raw Interrupt Status register SSPn_RIS 0 1I 106 11 5 7 SSP n Interrupt Clear register 55 _1 n 0 I 106 1126 SSP n Data register SSPn_DATA n 0 1 106 12 PA O O E EA AAE I EEA 108 12 1 OVERVIEW rcm 108 22 ance sa dta 108 12 5 DESCRIPTION Z u au nu nan REES 109 124 WAVBCHARACIBRISTIUS 109 145 BOMASTERMODES uu uuu z Suan 110 12 5 1 MASTER TRANSMITTER MODE
27. Stop MR2 TC will stop and CEN bit will be cleared if MR2 matches TC 1 Enable Enable reset TC when MR2 matches TC 1 Enable Stop MR1 TC will stop and CEN bit will be cleared if MR1 matches TC 1 Enable Enable reset TC when MR1 matches TC 1 Enable Enable generating an interrupt when MR1 matches the value in the TC 1 Enable Stop MR0 TC will stop and CEN bit will be cleared if MR0 matches TC 1 Enable Enable reset TC when MR0 matches TC 1 Enable Enable generating an interrupt when MR2 matches the value in the TC MR2IE 0 Disable R 1 Enable Enable generating an interrupt when MR0 matches the value in the TC MROIE 0 Disable R W 1 Enable SONiX TECHNOLOGY CO LTD Page 76 Version 2 0 N N Y SN32F720 Series 32 Bit Cortex M0 Micro Controller 7 7 5 CT16Bn Match register 0 3 CT16Bn 0 3 nz0 1 Address Offset 0x18 0x1C 0x20 0x24 The Match register values are continuously compared to the Timer Counter TC value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the CT16Bn_MCTRL register _ Bi Description Attribute 31 16 Reserved 8 R 0 15 0 MR 5 0 Timer counter matchvaue L RW 0 7 7 6 CT16Bn Capture Control register CT16Bn_CAPCTRL n 0 1 Address Offset 0x28 The Capture Control register is
28. XT _ 1 1 X j 144 0 0 p x gp E f 7 G The Auto CTS function typically eliminates the need for CTS interrupts When flow control is enabled a UCTS state change does not trigger host interrupts because the device automatically controls its own transmitter Without Auto CTS the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result Idle Status UTXD Start Stop Start Stop Start Stop UCTS During transmission of the second character the UCTS signal is negated The third character is not sent thereafter The USART maintains 1 on UTXD as long as UCTS is negated high As soon as UCTS is asserted transmission resumes and a start bit is sent followed by the data bits of the next character 13 8 AUTO BAUD FLOW 13 8 1 AUTO BAUD The USART auto baud function can be used to measure the incoming baud rate based on the AT protocol Hayes command If enabled the auto baud feature will measure the bit time of the receive data stream and set the divisor latch registers USARTn DLM and USARTn DLL accordingly Auto baud function is started by setting the START bit in USARTn ABCTRL register and can be stopped by clearing the START bit The START bit will clear once auto baud has finished and reading the bit will return the status of auto baud pending finished When auto baud function is started FIFO will be cleared not available to write the TX
29. ale source selection bit 0 MCLK source of master is from 125 PCLK 1 MCLK source of master is from GPIO MCLK output enable bit 0 Disable 1 Enable MCLKDIV 2 0 MCLK divider 0 MCLK MCLK source 1 MCLK MCLK source 2 2 MCLK MCLK source 4 n MCLK MCLK source 2 n n gt 0 14 6 3 125 Status register I28 STATUS Address Offset 0x08 31 16 Reseved FIFOLVI3 0 FIFO used level 19 01 0000 0 8 is used Empty 0001 1 8 FIFO is used 0010 2 8 is used 1000 8 8 FIFO is used Full Other Reserved FIFOEMPTY FIFO empty flag 0 FIFO is not empty 1 FIFO is empty Data read from FIFO will be zero FIFOFULL FIFO full flag OEY 0 FIFO is not full 1 FIFO is full Write operation to FIFO will be ignored FIFOTHF FIFO threshold flag 0 FIFOLV gt FIFOTH if act as Transmitter FIFOLV x FIFOTH if act as Receiver 1 FIFOLV FIFOTH if act as Transmitter FIFOLV FIFOTH if act as Receiver _52 Reserved a Current channel status 0 Current channel is Left channel 1 Current channel is Right channel 0 No 125 interrupt 1 125 interrupt occurs 14 6 4 125 Interrupt Enable register 125 Address Offset 0x0C SONiX TECHNOLOGY LTD Page 148 Version 2 0 kq wv SN32F720 Series S Q x 32 Bit Cortex M0 Micro Controller FIFOTHIEN FIFO threshold interrupt enable bit 0 Disable 1 Enable L FIFO overflow interrupt enable bit 0 Disable 1 Enable
30. 1 Enable HW set P0 2 as output mode automatically n 1 3 Reserved n 0 1 open drain control bit 0 Disable 1 Enable HW set 1 as output mode automatically P0 0 open drain control bit 0 Disable 1 Enable HW set P0 0 as output mode automatically n 1 3 Reserved SONiX TECHNOLOGY CO LTD Page 64 Version 2 0 N N 7 SN32F720 Series N N 32 Cortex M0 Micro Controller 10 CHANNEL ANALOG TO DIGITAL CONVERTOR ADC 61 OVERVIEW This analog to digital converter has 10 input sources with up to 4096 step resolution to transfer analog signal into 12 bits digital data The sequence of ADC operation is to select input source AINO AIN9 at first then set GCHS and ADS bit to 1 to start conversion When the conversion is complete the ADC circuit will set EOC bit to 1 and final value output in ADB register The ADC is 10 channel SAR structure and 12 bit resolution Build in P2CON to set pure analog input pin It is necessary to set AIN pins as input mode without pull up resistor by program Use CHS 3 0 to select AIN and GCHS enables global ADC channel the analog signal inputs to ADC engine The ADC reference high voltage includes two source one is internal Vdd AVREFHSEL 0 and the other one is external reference voltage input pin from P2 0 pin AVREFHSEL 1 The ADC resolution can be selected 8 bit or 12 bit through ADLEN bit in ADR register The ADC converting rate can be selected by ADCKS 1
31. HCLK 16 Other Reserved 3 Reserved RR USARTO clock source prescale value USARTOPRE 2 0 ano HCLK 4 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 3 4 4 Peripheral Reset register SYS1_PRST Address Offset 0 0 All bits are cleared by HW automatically after setting as 1 Reserved WDTRST RTCRST reset 0 No effect 1 Reset WDT RTC reset 0 No effect 1 Reset RTC 125 reset 0 No effect 1 Reset 125 12 0 reset 0 No effect 1 Reset 2 0 I2C1 reset 0 No effect 1 Reset 12 1 I2CORST l2C1RST w USARTIRST SONiX TECHNOLOGY CO LTD A End 19 18 Page 52 Version 2 0 N N 9 Y SN32F720 Series IS 32 Bit Cortex M0 Micro Controller T pge L EN 1 Reset USART1 0 No effect 1 Reset USARTO RR 15 14 Reserved SSP1RST SSP1 reset R W 0 No effect 1 Reset SSP1 SSPORST SSPO reset R W 0 No effect 1 Reset SSP0 ADCRST ADC reset R W 0 No effect 1 Reset ADC 10 Reserved Md 0 1 Reset CT32B1 0 1 Reset CT32B0 0 No effect 1 Reset CT16B1 0 No effect 1 Reset CT16B0 5 4 Reseved 0 No effect 1 Reset GPIO port 3 0 No effect 1 Reset GPIO port 2 0 No effect 1 Reset GPIO port 1 GPIOPORST GPIO port 0 reset R W 0 No effect 1 Reset GPIO port 0 SONiX TECHNOLOGY CO LTD Page 53 Version 2 0 N j SN32F720 Series S N N 32 Cortex
32. MLSB MSB LSB selection bit 0 MSB transmit first 1 LSB transmit first 11 5 3 SSP n Clock Divider register SSPn CLKDIV n 0 1 Address Offset 0x08 908 r nn a SSPn clock divider 0 SCK SSPn PCLK 2 1 SCK SSPn_PCLK 4 2 SCK SSPn_PCLK 6 X SCK SSPn PCLK 2X 2 11 5 4 SSP n Status register SSPn_STAT n 0 1 Address Offset 0x0C 317 Reseved __ 0 Data RX FIFO lt 4 1 Data in RX FIFO gt 4 TA _ 0 Data in TX FIFO gt 4 1 Data in TX FIFO lt 4 0 SSP controller is idle 1 SSP controller is transferring 0 RX FIFO is NOT full 1 RX FIFO is full 0 is 1 RX FIFO is empty 0 TX FIFO is NOT full 1 TX FIFO is full TX EMPTY TX FIFO empty flag 0 TX FIFO is NOT empty In Master mode the transmitter will begin to transmit automatically 1 TX FIFO is empty 11 5 5 SSP n Interrupt Enable register SSPn_IE n 0 1 Address Offset 0x10 This register controls whether each of the four possible interrupt conditions in the SSP controller is enabled TXHEIE TX half empty interrupt enable RW 0 Disable 1 Enable RXHFIE RX half full interrupt enable R W 0 Disable 1 Enable SONiX TECHNOLOGY CO LTD Page 105 Version 2 0 SON IX edet RXTOIE RX time out interrupt enable 0 Disable 1 Enable RXOVFIE RX Overflow interrupt enable 0 Disable 1 Enable 11 5 6 SSP n Raw Interrupt St
33. NS 32 Bit Cortex M0 Micro Controller Bit Name Description 3112 Reseved 1 0 ADB11 ADB4 bits for 8 bit ADC ADB11 ADBO bits for 12 bit ADC The AIN s input voltage v s ADB s output data 0 4096 VREFH 1 4096 VREFH 4094 4096 VREFH 4095 4096 VREFH For different applications users maybe need more than 8 bit resolution but less than 12 bit ADC converter First the AD resolution must be set 12 bit mode and then to execute ADC converter routine Then delete the LSB of ADC data and get the new resolution result The table is as following ADB10 8 bit 9 bit 10 bit 11 bit 12 bit Selected X Delete Note The initial value of ADC buffer ADB after reset is unknown 6 5 3 Port 2 Control register P2CON Address Offset 0x08 The Port 2 is shared with ADC input function Only one pin of port 2 can be configured as ADC input in the same time by ADM register The other pins of port 2 are digital I O pins Connect an analog signal to COMS digital input pin especially the analog signal level is about 1 2 VDD will cause extra current leakage In the power down mode the above leakage current will be a big problem Unfortunately if users connect more than one analog input signal to port 2 will encounter above curren
34. This register provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during a USARTn Il register access If an interrupt occurs during a USARTnR 1 register access the interrupt is recorded for the next USARTn I register access 3111 Reseved Rt TXERRIF TXERR interrupt flag 0 TXERR has not occurred 1 TXERR has occurred and interrupt is enabled ABTOIF Auto baud time out interrupt flag 0 Auto baud has not timed out 1 Auto baud has timed out and interrupt is enabled SONiX TECHNOLOGY LTD Page 131 Version 2 0 SON IX pae ABEOIF End of auto baud interrupt flag 0 Auto baud has not finished 1 Auto baud has finished successfully and interrupt is enabled FIFOEN Equivalent to FIFOEN bit in USARTn_FIFOCTRL register R 1 Gwi s aa lt s r INTID 2 0 R o Interrupt identification which identifies an interrupt corresponding to the USARTn RX FIFO 0x3 1 Receive Line Status RLS 0 2 2 Receive Data Available 0 6 2b Character Time out Indicator CTI 0 1 THRE Interrupt 0x0 4 Modem status 0x7 3b TEMT Interrupt Other Reserved INTSTATUS Interrupt status The pending interrupt can be determined by evaluating 1 USARTn_II 3 1 0 At least one interrupt is pending 1 No interrupt is pending Bits USARTn_II 9 8 are set by the auto baud function and signal a time out or end of auto baud co
35. UDCDn URIn UDTRn and URTSn 010 IRDA mode HW switches GPIO to UTXDn and URXDn 011 Smart Card mode HW will switch GPIO to UTXDn and enable UTXDn pin with open drain 100 Synchronous mode HW will switch GPIO to UTXDn URXDn and USCLK pin 101 RS 485 mode HW will switch GPIO to UTXDn URXDn pin USART enable 0 Disable All USART shared pins act as GPIO 1 Enable HW switches GPIO to USART pin according to MODE bits automatically 13 12 17 USART n Half duplex Enable register USARTn HDEN n 0 1 Address Offset 0x34 After reset the USART will be in full duplex mode meaning that both TX and RX work independently After setting the HDEN bit the USART will be in half duplex mode In this mode the USART ensures that the receiver is locked when idle or will enter a locked state after having received a complete ongoing character reception Line conflicts must be handled in SW The behavior of the USART is unpredictable when data is presented for reception while data is being transmitted For this reason the value of the HDEN register should not be modified while sending or receiving data or data may be lost or corrupted Note This register should be disabled when in smart card mode or IrDA mode Smartcard and IrDA by default run in half duplex mode Name 313 Reserved Half duplex mode enable bit 0 Disable 1 Enable 13 12 18 USART n Smardcard Interface Control regis
36. Vdd 0 2V Operating ambi nt temperatura L LL 40 85 C Storage ambient temperature TSION home d pha q ad aswa boa a aaa aiis 40 125 C 18 2 ELECTRICAL CHARACTERISTIC Standard Operating Conditions Typical temperature Ta 25 Operating Temperature 40C lt Ta lt 85 for Industrial Class The below data covers process corner range SS TT FF PARAMETER SYM DESCRIPTION MN UNIT Operating Voltage Supply voltage for core and external rail 18 33 36 V VDD rise rate VDD rise rate to ensure internal power on reset 0 05 vms Power Consumption System clock 12MHz 11218 1991 Normal mode System clock 50MHz 11314 System clock 12 2 Supply Current Syst lock 93 Sleep Mode Vdd 3 3V a 1 3 5 Vdd 3 3V 1995 Deep power down Mode Port Pins RESET pin High level inputvottage vw v Low levelinputvoltage sva v O vu CT o va v O V CE vsa v VO port pull up resistor Reu Vin Vss Vdd 33V CL eo pull down resistor Vin 33V 4o eo Pull up resistor disable Vin Vdd 2 u
37. gt Standard 125 gt Right justified Data Format gt MSB Left justified Data Format Channel Length gt Data Length Channel length Channel length 125 Ne i Left Right SD msb 1510 0 0 msb Isb 0 0 msb Data length BCLK Left ws Channel length Channel length Left Right Justified SD msb lsb 0 0 msb Isb 0 0 msb Data length gt Right WS E Channel length a Channel length Justified SD 0 0 0 msb lsb 0 0 0 msb Isb 0 0 0 Data length SONiX TECHNOLOGY CO LTD Page 144 Version 2 0 NI N 7 SN32F720 Series N x 32 Bit Cortex M0 Micro Controller Channel Length Data Length
38. gt Watchdog timer should be cleared if enabled before the Flash write or erase operation The erase operation sets all the bits in the Flash page to logic 1 gt HW will hold system clock and automatically move out data from RAM and do programming after programming finished HW will release system clock and let MCU execute the next instruction 15 2 EMBEDDED FLASH MEMORY The Flash memory is organized as 32 bit wide memory cells that can be used for storing both code and data constants and is located at a specific base address in the memory map of chip The high performance Flash memory module in chip has the following key features gt Memory organization the Flash memory is organized as a User ROM Boot ROM User ROM Up to 2K x 32 bits divided into 16 pages of 512 Bytes Boot ROM Up to 1K x 32 bits divided into 8 pages of 512 Bytes The Flash interface implements instruction access and data access based on the AHB protocol It implements the logic necessary to carry out Flash memory operations Program Erase Program Erase operations can be performed over the whole product voltage range 15 3 FEATURES gt Read interface 32 bit gt Flash Program Erase operation gt Code Option includes Code Security CS Write operations to the main memory block and the code options are managed by an embedded Flash Memory Controller FMC The high voltage needed for Program Erase operations is internally generated The ma
39. the switch will occur when the clock source is ready Ready bits in SYSO_CSST register indicate which clock s is are ready SYSCLKST bits in SYS0 CLKCFG register indicate which clock is currently used as system clock 3 2 5 CLOCK OUT CAPABITITY The MCU clock output CLKOUT capability allows the clock to be output onto the external CLKOUT pin The configuration registers of the corresponding GPIO port must be programmed in alternate function mode One of 6 clock signals can be selected as clock output HCLK IHRC ILRC PLL clock output ELS X TAL EHS X TAL selection is controlled the CLKOUTSEL bits 5 51 register SONiX TECHNOLOGY CO LTD Page 43 Version 2 0 N 7 SONIX 33 SYSTEM CONTROL REGISTERS 0 Base Address 0 4006 0000 3 3 1 Analog Block Control register SYSO_ANBCTRL Address Offset 0x00 Reset value 0x0000 0001 Note EHSEN ELSEN IHRCEN bit can NOT be cleared if the EHS X tal ELS X tal IHRC is selected as system clock or is selected to become the system clock i Frequency range driving ability of EHS X TAL 0 lt 12MHz 1 gt 12MHz External high speed clock enable 0 Disable EHS X TAL 1 Enable EHS X TAL ELSEN External low speed oscillator enable 0 Disable External 32 768 KHz oscillator 1 Enable External 32 768 KHz oscillator Internal high speed clock enable 0 Disable interna
40. 0 wo WAV SN32F720 Seri SO N N x 32 Bit Cortex M0 2 20 2 46 PIN sn NOM Max A 070 075 0 80 EM MBA OM NOTES A3 1 JEDEC OUTLINE N A b 08 025 050 2 DIMENSION b APPLIES TO METALLIZED TERMINAL a AND 15 MEASURED BETWEEN 0 15mm AND 0 30mm T ss NEM FROM THE TERMINAL TIP IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE 56 6 TERMINAL THE DIMENSION b SHOULD MEASURED IN THAT RADIUS AREA 3 THE MINIMUM K VALUE OF 0 20mm APPLIES L 035 040 945 4 BILATERAL COPLANARITY ZONE APPLIES TO THE K o20 EXPOSED HEAT SINK SLUG AS WELL AS THE UNIT mm TERMINALS SONiX TECHNOLOGY LTD Page 164 Version 2 0 N N 7 SN32F720 Series S N N 32 Bit Cortex M0 Micro Controller 21 MARKING DEFINITION 21 1 INTRODUCTION There are many different types in 32 bit MCU production line This note lists the marking definitions of all 32 bit MCU for order or obtaining information 21 2 MARKING INDETIFICATION SYSTEM SN32X X X X B PB Free Package Ly Material G Green Package Temperature 40 C 85 C Range W Wafer Shipping H Dice Package K SK DIP P 5 SOP X SSOP F LQFP J oil Device Device Part No ROM Type F Flash memory Title SONIX 32 bit MCU Production SONiX TECHNOLOGY LTD Page 165 Ve
41. 0 SONIA 8 4 BLOCK DIAGRAM SN32F720 Series 32 Bit Cortex M0 Micro Controller gt Interrupt CT32Bn_PWMx 2 MRxSTO CEN CRST gt a T POM a gt RESET 5 PWMxEN PWMxIOEN Y m gt EMCx gt CAPOEN 4 lt CAPOFE CAPOI CAPORE CAPO Interrupt SONiX TECHNOLOGY CO LTD Page 81 Version 2 0 NI WV 1 NIX 8 5 TIMER OPERATION The following figure shows a timer configured to reset the count and generate an interrupt on match The CT32Bn register is set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value 2 1 2 3 4 5 6 0 1 2 TC Reset Interrupt The following figure shows a timer configured to stop and generate an interrupt on match The CT32Bn MRx register is set to 6 In the next clock after the timer reaches the match value the CEN bit in CT32Bn TMRCTRL register is cleared and the interrupt indicating that a match occurred is generated PCLK
42. 00 Do Nothing 01 CT32Bn_PWM1 pin is LOW 10 CT32Bn_PWM1 pin is HIGH 11 Toggle CT32Bn_PWM1 EMCO 1 0 Determines the functionality of CT32Bn PWMO 00 Do Nothing 01 2 PWMO pin is LOW 10 2 PWMO pin is HIGH 11 Toggle 2 PWMO and also drive the state of CT32B1 PWMSGS output and also drive the state of CT32Bn_PWM2 output and also drive the state of CT32Bn_PWM1 output and also drive the state of 2 PWMO output 8 7 9 CT32Bn PWM Control register CT32Bn PWMCTRL nz0 1 Address Offset 0x34 The PWM Control register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by CT32Bn EM register For each timer a maximum of three single edge controled PWM outputs can be selected on the 2 PWMCTRL 93 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Name 81 24 Reserved CT32Bn PWMS GPIO selection bit 0 CT32Bn PWNG act as GPIO 1 CT32Bn PWMS pin act as match output and output signal depends on PWMSEN bit PWM2IOEN CT32Bn_PWM2
43. 25 v Levi2 260 270 280 v 13 00 12 80 12 60 12 40 12 20 12 00 11 80 11 60 11 40 11 20 11 00 FREQUENCY MHz SONiX TECHNOLOGY CO LTD N 40 IHRC 20 C 25 C 70 C 85 C 2 70 3 20 VDD V FREQUENCY KHz 20 00 19 00 18 00 15 00 14 00 13 00 12 00 11 00 p 17 00 DA 40 C 16 00 ante 10 00 1 60 2 10 2 60 VDD V 3 10 3 60 Page 160 Version 2 0 SONIX olen VDD v s Regulator 1 8V Output VDD v s Max 60 50 40 2 55 30 20 10 0 17 19 21 23 25 27 29 31 33 35 180 200 220 240 260 280 300 320 340 3 60 VDD V VDD V SONiX TECHNOLOGY CO LTD Page 161 Version 2 0 N N j SN32F720 Series NS 32 Bit Cortex M0 Micro Controller 1 9 FLASH PROGRAMMING PIN Programming Information of SN32F720 Series Chip Name SN32F727F SN32F726J Number Name Number Pin Number Pin Number Pin Number Pin Pin Pp io J 20 lasere 28 13 26 pis J Ll _ SONiX TECHNOLOGY CO LTD Page 162 Version 2 0 32 Bit Micro Controller a IES 20 PACKAGE INFORMATION 20 1 LQFP 48 PIN 9 00 BSC 7 00 BSC 9 00 BSC 7 00 BSC 0 5 BSC SONiX TECHNOLOGY LTD Page 163 Version 2
44. 5 ma Vddi 25V 85 7 ma Te 2 5 1 5128976 2 30 ms Vdd 2 5V 1 Word 32 bits Low Voltage Detector MISC Interrupt LVD Reset 1 8V Regulator Output voltage Vreg18 Vcc 25 Vdd 1 8V 3 6V IHRC Freq T 40C 85 C Vdd 1 8V 3 6V These parameters are for design reference not tested 1 measurements were performed with all pins configured as GPIO outputs driven LOW and pull up resistors disabled and VDD 3 3V 2 IHRC and ILRC are enabled external X tal are disabled and PLL is disabled 3 LVD and all peripherals are disabled 5 All oscillators and analog blocks are turned off 6 DPDWAKEUP pin is pulled HIGH internally 4 IHRC is disabled external high X tal is enabled and PLL is enabled 7 ILRC is enabled IHRC and external X tal are disabled and PLL is disabled 18 3 CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for information only and devices are guaranteed to operate properly only within the specified range 3 30V IVREG18 gt 25 mA s 70 Levio 19 200 210 v 26 270 280 V Levi2 290 300 3 10 v Levio 19 200 20 v Levelt 230 240
45. Deep power down mode when power is still applied to the VDD pin but the chip has entered Deep power down mode Note Backup registers will be reset only when all power has been completely removed from the chip mir DIL lame 31 8 Reseved BACKUPDATA 7 0 BACKUPDATA Data retained during Deep power down mode 4 7 2 Power control register PMU CTRL Address Offset 0x40 The power control register selects whether one of the ARM Cortex MO controlled power down modes Sleep mode or Deep sleep mode or the Deep power down mode is entered and provides the flags for Sleep or Deep sleep modes and Deep power down modes respectively Note The register retains data through the Deep power down mode when power is still applied to the VDD pin and will be reset only when all power has been completely removed from the chip Bit Name Reserved SLEEPEN Sleep mode enable 0 Disable 1 Enable WFI instruction will make MCU enter Sleep mode BE nd Deep sleep mode enable 0 Disable 1 Enable WFI instruction will make MCU enter Deep sleep mode KB Deep power down mode enable 0 Disable 1 Enable WFI instruction will make MCU enter Deep power down mode SONiX TECHNOLOGY CO LTD Page 58 Version 2 0 N N 7 SN32F720 Series 4 N N X 32 Bit Cortex M0 Micro Controller D GENERAL PURPOSE PORT GPIO 5 1 OVERVIEW m ports can be configured input
46. FIFO 0 13 12 2USART n Transmitter Holding register USARTn TH n 0 1 Address Offset 0x00 This register is the top byte of the USART TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in USARTn LC register must be zero in order to access this register 3058 Reseved 7 0 TH 7 0 The byte will be sent when it is the oldest byte in TX FIFO and the transmitter is available 13 12 3USART n Divisor Latch LSB registers USARTn_DLL n 0 1 Address Offset 0x00 The USART Divisor Latch is part of the USART Baud Rate Generator and holds the value used optionally with the Fractional Divider to divide the USARTn_PCLK clock in order to produce the baud rate clock which must be the multiple of the desired baud rate that is specified by the Oversampling Register typically 16X The USARTn_DLL and USARTn_DLM registers together form a 16 bit divisor and DLAB bit in USARTn LC register must be one in order to access these registers DLL contains the lower 8 bits of the divisor and DLM contains the higher 8 bits A zero value is treated like 0x0001 TE 91 8 Reserved determines the baud rate of the USART 13 12 4 USART n Divisor Latch MSB register USARTn DLM n 0 1 Address Offset 0x04 318 Reserved Bil 5 Description 7 0 DLM 7 0 The USART Divisor Latch MSB Register along w
47. FIFO and the transmitter will stop transmitting until auto baud function finishes or be stopped Two auto baud measuring modes are available which can be selected by the MODE bit in USARTn ABCTRL register In Mode 0 the baud rate is measured on two subsequent falling edges of the USART RX pin the falling edge of the start bit and the falling edge of the least significant bit In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the USART RX pin the length of the start bit The AUTORESTART bit in USARTn ABCTRL register can be used to automatically restart baud rate measurement if a timeout occurs the rate measurement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the URXD pin The auto baud function can generate two interrupts SONiX TECHNOLOGY CO LTD Page 124 Version 2 0 N NI j SN32F720 Series N E x 32 Bit Cortex M0 Micro Controller e ABTOINT interrupt in USARTn ll register will get set if the interrupt is enabled ABTOIE bit in USARTn IE register is set and the auto baud rate measurement counter overflows The ABEOINT interrupt in USARTn ll register will get set if the interrupt is enabled ABTOIE bit in USARTn IE register is set and the auto baud has completed successfully The auto baud interrupts have to be cleared by setting the corresponding ABTOINTCLR and ABEOIE bits in USARTn E register The fractional baud ra
48. Interrupt Status register CT32Bn_RIS 0 1 88 8 7 11 2 Timer Interrupt Clear register 32 _1 n 0 1 88 9 WATCHDOG TIMER 89 9 1 89 02 90 93 JWDTREGISIERS stc pi MR ded FIR 91 9 3 1 Watchdog Configuration register _ 91 9 3 2 Watchdog Clock Source register _CLKSOURCE 91 9 3 3 Watchdog Timer Constant register WDT TC 91 9 3 4 Watchdog Feed register 92 10 REAL TIME CLOCK RUC 93 101 OVERVIEW 93 93 10 3 FUNCTIONAL DESCRIPTION 44 93 INTRODUCTION RD PTT 93 10 32 RESET RIC REGISTERS 93 10 3 3 PIAG ASSERTION ewes 93 10 34 FET OPERATION 94 104 BLOCK DIAGRAN 95 10 5 REC REGISTERS EEA 96 10 5 1 Control register RTC_CTRL 96 10 52 RTC Clock Source Select register RTC_CLKS 96 10 5 3 RIG Interrupt E
49. LTD Page 136 Version 2 0 TERI Trailing Edge RI Set upon low to high transition of input RI Cleared after reading this register 0 No change detected on modem input RI 1 Low to high transition detected on RI SN32F720 Series SO N 32 Bit Cortex M0 Micro Controller 13 12 12 USART n Scratch Pad register USARTn SP n 0 1 Address Offset 0x1C This register has no effect on the USART operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of this register has occurred 80 8 Reserved RR _70 PAD 7O Areadable wrtablebyte RW O0 13 12 13 USART n Auto baud Control register USARTn_ABCTRL n 0 1 Address Offset 0x20 This register controls the process of measuring the incoming clock data rate for the baud rate generation and can be read and written at user s discretion Besides it also controls the clock pre scaler for the baud rate generation The reset value of the register keeps the fractional capabilities of USART disabled making sure that USART is fully SW and HW compatible with USARTs not equipped with this feature Ren ABTOIFC Auto baud time out interrupt flag clear bit 0 No effect 1 Clear ABTOIF bit This bit is automatically cleared by HW ABEOIFC End of auto baud interrupt flag clear bit 0 No effect 1 Clear ABEOIF bit This bit is automatically c
50. LTD Page 25 Version 2 0 gt Go WY SN32F720 Series Sv N x 32 Bit Cortex M0 Micro Controller 2 2 3 3 System Tick Timer Current Value register SYSTICK VAL Address 0xE000 E018 Refer to Cortex M0 Spec 31 24 Reserved CURRENT Reading this register returns the current value of the System Tick counter R W 0x7E7F35 Writing any value clears the System Tick counter and the COUNTFLAG bit in SYST_CSR 2 2 3 4 System Tick Timer Calibration Value register SYST_CALIB Address 0xE000 E01C Refer to Cortex MO Spec NOREF Indicates the reference clock to MO is provided or not 1 1 No reference clock provided SKEW Indicates whether the TENMS value is exact an inexact TENMS value can affect the suitability of SysTick as a software real time clock 0 TENMS value is exact 1 TENMS value is inexact or not given 29 24 Reseved TENMS Reload value for 10ms timing subject to system clock skew errors If the R W OxA71FF value reads as zero the calibration value is not known SONiX TECHNOLOGY CO LTD Page 26 Version 2 0 q 7 1 SONIX 23 NESTED VECTORED INTERRUPT CONTROLLER All interrupts including the core exceptions are managed by the NVIC NVIC has the following Features The NVIC supports 32 vectored interrupts 4 programmable interrupt priority levels with hardware priority level masking Low latency exception and interrupt handling Efficient processing of late arriving interrupts Implementati
51. M0 Micro Controller 4 SYSTEM OPERATION MODE 41 OVERVIEW The chip builds in four operating mode for difference clock rate and power saving reason These modes control oscillators op code operation and analog peripheral devices operation Normal mode Sleep mode Deep sleep mode Deep Power down mode v v v v 4 2 NORMAL MODE In Normal mode the ARM Cortex MO core memories and peripherals are clocked by the system clock The SYS1 AHBCLKEN register controls which peripherals are running Selected peripherals have individual peripheral clocks with their own clock dividers in addition to the system clock The peripheral clocks can be disabled respectively The power to various analog blocks IHRC EHS X TAL ELS X TAL PLL Flash LVD ADC can be controlled at any time individually through the enable bit of all blocks 4 3 LOW POWER MODES There are three special modes of processor power reduction Sleep mode Deep sleep mode and Deep power down mode CTRL register controls which mode is going to entered The CPU clock rate may also be controlled as needed by changing clock sources re configuring PLL values and or altering the system clock divider value This allows a trade off of power versus processing speed based on application requirements Run time power control allows disable the clocks to individual on chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any
52. OINV Polarity control This bit reverses the polarity of the direction control signal on the RTS pin 0 The direction control pin will be driven to logic 0 when the transmitter has data to be sent It will be driven to logic 1 after the last bit of data has been transmitted 1 The direction control pin will be driven to logic 1 when the transmitter has data to be sent It will be driven to logic 0 after the last bit of data has been transmitted Auto Direction control enable bit 0 Disable 1 Enable RTS pin is used for direction control HW will switch GPIO to Reserved Auto Address Detect enable 0 Disable 1 Enable RS 485 EIA 485 Receiver enable bit Only work when NMMEN 1 0 Disable 1 Enable NMMEN RS 485 EIA 485 Normal Multidrop Mode NMM enable bit R W 0 Disable 1 Enable In this mode an address is detected when a received byte causes the USART to set the parity error and generate an interrupt 13 12 20 USART n RS485 Address Match register USARTn RS485ADRMATCH n 0 1 Address Offset 0x40 This register contains the address match value for RS 485 EIA 485 mode Reserved Attribute Reset 308 R o _70 address value to be matched U I RW 0 13 12 21 USART n RS485 Delay Value register USARTn_RS485DLYV 0 1 Offset 0x44 SONiX TECHNOLOGY CO LTD Page 140 Version 2 0 N N 9 Y SN32F720 Series Is D Eu 32 Bit Cort
53. ONLY be switched on and off by HW SONiX TECHNOLOGY CO LTD Page 39 Version 2 0 N NI j SN32F720 Series N N 32 Bit Cortex M0 Micro Controller 3 2 2 PLL SN32F700 series MCU uses the PLL to create the clocks for the core and peripherals The input frequency range is 10MHz to 25MHz The input clock is divided down and fed to the Phase Frequency Detector PFD This block compares the phase and frequency of its inputs and generates a control signal when phase and or frequency do not match The loop filter filters these control signals and drives the voltage controlled oscillator VCO which generates the main clock and optionally two additional phases The VCO frequency range is 156MHz to 320MHz These clocks are divided by P by the programmable post divider to create the output clock s The VCO output clock is then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock The PLL settling time is 100 us E Fve Felkin vco DIV PFD LPF m VCO gt m gt Fclkout DIV 3 2 2 1 PLL Frequency selection The PLL frequency equations Fvco F M P The PLL frequency is determined by the following parameters
54. Offset 0x18 0x1C 0x20 0x24 The Match register values are continuously compared to the Timer Counter TC value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the CT32Bn register SONiX TECHNOLOGY CO LTD Page 85 Version 2 0 NONA 31 0 MR 310 Timer counter matchvale CR 8 7 6 CT32Bn Capture Control register CT32Bn_CAPCTRL n 0 1 Address Offset 0x28 The Capture Control register is used to control whether the Capture register is loaded with the value in the Counter timer when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges Note HW will switch I O Configuration directly when CAPOEN 1 HEUTE rM Capture 0 function enable bit 0 Disable 1 Enable CAPOIE Interrupt on CT32Bn CAPO event CAPO load due to a 32 event will generate an interrupt 0 Disable 1 Enable CAPOFE Capture on CT32Bn falling edge a sequence of 1 then 0 on CT32Bn will cause to be loaded with the contents of TC 0 Disable 1 Enable CAPORE Capture on CT32Bn rising edge a sequence of 0 then 1 CT32Bn
55. RTSCTRL Source for modem output RTS RTS is always forced to inactive state high modem loopback mode 0 DTRCTRL Source for modem output pin is always forced to inactive state high modem loopback mode SONiX TECHNOLOGY CO LTD Page 134 Version 2 0 N N o VAY SN32F720 Series 6 N N 32 Cortex M0 Micro Controller 13 12 10 USART n Line Status register USARTn LS n 0 1 Address Offset 0x14 Note gt 1 The break interrupt BI is associated with the character at the top of the USARTn_RB FIFO gt 2 The framing error FE is associated with the character at the top of the USARTn_RB FIFO gt 3 The parity error PE is associated with the character at the top of the USARTn_RB FIFO NI ON TXERR TX Error flag Only available iln smart card 0 operation 0 No TX Error 1 Smart card has NACKed a transmitted character one more than the number of times indicated by the TXRETRY field RXFE Error in RX FIFO flag RXFE 1 when a character with a error such as framing error parity error or break interrupt is loaded into the USARTn RB register This bit is cleared when the USARTn LS register is read and there are no subsequent errors in the USART FIFO 0 USARTn RB register contains no USART errors or FIFOEN 0 1 USARTn RB register contains at least one USART RX error TEMT Transmitter Empty flag TEMT 1 when
56. Reset 3058 Reseved R o MATCH ALL Match address selection RAN 0 Interrupt will only generated when the address matches one of the values in 2 SLVADDRO 3 register 1 If I2C is in monitor mode an interrupt will be generated on ANY address received This will enable the part to monitor all traffic on the bus SCLOEN SCL output enable bit R W 0 SCL output will be forced high 1 12C module may act as a slave peripheral just like in normal operation the I2C holds the clock line low until it has had time to respond to an 2 interrupt 0 Disable 1 Enable SONiX TECHNOLOGY CO LTD Page 116 Version 2 0 N M 2F72 1 SONIX 1 3 UNIVERSAL SYNCHRONOUS AND ASYNCHRONOUS SERIAL RECEIVER AND TRANSMITTER USART 13 1 OVERVIEW The USART offers a flexible means of full duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format The serial interface is applied to low speed data transfer and communicate with low speed peripheral devices The USART offers a very wide range of baud rates using a fractional baud rate generator It supports both synchronous one way communication and single wire communication It also supports the LIN local interconnection network Smartcard Protocol and IrDA infrared data association SIR ENDEC specifications and modem operations CTS RTS 13 2 FEATURES Full duplex 2 wire asynchronous data transfer Single wire
57. SSA Note Connect the Crystal Ceramic as near as possible to the XIN XOUT VSS pins of MCU Structure 1MHz 25MHz EHS external crystal ceramic resonator e Main Purpose System high clock source RTC clock source and PLL clock source e Warm up Time 2048 e XIN XOUT Shared Pin Selection Oscillator Mode XTALIN pin XTALOUT pin IHRC GPIO GPIO EHS X TAL Crystal Ceramic Crystal Ceramic SONiX TECHNOLOGY CO LTD Page 41 Version 2 0 N N 9 Y SN32F720 Series Eu 32 Cortex M0 Micro Controller The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time The loading capacitance values must be adjusted according to the selected oscillator The EHS crystal is switched and off using the EHSEN bit in Analog Block Control register SYSO_ANBCTRL 3 2 3 3 External Low speed ELS Clock The low speed oscillator can use 32768 crystal oscillator circuit 3 2 3 4 CRYSTAL Crystal devices are driven by LXIN LXOUT pins The 32768 crystal and 10pF capacitor must be as near as possible to MCU The ELS crystal is switched on and off using the ELSEN bit in Analog Block Control register SYS0 ANBCTRL LXIN 32768Hz LXOUT MCU ofl 10pF 10pF VDD SSA VCC Note Connect the Crystal Ceramic and as near
58. T CT32Bn_TC 2 3 4 5 6 CEN bit 1 0 Interrupt SONiX TECHNOLOGY LTD Page 82 Version 2 0 32 Cortex M0 Micro Controller SONIN ear crt te cnt 8 6 PWM 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value in 2 0 3 registers is equal to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs the PWM output remains continuously LOW 3 f a match value larger than the PWM cycle length is written to the CT32Bn 0 3 registers and the PWM signal is HIGH already then the PWM signal will be cleared on the next start of the next PWM cycle 4 famatch register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously CT32Bn_MR2 100 PWM1 CT32Bn_MR1 25 PWM 2 0 60 CT32Bn TC 0 25 60 100 TC resets When the match outputs are selected to perform as PWM outputs the timer reset MRnRST and timer stop MRnSTOP bits in
59. TXEN bit becomes 0 USART transmission will stop It is strongly suggested to let the USART HW implemented auto flow control features take care of limit the scope of TXEN to SW flow control Note It is advised that and RXEN are set in the same instruction if needed in order to minimize the setup and the hold time of the receiver Bit Na 31 8 Reserved 7 TXEN When this bit is 1 data written to the USARTn_TH register is output on the TXD pin as soon as any preceding data has been sent If this bit is cleared to 0 while a character is being sent the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the SONiX TECHNOLOGY CO LTD Page 138 Version 2 0 SON IX E USARTn_TH register or TX FIFO into the transmit shift register SW can clear this bit when it detects that the HW handshaking TX permit signal CTS has gone false or with SW handshaking when it receives XOFF character DC3 SW can set this bit again when it detects that the TX permit signal has gone true or when it receives an XON DC1 character RXEN 0 Disable RX related function R W 1 1 Enable RX 54 Reserved USARTn Mode 000 UART mode HW will switch GPIO to UTXDn and URXDn 001 Modem control mode HW will switch GPIO to UTXDn URXDn UDSRn UCTSn
60. User ROM EEPROM emulation HW checksum can be read other data will be read as 0 0 Note User may try to change security level from CS2 to CS0 or from CS1 to CSO HW shall 1 Mass erase the User ROM first User shall NOT execute this operation in debug mode since the SWD communication may fail during the mass erase procedure 2 Update security level includes 1 Option byte erase 4 New option byte programming includes Mass Erase Option byte erase CS2 cs New option byte programming 15 8 2 PROGRAM MEMORY The Flash memory can programmed 32 bits at a time CPU can program the main Flash memory by performing standard word write operations The PG bit in the FLASH_CTRL register must be set FMC preliminarily reads the value at the addressed main Flash memory location and checks that it has been erased If not the program operation is skipped and a warning is issued by the PGERR bit in FLASH STATUS register The end of the program operation is indicated by the EOP bit in the FLASH_STATUS register The main Flash memory programming sequence in standard mode is as follows Setthe PG bit in the FLASH_CTRL register Perform the data write at the desired address Wait for the BUSY bit to be reset Read the programmed value and verify SONiX TECHNOLOGY LTD 152 Version 2 0 N N 7 SN32F720 Series 4 N N 32 Bi
61. address received if the MATCH_ALL bit is set otherwise an address matching one of the four address registers Subsequent to an address match detection interrupts will be generated after each data byte is received for a slave write transfer or after each byte that the module thinks it has transmitted for a slave read transfer In this second case the data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master Following all of these interrupts the processor may read the data register to see what was actually transmitted on the bus 12 7 2 LOSS of ARBITRATION In monitor mode the 2 module will not be able to respond to a request for information by the bus master or issue an ACK Some other slave on the bus will respond instead This will most probably result in a lost arbitration state as far as our module is concerned Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected In addition hardware may be designed into the module to block some all loss of arbitration states from occurring if those state would either prevent a desired interrupt from occurring or cause an unwanted interrupt to occur Whether any such hardware will be added is still to be determined SONiX TECHNOLOGY CO LTD Page 112 Version 2 0 N TAY S a x 32 Bit 2 s 12 8 12 REGISTERS Base Addres
62. allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation gt to three CT16BO or two CT16B1 PWM outputs corresponding to match registers with the following capabilities Set LOW match Set HIGH on match Toggle on match Do nothing on match gt For each timer up to four match registers MRO MR3 can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs 7 3 PIN DESCRIPTION n Pin Name gt n CT16Bn CAPO I Capture channel input 0 Depends on GPlOn CFG eee CT16Bn PWMx Output channel x of Match PWM output SONiX TECHNOLOGY CO LTD Page 71 Version 2 0 SONIA 7 4 BLOCK DIAGRAM SN32F720 Series 32 Bit Cortex M0 Micro Controller MRxSTO5 pz CEN CRST Interrupt POLK TC gt p RESET MRxRST pz Y PWMxEN PWMxIOEN gt _ gt CT16Bn_PWMx EMCx gt C CAPO 11 CAPOT CAPO Interrupt SONiX TECHNOLOGY CO LTD Page 72 Version 2 0 NI WV 1 N N Eu x 32 Bit 2 s 7 5 TIMER OPERATION The following figure shows a timer configured to rese
63. are disabled TXEN 0 and RXEN 0 to ensure that the clock pulses function correctly These bits should not be changed while the transmitter or the receiver is enabled TXEN 1 and RXEN 1 gt 3 The Synchronous mode supports master mode only it can NOT receive or send data related to an input clock SCLK is always an output SCLK CPOL Idle Diagrams Status Nm 158 Aet X TECHNOLOGY LTD 129 Version 2 0 NF 7 1 SONIX 13 12 USART REGISTERS Base Address 0x4001 6000 USARTO 0x4005 6000 USART1 13 12 1 USART n Receiver Buffer register USARTn RB lt 0 1 Address Offset 0x00 This register is the top byte of the USART RX FIFO and contains the oldest character received and can be read via the bus interface The LSB bit 0 contains the first received data bit If the character received is less than 8 bits the unused MSBs are padded with zeros The Divisor Latch Access Bit DLAB in the USARTn LC register must be zero in order to access this register Since PE FE and BI bits correspond to the byte on the top of the USART RX FIFO i e the one that will be read in the next read from this register the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the USARTn LS register and then to read a byte from this register 3 8 Reseved CR RB 7 0 Contains the oldest received byte in the USART RX
64. chosen as a mode of operation the CAP input selected by CIS bits is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by CTM bits in this register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently the duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 x 1 Note If Counter mode is selected in the CNTCTRL register Capture Control CAPCTRL register must be programmed as 0 0 Nan SONiX TECHNOLOGY CO LTD Page 84 Version 2 0 NP M 1 SONIX CIS 1 0 Count Input Select In counter mode when CTM 1 0 are not 00 these bits select which CAP pin is sampled for clocking 00 CT32Bn CAPO Other Reserved CTM 1 0 Counter Timer Mode This field selects which rising PCLK edges can clear PC and increment Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Co
65. direction I O Pin Shared with Specific Analog Output Function e g XOUT Reu GPIOPn MODE x gt GPIOn Pin gt Input Bus gt GPIOn_CFG GPIOPn_MODE Output lt Latch Output Bus lt Analog IP Output Terminal Specific Output Function Control Some specific functions switch I O direction directly not through GPIOn MODE register SONiX TECHNOLOGY CO LTD Page 22 Version 2 0 GN WY SN32F720 Seri S N 32 Bit Cortex M0 2 CENTRAL PROCESSOR UNIT CPU 2 1 MEMORY MAP OxFFFF FFFF Reserved 0 010 0000 Reserved 0 010 0000 0 000 F000 Debug Control 0 8000 EDOO Private Peripheral Bus NVIC is 0 000 E000 0 000 0000 E Reserved 0 000 0000 0 4008 0000 Reserved External Device Reserved 0x4006 4000 0 4006 2000 x 0 000 0000 SYSO 0x4006 0000 5 5 0 4005 000 Reserved Reserved for External ps 1 0 4005 C000 0x4005 A000 SSP 1 0x4005 8000 USART 1 0x6000 0000 0x4005 6000 Reserved 0x4004 000 GPIO 3 Reserved for Peripheral BS GPIO 2 0 4004 A000 0x4004 8000 GPIO 1 0x4004 6000 GPIO 0 0x4008 0000 0x4004 4000 Peripheral Reserved 0x4003 4000 0x400
66. end of ADC converting through checking EOC 1 or ADCIF 1 If ADC interrupt function is enabled the program executes ADC interrupt service when ADC interrupt occurrence ADS is cleared when the end of ADC converting automatically EOC bit indicates ADC processing status immediately and is cleared when ADS 1 Users needn t to clear it by program 6 4 ADC CIRCUIT External High Reference Voltage Analog Signal Input Main Power Trunk The analog signal is inputted to ADC input pin AINn P2 n The ADC input signal must be through a 0 1uF capacitor The 0 1uF capacitor is set between ADC input pin and VSS pin and must be on the side of the ADC input pin as possible Don t connect the capacitor s ground pin to ground plain directly and must be through VSS pin The capacitor can reduce the power noise effective coupled with the analog signal If the ADC high reference voltage is from external voltage source the external high reference is connected to AVREFH P2 0 The external high reference source must be through 47uF C capacitor first and then 0 1uF capacitor These capacitors are set between AVREFH pin and VSS pin and must be on the side of the AVREFH pin as possible Don t connect the capacitor s ground pin to ground plain directly and must be through VSS pin SONiX TECHNOLOGY CO LTD Page 67 Version 2 0 ND E 7 1 SONIX 6 5 ADC REGISTERS Base Address 0 4002 6000 6 5 1 ADC Ma
67. half duplex communication Transmitter clock output for synchronous transmission 16 byte receive and transmit FIFOs Register locations conform to 16550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator Software or hardware flow control EIA 485 9 bit mode support with output enable Modem control signals CTS RTS ISO 7816 3 compliant Smartcard interface IrDA support VVVVVVVVVV VV 13 3 PIN DESCRIPTION Din Pin N Hi IN Serial Transmit data Serial clock of Synchronous mode Master Clear to Send When low this indicates that the MODEM or data set is ready to exchange data The CTS signal is a MODEM status input d i Depends on GPIOn_CFG whose conditions can be tested by reading bit 4 CTS of USARTn_MS register Request to Send RS 485 direction control pin When low this informs the MODEM or data set that the UART is ready to exchange data The RTS output signal can be set to an active low by programming bit 1 RTS of USARTn_MC register Loop mode operation holds this signal SONiX TECHNOLOGY LTD Page 117 Version 2 0 WY SN32F720 Series v NS x 32 Bit Cortex M0 Micro Controller nits inactivestate Data Terminal Ready When low this informs the MODEM or data set that the UART is ready to establish a communications link The DTR output signal can be set to an active low by programming bit 0 DTR of USARTn MC regis
68. hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part SONiX TECHNOLOGY CO LTD Main Office Address 10F 1 NO 36 Taiyuan Street Chupei City Hsinchu Taiwan R O C Tel 886 3 5600 888 Fax 886 3 5600 889 Taipei Office Address 15F 2 NO 171 Song Ted Road Taipei Taiwan R O C Tel 886 2 2759 1980 Fax 886 2 2759 8180 Hong Kong Office Unit No 705 Level 7 Tower 1 Grand Central Plaza 138 Shatin Rural Committee Road Shatin New Territories Hong Kong Tel 852 2723 8086 Fax 852 2723 9179 Technical Support by Email Sn8fae sonix com tw Page 167 Version 2 0
69. is the system work error area called dead band V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC application The power source of DC application is usually using battery When low battery condition and MCU drive any loading the power drops and keeps in dead band Under the situation the power won t drop deeper and not touch the system reset voltage That makes the system under dead band AC application SONiX TECHNOLOGY CO LTD Page 33 Version 2 0 N N Y SN32F720 Series D D E 32 Cortex M0 Micro Controller In AC power application the DC power is regulated from AC power source This kind of power usually couples with AC noise that makes the DC power dirty Or the external loading is very heavy e g driving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the system works under unstable power situation The power on duration and power down duration are longer in AC application The system power on sequence protects the power on successful but the power down situation is like low battery condition When turn off the AC power the VDD drops slowly and through the dead band for a while 3 1 3 2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION To improve the brown out reset needs to know the system minimum operating volta
70. multi master bus can be controlled by more than one bus master connected to it It is also SMBus 2 0 compatible Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus gt Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte gt Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a Repeated START condition Since a Repeated START condition is also the beginning of the next serial transfer the I2C bus will not be released The 2 interface is byte oriented and has four operating modes Master transmitter mode Master receiver mode Slave transmitter mode Slave receiver mode v v v v 12 2 FEATURES The 2 interface complies with the entire 2 specification supporting the ability to turn power off to the ARM Cortex MO without
71. output by SW Each individual port pin can serve as external interrupt input pin Interrupts can be configured on single falling or rising edges and on both edges The configuration registers control the electrical characteristics of the pads Internal pull up pull down resistor Most of the I O pins are mixed with analog pins and special function pins vy v v v v 5 2 GPIO MODE The MODE bits in the GPlOn CFG n 0 1 2 3 register allow the selection of on chip pull up or pull down resistors for each pin or select the repeater mode The repeater mode enables the pull up resistor if the pin is logic HIGH and enables the pull down resistor if the pin is logic LOW This causes the pin to retain its last known state if it is configured as an input and is not driven externally The state retention is not applicable to the Deep power down mode SONiX TECHNOLOGY CO LTD Page 59 Version 2 0 SONIX 5 3 GPIO REGISTERS Base Address 0x4004 4000 0x4004 6000 0x4004 8000 0x4004 A000 5 3 1 GPIO Port n Data register GPIOn_DATA n 0 1 2 3 Address offset 0x00 31 12 Reserved 24110 DATA 11 0 Input data read or output data write for 0 to Pn 11 GPIO 0 GPIO 1 GPIO 2 GPIO 3 SN32F720 Series 32 Bit Cortex M0 Micro Controller 5 3 2 GPIO Port n Mode register GPIOn_MODE n 0 1 2 3 Address offset 0x04 Note HW will switch I O Mode directly when Specific function Periph
72. peripheral with SYS1_PRST register after changing the prescale value e SSP1 clock source prescale value SSP1PRE 2 0 BOO MCLR 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 23 Reserved SSPOPRE 2 0 55 clock source prescale value R W 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 19 Reseved r ADCPRE 2 0 As value 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 15 Reseved CT32B1 clock source prescale value CT32B1PRE 2 0 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved SS 40 8 0 cok sorce pesee SONiX TECHNOLOGY CO LTD Page 50 Version 2 0 SON IX 7 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 7 R 9 CT16B1 clock source prescale value CT16B1PRE 2 0 000 HCLK 1 RAN 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved L aa a 16 0 clock source prescale value CT16BOPRE 2 0 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 3 4 3 APB Clock Prescale register 1 SYS1_APBCP1 Address Offset 0x08 Note Must reset the corresponding peripheral with SYS1_PRST re
73. signal behaves as a slave select main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits in SSPn CTRL1 register When the clock polarity control bit is LOW it produces a steady state low value on the SCK pin If the clock polarity control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The clock phase bit controls the phase of the clock on which data is sampled When CPHA 1 the SCK first edge is for data transition and receive and transmit data is at SCK 214 edge When 0 the 1 bit is fixed already and the SCK first edge is to receive and transmit data The SIO data transfer timing as following figure MLSB CPOL CPHA Diagrams Low use use SONiX TECHNOLOGY LTD 101 Version 2 0 N o WY SN32F720 Series Sv N N E 32 Bit Cortex M0 Micro Controller 11 4 2 SSI For device configured as a master in this mode CLK and FS are forced LOW and the transmit data line DX is in 3 state mode whenever the SSP is idle Once the bottom entry of the transmit FIFO contains data FS is pulsed HIGH for one CLK period The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the shifted out on the DX pin Likewise the MSB of the received d
74. terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below Vz 0 7V the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by Zener specification Select the right Zener voltage to conform the application 3 1 4 4 VOLTAGE BIAS RESET CIRCUIT The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely The operating voltage is not accurate as Zener diode reset circuit Use R1 R2 bias voltage to be the active level When VDD voltage level is above or equal to 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below 0 7V x R1 R2 R1 the C terminal of the PNP transistor SONiX TECHNOLOGY CO LTD Page 37 Version 2 0 N N Y SN32F720 Series D 32 Cortex M0 Micro Controller outputs low voltage and MCU is in reset mode Decide the reset detect voltage by R1 R2 resistances Select the right R1 R2 value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 gt R1 and the cap between VDD and C terminal voltage is larger than 0 7V The external r
75. the next positive edge of PCLK This is cleared by HW when the counter reset operation finishes CEN Counter Enable R W 0 Disable Counter 1 Enable Timer Counter for counting 7 7 2 CT16Bn Timer Counter register CT16Bn_TC n 0 1 Address Offset 0x04 Unless it is reset before reaching its upper limit the TC will count up to the value 0x0000FFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Bit _150 TCH50 TimerCounter RW O 7 7 3 CT16Bn Count Control register CT16Bn_CNTCTRL n 0 1 Address Offset 0x10 This register is used to select between Timer and Counter mode and in Counter mode to select the pin and edges for counting When Counter Mode is chosen as a mode of operation the CAP input selected by the CIS bits is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by CTM bits in this register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one e
76. used to control whether the Capture register is loaded with the value in the Counter timer when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges Note HW will switch I O Configuration directly when 1 Name Description Resemed o EI uM Capture 0 function enable bit 0 Disable 1 Enable CAPOIE Interrupt on 16 CAPO event CAPO load due to CT16Bn event will generate an interrupt 0 Disable 1 Enable CAPOFE Capture on CT16Bn CAPO falling edge a sequence of 1 then 0 on CT16Bn CAPO will cause CAPO to be loaded with the contents of TC 0 Disable 1 Enable CAPORE Capture 16 CAPO rising edge a sequence of 0 then 1 on CT16Bn CAPO will cause CAPO to be loaded with the contents of TC 0 Disable 1 Enable 7 7 7 CT16Bn Capture 0 register CT16Bn CAPO nz0 1 Address Offset 0x2C Each Capture register is associated with a device pin and may be loaded with the counter timer value when a specified event occurs on that pin The settings in the Capture Control register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges _ Bi Tr Resewed S 15 0 CAPO 15 0
77. 0 bits The two parameters decide ADC converting time AINO AREFH Internal V dd Z ADCKS 1 0 gt 2 N gt 2 CHS 3 0 ADC High Reference Voltage ADC Clock Counter SAR ADC Analog ENGINE Input ADB 11 0 gt m 2 UA EOC ADCIRQ gt 2 gt 2 gt m 2 ADENB ADS gt 2 avss gt m 52 Note For 8 bit resolution the conversion time is 12 steps For 12 bit resolution the conversion time is 16 steps Note ADC PCLK shall be less than 16MHz Note analog input level must be between the AVREFH and AVREFL Note The AVREFH level must be between the AVDD and AVREFL 2 0V HHH SONiX TECHNOLOGY CO LTD Page 65 Version 2 0 N N 9 Y SN32F720 Series D E 32 Bit Cortex M0 Micro Controller Note ADC programming notice 1 Set ADC input pin I O direction as input mode 2 Disable pull up resistor of ADC input pin 3 Disable ADC set ADENB 0 before enter low power Sleep Deep sleep Deep power down mode to save power consumption 4 Set related bit of P2CON register to avoid extra power consumption in power down mode 5 Delay 100us after enable ADC set ADENB 1 to wait ADC circuit ready for conversion 550 ONE N AY 6 2 ADC CONVERTING TIME The ADC converting time is from ADS
78. 0 0000 PMU 0x4003 2000 Reserved zs Reserved 0 4002 8000 02000 0000 2 SRAM 0x4002 6000 Reserved Reserved Ox1 FFF 2400 Reserved 0x4001 E000 Ox1FFF 2000 SSP O Reserved 4001 C000 0x1FFF 1000 125 4 0 4001 A000 0x1FFF 0000 0 4001 8000 USARTO 4001 6000 Reserved 4001 4000 RTC Reserved 0x4001 2000 WDT 4001 0000 Reserved 0 4000 8000 0 0000 2000 8 on chip FLASH 0x4000 6000 0x0000 0000 CT32B0 0x4000 4000 6 0 4000 2000 16 0 0 4000 0000 SONiX TECHNOLOGY LTD Page 23 Version 2 0 S Y Eu x 32 Bit oisi 2 2 SYSTEM TICK TIMER The SysTick timer is an integral part of the Cortex MO The SysTick timer is intended to generate a fixed 10 ms interrupt for use by an operating system or other system management software Since the SysTick timer is a part of the Cortex MO it facilitates porting of software by providing a standard timer that is available on Cortex MO based devices Refer to the Cortex MO User Guide for details 2 2 1 OPERATION The SysTick timer is a 24 bit timer that counts down to zero and generates an interrupt The intent is to provide a fixed 10 ms time interval between interrupts The system tick timer is enabled through the SysTick control register The system tick timer clock is fixed to the frequency of the system clock The block diagram of the SysTick timer SYSTICK CALIB 41 3 SYSTICK LOAD
79. 0 PCLK cycle 12 8 9 2 n Timeout Control register 2 TOCTRL n 0 1 Address Offset 0 2 Timeout happens when Master Slave SCL remained LOW for 32 12 0_ 1 cycle When 2 timeout occurs the I2C transfer will return to IDLE state and issue a TO interrupt to inform user That means SCL SDA will be released by HW after timeout User can issue a STOP after timeout interrupt occurred in Master mode Time out status will be cleared automatically by writing 2 CTRL or 2 register Bit lame ion 436 Reseved j R TO 15 0 Count for checking Timeout R W 0x0 0 Disable Timeout checking N Timeout period time N I2Cn PCLK cycle 12 8 10 2 n Monitor Mode Control register 12 MMCTRL 0 1 Address Offset 0x30 This register controls the Monitor mode which allows the 2 module to monitor traffic on the I2C bus without actually participating in traffic or interfering with the I2C bus In Monitor mode SDA output will be forced high to prevent the 12 module from outputting data of any kind including onto the 12 data bus Depending on the state of the SCLOEN bit the SCL output may be also forced high to prevent the module from having control over the I2C clock line Note The SCLOEN and MATCH ALL bits have no effect if MMEN bit is 0 i e if the module is NOT in monitor mode Name Description Attribute
80. 1 Start to ADC convert to 1 End of ADC convert The converting time duration is depend on ADC resolution and ADC clock rate ADC clock source is controlled by ADCKS 2 0 bits The ADC converting time affects ADC performance If input high rate analog signal it is necessary to select a high ADC converting rate If the ADC converting time is slower than analog signal variation rate the ADC result would be error So to select a correct ADC clock rate and ADC resolution to decide a right ADC converting rate is very important 12 bit ADC conversion time 1 ADC clock 4 16 sec 7 90 Meroe 8 _ 5 _ 010 ADCPCLK4 64 155 1 6 X 625 011 ADCPCLKB 8 7813 32 32 POM 28 28 3195 8 bit ADC conversion time 1 ADC clock 4 12 sec 83 333 333 333 166 667 ADC_PCLK 4 20 83 83 333 ADC_PCLK ADC_PCLK 8 imet 0 10 416 41 667 000 3 _ 001 2 8 41 667 ADC PCLK 16 5 208 20 83 PCLK 32 2 604 10 416 SONiX TECHNOLOGY CO LTD Page 66 Version 2 0 S v N N Eu x 32 Bit 6 3 ADC CONTROL NOTICE 6 3 1 ADC SIGNAL The ADC high reference voltage is internal Vdd or external voltage source The ADC low reference voltage is ground The ADC input signal vollage range must be from high reference voltage to low reference voltage The external high reference volt
81. 2 6 USART n Line Control register USARTN_LC n 0 1 133 13 12 9 USART n Modem Control register 05 MC n 0 1 133 13 12 10 USART n Line Status register LS n 0 1 135 13 12 11 USART n Modem Status register USARTn MS n 0 1 136 13 12 12 USART n Scratch Pad register USARTn SP 0 1 137 SONiX TECHNOLOGY CO LTD Page 9 Version 2 0 6 N E 32 2 2 13 12 13 USART n Auto baud Control register USARTn_ABCTRL 0 137 13 12 14 USART n IrDA Control register USARTn_IRDACTRL 0 I 137 13 12 15 USART n Fractional Divider register USARTn_FD n 0 I 138 13 12 16 USART n Control register USARTn_CTRL n 0 1 136 13 12 17 USART n Half duplex Enable register USARTn_HDEN 0 1 139 13 12 18 USART n Smardcard Interface Control register USARTn_SCICTRL 0 1 139 13 12 19 USART n RS465 Control register USARTn_RS485CTRL n O 140 13 12 20 USART n RS485 Address Match register RS4855ADRMATCH n 0 1 140 13 12 21 USART n RS465 Delay Value regi
82. 4 0 1 0 6 Reserved 7 8 bits 8 9 bits 31 32bits Max I2SEN 125 enable bit EMI 0 Disable 1 Enable 125 HW will switch GPIO to MCLK BCLK and WS FIFOTHI2 FIFO Threshold level R x SETS 0 FIFO threshold level 0 iii 0 8 1 threshold level 1 FIFO threshold level DL 1 0 Data Length R W 0x1 00 8 bits 01 16 bits 10 24 bits 11 32 bits 98 Reserved __ R o 7 CLRFIFO Clear 125 FIFO W 0 No effect 1 Reset FIFO FIFOLV bit becomes 0 FIFOEMPTY bit becomes 1 Data in FIFO will be cleared This bit returns O automatically 0 125 operation format R W 00 Standard 12S format 01 Left justified format 10 Right MSB justified format 11 Reserved Master Slave selection bit 0 Act as Master using internally generated BCLK and WS signals 1 Act as Slave using externally BCLK and WS signals TRS Transmit Receiver selection bit 0 Transmitter 1 Receiver Mono Stereo selection bit pure 0 Stereo 1 Mono Mute enable bit REGE 0 Disable Mute 1 Enable I2SSDA Output 0 Start Transmit Receive bit BEEN 0 Stop Transmit Receive 1 Start Transmit Receive 14 6 2 125 Clock register 125 CLK Address Offset 0x04 SONiX TECHNOLOGY CO LTD Page 147 Version 2 0 SONA LKDIV 7 BCLK divider BOLKDIVTO 0 BCLK MCLK 2 1 BCLK MCLK 4 2 BCLK MCLK 6 3 BCLK MCLK 8 n BCLK MCLK 2 n 2
83. 6 32 clock source WDT register block CLKOUTSEL WDTCLKSEL AHB clock for 125 125 125 PCLK 125 125 Clock Prescaler i 11 2 4 8 16 clock source register block AHB clock for ADC ee ADC_PCLK ADC ADC lock Prescaler i 1 2 4 8 16 Max 16MHz clock source register block AHB clock for 12 0 1260 PCLK 12 0 12 0 k j gt clock source register block 32 768KHz APB mE Prescaler AHB clock for CT32B1 d HSE Oscillator 24 512 spest PLLCLKou EXTALIN Crystal T i CT32B1_PCLK CT32B1 CT32B1 LXTALOUT oscillator Aleck source register block 32 768KHz a e AHB clock for CT32B0 Clock Prescaler 075280 T3280 A CT32BOCLKEN 1 2 4 8 16 clock source register block PLLCLKSEL AHB clock for CT16B1 NI UR CT16B1_PCLK CT16B1 CT16B1 lock Prescaler C l A CT16B1CLKEN 1 2 4 8 16 clock source register block AHB clock for CT16B0 32 768KHz CT16B0 Clock Prescaler 11657 128 CT16BOCLKEN 1 2 4 8 16 Clock source register block AHB clock for USART1 RTCSEL USART1 USART1_PCLK USART1CLKEN XTALIN gt High speed Crystal XTALOUT lt
84. 8 x 1 and the maximum Watchdog interval is Twpr peik x 128 x 256 The Watchdog should be used in the following manner 1 Select the clock source for the watchdog timer with WDTCLKSEL register 2 Set the prescale value for the watchdog clock with WDTPRE bits in APB Clock Prescale register 0 SYS1 APBCPO register 3 Set the Watchdog timer constant reload value TC register 4 Enable the Watchdog and setup the Watchdog timer operating mode in WDT CFG register 5 The Watchdog should be fed again by writing 0x55AA to WDT FEED register before the Watchdog counter underflows to prevent reset or interrupt When the watchdog is started by setting the WDTEN in register the time constant value is loaded in the watchdog counter and the counter starts counting down When the Watchdog is in the reset mode and the counter underflows the CPU will be reset loading the stack pointer and program counter from the vector table as in the case of external reset Whenever the value 0x55AA is written FEED register the value is reloaded in the watchdog counter and the watchdog reset or interrupt is prevented The watchdog timer block uses two clocks HCLK and WDT PCLK HCLK is used for the AHB accesses to the watchdog registers and is derived from the system clock The PCLK is used for the watchdog timer counting Several clocks can be used as a clock source for WDT PCLK clock IHRC ILRC ELS X tal and H
85. 85SDA 10 11 12 13 14 15 16 17 18 19 20 21 22 23 S 22222nu222223 Z lt lt lt lt lt Z Z lt lt lt lt lt S N DD 0 e OC CQ QN GQ QN n n 5 N X l m 5 SONiX TECHNOLOGY CO LTD Page 17 Version 2 0 d Sos X FL ded 1 5 PIN DESCRIPTIONS VDD VSS P Power supply input pins for digital circuit AVDD AVSS Power supply input pins for analog circuit VREG18 1 8V power pin Please connect 1uF capacitor to GND P0 0 Port 0 0 bi direction pin PO 0 URXD1 Schmitt trigger structure and built in pull up pull down resisters as input mode PO 1 UTXD1 Built in wakeup function URXD1 Receiver data input pin for USART1 P0 1 Port 0 1 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function UTXD1 USART1 Transmitter data output pin P0 2 Port 0 2 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function SCL1 1261 clock CT16BO CAPO 16 0 Capture input 0 P0 3 Port 0 3 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function SDA1 12 1 data pin CT32B0_PWM2 CT32B0 PWM output 2 P 0 4 Port 0 4 bi direction pin Schmitt trigger structur
86. CLK The clock to the watchdog register block can be disabled in AHB Clock Enable register SYS1 AHBCLKEN register for power savings Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source SONiX TECHNOLOGY CO LTD Page 89 Version 2 0 4 Sos X ke 92 BLOCK DIAGRAM Feed Watchdos WDT_TC WDT_FEED Feed OK Y Reload Counter 28 gt 8 bit Down Counter Enable Counter underflow M WDT WDINT WDTIE WDTEN J WDT Reset gt WDT Interrupt SONiX TECHNOLOGY CO LTD Page 90 Version 2 0 Y N N 9 Y SN32F720 Series D N 32 Cortex M0 Micro Controller 9 3 WDT REGISTERS Base Address 0x4001 0000 9 3 1 Watchdog Configuration register WDT CFG Address Offset 0x00 register controls the operation of the Watchdog through the combination of WDTEN and WDTIE bits This register indicates the raw status for Watchdog Timer interrupts A WDT interrupt is sent to the interrupt controller if both the WDINT bit and the WDTIE bit are set Reserved 08 0 Watchdog interrupt flag R W Read 0 Watchdog does not cause an interrupt 1 Watchdog timeout and causes an interrupt Only when WDTIE 1 Write 0 Clear this flag SW shall feed Watchdog before clearing Watchdog interrupt enable R W 0 Watchd
87. CT32B1 0Ox0000008C 36 Setable IRQ20 PSIRO 125 000000090 38 Setable IRQ22 USARTIIRO USART 7 0x00000098 39 IRQ23 I2C1IRQ_ 21 0 000000 40 Setabe IRQ24 ADCIRHO 1 1 0000000 41 A Setabe IRQ25 WDTIRO 00000004 42 9 Setable IRQ26 LVDIRQ LVD 1 1 0 0000008 43 IRQ27 RTCIRQ 1 1 00000002 4 Setable RQ28 PBIRO GPIO interrupt status of port3 _ 0x000000B0 _ 45 Setable 2 GPIO interrupt status of port2 0x000000B4 46 Settable IRQ30 PIIRO interrupt status of prt 0x0000 0088 IRQ11 090000 006 SONiX TECHNOLOGY LTD Page 27 Version 2 0 N o TRY SN32F720 Series Sv N x 32 Bit Cortex M0 Micro Controller 2 3 2 NVIC REGISTERS 2 3 2 1 1800 31 Interrupt Set Enable Register NVIC ISER Address 0xE000 E100 Refer to Cortex MO Spec The ISER enables interrupts and shows the interrupts that are enabled Interrupt set enable bits SETENADHSMI Write 0 No effect 1 Enable interrupt Read 0 Interrupt disabled 1 Interrupt enabled 2 3 2 2 IRQO 31 Interrupt Clear Enable Register ICER Address 0xE000 E180 Refer to Cortex MO Spec The ICER disables interrupts and shows the interrupts that are enabled LRENAI31 Interrupt clear enable bits Write 0 effect 1 Disable interrupt Read gt 0 Interrupt di
88. CT32Bn_MCTRL register must be set to zero except for the match register setting the PWM cycle length For this register set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register SONiX TECHNOLOGY CO LTD Page 83 Version 2 0 SONIX 8 7 CT32Bn REGISTERS Base Address 0 4000 4000 CT32B0 0x4000 6000 CT32B1 8 7 1 CT32Bn Timer Control register CT32Bn_TMRCTRL n 0 1 Address Offset 0x00 Note CEN bit shall be set at last Counter Reset R W 0 Disable counter reset 1 Timer Counter is synchronously reset on the next positive edge of PCLK This is cleared by HW when the counter reset operation finishes Counter Enable 1 Enable Timer Counter for counting 8 7 2 CT32Bn Timer Counter register CT32Bn_TC n 0 1 Address Offset 0x04 Unless it is reset before reaching its upper limit the will count up through the value OxFFFFFFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed 1 rib Name C 8 7 3 CT32Bn Count Control register CT16Bn_CNTCTRL n 0 1 Address Offset 0x10 This register is used to select between Timer and Counter mode and in Counter mode to select the pin and edges for counting When Counter Mode is
89. CTRICALCHARACTBRIS EIC 159 18 3 CHARACTERISTIC GRAPHS 160 19 FLASH ROM PROGRAMMING PIN 162 20 PACKAGE INFORMATION i 163 204 SU PIN 163 20 2 QFN46 PIN 164 21 MARKING DEEFINI ITION a aaa aaa 165 INTRODUCTION OL T uu 165 212 MARKINGINDETIFICATIONSYSTEM a 165 21 3 MARKING EXAMPLE 166 21 4 DATECODE SYSTEM 166 SONiX TECHNOLOGY LTD Page 11 Version 2 0 SON IX SN32F720 Series 32 Bit Cortex M0 Micro Controller 1 PRODUCT OVERVIEW 1 1 FEATURES Memory configuration 8KB on chip Flash programming memory 2KB SRAM 4KB Boot ROM Operation Frequency up to 50MHz Interrupt sources ARM Cortex MO built in Nested Vectored Interrupt Controller NVIC pin configuration Up to 43 General Purpose GPIO pins with configurable pull up pull down resistors GPIO pins can be used as edge and level sensitive inte
90. CTRL 2 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared 3123 Reseved PWM2IOEN CT16Bn_PWM2 GPIO selection bit R W 0 CT16Bn 2 pin act as GPIO 1 16 2 pin act as match output and output signal depends 2 bit PWM1IOEN CT16Bn_PWM1 GPIO selection bit R W 0 CT16Bn_PWM1 pin act as GPIO 1 CT16Bn_PWM1 pin act as match output and output signal depends on bit PWMOIOEN CT16Bn PWMO GPIO selection bit R W 0 CT16Bn PWMO pin act as GPIO 1 CT16Bn PWMO pin act as match output and output signal depends on PWMOEN bit 193 Reseved R O0 0 CT16Bn PWMe is controlled by 2 1 PWM mode is enabled for CT16Bn_PWM2 ENG It 0 CT16Bn is controlled by 1 PWM mode is enabled for CT16Bn_PWM1 Kumpa wa 0 CT16Bn PWMO is controlled by EMO SONiX TECHNOLOGY CO LTD Page 78 Version 2 0 Y N N Y SN32F720 Series D D E 32 Cortex M0 Micro Controller mode is enabled for 16 PWMO 7 7 10 CT16Bn Timer Raw Interrupt Status register CT16Bn_RIS n 0 1 Address Offset 0x38 This register indicates the raw status for Timer PWM
91. Data transfers are in principle full duplex with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data 11 2 FEATURES Compatible with Motorola SPI and 4 wire TI SSI bus Synchronous Serial Communication Supports master or slave operation 8 frame FIFO for both transmitter and receiver 4 bit to 16 bit frame Maximum SPI speed of 25 Mbps master or 6 Mbps slave in SSP mode Data transfer format is from MSB or LSB controlled by register The start phase of data sampling location selection is 1 or 2 d_phase controlled register VVVVVVVV SONiX TECHNOLOGY CO LTD Page 99 Version 2 0 NI 7 2 72 1 SO N i x 32 Bit 2 11 3 DESCRIPTION SCKn O SSP Serial clock Master LLL SSP Serial clock Slave Depends GPIOn SELn SPI Slave Select SSI Frame Sync Master NENNEN __ 1 SSP Slave Select Slave BDependsonGPIOn CFG MISOn I Master In Slave Out Master BDependsonGPlOn CFG Master In Slave Out Slave NENNEN Mos O Master Slave in Maste Master Out Slave In Slave CFG SONiX TECHNOLOGY LTD Page 100 Version 2 0 s lt Y N N x 32 Bit 2 2 11 4 DESCRIPTION 11 4 1 5 The SPI interface is a 4 wire interface where the SSEL
92. ECON USO Update this register will reset RTC_SECCNT and RTC ALMCNT HM PRSTU registers The zero value is not recommended and will be replaced with default value 0x8000 by HW 10 5 7 RTC Second Count register RTC_SECCNT Address offset 0x18 The RTC core has one 32 bit programmable counter and this register keeps the current counting value of this counter SECCNTI31 0 RTC second counter 31 0 The current value of the RTC counter 10 5 8 RTC Alarm Counter Reload Value register RTC_ALMCNTV Address offset 0x1C Reset value OxFFFFFFFF ALMCNTV 31 0 RTC alarm counter reload value R W OxFFFFFFFF Update this register will reset ALMCNT The zero value is not recommended and will be replaced with default value OXFFFFFFFF by HW SONiX TECHNOLOGY CO LTD Page 97 Version 2 0 VAY SN32F720 Series SO N 32 Bit Cortex M0 Micro Controller 10 5 9 RTC Alarm Count register RTC_ALMCNT Address offset 0x20 ALMONT 31 0 RTC alarm counter m The current value of the RTC alarm counter SONiX TECHNOLOGY CO LTD Page 98 Version 2 0 N N 7 SN32F720 Series 4 N N X 32 Bit Cortex M0 Micro Controller 1 1 SPI SSP 11 1 OVERVIEW The SSP is a Synchronous Serial Port controller capable of operation on a SPI and 4 wire SSI bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer
93. GPIO selection bit 0 2 2 pin act as GPIO 1 2 2 pin act as match output and output signal depends 2 bit PWM1IOEN CT32Bn_PWM1 GPIO selection bit 0 CT32Bn_PWM1 pin act as GPIO 1 CT32Bn_PWM1 pin act as match output and output signal depends bit PWM0IOEN CT32Bn PWMO GPIO selection bit 0 CT32Bn PWMO pin act as GPIO 1 CT32Bn PWMO pin act as match output and output signal depends PWMOEN bit Reserved PWM3EN PWMsB enable 0 2 PWNS is controlled by EM3 1 PWM mode is enabled for CT32Bn_PWM3 PWM2EN PWM2 enable 0 2 PWMe is controlled by EM2 1 PWM mode is enabled for 2 0 PWM1EN PWM1 enable 0 2 is controlled by 1 PWM mode is enabled for CT32Bn_PWM1 SONiX TECHNOLOGY CO LTD Page 87 Version 2 0 SON IX PWMOEN PWM0 enable R W 0 CT32Bn_PWM0 is controlled by EMO 1 PWM mode is enabled for 2 PWMO 8 7 10 CT32Bn Timer Raw Interrupt Status register CT32Bn_RIS n 0 1 Address Offset 0x38 This register indicates the raw status for Timer PWM interrupts A Timer PWM interrupt is sent to the interrupt controller if the corresponding bit in the CT16Bn IE register is set lame _31 5 Reserved EIE Interrupt flag for capture channel 0 0 No interrupt on CAPO 1 Interrupt requirements met on CAPO Interrupt for match channel 3 0 No in
94. LVD reset level R W 00 The reset assertion threshold voltage is 2 40V 01 The reset assertion threshold voltage is 2 70V 10 The reset assertion threshold voltage is 2 00V 11 Reserved SONiX TECHNOLOGY CO LTD Page 47 Version 2 0 WY SN32F720 Series Sv N a 32 Bit Cortex M0 Micro Controller 3 3 8 External RESET Pin Control register 5 50 EXRSTCTRL Address Offset 1 eT RESETDIS External RESET pin disable bit 0 Enable external RESET pin P3 6 acts as RESET pin 1 Disable P3 6 acts as GPIO pin 3 3 9 SWD Pin Control register SYS0 SWDCTRL Address Offset 0x20 S11 Reseved __ jJ R O SWDDIS SWD pin disable bit 0 Enable SWD pin P0 11 acts as SWDIO pin P0 10 acts as SWCLK pin 1 Disable P0 11 and P0 10 act as GPIO pins 3 3 10 Anti EFT Ability Control register 5 50 Address Offset 0x30 This register decides the HW anti EFT ability 958 Reseed oo 0_ oos RW 000b 010 Low 011 Medium 100 Strong SONiX TECHNOLOGY LTD Page 48 Version 2 0 NP 7 1 Sos X 34 SYSTEM CONTROL REGISTERS 1 Base Address 0x4005 E000 3 4 1 AHB Clock Enable register SYS1_AHBCLKEN Address Offset 0x00 The SYS_AHBCLKEN register enables the AHB clock to individual system and peripheral blocks Note gt 1 When the clock is disabled the peripheral register values may not be readable by SW a
95. MODE 6 GPIOn gt Specific Input Bus Pin gt Input Bus GPIOPn_MODE lt GPIOn_CFG Latch Output Bus Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn MODE register Bi direction I O Pin Shared with Specific Digital Output Function e g SPI I2C Reu GPIOPn MODE x GPIOn_CFG Pin gt I O Input Bus GPIOPn_MODE gt lt GPIOn_CFG Output Latch Specific Output Bus Specific Output Function Control Bit Specific Input Function Control Bit Some specific functions switch I O direction directly not through GPIOn MODE register SONiX TECHNOLOGY CO LTD Page 21 Version 2 0 N V SN32F720 Series NS x 32 Bit Cortex M0 Micro Controller e Bi direction I O Pin Shared with Specific Analog Input Function e g XIN ADC Reu GPIOPn MODE x GPIOn_CFG Pin gt I O Input Bus 4 GPIOn_CFG GPIOPn MODE EN Latch 4 I O Output Bus Analog IP Input Terminal Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn MODE register Bi
96. N N 7 SN32F720 Series N N 32 Bit Cortex M0 Micro Controller SN32F720 Series USER S MANUAL SN32F727 SN32F726 32 Bit Cortex MO Micro Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part SONiX TECHNOLOGY CO LTD Page 1 Version 2 0 NONA SN32F720 Series 32 Bit Cortex M0 Micro Controll
97. NOLOGY CO LTD Page 46 Version 2 0 SON IX 315 Reseved PORRSTF POR reset flag Set by HW when a POR reset occurs 0 Read No POR reset occurred Write Clear this bit 1 POR reset occurred EXTRSTF External reset flag Set by HW when a reset from the RESET pin occurs 0 Read No reset from RESET pin occurred Write Clear this bit 1 Reset from RESET pin occurred Attribute LVDRSTF LVD reset flag R W Set by HW when a LVD reset occurs 0 Read gt No LVD reset occurred Write gt Clear this bit 1 LVD reset occurred WDTRSTF WDT reset flag R W Set by HW when a WDT reset occurs 0 Read No watchdog reset occurred Write Clear this bit 1 Watchdog reset occurred SWRSTF Software reset flag R W Set by HW when a software reset occurs 0 Read gt No software reset occurred Write gt Clear this bit 1 Software reset occurred 3 3 7 LVD Control register SYSO_LVDCTRL Address Offset 0x18 The LVD control register selects four separate threshold values for generating a LVD interrupt to the NVIC or LVD reset vescription Attripute Hesel Reewed 0 Disable 1 Enable LVDRSTEN LVD Reset enable 0 Disable 1 Reseved 8 R 0 Reseved LVDINTLVL 1 0 LVD interrupt level R W 00 The interrupt assertion threshold voltage is 2 00V 01 The interrupt assertion threshold voltage is 2 70V 10 The interrupt assertion threshold voltage is 3 00V 11 Reserved LVDRSTLVL 1 0
98. On CFG 12 4 WAVE CHARACTERISTICS mE N I 1 l g P Data Data ru EE START Change Change STOP Signal Allowed Allowed Signal SONiX TECHNOLOGY CO LTD Page 109 Version 2 0 N NI j SN32F720 Series N N E x 32 Bit Cortex M0 Micro Controller 12 5 12 MASTER MODES 12 5 1 MASTER TRANSMITTER MODE Write 1 to STA bit START condition begins From Slave STA 0 j 1 Transmit Address gw o Transmission Data SDA Y 4 Write address and TXDATA Start transmit SCL held Low I SCL food ot S V tV J2V 4 5 6 7 9 2 3144 5V J6 U7 J8V J9V Write to TXDATA SCL i Falling ninth clock Repeat Start End of transmission 12 5 2 MASTER RECEIVER MODE Write 1 to ACK bit Write 1 to ACK bit Start Acknowledge sequence Start Acknowledge sequence Write 1 to STA bit START condition begins From Slave AGO Master 2 Write 1 to STO i STA 0 I I I 1 Transmit Address to Slave R W 1 Receiving Data from Slave Receiving Data from Slave v SDA it Cg CS CS C5 C9 C2 C Td 0 Ipz pe pslpa pa p2 pil D pelpe ps p4 pa p2 pil D 0 jac K y Write address and lt q ACK_is not sen
99. R OVERVIEW 31 3 SYSTEM 32 S Sans ua Edd uu Eu Rud M d Mc 32 3 1 1 POWER ON RESET POR etes te css nba mu EP Gesta LIRE Ice depu esten 32 312 WATCHDOG RESET WIE Raten is ed 33 3 1 3 BROWN QOUT ORE H 33 SONiX TECHNOLOGY CO LTD Page 3 Version 2 0 IN 7 SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller 4 13 1 BROWN OUT DESCRIPTION 33 3 1 3 2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION 34 31 3 3 BROWN OUT RESET IMPROVEMENT naa 34 3 1 4 FAXTHENRNALRESET m rFO O O M 35 3141 SIMPLY RC RESET CIRCUIT 36 A142 DIODE RC RESET CIRCUIT 36 S145 ZENER DIODE cati ui esas 37 3 1 4 4 VOLTAGE BIAS RESET CIRCUIT 37 3145 EXTERNAL RESET IC eT ha 38 222 SOFTWARE RESET sascha canta 38 3 2 SYSTEM CLOCK 39 3 2 1 INTERNAL RC CLOCK SQURCE au asaassassanaa
100. RVIEW e 54 4 2 NORMAGMODE n 54 43 Gs qi dq 8 0 e 54 4 3 1 5 MODE 54 4 3 2 DEEP SLEEP raa irse big vA PU dta Qu UI RAT 55 4 3 3 DEEP POWER DOWN DPD naa 55 4 3 3 Entering Deep power down mode 56 4 3 3 2 Exiting Deep power down mode 56 44 WAREUPINTBERRLUPT 56 4 5 STATE MACHINE OF PMU anis 56 4 6 OPERATION MODECOMPARSION TAB IE 57 4 7 PMUREGISTERS uu ul EE EES 58 4 7 1 Backup registers 0 to 15 PMU_BKP0 15 58 4 7 2 Power control register PMU_CTRL Rus apdE 56 GENERAL PURPOSE I O PORT GPIO 59 5 1 OVERVIEW umama mu MM DE M SM 59 52 GPIOMODE c as Si 59 5 3 GPIO REGISTERS 60 5 3 1 GPIO Port n Data register GPIOn DATA n 0 1 2 3
101. Reserved EHSRDY External high speed clock ready flag SONiX TECHNOLOGY CO LTD Page 45 Version 2 0 SON IX 0 EHS oscillator not ready 1 EHS oscillator e 8 Reserved ELSRDY low speed clock ready flag 0 EHS oscillator not ready 1 EHS oscillator ready 1 Reserved 0 IHRC not ready 1 IHRC ready 3 3 4 System Clock Configuration register 5 50 CLKCFG Address Offset 0 0 System clock switch status Set and cleared by HW to indicate which clock source is used as system clock 000 IHRC is used as system clock 001 ILRC is used as system clock 010 EHS X TAL is used as system clock 011 ELS X TAL is used as system clock 100 PLL is used as system clock Other Reserved System clock switch Set and cleared by SW 000 IHRC 001 ILRC 010 EHS 011 ELS X TAL 100 PLL output Other Reserved 3 3 5 AHB Clock Prescale register 5 50 AHBCP Address Offset 0x10 304 Reseved 3 0 AHB clock source prescale value R W 0000 SYSCLK 1 0001 SYSCLK 2 0010 SYSCLK 4 0011 SYSCLK 8 0100 SYSCLK 16 0101 SYSCLK 32 0110 SYSCLK 64 0111 SYSCLK 128 1000 SYSCLK 256 1001 SYSCLK 512 Other Reserved 3 3 6 System Reset Status register 5 50 RSTST Address Offset 0x14 This register contains the reset source except DPDWAKEUP reset since the LPFLAG bit in PMU CTRL register had presented this case SONiX TECH
102. Return to Zero NRZ transmit bit stream output from USART The output pulse stream is transmitted to an external output driver and infrared LED USART supports only bit rates up to 115 2Kbps for the SIR ENDEC In normal mode the transmitted pulse width is specified as 3 16 of a bit period The SIR receive decoder demodulates the Return to Zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to USART The decoder input is normally HIGH marking state in the Idle state The transmit encoder output has the opposite polarity to the decoder input A start bit is detected when the decoder input is low gt is a half duplex communication protocol If the Transmitter is busy i e the USART is sending data to the IrDA encoder any data on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy USART is receiving decoded data from the USART data on the TX from the USART to IrDA will not be encoded by IrDA While receiving data transmission should be avoided as the data to be transmitted could be corrupted gt 0 5 transmitted as a high pulse and 1 is transmitted as a 0 The width of the pulse is specified as 3 16th of the selected bit period in normal mode Start stop bit bit 0 1 0 1 0 0 1 1 0 1 bit perjod IrDA OUT 154 IrDA IN 1 RX 0 0 gt SIR decoder converts the IrDA compliant receive signal into a bit s
103. SLV TX HIT 0 No matched slave address 7 SVTXHT 1 Slave address hit and is called for TX in slave mode LV RX HIT 0 No matched slave address 1 Slave address hit and is called for RX slave mode 12 Master Slave status 0 l2C is in Slave state 1 12C is in Master state START DN Start done status 0 No START bit 1 MASTER mode a START bit was issued SLAVE mode a START bit was received STOP DN Stop done status 0 STOP bit 1 MASTER STOP condition was issued SLAVE mode a STOP condition was received NACK STAT NACK done status a 0 Not received a NACK 1 Received a NACK ACK STAT ACK done status 0 received 1 Received RX DN RX done status 0 No RX with ACK NACK transfer 1 8 bit RX with ACK NACK transfer is done SONiX TECHNOLOGY CO LTD Page 114 Version 2 0 kq Z WAY SN32F720 Series SO N N 32 Cortex M0 Micro Controller 12 8 3 2 n TX Data register 12 nz0 1 Address 0 08 This register contains the data to transmitted In Master TX mode CPU writes this register will trigger a TX function In Slave TX mode CPU has to write this register before next TX procedure _318 Reserved R j DATA 7 0 12 8 4 2 n RX Data register I2Cn RXDATA n 0 1 Address Offset 0 0 91 8 Reserved 8 R O DATA 7 0 Contains the data received Read this reg
104. SYS0_CLKCF6 46 3 3 5 AHB Clock Prescale register SYS0_AHBCP 46 3 3 6 System Reset Status register SYSO_RSTST 46 3 3 7 LVD Control register SYS0_LVDCTRL 47 3 3 8 External RESET Pin Control register SYS0_EXRSTCTRL 48 3 3 9 SWD Pin Control register SYS0_SWDCTRL 48 3 3 10 Ability Control register SYS0_ANTIEFT 48 3 4 SYSTEM CONTROL REGISTERS l aaa EEEE R Fest btc 49 3 4 1 AHB Clock Enable register SYSI_AHBCLKEN 49 3 4 2 APB Clock Prescale register 0 SYSI_APBCP0 50 3 4 3 APB Clock Prescale register 1 SYSI_APBCP1 51 SONiX TECHNOLOGY CO LTD Page 4 Version 2 0 IN N SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller 4 6 3 4 4 Peripheral Reset register 22 SYSTEM OPERATION 54 4 1 OVE
105. Slave In for SSP1 P3 4 Port 3 4 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode XTALIN External low speed X tal input pin P3 5 Port 3 5 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode XTALOUT External low speed X tal output pin P3 6 Port 3 6 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode RESET External Reset input Schmitt trigger structure active Low normally stay High P3 7 Port 3 7 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode XTALIN External high speed X tal input pin P3 8 Port 3 8 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode XTALOUT External high speed X tal output pin SONiX TECHNOLOGY CO LTD Page 20 Version 2 0 S NN Y SN32F720 Series 32 Bit Cortex M0 Micro Controller 1 6 PIN CIRCUIT DIAGRAMS Normal Bi direction Pin GPIOPn MODE I gt I O Input Bus GPIOPn MODE 6 Output Latch T O Output Bus Rep e Bi direction I O Pin Shared with Specific Digital Input Function e g SPI 12 Specific Input Function Control GPIOPn
106. UD RATE CALCULATION 121 13 7 MODEM CONTROL u a nunana E eta EE A aad us a RH 123 AVLO RTS SSS 123 13 7 2 E 124 13 8 FLOW 124 4204 AUTO PAUD l 124 AUTO BAUD MODES 125 13 9 SERIAT IREDATSIR MODE 126 13 10 SMART CARD MODE XU Mu IE MM DD PM UR r 128 13 10 1 SMART CARD SETUP PROCEDURE on pasados 128 13 11 SYNCHRONOUS MODE T 129 1512 Hp nee 130 134241 USART n Receiver Buffer register USARTn RB 0 1 130 13 12 2 USART n Transmitter Holding register USARTn TH n O 1 130 13 12 3 USART n Divisor Latch LSB registers USARTn DLL n 0 1 130 13 12 4 USART n Divisor Latch MSB register USARTn n 0 1 130 13 12 5 USART n Interrupt Enable register USARTn IE 0 1 131 13 12 6 USART n Interrupt Identification register USARTn II n 0 1 131 13 12 7 USART n FIFO Control register USARTn_FIFOCTRL n 0 1 133 13 1
107. USART1 Clock Prescaler 1 2 4 8 16 oscillator 1MHz 25MHz USART1 register block clock source clock for USARTO NL USARTO PCLK USARTOCLK a USARTO USARTO 1 2 4 8 16 gt clock source register block m 4 AHB clock for I2C1 i I2C1_PCLK I2C1 I2C1CLKEN aate Clock source register block AHB clock for GPIO GPIO block GPIOCLKEN AHB clock for SRAM gt SRAM block AHB clock for FLASH gt FLASH block AHB clock for RTC RTCCLKEN RTC_PCLK RTC RTC clock source register block SONiX TECHNOLOGY CO LTD Page 15 Version 2 0 SON IX 1 4 PIN ASSIGNMENT SN32F727F LQFP 48 pins D Ex 2 0 o 5 FE z O gt O Z F O 3 gt 9 EER EEI co u s lt al al a 5 x x Godda ug O ONT O C co gt gt gt D 48 47 46 45 44 43 42 41 40 39 38 37 1 1 36 P0 1 UTXD1 2 35 P0 2 CT16BO CAPO SCL1 3 34 2 0 PWMO2 SDA1 4 33 P0 4 SCLO0 5 32 5 50 016 31 N32F727F P0 6 SCK0 7 ons 30 PO 7 SELO 8 29 P0 8 MISOO CT16BO 9 28 P0 9 MOSIO CT16BO PWM 1 10 27 P0 10 SWCLK CT16BO PWM2 1 26 P0 11 SWDIO CT32BO0 PWM3 12 25 13 14 15 16 17 18 19 20 21 22 23 24
108. age from P2 0 must be higher than Low reference voltage 2V The low reference voltage is ground So the external reference voltage range must be under 2V Vdd 6 3 2 ADC PROGRAM The first step of ADC execution is to setup ADC configuration The ADC program setup sequence and notices are as following e Step 1 Enable ADC ADENB is ADC control bit to control ADENB 1 is to enable ADC ADENB 0 is to disable ADC When ADENEB is enabled the system must be delay 100us to be the ADC warm up time by program and then set ADS to do ADC converting The 100us delay time is necessary after ADENB setting not ADS setting or the ADC converting result would be error Normally the ADENB is set one time when the system under normal run condition and do the delay time only one time e Step 2 If the ADC high reference voltage is from external voltage source set the AVREFHSEL 1 The ADC external high reference voltage inputs from P2 0 pin It is necessary to set P2 0 as input mode without pull up resistor Step 3 Select the ADC input pin by CHS 3 0 enable P2CON s related bit for the ADC input pin and enable ADC global input When one AIN pin is selected to be analog signal input pin it is necessary to setup the pin as input mode and disable the pull up resistor by program Also to set the P2CON and the digital I O function including pull up is isolated Step 4 Start to execute ADC conversion by setting ADS 1 Step 5 Wait the
109. allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the external high clock or the internal high RC oscillator Clock output function which can reflect the internal high low RC oscillator HCLK PLL output and external high low clock Serial Wire Debug SWD In System Programming ISP supported Package Chip form support LQFP 48 pin QFN 46 pin Version 2 0 S SN32F720 Series 32 Bit Cortex M0 Micro Controller Features Selection Table Boot Freq 12 bit GPIO Wakeup Chip ROM RAM Loader Max USART TIMER SPI 12 125 PWM bib Package 16 bitx2 SN32F727F 8KB 2KB 4KB 50 MHz 2 32 bitx2 2 2 1 13 10CH 43 13 LQFP48 16 bitx2 SN32F726J 8KB 2KB 4KB 50 MHz 1 1 2 2 1 13 10 41 11 46 SONiX TECHNOLOGY LTD 13 Version 2 0 So X SN32F720 Series 32 Bit Cortex M0 Micro Controller 1 2 SYSTEM BLOCK DIAGRAM SWDIO SWCLK XTALIN LXTALIN XTALOUT LXTALOUT CLKOUT URXO UTX0 USCLK0 URI0 UDTR0 UDSR0 UCTS0 UDCD0 URTSO 1 URX1 UTX1 SCK0 SELO SDIO SDOO SCK1 SEL1 SDH 5001 SCL0 SDA0 SCL1 SDA1 25 I2SWS I2SSDA 25 TEST DEBUG INTERFACE ARM CORTEX M0 qm ILRC IHRC 16KHz 12MHz SYSO SYS1 PMU USARTO USART1 SPIO SPI
110. an then read the address byte and decide whether or not to enable the receiver to accept the following data While the receiver is enabled RXEN 1 in USARTn RS485CTRL register all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver 13 5 2 RS 485 EIA 485 AUTO ADDRESS DETECTION AAD MODE When both 9 bit mode enable bit and AADEN AAD mode enable bit in USARTn RS485CTRL register are set the USART is in auto address detect mode In this mode the receiver will compare any address byte received parity 1 to the 8 bit value programmed into the USARTn RS485ADRMATCH register If the receiver is disabled RXEN 0 in USARTn RS485CTRL register any received byte will be discarded if it is either data byte or an address byte which is different from the value USARTn RS485ADRMATCH register When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit and the receiver will be automatically enabled RXEN bit will be set by HW The receiver will also generate an RX Data Available RDA Interrupt While the receiver is enabled RXEN 1 in USARTn RS485CTRL register all bytes received will be accepted and stored in the RXFIFO until an address byte which is different from the MATCH
111. arm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from 0 0 Watchdog timer application note is as following Before clearing watchdog timer check status and check RAM contents can improve system error Don t clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information 3 1 3 BROWN OUT RESET 3 1 31 BROWN OUT DESCRIPTION The brown out reset is a power dropping condition The power drops from normal voltage to low voltage by external factors e g EFT interference or external loading changed The brown out reset would make the system not work well or executing program error VDD System Work Well Area Brown Out Reset Diagram The power dropping might through the voltage range that s the system dead band The dead band means the power range can t offer the system minimum operation power requirement The above diagram is a typical brown out reset diagram There is a serious noise under the VDD and VDD voltage drops very deep There is a dotted line to separate the system working area The above area is the system work well area The below area
112. art bit and the character LSB for MODE 0 in USARTn ABCTRL register the rate counter will continue incrementing with the pre scaled USART input clock USARTn PCLK 5 If MODE 0 the rate counter will stop on next falling edge of the USART pin If MODE 1 the rate counter will stop on the next rising edge of the URXD pin 6 The rate counter is loaded into USARTn DLM USARTn DLL and the baud rate will be switched to normal operation After setting the DLM DLL the end of auto baud interrupt ABEOINT in USARTn II register will be set if enabled The RSR will now continue receiving the remaining bits of the character gt AUTO BAUD RATE MODE 0 Waveform 0x41 or a 0x61 gt Start bito bitt bits V bit Parity Y Stop URXD Start bit LSB of A or a START bit in USARTn_ABCTRL Rate Counter 16 x Baud Rate UI 16 Cycles 16 Cycles gt AUTO BAUD RATE MODE 1 Waveform SONiX TECHNOLOGY CO LTD Page 125 Version 2 0 N j SN32F720 Series N N a X 32 Bit Cortex M0 Micro Controller A 0x41 or a 0x61 bit3 bit4 bit1 URXD Start bit LSB of A or g START bit in n MEME Qs Rate Counter 16 x Baud Rate UMUUUHUHMUUHUUMUUUII 16 Cycles bit2 13 9 SERIAL IRDA SIR MODE The IrDA mode is enabled by setting the USARTEN bit to 1 and MODE 2 0 010b in USARTn CTRL register The SIR Transmit encoder modulates the Non
113. as possible to the LXIN LXOUT VSS pins of MCU The capacitor between LXIN LXOUT and VSS must be 10pF 3 2 3 5 Bypass Mode Descriptior In Bypass mode the external clock signal Square sinus or triangle with 50 duty XTALOUT cycle must be provided to drive the XTALIN LXTALIN pin while the XTALOUT T LXTALOUT pin should be the inverse of External clock source the input clock signal Bypass EHS X tal can have a frequency of up to 25 MHz Select this mode by setting EHSEN bit in Analog Block Control register SYS0 ANBCTRL SONiX TECHNOLOGY CO LTD Page 42 Version 2 0 N N 9 Y SN32F720 Series N PPA TA 32 Bit Cortex M0 Micro Controller ELS X TAL must have a frequency of 32 768 KHz You select this mode by setting ELSEN bit in Analog Block Control register SYS0 ANBCTRL XTALIN XTALOUT LXTALIN LXTALOUT 1 to 25 MHz EHS XTAL has the advantage of producing a very accurate rate External X TAL on the main clock ERSIELS A TAL ELS X TAL must have a frequency of 32 768 KHz Load capacitors 3 2 4 SYSTEM CLOCK SYSCLK SELECTION After a system reset the IHRC is selected as system clock When a clock source is used directly or through the PLL as system clock it is not possible to stop it A switch from one clock source to another occurs only if the target clock source is ready clock stable after startup delay or PLL locked If a clock source which is not yet ready is selected
114. asahayqasaasanqasasqayasaasaskaqsaqashawaqasasiqaysqasaqskay 39 3 2 1 1 Internal High speed RC nasa 39 24 1 2 intemal Low speed RC Oscillator ILRC 39 22 2 s aang aed weds E OA 40 3 2 21 PLL FreguencyselectON 40 3 2 3 EXTERNAL CLOCK SOURCE 41 3 2 3 1 External High speed EHS Clot k u n aia i Glee 41 3 2 3 5 RY STALICER SUFFER LO EE EEES EE EN Eee EEEE 41 3 2 3 3 External Low speed ELS Clock 42 222 02 CRYSTAL nsise nea E AEEA E EEEE A E E AERE 42 323 3 Bypass Mode rreren n uama E E E MM M MM a MM M 42 3 2 4 SYSTEM CLOCK SYSCIK SELECTION ua aaa E 43 3 2 5 CLOCK OUT CAPABITITY E 43 3 3 SYSTEM CONTROL REGISTERS O 44 ENS Analog Block Control register SYS0_ANBCTRL 44 3 3 2 PLL control register SYS0_PLLCTRL a 44 3321 RECOMMEND FREQUENCY SETTING 45 3 3 3 Clock Source Status register SY 30 _CSST 45 3 3 4 System Clock Configuration register
115. ata is shifted onto the DR pin by the off chip serial slave device Both the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched 11 4 3 COMMUNICATION FLOW 11 4 3 1 SINGLE FRAME B n gt t uod or t RUN CI CPHA 1 SPI t ll gt TI FS DX DR MSB LSB SONiX TECHNOLOGY LTD Page 102 Version 2 0 N WY SN32F720 Series Sv NS 32 Bit Cortex M0 Micro Controller 11 4 3 2 MULTI FRAME SPI TI FO FO FO FO Fl Fl Fl Fl msb sb msb 155 SCK CS FO FO FO FO Fl Fl FI Fl DATA ml SONiX TECHNOLOGY LTD Page 103 Version 2 0 IN Z So S X PEME oi au herd 11 5 SSP REGISTERS Base Address 0x4001 C000 55 0 0 4005 8000 55 1 11 5 1 SSP Control register 0 SSPn_CTRLO n 0 1 Address Offset 0x00 Note gt 1 Must reset SSP FSM with FRESET 1 0 after changing any configuration of SSP when SSPEN 1 gt 2 HW will switch configurations refer to FORMAT bit directly when SSPEN 1
116. atus register SSPn RIS n 0 1 Address Offset 0x14 This register contains the status for each interrupt condition regardless of whether or not the interrupt is enabled in SSPn register This register indicates the status for SSP control raw interrupts An SSP interrupt is sent to the interrupt controller if the corresponding bit in the SSPn IE register is set Reserved TX FIFO is at least half empty or not 0 TX FIFO isn t at least half empty 1 TX FIFO is at least half empty RX FIFO is at least half full or not 0 RX FIFO isn t at least half full 1 RX FIFO is at least half full RXTOIF RX time out interrupt flag RXTO occurs when the RX FIFO is not empty and has not been read for a time out period 32 55 The time out period is the same for master and slave modes 0 RXTO doesn t occur 1 RXTO occurs RXOVFIF RX Overflow interrupt flag RXOVF occurs when the RX FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 0 RXOVF doesn t occur 1 RXOVF occurs 11 5 7 SSP n Interrupt Clear register SSPn IC n 0 1 Address Offset 0x18 2 u s Kum mi 9 more 0 W 11 5 8 SSP n Data register SSPn DATA n 0 1 Address Offset 0x1C TH 1c 31136 Reseved Write SW write data to be sent
117. bit 1 of USARTn MC register This permits modem status interrupts to be generated in Loopback mode by writing and bit 1 of MC register This bit provides a local loopback feature for diagnostic testing of the USART When this bit is set to 1 the following occur the transmitter TXD is set to the Marking logic 1 state the RXD is disconnected the internal TXD and RXD pin are connected the 4 MODEM Control inputs DSR CTS RI and DCD are disconnected and the 4 MODEM Control outputs RTS OUT1 and OUT2 are internally connected to the 4 MODEM Control inputs and the MODEM Control output pins are forced to their inactive state high In the loopback mode data that is transmitted is immediately received This feature allows the processor to verify the transmitter and receiver data paths of the USART In the loopback mode the receiver and transmitter interrupts are fully operational Their sources are external to the part The MODEM Control Interrupts are also operational but the interrupts sources are now the lower four bits of the MODEM Control Register instead of the four MODEM Control inputs The interrupts are still controlled by the Interrupt Enable Register 3 OU This bit controls the OUT2 internal signal in loopback mode only and OUT2 is internally connected to DCD 2 This bit controls the OUT1 internal signal in loopback mode only and OUT2 is internally connected 01
118. both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data 0 THR and or TSR contains valid data 1 THR and TSR are empty THRE Transmitter Holding Register Empty flag THRE indicates that the USART is ready to accept a new character for transmission In addition this bit causes the USART to issue THRE interrupt to if THREIE 1 THRE 1 when a character is transferred from the THR into the TSR The bit is reset to logic 0 concurrently with the loading of the Transmitter Holding Register by the CPU 0 THR contains valid data 1 THR TX FIFO is empty Break Interrupt flag When 1 is held in the spacing state all zeros for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all ones A USARTn LS register read clears BI bit The time of break detection is dependent FIFOEN bit in USARTn FIFOCTRL register 0 Break interrupt status is inactive 1 Break interrupt status is active FE Framing Error flag When the stop bit of a received character is a logic 0 a framing error occurs A USARTn LS register read clears FE bit The time of the framing error detection is dependent on FIFOEN bit in USARTn FIFOCTRL register Upon detection of a framing error the RX will attempt to re synchronize to the data and assume that the bad stop bit is actually an early start bit Howev
119. ched parity bit will be even 10 Forced 1 stick parity 11 Forced 0 stick parity Enable bit Disable parity generation checking 1 Enable parity generation and checking Stop Bit Select bit 0 1 stop bit 1 2 stop bits 1 5 if WLS bits 00 Must be 1 in Smart card mode Word Length Select bits 0 00 5 bit character length FUW 01 6 bit character length 10 7 bit character length 11 8 bit character length 13 12 9USART n Modem Control register USARTn nz0 1 Address Offset 0x10 SONiX TECHNOLOGY CO LTD Page 133 Version 2 0 N N 9 Y SN32F720 Series 32 Cortex M0 Micro Controller This register enables the modem loopback mode and controls the modem output signals _318 Reserved 7 CTS enable bit 0 Disable Auto CTS flow control 1 Enable Auto CTS flow control RTSEN RTS enable bit 0 Disable Auto RTS flow control 1 Enable Auto RTS flow control ERN M LMS Modem Loopback Mode Select bit 0 Disable 1 Enable The modem loopback mode provides a mechanism to perform diagnostic loopback testing Serial data from the transmitter is connected internally to serial input of the receiver RXD has no effect on loopback and TXD is held in marking state The DSR CTS DCD and RI pins are ignored Externally DTR and RTS are set inactive Internally the bit 4 and bit 5 of USARTn MS register are driven by bit 0 and
120. ction in order to use P0 10 and P0 11 as GPIO and may not debug by SWD function to debug or download FW any more SONIX provide Boot loader to check the status of P0 2 BOOT pin during boot procedure If P0 2 is Low during Boot procedure MCU will execute code in Boot loader instead of User code so SWD function is not disabled Exit Boot loader user code can still configure P0 2 as other functions such as GPIO 16 4 3 INTERNAL PULL UP DOWN RESITIORS on SWD PINS To avoid any uncontrolled IO levels the device embeds internal pull up and pull down resistor on the SWD input pins gt NJTRST Internal pull up gt SWDIO JTMS Internal pull up gt SWCLK JTCK Internal pull down Once a SWD function is disabled by SW the GPIO controller takes control again SONiX TECHNOLOGY CO LTD Page 156 Version 2 0 SONIX 1 7 SONIX provides an Embedded ICE emulator system to offer SN32F720 series MCU firmware development SN32F720 Embedded ICE Emulator System includes SN32F727 Starter Kit SN LINK USB cable to provide communications between the SN Link and PC IDE Tools KEIL RVMDK USB Cable to PC SN32F727 Starter Kit SN LINK IDE Tools 17 1 SN LINK SN LINK is a high speed emulator for 32 bit series MCU It debugs and programs based on SWD protocol In addition to debugger functions the SN LINK also may be used as a programmer to load firmware from PC
121. dge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently the duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 x 1 Note If Counter mode is selected in the CNTCTRL register Capture Control CAPCTRL register must be programmed as 0 0 SONiX TECHNOLOGY CO LTD Page 75 Version 2 0 SON IX Bit Name Description Attribute Reset 314 Reseved CIS 1 0 Count Input Select In counter mode when 1 0 are not 00 these bits select which pin is sampled for clocking 00 CT16Bn_CAP0 Other Reserved CTM 1 0 Counter Timer Mode This field selects which rising PCLK edges can clear PC and increment Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Counter Mode TC is incremented on rising edges on the CAPO input selected by CIS bits 10 Counter Mode TC is incremented on falling edges on the CAPO input selected by CIS bits 11 Counter Mode TC is incremented on both edges on the CAPO input selected by CIS bits 7 7 4 CT16Bn Match Control register 16 MCTRL nz0 1 Address Offset 0x14 Description Stop TC will stop and CEN bit will be cleared if MR3 matches 1 Enable Enable reset when matches 1 Enable Enable generating an interrupt when MR3 matches the value in the TC 1 Enable
122. e ARM Cortex MO WEI instruction 4 3 2 DEEP SLEEP MODE In Deep sleep mode the system clock to the ARM Cortex MO core is stopped and execution of instructions is suspended The clock to the peripheral functions are stopped because the power state of oscillators are powered down the clock source are stopped except RTC low speed clock source ELS X TAL ILRC if used Note User SHALL decide to power down RTC low speed clock source ELS X TAL oscillator or not if RTC is enabled The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Wake up the chip from Deep sleep mode by GPIO P0 0 P0 11 or RTC interrupt The RESET pin has keep functionality in Deep sleep mode The Deep sleep mode is entered by using the following steps 1 Write 1 to DSLEEPEN bit in PMU CTRL register 2 Execute ARM WFI instruction The advantage of the Deep sleep mode is that can power down clock generating blocks such as oscillators and PLL thereby gaining far greater dynamic power savings over Sleep mode In addition the Flash can be powered down in Deep sleep mode resulting in savings in static leakage power however at the expense of longer wake up times for the Flash memory 4 3 3 DEEP POWER DOWN DPD MODE In Deep power down mode power Turn off the on chip voltage regulator and clocks are shut off to the entire chip with the exce
123. e and built in pull up pull down resisters as input mode Built in wakeup function SCLO 12C0 clock pin P0 2 CT16BO SCL1 P0 3 SDA1 CT32B0_PWM2 P0 5 Port 0 5 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode PO S SDAO Built in wakeup function P0 6 SCKO PO 7 SELO SDAO 1280 data P0 6 Port 0 6 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function SCKO 55 0 Serial clock pin P0 7 Port 0 7 bi direction pin with high current sink driver Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function SELO SSPO Select pin P0 8 Port 0 8 bi direction pin PO 8 MISOO0 oa trigger structure and built in pull up pull down resisters as input mode uilt in wakeup function MISO0 55 0 Master In Slave Out pin 16 0 PWMO CT16B0 PWM output 0 P0 9 Port 0 9 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function MOSI0 SSPO Master Out Slave In pin 16 0 PWM1 CT16B0 PWM output 1 P0 10 Port 0 10 bi direction pin P0 10 SWCLK Schmitt trigger structure and built in pull up pull down resisters as input mode P0 9 MOSI0 CT16B0_PWM1 1 0 1 0 Built in wake
124. e by DPDWAKEUP pin reset source be identified checking the reset flags System Reset Status register SYS0 RSTST These sources act on the RST pin and it is always kept low during the delay phase The RESET service routine vector is fixed at address 0x00000004 in the memory map For more details refer to Interrupt and Exception Vectors Finishing any reset sequence needs some time The system provides complete procedures to make the power on reset successful For different oscillator types the reset time is different That causes the VDD rise rate and start up time of different oscillator is not fixed RC type oscillator s start up time is very short but the crystal type is longer Under client terminal application users have to take care of the power on reset time for the master terminal requirement The reset timing diagram is as following VDD LVD Detect Level Power vss VDD External Reset External Reset External Reset High Detect Low Detect Watchdog Overflow Ni Watchdog Normal Run i Watchdog Reset Watchdog Stop U System Normal Run System Status system stop External Watchdog Delay Time Reset Delay Reset Delay Time Time 3 1 1 POWER ON RESET POR The power on reset depends on LVD operation for most power up situations The power supplying
125. ected by writing the MODE bits to 100b in USARTn CTRL register The USART allows the user to control a bidirectional synchronous serial communications in master mode The SCLK pin is the output of the USART transmitter clock No clock pulses are sent to the SCLK pin during start bit and stop bit The CPOL bit in USARTn CTRL register allows the user to select the clock polarity and the CPHA bit allows the user to select the phase of the clock During the Idle state preamble and send break the external SCLK clock is not activated In synchronous mode the USART transmitter works exactly like in asynchronous mode But as SCLK is synchronized with TX according to CPOL and CPHA the data on TX is synchronous In synchronous mode the USART receiver works in a different manner compared to the asynchronous mode If Receiver is enabled RXEN 1 the data is sampled on SCLK depending on CPOL and CPHA without any oversampling A setup and a hold time must be respected which depends on the baud rate 1 16 bit time Note gt 1 The SCLK pin works in conjunction with the UTXD pin so the clock is provided only if TXEN 1 in USARTn_CTRL register and a data is being transmitted the data register USART_DR has been written This means that it is not possible to receive a synchronous data without transmitting data gt 2 CPOL bits in USARTn_SYNCCTRL register have to be selected when both the transmitter and the receiver
126. ed in the watchdog counter SONiX TECHNOLOGY CO LTD Page 92 Version 2 0 N j SN32F720 Series N N E x 32 Bit Cortex M0 Micro Controller 1 0 REAL TIME CLOCK RTC 10 1 OVERVIEW The RTC is an independent timer The RTC provides a set of continuously running counters which can be used to provide a clock calendar function with suitable software The counter values can be written to set the current time date of the system 10 2 FEATURES gt Programmable prescale value division factor up to 2 gt 32 bit programmable counter for long term measurement gt RTC clock source could be any of the following EHS XTAL clock divided by 128 ELS gt Reset sources of the RTC Core Prescale value Alarm Counter and Divider Cold boot DPDWAKEUP gt Three dedicated enabled interrupt lines Alarm interrupt generating a software programmable alarm interrupt Seconds interrupt generating a periodic interrupt signal with a programmable period length up to 1 second Overflow interrupt to detect when the internal programmable counter rolls over to zero 10 3 FUNCTIONAL DESCRIPTION 10 3 1 INTRODUCTION RTC core includes a 20 bit preload value RTC SECCNTV Every TR_CLK period the RTC generates an interrupt Second Interrupt if it is enabled RTC IE register The second block is 32 bit programmable counter that can be initialized to the current system time The system time is incr
127. emented at the TR_CLK rate and compared with a programmable date stored in the RTC_ALR register in order to generate an alarm interrupt if enabled in RTC IE register 10 3 2 RESET RTC REGISTERS The RTC_SECCNTV RTC_ALMCNTV RTC_SECCNT and RTC_ALMCNT registers are reset by cold boot or DPDWAKEUP reset 10 3 3 RTC FLAG ASSERTION The RTC Second interrupt flag SECIF is asserted on each RTC Core clock cycle before the update of the RTC Counter The RTC Overflow interrupt flag OVFIF is asserted on the last RTC Core clock cycle before the counter reaches 0 0 The RTC Alarm interrupt flag ALMIF are asserted on the last RTC Core clock cycle before the counter reaches the RTC Alarm counter reload value stored in the Alarm register SONiX TECHNOLOGY CO LTD Page 93 Version 2 0 X SN32F720 Series 32 Bit Cortex M0 Micro Controller 10 3 4 RTC OPERATION The following figure shows the RTC waveform when it is configured with RTC_SECCNTV 3 RTC_ALMCNTV 0x1000 RTC_PCLK V V 0x3 00 X 0 2 0 3 Y 0x0 AJ RTC SECCNT y Y 0 1 Y 0x3 0 0 Kon 0 2 Y 0 0 RTC_SECIF _ cleared SW RTC_ALMCNT X 0x1000 0 1001 0x0 0 1 RTC_ALMIF 2 RTC PCLK
128. er AMENDENT HISTORY Version Date Description 1 0 2013 01 17 First version released 1 1 2013 02 18 11 Fix typing errors 1 2 2013 02 27 1 Add notifications of GPIO settings in low power mode for low pin count package 2 Update Chap 17 Development Tool 3 Modify SysTick register names refer to core_cm0 h provided by ARM 1 3 2013 05 06 1 Update SysTick Timer block diagram 2 Add SYSO ANTIEFT register 3 Update supply current 4 Add Operation Mode Comparison Table 2 0 2013 06 28 1 Fix typing errors SONiX TECHNOLOGY CO LTD Page 2 Version 2 0 y SN32F720 Series N N 32 Bit Cortex M0 Micro Controller Table of Content AMENDENT HISTORY 2 PRODUCT OVERVIEW 12 FEATURES e 12 12 SYSTEM BLOCK DIAGRAM i presta ii 14 13 CLOCK GENERATION BLOCK DIAGRAM 15 14 0 PINASSIGNMENT ee eaaa 16 13 PINDESCRIPTIONS 18 16 PIN CIRCUIT DIAGRAMS 21 4 CENTRAL PROCESSOR UNIT CPU 23 21 pud td apa abre eei be leid tapa avito Mida NE 23 22 SYSTEM TICK TIMER u Zaa saqina
129. er it cannot be assumed that the next received byte will be correct even if there is no Framing Error 0 Framing error status is inactive 1 Framing error status is active PE Parity Error flag When the parity bit of a received character is in the wrong state a parity error occurs USARTn LS register read clears PE bit Time of parity error detection is dependent on FIFOEN bit in USARTn FIFOCTRL register 0 Parity error status is inactive 1 Parity error status is active SONiX TECHNOLOGY CO LTD Page 135 Version 2 0 BN WY SN32F720 Series NS 32 0 Micro Controller The overrun error condition is set as soon as it occurs A USARTn LS register read clears OE bit OE 1 when USART RSR has a new character assembled and the USARTn RB FIFO is full In this case the USARTn RB FIFO will not be overwritten and the character in the USARTn RS register will be lost 0 Overrun error status is inactive 1 Overrun error status is active Receiver Data Ready flag RDR 1 when the USARTn RB FIFO holds an unread character and is cleared when the USARTn RB FIFO is empty 0 USARTn RB FIFO is empty 1 USARTn RB FIFO contains valid data 13 12 11 USART n Modem Status register USARTn MS nz0 1 Address Offset 0x18 This register is a read only register that provides status information on USART input signals Note gt 1 Whenever the DCD bit changes state an interrupt is genera
130. er structure and built in pull up pull down resisters as input mode CT16B1 PWM1 PWM output 1 for CT16B1 URTSO USARTO Request To Send output pin P1 11 Port 1 11 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CLKOUT Clockout pin P2 0 P2 9 Port 2 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode AINO AIN9 ADC channel input 0 9 pins P3 0 Port 3 0 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode UDTRO USARTO Data Terminal Ready output pin SEL1 55 Slave Select pin Page 19 Version 2 0 P3 1 UDSRO SCK1 P3 2 UDCD0 MISO1 P3 3 URI0 MOSI1 P3 4 LXTALIN P3 5 LXTALOUT P3 6 RESET P3 7 XTALIN P3 8 XTALOUT SN32F720 Series 32 Bit Cortex M0 Micro Controller P3 1 Port 3 1 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode UDSRO USARTO Data Set Reagy input pin SCK1 Serial clock pin for SSP1 P3 2 Port 3 2 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode UDCDO USARTO Data Carrier Detect input MISO1 SSP1 Master In Slave Out pin P3 3 Port 3 3 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode URIO USARTO Ring Indicator input pin MOSI1 Master Out
131. eral ADC is enabled not through MODE register 3132 0 0 0 0 0 0 p MODE 11 0 Selects pin x as input or output x O to 11 0 Pn x is configured as input 1 Pn x is configured as output 5 3 3 GPIO Port n Configuration register GPlOn CFG n 0 1 2 3 Address offset 0x08 Reset value Note HW will switch I O Mode directly when Specific function Peripheral ADC is enabled not through GPlOn MODE register CFG11 1 0 ul CFG10 1 0 i CFG9 1 0 SONiX TECHNOLOGY CO LTD Configuration of Pn 11 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 10 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 9 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Page 60 4204 Reseved Rl Version 2 0 SONIX CFG8 1 0 CFG7 1 0 CFG5 1 0 CFG4 1 0 CFG6 1 0 CFG3 1 0 CFG2 1 0 CFG1 1 0 CFGO 1 0 Configuration of Pn 8 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 7 00 Pull up r
132. erved 11 EHS X TAL clock 128 10 5 3 RTC Interrupt Enable register RTC IE Address offset 0x08 31 3 Reserved OVFIE Overflow interrupt enable 0 Disable 1 Enable ALMIE Alarm interrupt enable 0 Disable 1 Enable SECIE Second interrupt enable 0 Disable 1 Enable 10 5 4 RTC Raw Interrupt Status register RTC RIS Address offset 0 0 SU3 Reseved jJ R O OVFIF Overflow interrupt flag This bit is set by HW when ALM ONT overflows ALM CNT counts from OxFFFFFFFF to 0x0 An interrupt is generated if OVFIE 1 0 Overflow not detected 1 32 bit programmable counter overflow occurred SONiX TECHNOLOGY CO LTD Page 96 Version 2 0 SON IX Alarm interrupt flag This bit is set by HW when ALM_CNT ALM_CNTV An interrupt is generated if ALRIE 1 0 Alarm not detected 1 Alarm detected Second interrupt flag This bit is set by HW when SEC CNT SEC ONTV An interrupt is generated if SECIE 1 0 Second flag condition not met 1 Second flag condition met 10 5 5 RTC Interrupt Clear register RTC IC Address offset 0x10 Reseved G R 0 4 1414 1 Clear OVFIF 1 Clear ALMIF 0 W 10 5 6 RTC Second Counter Reload Value register RTC_SECCNTV Address offset 0x14 Reset value 0x8000 _ Bit Descriptic Attribute Reset 3190 Reseved RTC second counter reload value S
133. eset circuit is with a stable current through R1 and R2 For power consumption issue application e g DC power system the current must be considered to whole system power consumption Note Under unstable power condition as brown out reset Zener diode reset circuit and Voltage bias reset circuit can protects system no any error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes reset sequence That makes sure the system work well under unstable power situation 3 1 4 5 EXTERNAL RESET IC Bypass Capacitor 0 1uF The external reset circuit also uses external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different application and system requirement to select suitable reset IC The reset circuit can improve all power variation 3 1 5 SOFTWARE RESET The entire MCU including the core can be reset by software by setting the SYSRESREQ bit in the AIRC Application Interrupt and Reset Control register in spec The software initiated system reset sequence is as follows 1 software reset is initiated by setting the SYSRESREQ bit 2 Aninternal reset is asserted 3 The internal reset is deasserted and the MCU loads from memory the initial stack pointer the initial program counter and the first instruction designated by the program counter and then begins e
134. esistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 6 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 5 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 4 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 3 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 2 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 1 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of 0 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode SN32F720 Series 32 Bit Cortex M0 Micro Controller z 5 3 4 GPIO Port n Interrupt Sense register GPlOn IS n 0 1 2 3 Address offset 0 0 Name Descripti
135. evel These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated 00 Trigger level 0 1 character 01 Trigger level 1 4 characters 10 Trigger level 2 8 characters 11 Trigger level 3 14 characters s3 Reseved 2 TXFIFORST TX FIFO Reset bit 0 No impact on either of USART FIFOs 1 Writing a logic 1 to reset the pointer logic in USART TX FIFO HW shall clear this bit automatically RXFIFORST RX FIFO Reset bit 0 No impact on either of USART FIFOs 1 Writing a logic 1 to reset the pointer logic in USART RX FIFO HW shall clear this bit automatically FIFOEN FIFO enable 0 No effect 1 Enable for both USART Rx and TX FIFOs and USARTn_FIFOCTRL 7 1 access This bit must be set for proper USART operation 13 12 8USART n Line Control register USARTn_LC n 0 1 Address Offset 0x0C This register determines the format of the data character that is to be transmitted or received _ Description Attribute Reset are Reseved SE 0 Disable access to Divisor Latches 1 Enable access to Divisor Latches 217 Control bit Bun Kd Disable break transmission 1 Enable break transmission Output pin USART TXD is forced to logic 0 PS 1 0 Parity Select bits R W 00 Odd parity Number of 1s in the transmitted character and the attached parity bit will be odd 01 Even Parity Number of 1s in the transmitted character and the atta
136. ex M0 Micro Controller The user may program this register with a delay between the last stop bit leaving the TXFIFO and the de assertion of RTS This delay time is in periods of the baud clock Any delay time from 0 to 255 bit times may be programmed 31 8 Reserved 7 0 DLY 7 0 The direction control RTS delay value This register works in conjunction R W with an 8 bit counter 13 12 22 USART n Synchronous Mode Control Register USARTn_SYNCCTRL n 0 1 Address Offset 0x48 This register controls the synchronous mode When this mode is in effect the USART generates or receives a bit clock on the SCLK pin and applies it to transmit and receive shift registers Synchronous mode should not be used with smartcard mode EEN CPHA Clock phase for edge sampling RW 0 Sample on the rising edge of SCLK 1 Sample on the falling edge of SCLK CPOL Clock polarity selection bit RW 0 SCLK idles at Low level 1 SCLK idles at High level O R SONiX TECHNOLOGY LTD Page 141 Version 2 0 SON IX 14 5 14 1 OVERVIEW The 125 bus specification defines 3 wire serial bus having one data clock and one word select signal The basic 125 connection has one master which is always the master and one slave 14 2 FEATURES 125 can operate as either master or slave Capable of handling 8 16 24 32 bit data length Mono and stereo audio data supported 125 and MSB justified data format
137. for the baud rate generation and can be read and written at the user s discretion This prescaler takes the APB clock and generates an output clock according to the specified fractional requirements In most applications the USART samples received data 16 times in each nominal bit time and sends bits that are 16 input clocks wide OVERS bit allows software to control the ratio between the input clock and bit clock This is required for smart card mode and provides an alternative to fractional division for other modes Note If the fractional divider is active DIVADDVAL gt 0 and 0 the value of the USARTn DLL register must 2 3 319 Reserved OVER8 Oversampling value 0 Oversampling by 16 1 Oversampling by 8 Not supported for IrDA mode R W 7 4 MULVAL 3 0 Baud rate pre scaler multiplier value MULVAL 3 0 1 0000 Baud rate pre scaler multiplier value is 1 for HW 0001 Baud rate pre scaler multiplier value is 2 for HW 1111 Baud rate pre scaler multiplier value is 16 for HW pranova Mo NUN baud rate generator will not impact the USART baud rate 13 12 16 USART n Control register USARTn CTRL n 0 1 Address 0x30 In addition to HW flow control Auto CTS and Auto RTS mechanisms this register enables implementation of SW flow control When TXEN 1 the USART transmitter will keep sending data as long as they are available As soon as
138. from the Flash memory as required by the CPU 15 6 PROGRAM ERASE The Flash memory erase operation can be performed at page level To ensure that there is no over programming the Flash programming and erase controller blocks are clocked by IHRC 15 7 EMBEDDED BOOT LOADER The embedded boot loader is used to reprogram the Flash memory using the USARTO serial interface This program is located in the Boot ROM and is programmed by during production SONiX TECHNOLOGY LTD Page 151 Version 2 0 q 7 SONIX 15 8 FLASH MEMORY CONTROLLER FMC The FMC handles the program and erase operations of the Flash memory 15 8 1 CODE SECURITY CS Code Security is a mechanism that allows the user to enable different levels of security in the system so that access to the on chip Flash and use of the ISP can be restricted Important Any Code Security change becomes effective only after the device has gone through a power cycle Writer can Read Erase Program User ROM cso SWD can Read Erase Program User ROM FW can Read Erase Program User ROM EEPROM emulation Writer can Erase Program User ROM SWD can NOT Read Erase Program User ROM CS1 X X FW can Read Erase Program User ROM EEPROM emulation HW checksum can be read other data will be read as 0 0 Writer can NOT Read Erase Program User ROM SWD can NOT Read Erase Program User ROM CS2 0xA5A5 X X X X FW can NOT Read Erase Program
139. g by 16 to increase the tolerance of the receiver to clock deviations In this case the maximum speed is limitedto maximum USARTn_PCLK 16 Sampled values Sampling Clock 5 fe 5 7 16 p 6 16 7 16 M lt T BIT TIME If the USARTn FD register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided USART can operate with or without using the Fractional Divider The desired baud rate can be achieved using several different Fractional Divider settings The following algorithm illustrates one way of finding a set of DLM DLL MULVAL and DIVADDVAL values Such set of parameters yields a baud rate with a relative error of less than 1 196 from the desired one The following example illustrates selecting the DIVADDVAL MULVAL DLM and DLL to generate BR 115200 when USARTn PCLK 12 MHz and Oversampling 16 USARTn PCLK UARTaupRATE m OS M M M Oversampling x 256 x DLM DLL x 1 DIVADDVAL MULVAL 12000000 115200 16 x 256 x DLM DLL x 1 DIVADDVAL MULVAL 256 x DLM DLL x 1 DIVADDVAL MULVAL 6 51 Since the value of MULVAL and DIVADDVAL should comply to the following conditions 1 1 S MULVAL s 15 2 0 S DIVADDVAL s 14 3 DIVADDVAL MULVAL SONiX TECHNOLOGY CO LTD Page 122 Versi
140. ge which is depend on the system executing rate and power level Different system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship System Mini Operating Voltage Vdd V P 9 Normal Operating Area PEPE System Reset Voltage System Rate Fcpu Normally the system operation voltage area is higher than the system reset voltage to VDD and the reset voltage is decided by LVD detect level The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset voltage 3 1 3 3 BROWN OUT RESET IMPROVEMENT How to improve the brown reset condition There are some methods to improve brown out reset as following LVD reset Watchdog reset Reduce the system executing rate External reset circuit Zener diode reset circuit Voltage bias reset circuit External reset IC Note The Zener diode reset circuit Voltage bias reset circuit and External reset IC can completely improve the brown out reset DC low battery and AC slow power down conditions SONiX TECHNOLOGY CO LTD Page 34 Version 2 0 N j SN32F720 Series N E x 32 Bit Cortex M0 Micro Controller LVD reset VDD Power yss Power is below LVD Detect Voltage and System Re
141. gister after changing the prescale value CLKOUTPRE 3 0 Clock out source prescale value 0000 Clock out source 1 0001 Clock out source 2 0010 Clock out source 4 0011 Clock out source 8 0100 Clock out source 16 0101 Clock out source 32 0110 Clock out source 64 0111 Clock out source 128 1000 Clock out source 256 1001 Clock out source 512 Other Reserved 27 Reed 3 R O I2C1PRE 2 0 Em prescale value R W 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 2 Reseved 1 WDTPRE 2 0 aon ber prescale value 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 101 HCLK 32 Other Reserved 19 18 Reserved SONiX TECHNOLOGY CO LTD Page 51 Version 2 0 SONIA 17 16 SYSTICKPRE 1 0 SN32F720 Series 32 Bit Cortex M0 Micro Controller SysTick clock source prescale value 00 HCLK 1 01 HCLK 2 10 HCLK 4 11 8 _15 Reserved RR 125 clock source prescale value I2SPRE 2 0 000 HCLK 1 RAN 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved n R 0 7 2 2 0 12 0 clock source prescale value RAN 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 7 Reserved RR USART1 clock source value USART1PRE 2 0 000 HCLK 1 R W 001 HCLK 2 010 HCLK 4 011 HCLK 8 100
142. in Flash memory can be read write protected against different levels of Code Security CS During a write operation to the Flash memory any attempt to read the Flash memory will stall the bus The read operation will proceed correctly once the write operation has completed This means that code or data fetches cannot be made while a write erase operation is ongoing For write and erase operations on the Flash memory the IHRC will be turn ON by FMC The Flash memory can be programmed and erased using ICP and ISP SONiX TECHNOLOGY CO LTD Page 150 Version 2 0 N NI 7 SN32F720 Series N N E 32 Cortex M0 Micro Controller 15 4 ORGANIZATION Block Name Base Address Size Byte Page 0 0x00000000 0x000001FF 512 Page 1 0x00000200 0x000003FF 512 User ROM Page 15 0x00001E00 0x00001FFF 512 Page 0 Ox1FFF0000 0x1FFFO1FF 512 Page 1 Ox1FFF0200 0x1FFFO3FF 512 Boot Loader Page 7 Ox1FFFOEOO Ox1FFFOFFF 512 15 5 READ The embedded Flash module can be addressed directly as a common memory space Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to interface with the CPU The main task of the read interface is to generate the control signals to read
143. interfering with other devices on the same I2C bus gt Standard I2C compliant bus interfaces may be configured as Master or Slave gt 12 Master features Clock generation W Start and Stop generation gt 12C Slave features Programmable I2C Address detection W Optional recognition of up to four distinct slave addresses Stop bit detection gt Supports different communication speeds Standard Speed up to 100KHz Fast Speed up to 400 KHz gt Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus gt Programmable clock allows adjustment of 12 transfer rates gt Data transfer is bidirectional between masters and slaves gt Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer SONiX TECHNOLOGY CO LTD Page 108 Version 2 0 Y N N 9 Y SN32F720 Series px N E 32 Cortex M0 Micro Controller gt Monitor mode allows observing all 12 traffic regardless of slave address gt I2C bus can be used for test and diagnostic purposes gt Generation and detection of 7 bit 10 bit addressing and General Call 12 3 PIN DESCRIPTION Description SCLn I2C Serial clock Output with Open drain Input depends on GPlOn CFG SDAn I2C Serial data Output with Open drain Input depends on GPl
144. interrupts A Timer PWM interrupt is sent to the interrupt controller if the corresponding bit in the CT16Bn IE register is set lame Interrupt flag for capture channel 0 0 No interrupt on CAPO 1 Interrupt requirements met on CAPO Interrupt flag for match channel 3 0 No interrupt on match channel 3 1 Interrupt requirements met on match channel 3 Interrupt flag for match channel 1 0 No interrupt on match channel 1 1 Interrupt requirements met on match channel 1 Interrupt flag for match channel 0 0 No interrupt on match channel 0 1 Interrupt requirements met on match channel 0 7 7 11 CT16Bn Timer Interrupt Clear register CT16Bn IC nz0 1 Address Offset 0x3C MR2IF Interrupt flag for match channel 2 0 No interrupt on match channel 2 1 Interrupt requirements met on match channel 2 Reserved 1 Clear CAPOIF bit 1 Clear MR3IF bit 0 No effect 1 Clear MR2IF bit 0 No effect 1 Clear MR1IF bit 0 No effect 1 Clear MROIF bit SONiX TECHNOLOGY CO LTD Page 79 Version 2 0 N M 2F72 1 SONIX 8 32 WITH FUNCTION 8 1 OVERVIEW Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitio
145. ister when RX DN 1 R 0x00 12 8 5 2 n Slave Address 0 register 2 SLVADDRO 0 1 Address Offset 0x10 Only used in slave mode In master mode this register has no effect If this register contains 0x00 the I2C will not acknowledge any address on the bus Register ADRO to ADRS will be cleared to this disabled state on reset BE and Slave address mode 0 7 bit address mode 1 10 bit address mode perse d General call address enable bit 0 Disable 1 Enable general call address 0x0 ADDRI9 0 The 2 slave address ADD 9 0 is valid when ADD MODE 1 ADD 7 1 is valid when ADD MODE 0 12 8 6 12 n Slave Address 1 3 register 12 SLVADDR1 3 nz0 1 Address Offset 0x14 0x18 Ox1C 3110 Reseved Ri ADDRI9 0 The 12 slave address R W 8 0 ADD 9 0 is valid when ADD MODE 1 ADD 7 1 is valid when ADD MODE 0 12 8 7 12 n SCL High Time register I2Cn SCLHT nz0 1 Address Offset 0x20 2 Bit Frequency 2 PCLK I2Cn SCLHT I2Cn SCLLT 308 Reseved oR Q9 SONiX TECHNOLOGY CO LTD Page 115 Version 2 0 SON IX k pedidos 7 0 SCLH 7 0 Count for SCL High Period time SCL High Period Time SCLH 1 12CO_PCLK cycle 12 8 8 12 n SCL Low Time register 2 SCLLT n 0 1 Address Offset 0x24 Bit Name 8 8 Reserved 7 0 SCLL 7 0 Count for SCL Low Period time SCL Low Period Time 6 1 12
146. ith the DLL register determines the baud rate of the USART SONiX TECHNOLOGY CO LTD Page 130 Version 2 0 NONA 13 12 5USART n Interrupt Enable register USARTn IE 0 1 Address Offset 0x04 The DLAB bit in USARTn LC register must be zero in order to access this register Bii Name Description Attribute Reset Stt Reserved _ R O TXERRIE TXERR interrupt enable bit The status of this interrupt can be read from TXERR bit in USARTn LS register 0 Disable 1 Enable Enables the auto baud time out interrupt enable bit 0 Disable 1 Enable ABEOIE End of auto baud interrupt enable bit 0 Disable 1 Enable TEMTIE TEMT interrupt enable bit The status of this interrupt can be read from TEMT bit in USARTn_LS register 0 Disable 1 Enable MSIE Modem Status interrupt enable bit The components of this interrupt can be read from USARTn_MS register 0 Disable 1 Enable RLSIE Receive Line Status RLS interrupt enable bit The status of this interrupt can be read from USARTn LS 4 1 0 Disable 1 Enable THREIE THRE interrupt enable bit The status of this interrupt can be read from THRE bit in USARTn LS register 0 Disable 1 Enable RDAIE RDA interrupt enable bit Enables the Receive Data Available interrupt It also controls the Character Receive Time out interrupt 0 Disable 1 Enable 13 12 6 USART n Interrupt Identification register USARTn n 0 1 Address Offset 0x08
147. ived SONiX TECHNOLOGY CO LTD Page 113 Version 2 0 N N 9 Y SN32F720 Series D D 32 Cortex M0 Micro Controller gt The General Call address has been received while the General Call bit GC in the ADR register is set gt data byte has been received while the 2 is in the master receiver mode gt A data byte has been received while the 2 is in the addressed slave receiver mode HW will clear after issuing ACK automatically Assert NACK HIGH level to SDA flag 0 No function 1 An NACK will be returned during the acknowledge clock pulse on SCLn when gt A data byte has been received while the 2 is in the master receiver mode HW will clear after issuing NACK automatically 0 Reserved 12 8 2 2 n Status register I2Cn STAT nz0 1 Address Offset 0x04 Check this register when I2C interrupt occurs and all status will be cleared automatically by writing 12 CTRL or 2 TXDATA register While I2CIF 1 the low period of the serial clock on the SCL line is stretched and the serial transfer is suspended When SCL is HIGH it is unaffected by the state of I2CIF Name Description Attribute Reset 3146 Reseved o I2CIF I2C Interrupt flag 0 I2C status doesn t change 1 Read 2C status changes Write Clear this flag 14 10 Reserved TIMEOUT Time out status 0 No Timeout 1 Timeout LOST ARB Lost arbitration 0 Not lost arbitration 1 Lost arbitration 7
148. l 12 MHz RC oscillator 1 Enable internal 12 MHz RC oscillator 3 3 2 PLL control register SYSO PLLCTRL Address Offset 0x04 3 Reseved Note PLLEN bit be cleared if the PLL is selected as system clock or is selected to become system clock Bi Bit Name 0 Disable 1 Enable System PLL clock source 00 IHRC 12 MHz oscillator 01 EHS X TAL 10 MHz 25 MHz Other Reserved Front divider value The division value F is the programmed 2 0 1 1 F 2 Post divider value P PSEL 2 0 2 000 010 Reserved 011 P 6 SONiX TECHNOLOGY CO LTD Page 44 Version 2 0 SONA 100 8 101 10 110 12 111 14 To select the appropriate values for it is recommended to follow these constraints 1 10MHzs lt 25MHz 2 150MHz lt lt 330MHz 3 2 M x31 4 F 1 or2 5 P 6 8 10 12 or 14 duty 50 2 5 6 20MHz 30MHz 40MHz 50MHz 24MHz 36MHz 48MHz 32MHz 22MHz 24MHz 50MHz with jitter lt 500 ps Felkin 10MHz 12MHz 16MHz 20MHz 22MHz 24MHz 25MHz 30MHz 32MHz 36MHz 40MHz 44MHz 48MHz 50MHz 3 3 2 1 RECOMMEND FREQUENCY SETTING Fvco F M Feikour P 3 3 3 Clock Source Status register 5 50 CSST Address Offset 0x08 Reserved PLLRDY PLL clock ready flag 0 PLL unlocked 1 PLL locked
149. l reset function is controlled by External RESET pin control SYS0 EXRSTCTRL register Default value is 1 which means external reset function is enabled External reset pin is Schmitt Trigger structure and low level active The system is running when reset pin is high level voltage input The reset pin receives the low voltage and the system is reset The external reset operation actives in power on and normal running mode During system power up the external reset pin must be high level input or the system keeps in reset status External reset sequence is as following External reset only external reset pin enable System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock SONiX TECHNOLOGY CO LTD Page 35 Version 2 0 m N j SN32F720 Series S N N 32 Cortex M0 Micro Controller Program executing Power on sequence is finished and program executes from Boot loader The external reset can reset the system during power on duration and good external reset circuit can protect the system to avoid working at unusual power condition e g brown out reset in AC power application 3 1 4 1 SIMPLY RC RESET CIRCUIT 100 ohm This is the basic rese
150. leared by HW ea AUTORESTART Restart mode 0 restart 1 Restart in case of timeout counter restarts at next USART falling edge BEBE Auto baud mode select bit 0 Mode 0 1 Mode 1 START This bit is automatically cleared after auto baud completion 0 Auto baud stop auto baud is not running 1 Auto baud start auto baud is running Auto baud run bit This bit is automatically cleared by HW after auto baud completion 13 12 14 USART n IrDA Control register USARTn IRDACTRL nz0 1 Address Offset 0x24 This register enables and configures the IrDA mode The value of this register should not be changed while transmitting or receiving data or data loss or corruption may occur Bil Name 31 6 Reserved PULSEDIV 2 0 Configures the pulse width when FIXPULSEEN 1 000 2x TPCLK 001 4x TPCLK 010 8x TPCLK 011 16 x TPCLK 100 32 x TPCLK 101 64 x TPCLK 110 128 x TPCLK 111 256 x TPCLK FIXPULSEEN IrDA fixed pulse width mode enable 0 Disable Pulse width 3 Oversampling x baud rate 1 Enable Pulse width is set by PULSEDIV bits SONiX TECHNOLOGY CO LTD Page 137 Version 2 0 N j 1 SONIX IRDAINV Serial input inverter 0 The serial input is not inverted 1 The serial input is inverted This has no effect on the serial output 0 Reserved 13 12 15 USART n Fractional Divider register USARTn FD n 0 1 Address Offset 0x28 This register controls the clock prescaler
151. lready then the PWM signal will be cleared on the next start of the next PWM cycle 4 Ifa match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously CT16Bn_MR2 100 PWM1 CT16Bn_MR1 25 En CT16Bn 0 60 CT16Bn TC 0 25 60 100 TC resets Note When match outputs are selected to perform as PWM outputs the timer reset MRnRST and timer stop MRnSTOP bits in 16 MCTRL register must be set to zero except for the match register setting the PWM cycle length For this register set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register SONiX TECHNOLOGY CO LTD Page 74 Version 2 0 NDS 7 1 SONIX eie 77 CT16Bn REGISTERS Base Address 0x4000 0000 CT16BO 0x4000 2000 CT16B1 7 7 1 CT16Bn Timer Control register CT16Bn_TMRCTRL n 0 1 Address Offset 0x00 Note CEN bit shall be set at last 8 ribute Counter Reset R W 0 Disable counter reset 1 Timer Counter is synchronously reset on
152. nable register 96 10 34 RTC Raw Interrupt Status register 96 10 5 5 RTC Interr pt Clear register RTG IG pM n Me 97 10 5 6 Second Counter Reload Value register RTC_SECCNT V 97 10 5 7 Second Count register RTC_SECCNT 97 10 5 8 RTC Alarm Counter Reload Value register RTC_ALMCNTV 97 105 9 Alarm Count register RTC_ALMCNT 98 1 SPI SSP 99 OVERVIEW MENS Mt sar tes patel eae up MED 99 99 113 rama ree eee vM MEE 100 SONiX TECHNOLOGY CO LTD Page 7 Version 2 0 IN 7 SN32F720 Series N N H x 32 Bit Cortex M0 Micro Controller INTERFACE DESCRIPTION ban God 101 101 RE C n 102 11 4 3 COMMUNICATION UNA DUD ad ORE 102 11 4 3 1 SINGLE FRAM E T 102 11432
153. nagement register ADC_ADM Address Offset 0x00 Reserved anaa a ae high reference voltage source select bit e 0 Internal VDD P2 0 is GPIO or AINO pin pae oe 1 Enable external reference voltage from P2 0 0 Disable 1 Enable ADC Clock source divider ADOS 000 PCLK 1 001 ADC_PCLK 2 010 ADC PCLK 4 011 PCLK 8 101 PCLK 16 110 PCLK 32 Other Reversed ADC resolution control bit R W 0 8 bit ADC 1 12 bit ADC ADC start control bit RW 0 ADC converting stops 1 Start to execute ADC converting ADS is cleared when the end of ADC converting automatically ADC status bit indicates ADC processing status immediately and is R W cleared when ADS 1 0 ADC progressing 1 End of converting and reset ADS bit ADC global channel select bit os g 0 Disable AIN channel 1 Enable AIN channel CHS 3 0 ADC input channels select bit RW 0000 AINO 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AING 0111 AIN7 1000 AIN8 1001 AIN9 Other Reversed Note If ADENB 1 users should set P2 n AINn as input mode without pull up System doesn t set automatically If P2CON n is set the P2 n AINn s digital I O function including pull up is isolated 6 5 2 ADC Data register ADC_ADB Address Offset 0x04 ADB is ADC data buffer to store AD converter result SONiX TECHNOLOGY CO LTD Page 68 Version 2 0 N j SN32F720 Series
154. nd the value returned is always 0x0 gt 2 HW will replace GPIO with CLKOUT function directly if CLKOUTSEL is Not 0 a CLKOUTSEL 2 0 Clock output source 000 Disable 001 ILRC clock 010 ELS clock 100 HCLK 101 IHRC clock 110 EHS clock 111 PLL clock output 27 25 Enables clock for WDT 0 Disable 1 Enable oe Enables clock for RTC 0 Disable 1 Enable bd a Enables clock for 125 0 Disable 1 Enable pese TE clock for 2 0 Disable x Enable Enables clock for I2C1 0 Disable 1 Enable 1938 Reseved Kawasan clock for USART1 0 Disable 1 Enable clock for USARTO Disable Reseved Kak Enables clock for SSP1 0 Disable 1 Enable s clock for SSP0 Disable eae Enables clock for ADC 0 Disable 1 Enable Reserved SONiX TECHNOLOGY CO LTD Page 49 Version 2 0 N N 9 Y SN32F720 Series D 32 Cortex M0 Micro Controller CT32B1CLKEN Enables clock for CT32B1 0 Disable 1 Enable Kil ieee clock for CT32B0 0 Disable 1 Enable Enables clock for CT16B1 0 Disable 1 Enable CT16BOCLKEN clock for CT16B0 0 Disable 1 Enable _54 Reserved GPIOCLKEN s clock for GPIO 0 Disable 1 Enable _20 Reserved 3 4 2 Clock Prescale register 0 5 51 Address Offset 0x04 Note Must reset the corresponding
155. ndition The auto baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto baud Control Register Given the status of USARTn_II 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The USARTn register must be read in order to clear the interrupt prior to exiting the Interrupt service routine Tn Il Overrun error OE Parity error PE Read USARTn_LS Highest Framing error FE or Break interrupt register Read USARTn_RB RDA 0100 RX data in FIFO reached trigger level FCRO 1 register or USART FIFO drops below trigger level Read 11 register THRE if source of interrupt or THRE 0010 Write THR register 0000 Lowest CTS DSR RI or DCD MSR Read Read USARTR II register TEMT 1110 qu TEMT if source of interrupt or Write THR register Minimum of one character in the RX FIFO and no character input or removed during a time period Read USARTn RB 1100 gnd depending on how many characters are in FIFO and register what the trigger level is set at 3 5 to 4 5 character times SONiX TECHNOLOGY CO LTD Page 132 Version 2 0 N SN32F720 Series Q N N 32 Bit Cortex M0 Micro Controller 13 12 7 USART n FIFO Control register USARTn_FIFOCTRL n 0 1 Address Offset 0x08 This register controls the operation of the USART RX and TX FIFOs _ Reserved RXTL 1 0 RX Trigger L
156. ne of reset trigger sources Y Pull High WAKEUP pin actives E DPDEN EI 3 lt 3 WFI instruction Sleep Run Deep power down gt mode mode Wake up condition Interrupt Wake up condition GPIO Wakeup Enter mode condition RTC interrupt 1 DSLEEPEN 1 2 WFI instruction Reset condition One of reset trigger sources actives Y Deep sleep mode SONiX TECHNOLOGY CO LTD Page 56 Version 2 0 NONA heer 4 6 OPERATION MODE COMPARSION TABLE ILRC EHS By EHSEN By EHSEN ELS ELSEN ELSEN By PLLEN ERE NE By IHRCEN By IHRCEN 100 RAM Maman Maman Peripherals By Enable bit of each By Enable bit of each Disable HCLK peripherals peripherals RTCEN By By Wakeup Source N A All interrupts Wakeup interrupt DPDWAKEUP pin RESET pin RTC interrupt kkk RTCENB RTC_CLKS ILRC ELS 0 x X x 1 ELS EE SONiX TECHNOLOGY CO LTD Page 57 Version 2 0 WY SN32F720 Seri Q N N E x 32 Bit Cortex M0 4 7 PMU REGISTERS Base Address 0x4003 2000 4 7 1 Backup registers 0 to 15 15 Address Offset 0x0 0x04 0x08 OxOC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 Ox2C 0x30 0x34 0x38 Ox3C The backup registers retain data through the
157. neral purpose registers for data operations The Stack Pointer SP In Thread mode the CONTROL register indicates the stack pointer to use SP R13 Main Stack Pointer MSP or Process Stack Pointer PSP On reset the processor loads the MSP with the value from address 0x00000000 LR R14 The Link Register LR It stores the return information for subroutines function calls and exceptions PC R15 The Program Counter PC It contains the current program address On reset the processor loads the PC with the value of the reset vector at address 0x00000004 The Program Status Register PSR combines Application Program Status Register APSR Interrupt Program Status Register IPSR Execution Program Status Register EPSR These registers are mutually exclusive bit fields in the 32 bit PSR 131 30 29 2827 252423 i PRIMASK The PRIMASK register prevents activation of all exceptions with configurable priority CONTROL The CONTROL register controls the stack used when the processor is in Thread mode SONiX TECHNOLOGY CO LTD Page 31 Version 2 0 N j SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller 3 SYSTEM CONTROL 3 1 RESET A system reset is generated when one of the following events occurs A low level on the RST pin external reset Power on reset POR reset LVD reset Watchdog Timer reset WDT reset Software reset SW reset DPDWAKEUP reset when exiting Deep power down mod
158. ning of a Flash operation 4 3 Reserved Programming error flag 0 Read error Write Clear this flag 1 Set by HW when the address to be programmed contains a value different from OXFFFFFFFF before programming 1 Reserved Busy flag 0 Flash operation is not busy 1 Flash operation is in progress This is set on the beginning of a Flash operation clear EOP bit at the same time and reset when the operation finishes or when an error occurs by HW 15 10 2Flash Control register FLASH CTRL Address offset 0x08 93817 Reseved RR Start Erase operation 1 Triggers an ERASE operation when set This bit is set only SW reset when the BUSY bit resets PER bit shall also be 1 when this bit _52 Reserved L ss This bit is set only by SW and reset when the BUSY bit resets Flash Programming chosen This bit is set only by SW and reset when the BUSY bit resets 15 10 3 Flash Data register FLASH DATA Address offset 0 0 For Page Program operations this should be updated by SW to indicate the data to be programmed _310 DATA 31 0 Datatobe programme RW SONiX TECHNOLOGY CO LTD Page 154 Version 2 0 SON IX 15 10 4 Address register FLASH ADDR Address offset 0x10 The Flash address to be erased or programmed should be updated by SW and the PG bit or PER bit shall be set before filling in the Flash add
159. ns optionally generating an interrupt In PWM mode up to three match registers can be used to provide a single edge controlled PWM output on the match output pins 8 2 FEATURES gt Two 32 bit counter timers gt Counter or timer operation gt Two 32 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt gt timer value may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge gt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation gt Upto four PWM outputs corresponding to match registers with the following capabilities Set LOW match Set HIGH on match Toggle on match Do nothing on match gt For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs 8 3 PIN DESCRIPTION lt iption 2 Con ration CT32Bn CAPO Capture channel input 0 Depends on GPlOn CFG pO CT32Bn PWMx O Output channel x of Match PWM output SONiX TECHNOLOGY CO LTD Page 80 Version 2
160. og timeout will cause a chip reset Watchdog reset mode Watchdog counter underflow will reset the MCU and will clear the WDINT flag 1 Watchdog timeout will cause an interrupt Watchdog interrupt mode Watchdog enable 0 Disable 1 Enable When enable the watchdog the WDT_TC value is loaded in the watchdog counter 9 3 2 Watchdog Clock Source register WDT_CLKSOURCE Address Offset 0x04 Nan e CLKSEL 1 0 Selected Watchdog clock source 00 IHRC oscillator 01 HCLK 10 ILRC oscillator 11 ELS X TAL 9 3 3 Watchdog Timer Constant register WDT TC Address Offset 0x08 The register determines the time out value Every time a feed sequence occurs the WDT content is reloaded in to the Watchdog timer It s an 8 bit counter Thus the time out interval is Twpr x 128 x 1 Twpr x 128 x 256 Watchdog overflow time 0 02us x 1 x 128 x 1 0 0625ms x 32 x 128 x 256 2 56us 65536ms 31 8 Reserved 7 0 TC 7 0 Watchdog timer constant reload value TC 7 0 1 0000 0000 Timer constant 1 0000 0001 Timer constant 2 1111 1110 Timer constant 255 1111 1111 Timer constant 256 SONiX TECHNOLOGY CO LTD Page 91 Version 2 0 N WY SN32F720 Series SO N X 32 Bit Cortex M0 Micro Controller 9 3 4 Watchdog Feed register WDT_FEED Address Offset 0 0 FV 15 0 Feed value Read as 0x0 W The watchdog is fed and the value is reload
161. ol and Status register SYSTICK CTRL Address 0 000 E010 Refer to Cortex MO Spec 31 17 Reserved This flag is set when the System Tick counter counts down to 0 and is cleared by reading this register R o EDE E 15 3 Reseved R 0 CLKSOURCE Selects the SysTick timer clock source 1 0 reference clock 1 system clock Fixed TICKINT System Tick interrupt enable R W 0 Disable the System Tick interrupt 1 Enable the System Tick interrupt the interrupt is generated when the System Tick counter counts down to 0 0 Disable 1 Enable 2 2 3 2 System Tick Timer Reload value register SYSTICK_LOAD Address 0 000 E014 Refer to Cortex MO Spec The RELOAD register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero This register is set by software as part of timer initialization The SYST_CALIB register may be read and used as the value for RELOAD if the CPU or external clock is running at the frequency intended for use with the SYST_CALIB value The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the system clock set to 50 MHz The SysTick clock system clock 50 MHz RELOAD system tick clock frequency x 10 ms 1 50 MHz x 10 ms 1 0x0007A11F Reseved ar _ _ Bit 230 RELOAD Value to load into the SYST_CVR when the counter is enabled and when Ox5F7F9B it reaches 0 SONiX TECHNOLOGY CO
162. on 2 0 N SN j SN32F720 Series S NS 32 Bit Cortex M0 Micro Controller Thus the suggested UART settings would be DLM 0 DLL 4 DIVADDVAL 5 and MULVAL 8 The baud rate generated is 115384 and has a relative error of 0 1696 from the originally specified 115200 13 7 MODEM CONTROL MC If Auto RTS mode is enabled the USART s receiver FIFO hardware controls the URTS output of the USART If the auto CTS mode is enabled the USART s transmitter will only start sending if the UCTS pin is low 13 7 1 AUTO RTS The Auto RTS function is enabled by setting the RTSEN bit Auto RTS data flow control originates in the USARTn RB module and is linked to the programmed receiver FIFO trigger level If auto RTS is enabled the data flow is controlled as follows When the receiver FIFO level reaches the programmed trigger level URTS is deasserted to a high value It is possible that the sending USART sends an additional byte after the trigger level is reached assuming the sending USART has another byte to send because it might not recognize the deassertion of URTS until after it has begun sending the additional byte URTS is automatically reasserted to a low value once the receiver FIFO has reached the previous trigger level The reassertion of URTS signals the sending USART to continue transmitting data If Auto RTS mode is disabled the RTSEN bit controls the URTS output of the USART If Auto RTS mode is enabled hardware controls
163. on Attribute Reset 31 12 Reseved R 0o j Selects interrupt on pin x as level or edge sensitive x 0 to 11 0 Interrupt on Pn x is configured as edge sensitive 1 Interrupt on Pn x is configured as event sensitive 5 3 5 GPIO Port n Interrupt Both edge Sense register GPlOn IBS nz0 1 2 3 Address offset 0x10 Bit Name Description ttribute Reset 3112 Reserved Rl Version 2 0 IBS 11 0 Selects interrupt on Pn x to be triggered on both edges x 0 to 11 0 Interrupt on Pn x is controlled through register GPIOn_IEV SONiX TECHNOLOGY LTD Page 61 C N N Y SN32F720 Series D D E 32 Bit Cortex M0 Micro Controller 1 Beth edges on Pn x trigger an interrupt 1 5 3 6 GPIO Port n Interrupt Event register GPlOn IEV nz0 1 2 3 Address offset 0x14 3132 Reserved Rl IEV 11 0 Selects interrupt on pin x to be triggered rising or falling edges x 0 to 11 0 Depending on setting in register GPlOn IS Rising edges or HIGH level on Pn x trigger an interrupt 1 Depending on setting in register GPlOn IS Falling edges or LOW level on Pn x trigger an interrupt 5 3 7 GPIO Port n Interrupt Enable register GPlOn IE nz0 1 2 3 Address offset 0x18 Bits set to HIGH in the IE register allow the corresponding pins to trigger their individual interrupts Clearing a bit disables interrupt triggering on that pin 31 12 Reserved IE 11 0 Selects in
164. on of System Control Registers Software interrupt generation V v v v v v 2 3 1 INTERRUPT AND EXCEPTION VECTORS Ex n No Priority Function Description 04 2 a 3 2 2 Handler 1 interrupt 7 0x0000 0008 3 1 Handler All class of fault 77 7 00000006 4 10 Reserved Reserved Reserved i _ 1243 EE NN _Settable SVCCall 7 Ox00000020 Reserved Reserved o Setable PendSV 1 1 11 1 0000008 15 Setable 1 1 0 0000003 16 Settable IRQOWAKEIRQ Wakeup interrupt 77 0 00000040 17 QSetabe IRQ 0 0000 0044 18 Setabe IRQ 0x00000048 19 X Settable IRQ3 Ox0000004C 20 00000 21 IRQS 00000054 22 6 0000008 23 Setabe 900005 24 IRQ8 0 0000060 25 IRQS j 0x00000064 26 1 0x0000 0068 28 Setabe IRQ12 050000 0070 _ 29 IRQ13 SSPOIRO SSPO 0x0000 0074 S0 IRQ14 SSP1IRQ_ SSP 1 1 1 1 0x00000078 31 Settable IRQ15 IPCORQ 120 1 1 0 0000007 392 Settable IRQ16 CTI6BOIRO 160 1 0 0000 0080 83 Setable IRQ17 CT16B1IRQ 0 0000 0084 34 Setable IRQ18 CT32B0IRQ CT32B0 1 1 1 0x00000088 35 Setable IRQ19 CT32B1IRQ
165. peripherals that are not required for the application Selected peripherals have their own clock divider for power control Note 1 The debug mode is not supported in Deep sleep and Deep Power down mode 2 The pins which are not pin out shall be set correctly to decrease power consumption in low power modes Strongly recommended to set these pins as input pull up 4 3 1 SLEEP MODE In Sleep mode the system clock to the ARM Cortex MO core is stopped and execution of instructions is suspended Peripheral functions if selected to be clocked in SYS1 AHBCLKEN register continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses The power state of the analog blocks EHS ELS X TAL PLL Flash LVD ADC is determined by the SONiX TECHNOLOGY CO LTD Page 54 Version 2 0 N N M SN32F720 Series O NN 0 x 32 Bit Cortex M0 Micro Controller enable bit of all blocks The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Wake up the chip from Sleep mode by an interrupt occurs The RESET pin has keep functionality in Sleep mode The Sleep mode is entered by using the following steps 1 Write 1 to SLEEPEN bit in PMU CTRL register 2 Execut
166. ption of the DPDWAKEUP pin DPDWAKEUP pin must be pulled HIGH externally to enter Deep power down mode and pulled LOW to exit Deep power down mode The processor state and registers peripheral registers and internal SRAM values are not retained However the chip can retain data in four BACKUP registers Wakes up the chip from Deep power down mode by pulling the DPDWAKEUP pin LOW Turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset will be triggered and the chip re boots The RESET pin has no functionality in Deep power down mode SONiX TECHNOLOGY CO LTD Page 55 Version 2 0 N 7 SN32F720 Series N 32 Bit Cortex M0 Micro Controller 4 3 31 Entering Deep power down mode Follow these steps to enter Deep power down mode from Normal mode 1 Pull the DPDWAKEUP pin externally HIGH Strongly recommended to set output high first and then set as input pull up to reduce pull up time Optional Save data to be retained during Deep power down to the DATA bits in Backup registers Write 1 to DPDEN bit in PMU CTRL register to enable Deep power down mode Time spent between step 1 and step 5 shall longer than 20 us Execute ARM Cortex MO WFI instruction After step 5 the PMU turns off the on chip voltage regulator and waits for a wake up signal from the DPDWAKEUP 4 3 3 2 Exiting Deep power down mode Follow these steps to wake up the chip f
167. r can t be clear by program The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and return to normal mode after reset sequence This method also can improve brown out reset condition and make sure the system to return normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal range Reduce the system executing rate If the system rate is fast and the dead band exists to reduce the system executing rate can improve the dead band The lower system rate is with lower minimum operating voltage Select the power voltage that s no dead band issue and find out the mapping system rate Adjust the system rate to the value and the system exits the dead band issue This way needs to modify whole program timing to fit the application requirement External reset circuit The external reset methods also can improve brown out reset and is the complete solution There are three external reset circuits to improve brown out reset including Zener diode reset circuit Voltage bias reset circuit and External reset IC These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead band The external reset information is described in the next section 3 1 4 EXTERNAL RESET Externa
168. registers is implementation defined and corresponds to the number of implemented interrupts PRI_ 4 n 3 Each priority field holds a priority value 0 192 The lower the value the E greater the priority of the corresponding interrupt The processor implements only bits 31 30 of each field bits 29 24 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register PRI 4 n42 Each priority field holds a priority value 0 192 The lower the value the E greater the priority of the corresponding interrupt The processor implements only bits 23 22 of each field bits 21 16 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register PRI 4 n 1 Each priority field holds a priority value 0 192 The lower the value the greater the priority of the corresponding interrupt The processor implements only bits 15 14 of each field bits 13 8 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register PRI 4 n Each priority field holds a priority value 0 192 The lower the value the greater the priority of the corresponding interrupt The processor implements only bits 7 6 of each field bits 5 0 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register 2 4 APPLICATION INTERRUPT AND RESET CONTROL AIRC Address OxE000 EDOC Refer to Co
169. ress FAR 81 0 Flash Address Choose the Flash addresse to erase when Page Erase is selected or to program when Page Program is selected Note Write access to this register is blocked when the BUSY bit in the FLASH STATUS register is set SONiX TECHNOLOGY CO LTD Page 155 Version 2 0 q Aa 7 2 72 1 So s X boue yeu t 16 sEniAL wiRE DEBUG SWD 16 1 OVERVIEW SWD functions are integrated into the ARM Cortex M0 The ARM Cortex M0 is configured to support up to four breakpoints and two watch points 16 2 FEATURES Supports ARM Serial Wire Debug SWD mode Direct debug access to all memories registers and peripherals No target resources are required for the debugging session Up to four breakpoints Up to two data watch points that can also be used as triggers V v v v v 16 3 PIN DESCRIPTION swak I SWDIO Serial Wire Data Input Output pin in SWD mode E 16 4 DEBUG NOTE 16 4 1 LIMITATIONS Debug mode changes the way in which reduced power modes work internal to the ARM Cortex M0 CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be higher than during normal operation in an application During a debugging session the SysTick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected 16 4 2 DEBUG RECOVERY User code may disable SWD fun
170. rom Deep power down mode 1 DPDWAKEUP pin transition from HIGH to LOW The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR Trigger point a system reset will be triggered and the chip reboots All registers except the to 15 will be reset 2 Once the chip has rebooted read DPDEN bit in PMU CTRL register to verify that the reset was caused by a wake up event from Deep power down and was not a cold reset Clear the DPDEN bit in PMU CTRL register Optional Read the stored data in the backup registers Setup the PMU for the next Deep power down cycle Qv d co 4 4 WAKEUP INTERRUPT System will exit Deep sleep mode when GPIO indicates a WAKEUP interrupt to the ARM core The port pins 0 0 to P0 11 are served as wakeup pins The user must program the registers for each pin to set the appropriate edge polarity for the corresponding wakeup event Only edge sensitive is supported to wakeup MCU Furthermore the interrupts corresponding to each input must be enabled in the NVIC Interrupts 0 in the NVIC correspond to 12 GPIO pins 4 5 STATE MACHINE OF PMU gt Reset lt Wake up condition Pulling the DPDWAKEUP pin LOW Enter mode condition iG 1 SLEEPEN 1 Enter mode condition Reset condition 2 WFI instruction 1 Pull High WAKEUP pin O
171. rrupt sources High current source driver 20 mA Programmable WatchDog Timer WDT Programmable watchdog frequency with watchdog clock source and divider System tick timer 24 bit timer The system tick timer clock is fixed to the frequency of the system clock The SysTick timer is intended to generate a fixed 10 ms interrupt Real Time Clock RTC LVD with separate thresholds Reset 1 65V for Vcore 1 8V 2 0 2 4 2 7V for VDD Interrupt 2 0 2 7 3 0V for VDD Fepy Instruction cycle Fceu Fsyscik 1 F svscuk 2 F 4 Operating modes SONiX TECHNOLOGY CO LTD Normal Sleep Deep sleep and Deep power down Page 12 Timer Two 16 bit and two 32 bit general purpose timers with a total of four capture inputs and 13PWMs Working voltage 1 8V 3 6V ADC 10 channel 12 bit SAR ADC Interface Two 2 controllers supporting I2C bus specification with multiple address recognition and monitor mode Two USART controllers with fractional baud rate generation and EIA 485 support Two SPI controllers with SSP features and multi protocol capabilities 125 Function with mono and stereo audio data supported MSB justified data format supported and can operate as either master or slave System clocks External high clock Crystal type 10MHz 25MHz External low clock Crystal type 32 768 KHz Internal high clock RC type 12 MHz Internal low clock RC type 16 KHz PLL
172. rsion 2 0 32 Cortex M0 Micro Controller 21 3 MARKING EXAMPLE Name ROM Type Device Package Temperature Material SN32F727FG Flash memory 727 LQFP 40 C 85 Green Package SN32F727W Flash memory 727 Wafer 40 85 SN32F727H Flash memory 727 Dice 40 C 85 SN32F726JG Flash memory 727 QFN 40 C 85 Green Package 21 4 DATECODE SYSTEM XX X X XXXXX Internal Use Day Month 1 January 2 February 9 September A October B November C December 03 2003 04 2004 05 2005 06 2006 Year SONiX TECHNOLOGY LTD Page 166 Version 2 0 SON IX SN32F720 Series 32 Bit Cortex M0 Micro Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and
173. rtex MO Spec The entire MCU including the core can be reset by SW by setting the SYSRESREQ bit in the AIRC register in Cortex MO spec Note To write to this register user must write to the VECTKEY field at the same time otherwise the processor ignores the write VECTKEY Register key NM Read as unknown Write 0 05 to VECTKEY otherwise the write is ignored ENDIANESS Data endianness implemented 0 Little endian 1 Big endian 1 amp 3 Reserved SYSRESETREO System reset request This bit read as 0 0 No effect 1 Requests a system level reset VECTCLRACTIVE Reserved for debug use This bit read as 0 When writing to the register you must write 0 to this bit otherwise behavior is Unpredictable 0 Reserved SONiX TECHNOLOGY CO LTD Page 29 Version 2 0 SONIX 2 5 CODE TABLE Address 2000 Code Security 15 0 Code Security R W OxFFFF CSO 0x5A5A CS1 0xA5A5 CS2 15 1 r l S R 0 0 X Reserved SONiX TECHNOLOGY CO LTD Page 30 Version 2 0 x SON IX 2 6 CORE REGISTER OVERVIEW moan ER R6 General purpose registers High registers R2 StackPointer SP R13 Link Register LR R14 Program Counter PC R15 PSR Program Status Register Interrupt mask register 2 Special registers CONTROL Control Register RO R12 Ge
174. s 0 4001 8000 2 0 0x4005 A000 I2C1 12 8 1 12 n Control register I2Cn CTRL nz0 1 Address Offset 0x00 The I2Cn CTRL registers control setting of bits that controls operation of the I2C interface When STA 1 and the 2 interface is not already in master mode it enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the 2 interface is already in master mode and data has been transmitted or received it transmits a Repeated START condition STA may be set at any time including when the I2C interface is in an addressed slave mode When STO 1 in master mode a STOP condition is transmitted on the 2 bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting STO bit can recover from an error condition In this case no STOP condition is transmitted to the bus The HW behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode If STA and STO are both set then a STOP condition is transmitted on the I2C bus if it the interface is in master mode and transmits a START condition thereafter If the 2 interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus Note 1 I2CEN
175. sabled 1 Interrupt enabled 2 3 2 3 IRQ0 31 Interrupt Set Pending Register NVIC_ISPR Address 0xE000 E200 Refer to Cortex M0 Spec The ISPR forces interrupts into the pending state and shows the interrupts that are pending Note Writing 1 to the ISPR bit corresponding to gt aninterrupt that is pending has no effect adisabled interrupt sets the state of that interrupt to pending SETPENDJ 31 0 Interrupt set pending bits Write 0 No effect 1 Change interrupt state to pending Read 0 Interrupt is not pending 1 Interrupt is pending 2 3 2 4 00 31 Interrupt Clear Pending Register NVIC ICPR Address 0xE000 E280 Refer to Cortex MO Spec The ICPR removes the pending state from interrupts and shows the interrupts that are pending Note Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt 31 Interrupt clear pending bits Write 0 effect 1 Removes pending state of interrupt Read gt 0 Interrupt is not pending 1 Interrupt is i SONiX TECHNOLOGY CO LTD Page 28 Version 2 0 OT N N 9 Y SN32F720 Series D 32 Cortex M0 Micro Controller 2 3 2 5 IRQO 31 Interrupt Priority Register NVIC_IPRn n 0 7 Address 0xE000 E400 0x4 n Refer to Spec The interrupt priority registers provide an 8 bit priority field for each interrupt and each register holds four priority fields This means the number of
176. set System Normal System Status System Stop IPower On Delay Time The LVD low voltage detector is built in SONiX 32 bit MCU to be brown out reset protection When the VDD drops and is below LVD detect voltage the LVD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not SW can monitor the signal by reading a dedicated status register An additional threshold level can be selected to cause a forced reset of the chip The LVD detect level is different by each MCU The LVD voltage level is a point of voltage and not easy to cover all dead band range Using LVD to improve brown out reset is dependent on application requirement and environment If the power variation is very deep violent and trigger the LVD the LVD can be the protection If the power variation can touch the LVD detect level and make system work error the can t be the protection and need to other reset methods More detail LVD information is in the electrical characteristic section Watchdog reset The watchdog timer is a protection to make sure the system executes well Normally the watchdog timer would be clear at one point of program Don t clear the watchdog timer in several addresses The system executes normally and the watchdog won t reset system When the system is under dead band and the execution error the watchdog time
177. sh Control register FLASH_CTRL 154 15 10 3 Flash Data register FLASH_DATAJ DER IE PRO FR UN da 154 15 10 4 Flash Address register FLASH_ADDR 155 16 SERIAL WIRE DEBUG SWD 156 OVERVIEW e E S 156 162 JEBATURBS aguas EE 156 16 3 PINDESCRIPTION siisii an 156 16 4 DEBUGNOTE Q 156 156 16 42 DEBUG RECOVERY xi a uuu aaa ea A EE 156 16 4 5 INTERNAL PULL UP DOWN RESITIORS on SWD PINS 156 17 DEVELOPMENT siesiscscensiasscniesucesuncvonccenssacocentasesasecanteduaceancdencdacesasssentcaassatedencuaticsecenccancse 157 VUE EL CET T R 157 T72 SN32EFE720 STARTER KI T 158 18 ELECTRICAL CHARACTERISTIC 159 18 1 ABSOLUTE MAXIMUM RATING ra 159 18 2 BLE
178. shall be set at last gt 2 HW will assign SCLO SCL1 0 50 pins as output pins with open drain function instead of GPIO automatically and HW will assign SCLO SCL1 SDAO SDAf pins as 20 high sinking current if 12 1 gt 3 ACK and NACK bits can t both be 1 when receiving data gt 4 User has to write 1 to ACK or NACK bit in Master mode to continue next RX process Description Reset EO wass 2 I2C Interface enable bit R W 0 Disable The STO bit is forced to 0 1 Enable I2EN shall not be used to temporarily release the 12C bus since the bus status is lost when I2CEN resets The ACK flag should be used instead 7 I2CMODE I2C mode selection bit AW 0 Standard Fast mode 1 Reserved 6 Reserved START bit RW 0 No START condition or Repeated START condition will be generated 1 Cause the 2 interface to enter master mode and transmit a START or a Repeated START condition Automatically cleared by HW STOP R W 0 Stop condition idle 1 Cause the 12C interface to transmit a STOP condition in master mode or recover from an error condition in slave mode Automatically cleared by HW Assert ACK Low level to SDA flag 0 Master mode gt No function Slave mode Return a NACK after receiving address or data 1 An ACK will be returned during the acknowledge clock pulse on SCLn when gt The address in the Slave Address register has been rece
179. ster USARTn_RS4S5DLYV n O 1 140 13 12 22 USART n Synchronous Mode Control Register USARTn_SYNCCTRL 0 1 141 14 j 142 n D med 142 14222 250 142 143 PINDESCRIPIEION u S u L uuu E 142 144 BLOCK DIAGRAM 143 144 7 PS CLUOR CONTROL 143 144 2 TEN TOC DIAGRAM uu 143 14 5 FUNCTIONAL DESCRIP ta 144 1451 ALS OPERATION 144 14 52 125 FIFO OPERAION canis 146 14 5 2 1 MONO 146 14 5 2 2 146 14 6 DPSREGISTERS EAEE SE 147 1401 IS Control register 123 GTRLJ 147 146 2 PBS Clo krev ister EK A 147 DS Status register I2S_STATUS 148 14 64 125 Interrupt Enable register I2S_IE 148 1400 125 Raw Interrupt Status register I2S_RIS
180. supported 8 word 32 bit FIFO data buffers are provided Generate interrupt requests when buffer levels cross a programmable boundary Controls include reset stop and mute options separately for 125 input and 125 output V Vv Vv V V Vv V 14 3 PIN DESCRIPTION Pin Name Type Description GPIO Configuration IPSBOLK 12S Bit clock Master x I o I2S Bit clock Slave Depends GPIOn_CFG IPSWS O _ 2S Word Select Master x 125 Word Select Slave GPIOn CFG IDSSDA 12STransmitted Serialdata __ 28 Received Serial data DependsonGPIOn CFG O 125 Master clock output __ 128 Master clock input from GPIO Depends on GPIOn_CFG SONiX TECHNOLOGY LTD Page 142 Version 2 0 32 Bit Cortex M0 Micro Controller 14 4 BLOCK DIAGRAM 14 4 1 125 CLCOK CONTROL MCLK SEL I28 MCLKDIV BCLKDIV HCLK 25 PCLK 125 DIV O 14 4 2 125 BLOCK DIAGRAM gt IPSMCLK 25 CTRL I2SWS 8 x 32 bit FIFO DNI _ IPSBCLK Y lt 126 FIFO b SERIAL ENCODER lt j s 125 STATUS gt 12S Interrupt 1258 RIS 125 IE SONiX TECHNOLOGY CO LTD Page 143 Version 2 0 32 Cortex M0 Micro Controller 14 5 FUNCTIONAL DESCRIPTION 14 5 1 125 OPERATION
181. t Cortex M0 Micro Controller 15 8 3 ERASE The Flash memory can be erased page by page or completely Mass Erase 15 8 3 1 PAGE ERASE A page of the Flash memory can be erased using the Page Erase feature of the FMC To erase a page the procedure below should be followed Set the PER bit in the FLASH CTRL register Program the FLASH ADDR register to select a page to erase Set the STRT bit in the FLASH CTRL register Wait for the BUSY bit to be reset Read the erased page and verify 15 8 3 2 MASS ERASE When the Flash memory read protection is changed from protected to unprotected a Mass Erase of the User ROM is performed by HW before reprogramming the read protection option 15 9 READ PROTECTION The read protection is activated by setting the Code Security bytes in Code option When the Flash memory read protection is changed from protected to unprotected a Mass Erase of the User ROM is performed by HW before reprogramming the read protection option SONiX TECHNOLOGY LTD Page 153 Version 2 0 NG WY SN32F720 Series Sv N 32 Bit Cortex M0 Micro Controller 15 10 FMC REGISTERS Base Address 0x4006 2000 15 10 1 Flash Status register FLASH_STATUS Address offset 0x04 Reset value 0x0000 0000 36 Reseved 00008 0 4 End of operation flag 0 Flash operation programming erase is not completed 1 Set by HW when a Flash operation programming erase is completed and is cleared on the begin
182. t I Start transmit SCL P Master terminal transfer 12 5 3 ARBITRATION In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the 2 bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and the 12 block immediately changes from master transmitter to slave receiver The 12C block will continue to output clock pulses on SCL until transmission of the current serial byte is complete Arbitration may also be lost in the master receiver mode Loss of arbitration in this mode can only occur while the 2 block is returning a not acknowledge to the bus Arbitration is lost when another device on the bus pulls this signal low Since this can occur only at the end of a serial byte the 2 block generates no further clock pulses SONiX TECHNOLOGY CO LTD Page 110 Version 2 0 N NI 7 SN32F720 Series N N 32 Cortex M0 Micro Controller 12 6 I2C SLAVE MODES 12 6 1 SLAVE TRANSMITTER MODE ni R SDA Receiving Address R W 1 Transmission Data Terminate by Master SONiX TECHNOLOGY CO LTD Page 111 Version 2 0 N NI j SN32F720 Series N N E 32 Cortex M0 Micro Controller 12 7 MONITOR MODE 12 7 1 INTERRUPT All interrupts will occur as normal when the module is in monitor mode This means that the first interrupt will occur when an address match is detected any
183. t circuit and only includes R1 and C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a power on signal from the timing difference Note The reset circuit is no any protection against unusual power or brown out reset 3 1 4 2 DIODE 8 RC RESET CIRCUIT R1 47K ohm 100 ohm This is the better reset circuit The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal The reset circuit has a simply protection against unusual power The diode offers a power positive path to conduct higher power to VDD It is can make reset pin voltage level to synchronize with VDD voltage The structure can improve slight brown out reset condition SONiX TECHNOLOGY CO LTD Page 36 Version 2 0 N N 7 SN32F720 Series S NS 32 Cortex M0 Micro Controller Note The R2 100 ohm resistor of Simply reset circuit and Diode amp RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over stress EOS 3 1 4 3 ZENER DIODE RESET CIRCUIT The Zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely Use Zener voltage to be the active level When voltage level is above Vz 0 7V the C
184. t leakage situation P2CON is Port2 Configuration register Write 1 into P2CON 9 0 will configure related port 2 pin as pure analog input pin to avoid current leakage Bit Description Attribute 3110 Reserved P2CONI9 0 P2 x configuration control bits x 0 to 9 RW 20 0 P2 x be an analog input ADC input or digital pins 1 P2 x is pure analog input can t be a digital I O pin Note When Port 2 n is general I O port not ADC channel P2CON n must set to 0 or the Port 2 n digital signal would be isolated SONiX TECHNOLOGY CO LTD Page 69 Version 2 0 kq Z WAY SN32F720 Series SO N N 32 Bit Cortex M0 Micro Controller 6 5 4 ADC Interrupt Enable register ADC_IE Address offset OX0C This register allows control over which A D channels generate an interrupt when a conversion is complete For example it may be desirable to use some A D channels to monitor sensors by continuously performing conversions on them The most recent results are read by the application program whenever they are needed In this case an interrupt is not desirable at the end of each conversion for some A D channels 3110 Reseved Rl IE 9 0 These bits allow control over which A D channels generate interrupts for R W conversion completion When bit x is one completion of a conversion on AIN x will generate an interrupt 6 5 5 ADC Raw Interrupt Status register ADC RIS Address offset 0x10
185. t the count and generate an interrupt on match The CT16Bn register is set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value PCLK 2 3 CT16Bn TC 1 2 3 4 5 6 0 1 2 TC Reset Interrupt The following figure shows a timer configured to stop and generate an interrupt on match The CT16Bn MRx register is set to 6 In the next clock after the timer reaches the match value the CEN bit in CT16Bn TMRCTRL register is cleared and the interrupt indicating that a match occurred is generated EN SN WAP CT16Bn_TC 2 3 4 5 6 CEN bit 1 0 Interrupt SONiX TECHNOLOGY CO LTD Page 73 Version 2 0 32 Cortex M0 Micro Controller SONIN 76 PWM 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is to zero unless their match value in 16 registers is equal to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs the PWM output remains continuously LOW 3 f a match value larger than the PWM cycle length is written to the CT16Bn registers and the PWM signal is HIGH a
186. te generator must be disabled DIVADDVAL 0 during auto baud Also when auto baud is used any write to USARTn DLM and USARTn DLL registers should be done before USARTn ABCCTRL register write The minimum and the maximum baud rates supported by USART are a function of USARTn_PCLK and the number of data bits stop bits and parity bits ratemin 2x PCLK lt UART lt PCLK lt r l wv aroma 16 215 baudrate 6 x 2 databits paritybits stopbits 13 8 2 AUTO BAUD MODES When the SW is expecting an AT command it configures the USART with the expected character format and sets the ACR Start bit The initial values in the divisor latches DLM and DLM don t care Because of the A or a ASCII coding 0x41 a 0x61 the USART Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges When the ACR Start bit is set the auto baud protocol will execute the following phases 1 START bit setting the baud rate measurement counter is reset and the RSR is reset The RSR baud rate is switched to the highest rate 2 A falling edge on URXD pin triggers the beginning of the start bit The rate measuring counter will start counting USARTn_PCLK cycles 3 During the receipt of the start bit 16 pulses are generated on the RSR baud input with the frequency of the USART input clock guaranteeing the start bit is stored in the RSR 4 During the receipt of the st
187. ted 13 5 6 RS485 EIA 485 FRAME STRUCTURE SN32F700 5 485 TRANSCEIVER URXD UTXD Differential Bus URTS e 13 6 BAUD RATE CALCULATION The USART baud rate is calculated as USARTn PCLK UART gauprate Oversampling x 256 x DLM DLL x 1 DIVADDVAL MULVAL Where USARTn PCLK is the peripheral clock USARTn DLM and USARTn DLL are the standard UART baud rate divider registers and DIVADDVAL and MULVAL are USART fractional baud rate generator specific parameters in USARTn FD register The value of MULVAL and DIVADDVAL should comply to the following conditions 1 1 S MULVAL s 15 2 0 lt DIVADDVAL s 14 3 DIVADDVAL MULVAL 4 Oversampling is 8 or 16 The value of the USARTn FD register should not be modified while transmitting receiving data or data may be lost or corrupted The oversampling method can be selected by programming the bit in USARTn FD register and can be either 16 or 8 times the baud rate clock e OVER8 1 Oversampling by 8 to achieve higher speed to USARTn PCLK 8 In this case the maximum receiver tolerance to clock deviation is reduced SONiX TECHNOLOGY CO LTD Page 121 Version 2 0 N j SN32F720 Series N E 32 Bit Cortex M0 Micro Controller uh sampingcoce f fa 72 73 3 8 3 8 gt lt 1 BIT TIME Sampled values e OVER8 0 Oversamplin
188. ted if the MODEM Status Interrupt is enabled gt 2 Whenever the RI bit changes from a high to a low state an interrupt is generated if the MODEM Status Interrupt is enabled 3 Whenever the DSR bit changes state an interrupt is generated if the MODEM Status Interrupt is enabled 4 Whenever the CTS bit changes state an interrupt is generated if the MODEM Status Interrupt is enabled Description Reserved DCD Data Carrier Detect State Complement of input DCD This bit is connected to USARTn MC 3 in modem loopback mode Ring Indicator State Complement of input RI This bit is connected to USARTn_MC 2 in modem loopback mode Data Set Ready State Complement of input signal DSR This bit is connected to USARTn MC 0 in modem loopback mode Clear To Send State Complement of input signal CTS This bit is connected to USARTn_MC 1 in modem loopback mode DDCD Delta DCD Set upon state change of input DCD Cleared after reading this register 0 No change detected on modem input DCD 1 State change detected on modem input DDSR Delta DSR Set upon state change of input DSR Cleared after reading this register 0 No change detected on modem input DSR 1 State change detected on modem input DSR DCTS Delta CTS Set upon state change of input CTS Cleared after reading this register 0 No change detected on modem input CTS 1 State change detected on modem input CTS SONiX TECHNOLOGY CO
189. ter USARTn SCICTRL n 0 1 a 0x38 tior Attribute Reset Reserved Rl TC 7 0 Count for SCLK clock cycle when SCLKEN 1 SCLK will toggle every R W 0 0 7 0 1 USARTn_PCLK cycle XTRAGUARD When the protocol selection T 0 this field indicates the number of bit R W N A times ETUs by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times character SONiX TECHNOLOGY CO LTD Page 139 Version 2 0 SON IX sia iss When the protocol selection T 0 the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK When NACK has occurred this number of times plus one the TX Error TXERR bit in USARTn_LS register is set an interrupt is requested if enabled and the USART is locked until the FIFO is cleared 4 Reserved SCLKEN SCLK enable Enable if the smart card to be communicated with requires a clock 0 Disable 1 Enable HW will switch GPIO to UnSCLK pin PROTSEL Protocol selection as defined the ISO7816 3 standard 0 T 0 1 T 1 NACKDIS NACK response disable bit Only applicable in T 0 0 A NACK response is enabled 1 A NACK response is inhibited Reserved 13 12 19 USART n RS485 Control register USARTn_RS485CTRL n 0 1 Address Offset 0x3C Name Reserved
190. ter to a high level Loop mode operation holds this signal in its inactive state Data Set Ready When low this indicates that the MODEM or data set is ready to establish the communications link with the UART The DSR signal is a MODEM status input whose condition can be tested by reading bit 5 DSR of USARTn MS register Data Carrier Detect When low indicates that the data carrier has been detected by the MODEM or data set The DCD signal is a MODEM status input whose condition can be tested by reading bit 7 DCD of USARTn MS register Ring Indicator When low this indicates that a telephone ringing signal has been received by the MODEM or data set The RI signal is a MODEM status input whose condition can be tested by reading bit 6 RI of USARTn MS register Depends on GPIOn_CFG Depends on GPIOn_CFG Depends on GPIOn_CFG SONiX TECHNOLOGY LTD Page 118 Version 2 0 32 Cortex M0 Micro Controller 13 4 BLOCK DIAGRAM TX UCTS MODEM SED gt gt USARTn TSR gt UTXD URI MS lt UDCD UDTR MC URTS UART Baud Rate Generator DLL DLM INTERRUPT RX USARTn_IE USARTn 4 RSR USARTn_Il gt USARTn_FC USARTn_LS
191. terrupt on match channel 3 1 Interrupt requirements met on match channel 3 Interrupt for match channel 2 0 No interrupt on match channel 2 1 Interrupt requirements met on match channel 2 t omm Interrupt flag for match channel 1 0 No interrupt on match channel 1 1 Interrupt requirements met on match channel 1 Interrupt for match channel 0 0 No interrupt on match channel 0 1 Interrupt requirements met on match channel 0 8 7 11 CT32Bn Timer Interrupt Clear register CT32Bn IC n 0 1 Address Offset 0x3G Reseved R o 1 Clear bit 1 Clear MR3IF bit 0 No effect 1 Clear MR1IF bit 0 No effect 1 Clear MR2IF bit 0 No effect 1 Clear MROIF bit SONiX TECHNOLOGY CO LTD Page 88 Version 2 0 N j SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller d WATCHDOG TIMER WDT 9 1 OVERVIEW The purpose of the Watchdog is to reset the MCU within a reasonable amount of time if it enters an erroneous state When enabled the Watchdog will generate a system reset or interrupt if the user program fails to feed or reload the Watchdog within a predetermined amount of time The Watchdog consists of a divide by 128 fixed pre scaler and a 8 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is 0x01 Hence the minimum Watchdog interval is Twpr 12
192. terrupt on pin x to be enabled x 0 to 11 0 Disable Interrupt on Pn x 1 Enable Interrupt on Pn x 5 3 8 GPIO Port n Raw Interrupt Status register GPlOn RIS nz0 1 2 3 Address offset Ox1C This register indicates the status for GPIO control raw interrupts A GPIO interrupt is sent to the interrupt controller if the corresponding bit in GPlOn IE register is set 3132 Reseved RR IF 11 0 GPIO raw interrupt flag x O to 11 0 No interrupt on Pn x 1 Interrupt requirements met on Pn x 5 3 9 GPIO Port n Interrupt Clear register GPlOn IC nz0 1 2 3 Address offset 0x20 31 12 Reserved IC 11 0 Selects interrupt flag on pin x to be cleared x 0 to 11 0 No effect 1 Clear interrupt flag on Pn x 5 3 10 GPIO Port n Bits Set Operation register GPlOn BSET nz0 1 2 3 Address offset 0x24 In order for SW to set GPIO bits without affecting any other pins in a single write operation the GPIO bit is set if the corresponding bit in the GPlOn BSET register is set SONiX TECHNOLOGY CO LTD Page 62 Version 2 0 SON IX Lm NN BSET 11 0 Bit Set enable x 0 to 11 0 No effect on Pn x 1 Set Pn x to 1 5 3 11 GPIO Port n Bits Clear Operation register GPlOn BCLR nz0 1 2 3 Address offset 0x28 In order for SW to clear GPIO bits without affecting any other pins in a single write operation the GPIO bit is cleared if the corresponding bit in this register is set
193. the RTS output and the actual value of URTS will be copied in the URTS Control bit of the USART As long as Auto RTS is enabled the value of the RTS Control bit is read only for software Example Suppose the USART operating in type 16550 mode has the trigger level in USARTn FIFOCTRL register set to 0x2 then if Auto RTS is enabled the USART will deassert the URTS output as soon as the receive FIFO contains 8 bytes The URTS output will be reasserted as soon as the receive FIFO hits the previous trigger level 4 bytes URXD start Byte Stop Start Bit o 7 Stop WitaryBit o 7 Stop URTS Read USARTn RX FIFO USARTn FIFO Level TSISISI Terre SONiX TECHNOLOGY CO LTD Page 123 Version 2 0 N WY SN32F720 Series S N N x 32 Bit Cortex M0 Micro Controller 13 7 2 AUTO CTS The Auto CTS function is enabled when CTSEN 1 If Auto CTS is enabled the transmitter circuitry checks the UCTS input before sending the next data byte When UCTS is active low the transmitter sends the next byte To stop the transmitter from sending the following byte UCTS must be released before the middle of the last stop bit that is currently being sent In Auto CTS mode a change of the UCTS signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set but the DCTS bit in the USARTn MS register will be set Ir X 1 __ 0 0 X 1 O E X
194. to MCU for engineering production even mass production SONiX TECHNOLOGY CO LTD Page 157 Version 2 0 SON IX ton lead 17 2 SN32F720 STARTER KIT SN32F727 Starter kit is easy development platform It includes SN32F727 real chip and connectors to input signal or drive extra device of user s application It is a simple platform to develop application as target board not ready The starter kit can be replaced by target board because of SN32F720 series MCU integrates SWD debugger circuitry n gt lt Er d SONAX SN32F707 SN32F717 SN32F727 Storter Kit REV V3 DB 011613 JP46 Mini USB connector S2 VDD power source is 3 3V from board Writer or external power J2 Do not short if External power source is used U1 SN32F727F real chip D3 Power LED C26 C35 10 ch ADC capacitors RESET button External reset trigger source WAKEUP button Trigger source to wake up from deep sleep down mode Y1 External high speed X tal Y2 External low speed 32 768KHz X tal J17 SN LINK connector J20 Short to force MCU stay in Boot loader SONiX TECHNOLOGY CO LTD Page 158 Version 2 0 N N 7 SN32F720 Series N N x 32 Bit Cortex M0 Micro Controller 1 8 ELECTRICAL CHARACTERISTIC 18 1 ABSOLUTE MAXIMUM RATING Supply voltage bayan a qapas ddan ide Ge aysayan ane awas usaha au 0 3V 3 6V Input in voltage Vin Vss 0 2V
195. to system is a rising curve and needs some time to achieve the normal voltage Power on reset sequence is as following Power up System detects the power voltage up and waits for power stable External reset only external reset pin enable System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from Boot loader v v v v v SONiX TECHNOLOGY CO LTD Page 32 Version 2 0 N N 7 SN32F720 Series NS x 32 Bit Cortex M0 Micro Controller 3 1 2 WATCHDOG RESET WDT RESET Watchdog reset is a system protection In normal condition system works well and clears watchdog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following e X Watchdog timer status System checks watchdog timer overflow status If watchdog timer overflow occurs the System is reset System initialization All system registers is set as initial conditions and system is ready Oscillator w
196. tream for USART gt SIR receive logic interprets a high state as 1 and low pulses as 0 gt transmit encoder output has the opposite polarity to the decoder input The SIR output is 0 when Idle gt In mode the STOP bits must be configured to 1 stop bit gt The IrDA specification requires the acceptance of pulses greater than 1 41 us The acceptable pulse width is pro grammable Glitch detection logic on the receiver filters out pulses of width less than 2 x low power baud rate Pulses of width greater than 2 low power baud rate will be accepted as a pulse gt receiver can communicate with a low power transmitter In low power mode the pulse width is not maintained at 3 16 of the bit period Instead the width of the pulse is 3 times the low power baud rate which can be a minimum of 1 42 MHz Generally the low power baud rate is 1 8432 MHz 1 42 MHz lt low power baud rate lt 2 12 MHz gt If FIXPULSEEN 0 in USARTn ED register the low level pulse width shall gt 2 16 baud cycle for receiver to be SONiX TECHNOLOGY CO LTD Page 126 Version 2 0 I N N 9 Y SN32F720 Series Is D Eu 32 Bit Cortex M0 Micro Controller accepted as a low pulse if FIXPULSEEN 1 the low level pulse width shall gt 1 2 IrDA Transmitter Pulse Width for receiver to be accepted as a low pulse gt PULSEDIV bits are used to select the pulse width when the fixed pulse width mode is used in IrDA mode
197. unter Mode TC is incremented on rising edges on the CAP input selected by CIS bits 10 Counter Mode TC is incremented on falling edges on the CAP input selected by CIS bits 11 Counter Mode is incremented on both edges on the CAP input selected by CIS bits 8 7 4 CT32Bn Match Control register CT32Bn MCTRL nz0 1 Address Offset 0x14 Bit Reseed zp ase Stop MR3 TC will stop and CEN bit will be cleared if MR3 matches TC 0 Disable 1 Enable Enable reset when matches 0 Disable 1 Enable Enable generating an interrupt when MR3 matches the value the 0 Disable 1 Enable Stop MR2 TC will stop and CEN bit will be cleared if MR2 matches 0 Disable 1 Enable Enable reset when MR2 matches 0 Disable 1 Enable Enable generating an interrupt when MR2 matches the value in TC 0 Disable 1 Enable ae Stop MR1 TC will stop and CEN bit will be cleared if MR1 matches TC 0 Disable 1 Enable Enable reset when MR1 matches 0 Disable 1 Enable BENE Enable generating an interrupt when MR1 matches the value in the TC 0 Disable 1 Enable ZA Stop MRO TC will stop and CEN bit will be cleared if MRO matches 0 Disable 1 Enable a 0 Disable 1 Enable EN Enable generating an interrupt when MRO matches the value in the TC 0 Disable 1 Enable 8 7 5 CT32Bn Match register 0 3 CT32Bn 0 3 nz0 1 Address
198. up function CTISBO PME SWCLK Serial Wire Clock pin 16 0 PWM2 CT16B0 PWM output 2 SONiX TECHNOLOGY CO LTD Page 18 Version 2 0 P0 11 SWDIO CT32B0_PWM3 P1 0 CT32B1_CAP0 25 1 1 2 1 PWMO I2SSDA P1 2 CT32B1 PWM 1 I2SBCLK P1 3 CT32B1 PWM2 125 5 P1 4 CT32B1_PWM3 DPDWAKEUP P1 5 CT32B0_CAP0 P1 6 URXD0 CT32BO PWMO V0 P1 7 UTXDO CT32B0_PWM1 1 8 16 1 UCTS0 P1 9 CT16B1 PWMO USCLKO P1 10 URTSO0 16 1 PWM1 P1 11 CLKOUT 2 0 2 9 0 9 P3 0 UDTRO SEL1 SONiX TECHNOLOGY CO LTD SN32F720 Series 32 Bit Cortex M0 Micro Controller P0 11 Port 0 11 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode Built in wakeup function SWDIO Serial Wire Debug input output pin CT32B0_PWM3 CT32B0 PWM output 3 P1 0 Port 1 0 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CT32B1_CAP0 CT32B1 Capture input 0 I2SMCLK 125 Main Clock pin P1 1 Port 1 1 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CT32B1 PWMO PWM output 0 for CT32B1 12550 125 Serial data pin P1 2 Port 1 2 bi direction pin Schmitt trigger structure and built in pull up pull down resisters as input mode CT32B1_PWM1 PWM output 1 for CT32B1
199. value is received When this occurs the receiver will be automatically disabled by HW RXEN bit will be cleared by HW the received non matching address character will not be stored in the RXFIFO 13 5 3 RS 485 EIA 485 AUTO DIRECTION CONTROL ADC RS485 EIA 485 mode includes the option of allowing the transmitter to automatically control the state of the DIR pin as a direction control output signal Set ADCEN bit in USARTn RS485CTRL register to enable this feature The ADCEN bit takes precedence over all other mechanisms controlling the direction control pin with the exception of loopback mode 13 5 4 RS485 EIA 485 DRIVER DELAY TIME The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de assertion of URTS This delay time can be programmed in the 8 bit USARTn RS485DLYV register The delay time is in periods of the baud SONiX TECHNOLOGY CO LTD Page 120 Version 2 0 N N Y SN32F720 Series D D E 32 Cortex M0 Micro Controller clock Any delay time from 0 to 255 bit times may be used 13 5 5 RS485 EIA 485 OUTPUT INVERSION The polarity of the direction control signal on the URTS pin can be reversed by programming OINV bit in USARTn RS485CTRL register When OINV bit is set the direction control pin will be driven to logic 1 driven LOW when the transmitter has data waiting to be sent The direction control pin will be driven to logic O driven High once the last bit of data has been transmit
200. when FIXPULSEEN 1 The value of these bits should be set so that the resulting pulse width is at least 1 63 ps gt 8 bit in USARTn FD register must be 0 in IrDA mode FIXPU 0 OVEF Transmitte se Width us j 0 3 16 x Baud rate 2 X L1 6 0 128 x 1 7 0 256 x SONiX TECHNOLOGY CO LTD Page 127 Version 2 0 NI M 1 N N x 32 Bit Dalec 13 10 SMART CARD MODE The Smart card mode is enabled by setting the USARTEN bit to 1 and MODE 2 0 011b in USARTn CTRL register the USART provides bidirectional serial data on the open drain UTXD pin No URXD pin is used in this mode If a clock source is needed as an oscillator source into the Smart Card a timer match or PWM output can be used in cases when a higher frequency clock is needed that is not synchronous with the data bit rate The USCLK pin may not be adequate for most asynchronous cards since it will output synchronously with the data and the data bit rate SW must use timers to implement character and block waiting times in stead SN32F700 ied icis Smart Card GPIO PWM CLK UTXD DATA GPIO RST 13 10 1 SMART CARD SETUP PROCEDURE A T 0 protocol transfer consists of 8 bits of data an even parity bit and two stop bits t that allow for the receiver of the particular transfer to flag parity errors through the NACK response Extra guard bits may be added according to card requirements
201. xecution SONiX TECHNOLOGY CO LTD Page 38 Version 2 0 N j SN32F720 Seri N N x 32 Bit Cortex M0 3 22 SYSTEM ifferent clock sources be used to drive the system clock SYSCLK 12 MHz internal high speed RC IHRC 16 KHz internal low speed RC ILRC PLL clock High speed external EHS crystal clock Low speed external ELS 32 768 KHz crystal vy v v v v Each clock source can be switched on or off independently when it is not used to optimize power consumption The micro controller is a dual clock system There are high speed clock and low speed clock The high speed clock is generated from the external oscillator amp on chip PLL circuit The low speed clock is generated from on chip low speed RC oscillator circuit ILRC 12 KHz 3 2 1 INTERNAL RC CLOCK SOURCE 3 2 1 1 Internal High speed RC Oscillator IHRC The internal high speed oscillator is 12MHz RC type The accuracy is 2 under commercial condition IHRC can be switched on and off using the IHRCEN bit in Analog Block Control register SYSO_ANBCTRL 3 2 1 2 Internal Low speed RC Oscillator ILRC The system low clock source is the internal low speed oscillator built in the micro controller The low speed oscillator uses RC type oscillator circuit The frequency is affected by the voltage and temperature of the system In common condition the frequency of the RC oscillator is about 16KHz Note The ILRC can

SN32F720 Series

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