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X3-SD16 User`s Manual

1. 10 A E 98 Figure 19 P16 Connector E A a aaas 101 Figure 20 X3 SDI6 J3 Orientatioh e ehe sa a ee DRE HG a ee ae 105 Figure 21 X3 SD16J3 Side Views zc aree e n pe EURO EORR GER PI ERE TUER RENE ERE 105 Figure 22 X3 SD16 Mechanicals Top View Rev B nennen enr 106 Figure 23 X3 SD16 Mechanicals Top View Rev A nennen enne enne 107 X3 SD16 User s Manual Introduction Real Time Solutions Thank you for choosing Innovative Integration we appreciate your business Since 1988 Innovative Integration has grown to become one of the world s leading suppliers of DSP and data acquisition solutions Innovative offers a product portfolio unrivaled in its depth and its range of performance and I O capabilities Whether you are seeking a simple DSP development platform or a complex multiprocessor multichannel data acquisition system Innovative Integration has the solution To enhance your productivity our hardware products are supported by comprehensive software libraries and device drivers providing optimal performance and maximum portability Innovative Integration s products employ the latest digital signal processor technology thereby providing you the competitive edge so critical in today s global
2. 15 Other Considerations M 16 Microsoft Visual Studi 2005 citet eee cleanin Re RIS EORR cto 17 DEI dd ccc 19 Nina 19 Writing Custom Acquisition 0 8 1 1 2 1 een neenon esee esso sesso esso 20 Snap Bxample 20 TOOIS 20 Program DEST OM i ote dte eben upset eerte cn UO RD RR ERE E Rl aep aed ES 21 The Host Applications 55 4e eet e e eet et tete et NO ee 21 E E 21 SII El E 22 Data Streaming e tnnt et iu ER E RR ER REO rete ete i uud eat 24 hour M n 25 FE PROM tiet reno obit p etie tere htl t Pet 25 25 Host Side Program OrganiZationives ee dese te e e A E gb 25 IApplicationlo cede ed e ttr HY TEGRREU 26 IEEE 26 eter ETE TENOR ER TENEO EROR ATEM RE VOY cr pn dS 29 Startins Data 1109 eie GESENDET ER 30 Handle Data Available e E FUR UD E
3. ee o eR EU ee GERE Ve Fate EE er Ig 68 PLL Control Intetface nsina teda et achete dte tpe eu nana ayia S HERE REIR eg 69 Notes About the PLE Configuration set tee e EROR D E ER ERR euet 70 Tamiutig Analysistsac seit ctf des t tu e ode die edebant puto die 71 2 IEEE A 71 Trigoer SOUEIGe ces 73 Framed Trigger Mode te eadeni aceite st 73 peint P CEA 74 Synchronizing Multiple 3 5 016 74 me ates hae set Mots tees abe esl EP cen ote 74 64 channel System Example sessi 75 FrameWork Logit Functionality 2i etate dte On rexit RR oa ci ee Re Eod 76 Power Controls and Thermal Desi gts see the rte Hehe pes eee GR EE ERR ado reete eget 78 System Thermal Designar er eere te metas ne dece e rebat Ee Ot 78 Temperature Sensor and Over Temperature Protection sss enne enne nennen ener ener 78 Reducing Power Consumption e d ee eee nde ei ede iue e bea turo aee esee cetus e 79 Alert ee ea d e etes ees nete eget rotes ae 79 OVeLVIe Wi io ost
4. C BINARY 7 7 0 04001090 90 800107 0000 0000 859 25 19 0250000 0000 0700 1 00050090 X9 111 1100 Table 5 Temperature Data Format The logic component provides a programmable temperature warning BARO 0x4 and failure BARO 0x5 The warning and fail may create alert packets when enabled Both temperature warning and failure are latched when they occur and must be cleared by a read their respective registers Table 10 Temperature Alarms Alarm Setting Temperature Celsius Set Register to Warning 70 X 460 Fail 85 550 A temperature failure results in a power down signal to the analog electronics signaling to shut down The FPGA and host interface remain active and the module should continue to communicate unless a catastrophe has occurred The thermal shutdown behavior of each X3 module is detailed in the specific discussion of that t module The power down can be cleared by reading from the temperature fail register The temperature sensor must be present and responding for the module to operate If the temp sensor fails this is treated as a temperature failure The logic continues to attempt to communicate with the temperature sensor If multiple failure conditions are found the logic should be reloaded Note that the control logic for the temperature sensor is in the application logic so the logic must be conf
5. e o ib Pete io e NE 79 Types otf ee Re tere ea i ette e eR tures RE ERI ME RO 80 Alert Packet Format 2 e LED eh eee Ree ee Soha eee 80 X3 SD16 User s Manual Software Support P 81 Taggme the Data Stream OG ov aus ees VERS NR iR 81 Using the X3 8D10 5 E EE RE RU RASEN IU ER 82 Where tO ru 82 Gettng Good Analog Performance ete ee t e e See chang ER RUE UD WEE ECI NA TA I RE RN ST TEES eee 82 Application Logic said RR GRE E T RP AER EE SI ERA REGES EN TRU HERO Aceves 83 Calibration V emere miae eru pei e tres 83 Production Calibration 3 cde ge HE Pre a UG SIRE S eR de pee eee 83 Updating the Calibration Coefficients ssssssssssssessesseeeeen eene i arenis nennen nnne nnne nnne 84 Performance e Ie RODRIGO tee AW HE Pap ERROR 85 Power Cons mption der ar ee e e ER ER IG ie tede i edi ete 85 Environmental nl aan vinta pect ede onte E eia nia eee ae beta ieee eee ee 86 Analog ee E RO IR ERE RT GENRE WEN NOH 86 Analog auiem o tere detto dte ede 92 uuu CRM EE 96 Inpu
6. FBlockCount 0 FBlockRate 0 FTriggered 1 TestCounter 0 Time Reset The class variables above are used to maintain counts of blocks received reception rate and whether the module is currently triggered These values are initialized prior to each streaming run The Time Reset is to clear any pass data rate calculations PrefillCount std max Settings PrefillPeriod 1 The above code extract the prefill count in seconds up to one second This variable will be used to prevent any instantaneous uderflow caused by the DACs wanting data The prefill count will be used to prefill the bus master region Module Dio DioPortConfig Settings DioConfig Module FrontPanel FrontPanelPortConfig Settings FrontPanelConfig The module supports programmable bit I O available on connector JP16 and on the Front Panel connector The code fragment above programs the direction of these DIO bits in accordance with the settings from the GUI Channel Enables Module Input Info Channels DisableAll Module Output Info Channels DisableAll for int i 0 i lt Channels i if Settings ActiveChannels i true false Module Output Info Channels Enabled i true int ActiveChannels Module Output Info Channels ActiveChannels if lActiveChannels Log Error Must enable at least one channel UI AfterStreamStop return false Disable input channels since this is DAC exam
7. Digital filter in A D rejects signals above Fs 2 A D Devices Texas Instruments ADS1278 Output Format 2 s complement 32 bit Number of A D Devices 16 simultaneously sampling Sample Rate 0 to 144 kHz Sample Clock Rates 1 2 kHz to 144 kHz PLL can generate clocks up to 280 MHz Calibration Factory calibrated for gain and offset errors Non volatile EEPROM coefficient memory Table 14 X3 SD16 A D Features Conversion clocking is provided through separate special circuitry that minimizes jitter on the clocks The clock circuitry allows for a variety of clock sources including two external sources to be used as conversion timebases See the clock discussion for more details The following block diagram shows the general arrangement of the A D The differential inputs from the front panel connector are adjusted for range through a differential amplifier and input to the A D X3 SD16 User s Manual Clk Programmable Gain 1 2 5 5 t Differential Input Ext Trigger Figure 13 X3 SD16 A D Channel Diagram Input Range and Conversion Codes The A D conversion codes for the analog ranges are shown in the following table voltages are differential meaning that 10V requires that the voltage difference between inputs is 10V The output codes are 2 s complement 24 bit numbers Range 20V Range 10V
8. e j JP2 Power Test P15 PCIe Figure 22 X3 SD16 Mechanicals Top View Rev B X3 SD16 User s Manual 106 asese RP3O RPS2 pA 152 mau pocas ED o HEP a i 88 ao ae B tty T 8 g RO i E m h BH le me Er we con B EHo SEN es am feles URDU C463 st meos za APR ae s 23 25 fein JU RH Ed 7W E e W H EH 2 rane mates DI d 529 m 79 EE PE in MILD Eu EN m HE 5 amus ur Sca 5 s STANDARD XMC3 W FAN d e HUM VES wai PIS PIS Ld Nei SF PCle 170 Lh zo cus o pensaci cn STANDARD N A E i 99 EXT cm 12 MET C214 acum c m T EF om djeg ie P guts HER m B Dm 5 1 lt gt mS gs call S te alta Se v ouM 4s x vj m Rig 22 n zs em 2 ng uis me 25 2 o amm afl ES 8 8 17 9 5 E 4 P a i m EEE cas Ex
9. By default 32 Mbytes 4MBytes observed under Linux are allocated as bus master memory which implies that the Pkt Size must be restricted to fit within this region The packet size is in terms of samples per enabled channel so if a module has 4 enabled channels of 16 bits each then a packet size of 1000 translates to 2000 32 bit words Thus we recommend a packets size that fits eight times in the bus master region So if your bus master region is 32 Mbytes then 4 Mbytes is a good size packets of less data will cause more interrupts to the host PC and thus less time for your software to do other tasks Alerts Group Enables out of band information packets to be delivered to the Host PC informing different conditions of the hardware Waveform Group Selects the type of waveform to be calculated by the software also external files can be used as the data source Frequency and Amplitude Group They determine in the case where data source is not a disk file the output waveform s frequency and percentage of full scale Digital I O Group This control governs the configuration of the P16 DIO port on the module The DIO port can be configured for input or output on a byte wise basis as a function of the configuration code in Digital I O Config Mask See the DIO Control Register description user logic offset 0x14 for details Front Panel I O Group This control governs the configuration of the Front Panel DIO port on the module The DIO
10. Log Stream not connected Open the boards return false Make sure packets fit nicely in BM region if FBusmasterSize 4 unsigned int Settings StreamPacketSize Log Error Packet size is larger than recommended size return false Next we test that the Stream object has been successfully connected to the module object happens at Open And then we verify that at least four packets will fit in the bus master are if SampleRate Module Output Info MaxRate Log Sample rate too high StopStreaming UI AfterStreamStop return false Clock config ActualSampleRate SampleRate Route clock to active analog devices Set reference based on clock source to obtain correct FrequencyActual double reference if Settings SampleClockSource 0 reference SampleRate Module Output Info ClockFactor Module Clock OutputClock PmcModule Timebase oExternal X3 SD16 User s Manual 47 else reference Module Output Info ReferenceClock Module Clock OutputClock PmcModule Timebase oVco Module Clock Reference reference Module Clock Frequency SampleRate The module may accept an external sample clock but also features a programmable PLL clock source which may be used as a sample clock for the A D input channels Module Trigger PmcModule tOutput false The code above states that the output trigger is in a inactive state
11. X3 SD16 DAC Features Conversion clocking is provided through separate special circuitry that minimizes jitter on the clocks The clock circuitry allows for a variety of clock sources including two external sources to be used as conversion timebases See the clock discussion for more details The following block diagram shows the general arrangement of the DAC The DACS are directly connected to the FPGA which provides direct control of the devices for custom logic designs The analog circuitry for the DAC output converts from the DAC output to a voltage range of 2 to 2V on the connector with reconstruction filtering Special output voltage ranges can be ordered to meet application requirements X3 SD16 User s Manual 59 Ert Clk Output 0v Output 10v Ext Trigger Figure 15 X3 SD16 DAC Channel Diagram Output Range and Conversion Codes The DAC conversion codes for the output voltages are shown the following table The output codes are 2 s complement 24 bit numbers Output Voltage Nominal Conversion Code hex 2V Ox7FFFFF HV 0x400000 OV 0x000000 1V 0xA00000 2V 0x800000 Table 18 DAC Conversion Coding X3 SD16 User s Manual 60 DAC Outputs The X3 SD16 DAC outputs are single ended voltage outputs with 1 ohm output impedance The output voltage 15 referenced to the card ground Each DAC channel has a reconstruction filter on its output T
12. external clock and external trigger inputs Connector Type MDR Number of Connections 68 Connector Part Number 3M part number 10268 55H3VC Mating Connector 3M part number 10168 6000EC IDC Digikey www digikey com P N MPB68A ND Cable Innovative part number 65057 MDR 68 male to male 36 inches 0 91 meters This is the MDR6S as viewed from the front panel Pin 35 Pin 68 lt gt Pin 1 Pin 34 X3 XMC Front Panel View X3 XMC JP1 Front Panel Connector Pin Assignments X3 SD16 User s Manual 96 AGND P P AGND DAC 0 8 4 nara DAC 2 10 DAC 3 11 DAC 4 12 5 13 DAC 6 14 DAC 7 15 AGND P P AGND AID 1 IN AID 1 IN AID 3 IN AID 3 IN AID 5 IN AID 5 IN AID 7 IN AID 7 IN AID 9 IN AID 9 IN AID 11 IN AID 11 IN AID 13 IN AID 13 IN AID 15 IN AID 15 IN AID 0 IN AID 0 IN AID 2 IN AID 21N AID 4 IN AID 4IN AID 6 IN AID 6 IN AID 8 IN AID 8 IN AID 10 IN AID 10 IN AID 12 IN AID 12 IN AID 14 IN AID 14 IN AGND AGND FP DIO 1 FP DIO 0 FP DIO 3 FP DIO 2 FP DIO 5 FP DIO 4 AGND AGND EXT CLK EXT CLK SYNC TRIGGER Note No Connect P Power I Input O Output I O Bidirectional All are relative to X3 module XMC P15 Connector P15 is the XMC PCI Express connector to the host X3 SD16 User s Manual pin header 0
13. int FVCXO Fphase detector 1 lt M 262144 5 Find operating mode fixed modulus or dual modulus A FVCXO mod Fphase_detector and value of A If A 0 then mode should be fixed divide if gt 0 then dual modulus mode is used X3 SD16 User s Manual 67 6 Select value of prescaler P based on operating mode Pick P and B such that M P B using smallest values and divisor ratio M possible For fixed divide P 1 2 or 3 For dual modulus 2 4 8 16 or 32 B 3 to 8191 integers 1 bypass 7 Check calculations Fout FVCXO D FVCXO PB A Fref 100 MHz lt FVCXO lt 140 MHz Table 4 Selecting values for PLL Divisors Fs MHz D FVCO Fref MHz R M A P B 31 100 4 124 4 100 1000 311 0 1 311 11 000 10 110 100 1000 110 0 1 110 5 100 20 102 100 1000 51 0 1 51 3 300 32 1056 100 1000 33 0 1 33 3 200 32 1024 100 1000 32 0 1 32 Table 5 PLL Example Settings The software tools provide hooks for direct programming of the PLL divisors to override the automatic functions in Malibu During experimentation the PLL registers can also be written using Peek Poke functions or scripts These functions are supported on the Debug tab in the example applications SNAP and WAVE Consult the AD9510 register map for details on register formats PLL Lock and Status The PLL has a status pin that can be programmed to show when the PLL is locked or other status information The
14. lt Settings PacketSize UI gt Log Error Frame count must exceed packet size UI gt AfterStreamAutoStop return The module supports both framed and continuous triggering In framed mode each trigger event whether external or software initiated results in the acquisition of a fixed number of samples In continuous mode data flow continues whenever the trigger is active and pauses while the trigger is inactive The code above issues a warning if the trigger mode is framed and ill formed FBlockCount 0 FBlockRate 0 FTriggered 1 The class variables above are used to maintain counts of blocks received reception rate and whether the module is currently triggered These values are initialized prior to each streaming run Channel Enables for inti 0 i Channels 1 Module Input Info Channels Enabled i Settings ActiveChannels i true false int ActiveChannels Module Input Info Channels ActiveChannels if ActiveChannels UI gt Log Error Must enable at least one channel UI gt AfterStreamAutoStop return The modules supports different quantity of A D channels of simultaneous data flow The previous call to GetSettings populated the Settings object with the number of channels to be enabled on this run That information is used to enable the required channels via the Channels object within the Module Input Info object X3 SD16 User s
15. 2005 using the NET UI and GNU GCC Linux Because the library has a common interface in all environments the code that interacts with Malibu is separated out into a class Applicationlo in the files Applicationlo cpp and h This class acts identically in all the platforms The Main form of the application creates an Applicationlo to perform the work of the example The UI can call the methods of the ApplicationIo to perform the work when for example a button is pressed or a control changed Sometimes however the ApplicationIo object needs to call back into the UI But since the code here is common it can t use a pointer to the main window or form as this would make Applicationlo have to know details of Borland DialogBlocks Linux or the environment in use The standard solution to decouple the ApplicationIo from the form is to use an Interface class to hide the implementation An interface class 15 an abstract class that defines a set of methods that can be called by a client class here ApplicationIo The other class produces an implementation of the Interface by either multiple inheriting from the interface or by creating a separate helper class object that derives from the interface In either case the implementing class forwards the call to the UI X3 SD16 User s Manual 25 form class to perform the action ApplicationIo only has to know how to deal with a pointer to a class that implements the interface and all UI depend
16. 77 Figure 5 Analog Input Bandwidth 0 to 1 MHz sample rate 144 87 Figure 6 Analog input settling time for 1 01 kHz 10Vp p square wave sample rate 144 2 87 Figure 7 Signal quality measurement 1 01 kHz input 19 9 Vp p sample rate 144 ksps 64K FFT no averaging 88 Figure 8 A D SNR vs Input Amplitude Vin 19 9Vp p 1 01 kHz 89 Figure 9 A D ENOB vs Sample Rate Vin 19 9Vp p 1 01 3 ene 89 Figure 10 A D SFDR vs Sample Rate Vin 19 9Vp p 1 01 kHz sine 89 Figure 11 A D THD vs Sample Rate Vin 19 9Vp p 1 01 kHz sine nennen 89 Figure 12 A D SNR vs Input Amplitude Fs 144 ksps Vin 1 01 kHz eene 9 Figure 13 A D SFDR vs Input Amplitude Fs 144 ksps Vin 1 01 kHz sine eene 9 Figure 14 A D ENOB vs Input Amplitude Fs 144 ksps Vin 1 01 KHZ sine 9 Figure 15 A D THD vs Input Amplitude Fs 144 ksps Vin 1 01 kHz sine eene 9 Figure 16 DAC Output for 1 01kHz sine 2Vp p 128 ksps update rate as measured by X3 SD16 A D with single ended 94 Figure 17 DAC Output for 2kHz sine 2Vp p 10 ksps update rate as measured by X3 SD16 A D with single ended zer eter teet 95 Figure 18 15 Connector
17. At the conclusion of the installation process ReserveMem exe will run except for SBC products This will allow you to set the memory size needed for the busmastering to occur properly This applet may be run from the start menu later if you need to change the parameters For optimum performance reserve at least 64 MB of memory for each Innovative board to be used simultaneously within the PC plus 32 MB for other system use For example if using two X5 400M modules reserve 2 64 32 MB 160 MB To reserve this memory the registry must be updated using the ReserveMem applet Simply type the desired size into the Rsv Region Size MB field click Update and the applet will update the registry for you If at any time you change the number of boards in your system then you must invoke this applet found in Start All Programs Innovative target board Applets Reserve Memory After updating the system exit the applet by clicking the exit button to resume the installation process 18 Figure 5 BusMaster configuration At the end of the install process the following screen will appear Installation The installation is complete Shut down your computer and install your board s then reboot your computer The drivers should load automatically and your board will become available Please refer to your Hardware Software Manual for instructions on hardware installation priorto powering the machine back on to make certain eve
18. DIO19 Digital IO 19 Fl DIO20 Digital IO 20 F2 DIO21 Digital IO 21 F3 DIO22 Digital IO 22 F4 DIO23 Digital IO 23 F5 DIO24 Digital IO 24 F6 DIO25 Digital IO 25 F7 X3 SD16 User s Manual 103 Signal Description P16 Pin DIO26 Digital IO 26 F8 DIO27 Digital IO 27 F9 DIO28 Digital IO 28 10 DIO29 Digital IO 29 11 DIO30 Digital IO 30 F12 DIO31 Digital IO 31 F13 DIO32 Digital IO 32 14 DIO33 Digital IO 33 F15 DIO34 Digital IO 34 F16 DIO35 PXI 10M Digital IO 35 PXI 10M Ref CIk F17 DIO36 PXI LBL6 Digital IO 36 PXI local bus left 6 F18 DIO37 PXI LBR_6 Digital IO 37 PXI local bus right 6 F19 DIO38 PXI DSTARA Digital IO 38 PXIE Differential STAR A A9 DIO39 PXI DSTARA Digital IO 39 PXIE Differential STAR A B9 DIO40 PXIE_100M Digital IO 40 PXIE 100M ref clk D9 DIO4 PXIE 100M Digital IO 41 PXIE 100M ref clk E9 DIO42 PXIE DSTARB Digital IO 42 PXIE Differential STAR B 19 DIO43 PXIE DSTARB Digital IO 43 PXIE Differential STAR B 19 DIO CLK PXI DSTARC Digital IO Clk PXIE Differential STAR C D19 DIO CLK PXI DSTARC Digital IO Clk PXIE Differential STAR C E19 Note PXI Express signals are only available when PXIE adapter card is used X3 SD16 User s Manual 104 Xilinx JTAG Connector JP3 is used for the Xilinx JTAG chain It connects directly with Xilinx JTAG cables such as Parallel Cable IV or Platform USB Connector T
19. Mnnovative 3 Typically most users will perform a Full Install by leaving all items in the Components to Install box checked If you do not wish to install a particular item simply uncheck it The Installer will alert you and automatically uncheck any item that requires a development environment that is not detected on your system 4 Click the Install button to begin the installation Note The default Product Filter setting for the installer interface is Current Only as indicated by the combo box located at the top right of the screen If the install that you require does not appear in the Product Selection Box 1 Change the Product Filter to Current plus Legacy X3 SD16 User s Manual 16 Each item of the checklist in the screen shown above has a sub install associated with it and will open a sub install screen if checked For example the first sub install for Quadia Applets Examples Docs and Pismo libraries is shown below The installation will display a progress window similar to the one shown below for each item checked Quadia Documentation Thank you for choosing Quadia Installing Documentation Figure 3 Progress is shown for each section X3 SD16 User s Manual 17 Tools Registration Registration Information User Name First Email Address Telephone Country Code Area Code Number Extension Fax Area Code
20. Number Company Name Address City State Country Postal Code Product Board M6713 2 2 Help Register Now Register Later Figure 4 ToolSet registration form Bus Master Memory Reservation Applet Reserve Memory for Dsp Combined DSP Board Usage Region Size Configuration Total physical memory MB 2047 Non paged pool size 256 Status Ok Update Help Exit Ready X3 SD16 User s Manual At the end of the installation process you will be prompted to register If you decide that you would like to register at a later time click Register Later When you are ready to register click Start All Programs Innovative Board Name Applets Open the New User folder and launch NewUser exe to start the registration application The registration form to the left will be displayed Before beginning DSP and Host software development you must register your installation with Innovative Integration Technical support will not be provided until registration is successfully completed Additionally some development applets will not operate until unlocked with a passcode provided during the registration process It is recommend that you completely fill out this form and return it to Innovative Integration via email or fax Upon receipt Innovative Integration will provide access codes to enable technical support and unrestricted access to applets
21. and sent to the Host PC via bus mastering X3 SD16 User s Manual 23 Data Streaming Capture Example Configure Setup Stream Zbt Ram EEProm Debug ER ER ER Select the Stream tab The controls on this tab control data pill flow meaning of each of the fields on this tab are Suspe explained below Data collection is initiated when the VCR Start button is z pressed and terminates when the VCR Stop button is pressed Log Pot QvemiteBdd or when the amount of data specified in the Data Logging configuration controls is accumulated Before r ate Block Count KB s Temp C Dig In To accommodate custom logic development the application TES supports execution of simple user authored scripts before and after the commencement of data flow The Start Scripts Before edit box specifies the full path spec to a text file containing valid script commands described below which will be executed prior to data flow Similarly the Start Scripts After edit box specifies the file containing commands to be executed after data flow is underway The following script commands are supported na Store n to logic register address a n Fetch n from logic register address p na Storen to port register address a p a n Fetch n from port register address ms n Delay n milliseconds All commands use postfix notation so parameters go before the co
22. are limited by the VCXO tuning range the PLL reference frequency and the PLL tuning parameter limits For the standard VCXO and PLL circuitry the sample clocks tuning resolution is st to 100 kHz Considering the divider that follows the VCXO the output resolution is shown in this table for several dividers For VCXO tuning range of 10 to 280 MHz and integer output divisors D 1 to 32 the allowable output ranges are shown Output Divisor D Lower Limit MHz Upper Limit MHz Resolution MHz 10 000 280 000 0 100 5 000 140 000 0 050 1 250 35 000 0 013 16 0 625 17 500 0 006 32 0 313 8 750 0 003 Table 3 Sample Clock Output Ranges and Resolution Programming the PLL and VCXO The VCXO used on the X3 SD16 is programmable to set the center frequency The frequency is set so that PLL runs at the maximum rate possible an even multiple of the A D clock rate So if the A D needs a 25 MHz clock the VCXO will be set to 25 MHz 10 250MHz This is the maximum frequency for the VCXO that is an even multiple of the desired clock rate The PLL will then run at 250 MHz and the dividers will be set to 10 X3 SD16 User s Manual 66 Programming the PLL to run at 250 MHz rate requires that the internal dividers be set so that the phase comparison is done at 100 kHz The remainder of this section discusses how to find these numbers for the PLL configuration For most applications the Malibu support software configures the PLL according to
23. are now ready to collect data or playback At this point trigger can be fired at any time to control the data acquisition process FrameWork Logic Functionality FrameWork Logic implements a data flow for the X3 SD16 that supports standard data acquisition and playback functionality This data flow when used with the supporting software allows the 3 5 16 to act as a data acquisition card with 2MB of data buffering and high speed data streaming to the host PCI Express The example software for the X3 SD16 demonstrates data flow control logic loading and data logging X3 SD16 User s Manual 76 Host Card 2 devices 16 channels PCle 2 devices 16 channels FR Figure 4 X3 SD16 FrameWork Logic Data Flow The data flow is driven by the data acquisition process Data flows from the A D devices into the A D interface component in the FPGA as they are acquired The data is then error corrected and the enabled channels are stored into the A D data buffer when trigger is true which is implemented a data queue in the SRAM When data is available in the buffer the packetizer pulls data from the queue creates data packets of the programmed size and sends those to the PCIe interface logic From here the Velocia packet system controls the flow of data to the host Data packets flow into host memory for consumption by the host program The DAC data flow is essentially the inverse of A D flow sample d
24. ch calibrated amp Module Input Calibrated range Settings Calibrated calibrated X3 SD16 User s Manual 36 Writing Custom Playback Applications This chapter explains how to write an application that plays a pre defined waveform the source of the waveform data maybe a disk file or calculated by the program on a per buffer basis Wave Example The Wave example in the software distribution demonstrates such functionality It consists of a host program in Windows or Linux which simultaneously works with user defined interface logic It uses the Innovative Malibu software libraries to accomplish the tasks Tools Required In general writing applications for an X3 module requires the development of host program This requires a development environment a debugger and a set of support libraries from Innovative Table 13 Development Tools Processor Development Environment Innovative Project Directory Toolset Host PC Borland Developers Studio Malibu Examples Snap Bcb Windows Microsoft Visual Studio 2008 Examples Snap VC9 Examples Snap Common Common Host Code Processor Development Environment Innovative Project Directory Toolset Host PC DialogBlocks Malibu Examples Snap WDialogBlocks Common Host Code Examples Snap Common On the host side the Malibu library is source code compatible with the above environments Th
25. clock distribution functions with a programmable VCXO This provides a clock generation range from 1 22 kHz to 280 MHz The useful range for the A Ds 18 limited to 144 kHz and to 192 kHz for the DACs X3 SD16 User s Manual 63 PLL REF SEL 100MHz 16 RIO Ext Clock Input P1 PXI DSTARA P16 VCXO 2 Port FPGA vreco PLL_CLKA_SEL AD 0 LVCMOS AD 1 LVCMOS DAC 0 LVCMOS DAC 1 LVCMOS FPGA FPGA FPGA Figure 1 X3 SD16 Clock Generation and Controls Block Diagram PLL reference is either a fixed 100 MHz reference clock or an external reference clock The output of the PLL is synchronous to the reference clock and the reference clock input or integer division of the reference determines the tuning resolution of the PLL To achieve an exact frequency that is not a division of the reference clock it is necessary to supply an external reference The PLL will generate an output synchronous to the external reference The sample clock for the front panel DIO is direct from the clock distribution circuitry and is NOT derived from the application logic clocks or PCI Express bus clock This is because these clocks have more jitter phase noise Note Conversion clocking is separate from triggering sample clock is the time when samples are digitized but trigger determines when those samples are kept External Clock and Reference Inputs The 3 5 16 has two external inputs that that may
26. data packets from the module For example it is often interesting when something happens to the unit under test such as a change in engine speed or completion of test stimulus X3 SD16 User s Manual 81 Using the X3 SD16 Where to start The best place to start with the X3 SD16 module is to install the module and use the SNAP example to acquire some data This program lets you log data from the module and use all the features like triggering clocks alerts and calibration ROM You can use this program to acquire some data and log it to disk This should let you verify that the module can acquire the data you want and give you a quick start on deciding what sample rates to use how to trigger the data acquisition best for your application and just get familiar with using the module The program also shows how to use BinView a data analysis and viewing program by Innovative that will let you see what you acquired in detail Both time domain and frequency domain data can be viewed and analyzed Data can also be exported to programs like Excel and MATLAB for further analysis Before you begin to write software taking a look at SNAP will allow you see everything working You can then look at the code for SNAP and modify it for your application or grab code from it that is useful A similar program for DAC outputs is provided call WAVE WAVE allows you to generate various waveforms on the host and play them out through the DAC channels DAC
27. enne nnne 21 uiii D nier t RR E CO EO I Or eI RR HG I Erga ds 22 Othet Softw te iioii esaet RH OH ER RD EPOR HU ET Er RE 22 Baseboard Package Installation nennen enne nennen enne 22 Board Packages mp 23 Unpacking the Package veg 23 Creating Symbolic Pn Cm 23 Completing the Board eene nennen tenente nnne 24 Lin x Directory Structure eee ette tmr eser iege ce fiere tete eere 24 ADpletsz iiem a Peces entres A 24 Docutiettatiolt s e LU UG 24 locnm MEE 24 Hardware iets td OR ue e edocet euch ve stems a Gah O eL E 24 About the X3 P 25 X3 Computing sou eS Nn ede etg UA DU RB ed 27 X3 SD16 User s Manual X3 PCIE PBXpress Interface n e ee EORR RS vens E REA NUS 29 Data B fferine and Memory uu pce ciere ERU US UDINE oe Ted GERE EARS 30 Gomp tational SRAM ine o RM BRIDE OR DR s
28. for conventional data playback applications In Framed mode triggers are rising edge sensitive Upon detection of each edge Trigger Frame Count samples are played from all active channels then playback terminates until the next trigger edge is detected If Trigger Auto is checked and the Trigger Source is software the X3 SD16 User s Manual 39 application automatically re triggers upon completion of processing of the previous packet This mode is ideal for application such as stimulus response etc Communications Group All X3 modules support data transfer between Host memory and the on board FPGA via a dedicated PCI Express bus interface Data is transferred in packets which consist of a two word header followed by a fixed length data buffer Header word zero contains the buffer length in bits 0 23 and a peripheral ID in bits 24 31 The Communications Pkt Size edit control specifies the size of the packets transferred between the target and the Host Each packet transferred results in a Host interrupt handled by the Malibu libraries Consequently larger packets amortize the Host interrupt processing more efficiently However packets are transferred using a contiguous page locked memory region of Host memory known as bus master memory which is allocated during installation via the ReserveMemDsp exe applet Windows Since bus master memory is Host memory it is limited in size by the amount of physical memory installed in the
29. i 2 Section2 StoreToRom Read from ROM Sectionl LoadFromRom for int i 0 i lt 50 i int x Sectionl AsInt i Section2 LoadFromRom for int i 50 i lt 100 i float x Section2 AsFloat i As delivered from the factory this EEPROM contains the calibration coefficients used for the A D error correction The serial EEPROM device is an Atmel AT24C16 or equivalent Caution the serial EEPROM contains the calibration coefficients for the analog and is preprogrammed at factory test Do not erase these coefficients or calibration will be lost Thermal Protection and Monitoring X3 modules have an on card temperature sensor that monitors the module and protects it from thermal damage The application software can monitor the module temperature and receive a warning if the temperature is above 70 C If the temperature exceeds 85C the module will shut down devices to prevent damage The temperature sensor is accurate to about 2 deg C with a resolution of 0 0625C Since it is mounted near the center of the card it indicates an average temperature not the maximum on the module Local hot spots may be 5 to 10 C hotter than the indicated reading The temperature sensor can be read by the host at address PCI BARO 0x3 The temperature is computed as Temperature C reading 0 0625 where the reading is a 12 bit signed number This table summarizes the relationship X3 SD16 User s Manual 36
30. markets Using our powerful data acquisition and DSP products allows you to incorporate leading edge technology into your system without the risk normally associated with advanced product development Your efforts are channeled into the area you know best your application Vocabulary X3 SD16 User s Manual 10 What is X3 SD16 The X3 module Family are XMC VITA 42 3 modules with a variety of IO capabilities and a PCI Express interface Each modules has a Spartan 3 application FPGA buffer memory and clocking features to support the IO functions Two SRAMs are used one each for buffer memory and application memory Then XMC has a 32 66 PCI interface to a single lane PCIe bridge chip DIO using P16 connection to the baseboard For sample rate generation the X3 SD16 has a precision low noise PLL or external clocks Trigger modes including software framed and external triggering provide precise control over sample acquisition and synchronization with other devices Timestamped alerts also provide the ability to monitor the acquisition process and correlate system events to the data Data acquisition control signal processing buffering and system interface functions are implemented in a Xilinx Spartan3A DSP FPGA 1 8 M gate device Two 512Kx32 memory devices are used for data buffering and FPGA computing memory The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset The MATLAB BSP supports real ti
31. on a Vista OS the dialog below may pop up In each case select Install this driver software anyway to continue gt Don t install this driver software You should check your manufacturer s website for updated driver software for your device Install this driver software anyway Only install driver software obtained from your manufacturer s website or disc Unsigned software from other sources may harm your computer or steal information See details Figure 1 Vista Verification Dialog X3 SD16 User s Manual 15 The Installer Program After launching Setup you will be presented with the following screen Please select product to install Innovative 3 Change Components to Install for Quadia Quadia Applets examples Docs and Pismo libraries Malibu Host libraries utilites Docs drivers amp DLLs Bin View Data graphing and analysis tool CodeHammer JTAG support for Code Composer Studio Innovative Components C Builder Support Product Registration ONE THEE Using this interface specify which product to install and where on your system to install it Figure 2 Innovative Install Program 1 Select the appropriate product from the Product Menu 2 Specify the path where the development package files are to be installed You may type a path or click Change to browse for or create a directory If left unchanged the install will use the default location of C
32. port can be configured for input or output on a byte wise basis as a function of the configuration code in Front Panel I O Config Mask See the Front Panel DIO Control Register description user logic offset 0x07 for details X3 SD16 User s Manual 40 Data Streaming Select the Stream tab The controls on this tab control data flow The meaning of each of the fields on this tab are explained below Data playback is initiated when the running man button is pressed and terminates when the Stop button is pressed Unframed mode or when an entire frame has played and trigger 15 not in re trigger mode framed mode To accommodate custom logic development the application supports execution of simple user authored scripts before and after the commencement of data flow Start Scripts Before edit box specifies the full path spec to a text file containing valid script commands described below which will be executed prior to data flow Similarly the Start Scripts After edit box specifies the file containing commands to be executed after data flow is underway The following script commands are supported 1 Store n to logic register address a n Fetch n from logic register address p na Storen to port register address p a n Fetch n from port register address ms n Delay n milliseconds commands use postfix notation so parameters go before the command For i
33. r Configuration 4 Total physical memory MB 255 Non paged pool size 4 Status k Update Help Exit Ready Binary File Viewer Utility BinView exe BinView is a data display tool specifically designed to allow simplified viewing of binary data stored in data files or a resident in shared DSP memory Please see the on line BinView help file in your Binview installation directory X3 SD16 User s Manual lt gt BinView c vista vistat 1 dump bin ac I4 4 b Pl Time Frequency Text Summary Server ini xl Z2BROG Q lt lt lt Zoom Out Zoomin gt gt gt 48 34 1 84 Counts e9 Sample E Amplitude vs Offset cho 10 20 30 40 50 60 70 80 90 100 Offset Leap 10 Span 100 ___ 5amples 4096 112
34. software in the SNAP example configures this pin to be digital lock detect It indicates when the PLL is locked and ready for use If the PLL lock 15 false the PLL is not working properly and may give poor results or inaccurate frequencies Even when the PLL is unable to lock it will produce an output so the mere presence of data does not indicate that the PLL is operating at the correct frequency or is stable The PLL lock can also generate an alert to the system if an unlock condition occurs In this mode when the PLL falls out of lock as indicated by a falling edge on the PLL status pin an alert message 1s created showing the time of the unlock and other system information See the Alert Log section for further information on using Alerts PLL lock is only valid for phase comparisons 25 MHz It is unreliable above this frequency X3 SD16 User s Manual 68 PLL Control Interface There are two AD9510 devices is mapped into the PCI Express memory space This allows the host to access the PLL control ports for configuration and status Writes to the PLL interface ports generate a serial data stream to the PLL that is used to configure the PLL U36 PLL clock divider BARI 0xA Table 6 Clock Device Address This interface is only for configuration accesses should be spaced by the host computer to be at least 2 ms apart The Malibu library handles this restriction as part of the function The PLL interface uses a 24 bit word to c
35. sub multiple for synchronization to work The system trigger must also be synchronous to the system clock to achieve simultaneous sampling It is not sufficient to simply drive the same signal to all cards since this may result in an indeterminate relationship to the clock The trigger must be synchronized to the clock If a clock reference is being used the trigger must be synchronous to the reference Sync Signal Sync is a bidirectional signal used to control the A D and D A timing The direction of sync is specified a software programmable register When the sync is designated as a master the sync signal is an output When designated as a slave the sync is an input The logic synchronizes sync to the sample clock Function Sync Master control master sync is OUTPUT from this card on trigger 1 0 slave sync is INPUT to this card on trigger 1 default Table 16 Sync Control Bit Register 0x1 X3 SD16 User s Manual 74 External Sync JP1 Pin Number Direction Slave input SYNC 34 Master output Table 17 Sync Signal The Sync signal is an LVTTL IO standard and has the following electrical characteristics Typical Maximum Logic High gt 14 3 6V Up to 5 5V if a 100 ohm series resistor is used Logic Low lt 0 7V 0 3V Input Impedance gt 1M ohm Table 18 Sync Signal Electrical Characteristics 64 channel System Example As an example a 64 chan
36. the Blink button to blink the LED on the board for the specified target It will continue blinking until you click Stop On OFF Use the On and Off buttons to activate or deactivate respectively the LED on the baseboard for the specified target When you exit the application the board s LED will remain in the state programmed by this applet fim Pmc Finder Target Number Set LED PEK X3 SD16 User s Manual 109 Logic Loader The logic loader applet is used to deliver known operational logic images to the user logic device installed on a X3 Servo The user logic must be loaded once per session as the logic part is cleared on bus reset or power up The utility may be used to configure the firmware either through its command line interface or from its GUI Windows user interface The former 15 often convenient during PC boot up to install a standard logic file Place a short cut with the command line option set into the Windows Startup folder to execute the program when the system is started This application supports configuration of the onboard Spartan 3 logic device from a bit file produced by popular logic design tools including Xilinx s It is essential that the Spartan 3 be programmed before using related applications since some of the baseboard peripherals are dependent on the personality of the configured logic Pmc Logic Loader DER Target b xj Exo File C lnnovativel
37. the desired sample rate The software configures the VCXO to the desired PLL frequency and then all PLL registers so that the output frequency 15 as close as possible to the required sample rate given the constraints of resolution as determined by the tuning parameters and the VCXO tuning range Note It is best to use the Malibu drivers for almost all applications and the following discussion is only for users who need to modify the PLL tuning for very unique applications The tuning equation for the AD9510 is Fvcxo Fret R x PB A where Fref 100 MHz or external reference frequency 1 to 16383 integers B 3 to 8191 integers 1 bypass A 0 to 63 integers used only in dual modulus mode P 1 2 3 4 8 16 or 32 and 10 MHz lt FVCXO lt 280 MHz All PLL tuning parameters R B A and P are software programmable through the PLL interface Step 1 Pick a phase detector frequency close to 100 kHz This Fphase detector gt 100kHz matches the PLL configuration on the card 2 Calculate a reference divisor so that the phase detector Fphase detector Fref R 100kHz frequency is close to 100kHz R 1 to 16383 100 kHz lt Fref lt 250 MHz 1000 for on board reference 3 For an output sample clock Fout find the output FVCXO Fout D divisor D that keeps the VCXO within its tuning range D 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 20 or 32 100 MHz x FVCXO x 140 MHz 4 Find PLL feedback divisor
38. tn tbe tute E Dt etc oe ess 54 AID CONVETTETS 2 ede ntt ere tet D d td DER te aor eb ee EUR re RR pt es Ere 54 Input Range and Conversion Codes tite tete ener E eR EI RE UNT 56 Driving the A D Ifnp ts ee ERO S E ERFURT OE NR ee CR e te t 57 AJD Filtet Characteristics re o aq t e etie en extant ise 57 Overtange Detect Oni OO S YER NEN INE SG 58 A D Sampling nite CER RE ec de RYE NU ER NISUS OSEE ees 58 D A Conversion Features senerara i e ai ota D TECH DE Fe Ee ere deerat 59 DA 59 Qutput Range and Conversion Codes t Re RD RS RE URB Id eR 60 DAC Outputs ce m 61 DAC Sample Underr i o EIOS RR RR RR CI RT EE E edt 61 DAG Update Rates Y EP NES ERE GE E OAE TCU USD RD Ee uds 62 Notes About Matching the A D and D A Data Rates essen ennemi inneren 63 Sample Rate Generation and Clocking Controls eese eene enne 63 External Clock and Reference Inputs 3 tee eed Ie T E e Ute Hee HERI re E N LT dees 64 PLL Output Range and Resolution Limitations sesessessssesseeeeeeeneeneneenne nennen nnne nnne erret 66 Programming the PLE and VCXO snc eie tva ip ie e erede dete Un ee GREG odas es 66 PLE Lock and
39. to communicate with the host computer while the Command Channel is a command and control interface from the host computer to the application logic The SelectMAP interface is the application FPGA configuration port for loading the logic image The data link is the primary data path for the data communications between the application FPGA and host computer When data packets are created by the application logic such as A D samples or required by the application logic for output devices such as DAC channels the data flows over the data link as packets The maximum transfer rate over the data link is 264 MB s with a 220 MB s sustained rate The data packets contain a Peripheral Device Number PDN that identifies the peripheral associated with the this data packet In this way the packet system is extensible to other devices that may be added to the logic For example an FFT analysis can be added to the logic and its result sent to the host as a new PDN for display and further analysis while maintaining other data streams from A D channels Table 5 Interfaces from PCI Express to Application Logic Application Logic Max Data Rate Typical Use Interface Data Link 264 MB s burst 240 MB s sustained Velocia packet system interface main path for data communications Command Channel 5 MB s sustained Command control and status SelectMAP 5 MB s Application logic configuration Data Buffering and Memory Use There are
40. trigger is true in continuous mode after a rising edge on the trigger input software or external until a falling edge is found The trigger is timed against the sample clock and may have a 0 to 1 sample uncertainty for an asynchronous trigger input The trigger control on the X3 SD16 module always ensures that a complete set of samples for the time period are acquired no matter when the trigger is de asserted This means that for an unsynchronized trigger input such as an external device you will always get samples for all enabled channels no matter when trigger is enabled or disabled DAC updates are identical in functionality to the A D sampling A D and DAC samples are always synchronous DAC updates occur only when the trigger 15 true on rising edges of the sample clock X3 SD16 User s Manual 72 The Malibu software tools provide trigger source configuration and methods for software triggering re triggering in framed mode and trigger mode controls Trigger Source A software trigger or external trigger can be used by the trigger controls Software trigger can always be used but external triggering must be selected This prevents spurious triggers from noise on external inputs The trigger source is level sensitive for the continuous mode or edge triggered for the framed mode triggering External Trigger JP1 Pin Number TRIGGER 68 Table 14 External Trigger Input External trigger is an LVTTL input and has th
41. wise basis as a function of the configuration code in Digital I O Config Mask See the DIO Control Register description user logic offset 0x14 for details Front Panel I O Group These controls govern the configuration of the Front Panel DIO port on the module The DIO port can be configured for input or output on a byte wise basis as a function of the configuration code in Front Panel I O Config Mask See the Front Panel DIO Control Register description user logic offset 0x07 for details Data Logging Group These controls govern the size of data files created by the application containing packet data received from the module during real time streaming The value of Data Logging Samples sets the upper bound on the number of stored events samples from each channel If the Data Logging Auto Stop checkbox is checked streaming will automatically terminate once the specified number of events have been collected and logged to disk Test Counter Group Use this control to enable a logic specific test mode if you are developing custom FPGA logic If you are using the stock factory supplied logic bit zero of the Test Register user logic offset 0x02 is controlled by Test Counter Enable which forces an incremental ramp to replace A D data from each channel Decimation Group These controls govern the behavior enable the decimation logic When enabled only one of every Nth sample of acquired data is retained within the internal on board FIFOs
42. 0 1 0 2 0 5 1 5 9 9 S N 10V RangSFDR 10V 10V Ra THD 10V db 45 2 51 3 59 3 66 80 2 86 dB 64 6 68 77 84 9 99 3 104 bits 7 2 82 9 5 10 6 13 14 dB 80 9 82 4 91 8 99 4 114 8 120 4 Table 27 A D Signal Quality for 10V Input Range 4V Range Vin Vp p 0 1 0 2 0 5 1 SIN 4V Range db 59 1 62 6 73 3 79 9 SFDR 4V Range dB 71 5 74 2 85 5 91 5 ENOB 4 V Range bits 9 5 10 1 11 8 12 9 THD 4V Range dB 94 96 6 102 8 113 3 Table 28 A D Signal Quality for 2V Input Range X3 SD16 User s Manual 90 S N vs Input Amplitude 100 90 80 n FA 60 ji S N 20V Range dd V SIN 4V 20 Range 10 S N 10V 0 Range 0 10205 1 5 99 12 15 19 9 Vin Figure 12 A D SNR vs Input Amplitude Fs 144 ksps Vin 1 01 kHz sine SFDR vs Input Amplitude 120 100 80 m 60 SFDR 20V 40 Range SFDR 10V 20 Range V SFDR 4V 0 Range 0 10205 1 5 99 12 15 19 9 Vin Figure 13 A D SFDR vs Input Amplitude Fs 144 ksps Vin 1 01 kHz sine ENOB vs Input Amplitude 16 14 12 10 2 8 a ENOB 20V 6 Range 4 ENOB 10V Range 2 V ENOB 4 V Range 0 9 01 0205 1 5 99 12 15 19 9 Vin Figure 14 A D ENOB vs Input Amplitude Fs 144 ksps Vin 1 01 kHz sine THD vs Input Amplitude 70 80 90 100 THD 20V 110 Range THD 10V nge 120 THD 4V Range
43. 05 in pin spacing vertical mount 114 arranged as 6 rows of 19 pins each Samtec ASP 105885 01 Samtec ASP 105884 01 ABCDEF Figure 18 P15 XMC Connector Orientation X3 SD16 User s Manual 98 Column Row A B C D E 1 PETOpO PETOnO 3 3 VPWR 2 GND GND GND GND MRSTI 3 3 3V VPWR 4 GND GND GND GND MRSTO 5 3 3V VPWR 6 GND GND GND GND 12V 7 3 3V VPWR 8 GND GND GND GND 12V 9 GAO 10 GND GND GND GND VPWR 11 EROpO PEROnO MBIST MPRESENT 12 GND GND GND GND VPWR 13 3 3VAUX MSDA 14 GND GND GA2 GND GND VPWR 15 MSCL 16 GND GND MVMRO GND GND 17 18 GND GND GND GND 19 PEX REFCLK PEX REFCLK WAKE ROOT Table 30 X3 XMC Connector P15 Pinout Note All unlabeled pins are not used by X3 modules but may defined in VITA42 and VITA42 3 specifications X3 SD16 User s Manual 99 Table 31 P15 Signal Descriptions Signal Description P15 Pin PETOp0 PETOn0 PCI Express Tx Al B1 PEROp0 PEROn0 PCI Express Rx 11 11 PEX REFCLK PCI Express reference clock 100 MHz A19 B19 MRSTI Master Reset Input active low F2 MRSTO Master Reset Output active low F4 GAO G
44. 130 8 010205 1 5 99 12 15 199 Vin Figure 15 A D THD vs Input Amplitude Fs 144 ksps Vin 1 01 kHz sine X3 SD16 User s Manual 91 Analog Output A summary of the analog output performance follows for the X3 SD16 module tests performed at room temperature with the module at approximately 30C using force air cooling Test environment was PCIe adapter card in PC running testbed software using FrameWork Logic Table 29 X3 SD16 Analog Output Performance Summary X3 SD16 User s Manual 92 Parameter Measured Units Test Conditions Bandwidth 0 4 dB 0 to 90 kHz 3 9Vp p Output Range 4 0 2 Vp p Standard on X3 SD106 calibration results may limit input range to 9596 differential of full scale nominal Offset 0 5 mV Factory calibration average of 64K samples Gain 0 02 Factory calibration average of 64K samples Ground Noise 622 uVp p Output commanded to update rate 128 ksps Ground Noise 110 dB Output commanded to update rate 128 ksps 0 to 64kHz span At limit of measurement SFDR 95 6 dB 1 01 kHz sine input 2Vp p 128 ksps update rate 64K point FFT S N 80 3 dB 1 01 kHz sine input 2Vp p 128 ksps update rate 64K point FFT THD 95 8 dB 1 01 kHz sine input 2Vp p 128 ksps update rate 64K point FFT ENOB 12 8 bits 1 01 kHz sine input 2Vp p 128 ksps update rate 64K point FFT Crosstalk 100 dB 1 kHz 19Vp p sine on activ
45. 3 121 5 50 87 7 103 6 14 3 125 6 100 86 5 102 9 14 118 144 86 104 14 120 4 Table 25 A D Signal Quality vs Sample Rate X3 SD16 User s Manual S N vs Sample Rate 91 90 89 88 87 dB S N 86 85 84 83 10 20 50 100 Sample Rate kHz 144 Figure 8 A D SNR vs Input Amplitude Vin 19 9Vp p 1 01 kHz sine ENOB vs Sample Rate 14 8 14 6 14 4 14 2 bits ENOB 13 8 13 6 10 20 50 100 Sample Rate kHz 144 Figure 9 A D ENOB vs Sample Rate Vin 19 9Vp p 1 01 kHz sine SFDR vs Sample Rate 109 108 107 106 105 104 103 102 101 100 99 dB SFDR 10 20 50 100 Sample Rate kHz 144 Figure 10 A D SFDR vs Sample Rate Vin 19 9Vp p 1 01 sine THD vs Sample Rate 112 114 116 118 m 120 122 124 126 128 10 20 50 100 144 Sample Rate kHz Figure 11 A D THD vs Sample Rate Vin 19 9Vp p 1 01 kHz sine X3 SD16 User s Manual 89 20V Range Vin Vp p 0 1 0 2 0 5 1 5 9 9 12 15 19 9 S N 20V Range db 40 3 46 2 54 8 61 75 4 80 4 82 1 84 2 87 2 SFDR 20V Range dB 59 9 66 5 77 2 83 3 96 7 101 102 1 105 5 105 2 ENOB 20V Range bits 6 4 7 4 8 8 9 8 12 2 13 13 3 13 7 14 2 THD 20V Range dB 72 7 78 8 88 5 91 6 108 2 114 9 118 9 117 3 116 7 Table 26 A D Signal Quality for 20V Input Range 10V Range Vin Vp p
46. 3 SD16 User s Manual 11 What kinds of applications are possible with Innovative Integration hardware Data acquisition data logging stimulus response and signal processing jobs are easily solved with Innovative Integration baseboards using the Malibu software There are a wide selection of peripheral devices available in the Matador DSP product family for all types of signals from DC to RF frequency applications video or audio processing Additionally multiple Innovative Integration baseboards can be used for a large channel or mixed requirement systems and data acquisition cards from Innovative can be integrated with Innovative s other DSP or data acquisition baseboards for high performance signal processing Why do I need to use Malibu with my Baseboard One of the biggest issues in using the personal computer for data collection control and communications applications is the relatively poor real time performance associated with the system Despite the high computational power of the PC it cannot reliably respond to real time events at rates much faster than a few hundred hertz The PC is really best at processing data not collecting it In fact most modern operating systems like Windows are simply not focused on real time performance but rather on ease of use and convenience Word processing and spreadsheets are simply not high performance real time tasks The solution to this problem is to provide specialized hardware assistance respon
47. 31 ERA R EER 31 cuca oui 31 R a a 32 Software Support isei de ee EA EAE E EE EG EE E Ea a Ea RE EN 32 Hardware Implementation eeir e EER ene asd i EEEE EE Uo dede 32 Digital VO Timing serie e HO RE T ERROR GE Se ROPA TALI GRE ERE TRUE ERREUR S 33 Digital IO Electrical Characteristics 5 5 2 aceite are ER end etd Ee EE GAME 34 Notes on Digital IO Use iscing ean e HERREN e RETE SERI 35 Serial EEPROM Intetrface esie ena don iie n ear m E Pe E M ERG PERRA 35 Thermal Protection and Monitoring sete ede eR RR Ee e GERE Redde 36 Fatl res Denm e ete vu depu a D oe dla e turpis nie Deseo td eei ce 38 TED lated E 39 JTAG Sati Path 39 BFrameWork Doglc 1 tage eta oue omen dde NIB nee Rd ee 40 Integrating with Host Cards and Systems sse enne nennen nnne 40 Developing Host Yd ciDI e SR Borland Turbo L M
48. AC 1 LVCMOS FPGA 4 FPGA FPGA Figure 1 X3 SD16 External Clock Path The selection of the PLL reference clock is also software programmable The reference clock multiplexer selects the PLL reference clock as either the 100 MHz oscillator or the PXI 100M input on P16 The control signal REF SEL is from the application logic FPGA and is set by the host software when the standard logic image is used external clock and reference inputs are LVDS and must be driven as a differential pair Each differential pair 1s 100 ohm terminated The LVDS inputs cannot be driven single ended both inputs must be actively driven Electrical characteristics of the inputs are shown in the following table X3 SD16 User s Manual 65 Parameter Min Typical Max Input Termination 100 ohms Table 1 X3 External Clock and Reference Input Requirements The external clock and reference inputs are from either the front panel connector JP1 or XMC secondary connector P16 To use the P16 connector inputs the carrier card must support the P16 pinout shown later in this chapter Here 1s where the external clock inputs are connected External Clock ext clk MDR6S front panel connector PXI DSTARA P16 a9 89 secondary connector PXIE 100M P16 D9 E9 J XMC secondary connector Table 2 External Clock and Reference Signal Pinouts PLL Output Range and Resolution Limitations The sample rates that can be generated
49. D16 is supported by the FrameWork Logic system from Innovative using VHDL and or MATLAB Simulink Signal processing data analysis and application specific algorithms may be developed for use in the X3 SD16 logic and integrated with the hardware using the FrameWork Logic Software support for the module includes host integration support including device drivers XMC control and data flow and support applets X3 SD16 User s Manual 53 X3 SD16 Block Diagram Ext CIk Ref J18 Ext J18 Ext Ref Figure 12 X3 SD16 Block Diagram A D Conversion Features A D Converters The X3 SD16 has 16 channels of 24 bit A D sampling at up to 144 kHz using Texas Instruments ADS1278 A Ds There are two ADS1278 devices on the card eight A D channels per device The inputs are not multiplexed and all 16 channels sample X3 SD16 User s Manual 54 simultaneously The ADS1278 is a sigma delta converter SD that has a sample rate at 128 or 256 the output data rate and digital filter in the device for out of band signal rejection and noise shaping As 15 typical of SD converters the device has a latency that is inherent in its sampling techniques corresponding to several samples Feature Description Inputs 16 independent Input Ranges 20V 10V 4V Programmable Input Impedance 20K ohm 15 pF excludes cable Maximum input voltage do not exceed or 20V damage may occur Anti alias filtering Single pole at 200 kHz
50. IVE Malibu I INNOVATIVE Malibu LinuxSupport A UTO Paths INNOVATIVE usr Innovative WINDRIVER usr Innovative WinDriver WXWIN usr wxWidgets 2 8 7 provided that this is the location where you have installed wx Widgets Summary Developing Host and target applications utilizing Innovative DSP products is straightforward when armed with the appropriate development tools and information X3 SD16 User s Manual 19 Writing Custom Acquisition Applications Most scientific and engineering applications require the acquisition and storage of data for analysis after the fact Even in cases where most data analysis is done in place there is usually a requirement that some data be saved to monitor the system In many cases a pure data that does no immediate processing is the most common application A logger that saves all data to disk file is feasible at modest data rates A dedicated RAIDO drive array partitioned as NTFS for data storage may be required if data rates approximate 80MBytes sec Snap Example The Snap example in the software distribution demonstrates such functionality It consists of a host program in Windows or Linux which simultaneously works with user defined interface logic It uses the Innovative Malibu software libraries to accomplish the tasks Tools Required In general writing applications for an X3 module requires the development of host program This requires a development environment a debugge
51. In the MalibuRed KerPlug directory there is a script called quicklink quicklink X5 400 1 1 These commands will create a symbolic link x5 400 pointing to X5 400 1 1 This script can be moved to the user s bin directory to allow it to be run from any directory X3 SD16 User s Manual 23 Completing the Board Install The normal board install is complete with the installation of the files The board driver install is already complete with the loading of the Malibu Red package If there are any board specific steps they will be listed at the end of this chapter Linux Directory Structure When a board package is installed its files are placed under the usr Innovative folder The base directory is named after the board with a version number attached for example the version 2 0 X5 400 RPM extracts into usr Innovative X5 400 2 0 This allows multiple version of installs to coexist by using a symbolic link to point to particular version Changing the symbolic link changes with version will be used Under the main directory there are a number of subdirectories Applets The applets subdirectory contains small application programs that aid in the use of the board For example there is a Finder program that allows the user to flash an LED on the board to determine which board is associated with a target number See the Applets chapter for a fuller description of the applets for a board Documentation This directory contains a
52. Innovative Integration X3 SD16 User s Manual X3 SD16 User s Manual The X3 SD16 User s Manual was prepared by the technical staff of Innovative Integration on June 16 2010 For further assistance contact Innovative Integration 2390 A Ward Ave Simi Valley California 93065 PH 805 578 4260 FAX 805 578 4225 email techsprt innovative dsp com Website www innovative dsp com This document is copyright 2010 by Innovative Integration All rights are reserved VSS Distributions 1 8016 Documentation Manual V SD16Master odm Rev 1 0 Table of Contents X3 SD16 gt User s Manual steve ves eetes geeo quse Dues Veusssa vales T pego ke dues 59 OU lO Real Lime Solutions uis reb tete e tt eo get qu ete ete po dee e ette Ea 10 EE 10 WohatiseXS SDL6 Lm 11 Wliatas Malibu ert iie tbe toe 11 Whatis Ctt Butlder 2 iet 11 Whatas MiCroSo1t MS V C oe ote IO eter tete ee eite GUUS adres 11 What kinds of applications are possible with Innovative Integration hardware sese 12 Why do I need to use Malibu with my Baseboard essen ener nnne nns 12 Finding detailed informa
53. LAB Simulink tools operate over the FPGA JTAG during development at a low rate it is necessary to use the SRAM for real time high speed data buffering The MATLAB Simulink library for the X3 modules demonstrate the use of the SRAM as a data capture buffer The SRAM captures real time high speed data that can then be read out into MATLAB for analysis or display as a snapshot This allows high speed real time to be captured and brought into MATLAB Simulink over the slow 10Mb sec link See the X3 FrameWork Logic User Guide for more details and examples Data Buffer SRAM The second SRAM is provides a 2MB memory pool local to the FPGA The Framework Logic implements a data buffer with one or more queues for the A D and D A streams as appropriate for the particular X3 module In the Framework logic the SRAM use is demonstrated as a multiple queue FIFO memory that divides the 2 MB memory buffer into separate queues virtual FIFOs for input and output The logic component referred to as Multi Queue SRAM controls the SRAM to create the FIFO queue functionality Custom logic applications can use the Multi Queue SRAM buffer component to add additional queues for new devices EEPROM A serial EEPROM on the X3 modules is used to store configuration and calibration information The interface to the serial EEPROM is an I2C bus that is controlled by the PCI logic device The device is an Atmel AT24C16 10SI a 16K bit device The I2C bus is slow and t
54. Manual 31 Packets scaled in units of events samples per each enabled channel int SamplesPerWord 1 Module ReturnPacketSize Settings PacketSize ActiveChannels SamplesPerWord 2 The size of the data packets sent from the module to the Host during streaming is programmable This is helpful during framed acquisition since the packet size can be tailored to match a multiple of the frame size providing application notification on each acquired frame In other applications such as when an FFT is embedded within the FPGA the packet size can be programmed to match the processing block size from the algorithm within the FPGA Start Loggers on active channels if Settings PlotEnable Graph Quit if Settings LoggerEnable Settings PlotEnable Logger Start BlocksToLog Settings SamplesToLog Settings PacketSize Settings SamplesToLog Settings PacketSize 1 0 Stopped false The example illustrates logging data to a disk file with post viewing of the acquired data using BinView The code fragment above closes any pending instance of BinView and logger data files BinView will not display data under Linux Module Dio DioPortConfig Settings DioConfig Module FrontPanel FrontPanelPortConfig Settings FrontPanelConfig The module supports programmable bit I O available on connector JP16 and on the Front Panel connector The code fragment above programs the direction of these DIO bits in accordance w
55. Range 2V Nominal Conversion Code hex 24 bit 2 s complement Differential Input Voltage 20V 10V 1V Ox7FFFFF 10V 5V 0 5V 0x400000 OV OV OV 0x000000 10V 5V 0 5V 0xA00000 20V 10V 1V 0x800000 Table 15 A D Conversion Coding X3 SD16 User s Manual 56 Driving the A D Inputs The X3 SD16 has fully differential inputs with 20K ohms input impedance The input range is specified as a differential voltage for the V and V input with a common mode voltage of for full range A full scale input is 10Vp p complementary wave on EACH of the inputs for a gain of 1 The input signals should be driven differentially to realize the full performance of the A D The differential inputs reject common mode noise from the system and the card itself to improve the conversion results If you drive the inputs single ended the results will be worse by at least 6dB in most cases worse if the system noise is high For signal ended use the unused input must be grounded Input voltage range is limited to 10V to 10V for single ended use for the standard configuration This means that single ended inputs sacrifice half of the available dynamic range The input signal must be able to drive a 20K ohm load This is the input resistance of the X3 SD16 Unused inputs should be grounded when the MDR68 cable is used to minimize crosstalk and noise pickup A D Filter Characteristics The A D channels have an anti alias filter to suppress hi
56. SPS or 16 bit 20 MSPS 2M option acoustics wide dynamic 7100 dB below 2 5 MSPS range applications X3 25M Two channels of 25 MSPS 16 bit A D and Xilinx Spartan3A DSP 1 8M Ultrasound pulse digitizing two channels of 16 bit 50 MSPS DAC 16 waveform generation and bits front panel DIO stimulus response X3 A4D4 4 channels of 16 bit 4 MSPS A D and 4 Xilinx Spartan3A DSP 1 8M Servo controls process channels 16 bit 2 MHz DAC with low instrumentation latency 8 bits front panel DIO X3 Servo 12 channels 16 bit 250 ksps A D and 12 Xilinx Spartan3A DSP 1 8M Electromechanical controls channels 16 bit 250 ksps DAC low 3 4M option process instrumentation latency 16 bits front panel DIO X3 DIO 64 bits 32 pairs digital IO to FPGA Xilinx Spartan3A DSP 1 8M Test pattern generation LVCMOS or LVDS with streaming 3 4M option remote IO interfaces digital playback and capture features controls X3 10M 8 channels of 16 bit 25 MSPS A D with Xilinx Spartan3A DSP 1 8 Measurement for high speed programmable gain and instrumentation vibration ultrasound fault front end Xilinx Spartan3A DSP FPGA detection systems neurophysical applications X3 2M 12 channels of 16 bit 10 MSPS A D with Xilinx Spartan3A DSP 1 8M Multi channel applications in programmable gain and instrumentation ultrasound video sensors and front end Xilinx Spartan3A DSP FPGA optical sensors X3 SD16 16 channels of 24 bit 144 kHz A D and Xilinx Spartan3A DSP 1 8M Vibra
57. T peer ere er uev 34 guum 35 Writing Custom Playback 8 1 seo sssse sese sse ssssee d 7 Mave Example sanete ette etre RO dut p Pm ee Ede RE ERR 37 Tools Requitedz eerte me betae ete ere ee It res 37 Program DSi On xo ntes tet abet e See ee EIS 38 The Host Application s E druide dS 38 User Interface rca ee reote eet e e rece e REOR Hh 38 X3 SD16 User s Manual Setup une RR S RENI B EE WISI NEU 39 Data Streaming nU EO aede aere eei ene nU 41 ER 41 DCD 42 Host Side Program Organizations so cet rhe ID PSI HN H e HUS 42 ApplicationlIo I va NGA TE GR TEN T t EUREN EE rg 42 Initializationzzs uuo E RERUH HEU GER ea i eb RE OU ERE 42 Logic Loading nisu UPRIGHT I TREE EN ITE er Ese SaS 45 Handle Data Required tiet ie GR PRI tet hoes Ue E EAM teet te eo eue e dove Uude 50 EEPtOtnACC6SS oou nep E E ae erar cp E Hadr 51 K3 SD16 Hard ri c Introduction ennonn ce terme ttc acts pedi cst es dfc cet osea credet ch toni s A ee 53 AJD Convetsion Eeatutes eene p n ee
58. TARA PXI DSTARA PXIE 100 PXIE 100M 10 DGND DGND DIO9 DGND DGND DIO28 PXIE_SYNC100 11 B DIO10 DIO29 PXIE_SYNC100 12 DGND DGND DIO11 DGND DGND DIO30 13 2 01012 5 DIO31 14 DGND DGND DIO13 DGND DGND DIO32 15 2 01014 6 DIO33 16 DGND DGND DIO15 DGND DGND DIO34 17 01016 01035 PXI 10M 18 DGND DGND DIO17 DGND DGND DIO36 PXI LBL6 19 DIO42 DIO43 DIO18 DIO_CLK DIO CLK PXI DIO37 PXIE DSTARB PXIE DSTARB PXI DSTARC 5 PXI LBR 6 Note all unused pins are not labeled X3 SD16 User s Manual 102 Table 33 P16 Signal Descriptions Signal Description P16 Pin DIO0 PXI TRIGO Digital IO 0 PXIE trigger 0 DIO PXI TRIGI Digital IO 1 PXIE trigger 1 C2 DIO2 PXI TRIG2 Digital IO 2 PXIE trigger 2 C3 DIO3 PXI TRIG3 Digital IO 3 PXIE trigger 3 C4 DIO4 PXI TRIG4 Digital IO 4 PXIE trigger 4 C5 DIOS5 PXI TRIGS Digital IO 5 PXIE trigger 5 C6 DIO6 PXI TRIG6 Digital IO 6 PXIE trigger 6 C7 DIO7 PXI TRIG7 Digital IO 7 PXIE trigger 7 C8 DIO8 PXI STAR Digital IO 8 PXIE star trigger C9 DIO9 PXIE_SYNC100 Digital IO 9 PXIE sync 100 C10 DIO10 PXIE SYNCIO0O Digital IO 10 PXIE sync 100 Cll Digital IO 11 C2 DIO12 Digital IO 12 C13 DIO13 Digital IO 13 C14 DIO14 Digital IO 14 C15 DIOI5 Digital IO 15 C16 DIO16 Digital IO 16 C17 DIO17 Digital IO 17 C18 DIO18 Digital IO 18 C19
59. X3 SD Hardware Images x3_sd_v3 bit ES Event Log baseboards enumerated HW Variant HW Rev Type X3 SD16 User s Manual 110 Applets The software release for a baseboard contains programs in addition to the example projects These are collectively called applets They provide a variety of services ranging from post analysis of acquired data to loading programs and logic to a full replacement host user interface The applets provided with this release are described in this chapter Shortcuts to these utilities are installed in Windows by the installation To invoke any of these utilities go to the Start Menu Programs Baseboard Name and double click the shortcut for the program you are interested in running Common Applets Registration Utility NewUser exe Some of the Host applets provided in the Developers Package are keyed to allow Innovative to obtain end user contact information These utilities allow unrestricted use during a 20 day trial period after which you are required to register your package with Innovative After the trial period operation will be disallowed until the unlock code provided as part of the registration is entered into the applet After using the NewUser exe applet to provide Innovative Integration with your registration information you will receive The unlock code necessary for unrestricted use of the Host applets A WSC tech support service code enabling fre
60. a method where functions can be plugged into the library to be called at certain times in response to certain events detected Events allow a tight integration between an application and the library These events are informational messages issued by the scripting and logic loader feature of the module They display feedback during the loading of the user logic and when script is used Alerts Module Alerts OnTimeStampRolloverAlert SetEvent this amp ApplicationIo HandleTimestampRolloverAlert Module Alerts OnSoftwareAlert SetEvent this amp ApplicationIo HandleSoftwareAlert Module Alerts OnWarningTemperature SetEvent this amp Applicationlo HandleWarningTempAlert Module Alerts OnPllLost SetEvent this amp ApplicationIlo HandlePllLostAlert Module Alerts OnInputFifoOverrun SetEvent this amp ApplicationIo HandleInputFifoOverrunAlert Module Alerts OnInputTrigger SetEvent this amp Applicationlo HandleInputTriggerAlert Module Alerts OnInputOverrange SetEvent this amp ApplicationIo HandleInputFifoOverrangeAlert This code attaches alert processing event handlers to their corresponding events Alerts are packets that the module generates and sends to the Host as packets containing out of band information concerning the state of the module For instance if the analog inputs were subjected to an input over range an alert packet would be sent to the Host interspersed into the data stream indicatin
61. a packet is delivered by the data streaming system OnDataRequired event will be issued to supply more data This event is set to be handled by HandleDataRequired Configure Stream Event Handlers Stream OnDataRequired SetEvent this amp ApplicationIo HandleDataRequired In this example a Malibu SoftwareTimer object has been added to the Applicationlo class to provide periodic status updates to the user interface The handler below serves this purpose Timer OnElapsed SetEvent this amp ApplicationIo HandleTimer Timer OnElapsed Thunk An event is not necessarily called in the same thread as the UI If it is not and if you want to call a UI function in the handler you have to have the event synchronized with the UI thread The call to Synchronize directs the event to call the event handler in the main UI thread context This results in a slight performance penalty but allows us to call UI methods in the event handler freely Creating a hardware object does not attach it to the hardware The object has to be explicitly opened The Open method open hardware Open Devices Module Target Settings Target Module Open Module Reset UI gt Status Module Device Opened Opened true This code shows how to open the device for streaming Each baseboard has a unique code given in a PC For instance if there are three boards in a system they will be targets 0 1 and 2 The order of the targets is determine
62. and 1 1 kHz sine 2Vp p each differential input Analog Input Frequency Response 0 ED SSS 2 4 6 8 10 12 14 16 18 20 1 2 1E 3 1 4 2 1 5 1 6 Figure 5 Analog Input Bandwidth 0 to 1 MHz sample rate 144 KHz 6000 5000 4000 3000 2000 1000 ina mV 1000 2000 3000 4000 5000 m 6000 Wa EXT See E as ipn aj 0 pg 10Vp p square wave sample rate 144 KHz 90 91 92 93 94 95 96 97 98 299 100 101 102 103 Figure 6 Analog input settling time for 1 01 kHz X3 SD16 User s Manual 87 BinView c projects x3 sd1 6 hardware reva qual data adc single toneldata2 bdd HEBA CO 9 Q Time Frequency Text Summary Server 17 32 Magnitude vs Frequency 0 g 20 SFDR 103 dB S N 85 9 dB 40 ENOB 14 0 bits 60 THD 119 9dB 64K pt FFT a 80 E Signal source noise S 100 ale 120 cM gt 140 160 180 10 101 109 10 10 KHz 1 Mat 98 ome SINAD dB ENS Sron 8 ETT jum Sample 562172 Leap 4096 hO Frequency domain data display Samples 1004010 Figure 7 Signal quality measurement 1 01 kHz input 19 9 Vp p sample rate 144 ksps 64K FFT no averaging Fs SIN SFDR ENOB THD kHz dB dB bits dB 10 90 2 107 6 14 7 126 5 20 88 3 102 3 14
63. arted The Stream Start command applies all of the above configuration settings to the module then enables PCI data flow However samples will not be acquired until the module is triggered ActualSampleRate static cast float Module Clock FrequencyActual std stringstream msg msg precision 6 msg Actual sampling rate ActualSampleRate 1 e3 KHz UI gt Log msg str FTicks 0 Timer Enabled true X3 SD16 User s Manual 33 Handle Data Available Once streaming 15 enabled and the module is triggered data flow will commence Samples will be accumulated into the onboard FIFO then they are bus mastered to the Host PC into page locked driver allocated memory following a two word header data packets Upon receipt of a data packet Malibu signals the Stream OnDataAvailable even By hooking this event your application can perform processing on each acquired packet Note however that this event is signaled from within a background thread so you must not perform non reentrant OS system calls such as GUI updates from within your handler unless you marshal said processing into the foreground thread context void ApplicationIo HandleDataAvailable PacketStreamDataEvent amp Event if Stopped return Static Buffer Packet Extract the packet from the Incoming Queue Event Sender gt Recv Packet IntegerDG Packet DG Packet When the event is signaled the data buffer mu
64. ary to clean them up if you want to test the X3 SD106 X3 SD16 User s Manual 82 Application Logic The application logic must be loaded after every system boot up or reset There is no on card storage for the logic image The logic can be loaded using the LogicLoad software applet or is loaded as part of the application itself such as SNAP If you write your own application you will need to either use LogicLoad or incorporate a logic loader in the application The code in SNAP is a good example of how to do this Logic loading takes about 5 10 seconds using the PCIe interface Calibration Every A D and DAC sample is error corrected on the X3 SD16 module in real time by the application FPGA This error correction is done as the samples flow through the FPGA and is done digitally This results in improved performance and reliability for the module because the error correction does not change over time or temperature The basic error terms for offset and scale factor are corrected by the logic This is a first order error correction where y mx b wherein x the input sample m gain correction and b offset correction The resultant samples are the error corrected output samples Trim range is about 1 5 for gain and 10 for offset Production Calibration Each X3 SD16 is calibrated as part of the production tests performed The calibration results are provided on the production test report with each module The results of the calibratio
65. ata flows from the PCI Express interface into the DAC data buffer and then into the DAC interface In the DAC interface the samples are modified to correct to analog gain and offset errors then converted to straight binary for the DAC device The Board Basics and Host Communications chapters of this manual discuss the use of the packet data system used on the X3 module family The X3 SD16 module FrameWork Logic connects the data from A D interface to the packet system by forming the 24 bit data into 32 bit words of consecutive enabled channels channels 0 1 etc Status indicators for the A Ds are integrated with the alert log to provide host notifications of important events for monitoring the data acquisition process some of which are unique to the X3 SD16 DAC data is also delivered as 32 bit words by the host then dissembled into channel data on the X3 SD16 The data sequence is ordered consecutively for the enabled channels channels 0 1 etc The complete description of the FrameWork Logic is provided in the FrameWork Logic User Guide including the memory mapping register definitions and functional behavior This logic is about 25 of the available logic in the application FPGA 1 8M gate device In many custom applications unused logic functions can be deleted to free up gates for the new application X3 SD16 User s Manual 77 Power Controls and Thermal Design The X3 SD16 module has temperature monitoring and power controls to ai
66. be used as sample clock plus two external inputs that may be used as the PLL reference clock The two external input clocks Ext Clk and PXI DSTARA can be directly used as the sample clock The 100 MHz clock oscillator and PXI 100M clock can be used as references to the PLL The following table shows the clock multiplexer controls for the X3 modules Control Signal Device Function Result PLL REF SEL PLL Reference Mux Selects either 100M or 100MHz fixed 0 100 MHz oscillator as the PLL reference 1 2 PXI 100M X3 SD16 User s Manual 64 Control Signal Device Function Result PLL CLKA SEL External Clock Mux Selects either Ext Clk or PXI DSTARA as 0 Ext input to the clock distribution 1 PXI DSTARA Table 1 X3 External and Reference Clock Selection To use an external clock the external clock multiplexer must be configured to select either the front panel external clock or the PXI DSTARA input on P16 The control signal CLKA SEL is from the application logic FPGA and is set by the host software when the standard logic image is used The following diagram shows the clock path when an external clock is used Note that the PLL is bypassed when using an external clock PLL REF SEL m 100MHz P16 ej Ext Clock Input P1 PXI VCXO 12C Port DSTARA P16 FPGA PLL CLKA SEL A D D LVCMOS 1 LVCMOS DAC D LVCMOS D
67. c Ls jJ p E wa 2 E m if iu emg LE e 140 qm m qm z LE fit E i ER k PU ba ee ea R192 Li D4 Application LED D4 PCI LED Figure 23 X3 SD16 Mechanicals Top View Rev A X3 SD16 User s Manual 107 Applets for the X3 Modules EEProm X3 Servo has two logic devices on it One controls the analog hardware This logic can be modified by the user and must be loaded by the user with an image on each session The second device performs the baseboard enumeration and PCI interface and has a ROM so that it can function at power up The EEProm applet is designed to allow field upgrades of this PCI logic firmware on the X3 Servo The utility permits an embedded firmware logic update file to reprogrammed into the module Flash ROM which stores the personality of the board Complete functionality is supplied in the application s help file Eeprom Programmer z Target svi File No devices detected Revision Family J Type Status Elapsed X3 SD16 User s Manual 108 Finder The Finder is designed to help correlate board target numbers against PCI slot numbers in systems employing multiple boards Target Number Select the Target number of the board you wish to identify using the Target Number combo box Blink Click
68. clock sources for the outputs The clock dividers on the outputs should be programmed to the same divisor to work with the standard logic The AD9510 is programmed during initialization of the card All configuration registers are written then an update command is sent to the PLL that makes the outputs update simultaneously After an update the clock is stable when the PLL status bit indicates a lock Timing Analysis There are several timing parameters associated with the clock control circuitry that affect the measurement process The following table summarizes two important effects Timing propagation delay through the logic for external clocks are shown for the maximum and typical timing The external clocks go through one or two multiplexers accounting for the differences in propagation delay to the various devices Jitter is summed as the root sum of squares for random jitter Clock Source Clock Destination Propagation Delay ns Additive Jitter ps RMS External clock or A D and DAC 3 6 typical 0 07 PXI DSTARA conversion clocks 5 0 maximum 100 MHz or PXIE 100M PLL Reference clock 1 2 typical 0 05 1 5 maximum Table 12 X3 SD16 External Sample Clock Timing Triggering The X3 SD16 has a triggering component in the FPGA that controls the data acquisition process The sample clock specifies the instant in time when data is sampled whereas triggering specifies when data is kept This allows the applicatio
69. ct to verify proper electrical operation EEPROM Access Select the EEPprom tab The controls on this tab allow the contents of the onboard EEPROM to be queried or changed The onboard EEPROM is used for non volatile storage of module identification strings digital calibration coefficients for each of the A D channels and for a calibration coefficient for the reference clock for the onboard PLL These values are determined during factory calibration and need not normally be changed by the user Debugging Select the Debug tab The controls on this tab support a few low level debug operations to be performed A debug script may be executed at any time to perform low level register fetches or stores to exercise custom FPGA firmware or determine the current hardware state Unlike the stream scripts described earlier this script executes manually via the button so you need not be streaming to put it to use A software alert may be generated by pressing the Software button The value in the edit control to the right of this button is supplied as the code for the alert which is returned and displayed in the log if software alerts are enabled for display Host Side Program Organization With the exception of OS Mb lib libOs_mb a and Analysis Mb lib libAnalysys a the Malibu library is designed to be re buildable in each of the different host environments Borland Builder Microsoft Visual Studio 2003 Microsoft Visual Studio
70. d by the location in the PCI bus so it will remain unchanged from run to run Moving the board to a different PCI slot may change the target identification The Led property can be use to associate a target number with a physical board in a configuration Malibu method Open is called to open the device driver for the baseboard and allocate internal resources for use The next step 15 to call Reset method which performs a board reset to put the board into a known good state Note that reset will stop all data streaming through the busmaster interface and it should be called when data taking has been halted Connect Stream Stream ConnectTo amp Module StreamConnected true UI gt Status Stream Connected PrefillPacketCount Stream PrefillPacketCount FHwPciClk Module Debug PciClockRate FHwBusWidth Module Debug PciBusWidth DisplayLogicVersion FChannels Module Input Info Channels Channels X3 SD16 User s Manual 44 Once the object is attached to actual physical device the streaming controller associates with a baseboard by the ConnectTo method Once connected the object is able to call into the baseboard for board specific operations during data streaming If an objects supports a stream type this call will be implemented Unsupported stream types will not compile The prefill method is used to fill the bus master region with default data so that an immediate underflow may be avoi
71. d in system integration Also the module has been designed to include conduction cooling to improve heat dissipation from the module These features can make the module more reliable in operation and also reduce power consumption System Thermal Design The X3 SD16 dissipates about 6 6 Watts typically for all analog channels running at full rate In standby mode the power dissipation is about 3 5W In an office or lab environment the module can run without forced air cooling Operating temperature is about 48C for a typical 24C office environment If your operating environment exceeds 40C you should carefully consider how to cool the module in your application Conduction or forced air cooling can be used to keep the module from exceeding its maximum operating temperature of 70C If the module temperature exceeds 85C as measured by the temperature sensor in the card the module will disable the analog power supplies to reduce power consumption Conduction cooling is supported for the module and provides an effective method in many applications A thermal plane in the card is attached to the center stripe on the card The card can then be cooled by mounting the card on host card that supports conduction cooling The conduction cooling method allows the module heat to be flowed out to the chassis The thermal plane has NO electrical connection in the module and cannot be used as a ground The front panel bracket is used for cooling and is attached
72. d to an external clock or an external clock This allows the module to synchronize to a system clock or use software programmable sample rates All clock selections are software programmable on the module Clock Mode Use for Restrictions Benefits PLL with internal Software programmable Clock rate has tuning resolution of about 10 Low jitter clock reference clock Hz PLL with external Software programmable External reference must be 1 to 100 MHz Lock to an external clock and reference clock referenced to 50 50 duty cycle see electrical requirements generate an sample clock external clock input below locked to it Clean up external clock jitter using the PLL External Clock Synchronize sampling to External clock must be 1 to 100MHz 50 50 Sample rate can be system devices duty cycle low jitter synchronized with other devices in the system Table 20 Sample Clock Modes The PLL can generate many sample rates that suit most applications The advantage of using the PLL is that the sample clock is very clean and low jitter The output frequency of the PLL is programmable and is determined by the reference clock rate and the VCXO tuning range Software functions for PLL configuration monitoring and clock distribution are provided in Innovative s Malibu software toolkit that configure the operating mode and sample rate required for the desired sample data rate The X3 SD16 uses one AD9510 devices for its PLL divider and
73. dard X3 XMC features are implemented in the application logic This feature set includes a data flow triggering features and application specific features In many cases this logic provides the features needed for a standard data acquisition function and is supported by software tools for data analysis and logging In this manual the FrameWork Logic features for each card are described in in general to explain the standard hardware functionality The X3 FrameWork Logic User Guide provides developers with the tools and know how for developing custom logic applications See this manual and the supporting source code for more information The X3 XMC modules are supported by the FrameWork Logic Development tools that allow designs to be developed in HDL or MATLAB Simulink Standard features are provided as components that may be included in custom applications or further modified to meet specific design requirements Integrating with Host Cards and Systems The X3 XMCs may be directly integrated PCI Express systems that support VITA 42 3 XMC modules The host card must be both mechanically and electrically compatible or an adapter card must be used The XMC modules conform to IEEE 1386 specification for single width mezzanine cards This specification is common to both PMC and XMC modules and specifies the size mounting mating card requirements for spacing and clearances There are several adapter cards that are used to integrate the XMC modules
74. ded void Applicationlo Close Stream Disconnect Module Close FStreamConnected false FOpened false UI gt Status Stream Disconnected Similarly the Close method closes the hardware Inside this method first we logically detach the streaming subsystem from its associated baseboard using Disconnect method Malibu method Close is then used to detach the module from the hardware and release its resources Logic Loading The user interface logic for the module must be loaded at least once per session it remains valid until power is removed from the board In the following code we show how to browse and configure the desired logic In the UL when the logic browse button is pressed LogicLoadBrowseBtnClick method gets called as shown below void fastcall TMainForm LogicLoadBrowseBtnClick TObject Sender Std auto ptr TOpenDialog Dialog new TOpenDialog NULL Dialog gt Filter Logic File bit bit Logic File exo All Files Dialog gt Title Select FPGA Logic File if LogicFilenameEdit gt Text Length Dialog gt InitialDir ExtractFilePath LogicFilenameEdit gt Text if Dialog gt Execute LogicFilenameEdit gt Text Dialog gt FileName The code above opens a dialog allowing the user to browse for logic file The filter property of this dialog masks out all the files in a folder other than bit file or exo file If the user cancels out no change wi
75. e The target board number is set to zero The order of the Exo Logie le targets is determined by the location in the PCI bus so it will remain unchanged from run to run While application 1s being launched the device driver is automatically opened for the baseboard and internal resources are allocated for use At this point stream 18 simply connected to the board and board has been reset to be in known good state Also if ID ROM is properly initialized module name and revision in addition to the Device Opened message is displayed in the message box Next we load the desired user interface logic The user logic for the module must be loaded at least once per X3 SD16 User s Manual 21 session it remains valid until power is removed from the board Use Configure button is to load the logic from an BIT file Setup Tab X3 Snap Example This tab has a set of controls that hold the Congue Steam Zbt Ram EEProm Debug j Communications parameters for data acquisition These settings are Source Output Alerts KHz Pkt Size Time Star Input Q Extemal 40 000 kH Overrun delivered to the target and configure the target when Solwa Input Tonge streaming is initiated via controls on the Stream tab Intemal Pll Lost described in the next section Active Channels Range Trigger Mode Source Frame Mode Cho 0 So
76. e channel input cable included all channels at noise floor X3 SD16 User s Manual 93 la BinView c projects x3 sd1 6 hardware reva qual data dac single tone data bdd Marh HEBR CO 9 O Time Frequency Text Summary Server Magnitude vs Frequency 0 SFDR 95 6 dB cho S N 80 3 dB 20 ENOB 12 8 bits 40 THD 95 8 dB 64K pt FFT 60 80 Ea 100 edi E 120 Py il 140 160 180 103 102 101 109 101 2 31 ae 21 98 SD dB E p 48 TEE Sample EMEI Leap 4036 080 7 Samples 786816 Figure 16 DAC Output for 1 01kHz sine 2Vp p 128 ksps update rate as measured by X3 SD16 A D with single ended input X3 SD16 User s Manual 94 22 BinView c projects x3 sd1 6 hardware reva qual data dac sample rate data_10k bdd Marh HEBA 9 O Time Frequency Text Summary Server Magnitude vs Frequency 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 45 5 0 KHz 2 41 Max S N dB S N 98 SINAD dB ENOB bits SFDR 98 THD 2 98 46 2 736 11 9 31 9 0 000348 103 248 Leap 40 Samples 49176 Figure 17 DAC Output for 2kHz sine 2Vp p 10 ksps update rate as measured by X3 SD16 A D with single ended input X3 SD16 User s Manual 95 Connectors Input Connector JP1 is the front panel connector for the analog inputs
77. e code that performs much of the actual functioning of the program outside of the User Interface portion of the program is therefore common code Each project uses the same file to interact with the hardware and acquire data X3 SD16 User s Manual Program Design The Wave example is designed to allow repeated data playback operations on command from the host As mentioned earlier data can be sourced from disk file or calculated on the fly on a per buffer packet basis The example application software is written to perform minimal processing of played data and is a suitable template for high bandwidth applications The example uses various configuration commands to prepare the module for data flow Parametric information is obtained from a Host GUI application but the code is written to be GUI agnostic board specific I O is performed within the Applicationlo cpp h unit Data is transferred from the Host to the module as packets of Buffers The Host Application The picture to the right shows the main window of Wave example This form is from the designer of the Borland Turbo version of the example It shows the layout of the controls of the User Interface The timer pop up menu and folder icons to the upper right are non visual components in Builder Timer controls timer ticks and pop up menu facilitate user to select channels on right click where the folder controls the posting of a File Open Dialog box They will not ap
78. e following electrical characteristics Typical Maximum Logic High gt 14 3 6V Up to 5 5V if a 100 ohm series resistor is used Logic Low lt 0 7V 0 3V Input Impedance gt 1M ohm Table 15 External Trigger Electrical Characteristics Framed Trigger Mode Framed trigger mode is useful for collecting data sets of a fixed size or playing a fixed number of samples each time the input trigger is fired In framed mode the trigger goes false once the programmed number of points N have been collected Start triggers that occur during a frame trigger are ignored The maximum number of points per frame is 16 777 216 2724 points while the minimum number of points is 2 Data flow to the host is independent of the framed triggering mode In most cases packet sizes to the host are selected to be integer sub multiples of the frame size to allow the entire data set to flow to the host That way the entire data frame can be moved immediately to the host without waiting for the next trigger frame The only restriction is that packet sizes are limited to a minimum of 2 32 bit words meaning that a packet must be at least 4 samples the samples composed of one or more channels of data X3 SD16 User s Manual 73 Decimation The data may be decimated by a programmed ratio to reduce the data rate or match the A D and DAC data rates Depending on the A D sample rate the DAC data rate may be 2x the A D data rate In th
79. e information pointing to overheating The most important thing to do is to determine the root cause of the failure The module could have failed the system power is bad or the environment is too harsh The first thing to do is inspect the module Is anything discolored or do any ICs show evidence of damage This may be due to device failure system power problems or from overheating If damage is noticed the module is suspect and should be sent for repair If not test the module outside the system in a benign environment such as on an adapter card in a desktop PC with a small fan It should not overheat If it does this module is now bad Now consider what may have caused the failure A bad module could be the cause but it could have went bad due to system failure or overheating The system power supply could cause a failure by not providing proper power to the module This could be too little power resulting in the module failing or power glitches causing the temp sensor to drop out Did other cards in the system fail If so this may indicate that a system problem must be solved If the module did overheat you should review the thermal design of the system What was the ambient temperature when failure occurred Is the air flow adequate Is air flow blocked to the card Did a fan fail If conduction cooling 18 being used what is the temperature of the surrounding components The heat must be dissipated either through conduction or convection
80. e software maintenance downloads of development kit software and telephone technical hot line support for a one year period X3 SD16 User s Manual Registration Information User Last Henderson r Emait Adress Telephone Country Code Area CodeNumber Extension Fax Area CodevNumber Company 4 Name Innovative Integration Address City State County Postal Code p Product Board Viste Access Code 935846148 0 Help E Register Now Ok Reserve Memory Applet ReserveMemDsp exe Each Innovative PCI based DSP baseboard requires 2 to 8 MB of memory to be reserved for its use depending on the rates of bus master transfer traffic which each baseboard will generate Applications operating at transfer rates in excess of 20 MB sec should reserve additional contiguous busmaster memory to ensure gap free data acquisition To reserve this memory the registry must be updated using the ReserveMemDsp applet If at any time you change the number of or rearrange the baseboards in your system then you must invoke this applet to reserve the proper space for the busmaster region See the Help file ReserveMemDsp hlp for operational details Data Analysis Applets Reserve Memory for Dsp Baseboards 21 Numberinstaled Matador family z Type System 2048 BM Region Size 2048 71 Rsv Region Size
81. e types of alerts of which the module is capable The enabled state of the check boxes is copied into the Settings AlertEnable array This code fragment applies the state of each bit in that array to the Alerts sub object within the module During streaming an alert message will be sent to the Host tagged with a special alert packet ID PID to signify the alert condition Calculate waveform buffer ShortDG Packet DG WaveformPacket Calculate Packet Size in shorts int packet_size shorts Settings StreamPacketSize ActiveChannels while packet size shorts 4 0 packet size shorts ActiveChannels Packet DG Resize packet size shorts PacketBufferHeader PktBufferHdr WaveformPacket PktBufferHdr PacketSize Settings StreamPacketSize PktBufferHdr Peripheralld Module Output PacketId PktBufferHdr 1 HeaderTagValueOriginal The buffer size is calculated in terms of samples per active channel based on the packet size specified in th GUI so for example is 1000 is the Packet size in the GUI and two channels are enabled then the short buffer 16 bit word will be of size 2000 In this example w chose a ShortBuffer since all X3 modules up to date have 16 bit DACs The for DAC 0x02 Builds waveform buffer X3 SD16 User s Manual 49 BuildWave WaveformPacket Settings WaveType Start Streaming Stream Start The Stream Start command applies all of the above config
82. encies are hidden The predefined UserInterface interface class is defined in Applicationlo h The constructor of Applicationlo requires pointer to the interface which is saved and used to perform the actual updates to the UI inside of ApplicationIo s methods Applicationlo Initialization The main form creates an Applicationlo object in its constructor The object creates a number of Malibu objects at once as can be seen from this detail from the header Applicationlo h PmcModule Module IUserInterface UI Innovative PacketStream Stream IntArray _Rx unsigned int Cursor 1164 BlocksToLog bool Opened bool Stopped bool StreamConnected Innovative StopWatch Clock Innovative DataLogger Logger IntArray DataRead Innovative BinView Graph Innovative Scripter Soripts float ActualSampleRate std string Root Innovative AveragedRate Time double FBlockRate std string FVersion Innovative SoftwareTimer Timer In Malibu objects are defined to represent units of hardware as well as software units The PmcModule defined in Target h represents the X3 specifuc board The PacketStream object encapsulates supported board specific operations Scripter object can be used to add a simple scripting language to the application for the purposes of performing hardware initialization during FPGA firmware development Buffer class object can be used to access buffer contents In addition under this constructor
83. ent PCI slot may change the target identification The Led property can be use to associate a target number with a physical board in a configuration Malibu method Open is called to open the device driver for the baseboard and allocate internal resources for use The next step is to call Reset method which performs a board reset to put the board into a known good state Note that reset will stop all data streaming through the bus master interface and it should be called when data taking has been halted Connect Stream Stream ConnectTo amp Module StreamConnected true UI gt Status Stream Connected FHwPciClk Module Debug PciClockRate FHwBusWidth Module Debug PciBusWidth DisplayLogicVersion FChannels Module Input Info Channels Channels Once the object is attached to actual physical device the streaming controller associates with a baseboard by the ConnectTo method Once connected the object is able to call into the baseboard for board specific operations during data streaming If an objects supports a stream type this call will be implemented Unsupported stream types will not compile void ApplicationIo Close Stream gt Disconnect Board Close X3 SD16 User s Manual 28 FOpened false Similarly the Close method closes the hardware Inside this method first we logically detach the streaming subsystem from its associated baseboard using Disconnect me
84. eographic Address 0 F9 1 Geographic Address 1 C12 GA2 Geographic Address 2 C14 MBIST Built in Self Test active low 11 MPRESENT Present active low 11 MSDA PCI Express Serial ROM data F13 MSCL PCI Express Serial ROM clock F15 MVMRO PCI Express Serial ROM write enable C16 WAKEZ Wake indicator to upstream device active low D19 Root device active low E19 X3 SD16 User s Manual 100 XMC P16 Connector P16 is the XMC secondary connector to the host and is used for digital IO data link and triggering functions XMC pin header 0 05 in pin spacing vertical mount Number of Connections 114 arranged as 6 rows of 19 pins each Connector Part Number Samtec ASP 105885 01 Figure 19 P16 XMC Connector Orientation X3 SD16 User s Manual 101 Table 32 X3 XMC Secondary Connector P16 Pinout Column Row A B C D E F 1 2 TRIGO DIO19 2 DGND DGND DIOI PXI TRIGI DGND DGND DIO20 3 gt DIO2 PXI TRIG2 DIO21 4 DGND DGND DIO3 PXI TRIG3 DGND DGND DIO22 5 DIO4 PXI TRIG4 DIO23 6 DGND DGND DIOS PXI 5 DGND DGND DIO24 7 z DIO6 PXI TRIG6 2 DIO25 8 DGND DGND DIO7 PXI TRIG7 DGND DGND DIO26 9 DIO38 DIO39 DIO8 PXI_ STAR DIO40 DIO41 DIO27 PXI_DS
85. es El Project Defaults Configuration Type Use of MFC Use of ATL Minimize CRT Use in ATL Character Set Common Language Runtime support Whole Program Optimization C General Additional Include Directories Malibu PlotLab Include for graph scope display Code Generation Run Time Library Multi threaded Debug DLL Precompiled Headers Create Use Precompile Headers Not Using Precompiled Headers Linker Additional Library Directories Innovative Lib Vc8 Application exe Use Standard Windows Libraries Mot Using ATL No Use Unicode Character Set Common Language Runtime Support jclr No Whole Program Optimization If anything appears to be missing view any of the example sample code Vc8 projects X3 SD16 User s Manual DialogBlocks DialogBLocks Project Settings under Linux Project Options Configurations Compiler name GCC Build mode Debug Unicode mode ANSI Shared mode Static Modularity Modular GUI mode GUI Toolkit lt your choice wxX11 wxGTK 2 etc gt Runtime linking Static or Dynamic we use Static to facilitate execution of programs out of the box Use exceptions Yes Use ODBC No Use OpenGL No Use wx config Yes Use insalled wx Widgets Yes Enable universal binaries No Debug flags ggdb DLINUX Library path INNOVATIVE Lib Gcc Debug WINDRIVER lib Linker flags AUTO WI PROJECTDIR Example lcf IncludePath I INNOVAT
86. ete o Ae OH TR TH IERI 28 Figure 8 DIO Control Register 1 0 14 33 Figure 9 Digital IO Port Addresses itane nca erm Hu o a ero d Grp 33 Figure TO Digital VO Port i uie ete ae o e ER RE HERO n RETO nts cade up e 33 Figure 11 X3 SD16 Module with analog shield installed eene nennen 53 Figure 12 X3 SD16 Block Diagram oe e C D E E 54 Figure 13 X3 SD16 A D Channel 20 nennen tnter ene tne rE eE enne E N enne 56 Figure 14 A D Frequency Response Differential input to 57 Figure 15 X3 SD16 DAC Channel Diagram esee 60 Figure 16 DAC Output Filter 0 0 nennen rene tne 61 Figure 1 3 5 116 Clock Generation and Controls Block 64 Figure 1 3 5 016 External Clock teen a e e aen aae enses E eren 65 Figure 2 Sample ended at debo tutes 72 Figure 3 Example 64 channel System Architecture eese eene nnne enne 76 Figure 4 X3 SD16 FrameWork Logic Data Flow eese nennen nennen
87. etionEvent amp event UI gt Log Load completed ok DisplayLogicVersion Finally the logic loader issues a process completion event when the load is complete This event is handled by HandleLoadComplete as shown above In this case all we do is update the UI so the user can see that the logic configuration is complete and application status is idle In other cases this could trigger the application to automatically perform additional tasks Starting Data flow After downloading interface logic user can setup clocking and triggering options The stream button then can be used to start streaming and thus data flow void ApplicationIlo StartStreaming if StreamConnected UI gt Log Stream not connected Open the boards return X3 SD16 User s Manual 30 Vip Set up Parameters for Data Streaming First have UI get settings into our settings store UI GetSettings Before we start streaming all necessary parameters must be checked and loaded into option object UI gt GetSettings loads the settings information from the UI controls into the Settings structure in the Applicationlo class if SampleRate Module Input Info MaxRate UI gt Log Sample rate too high StopStreaming UI AfterStreamAutoStop return We insure that the sample rate specified by the GUI is within the capabilities of the module if Settings Framed if Settings FrameCount
88. face The X3 module family has a PCI Express interface that provides a lane 2 5 Gbps full duplex link to the host computer The interface is compatible with industry standard PCI Express systems and may be used in a variety of host computers The following standards govern the PCI Express interface on the X3 XMC modules Table 4 PCI Express Standards Compliance Standard Describes Standards Group PCI Express 1 0a PCI Express electrical and protocol standards PCI SIG http www picmg com 2 5 Gbps data rate ANSI VITA 42 XMC module mechanicals and connectors VITA www vita org ANSI VITA 42 3 XMC module with PCI Express Interface VITA www vita org The X3 module family uses a Texas Instruments bridge chip to go from PCI Express to a local PCI bus on the module The PCI Express bridge works with the PCI FGPA to implement the Velocia packet system for data communications and also provides the module configuration and control features X3 SD16 User s Manual 29 di Data link to App Logic 32 bit 66 MHz PCI Express Bride 9 lt gt Command Channel PCI Express Local PCI Bus oe Serial Link X1 or x4 lane 32 bit 66 MHz lt gt SelectMAP interface to Connector P 15 app logic The major interfaces to the application logic are the data link command channel and SelectMAP interface The data link provides a high performance channel for the application logic
89. features such update clock controls and channel enables are shown WAVE allows you to become acquainted with the features and provides an example to the programmer for using the DACs Getting Good Analog Performance The 3 5 16 has analog dynamic range exceeding 100 dB To take advantage of this it is important to do the following Use differential input signals to eliminate system noise Single ended signals give typically 10 to 20 dB worse results because of noise pickup Band limit input signals Even though the A D has filtering and rejects most out of band noise it 15 a good idea to filter the incoming signal just to get rid of as much noise as possible Scale your input signals to utilize the full range of the input and outputs Make the signal as big as possible so that the noise is a not as much a factor Custom ranges can be ordered if necessary Use a high quality shielded cable The MDR68 cable was selected because it has a foil shield and delivers near coax performance Twist DAC outputs with the return current wire as a pair Use the GND on the adjacent pin for each DAC output Reference input signals to the module ground Be sure not to introduce ground loops If you decide to test the 3 5 16 to verify its performance be aware that most signal sources not good enough without additional filtering and careful use Most single ended lab instruments are limited by their distortion to about 80 dB Post filter is necess
90. ficant events Using alerts the application can create a time history of the data acquisition process that shows when important events occurred and mark the data stream to correlate system events to the data This provides a precision timed log of all of the important events that occurred during the acquisition and playback for interpretation and correlation to other system level events Alerts for critical system events such as triggering data overruns analog overranges and thermal warnings provide the host system with information to manage the module The Alert Log creates an alert packet whenever an enabled alert is active The packet includes information on the alert when it occurred in system time and other status information The system time is kept in the logic using a 32 bit counter running at the sample clock rate Each alert packet is transmitted in the packet stream to the host marked with a Peripheral Device Number corresponding to the Alert Log The Alert Log allows X3 modules to provide the host system with time critical information about the data acquisition to allow better system performance System events such as over ranges can be acted on in real time to improve the data acquisition X3 SD16 User s Manual 79 quality Monitoring functions can be created in custom logic that triggers only when the digitized data shows that something interesting happened Alerts make this type of application easier for the host to implement s
91. for the module to keep from overheating You should also review application and be sure that you have taken advantage of any power saving features on the module Many of the X3 modules have power saving features that allow you to turn off unused channels reduce clock rates or stop X3 SD16 User s Manual 38 data when the module is not in use The chapter discussing module specifics has information on both the power consumption and the power saving features that can be used LED Indicators The X3 modules have two LEDs one that is used for PCI Express interface and one from the application logic Both LEDs are on the back side of the card These LEDs are not visible from the front panel in most installations They are used primarily for debug The LED from the PCI Express interface FPGA D4 is usually used to find the target number of the module The Finder applet blinks the LED when the target module is addressed This allows systems with multiple modules to find out the software target number for each module Another use for the PCI LED is to indicate that the PCI interface logic loaded This LED should ALWAYS be on after the host computer boots If it is not on that means the PCI control logic did not load The possible causes for this are bad power defective module or missing PCI logic image In any case if this LED is off the card will not communicate to the host system The second LED D5 is from the application logic The purpo
92. fore it will make a the correct sample clock rate This device has many configurations that require programming of a large number of registers prior to use The X3 support software provides PLL configurations that satisfy most applications and should be used if possible For custom configurations the AD9510 data sheet should be consulted The X3 SD16 requires the clock assignments as show in the following table The sample clock fs in the FPGA clock is connected to AD9510 output 0 The divider should be programmed to use LVPECL output to the FPGA while the other clocks are CMOS FPGA 0 LVPECL A D device 0 even channels 44 CMOS A D device 1 odd channels 54 CMOS DAC device 0 channels 0 7 CMOS DAC device 1 channels 8 15 79 CMOS Table 11 PLL Output Assignments The VCXO is connected to the CLK2 input to the PLL The standard reference clock is 100 MHz to the PLL although an external reference may be used The output of the PLL section of the AD9510 can therefore be programmed to many numbers in the range of 10 to 280 MHz that may be subsequently divided in the outputs The dividers in the clock distribution section of the AD9510can be used to further divide the clock by 1 to 32 with the restriction only even numbers are used to make the clock a 5096 duty cycle X3 SD16 User s Manual 70 The external clock and optional fixed oscillator are connected to the CLK1 input The PLL must be programmed to use one of these two
93. ftware Size Unframed The setup tab contains a large number of controls al 2 2 C Enema 4000 Auto Retrioger used to configure the on board timebase alert Digital 1 0 Front Panel 1 0 Data Logging Test Counter Decimation fi 1 h 1 1 Config Mask Config Mask Samples Enable notifications analog channel selection range and 1000 M 5 Enable R triggering etc Each of these controls is described below LU Press F1 to see online help for this example No devices detected Clock Group module features an on board AD9510 PLL which may be used as a sample clock during analog acquisition Alternately an external sample clock may be used The C1ock Source radio control governs which timebase is used as the analog sample clock If the internal PLL is selected the sample rate entered in the Output Khz edit Module open Failure control is used to program the PLL to generate the specified sample rate during acquisition However if the clock source is external then the Output KHz control is used to inform the program of your intended external sample rate In that case you are expected to supply a clock running at the rate listed in the Clock Source KHz control to the external clock input connector on the module Communications Group All X3 modules support data transfer between Host memory and the on board FPGA via a dedicated PCI Express bus interface Data is transferred i
94. g the condition This information can be acted upon immediately or simply logged along with analog data for subsequent post analysis Module OnBeforeStreamStart SetEvent this amp ApplicationIo HandleBeforeStreamStart Module OnBeforeStreamStart Synchronize Module OnAfterStreamStart SetEvent this amp ApplicationIlo HandleAfterStreamStart Module OnAfterStreamStart Synchronize Module OnAfterStreamStop SetEvent this amp ApplicationIo HandleAfterStreamStop Module OnAfterStreamStop Synchronize Similarly HandleBeforeStreamStart HandleAfterStreamStart and HandleAfterStreamStop handle events issued on before stream start after stream start and after stream stop respectively These handlers could be designed to perform multiple tasks as event occurs including displaying messages for user These events are tagged as Synchronized so Malibu will marshall X3 SD16 User s Manual 43 the execution of the handlers for these events into the main thread context allowing the handlers to perform user interface operations The Stream object manages communication between the application and a piece of hardware Separating the I O into a separate class clarifies the distinction between an I O protocol and the implementing hardware In Malibu high rate data flow is controlled by one of a number of streaming classes In this example we use the events of the PacketStream class to alert us when a packet is required by the target When a dat
95. gain controls for auto ranging external front end signal conditioning A D Sampling Rates The ADS1278 supports sample rates from DC to 144 kHz The sample clock can be either an external clock input or generated on the card by a PLL A full description of the sample clocks is described in the sample rate generation section of this manual The ADS1278 requires a clock that is either a 256 or 512 multiple of the output data rate sample rate The standard logic and firmware use the high resolution mode of the converter for sample rates below 52 kHz or the high speed mode for sample rates above 52 kHz The high resolution mode requires 512 clocks per sample while the high speed mode requires 256 clocks per sample Parameter Min Max Units Sample rate 0 39 144 Ksps A D Clock Rate 10000 27 ns Clock Divisor 256 Fs gt 52 kHz 512 Fs lt 52 kHz clks sample High Speed Mode High Resolution Mode PLL Clock 0 12 280 MHz A D limited to 37 MHz Table 16 A D Clock Rate Requirements When the PLL is used the sample clock has a minimum rate of 1 2 kHz Sample rates lower than 1 2 kHz are supported using decimation in the logic The FrameWork logic supports 1 N decimation to which means that 1 point is kept for every N collected All channels must be decimated at the same rate when this mode is used in the standard logic Note that the PLL can generate clocks up to 280 MHz but the A D is limited to 37 MHz maximum clock ra
96. ge Max 3 6V Exceeding these will damage Min 0 3V the application FPGA Output Voltage 3 0V For load lt 12 0 lt 0 8V Output Current 12mA FPGA can be reconfigured for custom designs for other drive currents Input Logic 1 gt 2VDC Thresholds 0 lt 0 8VDC Input Impedance gt 1M ohm 15 pF Excludes cabling Pulldown 8K ohms Pulldown is in the logic Table 8 Digital IO Bits Electrical Characteristics Parameter Value Notes Input Voltage Max 3 6V Exceeding these will damage Min 0 3V the application FPGA Signaling LVDS 2 5V EIA 644 Standard Input common Min 0 30V mode voltage Typ 1 25V Max 2 20V X3 SD16 User s Manual Parameter Value Notes Input Logic Min 0 10V Differential voltage Vint Vin Thresholds Typ 0 30V Max 0 60V Termination 100 ohms Table 9 Digital IO Clock Input Electrical Characteristics Notes on Digital IO Use The digital IO on X3 family as supported using the standard FrameWork Logic is intended for low speed bit IO controls and status The interface 18 capable of data rates exceeding 75MHz and custom logic developers can implement much higher speed and sophisticated interfaces by modifying the logic The digital IO clock input and LVDS signal pair is a capable of rates exceeding 200 MHz Since the bit IO is connected to the command channel interface in the standard logic this limits the effective upda
97. gh frequency noise This filter is a single pole set to 200 kHz In addition to the analog filter the A D device itself has a digital filter that effectively removes inputs above Fs 2 See the test data section for measured result 0 00 10 00 20 00 Gain dB 30 00 40 00 200 00 100 00 0 00 100 00 Phase deg 200 00 300 00 10 100 1 10 100k Frequency Hz Figure 14 A D Frequency Response Differential input to A D X3 SD16 User s Manual 57 Overrange Detection The logic is used to detect overrange conditions on the A D devices When the input is at or above 99 of full scale Ox 7FFFO00 or negative 0x8000FF an analog overrange is likely to have occurred Overrange occurs when the input signal is above the input range selected is exceeded For small overrange conditions of less than 5 overrange the A D will recover in a few samples to proper readings For larger overrange conditions the A D may require longer to recover The A D overrange detection in the logic be used to trigger an alert in the logic to notify the application when this error condition has occurred The alert message shows when the overrange occurred in system time and which channels overranged Custom logic has access to the overrange bits in the A D interface component Each data sample indicates when an overrange occurs as part of its status byte appended to the data This allows implementation of automatic
98. gure Stream Event Handlers Stream OnDataAvailable SetEvent this amp ApplicationIo HandleDataAvailable Stream OnDataAvailable Synchronize X3 SD16 User s Manual 27 In this example a Malibu SoftwareTimer object has been added to the Applicationlo class to provide periodic status updates to the user interface The handler below serves this purpose Timer OnElapsed SetEvent this amp ApplicationIo HandleTimer Timer OnElapsed Thunk An event is not necessarily called in the same thread as the UI If it is not and if you want to call a UI function in the handler you have to have the event synchronized with the UI thread The call to Synchronize directs the event to call the event handler in the main UI thread context This results in a slight performance penalty but allows us to call UI methods in the event handler freely Creating a hardware object does not attach it to the hardware The object has to be explicitly opened The Open method open hardware Open Devices Module Target Settings Target Module Open Module Reset UI gt Status Module Device Opened Opened true This code shows how to open the device for streaming Each baseboard has a unique code given in a PC For instance if there are three boards in a system they will be targets 0 1 and 2 The order of the targets is determined by the location in the PCI bus so it will remain unchanged from run to run Moving the board to a differ
99. he calibration is read out of the EEPROM at initialization time by the application software and written into registers in the application logic for real time error correction The EEPROM also has a write cycle limit of 100K cycles so it should only be written to when calibration is performed or configuration information changes Once the write cycle duration limit 1s exceeded the device will not reliably store data any more X3 SD16 User s Manual 31 Digital I O The X3 modules have a digital IO port and is accessible over P16 that provides basic bit IO The port provides 44 bits of IO that may be used as inputs or outputs and a differential clock input The port is configured and accesses directly from the PCI Express host For more advance applications digital IO port may be reconfigured in custom logic applications for a variety purposes since it provides direct connections to the applicant FPGA The DIO port is presented on P16 See the connectors section of this chapter the connector pin out and information about the connector Software Support The digital I O hardware 1s controlled by the IUsesExtendedDioPort class Its properties Table 6 IUsesExtendedDioPort Class Operations DioPortConfig Configures banks of bits for input or output DioPortData Broadside Read Write to low order 32 bits of DIO DioPortDataHigh Property Broadside Read Write to high order 12 bits of DIO Only Typical use of the digital IO por
100. he condition is true we exit the routine after logging the message in the message log We can also do some more UI tricks here such as setting up the progress bar limits and disabling the configure button etc We further extract the file name from the Textbox and pass it to the Applicationlo method LoadLogic shown below ApplicationIo LoadLogic Initiate Logic Load Process void ApplicationIo LoadLogic if Opened X3 SD16 User s Manual 29 UI gt Log No module on specified target return DE hog ia SSeS eee See E UI gt Log Parsing Module logic file UI gt GetSettings Module Logic ConfigureFpga Settings ExoFile In this method we make a call to the Malibu function ConfigureFpga which allows new logic image to be loaded This method takes name of the image file as an argument which will be read and loaded into the interface logic Logic loading triggers a series of events which are managed by the background thread void ApplicationIo HandleProgress ProcessProgressEvent amp event UI gt UpdateLogicLoadProgress event Percent Process progress events are issued to give a percentage progress of the entire operation These event are handled by HandleProgress This handler calls a UI method UpdateLogicLoadProgress where a Progress bar control is updated to give a visual effect of the loading progress void ApplicationIo HandleLoadComplete ProcessCompl
101. he filter reduces higher frequencies in the DAC outputs due to the DAC switching Output response is flat out to about 50 kHz 10 00 40 00 50 00 20000 150 004 100 00 Phase deg 5000 10 100 1k 10k 100k 1 Frequency Hz Figure 16 DAC Output Filter Response The DAC outputs are driven by an op amp capable of 10 mA drive current This is sufficient for most applications If more drive current is required a power amplifier should be added to the system The DAC outputs should be carefully handled in the output cabling Each DAC output has a ground pin adjacent to it on the connector and in most cases this ground should be used as the return path for that output DAC Sample Underrun An underrun occurs when a DAC update is required but no new data is available This can occur if the application cannot keep up with the update rate An underrun can be caused by conditions such as the host being too busy to provide data in a timely fashion or a logic design that cannot meet the required update rate X3 SD16 User s Manual 61 When an underrun occurs the last point provided to the DAC 15 simply repeated For waveform generation this means that the output has a duplicated point For servo controls this creates a one sample delay in the output update Repeated underrun conditions result in large data latency and eventually the DAC FIFO overflowing If an underrun occurs i
102. igured to provide thermal protection It is unlikely except in cases of catastrophic failure that the module will overheat when the logic is not loaded since it is central to module operation X3 SD16 User s Manual Software support tools provide convenient access to the temperature and thermal controls These should be used in application programming configure and monitor the temperature as illustrated below Module Target 0 Module Open Create reference to thermal management object on module const LogicTemperatureIntf amp Temp Module Thermal Read current temperature float t Module LogicTemperature Read write current warning temperature float t Module LogicWarningTemperature Module LogicWarningTemperature 70 0 Read current failure temperature float t Module LogicFailureTemperature See if the module is in thermal shutdown bool state Module Failed Thermal Failures The X3 modules will shut down if the module temperature exceeds 85C This means that something is seriously wrong either with the module or with the system design Damage may occur if the module temperature exceeds this limit The Application LED will blink when the a temperature failure has occurred If your software was monitoring the alert packets you will also receive a temperature warning alert prior to failure The module temperature can always be read by the application software so this can also provid
103. ince they don t require host activity until the event occurs Types of Alerts Alerts can be broadly categorized into system IO and software alerts System alerts include monitoring functions such as temperature time stamp rollover and PLL lost These alerts just help keep the system working properly The temperature warning should be used increase temperature monitor and to prepare to shut down if necessary because thermal overload may be coming Better to shut down than crash in most cases The temperature failure alert tells the system that the module actually shut itself down This usually requires that the module be restarted when conditions permit The data acquisition alerts including over ranges overflows and triggering tell the system that important events occurred in the data acquisition process Overflow is particularly bad data was lost and the system should try to alleviate the system by unclogging the data pipe or just start over If you get an overrange alert then the data may just be bad for a while but acquisition can continue Modules with programmable input ranges can use this to trigger software range changes Software alerts are used to tag the data Any message can be made into an alert packet so that the data stream logged includes system information that is time correlated to the data Table 20 Alert Types Alert Purpose Timestamp rollover The 32 bit timestamp counter rolled over This can be used
104. into other form factor PCI Express systems such as desktop systems There are also adapter cards to electrically adapter the PCI Express XMC modules in older PCI systems that use a bridge device between the two buses PCI is not electrical X3 SD16 User s Manual 40 Host Type Bus Mechanical Form factor Adapter Example card Required XMC 3 module PCI Express 1 0a XMC single width None Kontron CP6012 slot www kontron com Diversified Technology CPB4712 http www diversifiedtechnology com p roducts cpci cpb4712 html Desktop PC PCI Express 1 0a PCI Express Plug in card PCIe XMC 3 Innovative 80172 adapter Desktop PC PCI 2 2 PCI Plug in card PCI XMC 3 Innovative 80167 adapter Compact PCI PCI Express 1 0 3U or 6U CPCle XMC 3 TBD Express adapter Cabled PCI PCI Express 1 0a Cabled PCI Express to Cable PCIe Innovative 90181 0 Express remote IO Adapter and 3 carrier PXI Express Compact PCI 3U 3U PXIe Innovative 80207 Express Adapter Embedded PC Stand alone PC Enclosure is Innovative 90201 90199 with dual XMC sites 195 x 252 x 75 mm X3 SD16 User s Manual 41 Developing Host Applications Developing an application will more than likely involve using integrated development environment IDE also known as an integrated design environment or an integrated debugging environment This is a type of computer software that assists computer programmers in developi
105. ionlo HandleTimer OpenWire NotifyEvent amp Event int DigIn DioData int FrontIn FrontPanelData Display status UI gt PeriodicStatus X3 SD16 User s Manual 51 FrontPanelData FrontIn DioData DigIn Initial trigger state machine below if IsTriggered Settings AutoTrigger return if PrefillCount PrefillCount if Settings ExternalTrigger 0 amp amp SoftwareTrigger X3 SD16 User s Manual PrefillCoun 0 52 X3 SD16 Hardware Introduction The X3 SD16 is a member of the X3 XMC family that has 16 channels of 24 bit 144 kHz A D conversion and 16 channels of 24 bit 192 kHz DAC with FPGA computing core designed for monitoring analyzing and generating wide dynamic range signals A dynamic range of over 100 dB with real time signal processing makes the X3 SD16 suitable for demanding applications in vibration and acoustic measurement generation and control A high performance computing core for signal processing data buffering and system IO is built around a Spartan3A DSP 1 8M gate FPGA Supporting peripherals include SRAM conversion timebase and triggering circuitry 44 bits digital IO and a PCI Express interface The module format is a single slot XMC conforming to IEEE 1386 CMC standard and is compatible with XMC 3 VITA 42 3 host sites Figure 11 X3 SD16 Module with analog shield installed Custom application logic development for the X3 S
106. ipt executes manually via the button so you need not be streaming to put it to use A software alert may be generated by pressing the Software button The value in the edit control to the right of this button is supplied as the code for the alert which is returned and displayed in the log if software alerts are enabled for display Host Side Program Organization With the exception of OS Mb lib libOs mb a and Analysis Mb lib libAnalysys a the Malibu library is designed to be re buildable in each of the different host environments Borland Builder Microsoft Visual Studio 2003 Microsoft Visual Studio 2005 using the NET UI and GNU GCC Linux Because the library has a common interface in all environments the code that interacts with Malibu is separated out into a class Applicationlo in the files Applicationlo cpp and h This class acts identically in all the platforms The Main form of the application creates an ApplicationIo to perform the work of the example The UI can call the methods of the ApplicationIo to perform the work when for example a button is pressed or a control changed Sometimes however the Applicationlo object needs to call back into the UI But since the code here is common it can t use a pointer to the main window or form as this would make Applicationlo have to know details of Borland DialogBlocks Linux or the environment in use The standard solution to decouple the Applicationlo from the form
107. irements eene nennen nnne nennen nnne 58 Table 7 X328DT6 DAG pen oed de te UR RU HI Coe deeds e DER cad 59 Table 18 DAC Conversion usse d e ERE HR RETRO EE META RISE REEL Re urge 60 Table 19 D A Clock Rate Requirements esses eene nennen nene nenne nnne 62 Table 20 Sample Clock Modes 3 e EORR RD GU Dept e c eet baee 63 Table 1 External and Reference Clock Selection sess 65 Table 1 External Clock and Reference Input Requirements eese 66 Table 2 External Clock and Reference Signal enne 66 Table 3 Sample Clock Output Ranges and Resolution ennemi 66 Table 4 Selecting values for PLL ice ERI e Ree a Up e 68 Table 5 PLE Example Settings 5 e se e e o GE te e E Ue e e EE e Ede dd 68 Table Clock Device Address et rem titer te Pd x ROG 69 7 Interface Word Forrmiat 2e ee I be EUR Oen o Fare ede coda 69 Table 8 PDERead Sequerice eer ee EO Ee ee RE Re IRE E DAS HL edt be es ec e UNE 69 Table 9 PLE Read Sequernce dtt RR GR Rt t e A RE e eg ost editus 70 T ble T10 PEE Read Word ied Ida e atleta d P e ai RE ete tee Le 70 Table T T PEE O tput Assignments e Sete ae NEU TRI RS 70 Table 12 X3 SD16 Ex
108. is case a decimation rate of 2 to the DACS is used to compensate for this disparity when the same data rate is desired The decimation simply discards N points for every point kept no averaging or filtering is used When decimation is true the number of points captured in the framed mode is the number of decimated points in other words the discarded points do not count Maximum decimation rate is 1 4095 When decimation is used in the framed trigger mode the number of points captured is after decimation The frame count is always the actual number of points inserted into the FIFO Synchronizing Multiple X3 SD16 Synchronizing multiple X3 SD16 for large channel count systems 18 supported so that simultaneous sampling and DAC updates are achieved This requires that the modules first be started in synchronization then that the clock and triggers be synchronous to one another In a multiple card system the sync signal is either from an X3 SD16 designated as the sync master or may be provided by a system signal The sync 15 connected to all of the slave cards in the slave system The sample clock must also be synchronized to all cards This can be achieved using a common clock signal or clock reference to the cards For example a 10 MHz signal from the system GPS or clock reference can be provided to each card so that its PLL can lock to the reference and generate the sample clocks All cards must run at the same frequency or an integer
109. is to use an Interface class to hide the implementation An interface class is an abstract class that defines a set of methods that can be called by a client class here ApplicationIo The other class produces an implementation of the Interface by either multiple inheriting from the interface or by creating a separate helper class object that derives from the interface In either case the implementing class forwards the call to the UI form class to perform the action ApplicationIo only has to know how to deal with a pointer to a class that implements the interface and all UI dependencies are hidden The predefined UserInterface interface class is defined in Applicationlo h The constructor of Applicationlo requires pointer to the interface which is saved and used to perform the actual updates to the UI inside of ApplicationIo s methods ApplicationIo Initialization The main form creates an Applicationlo object in its constructor The object creates a number of Malibu objects at once as can be seen from this detail from the header Applicationlo h PmcModule Module Innovative PacketStream Stream IUserInterface UI Innovative Scripter Script Innovative Buffer Packet X3 SD16 User s Manual 42 Innovative AveragedRate Time Innovative SoftwareTimer Timer In Malibu objects are defined to represent units of hardware as well as software units The PmcModule defined in Target h represents the X3 specific board The Packe
110. ith the settings from the GUI Set test mode Module TestCounterEnable Settings TestCounterEnable For test purposes the FPGA firmware supports replacement of analog input samples with ascending ramp data If the test counter is enabled in the GUI it is applied to the hardware using the preceeding code fragment Set Decimation Factor if enabled if Settings DecimationEnable Module Input Decimation Settings DecimationFactor else Module Input Decimation 1 The above code controls the desired decimation factor Route clock to active analog devices Set reference based on clock source to obtain correct FrequencyActual double reference if Settings SampleClockSource 0 reference SampleRate Module DecimationFactor SampleRate Module Clock OutputClock Ad9511 oExternal else reference Module Input Info ReferenceClock Module Clock OutputClock Ad9511 0Vco X3 SD16 User s Manual 32 Apply timebase correction factor if available double correction Settings PllCorrection if correction correction correction 1 0 NaN so fix it Module Clock ReferenceCalibrationFactor correction Module Clock Reference reference Module Clock Frequency SampleRate The module may accept an external sample clock but also features a programmable PLL clock source which may be used as a sample clock for the A D input channels All channels trigger toge
111. ive root folder in the text that follows For example the X5 400 RPM extracts into usr Innovative X5 400 ver A symbolic link named x5 400 is then created pointing to the version directory to allow a single name to apply to any version that is in use X3 SD16 User s Manual 22 Board Packages X5 400M Malibu LinuxPeriphLib ver rel 1586 rpm Board files and examples X5 210M X5 210M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 10M X3 10M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 25M X3 25M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 A4D4 X3 A4D4 LinuxPeriphLib ver rel i586 rpm Board files and examples X3 SD X3 SD LinuxPeriphLib ver rel i586 rpm Board files and examples X3 SDF X3 SDF LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 Servo X3 Servo LinuxPeriphLib ver rel 1586 rpm Board files and examples SBC ComEx Sbc ComEx LinuxPeriphLib ver rel 1586 rpm Board files and examples Unpacking the Package As root type rpm i h X5 400 LinuxPeriphLib 1 1 4 i1586 rpm This extracts the X5 400 board files into the Innovative root directory Use the package for the particular board you are installing Creating Symbolic Links The example programs assume that the user has created symbolic links for the installed board packages A script file is provided to simplify this operation by the Malibu Red package
112. lease MalibuLinux Red ver rel 1586 rpm Installs Baseboard Driver Kernel Plugin intel ipp rti 5 3p x32 rpm Installs Intel IPP library redistributable files X3 SD16 User s Manual 21 The installation CD or the web site contains a file called LinuxNotes pdf giving instructions on how to load these packages and how to install the drivers onto your Linux machine This file is also loaded onto the target machine by the the Malibu LinuxRed RPM These procedures need to be completed for every target machine Malibu To develop software for a baseboard the Malibu packages also must be installed Malibu LinuxPeriphLib ver rel 1586 rpm Installs Malibu Source Libraries and Examples Other Software Our examples use the DialogBlocks designer software and wxWidgets GUI library package for user interface code If you wish to rebuild the example programs you will have to install this software as well wxWidgets wxWidgets http www wxwidgets org DialogBlocks Anthemion http www anthemion co uk org dialogblocks Baseboard Package Installation Procedure Each baseboard installation for Linux consists of one or more package files containing self extracting packages of compressed files as listed in the table below Note that package version codes may vary from those listed in the table Each of these packages automatically extract files into the usr Innovative folder herein referred to as the Innovat
113. lication software to power down unused channels and run in reduced power mode for the A Ds If you incorporate these into your application you may be able to avoid problems later in hot installations Feature Power Saved Comments A D Channel enables 120 mW per channel 1 9W total min The A D channels and input amplifiers for that channel are powered off D A not used 60 mW per channel 1 W total min Turn off the clock to the D A devices Application FPGA not 3 1W Must reload the FPGA to resume operation configured 33 2 system clock 0 5W 33 MHz FPGA system clock Data rate to host is limited to 100 MB s typically Requires custom logic design Table 19 Reduced Power Options The 33 MHz system clock feature requires that the card reconfigured by installing a 0 ohm jumper for R228 This jumper is located near the PCIe interface device XIO2000A and is on the back of the card The factory can pre configure this if you decide to use this option in production As shipped the system clock is 66 MHz because this allows the system logic to support custom logic developers more easily Tests have shown that this reduces operating temperature by 4 C for room temperature testing with no forced air Total data rate from the module must be limited to 50MB s when 33 MHz clock is used Alert Log Overview X3 modules have an Alert Log that can be used to monitor the data acquisition process and other signi
114. ll occur in the selection box If logic file is selected then we will move on to the loading it X3 SD16 User s Manual 45 void _ fastcall TMainForm LogicLoadConfigBtnClick TObject Sender Io LoadLogic In UI LogicLoadConfigBtnClick shown above is executed in response to the Configure button click It immediately checks whether the device is opened and stream is connected If the condition is true we exit the routine after logging the message in the message log We can also do some more UI tricks here such as setting up the progress bar limits and disabling the configure button etc We further extract the file name from the Textbox and pass it to the Applicationlo method LoadLogic shown below ApplicationIo LoadLogic Initiate Logic Load Process void ApplicationIo LoadLogic if UI gt Log No module on specified target return prn K a a A UI gt Log Parsing Module logic file UI GetSettings Module Logic ConfigureFpga Settings ExoFile In this method we make call to the Malibu function ConfigureFpga which allows new logic image to be loaded This method takes name of the image file as an argument which will be read and loaded into the interface logic Logic loading triggers a series of events which are managed by the background thread void ApplicationIo HandleProgress ProcessProgressEvent amp event UI gt UpdateLogicL
115. me hardware in the loop development using the graphical block diagram Simulink environment with Xilinx System Generator The PCI Express interface supports continuous data rates up to 180 MB s between the module and the host A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications What is Malibu Malibu is the Innovative Integration authored component suite which combines with the Borland Microsoft or GNU C compilers and IDEs to support programming of Innovative hardware products under Windows and Linux Malibu supports both high speed data streaming plus asynchronous mailbox communications between the DSP and the Host PC plus a wealth of Host functions to visualize and post process data received from or to be sent to the target DSP What is Builder Builder is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the Builder IDE through the addition of functional blocks VCL components specifically tailored to perform real time data streaming functions What is Microsoft MSVC MSVC is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the MSVC IDE through the addition of dynamically created MSVC compatible classes specifically tailored to perform real time data streaming functions X
116. mmand For instance 0x01 0x02 1 causes the value 0x01 to be stored to logic address 0x02 The Stream Data Files Log check box controls whether received packets are logged in real time If checked data will be accumulated until the limit specified in the Data Logging Samples edit box is reached The Stream Data Files Plot check box controls whether the BinView file viewer applet is invoked when streaming terminates to allow perusal of the acquired data stored in the disk file not available under Linux The Stream Data Files Overwrite BDD check box controls whether a new BinView binary data descriptor file should be created as streaming terminates Normally this should be enabled so that a valid BDD is available for use by BinView when it is opened to view acquired data But under some circumstances such as when comments are added to the BDD file it may be desirable to avoid re creating the file each run During data flow the number of received data packets data transfer rate board temperature current DIO and Front Panel DIO pins state is shown in real time on the statistics status bar located at the bottom of the Streaming tab X3 SD16 User s Manual 24 Ram Test Select the ZbtRam tab The control on this tab allows the onboard ZBT ram to be tested In practice the ZbtRam is directly addressed by custom FPGA firmware However the stock logic provides means of accessing this RAM using methods in the module control obje
117. module They display feedback during the loading of the user logic and when script is used Alerts Module Alerts OnTimeStampRolloverAlert SetEvent this amp ApplicationIo HandleTimestampRolloverAlert Module Alerts OnSoftwareAlert SetEvent this amp ApplicationIo HandleSoftwareAlert Module Alerts OnWarningTemperature SetEvent this amp Applicationlo HandleWarningTempAlert Module Alerts OnPllLost SetEvent this amp ApplicationIlo HandlePllLostAlert Module Alerts OnInputFifoOverrun SetEvent this amp ApplicationIo HandleInputFifoOverrunAlert Module Alerts OnInputTrigger SetEvent this amp ApplicationIlo HandleInputTriggerAlert Module Alerts OnInputOverrange SetEvent this amp ApplicationIlo HandleInputFifoOverrangeAlert This code attaches alert processing event handlers to their corresponding events Alerts are packets that the module generates and sends to the Host as packets containing out of band information concerning the state of the module For instance if the analog inputs were subjected to an input over range an alert packet would be sent to the Host interspersed into the data stream indicating the condition This information can be acted upon immediately or simply logged along with analog data for subsequent post analysis Module OnBeforeStreamStart SetEvent this amp ApplicationIo HandleBeforeStreamStart Module OnBeforeStreamStart Synchronize Module OnAfterStreamStart SetEven
118. n are stored in the on board EEPROM memory These calibration values are used by the logic to correct the analog errors and are loaded into the A D and DAC components as part of the initialization by the software The calibration technique used during factory test determines the A D errors by first measuring the output with ground connected then a known voltage A value close to 95 full scale for each range are recommended The measurements are the average of 64K samples at each test voltage From these three points across the input range the gain and offset errors are calculated DACS outputs are calibrated using a precision voltmeter Outputs of 0V 95 FS 95 FS are commanded on the module and these points are used to calculate the gain and offset errors The voltmeter provides a high precision measurement that is the average over a 1 second period effectively rejecting the noise for this measurement test voltages are measured as part of the procedure with NIST traceable equipment Production calibration is performed at room temperature 24C with the module operating temperature at about 50C A minimum warm up period of 5 minutes is used for the testing Under normal circumstances calibration 1s accurate for one year For recalibration the module can be sent to Innovative or re calibrated using a similar test procedure X3 SD16 User s Manual 83 Updating the Calibration Coefficients A software applet for writing the calib
119. n packets which consist of a two word header followed by a fixed length data buffer Header word zero contains the buffer length in bits 0 23 and a peripheral ID in bits 24 31 The Communications Pkt Size edit control specifies the size of the packets transferred between the target and the Host Each packet transferred results in a Host interrupt handled by the Malibu libraries Consequently larger packets amortize the Host interrupt processing more efficiently However packets are transferred using a contiguous page locked memory region of Host memory known as bus master memory which is allocated during installation via the ReserveMemDsp exe applet Windows Since bus master memory is Host memory it is limited in size by the amount of physical memory installed in the PC By default 32 MBytes are allocated as bus master memory In practice packets of 0x40000 bytes in size tend to provide good performance while fitting into available bus master memory Under Linux the default is 4Mbytes of bus master region and is being researched how to increase it take this into consideration when specifying your packet size Packet Size is defined in events which corresponds to one sample of every enabled channel It is recommended that the calculated packet size in bytes fits four to eight times into the allocated bus master region Active Channels Group The X3 module support simultaneous acquisition up to the maximum number of channels X3 SD16 User
120. n this style represents menu commands For example Click Men mman Hm UCM a View Tools Customize X3 SD16 User s Manual 13 Windows Installation This chapter describes the software and hardware installation procedure for the Windows platform WindowsXP and Vista Do NOT install the hardware card into your system at this time This will follow the software installation Host Hardware Requirements The software development tools require an IBM or 100 compatible Pentium IV class or higher machine for proper operation An Intel brand processor CPU is strongly recommended since AMD and other clone processors are not guaranteed to be compatible with the Intel MMX and SIMD instruction set extensions which the Armada and Malibu Host libraries utilize extensively to improve processing performance within a number of its components The host system must have at least 1 GB of memory 2 GB recommended 1 GB available hard disk space and a DVD ROM drive Most versions of Windows released after Win2000 including XP Vista or Windows 7 referred to herein simply as Windows or later is required to run the developer s package software and are the target operating systems for which host software development is supported Software Installation The development package installation program will guide you through the installation process Note Before installing the host development libraries VCL components or MFC classes yo
121. n to collect data at the desired rate and keep only the data that is required On the X3 SD16 module all A D and DAC channels operate synchronously using the same clock and trigger The trigger controls allows data to be acquired continuously or during a specified time as triggered by either a software or external trigger Data can also be decimated to reduce data rates X3 SD16 User s Manual 71 Trigger Mode Data Collected Played Back Start Trigger Stop Trigger Continuous enabled channel pairs Software or rising edge of Software or falling edge of external trigger external trigger Framed N sample points for each of Software or rising edge of Stops when N samples are the enabled channel pairs external trigger collected back Decimation M points are discarded for every point kept May be used with either trigger mode Table 13 Table 1 Trigger Modes The sample rate is equal to the clock rate on the X3 SD16 module The trigger component operates at the sample rate for its data collection process The trigger is synchronized to the sample clock rate Fs Trigger Analog Input Samples are acquired for each sample period when trigger is true Figure 2 Sample Triggering As shown in the diagram A D samples are captured when the sample period and the trigger are true on rising edges of the sample clock The
122. nel system can be created using four X3 SD16 cards An Innovative X3 Timing card is used in this example to provide the synchronized triggers and clocks The X3 Timing card is configured to provide a 10 MHz reference clock to the system and triggers that are synchronized to this reference clock One of the X3 SD16 cards designated the synch master drives a sync to the other cards When the software releases the master sync all cards then start sampling in synchronization A trigger from either the system software or an external source begins the data acquisition playback process X3 SD16 User s Manual A D 0 15 e D A 0 15 Clock Trigger lt md A D 16 31 eee D A 16 31 Clock Trigger A D32 47 E cad D A 32 47 A 64 channel simultaneously sampling system RM employing 4x X3 SD16 and X3 Timing Figure 3 Example 64 channel System Architecture To synchronize the system the following steps must be followed 1 2 Software configures the cards for sync master slave common clock is provided to the X3 SD16 cards If a common reference clock is used then the 3 5 16 cards must be configured to use an external reference then the PLL for each card must lock to this signal Do not proceed until all cards in the system have their PLL locked Wait 65K clocks then the master should release the sync For best DC accuracy wait 5 minutes for thermal stabilization The cards
123. ng Flexible clocking and synchronization features for IO Data buffering and Computational Memory Two 2MB SRAM devices are used provide data buffering processor memory and computation memory for the Application FPGA Alert Log Monitors system events and error conditions to help manage the data acqusiton process Temperature Sensor Monitors the module temperature and provides thermal protection for the module X3 Computing Core The X3 XMC module family has an FPGA based computing core that controls the data acquisition process providing data buffing and host communications The computing core consists of a Xilinx Spartan3 or 3A DSP FPGA and two banks of 2MB SRAM memory The FPGA uses the memories for data buffering and computational workspace Table 3 X3 Computing Core Devices Feature X3 Module Device Part Number Application Logic SD SDF Xilinx Spartan 3 1M 351000 4 456 10M Servo 25M DIO Xilinx Spartan 3A DSP 1 8 XC3SD1800 4FGG676C 2M SD16 A4D4 Buffer Memory SD SDF Synchronous Burst ZBT 1Mx16 100 MHz SRAM SRAM 10M Servo 25M DIO 512Kx32 133 MHz 2M SD16 A4D4 Computational SD SDF Synchronous Burst ZBT 1Mx16 100 MHz Memory SRAM SRAM 10M Servo 25M DIO 512Kx32 133 MHz 2M SD16 A4D4 The main focus of the module is the X3 s computing core which connects the IO peripherals host communications and support feature
124. ng software The following sections will aid in the initial set up of these applications in describing what needs to be set in Project Options or Project Properties Borland Turbo BCB10 Borland Turbo C Project Settings When creating a new application with File New Forms Application C Builder Change the Project Options for the Compiler Project Options Compiler bcc32 Compatibility Check zero length empty base class Check zero length empty class member functions Vx In our example Host Applications if not checked an access violation will occur when attempting to enter any event function Le Access Violation OnLoadMsg Execute Load Message Event Because of statement Board gt OnLoadMsg SetEvent this amp Applicationlo DoLoadMsg Change the Project Options for the Linker Project Options Linker ilink32 Linking uncheck Use Dynamic RTL In our example Host Applications if not unchecked this will cause the execution to fail before the Form is constructed Error First chance exception at xxxxxxxx Exception class EAccess Violation with message Access Violation Process exe nnnn X3 SD16 User s Manual 15 Other considerations Project Options Compiler bcc32 Output Settings check Specify output directory for object files n release build Release debug build Debug Paths and Defines add Malibu Pre compiled headers uncheck everything Li
125. nker ilink32 Output Settings check Final output directory release build Release debug build Debug Paths and Defines ensure that Build Configuration is set to All Configurations add Lib Bcb10 change Build Configuration to Release Build add lib bcb10 release change Build Configuration to Debug Build add lib bcb10 debug change Build Configuration back to All Configurations Packages uncheck Build with runtime packages X3 SD16 User s Manual 16 Microsoft Visual Studio 2005 Microsoft Visual 2005 version 8 Project Properties When creating a new application with File New Project with Widows Forms Application New Project Project types Templates Visual C Visual Studio installed templates ATL CLR ASP NET Web Service class Library General BR Console Application DECR Empty Project MFC 1501 Server Project Gi Windows Forms Application Smart Device Ba windows Forms Control Library windows Service Win32 Other Languages My Templates Other Project Types FE Search Online Templates A project for creating an application with a Windows user interface Name Enter name Location Cisome folder Solution Create new Solution v C Create directory For solution Solution Name lt Enter_name gt Add to Source Control X3 SD16 User s Manual 17 Project Properties Alt F7 Configuration Properti
126. nstance 0x01 0x02 1 causes the value 0x01 to be stored to logic address 0x02 During data flow the number of played data packets data transfer rate board temperature current DIO and Front Panel DIO X3 Wave Configure Setup Stream Eeprom Debug Al Start scripts Enable ce Enable Front Rate KB s Temp Trig Comm Err Event log Be sure to read the help file For info on this program located in the root of the this example folder No baseboards enumerated pins state is shown in real time on the statistics status bar located at the bottom of the Streaming tab EEPROM Access Select the EEPprom tab The controls on this tab allow the contents of the onboard EEPROM to be queried or changed The onboard EEPROM is used for non volatile storage of module identification strings digital calibration coefficients for each of the A D channels and for a calibration coefficient for the reference clock for the onboard PLL These values are determined during factory calibration and need not normally be changed by the user X3 SD16 User s Manual Debugging Select the Debug tab The controls on this tab support a few low level debug operations to be performed debug script may be executed at any time to perform low level register fetches or stores to exercise custom FPGA firmware or determine the current hardware state Unlike the stream scripts described earlier this scr
127. nt In this example each received packet is logged to a disk file The packet header and the body are written into the file which implies that a post analysis tool such as BinView will be used to parse channelized data from the file Alternately custom applications may use the Innovative PacketDeviceMap object to conveniently extract channelized data from a packet data source Stop streaming when both Channels have passed their limit if Settings AutoStop amp amp IsDataLoggingCompleted amp amp Stopped Stop counter and display it double elapsed Clock Stop StopStreaming UI AfterStreamAutoStop UI Log Stream Mode Stopped automatically UI Log std string Elasped S FloatToString elapsed Packets are processed until a specified amount of data is logged or the GUI Stop button is pressed Auto analyze and retrigger in framed mode if Settings Framed return if Settings ExternalTrigger 0 amp amp Settings AutoTrigger int64 samples FBlockCount Settings PacketSize int triggers static cast int samples Settings FrameCount if triggers FTriggered SoftwareTrigger In the event that were operating in framed trigger mode the example code re asserts a software trigger each time a frames worth of data packets have been received If we re in continuous mode no action need be performed to sustain data flow EEProm Access Each PMC module c
128. ny documentation files for the project Open the index html file in the directory with a web browser to see the available files and a description of the contents Examples This directory and its subdirectories contain the projects source and example programs for the board Hardware This directory contains files associated with programming the board Logic and any logic images provided X3 SD16 User s Manual 24 About the X3 XMC Modules In this chapter we will discuss the common features of the X3 module family Specifics on each module are covered in later chapters X3 XMC Architecture The X3 XMC modules share a common architecture as well as many features such as the PCI Express interface data buffering features the Application Logic and other system integration features This allows the X3 XMC modules to utilize common software and logic firmware while providing unique analog and digital features Figure 7 X3 XMC Family Block Diagram The X3 XMCs have a variety of analog and digital IO front ends suited to many applications X3 SD16 User s Manual 25 Table 1 X3 Family X3 XMC Features FPGA Applications X3 SD 16 channels of 24 bit 216 ksps A D gt 100 Xilinx Spartan3 1M Vibration measurement dB 2M option acoustics wide dynamic range applications X3 SDF 4 channels of variable resolution speed A Xilinx Spartan3 1M Vibration measurement D up to 24 bit 5 M
129. oadProgress event Percent Process progress events are issued to give a percentage progress of the entire operation These event are handled by HandleProgress This handler calls a UI method UpdateLogicLoadProgress where a Progress bar control is updated to give a visual effect of the loading progress void ApplicationIo HandleLoadComplete ProcessCompletionEvent amp event UI gt Log Load completed ok DisplayLogicVersion X3 SD16 User s Manual 46 Finally the logic loader issues a process completion event when the load is complete This event is handled by HandleLoadComplete as shown above In this case all we do is update the UI so the user can see that the logic configuration is complete and application status is idle In other cases this could trigger the application to automatically perform additional tasks Starting Data flow After downloading interface logic user can setup clocking and triggering options The stream button then can be used to start streaming and thus data flow bool ApplicationIo StartStreaming Set up Parameters for Data Streaming First have UI get settings into our settings store UI GetSettings Before we start streaming all necessary parameters must be checked and loaded into option object UI gt GetSettings loads the settings information from the UI controls into the Settings structure in the Applicationlo class if FStreamConnected
130. ommunicate with the PLL that specifies a read or write access the PLL register address and the data byte to transfer For reads the data byte is a don t care The 24 bit word is as follows PLL register address Table 7 PLL Interface Word Format Writes Writes to the PLL are pokes to register located in the system memory at BARI OxA The data value is the 32 bit word as described above BARI 0xA X 00801C12 Write to PLL register 0 1 value 0x12 Table 8 PLL Read Sequence Reads Reads from the PLL require a two step process consisting of first a write to the PLL register specifying a read at an address followed by a read from the PLL register that returns the value of the PLL register specified by the address in the PLL word The PLL is read is a single byte For reads the PLL must be written to with a bit 23 as 1 and the address that 15 to be read then read from the PLL register For example a read to PLL register X 40 would be performed as X3 SD16 User s Manual 69 Read Write Value Comments BARI 0xA 00804000 Set up a read from PLL address X 40 BARI 0xA X x01303xx See format below Table 9 PLL Read Sequence The PLL readback word has the following format The PLL read must be performed before any additional writes are performed 0000000 1303 Table 10 PLL Read Word Notes About the PLL Configuration The PLL must be initialized through software be
131. ontains an IDROM region that can be used to write information associated with the module In the next line of code we make a call to Malibu method IdRom which returns an object that acts as interface to that region The following methods illustrate how to write and read information from IDROM StoreToRom and ReadRom are the two IdRom methods used to save and retrieve data to from memory X3 SD16 User s Manual 35 void ApplicationIo WriteRom Module IdRom Name Settings ModuleName Module IdRom Revision Settings ModuleRevision Module Clock ReferenceCalibrationFactor Settings PllCorrection size t range 0 range Ranges range for size t ch 0 ch lt Channels Module Input Gain range ch Settings Gain range ch Module Input Offset ch Settings AdcOffset range ch Module Input Calibrated range Settings Calibrated Module IdRom StoreToRom for r void ApplicationIo ReadRom Module IdRom LoadFromRom Settings ModuleName Module IdRom Name Settings ModuleRevision Module IdRom Revision Settings PllCorrection static cast float Module Clock ReferenceCalibrationFactor bool calibrated true for size t range 0 range lt Ranges range for size t ch 0 ch lt Channels ch Settings Gain range ch Module Input Gain range ch Settings Offset range ch Module Input Offset range
132. p data 10 8 0 12 X 1303000 amp 000 amp mq overflow 0 15 13 0 16 X 1303 amp adc overrange 23 17 0 24 DAC Underflow 35 25 Unused 0 Table 21 Alert Packet Format Since alert packets contain status words such as temperature for each packet a software alert can essentially be used to read temperature of the module and so that it can be recorded Software Support Applications have different needs for alert processing Aside from the bulk movement of data most applications require some means of handling special conditions such as post processing upon receipt of a stop trigger or closing a driver when an acquisition 18 completed When the alert system is enabled the module logic continuously monitors the status of the peripheral usually analog hardware present on the baseboard and generates an alert whenever an alert condition is detected It s also possible for application software to generate custom alert messages to tag the data stream with system information The Malibu software provides support for alert configuration and alert packet processing See the software manual for usage Tagging the Data Stream The Alert Log can be used to tag the data stream with system information by using software alerts This helps to provide system level correlation of events by creating alert packets in the data stream created by the host software Alert packets are then created by the X3 module and are in the stream of
133. pear in the running application User Interface This application has four tabs Each tab has its own significance and usage though few could be inter related these tabs share a common area which displays messages and feedback throughout the operation of the program Logic Tab lolx Configure Tab Configure setup stream Eeprom Debug Module Busmaster Size MB Target As soon as the application is launched device driver is k s F s cus opened and hardware is attached to the selected target FEX Logi Fle number In this tab we configure user interface logic The target board number is set to zero The order of the targets is determined by the location in the PCI bus so it will remain unchanged from run to run While application is being launched the device driver is automatically opened for the baseboard and internal 0 0 resources are allocated for use At this point stream is Be Ste ta reac For G S program foci He fot en oe this exam fors simply connected to the board and board has been reset to be in known good state Also if ID ROM is properly initialized module name and revision in addition to the Device Opened message is displayed in the message box Next we load the desired user interface logic The user logic for the module must be loaded at least once per X3 SD16 User s Manual 38 session it remains valid until power is
134. ple and enable output channels fragment above programs the direction of these DIO bits in accordance with the settings from the GUI FStreaming true X3 SD16 User s Manual 48 Set Decimation Factor int factor Settings DecimationEnable Settings DecimationFactor 0 Module Output Decimation factor Sample clocks will be affected by the decimation factor used data will be played by the DAC s but at a slower rate if decimation 15 enabled All channels trigger together Module Output ExternalTrigger Settings ExternalTrigger 1 Frame count in units of packet elements if Settings Framed Module Output Framed Settings FrameCount else Module Output Unframed Samples will not be played until the channels are triggered Triggering may be initiated by a software command or via an external input signal to the Trigger SMA connector The code fragment above selects the trigger mode enum IUsesX3Alerts AlertType Alert UsesX3Alerts alertTimeStampRollover UsesX3Alerts alertSoftware UsesX3Alerts alertWarningTemperature UsesX3Alerts alertPllLost UsesX3Alerts alertOutputFifoUnderrun UsesX3Alerts alertOutputTrigger for unsigned int 0 lt Settings AlertEnable size 1 Module Alerts AlertEnable Alert i Settings AlertEnable i true false The fragment above enables alert generation by the module The GUI control includes check boxes for each of th
135. ple rate during acquisition However if the clock source is external then the Output KHz control is used to inform the program of your intended external sample rate In that case you are expected to supply a clock running at the rate listed in the Clock Source KHz control to the external clock input connector on the module Active Channels Group The X3 modules support simultaneous playback to all their channels Decimation Group These controls govern the behavior enable the decimation logic When enabled the DAC s update rate will be affected thus the interrupt to the Host PC will be decreased All waveform samples will be deliver to the DAC s but the DAC s will be clocked at a slower rate Trigger Group Playback may be TRIGGERED using an external signal or via software The Trigger Source list control provides the means of selection Triggers act as a gate on data flow no data flows until a trigger has been received Triggers may be initiated via software or hardware depending on the Trigger Source control If software the application program must issue a command to initiate data flow If hardware a signal applied to the external trigger connector controls data flow Triggers are modal depending on the Trigger Mode control In Unframed mode triggers are level sensitive and data flow proceeds while the trigger is in the high active state and stops while the trigger is in the low inactive state This mode is ideal
136. pter card in PC running testbed software using FrameWork Logic Five minutes were allowed for thermal stabilization Table 24 X3 SD16 Analog Input Performance Summary Parameter Measured Units Test Conditions Analog Input Flatness 1 0 to 70 kHz Settling Time to 596 1 ms 1 01 kHz 10Vp p square wave digital filter in the A D limits settling time See graph Input Ranges 2 10 20 Vp p Standard on X3 SD106 calibration results may limit input range to 9596 of full scale nominal Offset 0 5 mV Factory calibration average of 64K samples Gain 0 02 of FS Factory calibration average of 64K samples Ground Noise 620 uVp p Input Grounded sample rate 144 ksps 64k samples X3 SD16 User s Manual 86 Parameter Measured Units Test Conditions Ground Noise 120 dB Input Grounded sample rate 144 ksps 64k samples FFT no averaging SFDR 103 dB 1 01 kHz sine input 1 9Vp p differential input 64K point FFT S N 85 9 dB 1 01 kHz sine input 1 9Vp p differential input 64K point FFT THD 119 9 dB 1 01 kHz sine input 1 9Vp p differential input 64K point FFT ENOB 14 bits 1 01 kHz sine input 1 9Vp p differential input 64K point FFT Crosstalk 100 dB 1 01 kHz 19Vp p input cable included all channels Common Mode Rejection 69 dB 1 01 kHz 19Vp p differential tested with MDR68 cable and screw terminal Intermodulation Distortion 116 dB 900 Hz
137. r and a set of support libraries from Innovative Table 12 Development Tools Processor Development Environment Innovative Project Directory Toolset Host PC Borland Developers Studio Malibu Examples Snap Bcb Windows Ea Microsoft Visual Studio 2008 Examples Snap VC9 Examples Snap Common Common Host Code Processor Development Environment Innovative Project Directory Toolset Host PC DialogBlocks Malibu Examples Snap DialogBlocks Common Host Code Examples Snap Common On the host side the Malibu library 15 source code compatible with the above environments The code that performs much of the actual functioning of the program outside of the User Interface portion of the program is therefore common code Each project uses the same file to interact with the hardware and acquire data X3 SD16 User s Manual 20 Program Design The Snap example is designed to allow repeated data reception operations on command from the host As mentioned earlier received data can be saved as Host disk files When using modest samples rates data can be logged to standard disk files However full bandwidth storage of multiple A D channels can require up to 80 MB s capacity to a dedicated RAIDO drive array partitioned as NTFS for data storage may be required The example application software is written to perform minimal processing of received data and is a suitable templa
138. ration coefficients to the EEPROM is provided EEPROM exe New coefficients are simply typed into the offset and gain field for each channel Calibration coefficients for gain should not be greater than 1 1 and offset 0x8000 If the calculated coefficients are larger than this they are either wrong or the channel is damaged X3 SD16 User s Manual 84 Performance Data Power Consumption The X3 SD16 requires the following power for typical operation with when using the FrameWork Logic This typical number assumes a 107 MHz system clock rate and all analog channels active for the application logic Table 22 X3 SD16 Power Consumption Voltage Maximum Condition Typical Typical Derived from Supplies these Devices Allowed Current Power Current A Required A W 3 3V 5A Before 1 16 3 8 Direct connect to devices on card power recommended application the PCIe host supplies use 3 3V as logic is loaded source 24C 3 3V 5A After 1 28 4 2 Direct connect to devices on card power recommended application the PCIe host supplies use 3 3V as logic 15 loaded source 27C 3 3V 5A 144 ksps 1 99 6 6 Direct connect to devices on card power recommended sample rate the PCIe host supplies use 3 3V as 30 card source no loading for D A temperature output or digital IO 12V 0 0 Not required Surge currents occur initially at power on and after application logic initializa
139. removed from the board Use Configure button is to load the logic from an BIT file Setup Tab Configure Setup stream Eeprom Debug 8 Bl B This tab has a set of controls that hold the Analog Es Clock DJA Config Decimation Trigger parameters for data playback These settings are Source Freg KHz Channels Enable Auto External Delay s Source Mode Frame Count delivered to the target and configure the target Internal ch T emm when streaming is initiated via controls on the Stream tab described in the next section Communications Packet Size Alerts Waveform Digital Config Time Stamp Type Dio The setup tab contains a large number of controls AU EM Trende Sine pe PLL Lost p Amplitude 5 used to configure the on board timebase alert Output Underrun Kano Output Trigger File 5 notifications analog channel selection range and triggering etc Each of these controls 1s described below Front Panel gt Event Log Clock Group The module features an on board AD9510 PLL which may be used as a sample clock during analog acquisition Alternately an external sample clock may be used The Clock Source radio control governs which timebase is used as the analog sample clock If the internal PLL is selected the sample rate entered in the Output Khz edit control is used to program the PLL to generate the specified sam
140. ret nnne nnne nnne 90 Table 29 X3 SD16 Analog Output Performance Summary sesesssssssesseseeeeeeeeene nennen nennen nnne nnne nens 92 T ble 30 X3 XMC Connector PIS Pino t eH UB IRE OR D e D Pede 99 Table 31 PI5 Signal Descriptions RIETI anes URS RENTUR GA 100 Table 32 X3 Secondary Connector P16 Pinout eesssssssesseseeseeeeee eene enne nennen nennen enne enne nnn 102 Table 33 P16 Signal Descriptions rss tere e RUE ERR EUG 103 Table 34 Xilinx JTAG Connector nennen nene 105 X3 SD16 User s Manual List of Figures Figure 1 Vist Verification Dialog niet naa AA tie eae rape donee pU EE ea e 15 Figure 2 Innovative Install Program e Leod detecte be election RR dan again sachet 16 Figure 3 Progress is shown for each 8 tne tete 17 Figure 4 ToolSet registration formi diese suero nee dee p e e PEL qua Dese edes 18 Figure 5 BusMaster configuration RUE pete tec pev donee 19 Figure 6 Installation complete ie e Ae eel ne ola EP e RI 19 Figure 7 X3 Family Block 25 X3 Computing Core Block 1 incisos n cer
141. rything is plugged in correctly Thank you from Innovative Integration 1 805 578 4260 www innovative dsp com Shutdown Now Shutdown Later Figure 6 Installation complete Click the Shutdown Now button to shut down your computer Once the shutdown process is complete unplug the system power cord from the power outlet and proceed to the next section Hardware Installation Hardware Installation Now that the software components of the Development Package have been installed the next step 1s to configure and install your hardware Detailed instructions on board installation are given in the Hardware Installation chapter following this chapter IMPORTANT Many of our high speed cards especially the PMC and XMC Families require forced air from a fan on the board for cooling Operating the board without proper airflow may lead to improper functioning poor results and even permanent physical damage to the board These boards also have temperature monitoring features to check the operating temperature The board may also be designed to intentionally fail on over temperature to avoid permanent damage See the specific hardware information for airflow requirements X3 SD16 User s Manual 19 After Power up After completing the installation boot your system into Windows Innovative Integration boards are plug and play compliant allowing Windows to detect them and auto configure at start up Under rare circ
142. s Each IO device directly connects to the application FPGA on the X3 module providing tight coupling for high performance Real time IO The FPGA logic implements an interface to each device that connects them to the X3 SD16 User s Manual 27 controls and data communications features on the module Support features such as sample triggering and data analysis are implemented in the logic to provide precise real time control over the data acquisition process X3 Computing Core Block Diagram The X3 module architecture is really defined by the features in the logic that connect the IO devices to the Velocia packet system For data from IO devices such as A Ds the data flows from the IO interface and is then enqueued in the multi queue buffer The packetizer then creates data packets from the data stream that are moved across the data link to the PCIe interface Packets to output devices travel in the opposite direction from the link to the deframer and into the multi queue data buffer The output IO such as a DAC then consumes the data from the queue as required The Alert Log monitors error conditions and important events for management of the data acquisition process The host interacts with the X3 computing core using the packet system for high speed data and over the command channel The packet system 1s the main data channel to the card and delivers the high performance real time data capability of moving data to and from the mod
143. s Manual 22 Trigger Group Acquisition may be triggered using an external signal or via software The Trigger Source radio control provides the means of selection Triggers act as a gate on data flow no data flows until a trigger has been received Triggers may be initiated via software or hardware depending on the Trigger Source control If software the application program must issue a command to initiate data flow If hardware a signal applied to the external trigger connector controls data flow Triggers are modal depending on the Trigger Mode control In Unframed mode triggers are level sensitive and data flow proceeds while the trigger is in the high active state and stops while the trigger 1s in the low inactive state This mode is ideal for conventional data acquisition applications In Framed mode triggers are rising edge sensitive Upon detection of each edge Trigger Frame Count samples are acquired from all active channels then acquisition terminates until the next trigger edge is detected If Trigger Frame Auto Retrig is checked and the Trigger Source is software the application automatically re triggers upon completion of processing of the previous packet This mode is ideal for application such as spectral analysis using fixed input buffers submitted to FFTs Digital I O Group These controls govern the configuration of the P16 DIO port on the module The DIO port can be configured for input or output on a byte
144. se of this LED 15 to indicate that the application logic has been configured and to blink when an over temperature condition occurs Custom logic designs can use it for any purpose When using the stock firmware the state of user logic LED D5 can be controlled using the Innovative X3 SD Led property JTAG Scan Path The X3 modules have a scan path for the Xilinx devices on the module This 15 used for logic development tools such as Xilinx ChipScope and System Generator and for initial programming of the PCI FPGA configuration FLASH ROM There are three devices in the scan chain the Xilinx FLASH ROM Spartan 3E 250K used for PCI control and the Spartan 3 3A application logic When the devices are identified in the scan chain you will see these devices in this order Table 11 X3 Modules FPGA JTAG Scan Path JTAG Device Module Device Function Number 0 X3 Xilinx 025 FLASH ROM PCI FPGA Spartan3E logic configuration ROM 1 X3 Xilinx Spartan3E 250 FPGA Control FPGA for PCI XC3S250E 4FTG256C Interface X3 SD16 User s Manual 39 Device Module Device Function Number 2 X3 SD X3 SDF Xilinx Spartan3 1000 FPGA Application Logic XC3S1000 4FGG456C optional 2M device could be installed here All others Xilinx Spartan3A DSP 1800 FPGA XC3SD1800 4FGG676C optional 3 4M device could be installed here FrameWork Logic Many of the stan
145. sed to write information associated with the module In the next line of code we make a call to Malibu method IdRom which returns an object that acts as interface to that region The following methods illustrate how to write and read information from IDROM StoreToRom and ReadRom are the two IdRom methods used to save and retrieve data to from memory void ApplicationIo WriteRom Module IdRom Name Settings ModuleName Module IdRom Revision Settings ModuleRevision for int ch 0 ch Channels ch Module Output Gain ch Settings DacGain ch Module Output Offset ch Settings DacOffset ch Module Output Calibrated Settings Calibrated Module IdRom StoreToRom void ApplicationIlo ReadRom Module IdRom LoadFromRom Settings ModuleName Module IdRom Name Settings ModuleRevision Module IdRom Revision for int ch 0 ch lt Channels ch Settings DacGain ch Module Output Gain ch Settings DacOffset ch Module Output Offset ch Settings Calibrated Module Output Calibrated A one second timer handler is used to calculate data rates and provide status on Digital I O temperature etc It is also to fire the very first trigger If the module is configured for Framed Mode then only one frame will be played If the module is configured to run in Un Framed Mode then one trigger is sufficient until the module is instructed to stop streaming void Applicat
146. sible solely for real time tasks Much the same as a dedicated video subsystem is required for adequate display performance dedicated hardware for real time data collection and signal processing is needed This is precisely the focus of our baseboards a high performance state of the art dedicated digital signal processor coupled with real time data I O capable of flowing data via a 64 bit PCI bus interface The hardware 1s really only half the story The other half is the Malibu software tool set which uses state of the art software techniques to bring our baseboards to life in the Windows environment These software tools allow you to create applications for your baseboard that encompass the whole job from high speed data acquisition to the user interface Finding detailed information on Malibu Information on Malibu is available in a variety of forms e Data Sheet http www innovative dsp com products malibu htm e On line Help nnovative Integration Technical Support nnovative Integration Web Site www innovative dsp com Online Help Help for Malibu is provided in a single file Malibu chm which is installed in the Innovative Documentation folder during the default installation It provides detailed information about the components contained in Malibu their Properties Methods Events and usage examples An equivalent version of this help file in HTML help format is also available online at http www innovative dsp com
147. st be copied from the system bus master pool into an application buffer The preceding code copies the packet into the local Buffer called Packet 4 Process the data packet PacketBufferHeader PktBufferHdr Packet size t Channel PktBufferHdr PeripherallId Discard packets from sources other than analog devices if Channel gt Channels return Each Buffer consists of a header and a body of data The header may be interrogated to determine the data source In the fragment above packets containing peripheral IDs greater than the number of enabled channels are discarded Consequently alert packets are not retained or processed Calculate transfer rate in KB s double Period Time Differential if Period FBlockRate Packet DG SizeInBytes Period 1 0e3 The code fragment above calculates the nominal block processing rate The AveragedRate object Time maintains a moving averaged filtered rate This rate is stored in FBlockRate for use by display method of the GUI if Settings LoggerEnable amp amp Logger Logged Start counter Clock Start Std stringstream msg msg Packet size Packet Size samples UI Log msg str X3 SD16 User s Manual 34 enabled log the data stream if Settings LoggerEnable Settings PlotEnable if FBlockCount BlocksToLog Logger LogWithHeader Packet Count the blocks gone by on each Channel FBlockCou
148. ster If the internal clock is used the data 1s latched at the beginning of any read from the port Data read from output bits is equal to the last latched bit values 1 e the last data written to the port by the host Digital I O port pins are pulled down to digital ground within the logic device Consequently the state of the DIO pins do not change as power is applied to the PC during system start up The pulldown resistor is about 8K ohms External signals connected to the digital I O port bits or timer input pins should be limited to a voltage range between 0 and 3 3V referenced to ground on the digital I O port connector Exceeding these limits will cause damage to the X3 module Digital I O Timing The following diagram gives timing information for the digital I O port when used in external readback clock mode see above for details This data is derived from device specifications and is not factory tested Extemal Readback Clock Input data V Data Valid V Figure 10 Digital I O Port Timing X3 SD16 User s Manual 33 Table 7 Digital I O Port Timing Parameters Digital IO Electrical Characteristics The digital IO pins are LVTTL compatible pins driven by 3 3V logic The DIO port connects directly to the application FPGA The DIO input clock is LVDS a differential input Warning the DIO pins are NOT 5V compatible Input voltage must not exceed 3 6V Parameter Value Notes Input Volta
149. support onlinehelp Malibu Innovative Integration Technical Support Innovative includes a variety of technical support facilities as part of the Malibu toolset Telephone hotline supported is available via X3 SD16 User s Manual 12 Hotline 805 578 4260 8 00 5 00 PM PST Alternately you may e mail your technical questions at any time to techsprt innovative dsp com Also feel free to register and browse our product forums at http forum iidsp com which are an excellent source of FAQs and information submitted by Innovative employees and customers Innovative Integration Web Site Additional information on Innovative Integration hardware and the Malibu Toolset is available via the Innovative Integration website at www innovative dsp com Typographic Conventions This manual uses the typefaces described below to indicate special text Typeface Meaning Text in this style represents text as it appears onscreen or in code It Source Listing also represents anything you must type Boldface Text in this style is used to strongly emphasize certain words Text in this style is used to emphasize certain words such as new Emphasis terms Cpp Variable Text in this style represents variables Text in this style represents C identifiers such as class function Cpp Symbol or type names KEYCAPS Text in this style indicates a key on your keyboard For example Press ESC to exit a menu Text i
150. t Connector JP eoi e ee ertet e et deeds tere tree 96 XMG PIS Connector eui ute ete diae n ee Me re P epe RM ERE DES 97 XMCG P T6 Connector o e reete e e Der a RR Re ed ipe debet e n m ape RU etu RUE 101 Note PXI Express signals are only available when PXIE adapter is used ees 104 Xilinx JTAG COnectots oreet ec ea ER epe ERA 105 Mech nicals 4 5 25 ok saree tetas recedat usi e het ier DER EHE EROR 106 Applets for the X3 Modules ete tese ooa ive qe deed ect age e Ue RS 108 E e E AAE E A E a a E ET E E a EE EA E E E AE ES 108 unn d LECHE 109 5 eee deb oO e bt UE REI puente e C RUE 110 T Vor cac NU Common Applets dts ei ene UR E D ERE UE E E ee RR D e e aes 111 Registration Utility IR 111 Reserve Memory Applet 112 Data Analysis Applets USER I AREE URP 112 Binary File Viewer Utility 6 enne enne nennen nente nennen eren enne 112 X3 SD16 User s Manual Lis
151. t involves first configuring the port using the Config operator This sets the byte direction and the clock mode The port is then ready for read write configurations to each port Hardware Implementation Digital I O port activity is controlled by the digital I O configuration control and data register Port direction is controlled by the configuration control register Bit Function 0 DIO bits 7 0 direction control 0 default 1 DIO bits 15 8 direction control 0 input default 2 DIO bits 23 16 direction control 0 input default 3 DIO bits 31 24 direction control 0 input default 4 DIO bits 39 32 output enable 0 input default 5 DIO bits 43 40 output enable 0 input default X3 SD16 User s Manual 32 Bit Function 30 6 31 Sample DIO inputs when DIO EXT CLK is true otherwise always sample 0 sample always default Figure 8 DIO Control Register BAR1 0x14 Port Address DIO L BARI 0x13 DIO H BARI 0x16 Figure 9 Digital IO Port Addresses Data may be written to read from the digital I O port using the digital I O port data registers Data written to ports bits which are set for output mode will be latched and driven to the corresponding port pins while data written to input bits will be ignored The input DIO may be clocked externally by enabling the external digital clock bit in the appropriate configuration regi
152. t of Tables Table L X3 XMCG Family etudes tet eO et VEN EN aid um 26 T ble2 X3 XMG Family Petipherals tee e eh ede o ERI Ia 27 T ble 3 X3 Computing Gore ei I tte tus estate cq radiata iss 27 Table 4 PCI Express standards Compli fGe UD Ee he Rt d bete tate iens 29 Table 5 Interfaces from PCI Express to Application 1 enne 30 Table 6 IUsesExtendedDioPort Class Operations sessi nnne 32 Table 7 Digital I O Port Timing Parameters eese rnnt 34 Table 8 Digital IO Bits Electrical 15 0000 34 Table 9 Digital IO Clock Input Electrical Characteristics nennen nnne 35 Table 10 Temperature Alarms iste eR RE ER EUR ERE ENIRO RAE TURA Ga 37 Table 11 X3 Modules FPGA JTAG Scan eie tete ete 39 Table 12 Development ER EU GG IU IR EE EH EAE REEL RR HERE 20 Table 13 Development Tools sede evi EU GUN DATEI C VERRE ENERO STERN 37 Table 14 X3 SD106 A D Features dt eod cam ede LP RE pls TG enda erp ed ot D EE C ERO De 55 Table 15 A D Conversion Coding ccceccesccessesseeseessceseeseeesecseeesecseeesecneesecaecsecaesseeaecseceaecaeeeaeceaesseseeecaeseseeaeeceaeeeseeeesnees 56 Table 16 A D Clock Rate Requ
153. t this amp ApplicationIlo HandleAfterStreamStart Module OnAfterStreamStart Synchronize Module OnAfterStreamStop SetEvent this amp ApplicationIo HandleAfterStreamStop Module OnAfterStreamStop Synchronize Similarly HandleBeforeStreamStart HandleAfterStreamStart and HandleAfterStreamStop handle events issued on before stream start after stream start and after stream stop respectively These handlers could be designed to perform multiple tasks as event occurs including displaying messages for user These events are tagged as Synchronized so Malibu will marshal the execution of the handlers for these events into the main thread context allowing the handlers to perform user interface operations The Stream object manages communication between the application and a piece of hardware Separating the I O into a separate class clarifies the distinction between an I O protocol and the implementing hardware In Malibu high rate data flow is controlled by one of a number of streaming classes In this example we use the events of the PacketStream class to alert us when a packet arrives from the target When data packet is delivered by the data streaming system OnDataAvailable event will be issued to process the incoming data This event is set to be handled by HandleDataAvailable After processing the data will be discarded unless saved in the handler Similarly OnDataRequired event is handled by HandleDataRequired Confi
154. t will occur on all channels since the channels are updated as a group The logic detects data underrun conditions to the DAC devices and can provide a warning of this condition The underrun is used to trigger an alert in the logic that notifies the application when this error condition has occurred The alert message shows when the underrun occurred in system time DAC Update Rates The PCM1681 supports update rates from DC to 192 KHz on the X3 SD16 module At maximum rate the transfer rate to the DACS is 192 000 samples sec 16 channels 4 bytes sample 12 288 MB s Large channel count systems may require attention to the system activity to support full rates to all channels For most PCs up to 4 modules should be trouble free For more than 4 modules consideration should be given to the overall system activity and a test run to verify performance The PCM1681 requires a clock that is either a 128 or 256 multiple of the output data rate sample rate as set by the clock mode of the DAC Parameter Min Max Units Sample rate 0 39 192 Ksps D A Clock Rate 25 ns Clock Divisor 128 Mode 000 256 Mode 000 clks sample PLL Clock 0 12 280 MHz D A limited to 40 MHz Table 19 D A Clock Rate Requirements When the PLL is used the sample clock has a minimum rate of 1 2 kHz Sample rates lower than 1 2 kHz are supported using decimation in the logic Note that the PLL can generate clocks up to 280 MH
155. tStream object encapsulates supported board specific operations Scripter object can be used to add a simple scripting language to the application for the purposes of performing hardware initialization during FPGA firmware development Buffer class object can be used to access buffer contents In addition under the Open method we hook up event handlers to various events Hook script event handlers Script OnCommand SetEvent this amp ApplicationIo HandleScriptCommand Script OnMessage SetEvent this amp ApplicationlIo HandleScriptMessage Configure Module Event Handlers Module Logic OnFpgaFileReadProgress SetEvent this amp ApplicationlIo HandleProgress Module Logic OnFpgaFileReadComplete SetEvent this amp ApplicationIo HandleParseComplete Module Logic OnFpgaParseProgress SetEvent this amp ApplicationIo HandleProgress Module Logic OnFpgaParseComplete SetEvent this amp ApplicationIo HandleParseComplete Module Logic OnFpgaParseMessage SetEvent this amp ApplicationIo HandleLoadError Module Logic OnFpgaLoadProgress SetEvent this amp ApplicationIlo HandleProgress Module Logic OnFpgaLoadComplete SetEvent this amp ApplicationIo HandleLoadComplete Module Logic OnFpgaLoadMessage SetEvent this amp ApplicationIlo HandleLoadError This code attaches script event handlers and X3 module logic loader s informational event handlers to their corresponding events Malibu has
156. te If you use an external clock you MUST input input the sample rate multiplied by the clock divisor For example a 100 kHz sample rate requires 100 000 samples sec 256 clocks sample 25 6 MHz X3 SD16 User s Manual 58 Be sure that your A D mode is set to either high resolution divisor 512 for sample rates below 52 kHz or high speed divisor 256 for rates at or above 52 kHz Supporting software functions in the Malibu library are used to configure the sample clock mode and decimation to achieve the desired sample rate Since the PLL configuration is somewhat complex it is recommended that these functions be used for most applications D A Conversion Features D A Converters The X3 SD16 has 16 channels of 24 bit D A conversion at up to 144 kHz consisting of two Texas Instruments PCM1681 DACs The two 1681 devices are configured so that all channels update simultaneously The PCM1681 is a sigma delta converter architecture Feature Description Outputs 16 independent Output Range 2V to 2V Output Drive Current 10 mA max D A Devices Texas Instruments PCM1681 Output Format 2 s complement 24 bit Number of DAC Devices 16 simultaneously updated Updated Rate DC 192 kHz Must be equal to A D clock rate Sample Clock Rates from PLL 1 2 kHz to 280 MHz Calibration Factory calibrated for gain and offset errors Non volatile EEPROM coefficient memory Table 17
157. te for high bandwidth applications The example uses various configuration commands to prepare the module for data flow Parametric information is obtained from a Host GUI application but the code is written to be GUI agnostic board specific I O is performed within the Applicationlo cpp h unit Data is transferred from the module to the Host as packets of Buffers The Host Application The picture to the right shows the main window of Snap example This form is from the designer of the Borland Turbo C version of the example It shows the layout of the controls of the User Interface The timer pop up menu and folder icons to the upper right are non visual components in Builder Timer controls timer ticks and pop up menu facilitate user to select channels on right click where the folder controls the posting of a File Open Dialog box They will not appear in the running application User Interface This application has four tabs Each tab has its own significance and usage though few could be inter related these tabs share a common area which displays messages and feedback throughout the operation of the program Logic Tab Configure Tab As soon as the application is launched device driver is 2 Capture Example opened and hardware is attached to the selected target Configure Setup Stream Zbt Ram EEProm Debug Driver number In this tab we configure user interface logic Bande M pen Clos
158. te or read rate to about 200 kHz The limitation on this rate is the slow speed of the command channel itself Again custom logic implementations can achieve much higher data rates The X3 FrameWork Logic user Guide details logic supporting the digital IO port and gives the pin information for customization Serial EEPROM Interface X3 modules have a serial EEPROM for storing data such as board identification calibration coefficients and other data that needs to be stored permanently on the card This memory is 16K bits in size Functions for using the Serial EEPROM are included in the Malibu Toolset and example programs that allow the software application programmer to easily write and read from the memory without having to program the low level interface Use the baseboard IdRom method to obtain a reference to the internally managed IusesPmcEeprom object as shown below Open the module Innovative X3 SD Module Module Target 0 Module Open Create a 50 32 bit word section at offset zero in ROM user space PmcIdromSection Sectionl Module IdRom Rom PmcIdrom waUser 0 50 Create a 50 32 bit word section at offset 50 in ROM user space PmcIdromSection Section2 Module IdRom Rom PmcIdrom waUser 50 50 Write to ROM for int i 0 i lt 50 i Sectionl AsInt i i 2 Sectionl StoreToRom for int i 50 i lt 100 i X3 SD16 User s Manual 35 Section2 AsFloat i static cast float
159. ternal Sample Clock Timing nnne nnne enne 71 Table 13 Table t gt Trigger Modes ure Rate tee ii EAR RERO e PNE 72 Table T4 External Trigger Eee t e etes ee I ie a 73 Table 15 External Trigger Electrical Characteristics nennen nnnm 73 Table 16 Sync Control Bit Register Ox e Sa I teet be Ra Wd St ade n P ea ee 74 Syne Signal uo eee et RE d ee add NIENTE 75 Table 18 Sync Signal Electrical Characteristics 75 Table 19 Reduced Power Options eed em HR e ee i E E 79 Table 20 Alert Types ccc accederet e RR UD ARE UR E WE UE dE e i e pipe eee eiut 80 Table 21 Alert Packet Eorma t eedem eene an dde n e b ER etait 81 Table 22 X3 SD16 Power Consumption nie em ra RR HE Re e asi b e d HEEL eo 85 Table 23 X3 SD16 Environmental Limits eese D RR ER Ee EE e ER P e 86 Table 24 X3 SD16 Analog Input Performance Summary eene nennen innen nnne 86 Table 25 A D Signal Quality vs Sample 0 44 00 eene eE EEKE 88 Table 26 A D Signal Quality for 20V Input Range nennen nnne nnne 90 X3 SD16 User s Manual Table 27 A D Signal Quality for 10V Input 2 2 90 Table 28 A D Signal Quality for 2V Input Range enne nennen nennen ne
160. ther Module Input ExternalTrigger Settings ExternalTrigger 1 Frame count in units of packet elements if Settings Framed Module Input Framed Settings FrameCount else Module Input Unframed Samples will not be acquired until the channels are triggered Triggering may be initiated by a software command or via an external input signal to the Trigger SMA connector The code fragment above selects the trigger mode enum IUsesX3Alerts AlertType Alert IUsesX3Alerts alertTimeStampRollover IUsesX3Alerts alertSoftware IUsesX3Alerts alertWarningTemperature IUsesX3Alerts alertPllLost IUsesX3Alerts alertInputFifoOverrun IUsesX3Alerts alertInputTrigger IUsesX3Alerts alertInputOverrange for unsigned int i 0 i Settings AlertEnable size 1 Module Alerts AlertEnable Alert i Settings AlertEnable i true false The fragment above enables alert generation by the module The GUI control includes check boxes for each of the types of alerts of which the module is capable The enabled state of the check boxes is copied into the Settings AlertEnable array This code fragment applies the state of each bit in that array to the Alerts sub object within the module During streaming an alert message will be sent to the Host tagged with a special alert packet ID PID to signify the alert condition Start Streaming Stream Start UI gt Log Stream Mode started UI gt Status Stream Mode st
161. thod Malibu method Close is then used to detach the module from the hardware and release its resources Logic Loading The user interface logic for the module must be loaded at least once per session it remains valid until power is removed from the board In the following code we show how to browse and configure the desired logic In the UI when the logic browse button is pressed LogicLoadBrowseBtnClick method gets called as shown below void _ fastcall TMainForm LogicLoadBrowseBtnClick TObject Sender Std auto ptr TOpenDialog Dialog new TOpenDialog NULL Dialog gt Filter Logic File bit bit All Files Dialog gt Title Select FPGA Logic File if LogicFilenameEdit gt Text Length Dialog gt InitialDir ExtractFilePath LogicFilenameEdit gt Text if Dialog gt Execute LogicFilenameEdit gt Text Dialog gt FileName The code above opens a dialog allowing the user to browse for logic file The filter property of this dialog masks out all the files in a folder other than bit file If the user cancels out no change will occur in the selection box If logic file is selected then we will move on to the loading it void _ fastcall TMainForm LogicLoadConfigBtnClick TObject Sender Io LoadLogic In UI LogicLoadConfigBtnClick shown above is executed in response to the Configure button click It immediately checks whether the device is opened and stream is connected If t
162. tion The power on surge current lasts for about 10 ms 5A on the 3 3V supply This surge is due primarily to charging the on card capacitors and the startup current of the FPGAs After initial power up the logic configuration will also result in a step change to the current consumption because the logic will begin to operate In our testing and measurements this has not been a surge current as much as a just a step change in the power consumption Power consumption varies and is primarily as a function of the logic design Logic designs with high utilization and fast clock rates require higher power Since calculating power consumption in the logic requires many details to be considered Xilinx tools such as XPower are used to get the best estimates X3 SD16 User s Manual 85 Environmental Table 23 X3 SD16 Environmental Limits Analog Input Condition Limits Operating Temperature 0 to 70 C ambient 70C as measured by the on card temp sensor Humidity Up to 95 non condensing Storage Temperature 40 to 125 C Vibration operating ETS 300 019 1 3 R3 class 3 3 Vibration storage ETS 300 019 1 1 R1 class 1 2 Vibration transportation ETS 300 019 1 2 R2 class 2 3 except for free fall class 2 2 A summary of the analog performance follows for the X3 SD16 module tests performed at room temperature with the module at approximately 48C Test environment was PCIe ada
163. tion monitoring 192 kHz D A with programmable gain and recording control Acoustic instrumentation front end Xilinx monitoring Geophysical Spartan3A DSP FPGA sensor interfaces The XMCs feature a Xilinx Spartan3 or Spartan3A DSP FPGA for signal processing and control In addition to the features in the Spartan3 3A logic such as embedded multipliers and memory blocks the FPGA computing core has two local SRAMs for data buffering and computing memory There are also a number of support peripherals for IO control and system integration Each XMC may have additional application specific support peripherals X3 SD16 User s Manual Table 2 X3 XMC Family Peripherals Peripheral Features XMC 3 PCI Express interface The XMC 3 host interface Integrates with PCI Express systems using one lane operating at 2 5 Gbps that provides up to 180 MB s sustained data rates This interface complies with VITA standard 42 3 which specifies PCI Express interface for the XMC module format The Velocia packet system provides fast and flexible communications with the host using a credit based flow control supporting packet transfers with the host A secondary command channel provides independent interface for control and status outside of the data channel that is extensible to custom applications XMC P16 Provides digital IO or a private link to host cards capable of 2200 MB s sustained operation Timing and triggeri
164. tion on Malibu eren nennen nnns 12 Online beh eae sd eae ies ence dated cts eas Re rie Ee ire i s WEINE ice 12 Innovative Integration Technical Support nennen ener eterne nennen nene 12 Innoyative Integration dq o ree ies iet te PRE dy 13 Typographic Conventions es eee ee etie n e eti e e Hand Le EIE PU E Hed 13 Windows Lins Cal ath Merced IE Host Hardware US INSIST RM 14 SoftWare Installation 4123 Se e SE ERU 14 Starting the Installation cesta enabdaestalecnetdacsedpetadensandsbalier unseat 15 Th Installer Program i aate eee aisi qu esee 16 Tools Registrationia em E en RE e E e eda T d In 18 Bus Master Memory Reservation 401202 0 0 2 0 ener ener enne neret n nennen 18 Hardware Installation HE earn eter n De doeet 19 After POWers p cited er e d aee d te etur ee ees pel De o tate E IY 20 Inst llation n LiNuX se 505 P CRAT Package File Names 5 si RR EGER GRE T EHE EAR ERR GR ER IE e AE 21 Prerequisites 2 need e ORE EET ERR AE Ea ERES 21 The Redistribution Package Group MalibuRed sss eene nnne
165. to extend the timestamp counter in software Software Alert The host software can create alerts to tag the data stream Over Temperature Alarm Sensor Failure The module temperature exceeded 85C Temperature Warning The module temperature exceeded 70C PLL Lost The sample clock PLL lost lock The PLL must be reconfigured ADC Queue Overflow The ADC data queue overflowed indicating the host did not consume the data quickly enough ADC Trigger The ADC trigger went active ADC Overrange An ADC channel was overranged DAC Trigger The DAC trigger went active DAC Queue Underflow The DAC data queue underflow indicating the host did provide data when required by the DAC Alert Packet Format Alert data packets have a fixed format in the system The Peripheral Device Number PDN is programmable in the software and is included in the packet header thus identifying the alert data packets in the data stream The packet shows the timestamp in system time what alerts were signaled and a status word for each alert X3 SD16 User s Manual 80 Dword Description 0 Header 1 PDN amp Total of Dwords in packet e g Headers data payload 1 Header 2 0x00000000 2 Alerts Signaled 3 Timestamp 4 0 5 Software Word 6 temp sensor error amp temp error amp 00 amp X 000 amp temp data 7 temp warning amp 000 amp X 000 amp tem
166. to the thermal plane The front panel is not electrically connected to the module ground plane its is only connected to the thermal plane When the module is operating the front panel usually feels slightly warm this is normal Temperature Sensor and Over Temperature Protection The temperature sensor is described in detail in the Board Basics chapter of this manual The temperature sensor is used to monitor the module temperature and protect it from overheating Temperature readings from the module are provided for system monitoring and are also reported in each alert packet During system development it is a good idea to have a look at the temperature and verify that everything is OK inside the system during actual use When the module exceeds 85C the analog power supplies shut down reducing the power consumption to about 3W The module can continue to communicate but no valid data will be collected A temperature warning may be enabled via the Alert Log when the temperature 15 above 70C If a warning occurs it is best to do something either to reduce power consumption such as turning off the A D channels turning on a system fan or turning off other things in the system The application LED on the module will flash when the module is too hot gt 85 The module must be completely powered down to restart once a failure occurs X3 SD16 User s Manual 78 Reducing Power Consumption The X3 SD16 has power controls that allow the app
167. two 2MB SBSRAM devices attached to the application FPGA that provide data buffering and computational RAM for FPGA applications X3 SD16 User s Manual 30 Computational SRAM The SRAM on the X3 family is a 2MB memory dedicated as FPGA local memory Applications in the FPGA may use the SRAM as a local buffer memory if the data buffer is too large to fit in FPGA block RAMs or as memory for an embedded processor in the FPGA The SRAM device connected to each Application FPGA 15 2 MB total size organized as 1M by 16 bits X3 SD and X3 SDF or 512K by 32 bits all others This device is a synchronous ZBT SRAM and supports clock rates up to 100 MHz on X3 SD and X3 SDF 133 MHz on all other modules All SRAM control and data lines pins are directly connected to the FPGA allowing the SRAM memory control to be customized to the application The Framework Logic provides a simple SRAM interface that can be readily modified for many types of applications Detailed explanation of the interface control logic is described in the FrameWork Logic User Guide The Framework Logic provides a simple register interface to the SBSRAM control logic that is used for test and demonstration FPGA logic developers can easily replace the simple register interface logic to build on top of the high performance logic core when integrating the SRAM into their logic design MATLAB developers frequently use the SRAM as the real time data buffer during development Since the MAT
168. u must have Microsoft MSVC Studio version 9 or later CodeGear RAD Studio 2007 2009 Embarcadero Rad Studio 2010 or QtCreator installed on your system depending on which of these IDEs you plan to use for Host development If you are planning on using these environments it is imperative that they are tested and known operational before proceeding with the library installation If these items are not installed prior to running the Innovative Integration install the installation program will not permit installation of the associated development libraries However drivers and DLLs may be installed to facilitate field deployment You must have Administrator Privileges to install and run the software hardware onto your system refer to the Windows documentation for details on how to get these privileges X3 SD16 User s Manual 14 Starting the Installation To begin the installation start Windows Shut down all running programs and disable anti virus software Insert the installation DVD If Autostart is enabled on your system the install program will launch If the DVD does not Autostart click on Start Run Enter the path to the Setup bat program located at the root of your DVD ROM drive i e E Setup bat and click to launch the setup program SETUP BAT detects if the OS is 64 bit or 32 bit and runs the appropriate installation for each environment It is important that this script be run to launch an install When installing
169. ule Since it uses an efficient DMA system it is very efficient at moving data which leaves the host system unburdened by the data flow The command channel provides the PCIe host direct access to the computing core logic for status control and initialization Since it is outside the packet system it is less complex to use and provides unimpeded access to the logic The application FPGA image is loaded by the host computer as part of the module initialization The image is loaded over the SelectMAP interface to the FPGA which is a byte wide configuration port on the FPGA from the host PCI Express X3 SD16 User s Manual 28 interface The configuration port for the is independent of the packet interface to the host and does not involve the use of the Velocia packet system The image can be loaded at any time over the SelectMAP interface allowing dynamic configuration of the FPGA for advanced applications Note There is no on card storage for this image and it must be loaded each time the host computer is powered down or reset Adding New Features to the FPGA The functionality of the computing core can be modified using the FrameWork Logic tools for the X3 module family The tools support development in either VHDL or MATLAB Signal processing data analysis and unique functions can be added to the X3 modules to suit application specific requirements See the X3 FrameWork Logic User Guide for further information X3 PCI Express Inter
170. umstances Windows will fail to auto install the device drivers for the JTAG and baseboards If this happens please refer to the TroubleShooting section X3 SD16 User s Manual 20 Installation on Linux This chapter contains instruction on the installation of the baseboard software for Linux operating systems Software installation on Linux is performed by loading a number of packages A Package is a special kind of archive file that contains not only the files that are to be installed but also installation scripts and dependency information to allow a smooth fit into the system This information allows the package to be removed or patched Innovative uses RPM packages in its installs Package File Names A package file name such as Malibu LinuxPeriphLib 1 1 3 1586 rpm encodes a lot of information Malibu Linux PeriphLib 1 1 3 1586 rpm Prerequisites for Installation In order to properly use the baseboard example programs and to develop software using the baseboard some packages need to be installed before the actual baseboard package The Redistribution Package Group MalibuRed This set of packages contain the libraries and drivers needed to run a program using Malibu This group is called MalibuRed because it contains the packages needed to allow running Malibu based programs on a target non development machine Red is short for redistributable WinDriver 9 2 1 1586 1pm Installs WinDriver 9 2 re
171. uration settings to the module then enables PCI data flow However samples will not be played until the module is triggered Log Stream Mode started UI gt Status Stream Mode started FTicks 0 return true Handle Data Required Once streaming is enabled and the module is triggered data flow will commence Samples will be bus mastered into the Module s FIFO and sent to the proper DAC The Buffer header is used by the Module s logic as a steering mechanism Note however that this event is signaled from within a background thread so you must not perform non reentrant OS system calls such as GUI updates from within your handler unless you marshal said processing into the foreground thread context void Applicationlo HandleDataRequired PacketStreamDataEvent amp Event SendOneBlock Event Sender void ApplicationIo SendOneBlock PacketStream PS ShortDG Packet DG WaveformPacket Calculate transfer rate in kB s double Period Time Differential if Period FBlockRate Packet DG SizeInBytes Period 1 0e3 No matter what channels are enabled we have one packet type to send here PS gt Send WaveformPacket FBlockCount HandleDataRequired will be called when a buffer is needed here we show that we will play a pre filled buffer at callback time every module interrupt X3 SD16 User s Manual 50 EEProm Access Each PMC module contains an IDROM region that can be u
172. we hook up event handlers to various events Hook script event handlers Script OnCommand SetEvent this amp ApplicationIo HandleScriptCommand Script OnMessage SetEvent this amp ApplicationIo HandleScriptMessage Configure Module Event Handlers Module Logic OnFpgaFileReadProgress SetEvent this amp ApplicationIo HandleProgress Module Logic OnFpgaFileReadComplete SetEvent this amp ApplicationIo HandleParseComplete Module Logic OnFpgaParseProgress SetEvent this amp ApplicationIo HandleProgress Module Logic OnFpgaParseComplete SetEvent this amp ApplicationIo HandleParseComplete Module Logic OnFpgaParseMessage SetEvent this amp ApplicationIlo HandleLoadError Module Logic OnFpgaLoadProgress SetEvent this amp Applicationlo HandleProgress Module Logic OnFpgaLoadComplete SetEvent this amp ApplicationIo HandleLoadComplete Module Logic OnFpgaLoadMessage SetEvent this amp ApplicationIlo HandleLoadError X3 SD16 User s Manual 26 This code attaches script event handlers and X3 module logic loader s informational event handlers to their corresponding events Malibu has a method where functions can be plugged into the library to be called at certain times or in response to certain events detected Events allow a tight integration between an application and the library These events are informational messages issued by the scripting and logic loader feature of the
173. ypes 14 pin dual row male header 2mm pin spacing right angle Number of Connections 14 arranged as 2 rows of 7 pins each Connector Part Number Samtec TMM 107 01 L D RA or equivalent Mating Connector AMP 111623 3 or equivalent Top of PCB Edge of PCB Pin 1 13 AA Pini Pin 14 v Pin 2 Figure 20 X3 SD16 J3 Orientation Figure 21 X3 SD16 J3 Side View Table 34 X3 JP3 Xilinx JTAG Connector Pinout Pin Signal Direction 1 3 5 7 9 11 13 Digital Ground Power 2 3 3V Power 4 TMS I 6 TCK I 8 TDO 10 TDI I 12 14 No Connect X3 SD16 User s Manual 105 Mechanicals The following diagram shows the X3 SD16 connectors and physical locations The bottom view of the XMC is shown which is the side against the host card when mounted The XMC conforms to IEEE 1386 form factor 75mm x 150mm spacing to the host card is 10 mm and consumes a single slot in desktop and Compact PCI PXI chassis The following views of the X3 SD16 show the connector placements The bottom view of the board is faces the carrier card when installed An EMI shield over the analog section is normally installed Detailed drawings for mechanical design work are available through technical support 16 Link JTAG 1 2 M 8 9 III z e poa X3 516 PCB 71490G REV B E ASSY 00258 A
174. z but the A D is limited to 37 MHz maximum clock rate The update clock can be either an external clock input or generated on the card by a PLL A full description of the sample clocks is described in the sample rate generation section of this manual If you use an external clock you MUST input input the sample rate multiplied by the clock divisor For example a 100 kHz sample rate requires 100 000 samples sec 256 clocks sample 25 6 MHz X3 SD16 User s Manual 62 Supporting software functions in the Malibu library are used to configure the sample clock mode and decimation to achieve the desired sample rate Since the PLL configuration is somewhat complex it is recommended that these functions be used for most applications Notes About Matching the A D and D A Data Rates Since the A D and D A must use the same clock rate on the X3 SD106 it is necessary to use a clock mode to match the A D clock divisor or provide data to the D A to compensate for the rate difference For A D sample rates below 52 kHz you must either provide data to the DAC at twice the A D rate or set the DAC decimation to 2 If the decimation 15 2 then the data rates are equal since the A D is using 512 clock divisor while the D A is using 256 clock divisor For rates above 52 kHz the D A and A D have the same clock divisors so the data rate 1s equal Sample Rate Generation and Clocking Controls The X3 SD16 can use a sample clock from the PLL the PLL locke

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