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STM8S207xx STM8S208xx

1. 5 Pinouts and pin description 5 1 Package pinouts Figure 3 LQFP 80 pin pinout Q Q 9 x S TR zZ I b s ER le ugaz DEE E M N o TI IE O 999 49 Ong 2 Caiaio o 2490 z gOJ22222 SO 18 EEEEE E DORT 4E 000000 oS Iz pSSIIIII ZEEE Gadaaa8nare amp u umnooonos amp adaaaanoaoaoocaanonoonoaoaonmnao ODON D 10 str oo O O ORK CO 10 st CO QN T Pom P P oP P P P Oo C O CO CO oo oO NRSTO 1 60 OPIS OSCIN PA1L 2 59 LIPI2 OSCOUT PA2LI 3 58 OPH Vssio AH 4 57 pg Veel 5 56 H PG4 VCAPLI 6 55 LIPG3 Vppll 7 54 O PG2 Vppio 1l 8 53 1 PG1 CAN_RX TIM3_CH1 TIM2 CH3 PASL 9 52 LIPGO CAN TX UART1_RX HS PA4LI 10 51 H PC7 HS SPI MISO UART1_TX HS PA50 11 50 1PC6 HS SPI MOSI UART1_CK HS Pall 12 49 O Vppio 2 HS PHON 13 48 D Vssio_2 HS PH1LI 14 47 E PC5 HS SPI_SCK PH2LI 15 46 O PC4 HS TIM1 CH4 PH3LI 16 45 LI PC3 HS TIM1 CH3 AINTS PF7LI 17 44 H PC2 HS TIM1 CH2 AIN14 PFGLI 18 48 O PC1 HS TIM1 CH1 AINT3 PFSLI 19 42 L PCO ADC ETR AIN12 PF40 20 41 PE5 SPI_LNSS T CN CO sf LO DO P OO Q e Ww o ot 00 OO NNN NNN OI QN QN noon Ooo Oo oOo tg LONGOHYTMATOTMORNRO L EO oijgyr
2. Option bits Factory Option Option Addr en E E n default Lud EE 6 5 4 3 2 1 D setting Read out 4800h protection OPTO ROP 7 0 00h ROP 4801h User boot OPT1 UBC 7 0 00h 4802h C0ode UBC NOPTI NUBC 7 0 FFh 4803h Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 00h function 4804n remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh AFR LSI IWDG WWDG WWDG 4805h OPT3 Reserved 00h Watchdog EN HW HW HAUT option NLSI NIWDG NWWDG NWWDG 4806h NOPT3 Reserved _EN HW HW HAUT FFh EXT CKAWU PRS PRS 4807h OPT4 Reserved 00h CLK SEL C1 co Clock option NEXT NCKAWUS NPR NPR 4808h NOPT4 Reserved FFh CLK EL sci SCH 4809h HSE clock OPT5 HSECNT 7 0 00h 480Ah Startup NOPT5 NHSECNT 7 0 FFh 480Bh OPT6 Reserved 00h Reserved 480Ch NOPT6 Reserved FFh 480Dh Flash wait OPT7 Reserved Wait state 00h 480En _ States NOPT7 Reserved Nwait state FFh 487Eh OPTBL BL 7 0 00h Bootloader 487Fh NOPTBL NBL 7 0 FFh 48 105 Doc ID 14733 Rev 11 ki STM8S207xx STM8S208xx Option bytes Table 13 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details
3. Table 9 General hardware register map continued Address Block Register label Register name dune 0x00 5320 TIM3_CR1 TIMS control register 1 0x00 0x00 5321 TIMS IER TIMS interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIMS status register 1 0x00 0x00 5323 TIM3_SR2 TIMG status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3_CCMR1 TIM3 capture compare mode register 1 0x00 0x00 5326 TIM3 CCMR2 TIM3 capture compare mode register 2 0x00 0x00 5327 TIM3_CCER1 TIMS capture compare enable register 1 0x00 0x00 5328 TIM3 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 532B TIM3_ARRH TIMG auto reload register high OxFF 0x00 532C TIM3_ARRL TIM3 auto reload register low OxFF 0x00 532D TIM3_CCR1H TIM3 capture compare register 1 high 0x00 0x00 532E TIMS CCR1L TIMS capture compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture compare register 2 low 0x00 jan a Reserved area 15 bytes 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler reg
4. 10 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 42 are derived from tests performed under ambient temperature fysstER frequency and Vpp supply voltage conditions tMASTER 1 MASTER Refer to UO port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 42 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 10 SCK SPI clock frequency MHz 1 te sck Slave mode 0 6 dE SPI clock rise and fall time Capacitive load C 30 pF 25 f SCK tsuNss NSS setup time Slave mode 4 X MASTER thuss NSS hold time Slave mode 70 1 W SCKH SCK high and low time Master mode tsck 2 15 tgck 2 15 tw SCKL t 1 Master mode 5 su MI Data input setup time isu Sl Slave mode 5 1 Master mode 7 ns Wi Data input hold time Ian Slave mode 10 tasoy Data output access time Slave mode 3 X MASTER taiso YY Data output disable time Slave mode 25 tso Data output valid time Slave mode after enable edge 75 two Data output valid time Master mode after enable edge 30 tiso Slave mode after enable edge 31 ASS Data output hold time tnmoy V Master mode after enable edge 12 Values based on design simulation and or characterization results and not tested in production Min time is for the minimum time to drive the output
5. Table 2 STM8S20xxx performance line features 2 2 E o 3 amp 2 z 215153 El E g z 9 2 E E E Q o e amp 55 82 EIS 2 EZ a g Device 8 859 EIS s ui E E E ETV as 2 2 c s 2 2 a 5 et a Oo iL E E E o E g x x o o Q S 2 18 2 H F E 3 5 I STM8S207MB 80 68 37 9 3 16 18 128 K 2048 6K STM8S207M8 80 68 37 9 3 16 18 64 K 2048 6K STM8S207RB 64 52 36 9 3 16 16 128 K 2048 6K STM8S207R8 64 52 36 9 3 16 16 64 K 1536 6K STM8S207R6 64 52 36 9 3 16 16 32K 1024 6K STM8S207CB 48 38 35 9 3 10 16 128K 2048 6K STM8S207C8 48 38 35 9 3 10 16 64 K 1536 6K No STM8S207C6 48 38 35 9 3 10 16 32K 1024 6K STM8S207SB 44 34 31 8 3 9 15 128 K 1536 6K STM8S207S8 44 34 31 8 3 9 15 64 K 1536 6K STM8S207S6 44 34 31 8 3 9 15 32K 1024 6K STM8S207K8 32 25 23 8 3 7 12 64K 1024 6K STM8S207K6 32 25 23 8 3 7 12 32K 1024 6K STM8S208MB 80 68 37 9 3 16 18 128 K 2048 6 K STM8S208RB 64 52 37 9 3 16 16 128K 2048 6K STM8S208R8 64 52 37 9 3 16 16 64K 2048 6 K STM8S208R6 64 52 37 9 3 16 16 32 K 2048 6 K STM8S208CB 48 38 35 9 3 10 16 128 K 2048 6 K Yes STM8S208C8 48 38 35 9 3 10 16 64 K 2048 6K STM8S208C6 48 38 35 9 3 10 16 32K 2048 6K STM8S208SB 44 34 31 8 3 9 15 128 K 1536 6K STM8S208S8 44 34 31 8 3 9 15 64 K 1536 6K STM8S208S6 44 34 31 8 3 9 15 32K 1536 6K Doc ID 14733 Rev 11 11 105 Block dia
6. Data guaranteed by design not tested in production 2 During the sample time the input capacitance Cam 3 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tg After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Electrical characteristics K Table 45 ADC accuracy with Ran lt 10 kQ Vopa 5 V Symbol Parameter Conditions Typ Max Unit fapc 2 MHz 1 2 5 IE Total unadjusted error fApc 4 MHz 1 4 3 fapc 6 MHz 1 6 3 5 fapc 2 MHz 0 6 2 IEg Offset error 7 fApc 4 MHz 1 1 2 5 fapc 6 MHz 1 2 2 5 fapc 2 MHz 0 2 2 lEgl Gain error fApc 4 MHz 0 6 2 5 LSB fApc 6 MHz 0 8 2 5 fapc 2 MHz 0 7 1 5 Epl Differential linearity error fapc 4 MHz 0 7 1 5 fApc 6 MHz 0 8 1 5 fapc 2 MHz 0 6 1 5 IE I Integral linearity error fapc 4 MHz 0 6 1 5 fApc 6 MHz 0 6 1 5 1 Data based on characterisation results for LQFP80 device with Vpgre Vngr not tested in production 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accurac
7. 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance d Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Electrical characteristics 10 3 2 Supply current characteristics The current consumption is measured as described in Figure 9 on page 53 Total current consumption in run mode The MCU is placed under the following conditions e A UO pins in input mode with a static value at Vpp or Vas no load e Allperipherals are disabled clock stopped by Peripheral Clock Gating registers except if explicitly mentioned e When the MCU is clocked at 24 MHz T4 x 105 C and the WAITSTATE option bit is set Subject to general operating conditions for Vpp and T4 Table 20 Total current consumption with code execution in run mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit fopu faster 24 MHz HSE crystal osc 24 MHz 4 4 Ta 105 C HSE user ext clock 24 MHz 3 7 7 30 HSE crystal osc 16 MHz 3 3 Supply f 16 MH HSE t clock 16 MH 2 7 z curentii fcpu fmaster 16 MHz SE user ext clock 16 MHz 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 m X HSE user ext clock 16 MHz 1 2 4 1 128 125 kHz from RAM CPU MASTER HSI RC osc 16 MHz 10 1 3 eu vasterR 128 15 625 uer RC osc 16 MHz 8 0 55 cpu MASTER 128 kHz LSI RC osc 128 kHz 0 45 IDD RUN HSE crystal osc
8. 76 105 Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Electrical characteristics Figure 32 Typ Von Von Vpp 3 3 V high sink ports 40 C a 250C H 85 C UE 1 75 1 25 Von Vox V s CH a o u 0 25 lo mA 10 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 41 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vumpsrn NRST Input low level voltage 1 0 3 V 0 3 x Vpp Vuunen NRST Input high level voltage 0 7 X Vpp Vpp 0 3 V Vounrst NRST Output low level voltage Wm loL 2 mA 0 5 Reuwrst NRST Pull up resistor 30 40 60 kQ tep ast NRST Input filtered pulse 9 75 ns Nre NRsT NRST Input not filtered pulse 500 ns toP NRST NRST output pulse 1 15 US 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 33 Typical NRST Vu and Vu vs Vpp 4 temperatures 40 C mM 25 C 85 C 125 C 4 E 3 gt 1 0 T T T T T T d 2 5 3 3 5 4 4 5 5 5 5 6 Voo V ky Doc ID 14733 Rev 11 77 105 Electrical characteristics STM8S207xx STM8S208xx
9. D D1 D3 A A2 48 las a 0 a2 Y E3 E1 us SS 17 Y Pin 1 identification 4 ER 16 c JL ere Table 53 64 pin low profile quad flat package mechanical data 10 x 10 mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 C 0 090 0 200 0 0035 0 0079 D 12 000 0 4724 D1 10 000 0 3937 E 12 000 0 4724 E1 10 000 0 3937 0 500 0 0197 K 0 000 3 500 7 000 0 0000 3 5000 7 0000 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 11 93 105 Package characteristics STM8S207xx STM8S208xx 94 105 Figure 46 48 pin low profile quad flat package 7 x 7 D ccc m 5B ME Table 54 48 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0
10. LO o a 49 48 D Plo 47 H PG4 46 H PG3 45 O PG2 44 PG1 CAN_RX 43 H PGO CAN TX 42 H PC7 HS SPI_LMISO 41 PC6 HS SPI_MOSI 40 HO Vppio_2 39 H Vssio 2 38 PC5 HS SPI SCK 37 H PC4 HS TIM1_CH4 36 PC3 HS TIM1_CH3 35 PC2 HS TIM1 CH2 34 H PC1 HS TIM1_CH1 33 H PES SPI NSS AIN11 PF3 VREF Vppa Vssa VREF AIN10 PFO AIN7 PB7 N5 PB5 N4 PB4 N3 PB3 N2 PB2 N1 PB1 NO PBO N8 PE7 N9 PE6 A A I2C SDA l2C_SCL TIM1_ETR TIM1 TIM1_CH2N TIM1_CH1N HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function CAN RX and CAN TX is available on STM8S208xx devices only Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Pinouts and pin description K Figure 5 LQFP 48 pin pinout NRST OSCIN PA1 OSCOUT PA2 Vssio 1 Vss VCAP Vpp Vppio 1 TIM3_CH1 TIM2_CH3 PA3 UART1_RX HS PA4 UART1_TX HS PA5 UART1_CK HS PA6 PD5 UART3_TX HS TIM2_CH1 BEEP HS TIM3_CH2 TIM1_BKIN CLK_CCO HS CLK_CCO HS TIM3_CH1 TIM2_CH3 T 12C_SCL HS TIM2_CH2 ADC_ETR HS SWIM PD6
11. Table 9 General hardware register map continued Address Block Register label Register name di 0x00530 mmer TM2contolregsteri gon 0x00 5301 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture compare mode register 3 0x00 0x00 5308 TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 5309 TIM2 CCER2 TIM2 capture compare enable register 2 0x00 0x00 530A TIM2 TIM2 CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00 00 530COx TIM2 PSCR TIM2 prescaler register 0x00 0x00 530D TIM2 ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5311 TIM2 CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5312 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5313 TIM2 CCR3H TIM2 capture compare register 3 high 0x00 0x00 5314 TIM2 CCR3L TIM2 capture compare register 3 low 0x00 po sie Reserved area 11 bytes 42 105 Doc ID 14733 Rev 11 DI STM8S207xx STM8S208xx Memory and register map
12. OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Pages 0 to 1 defined as UBC memory write protected 0x02 Pages 0 to 3 defined as UBC memory write protected 0x03 Pages 0 to 4 defined as UBC memory write protected OxFE Pages O0 to 255 defined as UBC memory write protected OxFF Reserved Note Refer to the family reference manual RM0016 section on Flash EEPROM write protection for more details OPT2 AFR7Alternate function remapping option 7 0 Port D4 alternate function TIM2_CH1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN5 port B4 alternate function AIN4 1 Port B5 alternate function I2C_SDA port B4 alternate function FC SCL AFRB5 Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alternate function AINO 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1 CHSN port B1 alternate function TIM1 CH2N port BO alternate function TIM1_CH1N AFRA Alternate function remapping option 4 0 Port D7 alternate function TLI 1 Port D7 alternate function TIM1 CHA AFRS3 Alternate function remapping option 3 0 Port DO alternate function TIM3_CH2 1 Port DO alternate function TIM1 BKIN AFR2 Alternate function remapping option 2 0 Port DO alternate function TIM3 CH2 1 Port DO alternate fu
13. 1 Data based on characterization results not tested in production 2 All power Vpp Vppio Vppa and ground Vss Vssjo Vssa pins must always be connected to the external supply 3 UO pins used simultaneously for high current source sink must be uniformly spaced around the package between the Vppio Vssio pins 4 lij piy Must never be exceeded This is implicitly insured if Vjy maximum is respected If Vu maximum cannot be respected the injection current must be limited externally to the liy unn value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy lt Vgs Por true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected 5 Negative injection disturbs the analog performance of the device See note in Section 10 3 10 10 bit ADC characteristics on page 84 6 When several inputs are submitted to a current injection the maximum Zus is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with Hm py maximum current injection on four I O port pins of the device Table 17 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 ge Ty Maximum junction temperature 150 56 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics 10 3 3 Operating conditions The
14. 6 2 K Table 7 lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case Table 7 Flash Data EEPROM and RAM boundary addresses Memory area Size bytes Start address End address 128 K 0x00 8000 0x02 7FFF Flash program memory 64 K 0x00 8000 0x01 7FFF 32 K 0x00 8000 0x00 FFFF 6K 0x00 0000 0x00 17FF RAM 4K 0x00 0000 0x00 1000 2K 0x00 0000 0x00 07FF 2048 0x00 4000 0x00 47FF Data EEPROM 1536 0x00 4000 0x00 45FF 1024 0x00 4000 0x00 43FF Register map Table 8 I O port hardware register map Address Block Register label Register name neset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0x00 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC CR1 P
15. Figure 34 Typical NRST pull up resistance vs Vpp 4 temperatures 40 C 60 25 C 85 C 55 125 C HH 45 iSS NRESET pull up resistance OW 2 5 3 3 5 4 45 5 5 5 6 Voo V Figure 35 Typical NRST pull up current vs Vpp 4 temperatures 140 4 120 s 100 g 5 o 80 2 60 40 C Im Bic a 25 C 2 40 Ee z Pd 85 C 20 ert 125 C a on 0 1 2 3 4 5 6 Vop VI ai15069 The reset network shown in Figure 36 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in Table 37 Otherwise the reset is not taken into account internally For power consumption sensitive applications the capacity of the external reset capacitor can be reduced to limit charge discharge current lf the NRSTsignal is used to reset the external circuitry care must be taken of the charge discharge time of the external capacitor to fulfill the external device s reset timing conditions The minimum recommended capacity is 10 nF Figure 36 Recommended reset pin protection Von STM8 External NRST A Internal reset reset e Filter circuit O0 1uF optional 78 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics
16. Electrical characteristics STM8S207xx STM8S208xx Figure 20 Typical Vu and Vu vs Von 4 temperatures 40 C 6 25 C 5 85 C 125 C a4 2 X gt 3 SI gt 2 1 25 3 3 5 4 4 5 5 5 5 6 Voo V Figure 21 Typical pull up resistance vs Vpp 4 temperatures 40 C 60 g 25 C 85 C 55 125 C G Q 50 4 pt a j 4 c Lemma BiB ga 41 G 9 D 45 o S 40 E 35 30 4 25 3 3 5 4 4 5 5 5 5 6 Voo V Figure 22 Typical pull up current vs Vpp 4 temperatures 140 ND o Q o E 5 80 60 4 t m pM mE 25 C amp 40 85 C P QST 125 C a p nk 0 1 2 3 4 5 6 Voo V ai15068 1 The pull up is a pure resistor slope goes through 0 72 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics Table 38 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk ho 10 mA Vpp 5V 2 VoL Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V 100 Von Output high level with 8 pins sourced lig 10 mA Vpp 5 V 2 8 y Output high level with 4 pins sourced ljo 4 mA Vpp 3 3 V 2 10 1 Data based on characteri
17. March 2011 LQFP64 14x14 LQFP64 10x10 2 LQFP32 7x7 LQFP48 7x7 LQFP44 10x10 m Communications interfaces High speed 1 Mbit s active beCAN 2 0B UART with clock output for synchronous operation LIN master mode UART with LIN 2 1 compliant master slave modes and automatic resynchronization SPlinterface up to 10 Mbit s 1C interface up to 400 Kbit s m 10 bit ADC with up to 16 channels m I Os Up to 68 I Os on an 80 pin package including 18 high sink outputs Highly robust UO design immune against current injection Development support Single wire interface module SWIM and debug module DM m 96 bit unique ID key for each device Table 1 Device summary Part numbers STM8S207xx STM8S207MB STM8S207M8 STM8S207RB STM8S207R8 STM8S207R6 STM8S207CB STM8S207C8 STM8S207C6 STM8S207SB STM8S20788 STM8S207S6 STM8S207K8 STM8S207K6 Part numbers STM8S208xx STM8S208MB STM8S208M8 STM8S208RB STM8S208R8 STM8S208R6 STM8S208CB STM8S208C8 STM8S208C6 STM8S208SB STM8S208S8 STM8S208S6 Doc ID 14733 Rev 11 1 105 www st com Contents STM8S207xx STM8S208xx Contents 1 IRMOGUCTION Sous casae rio eR QR D E ci d eU e De uu E SRA 9 2 DESCHPHON 11 2 2220 dw ERR Reece RUE Ear ee Rede e RR RR Ra Una 10 3 Block diagram e e E dr EE rao oa 6 s ee A Mee 12 4 Product overview 2ssssnnnnnnnaaaaa annan m n m EEN 13 4 1 Central processing unit GTM
18. SES ZE e ee c ee e SCK Input o YT I i wise Pi SCK e h M OUTUT 1 L sor L tov ty MO eu T4 thio dm ai14136 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp ky Doc ID 14733 Rev 11 81 105 Electrical characteristics STM8S207xx STM8S208xx 10 3 9 82 105 I2C interface characteristics Table 43 PC characteristics Standard mode DC Fast mode 12C Symbol Parameter Unit Min Max Min Max twsciL SCL clock low time 4 7 1 8 us tw SCLH SCL clock high time 4 0 0 6 tsuspa SDA setup time 250 100 trspa SDA data hold time o 9 o9 9009 SDA SDA and SCL rise time 1000 300 ns t ScL SDA _ SDA and SCL fall time 300 300 sc thistay START condition hold time 4 0 0 6 us lsusra Repeated START condition setup time 4 7 0 6 tsuisto STOP condition setup time 4 0 0 6 us STOP to START condition time Iw STO STA bus free 4 7 13 us Cp Capacitive load for each bus line 400 400 pF 1 faster Must be at least 8 MHz to achieve max fast Re speed 400kHz Data based on standard 1 C protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of
19. kyy STM8S207xx STM8S208xx Performance line 24 MHz STM8S 8 bit MCU up to 128 Kbytes Flash integrated EEPROM 10 bit ADC timers 2 UARTs SPI BC CAN Features m Core Max fopy up to 24 MHz 0 wait states cpu lt 16 MHz Advanced STM8 core with Harvard architecture and 3 stage pipeline Extended instruction set Max 20 MIPS 24 MHz m Memories Program up to 128 Kbytes Flash data retention 20 years at 55 C after 10 kcycles Data up to 2 Kbytes true data EEPROM endurance 300 kcycles RAM up to 6 Kbytes m Clock reset and supply management 2 95 to 5 5 V operating voltage Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Wait active halt amp halt low power modes Peripheral clocks switched off individually Permanently active low consumption power on and power down reset m interrupt management Nested interrupt controller with 32 interrupts Up to 37 external interrupts on 6 vectors m Timers 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 8 bit basic timer with 8 bit prescaler Auto wakeup timer Window watchdog independent watchdog
20. Figure 25 Typ Vo Vpp 5 V true open drain ports 40 C 25 C 85 C 1 5 125 C E Vor V lo mA 74 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics Figure 26 Typ Vo 8 Vpp 3 3 V true open drain ports 400 m 25 C 85 C 1541 125 C Figure 27 Typ VoL Vpp 5 V high sink ports 407C a 25 C 1 25 85 C 125 C Vor V Figure 28 Typ Vo Vpp 3 3 V high sink ports 40 C a 25 C 1 25 85 C 125 C Vor V ky Doc ID 14733 Rev 11 75 105 Electrical characteristics STM8S207xx STM8S208xx Figure 29 Typ Vpp Von Vpp 5 V standard ports p 740 m 25 C 1 75 85 C 15 125 C Von Vor V lo mA Figure 30 Typ Von Vou Vpp 3 3 V standard ports e 25 C 85 C 125 C Ven Vox V lo mA Figure 31 Typ Vpp Von 9 Vpp 5 V high sink ports 40 C 25 C 85 C 1 5 125 C 1 75 Ven Von V 25
21. 0 8 E e release to bootloader vector 150 US 1 Data guaranteed by design not tested in production Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T HSI internal RC fcpy fuAsrER 16 MHz Table 30 Peripheral current consumption Symbol Parameter Typ Unit Ibom TIM1 supply current 220 Ippcrimz TIM2 supply current 120 Ipp TIM3 TIM3 timer supply current 1 100 Ipp TIM4 TIM4 timer supply current 1 25 Ipp uarT1 YART1 supply current 2 90 Ipp uart3 UARTS supply current 110 al Ipp sPi SPI supply current 2 40 le DC supply current 50 Ibocan beCAN supply current 210 Ipp ADC2 ADC2 supply current when converting 3 1000 64 105 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential Ipp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Not tested in production Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Electrical characteristics Current consumption curves Figure 14 and Figure 15 show typical current consumption meas
22. 13 4 2 Single wire interface module SWIM and debug module DM 14 4 3 Interrupt controller aus iio cy mde Ee A eer aa aaaaaa 14 4 4 Flash program and data EEPROM memory n 15 45 Clock controller nunana RI ERR eR Sends i Rad wA PEREAT EE 16 4 6 Power management 17 4 7 Watchdog timers esse RA RR RREREXQUERE ERG ERR XA REREXA 4X Rd 17 4 8 Auto wakeup counter 18 4 9 Beeper PD 18 4 10 TIM1 16 bit advanced control mer 18 4 11 TIM2 TIMG 16 bit general purpose timers 18 4 12 TIM4 8 bit basic mer 19 4 13 Analog to digital converter ADC2 212 s2s ss sasa raka 19 4 14 Communication interfaces 19 4141 UARTI v a degree d x etis d eme ERE PRORA worked 20 4414 2 HARTERT Ron RR CR CE EL Soa A 20 4 14 8 SP weed EIER ds mE Piedad aw Ras EVER E Ear d kh 21 WU WEE 22 414 5 DECAN e WEEK rg ANER NEEN uu dan ar das Do d 22 5 Pinouts and pin description 23 5 1 Package pinouts cesse e eee de eee wae ea bowen ee a Ree RU 23 5 2 Alternate function remapping 00 e eee ee 33 6 Memory and register map 34 6 1 Memory map 222s skaka ska arnar t Ep aaa a 34 2 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Contents 10 11 6 2 Register M p um 35 Interrupt vector mapping 47 Option bytes uuunnnvnsssnnnnnnnnnnnnnnnnnnnnnnnnn a 48 Unique ID 11 31 12 k k NEE ENEE EE REEN
23. 14 000 14 200 0 5433 0 5512 0 5591 E3 12 350 0 4862 e 0 650 0 0256 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 11 91 105 Package characteristics STM8S207xx STM8S208xx Figure 44 64 pin low profile quad flat package 14 x 14 49 64 Pin 1 identification 1R ME Table 52 64 pin low profile quad flat package mechanical data 14 x 14 mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 000 0 4724 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 000 0 4724 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal places 92 105 Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Package characteristics K Figure 45 64 pin low profile quad flat package 10 x 10
24. 2 The ideal transfer curve 3 End point correlation line Er Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 42 Typical applic ation with ADC Rain an 000 AINx STM8 10 bit A D conversion Z Capc Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Electrical characteristics 10 3 11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vgs through a 100 pF capacitor until a functional disturbance
25. 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Package characteristics K Figure 47 44 pin low profile quad flat package 10 x 10 D D1 D3 33 23 34 22 bi e 12 Self 1 ah on j 4Y_ME Table 55 44 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 11 800 12 000 12 200 0 4646 0 4724 0 4803 D1 9 800 10 000 10 200 0 3858 0 3937 0 4016 D3 8 000 0 3150 E 11 800 12 000 12 200 0 4646 0 4724 0 4803 E1 9 800 10 000 10 200 0 3858 0 3937 0 4016 E3 8 000 0 3150 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 11 95 105 Package characteristics STM8S207xx STM8S208xx 96 105 Figure 48 32 pin low profile quad flat package 7 x 7 24
26. E sim 3t alternate E EEE Cal E S 2 8188 E function ster remap ait l 5 2 9 35 option bit a 20 202 2 II Sr x OI SPI 41 33 25 23 17 PE5 SPI NSS WO X X X O1 X X Port E5 master slave select 42 POUADCETR O X X X O1 X X Port CO mu o Timer 1 43 34 26 24 18 PC1 TIM1 CH1 lO X X X HS O3 X X Port C1 channel 1 Timer 1 44 35 27 25 19 PC2 TIM1 CH2 lO X X X HSO3 X X Port C2 channel 2 Timer 1 45 36 28 26 20 PC3 TIM1_CH3 1 O X X X HS OS X X Port C3 channel 3 Timer 1 46 37 29 21 PC4 TIM1_CH4 O X X X HS OS X X Port C4 channel 4 47 38 30 27 22 PC5 SPI_SCK VO X X X HS OS3 X X Port C5 SPI clock 48 39 31 28 Vssio 2 S UO ground 49 40 32 29 Vppio 2 S UO power supply SPI master 50 41 33 30 23 PC6 SPI_MOSI 1 O X X X HS OS X X Port C6 out slave in 51 42 34 31 24 PC7Z SPL miso o X X x HS O3 X X Port c7 SP master in slave out 52 43 35 32 Pao can_Tx vo x X O1 X X Port Go PECAN transmit 53 44 36 33 PG1 CAN_RX 1 O X X O1 X X Port G1 beCAN receive 54 45 PG2 1 O X X O1 X X Port G2 55 146 PG3 1 O X X O1 X X Port G3 56 147 PG4 1 O X X O1 X X Port G4 57 48 PIO 1 O X X O1 X X Port 10 58 IPH 1 O X X
27. Flash in operating mode HSI clock after 61 5 Suppl in hal d WE A D H upply current in halt mode H dx Flash in powerdown mode HSI clock after 45 wakeup Low power mode wakeup times Table 28 Wakeup times Symbol Parameter Conditions Typ Max Unit See t Wakeup time from wait note WU WFI mode to run mode fopu MASTER 16 MHz 0 56 Flash in operating 6 6 modell MVR voltage 4 regulator on Flash in powerdown 36 5 i Wakeup time active halt model HSI after us WU AH mode to run mode Flash in operating Wakeup 48 5 MVR voltage mode 4 regulator off Elash in powerdown 6 5 50 mode i Wakeup time from halt Flash in operating mode 52 WU H 3 VI mode to run mode Flash in powerdown mode 54 1 Data guaranteed by design not tested in production 2 twuwel 2 X 1 fmaster 7 X 1 fcpu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK ICKR register 5 Configured by the AHALT bit in the FLASH CH1 register 6 Plus 1 LSI clock depending on synchronization ky Doc ID 14733 Rev 11 63 105 Electrical characteristics STM8S207xx STM8S208xx Total current consumption and timing in forced reset state Table 29 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Ipp R Supply current in reset state kh acid mA Vpp 3 3 V
28. For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to
29. I Os used at the same time in output at low level with Io 20 mA Vo 1 5 V e Maximum two true open drain I Os used at the same time in output at low level with lot 20 mA VoL 2V PiNTmax 15 mA x 5 5 V 82 5 mW Piomax 10 MA x2 V x8 20 mA x 2 V x 2 20 mA x 1 5 V x 4 360 mW This gives Pintmax 82 5 mW and Pigmax 360 mW PDmax 82 5 mW 360 mW Thus Ppmax 443 mW Using the values obtained in Table 57 Thermal characteristics on page 97 T Jmax is calculated as follows for LOFP64 10 x 10 mm 46 C W Tumax 82 C 46 C W x 443 mW 82 C 20 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx STM8 development tools 12 12 1 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatil
30. UART3_RX PD4 PD3 PD2 PD1 PDO PEO PE1 Ty I2C SDA PE2 LIPES TIM1 BKIN SEO PD7 TLI OMONODORWND A 10 11 12 LI E R N EN Oo A ol A R A W R NI R jars R o Cal O C2 Co l Ee 36 A A 7 B6 5 4 N5 PB N4 PB N3 PB3 N2 PB2 N1 PB1 NO PBO I2C SDA A GC SCL A TIM1_ETR A TIM1 CH3N A FMI CH2N A TIM1_CH1N A H LIPG1 CAN RX PGO CAN TX F PC7 HS SPI MISO PC6 HS SPI_MOSI Vppio 2 Vssio 2 PC5 HS SPI SCK PC4 HS TIM1 CHA PC3 HS TIM1_CH3 H PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 PE5 SPI_NSS 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 4 CAN RXand CAN TX is available on STM8S208xx devices only Doc ID 14733 Rev 11 25 105 Pinouts and pin description STM8S207xx STM8S208xx Figure 6 LQFP 44 pin pinout PD5 UART3 TX HS TIM2 CH1 BEEP HS TIM3_CH2 TIM1 BKIN CLK_CCO HS TIM3_CH1 TIM2 CH3 HS CLK_CCO HS TIM2_CH2 ADC_ETR HS SWIM T y l2C SCL TyI
31. a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard Doc ID 14733 Rev 11 89 105 Package characteristics STM8S207xx STM8S208xx 11 90 105 Package characteristics To meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Package characteristics 11 1 11 1 1 K Package mechanical data LQFP package mechanical data Figure 43 80 pin low profile quad flat package 14 x 14 lt D D1 E E 60 H Ja ah o TT 40 1 Gees F b E3 E1 21 Pin 1 identification 1 n 20 Su Table 51 80 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 220 0 320 0 380 0 0087 0 0126 0 0150 c 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 350 0 4862 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800
32. e 29 Flash Data EEPROM and RAM boundary addresses 0 eee asas 35 I O port hardware register map 35 General hardware register map 37 CPU SWIM debug module interrupt controller registers eee eae 45 Interrupt mapping s resos RII A rh 47 Option DYES MP 48 Option byte description 49 Unique ID registers 96 bits aaa 52 Voltage characteristics socorrer n stu s s ask Vaska b aba nn 55 Current characteristics sassa skakar aaa akka kakak aaa 56 Thermal characteristics 56 General operating conditions 57 Operating conditions at power up power down 58 Total current consumption with code execution in run mode at Vpp 2 5 V 59 Total current consumption with code execution in run mode at Vpp 3 3 V 60 Total current consumption in wait mode at Vpp DN 61 Total current consumption in wait mode at Vpp 32N lll klakk aaa 61 Total current consumption in active halt mode at Vpp 5 V T4 40 to 85 C 62 Total current consumption in active halt mode at Vpp z 233N 00000000 62 Total current consumption in halt mode at Vpp 5 V Ta A0to brt ee 63 Total current consumption in halt mode at Vpp 32N kaka aka a 63 Wakeup MES e rr 63 Total current consumption and timing in forced reset state 64 Peripheral current consumption 1 2 sasa sakk nn 64 HSE user external clock characteristics 2l sers 66 HSE oscillator cha
33. for O j4 given in Table 57 Thermal characteristics Refer to Section 11 2 Thermal characteristics on page 97 for the calculation method T Jmax is given by the test limit Above this value the product behavior is not guaranteed Doc ID 14733 Rev 11 57 105 Electrical characteristics STM8S207xx STM8S208xx 10 3 1 58 105 Figure 12 fcpumax versus Vpp fceu MHz FUNCTIONALITY GUARANTEED FUNCTIONALITY NOT GUARANTEED T4 40 to 105 C IN THIS AREA 12 _ FUNCTIONALITY _ _ GUARANTEED Ta 40 to 125 C 8 a ES 4 REN urn 9t es fle 2S ci 0 2 95 4 0 5 0 55 SUPPLY VOLTAGE V Table 19 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 20 oo tvpp z us V Vpp fall time rate 2 1 o0 Reset release ini TEMP delay Vpp rising 1 70 ms Power on reset Vir threshold 2 65 2 8 2 95 V Brown out reset Vir threshold 2 58 2 73 2 88 V Brown out reset VHYS BOR hysteresis i MV 1 Guaranteed by design not tested in production VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cgy to the Vcap pin Geer is specified in Table 18 Care should be taken to limit the series inductance to less than 15 nH Figure 13 External capacitor Cer ESR C ESL o K Soo Rleak
34. frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control LIN master capability Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame LIN slave mode SPI Autonomous header handling one single interrupt per valid message header Automatic baud rate synchronization maximum tolerated initial clock deviation 15 96 Synch delimiter checking 11 bit LIN synch break detection break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support Maximum speed 10 Mbit s fyaster 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin Doc ID 14733 Rev 11 21 105 Product overview STM8S207xx STM8S208xx 4 14 4 4 14 5 22 105 Pc e PC master features Clock generation Start and stop generation e lC slave features Programmable DC address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz beCA
35. memory transfers Doc ID 14733 Rev 11 13 105 Product overview STM8S207xx STM8S208xx 4 2 4 3 14 105 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on six vectors including TLI Trap and reset interrupts Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Product overview 4 4 Flash program and data EEPROM memory e Upto 128 Kbytes of high density Flash program single voltage Flash memory e Upto2K bytes true data EEPROM e Read while write Writing in data memory p
36. option bytes to the option byte description table Added Section 9 Unique ID and listed this attribute in Features Section 10 3 Operating conditions added introductory text Table 18 General operating conditions replaced Cgy1 with VCAP and added data for ESR and ESL removed low power dissipation condition for TA Table 26 Total current consumption in halt mode at VDD 5 V TA 40 to 85 C replaced max value of lou at 85 C from 30 pA to 35 pA for the condition Flash in powerdown mode HSI clock after wakeup Table 33 HSI oscillator characteristics updated the ACC factory calibrated values Functional EMS electromagnetic susceptibility and Table 47 replaced IEC 1000 with IEC 61000 Electromagnetic interference EMI and Table 48 replaced SAE J1752 3 with IEC 61967 2 Table 57 Thermal characteristics changed the thermal resistance junction ambient value of LQFP32 7x7 mm from 59 C W to 60 C W 13 Apr 2010 9 A Doc ID 14733 Rev 11 103 105 Revision history STM8S207xx STM8S208xx 104 105 Table 58 Document revision history continued Date Revision Changes Added part number STM8S208M8 to Table 1 Device summary Updated reset state of Table 5 Legend abbreviations for pinout table Added footnote 4to Table 6 Pin description Table 9 General hardware register map standardized all reset state values updated the reset state valu
37. range 98 Doc ID 14733 Rev 11 3 105 Contents STM8S207xx STM8S208xx 12 STM8 development tools elll 99 12 1 Emulation and in circuit debugging tools 99 12 2 Software EE 100 12 2 1 STM8 toolset 1 21222nun2nnnnnnnnnninssnnnannsnnannnira 100 12 2 2 C and assembly toolchains 100 12 3 Programming tools See EE E akka aaa 100 13 Ordering information eee 101 14 Revision history shape eiui 3 84 cada 6 6 ese A ci ara da 102 4 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 ky Device Super iracas eae aed eee Vah om eee bon aes Ad eer a Rm E 1 STM8S20xxx performance line features 11 Peripheral clock gating bit assignments in CLK PCKENR 1 2 registers 16 TIM timer features 19 Legend abbreviations for pinout table 28 PIN GOSCNPLON 22 bu san cess n sk sa ER ee Gee dee gt de IN ea kee bela RD oe
38. to 0x00 509F Reserved area 59 bytes 0x00 50A0 me EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area 17 bytes 0x00 50B3 RST RST_SR Reset status register oxxx 0x00 50B4 to 0x00 50BF Reserved area 12 bytes 0x00 50C0 rfe CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte ky Doc ID 14733 Rev 11 37 105 Memory and register map STM8S207xx STM8S208xx Table 9 General hardware register map continued Address Block Register label Register name nese status 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB CLK CANCCR CAN clock control register 0x00 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD CLK SWIMCCR SWIM clock control register ea 0x00 50CE to 0x00 50D0 Reser
39. 00 7FO6 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 pert ee Reserved area 85 bytes 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 ER ITC_SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 OxFF possis Reserved area 2 bytes 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 ky Doc ID 14733 Rev 11 45 105 Memory and register map STM8S207xx STM8S208xx Table 10 CPU SWIM debug module interrupt controller registers continued Address Block Register Label Register Name aed e Reserved area 15 bytes 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BKA2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM br
40. 1 5 10 1 6 10 1 7 54 105 Pin loading conditions Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10 Figure 10 Pin loading conditions STMB pin 50PF Wt Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11 Figure 11 Pin input voltage STMB pin Cm Wt Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics 10 2 K Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 15 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including Vppa ang Vppio 0 3 6 5 Input voltage on true open drain pins PE1 PE2 Vss 0 3 6 5 V VN Input voltage on any other pin Vas 0 3 Vpp 0 8 IVppx Vppl Variations between different power pins 50 IVssx Vggl Variations between all the different ground pins 50 see Absolute maximum Vesp Electrostatic discharge voltage ratings electrical sensitivity on page 88 1 All power Vpp Vppio Vppa and ground Vss Vssjo Vssa pins must always be connected
41. 16 gt DA SE E3 E1 32 9 Pin 1 identification 1 8 C Table 56 32 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Package characteristics 11 2 11 2 1 Thermal characteristics The maximum chip junction temperature T Aus must never exceed the values given in Table 18 General operating conditions on page 57 The maximum chip junction temperature T jm in degrees Celsius may be calculated using the following equation TJmax Tamax Ppmax X JA Where TAmax is the maximum ambient temperature in C O ja is the package junction to ambient thermal resistance in C W e Ppmax is the sum of Pintmax and Pi omax PDmax Pintmax Puomax PinTmax is the
42. 24 MH 114 i fopu faster 24 MHz crystal osc DI Ta 105 C HSE user ext clock 24 MHz 10 8 18 HSE crystal osc 16 MHz 9 0 Supply z e 1 current in fopu faster 16 MHz HSE user ext clock 16 MHz 82 15 2 run mode HSI RC osc 16 MHz 8 1 13 2 0 code executed cPU faster 2 MHz HSI RC osc 16 MHz 8 1 5 from Flash fopy fyaster 128 125 kHz HSI RC osc 16 MHz 1 1 Mun fmastep 128 15 625 uer RC osc 16 MHz 8 0 6 fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 55 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off ky Doc ID 14733 Rev 11 59 105 Electrical characteristics STM8S207xx STM8S208xx Table 21 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fopu faster 24 MHz HSE crystal osc 24 MHz 4 0 Ta 105 C HSE user ext clock 24 MHz 3 7 7 3 HSE crystal osc 16 MHz 2 9 Supply 2 currentin fcpu fmaster 16 MHz HSE user ext clock 16 MHz 2 7 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 cede ted HSE user ext clock 16 MHz 1 2 4 1 execute fopy fMasTER1 28 125 kHz from RAM HSI RC osc 16 MHz 1 0 1 3 foru vaster 128 15 625 uer RC osc 16MHz 8 0 55 fopy fMASTER 128 kHz LSI RC osc 128 kHz 0 45 Dr HSE crystal osc 24 MH 11 0 id fopu
43. 2C SDA PD6 UART3 RX PD4 PD3 H PD2 PD1 PDO PEO PE1 PE2 AL oH Aa ni Aa AL ah oH w o w N w o w a w 80 PD7 TLI TIM1_CH4 WR aw NRST OSCIN PA1 OSCOUT PA2 Vssio 1 Vss VCAP Von Vppio 1 UART1 RX UART1_TX UART1_CK PG1 CAN_RX 32L PGO CAN TX 311 PC7 HS SPI MISO 30H PC6 HS SPI MOSI 290 Vppio 2 Vssio_2 270 PC5 HS 260 PC3 HS 250 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 230 PE5 SPI_NSS I 2d0oo doosomwm N SPI_SCK TIM1_CH3 O N R N qo H A Op a HU HO uh HN 2 o O N a N HN VDDA Vssa N7 PB7 N6 PB6 N5 PB5 N4 PB4 N3 PB3 N2 PB2 N1 PB1 DN NO PBO N9 PE6 A A A A A A A A A l2C_SDA l2C_SCL TIM1_ETR TIM1_CH3N TIM1_CH2N TIM1_CH1N 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 4 CAN RXand CAN TX is available on STM8S208xx devices only d 26 105 Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Pinouts and pin description K Figure 7 LQFP 32 pin pinout NR
44. 5 bytes 0x00 5240 UART3 SR UARTS status register COh 0x00 5241 UART3_DR UARTS data register OxXX 0x00 5242 UART3 BRH1 UARTS baud rate register 1 0x00 0x00 5243 UARTS BRR2 UARTS baud rate register 2 0x00 0x00 5244 UART3 CR1 UARTS control register 1 0x00 0x00 5245 ne UART3_CR2 UARTS control register 2 0x00 0x00 5246 UART3_CR3 UARTS control register 3 0x00 0x00 5247 UART3_CR4 UARTS control register 4 0x00 0x00 5248 Reserved 0x00 5249 UART3_CR6 UARTS control register 6 0x00 c Reserved area 6 bytes 40 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Memory and register map Table 9 General hardware register map continued Address Block Register label Register name dune 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1 CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1 CCMR3 TIM1 capture compare
45. 7xx STM8S208xx Product overview 4 12 TIM4 8 bit basic timer e 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 4 TIM timer features Counter Timer Timer size Prescaler Counting CAPCOM Complem Ext synch bits mode channels outputs trigger onization chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No TIMS 16 Any power of 2 from 1 to 32768 Up 2 0 No i TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 4 13 Analog to digital converter ADC2 STM8S20xxx performance line products contain a 10 bit successive approximation A D converter ADC2 with up to 16 multiplexed input channels and the following main features e Input voltage range 0 to VppA e Dedicated voltage reference VREF pins available on 80 and 64 pin devices e Conversion time 14 clock cycles e Single and continuous modes e External trigger input e Trigger from TIM1 TRGO e Endofconversion EOC interrupt 4 14 Communication interfaces The following communication interfaces are implemented e UART1 Full feature UART SPI emulation LIN2 1 master capability Smartcard mode IrDA mode single wire mode UARTS Full feature UART LIN2 1 master slave capability SPI Full and half duplex 10 Mbit s 12C Up to 400 Kbit s beCAN rev 2 0A B 3 Tx mailboxes up to 1 Mb
46. DR Port H data output latch register 0x00 0x00 5024 PH_IDR Port H input pin value register 0x00 0x00 5025 Port H PH_DDR Port H data direction register 0x00 0x00 5026 PH CR1 Port H control register 1 0x00 0x00 5027 PH CR2 Port H control register 2 0x00 0x00 5028 PI_ODR Port data output latch register 0x00 0x00 5029 PI_IDR Port input pin value register 0x00 0x00 502A Port PI DDR Port data direction register 0x00 0x00 502B PI CR1 Port control register 1 0x00 0x00 502C PI CR2 Port control register 2 0x00 36 105 Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Memory and register map Table 9 General hardware register map Address Block Register label Register name heset status 0x00 5050 to 0x00 5059 Reserved area 10 bytes 0x00 505A FLASH CR1 Flash control register 1 0x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection register OxFF 0x00 505F FLASH IAPSR Flash in application programming status 0x00 register 0x00 5060 to 0x00 5061 Reserved area 2 bytes 0x00 5062 Flash FLASH PUKR FESTEN 0x00 register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065
47. EN EE EE ERR RE ES 52 Electrical characteristics 0 00 cece 53 10 1 Parameter conditions 53 10 1 1 Minimum and maximum values 53 10 1 2 Typical values 0 ee ees 53 10 4 3 Typicalcurves cece rn 53 10 1 4 Typical current consumption 53 10 1 5 Pin loading conditions 54 10 1 6 Loading capacitor 54 10 1 7 Pininputvoltage 3 s as s saan jak Rr ka III 54 10 2 Absolute maximum ratings 55 10 3 Operating conditions s 22sssss sansar ara aaa ra 57 10 3 1 VCAP external capacitor 58 10 3 2 Supply current characteristics 1 1 11 222sa sana 59 10 3 3 External clock sources and timing characteristics 66 10 3 4 Internal clock sources and timing characteristics 68 10 3 5 Memory characteristics 222sssssaskskanaaaaaanaaa 70 10 3 6 I O port pin characteristics liiis 71 10 3 7 Reset pin characteristics llli 77 10 3 8 SPI serial peripheral interface 79 10 3 9 PC interface characteristics 0 0 0 cece cece eee ees 82 10 3 10 10 bit ADC characteristics 20 0 0 000 e eee 84 10 3 11 EMC characteristics 0 000 0000 tee 87 Package characteristics 0 00 cece eee eee 90 11 1 Package mechanical data 91 11 1 1 LQFP package mechanical data 91 11 2 Thermal characteristics EEN ENEE 9 97 11 2 1 Reference document 97 11 2 2 Selecting the product temperature
48. Hz prescaler 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilisation time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles OPT6 Reserved OPT7 WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash data EEPROM memory 1 wait state is required if fopy gt 16 MHz 0 No wait state 1 1 wait state d Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Option bytes Table 13 Option byte description continued Option byte no Description BL 7 0 Bootloader option byte For STM8S products this option is checked by the boot ROM code after reset Depending on the content of addresses 0x487E 0x487F and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UMO560 STM8L S bootloader manual for more details For STMB8L products the bootloader option bytes are on addresses OxXXXX and OxXXXX 1 2 bytes These option bytes control whether the bootloader is active or not For more details refer to the UMO560 STMBL S bootloader manual for more details OPTBL K Doc ID 14733 Rev 11 51 105 Unique ID STM8S207xx STM8S208xx 9 Unique ID The devices feature a 96 bit unique device identifier which provides a ref
49. I RC OSC cPu 216 MHz isissssssinuaa ees 65 Typ Ipp wFi VS Vpp HSI RC OSC fopu le KEE 65 HSE external clock source 66 HSE oscillator circuit diagram 2 0 ren 67 Typical HSI frequency variation vs Vpp at 4 temperatures 68 Typical LSI frequency variation vs Von 28 69 Typical Vu and Vip vs Vpp 4 temperatures 1 1 s ssa saa kakan 72 Typical pull up resistance vs Vpp 4 temperatures 2 2sa eee 72 Typical pull up current vs Vpp 9 4 temperatures 72 Typ Vor 9 Vpp 5 V standard porte 74 Typ Vo 9 Vpp 3 3 V standard porte 74 Typ Vo 9 Vpp 5 V true open drain porte 74 Typ Vo 9 Vpp 3 3 V true open drain porte 75 Typ Vor 9 Vpp 5 V high sink porte 75 Typ Vo 9 Vpop 8 3 V high sink ports 2 BIB 75 Typ Vpp Vou 9 Vpp 5 V standard ports 0 2 0 eese 76 Typ Vpp Vou Vpp 3 3 V standard porte 76 Typ Vpp Vou 9 Vpp 5 V high sink porte 76 Typ Vpp Vou 9 Vpp 8 3 V high sink porte 77 Typical NRST Vj and Vip vs Vpp 4 temperatures else 77 Typical NRST pull up resistance vs Vpp 4 temperatures 78 Typical NRST pull up current vs Vpp 4 temperatures 2 2 ia 78 Recommended reset pin protection 1 llli 78 SPI timing diagram slave mode and CPHA 0 1 1 2222222 lakka unan 80 SPI timing diagram slave mode and CPHA 21 80 SPI timi
50. Il2C FREQR PC frequency register 0x00 0x00 5213 I2C_OARL DC own address register low 0x00 0x00 5214 12C_OARH DC own address register high 0x00 0x00 5215 Reserved 0x00 5216 2c DC DR DC data register 0x00 0x00 5217 DC SR1 DC status register 1 0x00 0x00 5218 l2C SR2 DC status register 2 0x00 0x00 5219 Il2C SR3 DC status register 3 0x00 0x00 521A I2C TIR DC interrupt control register 0x00 0x00 521B I2C CCRL DC clock control register low 0x00 0x00 521C Il2C CCRH DC clock control register high 0x00 0x00 521D I2C_TRISER UC TRISE register 0x02 edis Reserved area 18 bytes ec Doc ID 14733 Rev 11 39 105 Memory and register map STM8S207xx STM8S208xx Table 9 General hardware register map continued Address Block Register label Register name die 0x00 5230 UART1_SR UART status register OSCH 0x00 5231 UART1 DR UART1 data register OxXX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 0x00 5235 UART1 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 DEE Reserved area
51. Lmmmmmmmzmrrrir u ul GEESS gt gt SNS DFAA z zz2ecc ecec2epowrez SSS eases soe lt lt Zz QOouUSSIr2zzz oo z999 FEE AAS SS ESE TEBE 1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 4 CAN RXand CAN TX is available on STM8S208xx devices only ky Doc ID 14733 Rev 11 23 105 Pinouts and pin description STM8S207xx STM8S208xx Figure 4 LQFP 64 pin pinout PD7 TLI PD5 UART3 TX HS TIM2_CH1 BEEP HS TIM3_CH2 TIM1_BKIN CLK_CCO HS CLK_CCO HS TIM3_CH1 TIM2_CH3 Ty2C SCL HS TIM2_CH2 ADC_ETR HSySWIM T 2C SDA PE3 TIM1_BKIN PD6 UART3_RX PD4 PD3 PD2 PD1 PDO PEO PE1 PE2 PE4 PG7 PG6 NRST OSCIN PA1 OSCOUT PA2 Vssio_1 Vss VCAP Von Vppio 1 TIM8 CH1 TIM2_CH3 PA3 UART1_RX HS PA4 O 10 UART1 TX HS PA5 O 11 UART1 CK HS PA6 O 12 AIN15 PF7 L 13 AIN14 PF6 O 14 AIN13 PF5 D 15 AIN12 PF4 DO Joo Ek Go o ez o o N o 2 o o u e u oo u N u o u u u E u w u N u E u eo 16 N17 18 19 20 21 22 23 24 25 26 27 28 293031 32
52. M Data retention mode Halt mode or reset Vir max 2 V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 19 on page 58 for the value of Vir ay Flash program memory data EEPROM memory General conditions T4 40 to 125 C Table 36 Flash program memory data EEPROM memory Symbol Vpp Parameter Operating voltage all modes execution write erase Conditions fopu lt 24 MHz Min 2 95 Typ Max 5 5 Unit prog Standard programming time including erase for byte word block 1 byte 4 bytes 128 bytes 6 6 ms Fast programming time for 1 block 128 bytes 3 3 ms terase Erase time for 1 block 128 bytes 3 3 ms Now Erase write cycles program memory TA 85 C 10k Erase write cycles data memory TA 125 C 300 k 1M cycles tReT Ipp Data retention program memory after 10 k erase write cycles at TA 85 C Tret 55 C 20 Data retention data memory after 10 k erase write cycles at TA 85 C TRET 55 C 20 Data retention data memory after 300k erase write cycles at Ta 125 C Supply current Flash programming or erasing for 1 to 128 bytes Tret 85 C years mA Data based on characterization r
53. N The beCAN controller basic enhanced CAN interfaces the CAN network and supports the CAN protocol version 2 0A and B It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load For safety critical applications the beCAN controller provides all hardware functions to support the CAN time triggered communication option TTCAN The maximum transmission speed is 1 Mbit Transmission e Three transmit mailboxes e Configurable transmit priority by identifier or order request e Time stamp on SOF transmission Reception 8 11 and 29 bit ID One receive FIFO 3 messages deep Software efficient mailbox mapping at a unique address space FMI filter match index stored with message Configurable FIFO overrun Time stamp on SOF reception Six filter banks 2 x 32 bytes scalable to 4 x 16 bit each enabling various masking configurations such as 12 filters for 29 bit ID or 48 filters for 11 bit ID Filtering modes Mask mode permitting ID range filtering ID list mode e Time triggered communication option Disable automatic retransmission mode 16 bit free running timer Configurable timer resolution Time stamp sent in last two data bytes Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Pinouts and pin description
54. O1 X X Porth 591 PI2 1 O X X O1 X X Port 12 60 PI3 1 O X X O1 X X Port I3 61 PI4 1 O X X O1 X X Port 14 62 PI5 1 O X X O1 X X Port I5 63 49 PG5 1 O X X O1 X X Port G5 641501 PG6 1 O X X O1 X X Port G6 ky Doc ID 14733 Rev 11 31 105 Pinouts and pin description STM8S207xx STM8S208xx Table 6 Pin description continued Pin number Input Output z sz el sti ol o Pi 9 o i E ridi dr alalalala TS l S 2 0 v 2l ala 5 alternate after remap L LL L L s g z c Siola se function Geen GiG GIG G 6 Elo 46 5 option bit Al Al 20 4 a I x W 65 51 PG7 voix X O1 X X Port G7 66 52 PE4 V O X X O1 X X Port E4 67 53 37 PES TIMI BKIN O X X X 01 X X Port Ea Timer break input 68 54 38 34 PE2 C SDA VO X X 01 T Port E2 I2C data 69 55 39 35 PE1 I C SCL VO X X 01 T Port E1 12C clock 70 56 40 36 PEUCLK CCO lolx X x IHSlO3 X X Port Eo Configurable clock output 71 PI6 1 O X X O1 X X Port l6 72 PI7 1 O X O1 Port I7 TIM1 BKIN Timer 3 AFR3 73 57 41 37 25 PDO TIM3_CH2 1 O X X X HS O3 X X Port DO CLK_CCO AFR2 74 58 42 38 26 PDi SWIM lyo x X x HslO4 X X Port D1 GA data inte
55. PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 lc PCKEN24 Reserved PCKEN20 Reserved Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Product overview 4 6 4 7 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is base
56. RIT transmit UART1 12 12 12 1111 PAS UART1 CK l O X X X HS O3 X X Port A6 synchronous clock 13 PHO 1 O X X HS O03 X X Port HO 141 PH1 1 O X X HS OS X X Port H1 151 PH2 1 O X X O1 X X Port H2 16 PH3 1 O X X O1 X X Port H3 17 13 PFZ AIN1S O X X O1 X X Port F7 Analog input 15 18 14 PFG AIN14 Volx X 01 X X Port Fe nalog input 14 19 15 PFS AIN13 o X X O1 X X Port F5 Analog input 13 20 16 8 PFA AIN12 o x x 01 X X Port F4 nalog input 12 21 17 PFS AIN11 VO X X 01 X X Port F3 Analog input 11 ADC positive reference 22118 Vner S waa 23 19 13 12 9 VppA S Analog power supply ky Doc ID 14733 Rev 11 29 105 Pinouts and pin description STM8S207xx STM8S208xx Table 6 Pin description continued Pin number Input Output z DS BEEF Bi ee mw DIS Pin name s 2 E a 3t alternate a n n n a cz g gjaja function after remap G GiGIGG 95 EIS as option bit Al Al ll ll a Sr x OI 24 20 14 13 10 VssA S Analog ground ADC negative reference SS VREF S voltage 26 22 PFO AIN10 vo x x O1 x X Port Fo alog input 10 27 23 15 14 PB7 AIN7 VO X X X O1
57. SCL Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Electrical characteristics K Figure 40 Typical application with DC bus and timing diagram VDD VDD 47kQ 47 4 STM8S20xxx l START e J SUSTA oa wa Nf XK t SDA gt SH lr SDA Isu SDA gt tsu STA STO E th sTa 4 tw SCEL th SDA SCL tw SCLH jee tr SCL gt e gt 4 SOL 4 Su STO ai17 1 Measurement points are made at CMOS levels 0 3 x Vpp and 0 7 x Vpp Doc ID 14733 Rev 11 83 105 Electrical characteristics STM8S207xx STM8S208xx 10 3 10 84 105 10 bit ADC characteristics Subject to general operating conditions for VppA faster and Ta unless otherwise specified Table 44 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VppA 3 to 5 5 V 1 4 fanc ADC clock frequency MHz VppA 4 5 to 5 5 V 1 6 VppA Analog supply 3 5 5 V Vngr Positive reference voltage 2 75 VppA V Vrer Negative reference voltage Vssa o50 v Vssa Vppa V Vain Conversion voltage range Devices with external VREF Vrer V Vngr Vngr pins Internal sample and hold Canc capacitor 3 pF f 4 MHz 0 75 ts Sampling time ae us fADC 6 MHz 0 5 tstap Wakeup time from standby 7 us fADC 4 MHz 3 5 us Total conversion time including E conv sampling time 10 bit resolution fanc 6 MHz ee hS 14 l fApc
58. ST OSCIN PA1 OSCOUT PA2 Vss VCAP VDD Vppio AIN12 PF4 DD JO Om E obh N o PD5 UARTS TX HS TIM2_CH1 BEEP HS TIM3_CH2 TIM1 BKIN CLK_CCO HS TIM3_CH1 TIM2_CH3 HS TIM2_CH2 ADC_ETR HS SWIM PD7 TLI PD6 UART3_RX PD4 PD3 PD2 PD1 PDO w es w A w o N oO N o IW N N o m Cc oo SW Ho Be Be el EJ w hei R 2 a hel o Vopa Vssa N5 PB5 N4 PB4 N3 PB3 N2 PB2 N1 PB1 NO PBO UC SDA l2C_SCL TIM1_ETR TIM1 TIM1_CH2N TIM1_CH1N 240 PC7 HS SPI_MISO PC6 HS SPI_MOSI PC5 HS SPI_SCK PC4 HS TIM1_CH4 PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 PE5 SPI_NSS 1 2 HS high sink capability alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Doc ID 14733 Rev 11 27 105 Pinouts and pin description STM8S207xx STM8S208xx 28 105 Table 5 Legend abbreviations for pinout table Type l Input O Output S Power supply Level Input CM CMOS Output HS High sink Output speed O1 Slow up to 2 MHz O2 Fast up to 10 MHz OS Fast slow programmability with slow as default state after reset OA Fast slow programmability
59. STM8 Product class STM8 microcontroller S Family type S Standard 208 M Sub family type 208 Full peripheral set 207 Intermediate peripheral set Pin count K 32 pins S 44 pins C 48 pins R 64 pins M 80 pins B Program memory size 6 32 Kbyte 8 64 Kbyte B 128 Kbyte T Package type T LQFP 6 Temperature range 3 40 C to 125 C 6 40 C to 85 C B Package pitch No character 0 5 mm B 0 65 mm C 0 8 mm Packing No character Tray or tube TR Tape and reel TR For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you Refer to Table 2 STM8S20xxx performance line features for detailed description Doc ID 14733 Rev 11 101 105 Revision history STM8S207xx STM8S208xx 14 102 105 Revision history Table 58 Document revision history Date 23 May 2008 Revision 1 Changes Initial release 05 Jun 2008 Added part numbers on page 1 and in Table 2 on page 1 1 Updated Section 4 Product overview Updated Section 10 Electrical characteristics 22 Jun 2008 Added part numbers on page 1 and in Table 2 on page 1 1 12 Aug 2008 Added 32 pin device pinout and ordering information Updated UBC option d
60. TOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Ly Doc ID 14733 Rev 11 105 105
61. X X Port B7 us 28 24 16 15 PB6 AING VOX X X lot x x Port Be dut Analog DC SDA 29 25 17 16 11 PB5 AIN5 lO X X X O1 X X Port B5 input 5 AFR6 Analog Po SCL 30 26 18 17 12 PB4 AIN4 lO X X X O1 X X Port B4 input 4 AFR6 Analog TIM1_ETR 31 27 19 18 13 PB3 AIN3 lO X X X O1 X X Port B3 input 3 AFR5 Analo TI 32 28 20 19 14 PB2 AIN2 lO X X X O1 X X Port B2 in iE CH3N P AFR5 Analo TIMI 33 29 21 20 15 PB1 AIN1 lO X X X O1 X X Port B1 in e CH2N p AFR5 Analo TMA 34 30 22 21 16 PBO AINO lO X X X O1 X X Port BO in Ges CH1N P AFR5 35 PHaTIM1_ETR V O X X O1 x X Port H4 Timer 1 trigger input Timer 1 36 PH5 TIM1_CH8N I O X X O1 X X Port H5 Jinverted channel 3 Timer 1 37 PH6 TIM1_CH2N 1 O X X O1 X X Port H6 linverted channel 2 Timer 1 38 PH7 TIM1_CHIN I O X X O1 X X Port H7 inverted channel 2 39 31 23 PE7 AIN8 yox O1 Port E7 Analog input 8 40 32 24 22 PE6 AIN9 O X X X O1 X X Port E6 Analog input 9 30 105 Doc ID 14733 Rev 11 ki STM8S207xx STM8S208xx Pinouts and pin description Table 6 Pin description continued Pin number Input Output z DS TREES BE e ZE B Sl TI Pin name SP
62. ackage mechanical data 96 Thermal characteristics 97 Document revision history 102 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 ky STM8S20xxx performance line block diagram 12 Flash memory organisation 15 LQFP 80 pin pinout 1 135 Esia sale ete 23 LQFP 64 pin pinout esii ena aaaea nae ka A a E E EAS a a aa Ae a EE a RA E 24 EQFP 48 pin pinout 144 iesi EEN NEE hr Sl RA A edhe IX dE RYE RET 25 LQFP 44 pin pinout 0 00 0 26 LOFP 32 pin pinout NEE NEEN EE NEE aa NENNEN NEEN CN 27 Memory Wap 2215 dc s s ed aes E rem POSE acr RU RU RUE UR RUE pom RUE D A Se E RUE E 34 Supply current measurement conditions 53 Pin loading conditions 2 0 RI I eee 54 Pin input voltage silo ae mea RR RR RI p ye ga ee xau ae Ra Ex 54 tcPUmax VBISUS Vink EE 58 External capacitor Uer 58 Typ IDD RUN VS Vpp HS
63. and the max time is for the maximum time to validate the data Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z K Doc ID 14733 Rev 11 79 105 Electrical characteristics STM8S207xx STM8S208xx Figure 37 SPI timing diagram slave mode and CPHA 0 CPHA 0 FF CPOL 0 i i SCK Input GO 3i iT o 7 o A F tv SO Ab i t SCK t la SO Zap h SO pet gt ne m Mim dis SO 4 MISO i OUTPUT MSB OUT SE our SE OUT su Sl 9 4 atin 6 Ol INPUT l r this ai14134 Figure 38 SPI timing diagram slave mode and CPHA 10 NSS input SU NSS Eae tc SCKj NSS 44 CPHA 1 Lo 3 ANA 0 JF cc X amp CPOL 0 i deeg x CPHA 1 w SGKH 4 gt d i E if Ja pi SCK at di th SO Zap ees is Sons MISO So OUTPUT weier BIT6 OUT om OUT me Sl E EE SI INPUT L MSN o I I TAN em IN ai14135 i CPOL 1 mp un TE ru 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Von d 80 105 Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Electrical characteristics Figure 39 SPI timing diagram master mode High NSS input A le SCKj CPHA 0 N d N a CPOL 0 i z i T sl Eisen i n i i
64. apture compare 0x00 8038 13 TIM2 TIM2 update overflow 0x00 803C 14 TIM2 TIM2 capture compare 0x00 8040 15 TIM3 Update overflow 0x00 8044 16 TIM3 Capture compare 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19 Fe DC interrupt Yes Yes 0x00 8054 20 UART3 Tx complete 0x00 8058 21 UARTS Receive register DATA FULL 0x00 805C 22 ADC2 ADC2 end of conversion 0x00 8060 23 TIM4 TIM4 update overflow 0x00 8064 24 Flash EOP WR PG DIS 0x00 8068 Bee 0x00 806C to 0x00 807C 1 Except PA1 Lyr Doc ID 14733 Rev 11 47 105 Option bytes STM8S207xx STM8S208xx 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 12 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 12 Option bytes
65. cy of HSI oscillator factory calibrated 2 95 V Vpp 5 5 V 3 02 3 0 40 C lt T lt 125 C HSI oscillator wakeup 1 su HS time including calibration T ES HSI oscillator power 2 open consumption VE HA 1 Guaranteeed by design not tested in production 2 Data based on characterization results not tested in production Figure 18 Typical HSI frequency variation vs Vpp at 4 temperatures 40 C 3 7 25 C 85 C 2 125 C Lo o ee 2 3 T T T T T T i 2 5 3 3 5 4 4 5 5 5 5 6 Vpp V ai15067 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 34 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit figi Frequency 110 128 146 kHz Laut sn LSI oscillator wakeup time 70 US Ipp Lsi LSI oscillator power consumption 5 pA 1 Guaranteeed by design not tested in production Figure 19 Typical LSI frequency variation vs Vpp 25 C 3 4 2 gt 1 0 ee T 1 2 3 T T T d 2 5 3 4 5 5 5 6 Vop VI ai15070 ky Doc ID 14733 Rev 11 69 105 Electrical characteristics STM8S207xx STM8S208xx 10 3 5 70 105 Memory characteristics RAM and hardware registers Table 35 RAM and hardware registers Symbol Parameter Conditions Min Unit VR
66. d herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AU
67. d on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Doc ID 14733 Rev 11 17 105 Product overview STM8S207xx STM8S208xx 4 8 4 9 4 10 4 11 18 105 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode
68. device must be used in operating conditions that respect the parameters in Table 18 In addition full account must be taken of all physical capacitor characteristics and tolerances Table 18 General operating conditions Symbol Parameter Conditions Min Max Unit Ta lt 105 C 0 24 MHz fopu Internal CPU clock frequency 0 16 MHz Vpp Vpp jo Standard operating voltage 2 95 5 5 V Cext vapacnanee Mf A70 3300 nF external capacitor NCAR ESR of external capacitor GEF 0 3 Ohm ESR of external capacitor 15 nH 44 48 64 and 80 pin devices with output on 8 standard ports 2 high sink 443 Power dissipation at ports and 2 open drain ports Pp T4 85 C for suffix 6 simultaneously mW or TA 125 C for suffix 3 32 pin package with output on 8 standard ports and 2 360 high sink ports simultaneously Ambient ES SES Maximum power dissipation 40 85 T suffix version A Ambient SES SES Maximum power dissipation 40 125 C suffix version 6 suffix version 40 105 Ty Junction temperature range 3 suffix version 40 1309 1 Care should be taken when selecting the capacitor due to its tolerance as well as its dependency on temperature DC bias and frequency in addition to other factors 2 To calculate Pp TA use the formula Ppmax TJmax Ta Oja see Section 11 2 Thermal characteristics on page 97 with the value for Tjmax given in Table 18 above and the value
69. e 128 kHz 11 45 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CH1 register Table 25 Total current consumption in active halt mode at Vpp 3 3 V Conditions Symbol Parameter Main voltage Typ Unit regulator Flash model Clock source MVR HSE crystal osc 16 MHz 600 Operating mode 6 LSI RC osc 128 kHz 200 n HSE crystal osc 16 MHz 540 Ipp AH SE M Powerdown mode uA active halt mode LSI RC osc 128 kHz 140 Operating mode 66 Off k LSI RC osc 128 kHz Powerdown mode 9 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CH1 register d 62 105 Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Electrical characteristics Total current consumption in halt mode Table 26 Total current consumption in halt mode at Vpp 5 V T4 40 to 85 C Symbol Parameter Conditions Typ Max Unit Flash in operating mode HSI 63 5 Boss tege clock after wakeup x DD H upply current in halt mode H Flash in powerdown mode HSI 6 5 35 clock after wakeup Table 27 Total current consumption in halt mode at Von 3 3 V Symbol Parameter Conditions Typ Unit
70. e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIMS input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Fourindependent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM2 TIM3 16 bit general purpose timers 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 Timers with 3 or 2 individually configurable capture compare channels PWM mode Interrupt sources 2 or 3 x input capture output compare 1 x overflow update Doc ID 14733 Rev 11 ky STM8S20
71. each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 49 ESD absolute maximum ratings Symbol Ratings Conditions Class a Unit value Electrostatic discharge voltage TA 25 C conforming to VESD HBM Human body model JESD22 A114 A 2000 Y Electrostatic discharge voltage Ta 25 C conforming to VESD CDM Charge device model JESD22 C101 y 1000 X 1 Data based on characterization results not tested in production 88 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable I O pin is performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 50 Electrical sensitivities Symbol Parameter Conditions Class Ty 25 C A LU Static latch up class Ta 85 C A T 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when
72. eakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF pen Bugs Reserved area 5 bytes 1 Accessible by debug module only 2 Product dependent value see Figure 8 Memory map d 46 105 Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Interrupt vector mapping 7 Interrupt vector mapping Table 11 Interrupt mapping Eo Description WEED Makeup om Vector address RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes Yes 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTIS Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 beCAN beCAN RX interrupt Yes Yes 0x00 8028 9 beCAN beCAN TX ER SC interrupt 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIMI E 0x00 8034 12 TIM1 TIM1 c
73. erence number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm The unique device identifier is ideally suited e Foruse as serial numbers e Foruse as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory e Toactivate secure boot processes Table 14 Unique ID registers 96 bits Unique ID bits PH description 7 6 5 4 3 2 1 0 0x48CD X co ordinate on U_ID 7 0 0x48CE the wafer U_ID 15 8 Ox48CF v co ordinate on U ID 23 16 0x48D0 the wafer U_ID 31 24 0x48D1 Wafer number U ID 39 32 0x48D2 U_ID 47 40 0x48D3 U_ID 55 48 0x48D4 U_ID 63 56 0x48D5 Lot number U_ID 71 64 0x48D6 U_ID 79 72 0x48D7 U_ID 87 80 0x48D8 U_ID 95 88 52 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Electrical characteristics 10 10 1 10 1 1 10 1 2 10 1 3 10 1 4 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply vo
74. es of RST SR CLK SWCR 14 Sep 2010 10 CLK HSITRIMR CLK SWIMCCR IWDG KR and ADC DRx registers added the reset values of the CAN paged registers Figure 36 Recommended reset pin protection replaced 0 01 uF with 0 1 pF Figure 40 Typical application with I2C bus and timing diagram tw SCKH lw SCKL tsck and tysck replaced by twisci p tw scLL t scL and sc respectively Table 1 Device summary added STM8S207K8 Table 2 STM8S20xxx performance line features added STM8S207K8 device and changed the RAM value of all other devices to 6 Kbytes Figure 3 Figure 4 Figure 5 and Figure 7 removed TIM1 CHA from 22 Mar 201 1 11 pins 80 64 48 and 32 respectively Table 6 Pin description updated note 3 and added note 5 Table 9 General hardware register map removed DC PECH register Section 10 3 7 Reset pin characteristics added text regarding the rest network d Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services describe
75. escription in Table 13 on page 49 USART renamed UART1 LINUART renamed UART3 Max ADC frequency increased to 6 MHz 20 Oct 2008 Removed STM8S207K4 part number Removed LQFP64 14 x 14 mm package Added medium and high density Flash memory categories Added Section 6 Memory and register map on page 34 Replaced beCAN3 by beCAN in Section 4 14 5 beCAN Updated Section 10 Electrical characteristics on page 53 Updated LQFP44 Figure 47 and Table 55 and LQFP32 outline and mechanical data Figure 48 and Table 56 08 Dec 2008 Changed Vpp minimum value from 3 0 to 2 95 V Updated number of High Sink I Os in pinout Removed FLASH NFPR and FLASH _FPR registers in Table 9 General hardware register map 30 Jan 2009 Removed preliminary status Removed VQFN32 package Added STM8S207C6 STM8S207S6 Updated external interrupts in Table 2 on page 1 f Updated Section 10 Electrical characteristics 10 Jul 2009 Document status changed from preliminary data to datasheet Added LQFP64 14 x 14 mm package Added STM8S207M8 STM8S207SB STM8S208R8 STM8S208R6 STM8S208C8 and STM8S208C6 STM8S208SB STM8S208S8 and STM8S208S6 Replaced CAN with beCAN Added Table 3 to Section 4 5 Clock controller Updated Section 4 8 Auto wakeup counter Added beCAN peripheral impacting Table 7 and Figure 6 Added footnote about CAN_RX TX to pinout figures 3 4 and 6 Table 6 Removed X from wp
76. esults not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Electrical characteristics 10 3 6 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 37 1 O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level Vu voltage 0 3 0 3 x Vpp V Input high level Vpp 5 V Vin voltage 0 7 x Von Vpp 0 3 V V Vhys Hysteresis 700 mV Rou _ Pull up resistor Vpp 5 V Vin Vss 30 45 60 kQ Fast I Os 20 2 E te te Rise and fall time Load 50 pF R F 10 90 Standard and high sink I Os 425 2 ns Load 50 pF Input leakage lkg Current Vss S VinS Vpp 1 yA analog and digital Analog input lt lt 2 likg ana leakage current Vss VNS Von 230 La Leakage c rtent in Injection current 4 mA x10 uA att adjacent VO 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data based on characterization results not tested in production K Doc ID 14733 Rev 11 71 105
77. faster 24 MHz crystal osc DI i Ta lt 105 C HSE user ext clock 24 MHz 10 8 18 0 HSE crystal osc 16 MHz 8 4 Supply B 2 MR fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 82 15 2 run mode HSI RC osc 16 MHz 8 1 13 2 code 2 executed cPU faster 2 MHz HSI RC osc 16 MHz 8 1 5 from Flash fopu fuAsTER 28 125 kHz HSI RC osc 16 MHz 1 1 Kach fmasteR 128 15 625 HSI RC osc 16 MHZ 8 0 6 fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 55 1 Data based on characterization results not tested in production 2 Default clock configuration 60 105 Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Electrical characteristics Total current consumption in wait mode Table 22 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit fopu faster 24 MHz HSE crystal osc 24 MHz 2 4 Ta 105 C HSE user ext clock 24 MHz 1 8 4 7 HSE crystal osc 16 MHz 2 0 Supply fcpu fmaster 16 MHz HSE user ext clock 16 MHz 1 4 4 4 open current in HSI RC osc 16 MHz 12 16 mA wait mode fopu fuAsTER 1 28 125 kHz HSI RC osc 16 MHz 1 0 EH fmasteR 128 15 625 Tuer RC osc 16 MH2 8 0 55 fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default c
78. gram STM8S207xx STM8S208xx 3 Block diagram Figure 1 STM8S20xxx performance line block diagram Reset block 4 XTAL1 24 MHz lt gt Clock controller Reset Dee Reset 4 RC int 16 MHz Detector FOR BOR ES RC int 128 kHz Clock to peripherals and core Window WDG STM8 core lt gt 5 gt Independent WDG Debug SWIM Up to 128 Kbytes Single wire debug interf 400 Kbit s amp 10 Mbit s L high density program Flash 2 Fc lt gt Up to 2 Kbytes data EEPROM SPI 5 gt E Up to 6 Kbytes RAM UART1 5 gt lt gt Boot ROM Up to 16 bit advanced control KA Ge UART3 lt gt timer TIM1 LIN master SPI emul Master slave autosynchro 3 complementary outputs 1 Mbit s ul beCAN 5 gt lt gt 16 bit general purpose Ka Up to E timers TIM2 TIM3 5 CAPCOM channels Address and data bus RJ uc md NE 16 channels gt ADC2 lt gt 2 8 bit basic timer TIM4 1 2 4 kHz E Beeper lt beep AWU timer d 12 105 Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Product overview 4 4 1 Product overview The following section intends to give an overview of the basic features of the STM8S20xxx performance line functional modules and peripherals
79. hown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes on page 48 When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 Doc ID 14733 Rev 11 33 105 Memory and register map STM8S207xx STM8S208xx 6 Memory and register map 6 1 Memory map Figure 8 Memory map 0x00 0000 RAM up to 6 Kbytes 0x00 17FF M T 1024 bytes stack 0x00 1800 Reserved 0x00 3FFF 0x00 4000 Up to 2 Kbytes data EEPROM 0x00 47FF 0x00 4800 0x00 487F Option bytes 0x00 4900 i Reserved i 0x00 4FFF 0x00 5000 GPIO and peripheral registers 0x00 57FF see Table 8 and Table 9 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7FOO CPU SWIM debug ITC 0x00 7FFF registers see Table 10 0x00 8000 0x00 807F 32 interrupt vectors 0x00 8080 Flash program memory 64 to 128 Kbytes 0x02 7FFF 34 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Memory and register map
80. hrough a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources Four different clock sources can be used to drive the master clock 1 24 MHz high speed external crystal HSE Up to 24 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI _ 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 3 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 beCAN PCKEN23 ADC PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN 1 1 SPI PCKEN25 Reserved
81. ister 0x00 0x00 5346 TIM4_ARR TIM4 auto reload register OxFF ported Reserved area 185 bytes ec Doc ID 14733 Rev 11 43 105 Memory and register map STM8S207xx STM8S208xx Table 9 General hardware register map continued Address Block Register label Register name din 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC CR3 ADC configuration register 3 0x00 0x00 5404 SE ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADC TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC TDRL ADC Schmitt trigger disable register low 0x00 purius Reserved area 24 bytes 0x00 5420 CAN MCR CAN master control register 0x02 0x00 5421 CAN MSR CAN master status register 0x02 0x00 5422 CAN TSR CAN transmit status register 0x00 0x00 5423 CAN TPR CAN transmit priority register OxOC 0x00 5424 CAN RFR CAN receive FIFO register 0x00 0x00 5425 CAN IER CAN interrupt enable register 0x00 0x00 5426 CAN DGR CAN diagnosis register 0x0C 0x00 5427 CAN_FPSR CAN page selection register 0x00 0x00 5428 CAN PO CAN paged register 0 Oxxx 9 0x00 5429 CAN_P1 CAN paged register 1 Oxxx 9 0x00 542A CAN_P2 CAN paged register 2 0
82. it s Doc ID 14733 Rev 11 19 105 Product overview STM8S207xx STM8S208xx 4 14 1 UART1 Main features One Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fcp 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fcpy 16 LIN master mode Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame 4 14 2 UART3 Main features 20 105 1 Mbit s full duplex SCI LIN master capable High precision baud rate generator Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Product overview 4 14 3 Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fcp 16 and capable of following any standard baud rate regardless of the input
83. ity and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Suppo
84. lly the IAP and communication routines Figure 2 Flash memory organisation Data Data memory area 2 Kbytes EEPROM memory 2 00 00 0 00000 st Option bytes Programmable area from 1 Kbyte UBC area 2 first pages up to 128 Kbytes Remains write protected during IAP 1 page steps Up to 128 Kbytes Flash dq program memory Program memory area Write access possible for AP Doc ID 14733 Rev 11 15 105 Product overview STM8S207xx STM8S208xx 4 5 16 105 Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock fmaster coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safeclock switching Clock sources can be changed safely on the fly in run mode t
85. lock configuration measured with all peripherals off Table 23 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fopy fuAsTER 24 MHz HSE crystal osc 24 MHz 2 0 Ta 105 C HSE user ext clock 24 MHz 1 8 4 7 HSE crystal osc 16 MHz 1 6 Soen fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 1 4 4 4 upply DD WFI current in HSI RC osc 16 MHz 1 2 1 6 mA waitmode fopu fyaster 128 125 kHz HSI RC osc 16 MHz 1 0 a vaster 128 15 25 ici RC osc 16 MHz 8 0 55 cig fmastep 128 15 625 S RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off K Doc ID 14733 Rev 11 61 105 Electrical characteristics STM8S207xx STM8S208xx Total current consumption in active halt mode Table 24 Total current consumption in active halt mode at Vpp 5 V TA 40 to 85 C Conditions Symbol Parameter Mainvoltage Typ Max Unit regulator Flash model Clock source MVR 2 HSE crystal oscillator 16 MHz 1000 Operating mode ET i oscillator 128 kHz SM ean 2 S ill Supply current in HSE crystal oscillator 940 IDD H _ active halt mode 16 MHz HA Powerdown mode LSI RC oscillator 140 128 kHz Off Operating mode SI RC oscillator 68 Powerdown mod
86. ltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and T4 Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean x 2 X Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption For typical current consumption measurements Vpp Vppio and Vppa are connected together in the configuration shown in Figure 9 Figure 9 Supply current measurement conditions 5 V 0r 3 3 V A Von NP DDA Vppio Vss VssA Vssio Doc ID 14733 Rev 11 53 105 Electrical characteristics STM8S207xx STM8S208xx 10
87. ltage limits to be applied on any I O pin to SE ni k e C 2B FESD MASTER induce a functional disturbance conforming to IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 5 V Ta 25 C Verte applied through 100pF on Vpp and Vas pins fyasterR 16 MHz 4A to induce a functional disturbance conforming to IEC 61000 4 4 Doc ID 14733 Rev 11 87 105 Electrical characteristics STM8S207xx STM8S208xx Electromagnetic interference EMI Emission tests conform to the SAE IEC 61967 2 standard for test software board layout and pin loading Table 48 EMI data Conditions 1 Symbol Parameter Monitored Max fuse fcpu Unit SEET DS frequency band 8 MHz 8MHz 8 MHz 8 MHz 16 MHz 24 MHz 0 1MHz to 30 MHz 15 20 24 Vpp 5 V Peak level TA 25 C 30 MHz to 130 MHz 18 21 16 dByV SEMI LQFP80 package 130 MHz to 1 GHz 1 1 4 conforming to SAE IEC Se EM 61967 2 SAE EMI level 2 2 5 2 5 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of
88. mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1 CNTRL TIM1 counter low 0x00 0x00 5260 i TIM1 PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1 PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1 ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1 RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1_CCR8L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 ee Reserved area 147 bytes ky Doc ID 14733 Rev 11 41 105 Memory and register map STM8S207xx STM8S208xx
89. nction CLK_CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2 CHSG port D2 alternate function TIM3 CH 1 Port A3 alternate function TIM3_CH1 port D2 alternate function TIM2_CH3 AFRO Alternate function remapping option 0 0 Port D3 alternate function TIM2_CH2 1 Port D3 alternate function ADC_ETR K Doc ID 14733 Rev 11 49 105 Option bytes STM8S207xx STM8S208xx 50 105 Table 13 Option byte description continued Option byte no OPT3 Description LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler 00 24 MHz to 128 k
90. ng diagram master moda U r a othe hl Rae bee tet eee eaaauns 81 Typical application with DC bus and timing diagram 83 ADC accuracy characteristics ccc eee 86 Typical application with ADC 0 00 ccc tees 86 80 pin low profile quad flat package 4Axi i akak akar 91 64 pin low profile quad flat package 4Axi i tee 92 64 pin low profile quad flat package xip ee 93 48 pin low profile quad flat package xv 94 44 pin low profile quad flat package O0xim0 eee 95 32 pin low profile quad flat package xv 96 Doc ID 14733 Rev 11 7 105 List of figures STM8S207xx STM8S208xx Figure 49 8 105 STM8S207xx 208xx performance line ordering information scheme Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Introduction 1 Introduction This datasheet contains the description of the STM8S20xxx performance line features pinout electrical characteristics mechanical data and ordering information e Forcomplete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 e Forinformation on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e Forinformation on the STM8 core please
91. occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 47 EMS data Symbol Parameter Conditions Level class V Vo
92. ol of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 One free version that outputs up to 32 Kbytes of code is available For more information see www cosmic software com e Haisonance C compiler for STM8 One free version that outputs up to 32 Kbytes of code For more information see www raisonance com e STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Ordering information 13 Ordering information Figure 49 STM8S207xx 208xx performance line ordering information scheme 3 Example
93. ort C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 Doc ID 14733 Rev 11 35 105 Memory and register map STM8S207xx STM8S208xx Table 8 UO port hardware register map continued Address Block Register label Register name Vue 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register 0x00 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 0x00 5016 Port E PE_DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register 0x00 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0x00 0x00 5020 Port G PG DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG CR2 Port G control register 2 0x00 0x00 5023 PH O
94. ossible while executing code in program memory e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 The size of the UBC is programmable through the UBC option byte Table 13 in increments of 1 page 512 bytes by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory Up to 128 Kbytes minus UBC e User specific boot code UBC Configurable up to 128 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usua
95. product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pyomax represents the maximum power dissipation on output pins where Promax Nool Z Vpp Vouy lou and taking account of the actual Vo Jo and Voulog of the I Os at low and high level in the application Table 57 Thermal characteristics Symbol Parameter Value Unit SI mec cpm e 45 C W Oja aoe 46 C W M EE 57 C W Oja o bu DE 54 C W Oja GE EE 60 C W 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org Doc ID 14733 Rev 11 97 105 Package characteristics STM8S207xx STM8S208xx 11 2 2 98 105 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Figure 49 STM8S207xx 208xx performance line ordering information scheme 1 on page 101 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions e Maximum ambient temperature Tama 82 C measured according to JESD51 2 e IpDmax 15 mA Von 5 5 V e Maximum eight standard I Os used at the same time in output at low level with Io 10 mA Vg 22V e Maximum four high sink
96. racteristics liil nen 67 HSI oscillator characteristics liliis ren 68 LSI oscillator characteristics liliis eren 69 RAM and hardware registers 1l ss nsa kaka rn 70 Flash program memory data EEPROM memory 70 I O static characteristics liiis rh 71 Output driving current standard porte 73 Output driving current true open drain porte 73 Output driving current high sink porte 73 NRST pin characteristics 77 SPI characteristics 79 egene EE bem Ae tote bee E LU 82 ADC characteristics 84 ADC accuracy with RAIN lt 10kO VppA EM Li ULP Tu Sft IE E 85 ADC accuracy with Rain lt 10 kQ RAIN VDDA e MPH CV HM d 85 EMS data esaet dese e hem tes PA Eed a RACE Meech biet Que frr bee ee oe 87 EMI data LIT 88 Doc ID 14733 Rev 11 5 105 List of tables STM8S207xx STM8S208xx Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 6 105 ESD absolute maximum ratings llis ren 88 Electrical sensitivities 89 80 pin low profile quad flat package mechanical data 91 64 pin low profile quad flat package mechanical data 14 x 14 92 64 pin low profile quad flat package mechanical data 10 x 10 93 48 pin low profile quad flat package mechanical data 94 44 pin low profile quad flat package mechanical data 95 32 pin low profile quad flat p
97. refer to the STM8 CPU programming manual PM0044 ki Doc ID 14733 Rev 11 9 105 Description STM8S207xx STM8S208xx 2 Description The STM8S20xxx performance line 8 bit microcontrollers offer from 32 to 128 Kbytes Flash program memory They are referred to as high density devices in the STM8S microcontroler family reference manual All devices of the STM8S20xxx performance line provide the following benefits reduced System cost performance robustness short development cycles and product longevity The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I O independent watchdogs with a separate clock Source and a clock security system Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout memory map and and modular peripherals Full documentation is offered with a wide choice of development tools Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state of the art technology for applications with 2 95 V to 5 5 V operating supply 10 105 Doc ID 14733 Rev 11 ki STM8S207xx STM8S208xx Description K
98. rface 75 59 43 39 27 PDz riMa CH1 1 0 X X X HS OS X X Port D2 Timer 3 TIM2_CH3 channel 1 AFR1 76 60 44 40 28 PD TM2 CH2 O X X X HS 03 X X Port a Timer 2 ADS Sin channel 2 AFRO PD4 TIM2_CH1 B Timer 2 BEEP output 77 61 45 41 29 Ep VO X X X HS O3 X X Port D4 hannel 1 AFR7 78 62 46 42 30 PD5 UART3_TX V O X X X 01 X X Port p5 UARTS data transmit PD6 UARTS data 79 63 47 43 31 a ara pen VO X X X O1 X X Port D6 ceive Top level TIM1_CH4 80 64 48 44 32 PD7 TLI vol X X X O1 X X Port D7 Ta AFRA The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader These pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader 2 The beCAN interface is available on STM8S208xx devices only In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to Vpp are not implemented The PD1 pin is in input pull up during the reset phase and after the internal reset release Available in 44 pin package only On other packages the AFR4 bit is reserved and must be kept at 0 32 105 Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Pinouts and pin description 5 2 Alternate function remapping As s
99. rted by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 Doc ID 14733 Rev 11 99 105 STM8 development tools STM8S207xx STM8S208xx 12 2 12 2 1 12 2 2 12 3 100 105 Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 A free version that outputs up to 32 Kbytes of code is available STMB8 toolset STMB8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST Visual Develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Contr
100. to the external power supply 2 Iw must never be exceeded This is implicitly insured if Vjy maximum is respected If Vu maximum cannot be respected the injection current must be limited externally to the liy pi value A positive injection is induced by Vi Vpp while a negative injection is induced by Viy Vas For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected Doc ID 14733 Rev 11 55 105 Electrical characteristics STM8S207xx STM8S208xx Table 16 Current characteristics Symbol Ratings Max Unit Jupp Total current into Vpp power lines source 60 lyss Total current out of Vgs ground lines sink 2 60 Output current sunk by any I O and control pin 20 lo Output current source by any I Os and control pin 20 Total output current sourced sum of all I O and control pins for devices with two Vppio pins 200 Total output current sourced sum of all I O and control pins for devices with one Vppjo pin 100 R gt Total output current sunk sum of all UO and control pins for devices with two Vggio pins 190 Total output current sunk sum of all I O and control pins for R We 80 devices with one Vsgio pin Injected current on NRST pin 4 Ingen 9 Injected current on OSCIN pin 4 Injected current on any other pin 4 Zlinuemn Total injected current sum of all I O and control pins 9 20
101. tor oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Electrical characteristics Table 32 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fuse External high speed oscillator 1 24 MHz frequency Rr Feedback resistor 220 kQ Cc Recommended load capacitance 20 pF C 20 pF 6 startup fosc 24 MHz 2 stabilized 9 IpD HSE HSE oscillator power consumption mA C 10 pF 6 startup fosc 24 MHz 1 5 stabilized Om Oscillator transconductance 5 mA V tsutuse Startup time Vpp is stabilized 1 ms 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value Refer to crystal manufacturer for more details Data based on characterization results not tested in production tsu usE is the start up time measured from the moment it is enabled b
102. u column of I C pins no wpu available Added Table 11 Interrupt mapping d Doc ID 14733 Rev 11 STM8S207xx STM8S208xx Revision history Table 58 Document revision history continued Date Revision Changes Section 10 Electrical characteristics Added data for TBD values updated Table 15 Voltage characteristics and Table 18 General operating conditions updated VCAP specifications in Table 18 and in Section 10 3 1 VCAP external capacitor updated Figure 18 8 replaced Figure 19 updated Table 35 RAM and hardware registers cont d updated Figure 22 and Figure 35 added Figure 40 Typical application with DC bus and timing diagram Removed Table 56 Junction temperature range Added link between ordering information Figure 49 and STM8S20xx features Table 2 10 Jul 2009 Document status changed from preliminary data to datasheet Table 2 STM8S20xxx performance line features high sink UO for STM8S207C8 is 16 not 13 Table 3 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers updated bit positions for TIM2 and TIMG Figure 5 LQFP 48 pin pinout added CAN TX and CAN RX to pins 35 and 36 noted that these pins are available only in STM8S208xx devices Figure 7 LQFP 32 pin pinout replaced uart2 with uart3 Table 6 Pin description added footnotes concerning beC AN availability and UART1 RX and UART3_RxX pins Table 13 Option byte description added description of STM8L bootloader
103. ured with code executing in RAM Figure 14 Typ Ipp RUN vs Vpp HSI RC OSC fcpu 16 MHz 40 C ke 25 C 85 C 35 125 C 3 lt TI u E 25 H Io z 2 g 15 1 0 5 0 r r r r T T d 25 3 3 5 4 45 5 5 5 6 Voo V Figure 15 Typ Ipp wF vs VDD HSI RC osc fepy 16 MHz 40 C 254 25 C 85 C 2 125 C T E 15 Ba 2 0 5 0 T T T T d 25 d 3 5 4 45 5 55 6 Von V ki Doc ID 14733 Rev 11 65 105 Electrical characteristics STM8S207xx STM8S208xx 10 3 3 66 105 External clock sources and timing characteristics HSE user Subject to general operating conditions for Vpp and Ty external clock Table 31 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit ins um sad Em clock source 0 24 MHz Vasen SEH input pin high level 0 7 x Vpp Vpp 0 3 V V EC input pin low level Ve 0 3 x Vpp i ILEAK_HSE eech EES Vss lt Vin lt Vpp 1 1 uA 1 Data based on characterization results not tested in production Figure 16 HSE external clock source External clock source VHseH b 4 VHSEL L OSCIN JUUL D gt fuse STM8 HSE crystal ceramic resona
104. ved area 3 bytes 0x00 50D1 Wd WWDG CR WWDOG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to 0x00 50DF Reserved area 13 bytes 0x00 50E0 IWDG_KR IWDG key register Oxxx 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register OxFF 0x00 50E3 to 0x00 50EF Reserved area 13 bytes 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer register Ox3F 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F 0x00 50F4 to 0x00 50FF Reserved area 12 bytes 38 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Memory and register map Table 9 General hardware register map continued Address Block Register label Register name due 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 CR SPI DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF DEAE Reserved area 8 bytes 0x00 5210 DC CR1 DC control register 1 0x00 0x00 5211 I2C_CR2 DC control register 2 0x00 0x00 5212
105. with fast as default state after reset Port and control configuration Input float floating wpu weak pull up Output T True open drain OD Open drain PP Push pull Reset state Bold X pin state after internal reset release Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release Doc ID 14733 Rev 11 d STM8S207xx STM8S208xx Pinouts and pin description Table 6 Pin description Pin number Input Output SE BESSER d T re mw e o zl I A Pin name E E E 3 5 alternate R nasa FES S Saa CS functi after remap w L L uu sez cS oa unction tion bit GoGo E Se GG option bit ui 1 1 1 1 1 NRST UO X Reset 2 2 2 2 2 PAI OSCIN vol x x O1 X X Port A1 Resonator crystal in 33 38 s s3 PaoscouUT olx x x Lol x x Port az Resonator crystal out 41414 14 Vssio 1 S UO ground 5 5 5 5 4 Vss S Digital ground 6 6 1665 VCAP S 1 8 V regulator capacitor 7 7 7 7 6 Vpp S Digital power supply 8 8 8 8 7 Vppo 1 S UO power supply Timer 2 TIM3_CH1 9 19191 PAS TIM2 CH3 O X X X O1 X X Port A3 channel3 AFR1 10 10 1101 9 PA4 UART1_RX 10 X X X HS O3 X X Port A4 UART1 receive 11111 111 101 PAS UART1 TX 1 O X X X HS OS X X Port A5 PA
106. xXx 9 0x00 542B beCAN CAN_P3 CAN paged register 3 Oxxx 9 0x00 542C CAN P4 CAN paged register 4 Oxxx 3 0x00 542D CAN P5 CAN paged register 5 Oxxx 3 0x00 542E CAN_P6 CAN paged register 6 Oxxx 9 0x00 542F CAN_P7 CAN paged register 7 Oxxx 9 0x00 5430 CAN P8 CAN paged register 8 Oxxx 9 0x00 5431 CAN P9 CAN paged register 9 Oxxx 9 0x00 5432 CAN PA CAN paged register A Oxxx 9 0x00 5433 CAN PB CAN paged register B Oxxx 9 0x00 5434 CAN PC CAN paged register C Oxxx 9 0x00 5435 CAN PD CAN paged register D Oxxx 9 0x00 5436 CAN PE CAN paged register E Oxxx 9 44 105 Doc ID 14733 Rev 11 ky STM8S207xx STM8S208xx Memory and register map Table 9 General hardware register map continued Address Block Register label Register name deed 0x00 5437 beCAN CAN PF CAN paged register F Oxxx 9 Ge Reserved area 968 bytes 1 Depends on the previous reset source 2 Write only register 3 If the bootloader is enabled it is initialized to 0x00 Table 10 CPU SWIM debug module interrupt controller registers Address Block Register Label Register Name eech 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 cPu XL X index register low 0x00 0x
107. y of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for In pin and Zlwupmn in Section 10 3 6 does not affect the ADC accuracy Table 46 ADC accuracy with RAIN 10 ko RAIN VppA 3 3 V Symbol Parameter Conditions Typ Max Unit fADC 2MHz 1 1 2 lEx Total unadjusted error fADC 4 MHz 1 6 2 5 fap 2 MHz 0 7 1 5 IEg Offset error E fapc 4 MHz 1 3 2 fap 2 MHz 0 2 1 5 IE Gain error LSB fapc 4 MHz 0 5 2 fap 2 MHz 0 7 1 lEpl Differential linearity error fapc 4 MHz 0 7 1 fap 2 MHz 0 6 1 5 IE Integral linearity error S fapc 4 MHz 0 6 1 5 Doc ID 14733 Rev 11 85 105 Electrical characteristics STM8S207xx STM8S208xx 86 105 Figure 41 ADC accuracy characteristics A i g p HS Ee Vasa V T 1022 _ ppa7 Ssa 1LSB 7 7 IDEAL 1024 Zz z 1021 4 qe l B eu i Hel E dE pt L4 8 e 7 WI 1 6 f 2 pesce 1 Zi A 1 Le 1 k 5 4 o 4 4 Eo EL 1 Je 3 4 i 2 i i i 7 P E i 2 1 7 L i 1 DOE W 1 LSBipeaL i i L i L I 0 1 2 3 4 5 6 T 1021102210231024 VssA Vopa 1 Example of an actual transfer curve
108. y software to a stabilized 24 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 17 HSE oscillator circuit diagram Resonator fuse to core OSCIN gt p Resonator IS Consumption control STM8 OSCOUT HSE oscillator critical gm formula 2 Jmcrit 2x x fuse x Rm 2Co C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification C Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 42C 52C Grounded external capacitance Om gt gt Omcrit ky Doc ID 14733 Rev 11 67 105 Electrical characteristics STM8S207xx STM8S208xx 10 3 4 68 105 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and TA fuse High speed internal RC oscillator HSI Table 33 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fug Frequency 16 MHz Trimmed by the Accuracy of HSI oscillator CLK_HSITRIMR register 4 edis 1 0 for given Vpp and TA conditions Vpp 5 V Ta 25 C 1 5 1 5 ACCugsi Von 5 V 3 96 25 C lt Ta lt 85 C SH ES Accura
109. zation results not tested in production Table 39 Output driving current true open drain ports Symbol Parameter Conditions Max Unit lo 10 mA Vpp 5 V 1 VoL Output low level with 2 pins sunk ho 10 mA Vpp 3 3 V 1 50 V lio 20 mA Vpp 5 V 20 1 Data based on characterization results not tested in production Table 40 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk lio 10 MA Vpp 5 V 0 8 VoL Output low level with 4 pins sunk lio 10 MA Vpp 3 3 V 100 Output low level with 4 pins sunk lio 20 MA Vpp 5 V 1 50 y Output high level with 8 pins sourced lio 10 mA Vpp 5 V 4 0 Vou Output high level with 4 pins sourced lio 10 mA Vpp 3 3 V 2 101 Output high level with 4 pins sourced lio 20 mA Vpp 5 V 3 3 1 Data based on characterization results not tested in production A Doc ID 14733 Rev 11 73 105 Electrical characteristics STM8S207xx STM8S208xx Typical output level curves Figure 24 to Figure 31 show typical output level curves measured with output on a single pin Figure 23 Typ Vo 8 Vpp 5 V standard ports 40 a 25 C 125 85 C 125 C Vor V Figure 24 Typ Vo Vpp 3 3 V standard ports 40 C a 25 C 1 25 85 C 125 C 0 75 Vor V lo mA

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