C TG INO_ver1.4(2)
Contents
1. n BED a sz ernie 27 52 carm rans se roma 2 35 Germ 2 36 40 F1LY6 J2 40 41 FLLY7 da Aq 42 11 7 J2 42 43 FLLY8 J2 43 44 F1LY8 J2 44 45 FLLY9 J2 45 46 F1LY9 J2 46 47 F1LY10 72 47 F2LY10 48 F1LY10 J2 48 F2LY10 51 FILY12 02 51 F2LY12 52 F1LY12 22 52 F2LY12 53 F1LY13 72 53 F2LY13 1 54 F1LY13 2 54 F2LY13 1 55 F1LY14 72 55 F2LY14 1 56 F1LY14 02 56 F2LY14 1 58 GND 72 58 GND 1 59 GND 72 59 GND 1 60 GND 52 60 GND C d Gul Gul ql Gl Gl ql C G 1 cl al ql ql Gl ql ql c G J4 32 F3LY2 4 33 F3LY3 4 34 4 35 F3LY4 4 36 F3LY4 4 37 F3LY5 4 38 F3LY5 4 39 F3LY6 4 40 F3LY6 4 41 F3LY7 4 42 F3LY7 4 43 F3LY8 4 44 F3LY8 4 45 F3LY9 4 46 F3LY9 74 49 F3LY11 4 50 F3LY11 4 51 F3LY12 4 52 F3LY12 4 53 F3LY13 4 54 F3LY13 4 55 F3LY14 4 56 F3LY14 4 57 GND 4 58 GND 4 59 GND 4 60 GND al Cil Gl Gl Gay Gil Ga Gil Gal GI aT a O 00 29731 15 32 Laro 5 34 15 35 15 36 5 37 15 38 55 39 J5 40 C Co G Oly O1 Ory Guy O1 Aj Bl A BY Ln 75 4 C2. 15 4 5 50 5 51 15 52 19 53 15 54 5 55 5 56 5 57 15 58 5 59 5 60 LO F4LY2 FALY2 F4LY3 FALY3 F4uy4 F4LY4 F4LY5 FALY5 F4LY6 FALYO 41 7 FALY7 F4LY8 F4LY8 F4LY9 F4LY9 F4LY1 F4LY10 FALY1 FALY1 FALYI FALYI1 FALYI FALYI FALYI FALYI GNI GNI GNI GNI T w N N L I 4 D T OO UOT O J 21 J2 J4 J5 1 FILX1 J2 1 F2LX1 J4 1 F3LX1 75 1 F4LX1 3 F1LX2 32 3 F2LX2 J4 3 F3LX2 195 3 F4LX2 4 F1LX2 52 4 F2LX2 J4 4 F3LX2 95 4 FALX2 5 F1LX3 02 5 F2LX3 J4 5 F3LX3 195 5 F4LX3 T eme 22 ema pur Iesus as rae s nus rane w s Tesua s s Pana prs ense w s Iesus s s ra 10 FLLX5 72 10 F2LX5 J4 10 F3LX5 J5 10 FALX5 11 F1LX6 72 i F2LX6 J4 11 F3LX6 75 11 F4LX6 12 F1LX6 72 12 F2LX6 94 12 F3LX6 75 12 F4Lx6 13 FLLX7 22 13 21 7 J4 13 F3LX7 5 13 F4LX7 14 FLLX7 72 14 21 7 J4 14 F3LX7 75 14 FALX7 15 F1LX8 J2 15 F2LX8 J4 15 F3LX8 75 15 F4LX8 16 FLLX8 02 16 F21X8 J4 16 F3LX8 75 16 FA4LX8 17 FLLX9 72 17 F2LX9 4 17 F3LX9 25 17 FALX9 18 FL
3. TO F2Y TO TO FAY These are 16 bit counters except LTO which is 24 bit counter and will enable on CAMAC command amp 1 amp F 26 and will disable on CAMAC command amp A 1 amp F 24 readable on CAMAC bus using CAMAC commands as follows Read Scalar LTO low N amp A 14 amp F 2 Read Scalar LTO high gt N amp A 15 amp F 2 bits 8 15 are 0 Read Scalar Lam width low gt amp 12 amp F 2 Read Scalar LAM width high gt amp A 13 amp F 2 bits 8 15 are 0 Read Scalar TO F1X gt amp A 0 amp F 2 Read Scalar F2X gt N amp A 1 amp F 2 Read Scalar F3X gt N amp A 2 amp F 2 Read Scalar TO FAX amp A 3 amp F 2 Read Scalar TO F1Y amp 4 amp F 2 Read Scalar F2Y gt N amp A 5 amp F 2 Read Scalar F3Y gt N amp A 6 amp F 2 Read Scalar TO FAY N amp A 7 amp F 2 These scalars can be cleared by individual commands or a common command as follows Reset Scalar LTO amp A 14 amp F 11 Read Scalar_Lam_width gt N amp A 12 amp F 2 Reset Scalar TO FIX gt amp A 0 amp F 11 Reset Scalar TO F2X amp A 1 amp F 11 Reset Scalar TO F3X amp AQ amp F 11 Reset Scalar TO FAX amp 3 amp F 11 Reset Scalar TO F1Y gt amp A 4 amp F 11 Reset Scalar F2Y N amp A 5 amp F 11 Reset Scalar TO F3Y N amp A 6
4. Bit 3 F4LX8 F4LX5 Bit 0 x FAY6 F4X13 mask register N amp A 12 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F4LY6 F4LY5 FALY4 F4ALY3 F4LY2 FALY1 F4LX14 F4LX13 F4LY 14 F4LY7 mask register N amp A 13 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F4LY14 F4LY13 FALY12 FALY11 FALY10 FALYO FALY8 F4LY7 The blocking of respective input works as follows Mask reg input 5o olo trigger logic F 17 AQ 0W n z Preset Q F 17 AQ W n 20 orZ Clr If mask is set then the respective input does not take part in the trigger logic but allows the other inputs to decide the coincidence Once mask is set the respective input is always treated as 1 On POWER 7 all masks are set but no trigger will be generated inputs to be unmasked Only ones which are no working should be masked Mask for intermediate trigger N amp A 14 amp 0 with data bits as shown The blocking of respective intermediate trigger works as follows Intermediate trigger Active gis N To trigger logic Mask reg Ma k five hich T TO Preset Q F 17 A 14 W n 1 F 17 A 14 W n 0 Or Z Clr If mask is set then the respective intermediate trigger does not take part in further trigger logic but allows the other intermediate trigger inputs to decide the coincidence Once mask is set the respective in
5. amp F 11 Reset Scalar FAY N amp A 7 amp F 11 Reset ScalarsAll gt N amp A 15 amp F 11 Total of 10 scalars Scalers on LTO and LAM width are 24bit Others are 16bits Status of control signal The status of control signals like I LAM Q X can be read on CAMAC command N amp A 1 amp F 1 The bit pattern is as follows General Upon POWER ON and command Z the module will be in clear state i e LAM REQ will be cleared LAM ENABLE will be reset scalers will be cleared Multiplicity Latched input registers will be zero All input masks are set Command accepted signal X is generated on each implemented CAMAC command as listed in this manual Commands C and I have not been implemented and have no effect on the module CAMAC TRIGGER GENERATOR for INO INO Application note This note gives a guide on the use of the module It describes the connector details input interconnections and CAMAC commands It will serve as a ready reference Front panel diagram Connector details There are two boards one base board which has the CFMFC PC edge connector and one piggy board which connects to the base board via a 60 pin FRC cable Connectors J1 and J2 on the piggy board connectors J4 and J5 are on the base board and connectors J3 on both the boards for interconnection Picov hoard J3 J4 RaFrd TI 15 12
6. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 F2LY6 F2LY5 F2LY4 F2LY3 F2LY2 F2LY1 F2LX14 F2LX13 Read Command amp 3 amp F 0 with data bits as shown Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 F3LX8 F3LX7 F3LX6 F3LXS F3LX4 F3LX3 F3LX2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F2LY14 F2LY13 F2LY12 F2LY11 F2LY10 F2LY9 F2LY8 F2LY7 Read Command amp A 4 amp 0 with data bits as shown Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 F3LY10 F3LY9 F3LY8 F3LY7 F3LY6 F3LY5 F3LY4_ F3LY3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F3LY2 F3LY1 F3LX14 F3LX13 F2LX12 F3LX11 F3LX10 F3LX9 Read Command amp A 5 amp 0 with data bits as shown Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 F4LX12 F4LX11 F4LX10 F4ALX9 F4LX8 FALX7 F4LX6 F4LXS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FALXA4 FALX3 FALX2 F4LX1 F3LY14 F3LY13 F3LY12 F3LY11 Read Command amp 6 amp 0 with data bits as shown Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 F4LY14 F4LY13 F4LY12 FALY11 FALY10 FALY9 FALY7 Read Command amp 7 amp F 0 with data bits as shown Bit 15 0 Bit 14 Bit 13 0 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 Scalars LTO TO_F1X TO F2X TO F3X TO
7. CAMAC TRIGGER GENERATOR for INO INO Contents Specifications User manual Test setup and observations Application note Technical reference manual CAMAC TRIGGER GENERATOR for INO INO Specifications The CAMAC Trigger Generator INO CTG has been designed to generate final trigger based on Predefined Coincidence Criterion on a large number of input signals from the prototype Neutrino detector Additionally it has SCALARS for the FINAL TRIGGER and for a number of intermediate coincidence logic signals The SCALARS can be read on CAMAC The valid signals are latched with final trigger and can also be read on CAMAC Inputs can be individually deselected from taking part in the trigger generation It has been implemented as a two width CAMAC module and most of the logic has been implemented in Altera 10K50 field programmable gate array device I COINCIDENCE i BLOCK registers I CAMAC bus SCALERS t LAM logic lt i Logic Trigger Trigger Out lt Final Trigger Fig 1 Block Schematic of the INO_CTG This module accepts first level trigger information derived from the individual layers of the detectors namely in terms of one two three and four fold signals Further COINCIDENCE LOGIC is implemented in the INO_CTG module There are a total of 112 signals coming on LVDS lines to the CAMAC module Trigger signals generated from the detector assembly Input One two three an
8. F N3 170 Write data 0 NAF N 4170 Write data 0 NAF N 5170 Write data 0 NAF N 6170 Write data 0 7 170 Write data 0 NAF 8 170 Write data 0 NAF N 9170 Write data 0 NAF N 10170 Write data 0 NAF N 11170 Write data 0 NAF N 12 170 Write data 0 NAF N 13 170 Write data 0 NAF N 14170 3 Disabling a specific input for ex Input F3LX1 Write data 254 NAF N717 This enables all the other inputs in this group 4 Enabling a specific input for ex Input F3LX1 Write data 1 NAF N717 This disables all the other inputs in this group If it is required to enable or disable a specific input without disturbing others in the group then the previous value of the group must be preserved and only that bit should be modified In the above example if the group mask is defined as MASKS then it should be modified as MASK8 MASKS bit wise AND OxFE to enable and MASK8 MASKS bit wise OR 0x01 to disable 5 Reading multiplicity registers NAF N 026 enable LAM Wait for LAM NAF N00 Read data NAF N10 Read data NAF N20 Read data NAF N30 Read data NAF N40 Read data NAF N50 Read data NAF N60 Read data NAF N70 Read data NAF N 0 10 reset LAM 6 Reading scalers NAF N02 Read data NAF N12 Read data NAF N22 Read data NAF N 32 Read data NAF N 42 Read data 52 Read data NAF N 62 Re
9. F 10 Once LAM is generated and till it is cleared another event will generate only LTO and not FTO LAM disable F 24 A 0 LAM enable F 26 A 0 FTO Reset LAM F 10 A 0 or Z LOGIC Mask registers are provided to individually enable disable inputs from taking part in the coincidence After power on all channels are masked According to the bits in the mask corresponding inputs will be masked bit 20 or unmasked bit 1 The Mask registers are 8 bit wide and the bits assignment is as follows F1X8 F1 X1 mask register N amp A 0 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FILX8 FILX7 FILX6 FILXS FILX4 FILX3 FILX2 FILXI F1Y2 F1X9 mask register N amp A 1 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FILY2 FILY1 FILX14 FILX13 FILX12 FILX11 FILXIO FILX9 F1Y10 F1Y3 mask register N amp A 2 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FILY10 FILY9 FILYS FILY7 FILY6 FILYS FILY4 FILY3 F2X4 F1Y11 mask register N amp A 3 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 F2LX4 F2LX3 F2LX2 F2LXI Bit 2 Bit 1 FILY13 FILY12 Bit 0 FILY11 Bit 3 FILY14 F2X12 F2X5 mask register N amp A 4 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F2LX12
10. F2LX11 F2LX10 F2LX9 F2LX8 F2LX7 F2LX6 F2LXS F2Y6 F2X13 mask register N amp A 5 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 F2LY6 F2LYS F2LY4 F2LY3 Bit 3 F2LY2 Bit 2 Bit 1 F2LY1 F2LX14 Bit 0 F2LX13 14 F2LY7 mask register amp 6 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F2LY14 F2LY13 F2LY12 F2LY11 F2LY10 F2LY9 F2LYS F2LYT7 F3X8 F3X1 mask register N amp A 7 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F3LX8 F3LX7 F3LX6 F3LX5 F3LXA4 F3LX3 2 F3LX1 F3Y2 F3X9 mask register N amp A 8 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F3LY2 F3LY1 F3LX14 F3LX13 F3LX12 F3LX11 F3LX10 F3LX9 10 F3Y3 mask register N amp A 9 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 F3LY10 F3LY9 F3LY8 F3LY7 Bit 2 Bit 1 F3LYS F3LY4 Bit 3 F3LY6 Bit 0 F3LY3 F3Y11 mask register N amp A 10 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FALX4 F4LX2 F4LX1 F3LY14 F3LY13 F3LY12 F3LY11 F4X12 F4X5 mask register N amp A 11 amp F 17 with data bits as shown Bit 7 Bit 6 Bit 5 Bit 4 F4LX12 F4LX11 F4LX10 FALX9 Bit 2 Bit 1 F4LX7 FALX6
11. F2LX6 F2LX11 amp LX12 amp F2LX13 amp F2LX14 F2LY amp F2LY2 amp F2LY3 amp F2LY4 F2LY2 amp F2LY3 amp F2LY4 amp F2LY5 F2LY3 amp F2LY4 amp F2LY5 amp F2LY6 F2LY11 amp F2LY12 amp F2LY13 amp F2LY14 F3LX1 amp F3LX2 amp F3LX3 F3LX2 amp F3LX3 amp F3LX4 F3LX3 amp F3LX4 amp F3LX5 F3LX12 amp X13 amp 14 F3LY amp F3LY2 amp F3LY3 F3LY2 amp F3LY3 amp F3LY4 F3LY3 amp F3LY4 amp F3LY5 F3LY12 amp FILY13 amp F3LY14 FALX amp F4LX2 FALX2 amp F4LX3 FALX3 amp F4LX4 FALX13 amp F4LX14 FALY amp F4LY2 F4LY2 amp F4LY3 F4LY3 amp F4LY4 13 amp F4LY14 LTO TO_F1X TO_FLY TO_F2Y TO TO FAX TO F4Y Note LTO is assigned to one of the front panel outputs connector LAM ENABLE SET N amp A 0 amp F 26 LAM ENABLE RESET N amp 0 amp F 24 Z S2 LAM REQD 1 LAM REQ CLK FTO LAM REQ RESET amp A 0 amp F 10 752 LAM LAM REQ amp LAM ENABLE FTO LTO amp LAM Note FTO is assigned to three of the front panel NIM outputs on Lemo connectors Q LAM CAMAC command amp A 0 amp F 8 LAM LOGIC Final LAM signal is sent on CAMAC bus when FTO is generated and LAM is enabled through CAMAC command N amp A 0 amp F 26 LAM can be disabled through CAMAC command N amp A 0 amp F 24 and reset through CAMAC command N amp A 0 amp
12. LX9 02 18 F2LX9 J4 18 F3LX9 75 18 F4LX9 19 FLLX10 J2 19 F2LX10 94 19 F3LX10 I J5 19 F4LX10 RU F11X10 32 20 F2LX10 74 20 F3LX10 75 20 F4LX10 SE FILX11 22 21 F2LX11 i J4 21 F3LX11 195 21 F4LX11 22 F1LX11 72 22 F2LX11 J4 22 11 195 22 F4LX11 23 11 12 22 23 F2LX12 i J4 23 F3LX12 195 23 F4LX12 24 F1LX12 72 24 F2LX12 74 24 F3LX12 25 24 FALX12 25 FLLX13 72 25 F2LX13 i 74 25 F3LX13 195 25 F4LX13 26 F1LX13 72 26 F2LX13 I 74 26 F3LX13 25 26 FALX13 27 FILX14 02 27 F2LX14 i J4 27 F3LX14 195 27 FALX14 28 F1LX14 22 28 F2LX14 J4 28 F3LX14 25 28 F4LX14 29 F1LY1 52 29 F2LYl 74 29 F3LY1 75 29 F4LY1 1 30 F1LY1 72 30 F2LY1 J4 30 F3LY1 75 30 F4LY1 commands For INO TEST module Z C reset module F 26 A 0 Disable O P F 24 A 0 enable O P F 16 A 0 enable or Disable coincidence pattern out of 5 O P Example COMMAND F 24 A 0 Write DATA IF COMMAND F 16 A 0 will enable all 5 O P For INO module Initialize Z Set LAM mask clear LAM clear multiplicity register clear scalers F 0 A 0 7 Read multiplicity registers F 1 A 1 Read status F 2 A 0 7 read scalers on intermediate coincidences F 2 A 14 15 read LTO scaler F 2 A 12 13 read LAM width scaler F 8 A 0 Test LAM Q 0 if LAM set F 10 A 0 Clear LAM F 11 A 0 15 clear scal
13. ad data NAF N72 Read data NAF N 12 2 read LAM width scaler low Read data NAF N 132 read LAM width scaler high Read data NAF N 142 read LTO scaler low Read data NAF 152 read LTO scaler high Read data CAMAC TRIGGER GENERATOR for INO INO CTG Test setup and observations Test setup As the inputs to the INO CTG module are LVDS logic signal which are not available from any standard logic source a special CAMAC module was developed to generate the required test signal The highest fold of coincidence is 5 on Ifold signal from the first layer thus this test module generates 5 separate signals These five signals can be individually masked so as to facilitate the coincidence logic of the INO CTG module These five signals are in two groups of two and three signals Two free running signal sources are built in in the tset module with the width as well as overlap of these two signals groups settable using front panel pots This allows the testing of the minimum overlap required to generate final trigger The five signals can be individually connected to any of the 112 inputs using a specially made cable with 10 pin FRC connector on one end and five individual pairs on the other A block schematic of the test setup is as shown J1 J2 J3 J5 are 60 pin standard FRC connectors Step by step procedure for field testing of the module using CAMAC test module 1 Adjust the widths and overlaps of the output signals
14. arying delay before clearing LAM Now read the LAM width scaler With different values for the delay this should give appropriate value Test program for checking LAM width scaler Wait for LAM Delay time value N 0 10 reset LAM 122 Read data NAF N 132 Read data 9 Set different values for LTO FTO widths and check the output Observations The module has been tested for all its functionality as listed as below and is found to be working as required Minimum overlap to detect coincidence Propagation delay from input to output Feedback notes
15. d four fold signals each for 14 X and 14 Y layers Total 28 4 112 from Level 1 Signals Low Voltage Differential Signaling LVDS with 400mV differential signals Connectors 4x60 pin standard connectors with 0 1 pitch Output 28 signals on each connector Inputs to be connected on twisted pair flat cable LTO Logic trigger out fanout of 1 as NIM output FTO Final trigger out LTO amp not LAM fanout of 3 as NIM output LTO amp FTO width in multiples of 50 ns 1 to 7 clocks default 50 ns LAM CAMAC Look At Me generated with FTO Multiplicity Register All 112 inputs latched on FTO to be read on CAMAC Scalers Eight scalers on intermediate triggers one on LAM width CAMAC TRIGGER GENERATOR for INO INO CTG User manual This module has been implemented as a two width CAMAC module and most of the logic has been implemented in Altera 10K50 field programmable gate array device Low Voltage Differential Signaling LVDS has been used as input interface signal standard Output signals are generated as NIM logic level It has been designed to generate final trigger based on Predefined Coincidence Criterion on a large number of input signals from the prototype Neutrino detector Additionally it has SCALARS for the FINAL TRIGGER and for a number of intermediate coincidence logic signals The SCALARS can be read on CAMAC The valid signals are latched with final trigger and can also be read on CAMAC Inputs can be i
16. ers F 17 A 0 13 set reset input mask 1 set 0 reset F 17 A 14 set reset mask register for intermediate coincidence 1 set 0 reset F 17 A 15 set LTO FTO width F 24 A 0 set LAM mask disable LAM F 26 A 0 reset LAM mask enable LAM Recommended sequence of commands After POWER ON or any other time to reinitialize the module Initialize Z Set input mask registers Enable LAM After receiving LAM Read multiplicity registers Clear multiplicity registers Clear LAM To estimate the system dead time read LAM width scaler Clear LAM width scaler To estimate the input event rate Read trigger scalers Clear trigger scalers Sample programs for the CAMAC spy program 1 Enable all inputs reset masks for details of bit map see user manual Write data 255 NAF N017 Write data 255 NAF N117 Write data 255 NAF N217 Write data 255 NAF 317 write data 255 NAF N 417 Write data 255 NAF N 5 17 write data 255 NAF 6 17 Write data 255 NAFzN717 Write data 255 NAF N 817 Write data 255 NAF N 917 Write data 255 NAF N 10 17 Write data 255 NAF N 11 17 Write data 255 NAF N 12 17 Write data 255 NAF N 13 17 Write data 255 NAF N 14 17 Write data 255 2 Disable all inputs reset masks for details of bit map see user manual Write data 0 NAF N 0 17 Write data 0 1170 Write data 0 NAF N 2170 Write data 0 NA
17. ndividually deselected from taking part in the trigger generation The individual blocks of the module are described in details Trigger Logic The primary functionality of the module is to generate a trigger based on pre defined trigger pattern on 112 inputs It can be described with the help of a block diagram as follows One fold Inp AX One fold Inputs 14Y Scaler TO Two Fold Coincedence Logic Block Two Fold Inputs 14X SCALAH F2X Two Fold Inputs 14 Y SCALAR TO F2Y Three Fold Coincedence Logic Block Three Fold 4 X SCALAH TO F3X Three Fold 4 Y SCALAR TO F3Y Four Fold Coincedence Logic Block Four Fold Inputs 14 X SCALAR TO Four Fold Inputs 14 Y SCALAR TO F4Y Trigger Logic in Boolean equations TO FIX FILX1 amp FILX2 amp FILX3 amp FILX4 amp FILX5 FILX2 amp FILX3 amp FILX4 amp FILX5 amp FILX6 FILX3 amp amp FILX5 amp FILX6 amp FILX7 FILXIO amp FILXII amp FILXI2 amp FILX13 amp FILXIA TO_FLY FILY1 amp FILY2 amp FILY3 amp FILY4 amp FILYS FILY2 amp FILY3 amp FILY4 amp FILYS amp FILY6 FILY3 amp FILY4 amp FILYS amp FILY6 amp FILY7 FILY5 amp FILY11 amp FILY12 amp FILYI3 amp FILY14 TO_F2X F2LX1 amp F2LX2 amp F2LX3 amp F2LX4 F2Y TO TO F4Y F2LX2 amp F2LX3 amp F2LX4 amp F2LX5 F2LX3 amp F2LX4 amp F2LX5 amp
18. of the test module as per required test stimulus 2 Connect the five outputs to the required inputs of the INO module 3 Enable the test module by enabling and unmasking its five output 4 Run test programs to test various features of the INO CTG module as detailed in the application note 5 Checking multiplicity logic a To test two fold coincidence first connect only one input to one of the four fold input and check that no coincidence is generated b With this connection itself mask off the neighboring input so that this will now form a coincidence condition Check if trigger is generated LTO FTO and LAM should be generated Also the multiplicity registers read should be correct c In similar way check the two fold for other four fold inputs d Following similar steps check three four and five fold coincidences 6 In all of the above tests check if LAM enable disable and reset works correctly When LAM is set on trigger and is disabled it will be removed from the CAMAC bus But will be reasserted when it is enabled Whereas resetting LAM will clear the LAM request register and enabling or disabling it will have no effect on the LAM on CAMAC bus 7 In all of the above tests check if the respective scalers are read correctly 8 Also check the LAM width scaler It indicates the system dead time To test this feature connect inputs so that trigger will happen Enable the respective inputs Wait for LAM then put a v
19. put is always treated as 0 On POWER 7 all masks are set but no trigger will be generated All intermediate triggers should be unmasked Masking any one will not block the trigger logic Pulse width on front panel LTO and FTO amp A 15 amp 7 W 4 1 Width in term of multiples of clock 50ns specified by W in range 1 to 7 Default value is 6 The leading edge of the LTO and FTO signals starts with the leading edge of coincidence overlap after the propagation delay involved in the trigger logic and the width will vary from set to one additional clock jitter CAMAC OUTPUT Multiplicity logic the inputs to be latched with LTO Will be cleared with multiplicity register clear CLEAR N amp A 1 F 10 The input pattern can be read as follows Read Command amp 0 amp F 0 with data bits as shown Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 FILY2 FILY1 FILX14 FILX13 FILX12 FILX11 FILX10 FILX9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FILX8 FILX7 FILX6 FILX5 FILX4 FILX3 FILX2 FILX1 Read Command amp A 1 amp 0 with data bits as shown Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 F2LX4 F2LX3 F2LX2 F2LX1 FILY14 FILYI3 FILY12 FILY11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FILY10 FILY9 FILY8 FILY7 FILY6 FILYS FILY4 FILY3 Read Command amp A 2 amp 0 with data bits as shown
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