MSC8144 PCI Example Software
Contents
1. P11 COP USBTap EE COP CodeWarrior for PowerQUICC Figure 3 Hardware Setup 3 2 Switch Settings Table 1 shows the switch settings required to connect the MSC8144 and the MPC8560 to the debugger tools Refer to the MSC8144 ADS User s Manual for details about the switch settings Table 1 MSC8144ADS Switch Settings Switch Settings 1 8 Description Swi 00000110 Default setting SW2 01101111 Host MPC8560 operates normally disable JTAG chain for MSC8144 and MPC8560 SW3 10010111 Default setting SW4 01100010 Default setting Note 0 ON 1 OFF 3 3 Board Control and Status Register Setting The board control and status registers BCSRx are a group of 8 bit read write registers that control or monitor most ADS hardware options These registers can be accessed from the host local bus To enable the PCI interface on the MSC8144ADS bits 2 and 3 of BCSRI must by set as shown in Example 1 For details on the BCSRx bit definitions refer to the MSC8 44ADS User s Manual Example 1 Enable PCI in BCSR1 void setBCSR1 uint8 t bcsrl uint8 t 0xF8000001 bcsrl 0x30 4 PCI Device Detection Example Before the PCI host can configure each device on the bus it must first scan the bus to determine what PCI devices or PCI PCI bridges are on the bus By scanning the bus the host can determine each device part number manufacturer and device number on the bus2. Select device number 21 Access the GPL Base Address Register 0 offset 0x14 CONFIG DATA 0xC0000000 Write Reassign new GPLBARO 0xC0000000 MSC8144 PCI Example Software Rev 0 8 Freescale Semiconductor MSC8144 Inbound Configuration Example In this example the host assigns a chunk of memory in the PCI memory space to map the MSC8144 inbound window in M2 The host configures the MSC8144 GPLBARO 0xC0000000 to give a one to one mapping between the PCI view and MSC8144 local view as shown in Figure 6 MIU PCI View MSC8144 GPLBARO 512 KB 0xC0000000 512 KB 0xC0000000 Figure 6 Example MSC8144 GPLBARO Configuration Example 3 shows the function called by the MPC8560 to calculate the size of a device inbound window Example 3 Determine Memory Requirement uint32 t getWindowSize uint32 BusNum uint32 t DevNum uint32 t Reg 6 uint32_t new orig uint32_t size Read CfgReg orig getPCIConfigReg32 BusNum DevNum Reg Write all 1 s set PCIConfigReg32 BusNum DevNum Reg OxFFFFFFFF Read back to determine size new getPCIConfigReg32 BusNum DevNum Reg Restore orig register value setPCIConfigReg32 BusNum DevNum Reg orig Calculate size required by agent if new amp 1 size new 3 1 1 0 space else size new 1 Memory space return size MSC8144 Inbound Co
3. MPC8560 to scan the PCI bus for devices This code has been simplified to scan only bus number 0 Example 2 Scan PCI Devices void scanDevices uint32 t i uinti6 t VendorID DeviceID uint32 t BusNum 0 for i 0 i lt 0x20 1 VendorID getPCIConfigReg16 BusNum i REG VENDORID DeviceID getPCIConfigRegi6 BusNum i REG DEVID if VendorID OxFFFF printf Device found Device x Bus x DevID x VendorID x n i BusNum DeviceID VendorID 5 Memory Allocation Example A transaction with the MSC8144 as the target is an inbound transaction When the MSC8144 boots from PCI the boot code sets up the three inbound windows for M2 M3 and DDR memory as shown in Figure 5 The MSC8144 PCI boot code configures the base addresses in local memory and the sizes of these inbound windows The PCI inbound translation address register PITARn defines base address of the inbound translation windows in the MSC8144 memory space The PCI inbound window attribute register PIWARn defines the size of a window as well as other properties and enables that window It is the host that allocates memory to each device on the PCI bus in a device independent manner The host allocates memory by creating a memory map in the PCI memory space It writes to each device GPL base address register GPLBARx in the PCI configuration space to create a mapping between the PCI view and the device local memory view MSC81
4. PIMMR to 0x30000000 through the CONFIG_ADDR and CONFIG_DATA configuration access registers The host also configures another outbound window at 0x90000000 so that transactions from this space are mapped to the PCI space at 0x30000000 Figure 9 shows a diagram of the CCSR address space mapping and Table 5 shows how the MPC8560 configures the MSC8144 PIMMR base address MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 11 MSC8144 CCSR Mapping Example MPC8560 PCI View MSC8144 POTAR PIMMR 0x30000000 0x30000000 POBAR 0x90000000 0xFE000000 Host MPC8560 Side Agent MSC8144 Side I Figure 9 MSC8144 CCSR Address Space Mapping Table 5 MPC8560 Outbound Window for MSC8144 CCSR Mapping Access e Register Value Type Description CONFIG ADDR 0x8000A810 Write Allow a PCI configuration access when CONFIG_DATA is accessed Select bus number 0 Select device number 21 Access the PIMMR Base Address Register offset Ox10 CONFIG DATA 0x30000000 Write PIMMR 0x30000000 CCSR mapping in PCI space For example if the MPC8560 needs to read MSC8144 PCI error status register PCI ESR then the MPC8560 accesses the outbound window that maps to the MSC8144 CCSR space The PCI ESR is at OxFFF7A000 in the MSC8144 local space With a base address of 0xFE000000 the PCI ESR has an offset of 0x01F7A000 from the CCSR base To access this register t
5. The PCI specification requires each PCI device to provide 256 bytes of configuration registers The configuration registers supply the information needed for device configuration including the vendor ID device ID command and status revision ID class code and header type fields as shown in Figure 4 MSC8144 PCI Example Software Rev 0 4 Freescale Semiconductor PCI Device Detection Example Address Offset Device ID Vendor ID 0x00 PCI Status PCI Command Config 0x04 Base Class Subclass Std Prog T Code Code Interface 0 08 BIST Header Latency Cache Line Control Type Timer Size 0x0C PIMMR Base Address Register 0x10 GPL Base Address Register 0 0x14 GPL Base Address Register 1 0x18 GPL Extended Base Address Register 1 oxic GPL Base Address Register 2 0x20 GPL Extended Base Address Register 2 0x24 Reserved 0x28 Subsystem Subsystem Device ID Vendor ID 0x2C Reserved 0x30 Reserved Capabilities Pointer 0x34 Reserved 0x38 PCI Bus PCI Bus PCI Bus PCI Bus Ox3C MAX LAT GNT Interr Pin Interr Line x Reserved 0x40 Reserved PCI Function 0x44 Configuration Figure 4 MSC8144 PCI Configuration Space Registers On the MSC8144ADS the MPC8560 host can access the MSC8144 configuration space registers through two registers that are memory mapped in the MPC8560 memory space e CONFIG ADDR Specifies the selected device configuration re
6. error volatile uint32 t pci eacr PCI error volatile uint32 t pci eeacr PCI error volatile uint32 t pci edcr PCI error volatile uint8 t reserved1 0x038 0x01C PCI Inbound Registers pci inbound window t inbound2 pci inbound window t inbound1 pci inbound window t inbound0 volatile uint8 t reserved2 0x100 0x080 PCI Outbound Registers pci outbound window t outbound 6 volatile uint8 t reserved3 0x1F8 0x190 PCI Control Registers volatile uint32 t dtcr volatile uint8 t reserved4 0x200 msc8144 pci regs Ox1FC Discard Timer Control Register MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 25 MPC8560 Header File THIS PAGE INTENTIONALLY LEFT BLANK MSC8144 PCI Example Software Rev 0 26 Freescale Semiconductor MPC8560 Header File THIS PAGE INTENTIONALLY LEFT BLANK MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 27 How to Reach Us Home Page www freescale com Web Support http www freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 8
7. local outbound window This address is translated to the PCI address that is mapped to the MSC8144 local inbound window The right screenshot shows the MSC8144 reading the same value from its local inbound window 1 MPC8560 writes data to outbound window outbound uint32 t CEP OCE outbound uint32 t00x11223344 inbound uint32 t InboundLocal data inbound 2 MSC8144 reads data from inbound window LOSE Location 0 00006014 Figure 8 MSC8144 Inbound Example 7 MSC8144CCSR Mapping Example Before we look at an example MSC8144 outbound transaction let us first consider how to configure the host MPC8560 to view MSC8144 configuration control and status registers CCSR map The address space includes control and status registers for DMA CLASS DDR clock timers GPIO PCI RapidIO and so on External masters do not need the location of a device s CCSR memory space Instead they access a device s CCSR through a window defined by the PIMMR base address configuration register in the configuration register space as shown in Figure 4 The PIMMR defines the address for accessing the local CCSR memory space of a device It specifies an address in the PCI space where the CCSR space 15 mapped The CCSR memory space is 32 Mbytes Subtracting 32 Mbytes from the top of the MSC8144 address space gives the CCSR base address of 0xFE000000 In this example the host configures
8. lt lt 11 FuncNum OxFF lt lt 8 RegNum amp OxFC ENABLE yrs return value void writePCIConfigReg uint32 t BusNum uint32 t DevNum uint32 t Reg uint32 t Data uint32 t cfg addr uint32 t data32 data32 SwapLong Data if Reg amp 0x3 1 data32 data32 gt gt 8 MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 17 dr mI o __ I 00 MPC8560 Host Configuration Code else if Reg amp 0x3 2 data32 data32 gt gt 16 else if Reg amp 0x3 3 data32 data32 gt gt 24 cfg ConstructConfigWord BusNum DevNum Reg WRITE UINT32 mpc8560 config addr cfg WRITE UINT32 mpc8560 gt config data data32 void setPCIConfigReg32 uint32 t BusNum uint32 t DevNum uint32 t Reg uint32 t Data void setPCIConfigReg16 uint32_t BusNum uint32 t DevNum uint32 t Reg uint16 t Data void setPCIConfigReg8 uint32 t BusNum uint32 t DevNum uint32 Reg uint8 t Data uint32 t readPCIConfigReg uint32 t BusNum uint32 t DevNum uint32 t Reg writePCIConfigReg BusNum DevNum Reg Data writePCIConfigReg BusNum DevNum Reg Data writePCIConfigReg BusNum DevNum Reg Data uint32 t cfg uint32 t cfg data cfg addr ConstructConfigWord BusNum DevNum Reg WRITE UINT32 mpc8560 config addr cfg READ UINT32 cfg data mpc8560 config data cfg data SwapL
9. space as shown in Figure 4 The BMST bit must be set so that the MSC8144 behaves as a bus master In Figure 11 the MSC8144 performs an outbound transaction The bottom screenshot shows the MSC8144 writing the value OXDEADBEEF to its local outbound window This address is translated to the PCI address that is mapped to the MPC8560 local inbound window The top screenshot shows the MPC8560 reading the same value from its local inbound window 2 MPC8560 reads data from inbound window Li ox Location ml FOXDEADBEEF EADBEEF OxO06FFFC4 inbound uint32 t InboundLocal data inbound r outbound N Location 3 outbound OxE 0000000 0 0000 00 outbound OxDEADBEEF OxE 0000000 1 MSC8144 writes data to outbound window Figure 11 MSC8144 Outbound Example 9 Cache Line Size The MSC8144 PCI controller has an internal cache line of 32 bytes Although the cache line size register in the configuration space is writable only the value 8 is valid This value indicates a cache line of 8 doublewords or 32 bytes When the MSC8 144 acts as a target the bus command PCI MEMORY READ fetches cache line of data 32 bytes of data are fetched regardless of the size requested by the initiator In the MSC8 144 there is no difference between PCI MEMORY READ and PCI MEMORY READ LINE commands because the entire cache line is fetched in both cases The PCI MEMORY READ MULTIPLE command is also simila
10. tint ack volatile uint8 treserved OxBF4 volatile uint32 tpotar0 volatile uint32 tpotear0 volatile uint32 tpowbar0 MSC8144 PCI Example Software Rev 0 MPC8560 Header File Freescale Semiconductor 23 MPC8560 Header File volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile uint8_treservedo 0 4 uint32_tpowaro uint8_treservedI 0xC uint32 tpotarl uint32 tpotearl uint32 tpowbarl uint8 treserved2 0x4 uint32 tpowarl uint8 treserved3 0xC uint32 tpotar2 uint32 tpotear2 uint32 tpowbar2 uint8 treserved4 0x4 uint32 tpowar2 uint8_treserved5 0xC uint32_tpotar3 uint32_tpotear3 uint32 tpowbar3 uint8 treserved6 0x4 uint32 tpowar3 uint8 treserved7 0xC uint32 tpotar4 uint32 tpotear4 uint32 tpowbar4 uint8 treserved8 0 4 uint32 tpowar4 uint8 treserved9 0x10C uint32 tpitar3 uint8 treservedlO 0x4 uint32 tpiwbar3 uint32 tpiwbear3 uint32 tpiwar3 uint8 treservedll 0xC uint32 tpitar2 uint8 treserved12 0x4 uint32 tpiwbar2 uint32 tpiwbear2 uint32
11. 4 PITAR 0 00000000 POTAR POBAR 0xE0000000 0xE0000000 a Host MPC8560 Side Ageni MSC8144 Side Figure 10 MSC8144 Outbound MPC8560 Inbound Address Mapping Table 6 MSC8144 PCI Outbound Registers Settings MSC8144 Address as Visible Address as Visible iL gi Register to MSC8144 to MPC8560 value Description POTARO OxFFF7A100 0x91F7A100 0x000E0000 Set base address 0xE0000000 as the translated address in the PCI memory space POBARO OxFFF7A108 0x91F7A108 0x000E0000 Set base address 0xE0000000 as the outbound window 0 in the MSC8144 local memory space POCMRO OxFFF7A110 0x91F7A110 OxA00F8000 Enable the inbound translation window 0 Map window 0 to PCI memory space Enable streaming Set translation window 0 size as 128 MB Table 7 MPC8560 PCI Inbound Registers Settings Register Value Description PITAR1 0x00000000 Set base address 0x00000000 as the translated address in the local MPC8560 memory space PIWBAR1 0x000E0000 Set base address 0xE0000000 as the address in the PCI memory space PIWAR1 OxAOF5501B Enable the inbound translation window 1 Inbound window 1 is prefetchable Target interface is local memory Enable read and write with snooping Set translation window 1 size as 256 MB MSC8144 PCI Example Software Rev 0 14 Freescale Semiconductor Cache Line Size Before the MSC8144 can initiate PCI accesses the MPC8560 must configure the MSC8144 PCI bus command register which has an offset of 0x04 in the PCI configuration
12. 44 SED 0x40000000 098 Inbound Window 2 0xC0000000 M2 512 KB Inbound Window 0 Ma 0xD0000000 16 MB Inbound Window 1 Figure 5 MSC8144 Inbound Window Configuration at Boot MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 7 Memory Allocation Example To determine the size requirements of the MSC8144 inbound windows MPC8560 writes to the MSC8144 GPLBARx in the PCI configuration space as shown in Figure 4 These base address registers specify the mapping of the device inbound windows in the PCI space The host first reads these base address registers to get the initial setting It then writes all 1 to these base address registers and reads them back to determine the memory size required by the inbound window Then the host can allocate memory for each device in the PCI space Table 3 shows the steps by which the MPC8560 determines the MSC8144 inbound window 0 memory requirement The MPC8560 addresses the MSC8144 GLBARO register by writing to the CONFIG ADDR register Then it reads the CONFIG DATA to get the value of GPLBARO which defines the inbound window 0 base address register in the PCI memory space The host must save this value to restore later Next the host writes OXFFFFFFFF to the MSC8144 GPLBARO and reads back the register The number of bits set determines how much address space is required For example a GPLBARO value of OxFFF80000 has the upper 13 bits of the address register set indicatin
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14. Example Software Rev 0 22 Freescale Semiconductor define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define typedef REG REVID REG BUSPROGIF REG SUBCLASS REG BASECLASS REG CACHELINESZ REG BUSLATENCY REG HDRTYPE REG BISTCTL REG PIMMRBACR REG GPLBARO REG GPLBARI1 REG GPLEXTBARI1 REG GPLBAR2 REG GPLEXTBAR2 REG SUBSYSID REG CAPABILITYPTR REG INTERRLINE REG INTERRPIN REG MINGNT REG MAXLAT REG FUNCTION REG ARBITER IZE 4KB IZE 8KB IZE 16KB IZE 32KB IZE 64KB IZE 128KB IZE 256KB IZE 512KB IZE 1MB IZE 2MB IZE 4 IZE 8MB IZE 16MB IZE 32MB IZE 64MB IZE 128MB IZE 256MB IZE 512MB IZE 1GB IZE 2GB IZE 4GB ANNNNNNNNNNNNANNHNNNNHnNHNNMN struct REG SUBSYSVENDORID Ox0C OxOD OxOE OxOF Ox10 Ox11 0x12 0x13 0 14 0 15 0 16 0 17 0x18 0x19 1 Ox1B Ox1C 0 1 Ox1E Ox1F 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0 0010 0 0014 0 0018 0x001C 0x0020 0x0024 0x002C 0x002E 0x0034 0x003C 0x003D 0x003E 0x003F 0x0044 0x0046 volatile uint32 tconfig addr volatile uint32 tconfig data volatile uint32
15. Freescale Semiconductor Application Note Document Number AN3098 Rev 0 11 2006 MSC8144 PCI Example Software by Barbara Johnson NCSD DSP Applications Freescale Semiconductor Inc Austin In a PCI system auto configuration software offers ease of use for the system user by automatically configuring PCI add in cards at power on This application note provides example software for use by a PCI host to configure the MSC8144 DSP as a PCI agent This device configuration is required before any PCI transactions can occur between the host and the MSC8144 1 PCI Basics Peripheral component interconnect PCI is a standard that provides an interconnect mechanism between peripheral components add on devices and memory subsystems Developed by Intel PCI is widely used in modern PC s to provide a way of adding peripherals such as video cards sound cards and network adapters on the same bus that is used to communicate with the CPU Figure 1 shows an example PCI based system The CPU connects to the primary PCI bus on a PCI host bridge that translates between CPU bus cycles and PCI bus cycles The PCI PCI bridge connects the primary PCI bus to the secondary PCI bus Electrical loading issues limit the number of devices that a single PCI bus can support so PCI PCI bridges are often used to allow the system to support more PCI devices To support older legacy devices some PCs use a PCI ISA bridge for connecting to the PCI bus
16. Freescale Semiconductor Inc 2006 All rights reserved WIN 3 A 11 12 13 Contents PCI scd debes yg ed aoa Ee i la s 1 MSC8144 PCI Controller 3 Hardware Requirements and Setup 3 3 1 Requirements siii 3 3 2 Switch Settings IIIA 4 3 3 Board Control and Status Register Setting 4 PCI Device Detection Example 4 Memory Allocation Example 7 MSC8144 Inbound Configuration Example 9 MSC8144 CCSR Mapping Example 11 MSC8144 Outbound Configuration Example 13 Cache Line Size i46 be ao ein at a d ei aa 15 Latency Timer v viat we ec e re s 15 Interrupt Handling 16 MPC8560 Host Configuration Code 16 MPC8560 Header File 22 2 2 freescale semiconductor PCI Basics CPU Memory PCI Host Bridge PCI Bus 0 PCI ISA Network PCI PCI Bridge Adapter Bridge Video ISA Bus PCI Bus 1 Controller SCSI Figure 1 Example PCI System In Figure 1 the CPU operates as the PCI host In the host mode the CPU configures the PCI devices attached to the bus Because PCI uses a shared bus topology there must be an arbitration scheme to grant bus mastership to the requesting PCI device Arbitration is handled by th
17. I SetBCSR1 Scan devices on the bus MSC8144 PCI Example Software Rev 0 20 Freescale Semiconductor MPC8560 Host Configuration Code scanDevices Set 8560 as the arbiter setPCIConfigReg16 BusNum MPC8560 PCIDEVICENUM REG ARBITER 0 Set latency timer to max clock cycles to generate stop setPCIConfigReg8 BusNum MPC8560 PCIDEVICENUM REG BUSLATENCY OxF8 kkkkkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 8560 Outbound 8144 Inbound 8560 0x8000 0000 gt PCI 0 8000 0000 gt 8144 000 0000 Size 512KB fi kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkk kkkk Determine window sizes for 8144 GPLX 0 0010 0000 size getWindowSize BusNum MSC8144 PCIDEVICENUM REG GPLBARO M2 Reassign 8144 inbound window 0 start addr in PCI memory space setPCIConfigReg32 BusNum MSC8144 PCIDEVICENUM REG GPLBARO OutboundPCI Read 8144 PCI base inbound window 0x2000 0008 prefetchable windowstart getPCIConfigReg32 BusNum MSC8144 PCIDEVICENUM REG GPLBARO Set outbound window local address 0x80000000 PCI address 0x20000000 512KB size setOutbound1 OutboundLocal OutboundPCI calcWindowSize size fi kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 8144 Outbound 8560 Inbound 8144 OxEOO0 0000 gt PCI 0xE000_0000 gt 8560 0 0000 0000 Size 256MB kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkk
18. byte buffers to allow PCI to memory and memory to PCI streaming Memory prefetching of PCI read accesses and support for delayed read transactions Posting of processor to PCI and PCI to memory writes e Inbound and outbound address translation units for address mapping between PCI and local busses e Supports parity e PCI 3 3 V compatible 3 Hardware Requirements and Setup tests described in this document were performed on the MSC8144 application development system MSC8144ADS which consists of an MPC8560 host processor that connects to the MSC8144 on the PCI bus 3 1 Requirements The following items are required to run the examples presented in this document e MSC8144ADS board e PC with CodeWarrior for StarCore version 3 2 or later PC with CodeWarrior for PowerPC version 8 7 or later e USBTap for MSC8144 OCE connection e USBTap for MPC8560 COP connection Two sets of debugger tools are required to connect to the MSC8144 and the MPC8560 A USBTap for OCE connects the MSC8144 to the CodeWarrior for StarCore tools through JTAG Similarly a USBTap for COP connects the MPC8560 to the CodeWarrior for PowerQUICC tools through JTAG Figure 3 shows the hardware setup MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 3 PCI Device Detection Example MSC8144ADS py USBTap PC with E MPC8560 291 44 EE OCE CW for StarCore
19. e Semiconductor MPC8560 Host Configuration Code uint32_t InboundPCI 0xE0000000 uint32_t PCI8144BASE 0x01F7A000 msc8144 pci regs msc8144 mpc8560 pci regs mpc8560 mpc8560 pci regs 0x40008000 void setBCSR1 uint32 t SwapLong uint32 t uint32 t ConstructConfigWord uint32 t uint32 t uint32 t void setPIMMR uint32 t void scanDevices uint32 t getWindowSize uint32 t uint32 t uint32 t void setOutbound1 uint32 t uint32 t uint32 t void setOutbound2 uint32 t uint32 t uint32 t uint32 t calcWindowSize uint32 t void writePCIConfigReg uint32 t uint32 t uint32 t uint32 t void setPCIConfigReg32 uint32 t uint32 t uint32 t uint32 t void setPCIConfigReg16 uint32 t uint32 t uint32 t uintl6 t void setPCIConfigReg8 uint32 t uint32 t uint32 t uint8 t uint32 t readPCIConfigReg uint32 t uint32 t uint32 t uint32 t getPCIConfigReg32 uint32 t uint32 t uint32 t uintl6 t getPCIConfigRegl6 uint32 t uint32 t uint32 t uint8 t getPCIConfigReg8 uint32 t uint32 t uint32 t uint32 t SwapLong uint32 t value value value lt lt 24 value amp lt lt 8 value amp OxFFOOOOUL gt gt 8 value 0xFF000000UL gt gt 24 return value uint32_t ConstructConfigWord uint32 t BusNum uint32_t DevNum uint32_t RegNum uint32_t value uint32 t FuncNum 0x0 value BusNum OxFF lt lt 16 DevNum OxFF
20. e host or an external arbiter From the host perspective the PCI devices are accessible through a read write mechanism An address space dedicated for PCI use contains a memory range for each PCI device on the bus The host accesses the PCI devices by performing reads or writes to specific addresses in the PCI memory space as shown in Figure 2 Host View Device x PCI memory Device y Program Main memory Figure 2 Example Host View Devices on the PCI bus must be configured before they can be used For example when a PC first boots up each PCI device is assigned a region of PCI address space so that it becomes accessible to the CPU After the devices are initialized they respond to transactions that fall within their allocated memory ranges MSC8144 PCI Example Software Rev 0 2 Freescale Semiconductor MSC8144 PCI Controller 2 MSC8144 PCI Controller The MSC8144 PCI controller complies with the PCI Local Bus Specification Revision 2 2 It operates in agent mode and can act as initiator master or target slave device It uses a 32 bit multiplexed address data bus that operates at frequencies up to 66 MHz Features of the PCI controller are as follows e 32 bit PCI interface Up to 66 MHz operation Agent mode e Accesses to all PCI address spaces e 64 bit dual address cycles as a target only e Internal configuration registers accessible from PCI and internal buses e Contains L2 ICache line 32
21. g a size of 202 19 512 Kbytes Now the host knows that it must allocate 512 Kbytes of memory in the PCI memory space before it can access the MSC8144 inbound window 0 The host must then assign an address in the PCI space because the GPLBARO now contains the sizing information These steps should be repeated for GPLBARI and GPLBAR 2 registers to determine the memory requirements for inbound windows 1 and 2 Table 3 Memory Allocation by MPC8560 Access Register Value ACCESS Description Type 1 CONFIG_ADDR 0 8000 814 Write Allow a PCI configuration access when CONFIG_DATA is accessed Select bus number 0 Select device number 21 Access the GPL Base Address Register 0 offset 0x14 CONFIG_DATA 0x00000000 Read GPLBARO 0x00000000 inbound window 0 in PCI space 2 CONFIG_ADDR 0x8000A814 Write Allow a PCI configuration access when CONFIG_DATA is accessed Select bus number 0 Select device number 21 Access the GPL Base Address Register 0 offset 0x14 CONFIG DATA OxFFFFFFFF Write GPLBARO 0xFFFFFFFF 3 CONFIG ADDR 0x8000A814 Write Allow a PCI configuration access when CONFIG DATA is accessed Select bus number 0 Select device number 21 Access the GPL Base Address Register 0 offset 0x14 CONFIG DATA OxFFF80000 Read GPLBARO OxFFF80000 Upper 13 bits are set Size 2 82 19 512 4 CONFIG ADDR 0x8000A814 Write Allow a PCI configuration access when CONFIG DATA is accessed Select bus number 0
22. gister to be accessed e CONFIG DATA Data is transferred to or from CONFIG_DATA register For example the host addresses a particular device on the bus by writing to the CONFIG_ADDR with the bus number device number and the configuration register to access Next the host either writes the CONFIG_DATA with the value to write to the selected configuration register or the host reads the CONFIG_DATA to determine the value of the selected configuration register Note that in the MPC8560 the CONFIG_ADDR register uses big endian but the CONFIG_DATA register uses the little endian convention MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 5 PCI Device Detection Example To scan the bus the host will try to read the Vendor and Device ID Configuration Registers for all valid device number values A target is selected during a configuration access when its IDSEL signal is selected The IDSEL signal acts as the chip select signal On the MSC8144ADS the MPC8560 s AD21 pin connects to the MSC8144 s IDSEL pin This connection means that the MSC8 144 has a device number of 21 on bus 0 The MPC8560 has a device number of on bus 0 Selecting a device number other than 0 and 21 will return an invalid value since only MPC8560 and MSC8144 are present on the PCI bus on the MSC8144ADS If the device does not exist the Vendor ID returns a OKFFFF which indicates an invalid vendor Table 2 shows the CONFIG_ADDR and CONFIG DATA regis
23. he MPC8560 needs to read the following address Eqn 1 PCI ESR 0x90000000 0xFFF7A000 0xFE000000 0x91F7A000 As you can see the PIMMR allows an external master to access a device s internal memory mapped registers without knowing where the CCSR resides This is especially useful because the CCSR base address is programmable so that the PCI host can read and write the MSC8144 memory mapped registers MSC8144 PCI Example Software Rev 0 12 Freescale Semiconductor MSC8144 Outbound Configuration Example 8 MSC8144 Outbound Configuration Example In Section 5 Memory Allocation Example we noted that the MSC8144 configures three inbound windows for M2 M3 and DDR at bootup The boot code does not configure the outbound windows so the host must configure them Knowing how the MPC8560 can access the MSC8144 memory mapped registers we allow the MPC8560 to set up the MSC8144 outbound window using the PIMMR The MSC8144 defines an outbound memory window in the address range 0xE0000000 0xE7FFFFFF Both the configuration access registers CONFIG_ADDR and CONFIG DATA fall within this 128 Mbyte window If the address is not 7 CONFIG ADDR 0xE7FFFFF4 CONFIG DATA then the transaction is forwarded to the PCI port When the MSC8 144 initiates a transaction the PCI outbound base address register POBAR7 defines the location of the outbound translation in MSC8144 memory space The POTARn defines the starting p
24. he general purpose interrupt request lines IRQ0 15 and INT_OUT be used to route interrupt sources 12 MPC8560 Host Configuration Code Switch settings SW1 00000110 PCI boot SW2 01101111 Disable JTAG chain SW3 10010111 PCI 256M DDR SW4 01100010 include lt stdio h gt include mpc8560pci h Check which ADx pin is connected to IDSEL define MSC8144 PCIDEVICENUM21 define MPC8560 PCIDEVICENUMO PCI device id for MSC8144 define MSC8144 PCIDEVIDOx1400 define MPC8560_PCIDEVIDOx0009 define MPC8560 PCIVENDORIDOx1057 define MSC8144 PCIVENDORIDOx1957 define READ UINT8 data data uint8 t arg define READ UINT16 data data uinti6 t arg define READ UINT32 data data uint32 t arg define GET UINTS arg uint8 t arg define GET UINT16 arg uinti6 t arg define GET UINT32 uint32 t arg define WRITE UINT8 data arg uint8 t data define WRITE UINT16 arg data arg uinti6 t data define WRITE UINT32 arg data arg uint32 t data uint32 t IMMR8144Local 0x90000000 uint32 t OutboundLocal 0x80000000 uint32 t InboundLocal 0x00000000 uint32 t IMMR8144PCI 0x30000000 uint32 t OutboundPCI 0xC0000000 MSC8144 PCI Example Software Rev 0 16 Freescal
25. ine size new getPCIConfigReg32 BusNum DevNum Reg Restore orig register value setPCIConfigReg32 BusNum DevNum Reg orig Calculate size required by agent if new amp 1 size new 3 1 I O space else size new OxF 1 Memory space return size MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 19 MPC8560 Host Configuration Code void setOutbound2 uint32_t LocalAddr uint32_t PCIAddr uint32 t WindowSize PCI address mpc8560 potar2 PCIAddr gt gt 12 Local Addr mpc8560 gt powbar2 LocalAddr gt gt 12 Enable memory read write window size mpc8560 gt powar2 0x80044000 WindowSize void setOutbound1 uint32 t LocalAddr uint32 PCIAddr uint32 t WindowSize PCI address mpc8560 gt potarl PCIAddr gt gt 12 Local Addr mpc8560 gt powbarl LocalAddr gt gt 12 Enable memory read write window size mpc8560 gt powarl 0x80044000 WindowSize uint32 calcWindowSize uint32 t Size int i uint32 t WindowSize 0 for i 0 i 32 1 if Size amp 0x01 WindowSize i Size Size gt gt 1 WindowSize WindowSize 1 return WindowSize void main uint32_t BusNum 0 uint32 t outbound inbound uint32 t size uint32 t windowstart uintl6 t status 8144 uint32 t data Set BCSR1 RGMII1EN and RGMII2EN 1 Disable to select PCI UTP instead of RGMI
26. k Set inbound window local address 0x00000000 PCI address 0xE0000000 PCI address mpc8560 gt piwbar1 InboundPCI gt gt 12 Local mpc8560 pitarl InboundLocal gt gt 12 Enable prefetch target i f local mem r w snoop 256MB size mpc8560 gt piwarl OxAOF5501B kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkk kkkk 8144 PIMMR memory mapped space 8560 0x9000 0000 gt PCI 0x3000 0000 gt 8144 0000 IMMR Size 32MB ck ck ce ck ke ck ck ce ck ce cec ce ce ce ce ck ce cec ce ck ck ce ck ce cec ce ck ce ce ck KKK Determine window size and set start addr for 8144 PIMMR size getWindowSize BusNum MSC8144 PCIDEVICENUM REG_PIMMRBACR IMMR 32MB Reassign 8144 inbound window 1 start addr in PCI memory space setPCIConfigReg32 BusNum MSC8144 PCIDEVICENUM REG PIMMRBACR IMMR8144PCI windowstart getPCIConfigReg32 BusNum MSC8144 PCIDEVICENUM REG PIMMRBACR Set outbound window local address 0x00000000 PCI address 0x30000000 32MB size setOutbound2 IMMR8144Local IMMR8144PCI calcWindowSize size MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 21 MPC8560 Header File BMST 1 MEM 1 PERR SERR 1 setPCIConfigReg16 BusNum MPC8560 PCIDEVICENUM REG BUSCMD 0x0146 BMST 1 MEM 1 PERR SERR 1 setPCIConfigReg16 BusNum MSC8144 PCIDEVICENUM REG BUSCMD 0x0146 kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
27. kkkkkkkkkkkkkkkkkkkkk Now 8560 can access 8144 memory mapped registers to set up 8144 s outbound windows kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxkk PCI8144BASE PCI8144BASE IMMR8144Local msc8144 msc8144 pci regs PCI8144BASE MSC8144 outbound 0 enable prefetch streaming msc8144 gt outbound 0 potar InboundPCI gt gt 12 msc8144 gt outbound 0 pobar 0x000E0000 msc8144 gt outbound 0 pocmr 0xA00F8000 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Perform outbound transaction 8560 writes to 8144 memory Step through code here to write to memory Then in 8144 project step through code to read memory Pi kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk outbound uint32_t OutboundLocal outbound uint32_t 0x11223344 kkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkk Perform inbound transaction 8144 writes to 8560 memory In 8144 project step through code to write to memory Then step through code here to read memory kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk inbound uint32_t InboundLocal data inbound 13 MPC8560 Header File include os_datatypes h CONFIG ADDR bits define ENABLE 0x80000000 Configuration Access Registers define REG VENDORID 0x0000 define REG DEVID 0x0002 define REG BUSCMD 0x0004 define REG BUSSTATUS 0x0006 MSC8144 PCI
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29. nfiguration Example An inbound transaction in which the MSC8144 15 the target means that the host MPC8560 is the bus master or the initiator performing an outbound transaction Outbound transactions require address translation to map transactions from the internal address space of the MPC8560 to the external PCI address space MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 9 MSC8144 Inbound Configuration Example MPC8560 registers to handle the address translation task are as follows e PCI outbound translation address register selects base address of the external PCI address space for hits in the outbound window e PCI outbound window base address register POWBARn points to base address of the outbound window in MPC8560 local address space e PCI outbound window attributes register POWARn enables the address translation window specifies the transaction type and defines the window size Table 4 shows the outbound window 1 of size 512 Kbytes starting at 0x80000000 in the MPC8560 local address space for translation to the external PCI address starting at 0xC0000000 Table 4 MPC8560 PCI Outbound Register Settings Register Value Description POTAR1 0x000C0000 Set base address 0xC0000000 as the translated address in the PCI address space POWBARI 0x00080000 Set base address 0x80000000 as the outbound address from the MPC8560 POWAR1 0x80044012 Enable the outbound translati
30. oint of the outbound translation address in the destination PCI memory space The POCMRz defines the size of an outbound translation window defines properties and enables that window Mapping the MSC8144 outbound window to the PCI space with a one to one mapping means that both the POBARO and POTARO registers are set to map a window at OXE0000000 The MPC8560 writes to these registers through the PIMMR mapping in the PCI space The MSC8144 can access the POTARO locally at OXFFF7A100 Based on the settings for mapping the CCSR map the MPC8560 can access the MSC8144 POTARO from its local space at 0x91F7A100 Similarly it can access the MSC8144 POBARO and POCMRO registers from 0x91F7A108 and 0x91F7A110 respectively Eqn 2 0x90000000 0xFFF7A100 0xFE000000 0x91F7A100 Eqn 3 0x90000000 0xFFF7A108 0xFE000000 0x91F7A108 4 POCMRO 0 90000000 0xFFF7A110 0xFE000000 0x91F7A110 Suppose the MPC8560 receives inbound transactions at address 0x00000000 so that the mapping is as shown in Figure 10 The MPC8560 configures the MSC8144 outbound window register settings as shown in Table 6 Its inbound window register settings are shown in Table 7 MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 13 MSC8144 Outbound Configuration Example MPC8560 PCI View MSC814
31. on window 1 Enable memory read and write transactions Set translation window 1 size as 512 Kbytes Figure 7 depicts the MPC8560 outbound address translation mapping An access to the MPC8560 local address starting at 0x80000000 is routed to the PCI memory space starting at 0xC0000000 Notice that the PCI address is configured to be the same as the local address for a simple one to one mapping The left side of the dotted line gives register settings on the MPC8560 side and the right side of the dotted line gives register settings on the MSC8144 side Note that the MPC8560 POTAR must have the same value as the MSC8144 GPLBAR MPC8560 PCI View MSC8144 POBAR 0x80000000 CoN GPLBAR PITAR POTAR 2 0xC0000000 0xC0000000 gt 0xC0000000 Host MPC8560 Side Agent MSC8144 Side I Figure 7 MPC8560 Outbound MSC8144 Inbound Address Mapping MSC8144 PCI Example Software Rev 0 10 Freescale Semiconductor MSC8144 CCSR Mapping Example Before the MSC8144 DSP can respond to memory accesses the MPC8560 processor must configure the MSC8144 PCI command configuration register which has an offset of 0x04 in the PCI configuration space The MEM bit must be set to allow the MSC8144 to respond to memory accesses Figure 8 shows an example in which the MSC8144 performs an inbound transaction The left screenshot shows the MPC8560 writing the value 0x 11223344 to its
32. ong cfg data if Reg amp 0x3 1 cfg data cfg data 8 else if Reg amp 0x3 2 cfg data cfg data 16 else if Reg amp 0x3 3 cfg data cfg data 24 return cfg data uint32 t getPCIConfigReg32 uint32_t BusNum uint32 t DevNum uint32 t Reg uint16 t getPCIConfigReg16 uint32 t BusNum uint32 t DevNum uint32 t Reg return uint32 t readPCIConfigReg BusNum DevNum Reg return 1118516 t readPCIConfigReg BusNum DevNum Reg MSC8144 PCI Example Software Rev 0 18 Freescale Semiconductor D PP br MPC8560 Host Configuration Code uint8 t getPCIConfigReg8 uint32 t BusNum uint32 t DevNum uint32 t Reg return uint8 t readPCIConfigReg BusNum DevNum Reg void scanDevices uint32 t i uintl6 t VendorID DeviceID uint32 t BusNum 0 for i 0 i 0 100 1 VendorID getPCIConfigRegl6 BusNum i REG VENDORID DeviceID getPCIConfigReg16 BusNum i REG DEVID if VendorID OxFFFF printf Device found Device x Bus x DevID x VendorID sx n i BusNum DeviceID VendorID void setBCSRl1 uint8 t bcsrl uint8_t 0xF8000001 bcsrl 0x30 uint32 t getWindowSize uint32 t BusNum uint32 t DevNum uint32 t Reg uint32_t new orig uint32_t size Read CfgReg orig getPCIConfigReg32 BusNum DevNum Reg Write all 1 s setPCIConfigReg32 BusNum DevNum Reg OxFFFFFFFF Read back to determ
33. r but it supports prefetching This command causes a prefetch of the next cache line 10 Latency Timer The minimum grant MIN_GNT space register defines the minimum time in increments of 250 ns during which the master retains ownership of the bus for adequate performance This read only register is useful in determining the value to be programmed into the bus master latency timer LT configuration register Because the MSC8144 PCI controller is a bridge between PCI and local memory it does not have specific requirements for the LT when it operates as a bus master Therefore MIN_GNT is hard wired to zero MSC8144 PCI Example Software Rev 0 Freescale Semiconductor 15 Interrupt Handling Configuration software should configure LT according to system requirements The value 15 system dependent and this value should be tuned to maximize utilization without starving the other PCI bus masters For example leaving the LT at zero may require the master to rearbitrate for the bus for long data transfers but setting it to the maximum value may potentially keep other masters from accessing the bus 11 Interrupt Handling In many PCI devices the INTA INTB INTC and INTD pins signal interrupts to the PCI bus The interrupt pin configuration register in the configuration space at offset 0x3D indicates which of these four pins the device uses However the MSC8144 does not implement these four PCI interrupt pins It is recommended that t
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35. ter values that the MPC8560 accesses to read its own and the MSC8144 s vendor and device information Table 2 Device Detection by MPC8560 Access pu Access Register Value Type Description 1 CONFIG_ADDR 0 80000000 Write Allow a PCI configuration access when CONFIG_DATA is accessed Select bus number 0 Select device number 0 Access the PCI ID Configuration Register offset 0x00 CONFIG_DATA 0x1057 Read Vendor ID 0x1057 Freescale Semiconductor 2 CONFIG_ADDR 0 80000002 Write Allow a PCI configuration access when CONFIG_DATA is accessed Select bus number 0 Select device number 0 Access the PCI Device ID Configuration Register offset 0x02 CONFIG_DATA 0x0009 Read Device ID 0x0009 8560 3 CONFIG_ADDR 0 8000 800 Write Allow a PCI configuration access when CONFIG_DATA is accessed Select bus number 0 Select device number 21 Access the PCI Vendor ID Configuration Register offset 0x00 CONFIG_DATA 0x1957 Read Vendor ID 0x1957 Freescale Semiconductor 4 CONFIG_ADDR 0 8000 802 Write Allow a PCI configuration access when CONFIG DATA is accessed Select bus number 0 Select device number 21 Access the PCI Device ID Configuration Register offset 0x02 CONFIG_DATA 0x1400 Read Device ID 0x1400 MSC8144 MSC8144 PCI Example Software Rev 0 6 Freescale Semiconductor Memory Allocation Example Example 2 shows code that runs on the
36. tpiwar2 uint8 treserved13 0xC uint32 tpitarl uint8 treservedl4 0x4 uint32 tpiwbarl uint32 tpiwbearl uint32 tpiwarl uint8 treserved15 0xC mpc8560 pci regs MSC8144 PCI Example Software Rev 0 24 Freescale Semiconductor typedef struct MPC8560 Header File PCI Outbound Translation Address Register PCI Outbound Base Address Register PCI Outbound Comparison Mask Register PCI Inbound Translation Address Register PCI Inbound Base Address Register PCI Inbound Extended Base Address Register PCI Inbound Window Attributes Register status register capture disable register enable register attributes capture register address capture register extended address capture register data capture register volatile uint32 t potar volatile uint8 t reserved1 0 4 volatile uint32 t pobar volatile uint8 t reserved2 0 4 volatile uint32 t pocmr volatile uint8 t reserved3 0 4 pci outbound window t typedef struct volatile uint32 t pitar volatile uint8 t reservedl 0x4 volatile uint32 t pibar volatile uint32 t piebar volatile uint32 t piwar volatile uint8 t reserved2 0x4 pci inbound window t typedef struct PCI Error Management Registers volatile uint32_t pci esr PCI error volatile uint32 t pci ecdr PCI error volatile uint32 t pci err PCI error volatile uint32 t pci eatcr PCI
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