TTC/TTS Tester (TTT) Module User Manual
Contents
1. applied to the board e G0 3 indicate the Serial Number IP and MAC address that is currently set e G4 7 indicate the current TTS state being sent to the Ch A Fiber LED Functions inside of the VERIFY firmware are described in the TTT Hardware Verification Procedure section of this document 3 3 NIM Outputs The NIM outputs can be seen in Figure 1 and are labeled as BCO J5 L1A J4 NIMO J18 aux BCO and NIM1 J19 aux L1A Modes for NIM outputs can be selected using TTTControlRegister bits 4 to 7 In the default mode TTTControlRegisters 7 4 0x2 set to 0x0 e J5 will output BCO generated internally on the TTT e J4 will output the L1As being generated by the TTT as setup by the software see the Software Configuration Section In the receiver mode TTTControlRegisters 7 4 0x2 set to 0x1 e J5 and J4 will output the BCOs and L1As received on Fiber Channel A e J18 and J19 will output the BCOs and L1As received on Fiber Channel B 3 4 NIM Inputs The NIM inputs can be seen in Figure 1 and are labeled NIM_INO J20 NIM_IN1 J21 NIM_IN2 322 and NIM_IN3 J23 The default mode only utilizes NIM_INO which looks for falling edges and generates a single L1A Currently no other features or configurations are available for the NIM Inputs but a configuration register has been made available for future modes TTTNimInConfig 3 5 LHC Clock Input This input provides the option to substitute an external clock for the on boa2. 3 Firmware Core For more information on software configuration please see the Software Configuration sec tion Serial Number MAC Address IP Address 000 08 00 30 F3 00 00 192 167 2 32 001 08 00 30 F3 00 01 192 168 2 33 002 08 00 30 F3 00 02 192 168 2 34 003 08 00 30 F3 00 03 192 168 2 35 004 08 00 30 F3 00 04 192 168 2 36 005 08 00 30 F3 00 05 192 168 2 36 006 08 00 30 F3 00 06 192 168 2 38 007 08 00 30 F3 00 07 192 168 2 39 008 08 00 30 F3 00 08 192 168 2 40 009 08 00 30 F3 00 09 192 168 2 41 010 08 00 30 F3 00 0a 192 168 2 42 Table 2 IP and MAC Addresses I P addresses are set by jumper on the PC board as shown in Table 2 For reference on how the jumpers are set up see the section Jumpers Setting the Serial Number In addition to being used by the software to configure the TTT the ethernet can be used to write to the flash on the TTT Writing to the flash over IPBus allows for firmware updates to be carried out without a JTAG programming device Information on how to do this is available in the Software Configuration section This is only valid for non volatile programming and the old software version will be overwritten 3 8 Buttons Two buttons are available on the TTT and are appropriately labeled SW1 is a reset and SW2 causes an L1A to occur on a falling edge Both buttons are pulled high to 3 3V by default through the Spartan 6 s internal resistors and go low 0V when pressed Firmware de
3. ControlReg_enRepeats 0x00000112 0x00000002 R W enable repeats TTSControlReg_enBP 0x00000112 0x00000004 R W enable back pressure TTSControlReg_enRandTrig 0x00000112 0x00000008 R W enable random triggers TTSControlReg disableBlanking 0x00000112 0x00000010 R W disable blankking of L1A in orbit gap TTSStatusReg 0x00000113 Oxf R Status Register TTSStatusReg FifoEmpty 0x00000113 0x00000001 R Fifo Empty TTSStatusReg FifoFull 0x00000113 0x00000002 R Fifo Full TTSActionReg 0x00000114 Oxf R W Action Register TTSActionReg L1Aen 0x00000114 0x00000001 R W bit 0 L1A enable TTSActionReg_advanceFifo 0x00000114 0x00000002 R W bit 1 advance TTS FIFO to next word TTSActionReg_captureTrigCnt 0x00000114 0x00000004 R W bit 2 capture trigger count for readout TTSActionReg_genNewRand 0x00000114 0x00000008 R W bit 3 generate new random number TTSActionReg RST 0x00000114 0x00000080 R W bit 7 reset TTSDataReg 0x00000115 Ox fPftttt R Where data selected by TTSFi foByte is presented 10
4. TTC TTS Tester TTT Module User Manual Eric Hazen hazen bu edu Christopher Woodall cwoodall bu edu Charlie Hill chill90 bu edu May 24 2013 Contents 1 Overview z5 A 2 Quick Start Guide 3 Hardware Description 3 1 Jumpers Setting the Serial Number aaao aae 3 2 LED Arrangements 4 40 a a A E RA A A eee Ge a a ad 3 32 NIM Outputs 2 2s A A A a eRe Pe A Sy NIM Put Li a E e PL A e WR asi bse oot NS GO a Base 3 5 LHC Clock Input 00 e A ie es 3 6 Optical Fiber Transceivers o oo ee 3 64 LPC Protocol coa da Pe A A a ee Be Se 36 22 SEP Transmitters ad A A a A Bod 3 6 3 OEP Receiver 244 a A AAA re 3 0 Ethernet Intertace us isos a da A a ia es 3 8 Buttons oes it AA RA A TE SO ee ee E e vee Ge eh O E A ahs Me aan ed 3 10 Legacy TTS EVDS o cece ted ee dauh A ht ee le eo ee eel a 4 Software Configuration 5 TTT Hardware Verification Procedure 6 IPBus Registers COONNNAWAA OCA 00 1 Overview This document describes a module developed at Boston University for use in CMS test stands especially those based on MicroTCA using the AMC13 module for clock trigger DAQ functions The TTC TTS Tester Module TTT performs the following functions e Generate simulated TTC signals on two optical fiber outputs with LIA generated periodically or at pseudo random intervals BCO with correct spacing every 3563 clocks CMS trigger rules observed programmable TTS buffer
5. bouncing is performed on both buttons 3 9 JTAG Port A JTAG at site J1 is provided as a standard 1 inch header The signal names are marked TMS TDI etc on the TTT board This particular JTAG pinout is meant for use with the Digilent HS 1 JTAG programmer for Xilinx chips However another JTAG programmer which is compatible with the Xilinx ISE software or known to be compatible with Xilinx 6 series chips may also work but will receive no user support This port can be used for both volatile program to FPGA and non volatile program to SPI Flash programming using the provided bit and mes files 3 10 Legacy TTS LVDS In the default mode set by writing FIXME to the FIXME register the LVDS channels act as follows e Channel A and Channel B Tx send the TTS state being received from the AMC13 e All Rx channels are turned off In legacy mode set by writing FIXME to the FIXME register the channels act as follows e Channel A and Channel B Rx receive the TTS state SFP new TTS messages are ignored e Channel A Tx passes through Channel A Rx the same goes for Channel B 4 Software Configuration Charlie 5 TTT Hardware Verification Procedure Blank for now Will be filled in 6 IPBus Registers Describe all available registers Table 3 TTT Register Table Name Address Bit Mask R W Description VERSION 0x00000000 Ox fEfheret R Format YYYYMMDD where YJear MJonth and Day FirmwareVer
6. it TTSL1APerOrbit 0x00000104 Oxf R W number of L1A per orbit TTSRepeatPeriod 0x00000105 Ox fEfFeret R W time between repeats in orbits TTSFifoByte 0x00000106 OxfEfEfEfE R W Select byte to read TTSFifoByte_FifoData 0x00000106 0x0000000f R W Fifo data TTSFifoByte_FifoWordCnt 0x00000106 0x00000030 R W Fifo Word Count TTSFifoByte_TriggerCnt 0x00000106 0x000003c0 R W Trigger Count TTSFifoByte_CounterMux 0x00000106 0x00000400 R W Counter Mux TTSCounterByte 0x00000107 Ox fEfhfret R W Select coutner to read 0 3 Rule violation 1 4 TTSRateSet 0x00000108 Ox fEfheret R W random threshold Continued on next page Table 3 continued from previous page Name Address Bit Mask R W Description TTSRulel 0x00000109 OxfEfEfEfE R W no more than 1 trig N Bx TTSRule2 0x0000010a OxfEfEfEfE R W no more than 2 trig N Bx TTSRule3 0x0000010b OxfEfEfEfE R W no more than 3 trig N Bx TTSRule4 0x0000010c Ox R W no more than 4 trig N Bx TTSClkSel Ox0000010d Oxf R W select orbit signal clock phase TTSSetBPDelay 0x0000010e Ox fPftttt R W delay responding to BSY OFW TTSBPSampleMask 0x0000010f Ox R W sample TTS when n and BcN TTSTTCBxNum 0x00000110 Oxf R W NIM TTS output at this BcN TTSTTCCmdPrescale 0x00000111 Ox R W NIM TTS prescale not impl yet TTSControlReg 0x00000112 Ox fEfifhet R W Control Register TTSControlReg enBurt 0x00000112 0x00000001 R W enable burst 1 trigger per or bit TTS
7. of the TTC system The A channel is used to carry L1A generated internally or received from the NIMO input The B channel sends broadcast commands such as those shown in Table 1 BCR BCO is sent every orbit 3563 clocks Other broadcast commands may be sent under software control Typically to start a data collection run on a test stand the sequence OCR ECR would be sent with L1A disabled before the start of data taking Value Acronym Name 00101000 0x28 OCR Orbit Count Reset 00000010 0x02 ECR Event Count Reset 00000001 0x01 BCR a k a BCO Bunch Count Reset Table 1 TTC Broadcast Commands Send Processed by TTT 3 6 3 SFP Receiver The SFP Receiver receives a bitstream from the AMC13 module which carries TTS and local trigger infor mation The TTC protocol is currently used A broadcast command is sent periodically by the AMC13 in which the upper 4 bits represent the current TTS state Channel A is used for local L1A generated in the AMC13 The TTS state is output to the corresponding RJ 45 connector and also used to modify the operation of the internal L1A generator If the TTS signals represent any state other than Ready the L1A will be halted until the state returns to Ready 3 7 Ethernet Interface The ethernet interface seen in Figure 1 can be used to comunicate between the TTT board and a computer over an 100Mb Full Duplex ethernet connection All ethernet transactions are handled by the IPBus v1
8. onnectors output BCO s and take the received messages and output the L1A s and BCO0 s on the associated NIM outputs you need to write 0x10 to the TTTControlReg Address 0x2 Please refer to Figure 1 for location More detailed information can be found in the section NIM Outputs 3 Hardware Description Figure 2 is a basic interface diagram nmo OH uma OH wz O nms OH NIM L1A out NIM BCO out Spare NIM 2 out Spare NIM 3 out Ext CLK o4 TTS out 2 TTS in 2 LVDS LVDS 10 100 Ethernet Figure 2 TT T Block Diagram with all connectors noted 3 1 Jumpers Setting the Serial Number The TTT board provides 4 GPIO pins on J14 surrounded by 3 3V J3 and GND J17 These 4 GPIO pins go to pins P35 P32 P30 and P39 on the Spartan 6 and are used to set the serial number Each board is assigned and shipped with a serial number in a 4 bit number space where each bit of the serial number corresponds to one jumper as indicated in Figure 3 The jumper setting of 0 is reserved for verification mode 3 Q a 23 SN 0 SN 1 SN 2 SN 3 To MEN Figure 3 Configuration for Settings Jumpers 3 2 LED Arrangement Figure 4 shows the LED arrangement on the front of the TTT In the default power on mode of operation the LEDs indicate the following Figure 4 LED Arrangement and Association e When RO is solid the DCM is locked and reliable operation can be expected e Rl indicates that power is being
9. rd 40 079 MHz crystal It must be selected by writing FIXME to register FIXME 3 6 Optical Fiber Transceivers Two SFP cages are provided for optical fiber transceivers For compatibility wit the TTC system it is recommended to use SFP transcievers compatible with the ATM network protocol 3 6 1 TTC Protocol The SFP transceivers process biphase mark encoded bit streams using the protocol specified for the CERN TTC system The biphase mark encoding scheme is illustrated in Figure 5 Two bits called channels A B are transmitted each clock cycle Channel A indicates that an L1A is present while channel B is used to carry serial data as detailed in Figure 6 Channel B sends 1 s continuously when idle with a 1 0 transition representing the start of a frame Various types of frames are documented for the TTC system but the only type used by this board is the Broadcast Command frame An 8 bit command is transmitted with the values of the bits shown in Fig 6 4 24 9501ns _ gt A Channel B Channel Unlimited string length when idle String length gt 10 illegal switch phase Figure 5 TTC Low Level Encoding General Frame Idle Start Stop Broadcast Command Data L BcN Reset EvN Reset CMD Data 0 CMD Data 1 CMD Data 2 CMD Data 3 Test CMD O Test CMD 1 Figure 6 TTC Frame and Broadcast Command Format 3 6 2 SFP Transmitter The transmitters simulate the output
10. sionID 0x00000000 Oxf R Firmware Version ID same as VERSION maintains back wards compatibility STATUS 0x00000001 OX EEEELEfE R 0x1 read write FLASH_MemoryRead 0x00000001 0x00000004 R Read to get Memory Read FLASH_FIFOempty 0x00000001 0x00000002 R Fifo Empty Status FLASH_BUSY 0x00000001 0x00000001 R Flash Busy FLASH_CMD 0x00000001 OxfEHEE W Flash command register TTTControlReg 0x00000002 Oxf R W Control Reg TTTControlReg_ChangeClockSrc 0x00000002 0x00000004 R W Write to 1 to change clock source to LHC Clock FIXME TTTControlReg_DisableBCO 0x00000002 0x00000008 R W Write to 1 to disable BCO s on all output streams TTTControlReg NimModes 0x00000002 0x000000f0 R W Sets NIM modes the controls are as follow write l to bit 0 to switch to receiver mode TTTActionReg 0x00000003 Oxf R W Action Register TTTActionReg SendBcastCmd 0x00000003 0x00000002 R W Write 1 to send Beast Com mand must be manually reset to 0 TTTBcastCmd 0x00000004 Oxf R W Load Broadcast command into the lower 8 bits the remaining bits do not matter Send using TTTActionReg bit 1 FLASH WBUF 0x00001000 OxfEfEEE R W Write flash FLASH RBUF 0x00001080 OX EEFELHfE R W Read flash TTSOrbitLength 0x00000100 Oxf R W BX per orbit nom 3563 TTSTrigStart 0x00000101 Oxf R W delay to first trigger TTSOrbitMax 0x00000102 Oxf R W number of orbits with triggers TTSL1ASpacing 0x00000103 Ox fPftttt R W spacing of L1A within orb
11. status respected e Receive and process TTS status from AMC13 on optical fiber Use to modulate trigger rate for internally generated L1A Translate to legacy TTS FMM output on RJ 45 connector JTAG connector 5V power in Jumpers center NIM Inputs 3 2 e mdi lt Aux outputs NIM Pai 1 e E BCO L1A S Buttons a e j pd OA IS Reset y EI Out In Out In TTC TTS LEDs New a B External clock in TTS Interface Fiber to Legacy AMC13 ETA ouk NIM BCO out NIM Ethernet 10 100 Figure 1 Board Overview with Connectors Illustration 1 shows an overview of the board with connectors and controls Detailed information is in the Hardware Description section 2 Quick Start Guide Connect a 5V power supply to the power connector J9 Use the supplied wall transformer or make your own cable center terminal is positive The board should provide the following functions without any software intervention e The BCO nim output should provide a 75ns three clock cycles wide pulse at the LHC orbit frequency e Both TTC fiber outputs transmitter on SFP should provide a valid TTC bit stream with BCO encoded every 88us e The TTS state received from the AMC13 on the SFP receivers should be output as LVDS on the RJ 45 outputs e The NIMO input should generate a L1A on both TTC outputs when a falling edge is seen In order to use the board in receiver mode where the Channel A and Channel B SFP c
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