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FPGA board user manual

1. 120 DONE 162 204 GND 121 163 D2 205 VREF1 122 PROGRAM 164 VCCINT 206 123 165 207 124 07 166 GND 208 VREF1 125 10 167 01 209 I O 126 VREF3 168 VREF2 210 Gck2 127 vo 169 VREF2 211 GND 1128 170 212 129 GND 171 VREF2 213 GCK3 130 VREF3 172_ GND 214 VCCINT 1131 10 1173 VO 215 VREFO 132 VREF3 174 216 133 VREF3 175 VREF2 217 10 134 06 176 vo 218 VREFO 135 GND 177 Do DIN 219 GND 136 VCCO 178 BUSY DOUT 220 137 VCCINT 179 CCLK 221 VO 138 D5 180 VCCO 222 VREFO 139 181 223 140 VREF3 182 GND 224 VO 141 VO 183 TDI 225 VCCINT 1142 10 184 CSV 226 143 GND 185 WRITE 227 GND 144 VREF3 1186 VO 228 VO 145 D4 187 VREF1 229 1146 10 1188 10 230 VREFO 147 VREF3 189 I O 231 10 148 190 GND 232 VREFO 1149 10 191 1 233 GND 150 192 234 151 GND 193 VREF1 235 W O 152 VO 194 VREF1 236 VREFO 153
2. esse 22 Table 19 Choice of the clock sources eese 23 Table 20 External clock signals and termination resistors 23 Table 21 Crystal oscillator control signals and usage 24 Table 22 Reset pulse polarity selection eee 25 Table 23 User button connection with FPGA eese 25 Table 24 LED signals and corresponding FPGA pins 26 Table 25 Signals on the eight position DIP switch eee 26 Table 26 Grouping bank and signal assignment of VREF jumpers 28 Table 27 Correspondence of VREF jumpers to individual devices 30 Table 28 Options for running the RAM and their activation 3l Table 29 Assignment of signals to the STAC connector 33 Table 30 Assignment of signals to the ST5A connector 34 Table 31 Assignment of signals to the ST5B connector 35 Table 32 Dedicated signals on connector 36 Table 33 Pin assignment of Spartan II FPGAs in the PQ 208 package 41 Table 34 Pin assignment of Virtex FPGAs in the HQ 240 package 43 Table 35 Pin assignment of Virtex E FPGAs in the HQ 240 package 45 ErSt Electronic GmbH Aeschstras
3. 9 9 E 5 S c SignalName 6 SignalName 2 o gt o gt Unconnected 51 L22P _ 76 155 L43P _ 52 63 74 L20N 77 188 159 L42N _ 53 6 78 L20P 78 139 160 L42P _ 54 68 79 L19N 79 141 162 5 55 70 81 L17N 80 149 170 L41N _ 56 71 82 L16N 281 151 173 DLLL40P 57 81 93 L16P 82 152 174 L39P _ 58 83 95 VREF_Li3N 83 1 7 L37N _ 59 86 99 L12N 84 163 189 L37P 60 87 100 L12P _ 85 162 188 L36N _ 61 89 102 L11N _ 86 165 192 L36P _ 62 90 103 L9P 287 172 199 L35N _ 63 94 107 LON _ 88 173 200 L34N _ 64 9 110 L8N _ 89 176 203 L33P _ 65 10 114 L7N 290 179 206 L32N _ 66 99 117 DLLL6P 91 181 209 L30N _ 285 DLLL6N 92 187 215 L29N 68 109 127 L5P 293 189 217 L29P _ 69 110 128 L4N 294 192 221 L28P 270 112 181 L3P _ 95 194 223 L26P 71 120 139 L3N _ 96 195 224 L25N 72 122 141 L2P 297 199 228 L25P 73 123 142 L1P 98 205 234 lo 3 74 129 149 L1N 99 206 235 L23P _75 _133 153 LON 100 204 237 Table 31 Assignment of signals to the ST5B connector ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 36 47 3 10 5 Dedicated Signals The header connector ST4B contains some dedic
4. 100 137 GND 169 GND 201 138 1170 VCCO 202 139 1171 VCCINT 203 O_VREF 1140 172 VO 204 141 10 173 205 WO VREF200 1142 D2 1174 VO 206 143 VCCINT 1 05 19 207 144 VCCO 176 VO 208 VCCO 145 GND 177_ GND 146 01 178 I O_VREF 1147 WO_VREF100 1179 1148 I O 1180 I O 1149 1181 IO 150 VREF 182 GCK2 1151 1183 GND Table 33 Pin assignment of 5 FPGAs in the PQ 208 package denoted with I O_VREF are optional reference voltage pins on all devices Pins denoted with I O_VREF100 are additional reference voltage pins on XC28100 and XC2S150 devices Pins denoted with I O_VREF200 are additional reference voltage pins on XC2S200 devices ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 42 47 5 3 Virtex Devices HQ 240 Package Pin Description 40 VREF6 80 VREF5 1 GND 14110
5. 195 237 VO 154 VREF2 196 GND 238 I O 155 197 VCCO 239 TCK 156 D3 198 VCCINT 240 VCCO 157 VREF2 199 1 0 158 GND 200 VO Table 34 Pin 159 10 201 ee 160 1 0 202 10 161 VREF2 203 ErSt Electronic GmbH Aeschstrasse 171 CH 8123 Ebmatingen Fax Phone Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALX2S XCV XCVE User Manual 44 47 5 4 Virtex E Devices HQ 240 Package Pin Description 40 VREF10 6 80 VREF10 5 GND 41 L52P 181 105 2 TMS 42 L52N 82 L41N 43 VCCINT 83 GND 4 163 44 84 VREF 141 5 VREF 163 45 GND 85 6 L62P 46 86 VREF 5 7 L62N 47 VREFLSIN 87 DLL L40N 8 GND 48 VREF6106 88 VCCINT 9 VREF_L6iP_ 49 89 GcK1 10 L61N 50 VREF 150 90 11 VREF610 7 51 GND 91 GND 12 vREFLeoP 52 L49P 92 GCK0 13 160 53 149 193 IDLL_L40P 14 GND 54 VREF 6 94 VREF L39N 11524660 55 95 16 VCCI
6. 163 D2 205 VREF 17 122 PROGRAM 164 VCCINT 206 L7N 123 INIT 165 207 VCCO 1124 D7 166 GND 208 VREF 1 125 130 167 01 209 16 126 VREF_L30P 168 VREF 118 _ 210 Gck2 127 L29N 169 VREF6102 211 GND 128 129 170 117 212 VCCO 129 GND 171 VREF_L17P 213 GCK3 130 VREF_L28N 172 GND 214 131 128 173 116 215 DLL L6N 132 VREF6103 174 116 216 VREF 0 133 VREF L27N 175 VREF 2 217 L5P 1134 D6 176 VCCO 218 VREF_L5N 135 GND 177 DO DIN 219 GND 136 VCCO 178 BUSY DOUT 220 L4P 137 VCCINT 179 CCLK 221 L4N 1138 D5 180 VCCO 222 VREF610 0 139 126 181 TDO 223 L3P 1140 VREF103 182 GND 224 L3N 1141 125 183 TDI 225 VCCINT 142 L25P 184 226 1143 GND 185 WRITE 227 GND 144 VREF_L24N 186 L13P 228 L2P 145 D4 187 VREF L13N 229 VREF L2N 1146 VCCO 188 L12P 230 VREF610 1147 VREF 3 189 L12N 231 VREF40 0 148 VCCINT 190 GND 232 1149 103 191 VREFLIIP 233 GND 150 192 L11N 234 L1P 151 GND 193 VREF610_1 235 LIN 152 L23N 194 VREF L10P 236 153 L23P 195 110 237 LON 154 VREF L22N 196 GND 238 IO 0 155 122 197 239 156 D3 198 VCCINT 240 VCCO 157 VREF_L21P_ 199 L9P i 158 GND 200 LON Table 35 Pin 159 120 201
7. ASIC Application Specific Integrated Circuit DIL Dual Inline DIP Dual Inline Package DLL Delay Locked Loop FPGA Field Programmable Gate Array GND System Ground HQ Thermally enhanced QFP IEEE Institute of Electrical and Electronics Engineers IOB Input Output Block ISP In System Programmable JTAG Joint Test Action Group LED Light Emitting Diode OTP One Time Programmable PG Personal Computer PCB Printed Circuit Board PLCC Plastic Leaded Chip Carrier PLL Phase Locked Loop PROM Programmable Read Only Memory PWM Pulse Width Modulation QFP Quad Flat Pack SCP Serial Configuration PROM SMD Surface Mounted Device SPROM Serial PROM VCCINT Internal supply voltage VCCO Output driver supply voltage VCCOPT Optional supply voltage VCXO Voltage Controlled Crystal Oscillator VQ Plastic very thin QFP ZBT Zero Bus Time Spartan ll and Virtex are trademarks of Xilinx Inc ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 5 47 Contents AES 005 c ces eens 8 EE c 2 9 2 1 Key Features 5i iie uus Eoo 9 2 2 e 9 2 3 Function Description 11 3 Technical Information 13 31 Power Supply sssssssssssssssssssssssssss
8. other layers are driven also The maximal output current of 20mA of an FPGA port is sufficient for up to four layers If more than four levels are used or to avoid driving certain LEDs the jumpers of the appropriate LEDs of the remaining layers must be removed 3 7 Eight Position DIP Switch The eight position DIP switch SW1 can be used for application specific purposes In the On position the connected FPGA pin is tied to ground In the Off position the connected FPGA pin is pulled to VCCINT via a resistor The assignment of the switches to the FPGA pins is as follows 1 DO DIN 153 177 2 D1 146 167 3 D2 142 163 4 D3 135 156 5 04 126 145 6 D5 119 138 7 D6 115 134 8 D7 108 124 Table 25 Signals on the eight position DIP switch The switches are connected to the FPGA via resistors of 510Q Owing to these resistors the Select MAP mode can be used even if some switches are closed to ground ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 27 47 3 8 Reference and I O Signals For the smaller FPGA devices some pins are usable as general I Os whereas these pins are reference voltage inputs on the larger ones Certain I O standards need no reference voltages In these cases all of these pins may be used as general 1 05 on every FPGA type To make the board as versatile a
9. 14 17 VREF_L50N 116 45 50 L6ONN 14 10 13 L50P 117 44 49 VREF_L60P 142 9 12 VREF610 6 118 43 48 vREFe10 7 143 8 11 VREF 119 42 47 6 144 7 10 L51P 120 41 46 VREF_L61P 145 6 9 L52N 121 37 42 L62N 146 4 2 1 L52P 122 36 41 Lo2P 147 3 6 10 6 123 35 40 VREF_L63N 148 5 L53N 124 34 39 L63P 149 5 4 L53P 125 33 38 7 150 3 Table 29 Assignment of signals to the ST4C connector Aeschstrasse 171 Phone CH 8123 Ebmatingen Fax 441 1 980 61 44 41 1 980 61 30 ErSt Electronic GmbH Internet http www erst ch EVALX2S XCV XCVE User Manual 34 47 3 10 3 Signal Assignment to Connector ST5A The following table shows the assignment of the FPGA pins to the ST5A connector pins S Sc SignalName o 1 GENES Button2 2 1 3 VREFIO 5 4 69 80 VREF 5 5 74 86 VREF_L41P 6 73 84 DLL L40N 7 87 VREF L39N 8 82 94 VREF 9 97 L38N 10 84 96 10 84 96 10 4 11 88 101 VREF610 4 12 96 109 VREF L35P 13 95 108 VREF L34P 14 98 111 L33N 15 100 113 VREF 4 16 102 115 L32P 17 18 VREF L30P 18 VREF_L28N 19 111 130 VREF610 20 113 132 VREF_L27N 21 1
10. 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCV User Manual 47 47 7 Appendix C Schematic Diagram and PCB Layout The following pages show the technical details of the board Top overlay silk screen and top layer Mid layer 1 Mid layer 2 Bottom overlay silk screen and bottom layer Schematic diagram The ground plane and the supply voltage plane shown ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch
11. 2 Slave Serial Mode In slave serial mode the FPGA receives configuration data in bit serial form from a serial PROM or other source of serial configuration data An external device e g XChecker cable generates the download clock Multiple FPGAs can be daisy chained for configuration from a single source After a particular FPGA has been configured the data for the next device is routed to the DOUT pin The slave serial mode is selected by the following jumper settings Table 12 Slave serial mode selection 3 2 2 1 Configuration via XChecker Port In slave serial mode the serial configuration data comes from the XChecker port J4 Either a parallel or a serial cable may be used Due to the 3 3V cable supply voltage we recommend to use an appropriate cable Xilinx order number HW XCH8V Nevertheless experiments with 5V cables showed that these cables work well down to 3V parallel cables even down to 2V The circumstances under which a certain cable will work depend on many factors including the PC used Whether a cable that is specified for 5V operation will work is not guaranteed In any case we strongly recommend using the MultiLinx cable that has the additional advantage of being able to use the USB bus This brings an enormous increase in download speed ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 20 47 T
12. CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 6 47 3 9 RAM ODBpMtIOn enano 31 3 10 Signals on Header Connectors 32 3 10 1 Signal Over vie 32 3 10 2 Signal Assignment to Connector ST4C 33 3 10 3 Signal Assignment to Connector ST5A 34 3 10 4 Signal Assignment to Connector ST5B 35 3 10 5 Dedicated Signals neun ea de 36 3 11 Stack Extension esossssoossssonssssonssnnnsnssnnsnssnnnnsnnnnnnsnnnnnsnnnnenen 36 37 5 Appendix A FPGA Pin Assiegnments 39 5 1 Special Considerations 39 5 2 Spartan II Devices in PQ 208 Package 40 53 Virtex Devices in HQ 240 Packaege 42 54 Virtex E Devices HQ 240 Packaege 44 6 Appendix B Changes and Improvements 46 7 Appendix C Schematic Diagram and PCB Layout 47 Figures Figure 1 Block diagram of the board module eee 11 Figure 2 Wiring of the daisy chain eese 22 ErSt Electronic GmbH Aeschstras
13. J80 VREF_L22N J81 VREF_2 J82 VREF10_2 J83 VREF610_2 X J85 VREF_L11P X X X X X X X X J86 VREF_L10P J87 VREF_L7P J88 VREF_L13N J89 VREF_1 J90 VREF10_1 J91 VREF610_1 XT J93 VREF_L2N X X X X X X X X J94 VREF_L0P J95 VREF_L5N J96 VREF_0 0 J97 VREF40_0 J98 VREF610_0 J99 VREF610 J100 L5P J101 L1P Table 27 Correspondence of VREF jumpers to individual devices ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 31 47 3 9 2 RAM Option The ZBT RAM U10 is an optional component of the module If this RAM is present the header connector ST5B where all RAM signals are routed to is not available This is to avoid conflicts when you stack several boards The synchronous RAM clock input is specially handled First it may be driven directly from GCK2 over the coaxial SMB connector J17 In this case you should use this GCK2 clock to drive the FPGA also Doing the clocking that way you have a true synchronous system clock for both FPGA and RAM Second you may drive the RAM clock from the FPGA output signal L20N pin 138 on Spartan ll pin 159 on Virtex E by inserting jumper J124 Now you are free to use any clock for the FPGA but the price to pay is that you do not have a true synchronous system clock for the RAM any more How
14. O e For Virtex E devices the signals are named with their low voltage differential input names e Dedicated signals and multipurpose signals such which may change to general I Os after configuration are named with the function name they have prior to configuration e Reference voltage pins have the string VREF in their name e Shading indicates banking 5 1 Special Considerations 1 Pins 25 55 85 116 146 176 207 216 and 231 are I O pins on Virtex devices whereas they are VCCO pins on Virtex E devices These pins are connected to VCCO on this board module If you use this module with a Virtex device configure these pins as input 2 Pins 87 and 215 are VREF pins on Virtex devices whereas they are general I Os on Virtex E devices 3 Pins 5 12 47 73 108 133 168 194 and 229 are optional reference voltage pins in the Virtex 100E to 1000E devices 4 Pins 54 66 115 126 175 187 and 236 are optional reference voltage pins in the Virtex 200E to 1000E devices 5 Pins 26 33 86 94 147 154 208 and 216 are optional reference voltage pins in the Virtex 400E to 1000E devices 6 Pins 1 48 72 109 132 169 193 222 and 230 are optional reference voltage pins in the Virtex 600E to 1000E devices 7 Pins 19 40 80 101 140 161 and 201 are optional reference voltage pins in the Virtex 1000E devices ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Inte
15. VREFIO1 160 120 202 18 1161 VREF10 2 203 L8N ErSt Electronic GmbH Aeschstrasse 171 CH 8123 Ebmatingen Fax Phone Internet 441 1 980 61 44 41 1 980 61 30 http www erst ch EVALXCV User Manual 46 47 6 Appendix B Changes and Improvements This appendix lists the changes and improvements of the board module compared to its predecessor EVALXCV HQ240 Changes e signals TDI and are no longer routed to the pins 68 and 71 of ST4B This makes it now possible to interconnect stacked boards in a single JTAG chain e Connectors J4 XChecker and J5 now have two rows to enable the wiring of external configuration chains within a stack e The order of the power connectors for VCCINT VCCO and VCCOPT is now the same as on the power module PWR3 Additional Features e User buttons are now also accessible on header connector ST5A at pin 2 Button 2 and pin 3 Button3 When you stack several boards the buttons will now be connected in parallel Pressing the button of the topmost board has now the same effect as pressing the same button on all boards simultaneously We have done this because it is not possible to reach either button 1 or button 2 with a finger when the boards are stacked e Asynchronous ZBT RAM has been added It gets its clock either from GCk2 synchronous clock for both FPGA and RAM or from an output of the FPGA ErSt Electronic GmbH Aeschstrasse
16. connect an external supply 3 1 4 Mounting the PWR3 Power Module The power module can be plugged to the board module by means of two single inline 50 pole connector pairs The assembly is correct if the three four pole output connectors of the power module and the single six pole supply voltage connector of the board module are on the same side Please check that the orientation of the two boards and the output voltage settings of the power module refer to the PWR3 user manual are correct before applying power ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 17 47 3 2 FPGA Configuration The FPGAs with Virtex architecture support the following four configuration modes e Master Serial Mode e Slave Serial Mode e SelectMAP mode e Boundary scan mode The configuration pins M2 M1 MO select among these modes with the option in each case of having the IOB pins either pulled up or left floating prior to configuration The selection codes are listed in Table 7 An inserted jumper ties the appropriate pin to ground whereas the pin is pulled high if the jumper is removed Here and in the following tables a Yes in the jumper column means that the jumper is present whereas a means that no jumper is plugged in Mode J3 J2 J1 CCLK Bits Busy Internal M2 M1 MO Direction D
17. of Arithmetic Functions Virtex Device Quad Data Rate QDR SRAM Interface CDMA Matched Filters Implementation in Virtex Devices PN Generators Using the Virtex SRL Macro Linear Feedback Shift Registers in Virtex Devices IDCT implementation in Virtex Devices for MPEG applications Data Width Conversion FIFOs using Virtex Block SelectRAM CAM in Block Select RAM Designing Flexible Fast CAMs with Virtex Slices CAM in ATM applications An Overview of Multiple CAM Designs in Virtex Devices Double Data Rate SDRAM Powering Virtex FPGAs Board Routability Guidelines with Xilinx Fine Pitch BGA Packages Virtex Analog to Digital Converter Virtex Synthesizable Delta Sigma DAC Aeschstrasse 171 Phone 441 1 980 61 44 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 38 47 XAPP153 Status and Control Semaphore Registers Using Partial Reconfiguration XAPP152 Virtex Power Estimator User Guide XAPP151 Virtex Configuration Architecture Advanced Users Guide XAPP137 Configuring Virtex FPGAs from Parallel EPROMs with a CPLD XAPP136 Synthesizable 143 MHz ZBT SRAM Interface XAPP135 Virtex I V Curves for Various Output Options 134 Virtex Synthesizable High Performance SDRAM Controller XAPP133 Using the Virtex SelectlO 132 Using the Virtex Delay Locked Loop XAPP131 170MHz Synchronous and Asynchronous FIFOs Using the Virtex Block SelectRAM XAPP130 Using the Virtex Block
18. which works with 3 3V For other I O standards which work with 1 5V or 2 5V the 3 3V voltage must be taken from a third source The voltages VCCINT VCCO and VCCOPT may be taken from external power supplies via the power connectors The preferred method however is the usage of the power module PWR3 that we developed especially for this purpose The power module can be plugged onto the Virtex board module by means of two 50 pole connectors In addition the power module also generates eight reference voltages needed by the FPGA to support the multi standards Beside the 50 pole connectors the power module is equipped with three power connectors and can be connected to other board modules using cables 1to 12 VCCOPT 131025 GND 261042 Reserved 43 f VREF0 44 VREF1 516 45 VREF2 46 47 VREF4 48 VREF5 49 VREF6 50 VREF7 1012 _ VCCINT 517 13 to 38 GND 39 to 50 VCCO Table 1 Pin assignment on the power header connectors ST6 and ST7 ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 14 47 3 1 1 3 3V Supply 3 3V supply is needed for various devices SPROMs crystal oscillators voltage supervisor general purpose LEDs JTAG and XChecker ports This supply may be derived from V
19. 14 133 VREF10 22 121 140 VREF_L24N 23 125 144 24 127 147 Signal Name Connector Pin Spartan ll Pin Virtex Pin VREF L22N 26 134 154 VREF 21 27 136 157 VREF10 2 28 140 161 VREF L18P 29 147 168 VRE610 2 30 148 169 17 31 171 VREF 2 32 175 L13P 33 186 VREF 0 34 167 194 VREF L11P 35 164 191 VREF610 1 26 166 193 L10N 37 168 195 L8P 39 175 202 VREF_L7P 40 178 205 1 41 180 208 0 42 202 231 VREF_L5N 43 L4P _44 191 220 VREF610 0 45 193 222 VREF610 46 201 230 VREFL2N 47 200 229 VREF40 0 48 188 216 VREF_LOP 49 203 236 101 38 174 201 Table 30 Assignment of signals to the ST5A connector ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 35 47 3 10 4 Signal Assignment to Connector ST5B The following table shows the assignment of the FPGA pins to the ST5B connector pins This connector is no present when the ZBT RAM is mounted on the board
20. 185 SW4 XCS 160 184 Table 23 User button connection with FPGA The connection of a user button with the FPGA is routed over a 5100 resistor A pressed button does therefore not harm the SelectMAP interface 3 6 LEDs The eight LEDs D2 to D9 are intended as optical indicators for the display of status information D1 is connected to the DONE pin of the FPGA and D10 VCCOPT 011 VCCO and D12 VCCINT serve as power indicator LEDs The DONE LED turns on at the end of a successful bit stream download Note The VCCO indicator LED D11 will not lit when the VCCO voltage is 1 5V or less since this value is below the forward voltage of the LED The LEDs D2 to D9 turn on whenever the corresponding FPGA output is low Each LED may be disconnected from the I O signal by removing the corresponding jumper The following table shows the assignment to the jumpers and the FPGA pins ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 26 47 02 J14 148 46 56 D3 J13 L45N 57 67 D4 J12 L45P 58 68 D5 J11 L44P 60 71 D6 J10 L10N 168 195 D7 J9 L23N 132 152 D8 J8 L33N 100 113 09 47 L38N 84 96 Table 24 LED signals and corresponding FPGA pins Note If the board module is used within a stack the LEDs of all layers are connected in parallel If a LED is driven by the FPGA the LEDs of the
21. 2 of the FPGA to achieve a real synchronous system clock Alternatively you can generate the RAM clock internally to the FPGA In this case the clock is gated through an output pin connected to the RAM clock input via a jumper The GCK2 clock may then not be driven externally By stacking several boards you may implement circuits whose complexity is beyond the scope of a single FPGA The whole stack is configurable with a single download by means of an external daisy chain You can also link the stacked boards in a JTAG chain Two sockets are provided to hold Xilinx OTP SCPs two XC1704L in a PLCC44 package In addition two ISP SCPs XC1800 family are mounted on the back side of the board You can program these SCPs using the JTAG mode Four clock sources can be used where two of them are either an onboard crystal oscillator or an external source The other two sources are always external sources The crystal oscillators are mounted in sockets and can therefore be exchanged easily Both a DIL 8 and a DIL 14 package can be used There is the possibility to terminate all clock traces near the FPGA with resistors to ground These resistors may be mounted by you on the bottom side of the PCB A voltage supervisor circuit generates a short pulse of ca 2ms duration whenever the core supply voltage VCCINT drops below 2 2V 1 7V for Virtex E and on power up The polarity of the reset pulse can be chosen to be either active high or active low Su
22. 8 10 2 TMS 14210 82 10 B vo 43 VCCINT 83 GND 4 vo 44 84 VREF5 5 VREF7 45 GND 185 10 l6 vo 46 vo 86 vo 7 vo 47 VREF6 87 VREF5 8 48 VREF6 88 VCCINT 9 VREF7 49 Vo 89 10 1 0 50 6 90 11 VREF7 51 GND 91 GND 12 VREF7 52 92 13 vo 53 93 vo 14 GND 54 VREF6 94 VREF4 15 vcco 55 10 95 10 16 VCCINT 56 10 96 O 117 vo 57 10 97 VREF4 11810 58 98 GND 19 7 59 GND 99 10 20 1O 60 0 1100 231 vo 61 101 VREF4 22 GND 62 M2 1102 10 23 VREF7 163 10 103 IO 244 vo 64 10 104 VCCINT 25 10 65 105 26 VREF7 66 VREF5 106 GND 27 vo 167 10 1107 10 28 vo 168 10 108 VREF4 29 GND 69 GND 109 VREF4 30 70 VREF5 1110 10 31 VO 71 vo 111 VREF4 32 VCCINT 72 5 112 GND 33 VREF6 73 VREF5 1113 34 VO 174 vo 1114 35 VO 75 115 VREF4 36 VREF6 76 116 37 GND 77 VCCINT 1117 0 38 78 vo 118 vo 39 VO 79 vo 119 GND J ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 43 47
23. A family in the PQ208 or HQ 240 package respectively This board is especially suited to test digital circuits during the early stages of their development You can easily attach a logic analyzer an watch the signals in real time The high count of system gates enables you to implement circuits that reach the complexity of ASICs The configuration data of the FPGA is downloadable using one of four modes master serial mode XChecker slave serial mode SPROM boundary scan mode JTAG and SelectMAP mode The block diagram of Figure 1 shows the functional blocks of the board Reference Voltage 10 Connections Power and Vret General I O User Interaction 8 Viet 4 Clocks Configuration External Connection Onboard Item Functional Group Figure 1 Block diagram of the board module ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 12 47 All general I Os of the FPGA are routed to header connectors If you use I O standards that need reference voltages you can select up to eight different voltage levels for all eight banks individually with jumpers An optional ZBT RAM helps you to support memory demanding implementations like imaging and telecommunication applications The clock input of this RAM is connected to the global clock GCK
24. CCO or VCCOPT according to the following table VCCO 424 3 3 1 5V 3 3V 1 2 2 5V 3 3V 1 2 3 3 not used 2 3 Table 2 Derivation of the 3 3V supply voltage In the case of a VCCO voltage of 3 3V the VCCOPT voltage is not needed If the power supply device is a PWR3 power module its VCCOPT output may be used for arbitrary purposes e g as a 5V power supply 3 1 2 Reference Voltages The FPGAs have eight I O banks which must be supplied with different reference voltages depending on the used I O standard Usually you do not need more than two different I O standards at one time For convenience two different reference voltages are generated on the board derived from VCCINT using trim potentiometers In conjunction with the PWR3 power module the reference voltages should be taken from the PWR3 This way you can operate all eight banks differently R56 _ VREFO onboard R55 VREF1 onboard Table 3 Trim potentiometer for internal reference voltages The internal reference voltages can be monitored at the connectors J110 VREFO and J111 VREF1 respectively Connect a voltmeter to the appropriate port while adjusting the potentiometer ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 15 47 The choice of a reference voltage source is done using jumpers To choose an
25. E User Manual 3 47 Manual Version EVALXC2S Version 1 0 September 2000 EVALXCV Version 1 0 September 2000 EVALXCVE Version 1 0 September 2000 This manual describes the technical properties and the usage of the following products 2 5V Versions EVALXCV HQ240 Version 1 0 September 2000 with XCV50 8 00 EVALXC2S PQ208 Version 1 0 September 2000 with 2550 25200 1 8V Versions EVALXCVE HQ240 Version 1 0 September 2000 with 50E 1000E FPGA ErSt Electronic GmbH 2000 The ErSt Electronic GmbH reserves the right to make changes and improvements of the product without notice Important Note The EVALXC2S XCV XCVE board module series has been designed and tested exclusively for the usage as a development tool In particular strong electromagnetic radiation may be produced ErSt Electronic GmbH does not undertake any liability for damages that may result from an improper use of this product ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 4 47 Notational Conventions 1 Names of active low signals are marked with a trailing or start with x e g CS or XCS 2 When used to describe signal voltage levels 0 means low voltage 1 means high voltage 3 Table and figure references are printed in an italic font 4 Signal names within a sentence are printed in an italic font Abbreviations
26. EVALXC2S XCV XCVE User Manual Ae Board Module For Xilinx LL IIR NT mon ranqa om meer TTG gt ee Sidi rh LE F ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXC2S XCV XCVE User Manual ErSt Electronic GmbH Aeschstrasse 171 Phone CH 8123 Ebmatingen Fax Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALX2S XCV XCV
27. NT 56 148 96 L38N 17 L59P 57 L48N 97 VREF_L38P 18 L59N 58 98 GND 19 107 59 GND 99 L37N 20 L58P 60 100 L37P 21 L58N 61 101 VREF10 4 22 GND 62 2 102 L36N 23 VREF_L57P 163 147 103 L36P 24 57 64 L47P 104 VCCINT 25 65 L46N 105 126 VREF 7 66 VREF L46P 106 GND 27 6 67 145 107 135 28 156 68 145 108 VREF L35P 29 GND 69 GND 109 VREF610_4 30 70 VREF 144 110 L34N 31 106 711 L44P 111 VREF L34P 32 VCCINT 72 VREF610 5 112 GND 33 VREF_L55P 73 VREF_L43N 113 L33N 34 L55N 74 L43P 114 L33P 35 154 75 GND 115 VREF_4 36 VREF 154 76 116 VCCO 37 GND 77 117 L32N 38 L53P 78 142 118 2 39 153 79 _L42P 119 GND ErSt Electronic GmbH Aeschstrasse 171 Phone CH 8123 Ebmatingen Fax Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALX2S XCV XCVE User Manual 45 47 120 DONE 162 L19N 204 GND 121
28. SelectRAM Spartan ll XAPP134 Synthesizable High Performance SDRAM Controller XAPP136 Synthesizable 200 MHz ZBT SRAM Interface XAPP142 Using Xilinx Programmable Logic with High Speed Printers XAPP169 MP3 NG A Next Generation Consumer Platform XAPP173 Using Block SelectRAM Memory in FPGAs XAPP174 Using Delay Locked Loops Spartan II FPGAs XAPP175 High Speed FIFOs In 5 FPGAs 176 Spartan Il FPGA Family Configuration and Readback 177 5 Family I V Curves for Various Output Options XAPP178 Configuring Spartan Il FPGAs from Parallel EPROMs XAPP179 Using Selectl O Interfaces in 5 FPGAs XAPP200 Synthesizable 1 6 Gbytes s DDR SDRAM Controller XAPP211 Pseudo Random Noise Generators Using the SRL Macro Data Book VirtexTM 2 5V Field Programmable Gate Arrays Virtex E 1 8V Field Programmable Gate Arrays Datasheet Spartan ll Family FPGAs XC2S00 ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 39 47 5 Appendix A FPGA Pin Assignments This appendix lists the FPGA pin assignments of devices compatible with the board module The naming corresponds to the one in the Xilinx data sheet as far as possible e Active low signals are marked with a at the end of the name e For Spartan ll and Virtex devices a general I O signal is denoted with I
29. Vo 169 10 1109 vo vREF200 30 10 170 10 1110 10 31 VO VREF 171 vo 111 1 VREF 32 GND 72 GND 1112 33 VO 73 VO VREF 1113 10 134 VO 174 10 1114 vo 100 135 vo 175 10 1115 06 36 vo 76 VCCINT 116 GND 137 10 77 GCK1 117 VCCO 38 VCCINT 78 118 VCCINT 39 VCCO J 79 GND 119 D5 J ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 41 47 1120 IOo 152 IO VREF200 184 VCCO 1121 0 153 DO DIN 185 GCK3 122 154 BUSY DOUT 186 123 155 CCLK 187 124 GND 156 188 10 125 VREF 157 189 VREF 126 D4 158 GND 190 GND 127 VO 159 TDI 191 128 160 cs 192 129 IO TRDY 161 WR 193 130 VCCO 162 200 1194 10 131 GND 163 195 132 IRDY 164 1 O_VREF 196 VCCINT 133 165 197 134 166 198 GND 135 D3 167 VO 100 199 W O 136 1 VREF 168 200 WO
30. WR3 Voltage supervisor with reset button Two separate crystal oscillators with sockets DIL8 or DIL14 Jumpers to select between internal and external clock sources Four SMB connectors next to the FPGA for feeding high frequency clocks Two header connectors two rows with 50 pins each for I Os clocks and control signals Two header connectors one row with 50 pins each for supply and reference voltages from power module Four ground clips Two user buttons Eight position DIP switch Display with eight LEDs Done LED Power LEDs Mode jumpers M1 M2 Daisy chain configuration with other board modules possible Several boards may be connected to form a stack Board size 100mm x 150mm 2 2 Applications 9 9 9 9 9 9 9 ASIC Emulation Error monitoring and analysis Digital PLL circuits PWM controller Adaptive digital filters Signal multiplexers Stimuli generators High speed encoder decoder Memory controller Interface controller ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual ErSt Electronic GmbH 10 47 Aeschstrasse 171 Phone CH 8123 Ebmatingen Fax Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALX2S XCV XCVE User Manual 11 47 2 3 Function Description The board module EVALXC2S XCV XCVE is equipped with a member of the Xilinx Spartan ll Virtex or Virtex E FPG
31. and I O Signals Note When you stack several modules the VREF signals of all modules are connected in parallel Therefore you must use the same I O standard for same banks on each module The tables on the following pages show the connections of the FPGA pins to the header connectors ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 33 47 3 10 2 Signal Assignment to Connector ST4C The following table shows the assignment of the FPGA pins to the ST4C connector pins 9 9 8 Sc 8 S c 5 Signal sa 9 SignalName 2 o gt o o gt VREF_L43N 101 62 73 VREF L54N 126 36 VREF610 5 102 61 72 L54P 127 31 35 L44P 103 60 71 L55N 128 30 34 VREF_L44N 104 59 70 VREF L55P 129 29 33 L45P 105 58 68 lO 6 130 27 31 1454 106 57 67 L56N 131 24 28 VREF_L46P 107 66 L56P 132 23 27 L46N 108 65 VREF7 133 22 26 L47P 109 64 157 134 21 LN 110 63 VREF_L57P 135 20 23 L48N 11 57 L58N 136 18 21 L48P 112 46 56 L58P 137 17 20 VREF 6 113 49 54 10 7 138 16 19 L49N 114 48 53 L59N 139 15 18 L49P 115 47 52 L59P 140
32. ated signals which are used as clock and configuration signals You can not change the function of these signals by any FPGA configuration GCKO_ext _ 52 92 over J26 1 2 1 54 89 over J27 1 2 GCK2 et 56 210 over J28 GCK3 ext 58 213 over J29 TK 69 _ 239 TS 70 _ 2 DUP 76 _ N A goes to pin 1 of J25 DDOWN 77 N A goes to pin 4 of J25 Table 32 Dedicated signals on connector ST4B 3 11 Stack Extension When several board modules are stacked the signal direction of I O pins of different levels must be chosen very carefully Short circuits between the FPGAs may result in damages or shortens their life Not configured pins of the FPGA are in a high impedance state During the assembly of the stack you should pay attention to the fact that the pins of one module are aligned exactly with the holes of the sockets of the other module A good possibility to accomplish this is the usage of two pieces of a prototyping board Each of these pieces should have three rows with 50 holes Before the assembly these pieces are sled up to the ends of the connector pins Thereby the pin ends keep their positions To disassemble a stack we recommend the usage of pliers that are used to remove locking rings The claws of the pliers should be covered with plastic or rubber tubes to prevent damages on the boards The modules are then separated easily by repeated application of gen
33. ch a reset pulse is also generated when you press the reset button An eight position DIP switch is available for user specific applications In addition there are three push buttons One of them is intended primarily for use as a reset button and is connected to the voltage supervisor circuit The other two buttons are available for arbitrary purposes A row with eight LEDs may function as a display for status and error messages You may disconnect these LEDs from the I O signals by means of jumpers This is especially useful if you stack several boards and do not want to have the LEDs connected in parallel ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 13 47 3 Technical Information This chapter gives a detailed description of the technical details of the board Please consult the schematic diagrams where you find the components who s designators are mentioned in the text 3 1 Power Supply Due to the 0 18 0 22um process the FPGA works with an internal supply voltage VCCINT of 1 8 2 5V and an output driver voltage VCCO of up to max 3 3V Depending on the chosen I O standard VCCO can be 1 5V 2 5V or 3 3V All inputs are 5V compatible Other devices on the board crystal oscillators and SCPs need a supply voltage of 3 3V This voltage can be derived via a jumper from VCCO if an appropriate I O standard is used i e one
34. ert U6 only In order to use these devices as the source of serial configuration data the following jumper settings apply Js2 PROMSel 23 Table 9 Selecting the XC1704 PROMs as serial configuration data source 3 2 1 2 In System Programmable PROMs The two ISP PROMs U1 and U2 both in VQ44 package of the XC1800 family are optional Depending on the size of the FPGA only one or both of them are needed These devices are programmable many times over the JTAG port but work otherwise the same as the XC1700 family If no ISP PROMs are present the bypass resistor R61 0 Q connects the JTAG data input directly with the FPGA If only one if the ISP PROMS is used the resistor R29 0 bypasses the second one The jumper settings to use these devices as the source of configuration data are as follows Js2 PROMSel 1 2 Table 10 Selecting the XC1804 ISP PROMs as serial configuration data source ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 19 47 You can program the devices via the JTAG port J5 TDI of U1 is connected directly with the corresponding pin of J5 U2 is chained with U1 i e TDI of U2 is connected with TDO of U1 The pin assignment of the JTAG port is listed in Table 11 1 TMS 2 TDI 3 TDO 4 5 GND 6 3 3V Table 11 JTAG port pin assignment 3 2
35. ever you may use the DLLs of the FPGA to produce the system clock When you feed the clock from J17 GCK2 you have the option to terminate the line with resistor R62 at the RAM R51 at the FPGA or both You may put the RAM into Linear Burst Mode by inserting J122 The following table summarizes what has been described above Option Action to activate option True synchronous clock for both Feed external clock J17 and remove FPGA and RAM jumper J124 FPGA output drives RAM clock anylnsert jumper J124 and configure the clock drives FPGA FPGA to put out the RAM clock on pin 138 for Spartan ll or pin 159 for Virtex E Terminate GCK2 clock line at the Solder R51 to the bottom of the board FPGA Terminate the GCK2 clock line at Solder R62 to the bottom of the board jthe RAM Running RAM in linear burst mode Insert jumper J122 Table 28 Options for running the RAM and their activation ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 32 47 3 10 Signals on Header Connectors 3 10 1 Signal Overview All general I O signals of the FPGA are routed to header connectors This includes all the VREF pins also If you want to operate a bank with an I O standard that needs a reference voltage you must connect all VREF pins of that bank to the appropriate reference voltage see 3 8 Reference
36. he jumper settings to use the XChecker port are as follows J32 PROM Sel Removed neither 1 2 nor 2 3 connected Table 13 Jumper settings for XChecker configuration The pin assignments of the XChecker port connector are listed in the following table Table 14 XChecker port pin assignment 3 2 3 SelectMAP Mode The SelectMAP mode is the fastest configuration option Byte serial data is written into the FPGA with a BUSY flag controlling the flow of data An external data source provides a byte stream CCLK a Chip Select CS signal and a Write signal WRITE If BUSY is asserted High by the FPGA the data must be held until BUSY goes Low Data can also be read using the Select MAP mode If WRITE is not asserted configuration data is read out of the FPGA as part of a readback operation The SelectMAP mode is selected by the following jumper settings Table 15 SelectMAP mode selection ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 21 47 The byte serial data is fed from an external source to the SelectMAP port J6 using the following pin assignments PinofSelectMAP port J6 Signal Name 1 DO 2 Di 3 D2 4 D3 5 D4 6 D5 7 06 8 07 9 ____BUSY DOUT 10 WRITE 11 CS 12 GND Table 16 SelectMAP por
37. internal reference voltage you must set the jumpers according to the following table 0 J102 1 2 1 4108 1 2 2 4104 1 2 3 4105 1 2 4 J106 2 3 5 107 2 3 6 J108 2 3 7 J109 2 3 Table 4 Choosing an internal reference voltage When an external reference voltage is used a dedicated reference voltage can be assigned to each bank The jumper settings are listed in Table 5 0 J101 BENE 2 1 4103 23 2 2 4104 3 J105 2 3 u 4 J106 1 2 5 J107 UR 6 J108 2 7 4109 Table 5 Choosing an external reference voltage ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 16 47 3 1 3 Output Driver Supply Voltage You can connect each of the eight I O bank s output driver supply to the VCCO voltage individually To do this set the jumpers J114 to J121 according to the following table Table 6 Connecting the output driver voltage The VCCO voltage comes from the power module and can be selected to be 1 5V 2 5V 3 3V If you use an I O standard that does not require an output driver voltage just remove the corresponding jumper If you need two or three different output driver voltages at the same time you can do this be removing the appropriate jumper and using one of the jumper pins to
38. onnections The configuration bit streams are then fed to the lowest layer SCP or XChecker ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 23 47 3 3 Clock All four clock signals GCKO to are routed to header connectors GCKO and GCK1 may get the clock signal either from an internal crystal oscillator or from an external source see Table 19 J26 GCK0 427 GCK1 Source GCK1 Source 2 3 2 3 internal U3 internal U4 2 3 1 2 internal U3 external ST4B 54 1 2 2 3 external ST4B 52 internal U4 1 2 1 2 external ST4B 52 external ST4B 54 Table 19 Choice of the clock sources 3 3 1 External Clock The assignment of the clock signals on the header connectors is listed in 1 FPGA pins for Spartan ll devices are put in parenthesis Table 20 There is also the possibility to feed the clock via a SMB connector mounted next to the FPGA This is the preferred method at high clock frequencies Direct Clock Termination __ST4B _Connector SMB _ Resistor GCKO 52 92 80 415 GCKO R49 GCK1 54 89 77 J16 GCK1 R50 GoK2 56 210 182 J17 GCK2 R51 GCK3 58 213 185 J18 GCK3 R52 FPGA pins for Spartan ll devices are put in parenthesis Table 20 External clock signals and termination resistors 3 3 1 1 Termination Resistors All clock signal
39. out Pullups Master Serial Yes Yes Yes Out 1 Yes Boundary San Yes 1 No No Select MAP _ _ Ye In 8 N No Slave Serial 07 7 l 1 N No Master Serial Yes Yes Out 1 Yes Yes Boundary Scan Yes Yes 1 No Yes Select MAP Yes Ye In 8 No Yes Slave Serial Yes In 1 No Yes Table 7 Setting the configuration modes 3 2 1 Master Serial Mode In master serial mode the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit serial data to the DIN input The FPGA accepts this data on each rising CCLK edge After the FPGA has been loaded the data for the next device in a daisy chain is presented on the DOUT pin after the rising CCLK edge The preamble is also forwarded to other devices in the daisy chain SPROM RESET pin is driven by INIT and CE input is driven by DONE ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 18 47 The master serial mode is selected by the following jumper settings Table 8 Master serial mode selection 3 2 1 1 One Time Programmable PROMs Two sockets for XC1704L devices in a PLCC44 package are available U6 is the first device in the chain The CEO output of the first device enables the second device after all of its contents has been put out If your particular FPGA only needs one PROM to hold the configuration bit stream ins
40. pers Aeschstrasse 171 Phone CH 8123 Ebmatingen Fax 41 1 980 61 44 41 1 980 61 30 ErSt Electronic GmbH Internet http www erst ch EVALX2S XCV XCVE User Manual 29 47 Bank Jumper and Signal 435 VREF_L61P 436 VREF 157 437 VREF 160 488 L62N gt gt J39 VREF_7 J40 VREF10_7 J41 VREF610_7 _J42 VREF_L63N VREF_L50N X X X X X X X X X X 444 VREF 151 J45 VREF 155 J46 VREF_L54N 6 J47 VREF610 6 gt gt gt gt gt x lt 48 VREF_6 449 VREF10 6 J50 L54P J52 VREF L44N X X X X X X X X X X J53 VREF_L43N 454 141 J55 VREF_L46P J56 VREF_5 457 VREF610 5 J58 VREF10_5 J60 VREF_L34P J61 VREF 135 J62 VREF L38P 463 VREF L39N 4 J64 VREF 4 E 465 VREF10_4 466 VREF610 4 J67 L38N ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 30 47 Bank Jumper and Signal J69 VREF_L28N J70 VREF_L27N J71 VREF_L24N J72 VREF_L30P gt 473 VREF_3 474 VREF10 3 J75 VREF610 3 7277 VREF_L21P X X X X X X X X X X J78 VREF_L18P J79 VREF L17P
41. re stacked In this case only U3 may be used in a PLL loop and J31 as well as the loop filter component R53 should be removed 3 4 Reset and Voltage Supervision U5 works as a reset and voltage supervision circuit A functional reset can be issued at any time by pressing the push button SW2 The button is connected to the voltage supervisor circuit U5 which in turn generates a reset pulse on BUSY DOUT FPGA pin 178 A reset pulse is also generated whenever VCCINT drops below a predefined threshold of 2 2V Spartan ll Virtex or 1 7V Virtex E and on power up The pulse duration is approximately 2ms You can select the polarity of the reset pulse with jumper J23 The settings are listed in Table 22 ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 25 47 1 2 Active Low 2 3 Active High Table 22 Reset pulse polarity selection Note A manual reset initializes the internal circuits of the FPGA registers counters finite state machines etc and must be implemented in the design appropriately There is no dedicated reset pin on the FPGA 3 5 User Buttons Two user buttons SW3 and SW4 are available for arbitrary purposes A pressed button ties the connected FPGA pin to ground while the pin is pulled to VCCINT if the button is released Button Signal Name Spartan l Pin Virtex Pin SW3 XWRITE 161
42. rnet http www erst ch EVALX2S XCV XCVE User Manual 40 47 5 2 Spartan ll Devices in PQ 208 Package Pin Description 40 GND 80 1 GND 41 10 81 10 2 TMS 42 Vo vREF100 82 10 86 vo 143 VO 183 10 4 vo vREF200 44 vo 84 VO VREF 5 O 45 VO VREF 85 GND 6 1 VREF 46 10 86 vo vo 47 vo vREF200 187 10 18 NO 48 vo 8 vo 9 vo VREF100 44 vo 89 vo 10 Vo 50 Mt 90 vo 11 GND 51 GND 91 VCCINT 2 VCCO 52 0 92 VCCO 13 VCCINT 53 VCCO 93 GND 14 1O 54 2 194 10 15 10 55 PWDN 95 vREF100 16 vo 56 STATUS 96 vo 17 57 I O 200 97 10 18 TO 58 10 98 IO VREF 19 GND 59 VREF 99 1 0 20 vo 60 100 vo vREF200 231 VO VREF 161 10 1101 22 10 62 VREF100 1102 23 163 VO 103 GND 24 VO IRDY 64 GND 104 DONE 25 GND 165 105 52 vCCO 66 VCCINT 106 PROGRAM 27 VO TRDY 167 10 107 Inn 28 68 10 108 D7 29
43. s may be terminated with resistors R49 to R52 These are connected immediately from the FPGA pin to ground These resistors form a parallel termination The values of the resistors should match the impedance of the circuit board trace having a nominal value of 100 Ohms Please consider the maximal output current capability of the clock source The resistors SMD size 0805 can be soldered to the board directly beneath the FPGA on the bottom side of the PCB ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 24 47 3 3 2 Internal Clock Crystal Oscillators Since the clock frequency depends strongly on the application the oscillators must be exchangeable The oscillators socket can hold DIL 8 or DIL 14 packages Pin 1 is common for both types of packages 3 3 2 1 VCXO with Feedback Loop Oscillators of the VCXO type need a control signal at pin 1 Uc To get a closed feedback loop this signal must be connected via FPGA to Usu You have the possibility to build an RC loop filter be mounting R54 C41 and R53 C42 In this case jumpers J30 and J31 remain open Table 21 Crystal oscillator control signals and usage Note The jumper J31 UC VCXO must be inserted to connect pin 1 of U4 with signal L43P if a feedback signal for a VCXO is needed Beware in mind that the L43P signals are connected in parallel if several boards a
44. s possible you can connect every possible VREF pin individually to a reference voltage by inserting a jumper Table 26 gives an overview of the jumper groupings and assignments to the I O banks In Table 27the correspondence of each VREF jumper to the individual devices is listed A jumper belongs to a certain device if there is a cross in the device column No cross in the device column means that you can use the corresponding FPGA pin for general I O ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 28 47 J98 VREF610_0 Bank _Virtex and Spartan Virtex only Spartan only J35 VREF L61P vis 7 486 VREF L57P i ss T J37 VREF_160P J42 VREF L63N 245 VREF 155 62 243 VREF_L5ON 347 EE J50 154 J44 VREF_L51N BEL 449 10 6 452 VREF_L44N a 5 453 VREF 143 ie HEN J54 VREF_L41P 2 7162 VREF L38P 4 460 VREF_L34P o aa J67 L38N J61 VREF_L35P J68 L33N J66 VREF610 4 J69 VREF L28N o 3 J70 VREF L27N J76 L29N J71 VREF_L24N J75 VREF610 3 J77 VREF_L21P 1 2 178 VREF L18P J84 L16P J79 VREF L17P 2 485 VREF_L11P i ea 1 J86 VREF_L10P J92 L12P J87 VREF_L7P J91 VREF610 1 J95 VREF L5N o 498 VREF L2N on J100 15 J94 VREF_LOP J101 LAP J99 VREF610 Table 26 Grouping bank and signal assignment of VREF jum
45. se 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 7 47 Tables Table 1 Pin assignment on the power header connectors ST6 and ST7 13 Table 2 Derivation of the 3 3V supply voltage a a s 14 Table 3 Trim potentiometer for internal reference voltages 14 Table 4 Choosing an internal reference 9 99 15 Table 5 Choosing an external reference voltage eee 15 Table 6 Connecting the output driver voltage eene 16 Table 7 Setting the configuration modes eene 17 Table 8 Master serial mode selection eese 18 Table 9 Selecting the XC1704 PROMs as serial configuration data source 18 Table 10 Selecting the XC1804 ISP PROMs as serial configuration data source 18 Table 11 JTAG port pin assignment eene nennen 19 Table 12 Slave serial mode selection eese 19 Table 13 Jumper settings for XChecker configuration 20 Table 14 XChecker port pin assignment cesses eene 20 Table 15 SelectMAP mode selection eene 20 Table 16 SelectMAP port pin assignment esses 21 Table 17 Boundary scan mode selection eene 21 Table 18 Pin assignment of daisy chain connector J25
46. se 171 Phone 41 198061 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 8 47 1 Introduction This manual describes the specific properties of the board module like power supply reference voltages FPGA configuration clocks reset LEDs DIP switches and I O signals Please take information about the FPGA from the Xilinx literature see chapter 4 Literature Online information can be found on the Xilinx websites http www xilinx com and http www support xilinx com Information about new products and new developments can be found on the ErSt Electronic Website http www erst ch If you have questions you may write to the following email address info erst ch We will answer as soon as possible usually within one or two days ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 9 47 2 Overview 2 1 9 9 o 9 9 9 9 9 9 9 9 Key Features Download Master Serial Mode SPROM with socket Slave Serial Mode XChecker header connector Boundary Scan Mode JTAG header connector SelectMAP Mode header connector Configuration from onboard SCPs ISP SCPs programmable via JTAG sockets for OTP SCPs bank reference voltages Two adjustable VREFs for 8 I O banks selectable via jumpers or eight external voltages e g from power module P
47. ssssssssssesssssssssssssssssssss 13 SARL 33V SUPDPIY 14 311 2 Reference Voltages 14 3 1 3 Output Driver Supply 16 3 1 4 Mounting the PWR3 Power Module 16 3 2 FPGA Configuration 17 321 Master Serial Mode enter 17 3 2 1 1 One Time Programmable PROMSs eene 18 3 2 1 2 System Programmable 5 0 200222 18 32 2 Slave Serial 19 3 2 2 1 Configuration via XChecker Port 19 3 23 seleciMAP Mode nee ie inde La 20 3 2 4 Boundary Scan Mode us E 21 3 25 Daisy Cham ine UU ERBEN 21 33 ich ar 23 3 3 _ External erlernen 23 3 3 1 1 Termination Resistors 24000 23 3 3 2 Internal Clock Crystal Oscillators 24 3 3 2 1 VCXO with Feedback Loop eee 24 3 4 Reset and Voltage Supervision 24 33 User Bill 25 3 6 LEDS ecc 25 3 7 Eight Position DIP Switch 26 3 8 Reference and Signals 27 ErSt Electronic GmbH Aeschstrasse 171 Phone 41 1 980 61 44
48. t pin assignment 3 2 4 Boundary Scan Mode In the boundary scan mode no non dedicated pins are required configuration being done entirely through the IEEE 1149 1 Test Access Port Configuration and readback is always available The boundary scan mode simply locks out the other modes The boundary scan mode is selected by the following jumper settings Table 17 Boundary scan mode selection The pin assignment of the JTAG port 45 is listed in Table 11 3 2 5 Daisy Chain If several board modules are stacked together there is the possibility to configure the whole stack at once To do this the individual layers must be connected in form of a daisy chain This is accomplished by connecting appropriate pins of connector J25 see Table 18 externally ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 22 47 1 DUP 2 3 _ BUSY DOUT 4 DDOWN Table 18 Pin assignment of daisy chain connector J25 Use the following scheme for the external connections dup din dout ddown Figure 2 Wiring of the daisy chain The easiest way to make the connections dup din and dout ddown is to insert a jumper However these connections are only needed if the stack is connected to a main board and if the configuration data comes from the main board If the main board is not used you need only the doui din c
49. tle pressure with the pliers on all four corners ErSt Electronic GmbH Aeschstrasse 171 Phone 441 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALX2S XCV XCVE User Manual 37 47 4 Literature The following list is an excerpt from the Xilinx literature concerning the Virtex FPGA family The corresponding PDF files may be downloaded directly from http www xilinx com apps virtexapp htm http www xilinx com apps sp2app htm or be requested from a Xilinx distributor Application Notes Virtex XAPP243 XAPP242 XAPP241 XAPP240 Devices XAPP237 XAPP235 XAPP234 XAPP233 XAPP232 XAPP231 XAPP230 XAPP217 XAPP215 XAPP214 XAPP212 XAPP211 XAPP210 XAPP208 XAPP205 Memory XAPP204 XAPP203 XAPP202 XAPP201 XAPP200 XAPP158 XAPP157 155 154 ErSt Electronic GmbH Bus LVDS with Virtex E Devices Interfacing to Lara Networks Search Engine using Virtex Devices Virtex EM FIR Filter for Video Applications High Speed Buffered Crossbar Switch Design using Virtex EM Virtex E LVPECL Receivers in Multi Drop Applications Virtex E Package Compatibility Guide Virtex SelectLink Communications Channel Multi channel 622 Mb s LVDS Data Transfer with Virtex E Devices Virtex E LVDS Drivers and Receivers Interface Guidelines Multi Drop LVDS with Virtex E FPGAs The LVDS I O Standard Gold Code Generators in Virtex Devices Design Tips for HDL Implementation

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