Using MC683xx M-bus software to communicate between processor
Contents
1. EXTERNAL REFERENCE DECLARATIONS XREF SCR System Control Reg XREF PBCNT Port B Control Reg XREF PIVR Peripheral Interrupt Vector Reg XREF PICR Peripheral Interrupt Control Reg XREF MADR MBUS Address Reg XREF MFDR MBUS Freq Divider Reg XREF MBCR MBUS Control Reg XREF MBSR MBUS Status Reg XREF MBDR MBUS Data Reg i Constants UVECBASE EQU 100 User Vector Base MBUSVEC EQU UVECBASE D 4 MBUS vector location MBUSHAN EQU 15000 MBUS Interrupt Handler location S307_AD EQU 66 Slave 68307 MBus Address DRXCNT EQU 3 Data RECEIVE COUNT 2 1 Dummy ATXCNT EQU 1 Address TRANSMIT COUNT DTXCNT EQU 2 Data TRANSMIT COUNT Main Program es SSS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS ORG 10000 RANDOM LOCATION FOR ASSEMBLY AND L FFFFFEFF SCR Clear SCR bit 8 MBUS CLock Active MOVE B 40 PIVR Vector 40 Vector address 100 OR W 000D PICR MBUS Interrupt level 5 MOVE L MBUSHAN MBUSVEC Set up MBUS Interrupt Handler OR W 3 0003 PBCNT Enable MBUS Lines BSR INIT MBM Initialise MBus as master WRITE TO SLAVE 68307 MBus Write Chip Addr2. m Tx Slave Rx 1st data Rx 2nd data No Stop Master Activity Address byte Ack Block Slave to Tx M bus Rx Slave Tx 1st data Tx 2nd data Slave Activity Address byte byte Figure 3b Summary of M bus Activity for the Master Receive Block For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Listing 1 M bus Master Software CKCkckckckckckck ck kckckck kckckckck ck kckckckckckckckckckckckckck KA KA KA KA KA KA KA KARA AAA KA KA KA KA KARA FREESCALE 68307 IMBP TEST BOARD MBUS xX MODULE MBM_INT SRC DATE 8 4 94 Developed by Freescale m HI END Applications K x East Kilbride j NOTES Master MBUS Routine using interrupts for a Master Slave Test id The number of bytes transmitted and received is completely controlled by the master i e When the slave is receiving data it acknowledges all the time and the master dictates the number of bytes to transfer When the slave is transmitting the master bi receiver acknowledges dictate whether the slave is to send further bytes or not i The Master 1 Writes out the slave chip address and 2 slave data bytes 2 Writes out the slave chip address and reads 2 slave data bytes 3 Verifies the data read back against that originally sent
3. SLAVE OPERATION NOT IMPLEMENTED KOK ROK ROK ck ckck ck ck RARA ckck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ck KR KAR ck ck ck ckck ck ck ck ck ckck ck ck KKK ck ck ck KKK KK KKK KEK Buffers and Variables ck ck ck ck ck ck ke ke ke ce ke ce ke ce 0e ce ke ce 0k ce 0e ce ke ce ke ck ce ce ce ce ce ce ke ce ce ce ce ck ce ce ce ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kc k ko ko v V WRITE V CHIPAD V DRXCNT V ATXCNT V DTXCNT S307 DATA AN496 D DC B 1 DC B 307 AD DC B DRXCNT DC B ATXCNT DC B DTXCNT DC B SAA 55 END Slave write True Chip Address variable Slave 307 Add Set up variables Data Receive Count Addr Transmit Count Data Transmit Count Chip 1 Data For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Listing 2 M bus Slave Software LELLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLLLLLLLLE FREESCALE 68307 IMBP TEST BOARD MBUS 5 x MODULE MBS INT SRC DATE 8 4 94 Developed by Freescale HI END Applications E East Kilbride NOTES ud Slave MBUS Routine using interrupts for a Master Slave Test The number of bytes transmitted and received is completely i controlled by the master i e When the slave is receiving data it acknowledges all the time and the master dictate
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5. KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KK KKK KKK KKK KKK KKK KKK KKK KEK STX_DATA BIST 0 MBSR CHECK ACK FROM RECEIVER BEQ NXT_TX IF ACK THEN TX NEXT DATA BYTE AND B SEF MBCR TX complete so swap to Rx MOVE B MBDR DO Dummy read to free bus SCL BRA END_SLAVE Finish and await Master NXT_TX MOVE B A0 MBDR Tx next data byte BRA END_SLAVE EXIT KOK ROK RK RK RK RK RK RK RK KK RK KK RK KK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KK KKK KKK KK Post Slave data Receive Control KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK SRX_DATA MOVE B MBDR DO READ DATA MOVE B DO A0 Store data in next data buffer location END SLAVE MOVE L A7 D1 POP D1 REGISTER FROM STACK MOVE L A7 D0 POP DO REGISTER FROM STACK RTE KOK RK RK RK RK RK RK RK RK KK RK RK KK KK RK KK KK KK KK k k KK KK KK KK k k KK KK k k k KKK KKK KKK KKK KK KKK KKK KKK Buffers and Variables KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK RARA KK KKK KK KKK DATABUF DS B 0 Slave data buffer between Rx and Tx END AN496 D For More Information On This Product Go to www freescale com 11 Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler
6. at around the same time The built in M bus transfer mechanism means it does not matter in which order they are serviced The master and slave interrupt service order used in the flowcharts of Figures 2a and 3a is purely for demonstration purposes The interrupt handlers are shown such that the data flow is always from transmitter to receiver It should be understood that the master and slave interrupt handlers are happening at the same time as are the transmit and receive of a particular byte Transfer Blocks The master M bus controls the number of data bytes within each transmit receive block Observe Figures 2b and 3b which give a summary of the activity on the M bus during the master transmit and master receive blocks respectively When the master is transmitting data master transmit block the slave acknowledges all bytes received and the master decides when the transfer is completed by setting a STOP condition see Figure 2b When the master is AN496 D For More Information On This Product Go to www freescale com 3 Freescale Semiconductor Inc receiving data master receive block it decides when the transfer is complete by stopping acknowledges on the last received byte thereby stopping the slave transmitting and setting a STOP condition see Figure 3b Software Implementation The software used is shown in Software listing 1 and 2 Only the method of enabling the M bus and interrupts at the start of the software listings is
7. busy KOK ROK RK RK RK RK RK RK RK KK RK RK KK RK RK KK KK KK KK KK KK KK KK KK KK KKK KKK KK KK KKK KKK KKK KKK KKK KKK KK POST BYTE TRANSMISSION RECEPTION SOFTWARE RESPONSE KOK KK RK RK RK RK RK RK RK RK RK RK RK KK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KKK KKK KK KK ORG ISR BCLR MOVE MOVE MOVE MOVE BIST BEQ BIST BEQ EE Ee MBUSHA 1 MBSR DO AT D1 AT 4 MBCR MASTRX Start of Interrupt Handler CLEAR THE MIF FLAG PUSH D0 REGISTER TO STACK PUSH D1 REGISTER TO STACK Clear general data reg Clear general data reg CHECK THE MSTA FLAG BRANCH IF SLAVE MODE CHECK THE MODE FLAG BRANCH IF RECEIVE MODE KOK KK RK RK RK RK RK RK RK RK RK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KK KKK KKK Master TRANSMIT caused Interrupt KOK KK RK RK RK RK RK RK RK KK RK KK KK RK RK KK KK KK KK KK KK RK KK KK KK KK KK KKK KKK KK KKK KKK KKK KKK KKK KKK MASTX BIST BNE TXADDR MOVE BEQ TXDATA MOVE BEQ EQ WERENWE RA ENDMASTX BCLR SETMASTRX BCLR BCLR BSET SUBO OVE UBO OVE B 0 MBSR ENDMASTX V_ATXCNT D1 TXDATA 1 V_ATXCNT V_WRITE D1 SETMASTRX V_DTXCNT D1 ENDMASTX 1 V_DTXCNT A0 MBDR END 5 MBCR END 3 MBC 4 MBC 5 MBC AM W CHECK ACK FROM RECEIVER F NO ACK END TRANSMISSION CHECK Address TX COUNT f address already Complete go to data Decrement A
8. specific to the MC68307 Thereafter the code is generic for any 683xx device with an M bus module The 683xx M bus slave software should always be set running before the master software such that the prospective slave is initialised as a receiver before the master transmits the slave address The software uses interrupts to control the byte transfers within each block The M bus master starts the transfer by transmitting the slave address Thereafter interrupts are generated on both the master and slave M bus to control the test The M bus hardware protocol does not care which order the interrupts are serviced by the master transmitter or receiver or slave transmitter or receiver at the end of each byte Consider that the master is in charge of generating the SCL clocks to shift data out the transmitter and into the receiver when a transmit receive is initiated by writing reading the M bus data register respectively However the clocks do not start until the slave has released the clock line on the bus by making its corresponding read write of its M bus data register Therefore both 683xx M bus master and slave interrupts have to initiate the next data transfer The slave frequency can be programmed as greater or less than that of the master M bus implements a clock synchronisation mechanism such that the clock with the shortest high time and longest low time dictates the open drain clock For example if the programmed slave M bus clock frequ
9. the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal
10. transmitter dictates there are no more bytes to send Indeed both master and slave can be charged with controlling the transfer block For instance the software protocol may transfer a byte count as part of the communication or use a fixed number of transfer bytes every time For the best choice in software control transfers can adopt either a status polling method or interrupts at the end of each byte The interrupt option is most commonly used to minimise the time the processor is tied up with the transfers overhead If enabled the interrupts are generated on the completion of each 9 bits 8 data bits plus an acknowledge M bus Master Mode Operation Using interrupts to transmit data to the addressed slave is straightforward During the M bus initialisation the 683xx M bus sets up master transmitter mode sets the M bus frequency enables interrupts provides an interrupt handler and STARTS the block transfer The targeted slave address with lsb 1 for slave receiver mode is transmitted by writing to the M bus data register On each subsequent end of byte interrupt further data bytes are transmitted by writing data to the M bus data register until the block is complete On the interrupt at the end of the last byte the software STOPs the transfer For receiving from the addressed slave the initialisation is exactly the same Remember that even if receiving the first operation is to transmit the targeted slave address except this time Is
11. Freescale Semiconductor Order this document as AN496 D AN496 D Using MC683xx M bus software to communicate between processor systems James Gilbert Applications Group High Performance Products Freescale Semiconductor Inc East Kilbride Scotland Introduction M bus is an I2C compatible bus interface used in the 683xx family It is a serial interface comprising two open drain bidirectional signals namely serial clock SCL and serial data SDA Multiple devices can be connected directly to these open drain lines and indeed this is good reason for the widespread adoption of the bus as an efficient IC communication method in end systems A typical scenario would consist of a processor with an M bus master controlling the data flow between several slaves such as LCDs real time clocks keypads A D converters and memories Moreover a built in bus collision mechanism supports multiple M bus masters as well as multiple slaves The M bus module of the 683xx is flexible enough to operate as either an M bus master or a slave This application note demonstrates control software for M bus communication between two identical MC68307 systems one configured with an M bus master and the other an M bus slave Only a short piece of initialisation code needs to be changed to make the MC68307 code applicable to other 683xx devices with M bus Overview of M bus Software Transfer Mechanism For full details of M bus features and a complete specific
12. K RK KK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KK KKK KKK KK KKK KKK KK INIT_MBM MOVE MOVE MOVE MOVE MOVE RTS NOTE By not KKK KKK KKK KKK KKK KKK KKK KKK Poll the MBUS BUSY KKK KKK KKK ck ckck KKK KKK KKK KKK MBBUSY BIST BNE RTS WWwWu writing 2700 SR 0 MBSR S0C MFDR 00 MBCR 80 MBCR 5 MBSR MBBUSY DISABLE INTERRUPTS BY SETTING TO LEVEL 7 CLEAR INTERRUPT PEND ARBITRATION LOST SET FREQUENCY DISABLE AND RESET MBUS ENABLE MBUS ADR the 68307 MBUS slave address 0 KKK KKK KR KKK KK KK KKK KKK KK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KK KK KK KK KK KK KKK KKK KKK KKK KKK KKK KK KK TEST MBB BIT AND WAIT UNTIL IT IS CLEAR KKK KK RK RK RK RK RK RK KK KK RK RK RK KK RK KK KK KK KK KK KK KK KK KKK KKK KK KK KK KK KKK KKK KKK KKK KKK KKK KK GENERATION FIRST BYTE OF DATA TRANSFER KOK KOK RK RK RK RK RK RK RK RK RK RK RK KK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KKK KKK KKK KEK WRITE1 BIST BNE TXSTART BSET BSET BSET MOVE MOVE MBF REE BIST BEQ RTS B W 5 MBSR WRITE1 4 MBC 5 MBC 6 MBC V_CHIPAD MBDR 2000 SR AHN 5 MBSR MBF REE TEST MBB BIT AND WAIT UNTIL IT IS CLEAR SET TRANSMIT MODE SET MASTER MODE GENERATE START Enable MBUS Interrupts TRANSMIT THE SLAVE CHIP ADDRESS ENABLE INTERRUPTS BY SETTING TO LEVEL 0 TEST MBB BIT If bus is still free wait until
13. KK RK KK KK KK KK KK KK KK KK KKK ckckckckckck KKK KKK KKK KKK KKK KKK KEK INIT_MBS OVE W 2700 SR DISABLE INTERRUPTS BY SETTING TO LEVEL 7 OVE B 0 MBSR CLEAR INTERRUPT PEND ARBITRATION LOST OVE B 10 MFDR Set FREQUENCY OVE B S307_AD MADR Set MBUS slave address OVE B 00 MBCR DISABLE AND RESET MBUS OR B C0 MBCR ENABLE MBUS Ints TXAK OVE W 2300 SR Enable INTS BY SETTING TO LEVEL 3 RIS kkkkxkxkxkkkxkxkkkxkxkkkxkkkkkkkkkkkkkkxkkkkxkkkkkkkkkkkkkkkkkkkkkkxkkkkxkkkkkkkkkkkkkkkkkkkxk Poll the MBUS BUSY KOK OK RK RK ROK RK RK RK RK RK KK KK KK KK RK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KKK KKK KKK KKK KK MBBUSY BIST 5 MBSR TEST MBB BIT BNE MBBUSY AND WAIT UNTIL IT IS CLEAR RTS For More Information On This Product 10 Go to www freescale com Freescale Semiconductor Inc KOK KK RK RK RK RK RK RK RK RK RK RK RK RK RK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KK KK KK KKK KKK KK KKK KKK KK POST BYTE TRANSMISSION RECEPTION SOFTWARE RESPONSE KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK K KK KKK ORG MBUSHAN Start of Interrupt Handler ISR BCLR 1 MBSR CLEAR THE MIF FLAG MOVE L DO AT PUSH DO REGISTER TO STACK MOVE L D1 AT PUSH D1 REGISTER TO STACK MOVE L 0 D0 Clear general data reg MOVE L 0 D1 Clear general data reg Interrupt Counter ADDO L 1 D3 Not used simply monitor BIST 5 MBCR CHECK THE MSTA FLAG BEQ SLAVE BRA
14. NCH IF SLAVE MODE MASTER BRA MASTER Master not implemented so error KOK ROK RK RK RK RK RK RK RK RK RK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KKK KKK SLAVE MOVE B MBSR D6 Read MBSR BIST B 6 D6 Is it slave address byte BEQ SLAVE_DATA If not then data KOK ROK RK RK RK RK RK RK RK KK RK KK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KK KKK KKK KKK KK KKK KKK KKK Addressed as SLAVE KK RK RK RK RK RK RK KK RK KK RK RK KK KK KK KK KK KK KK KK KK KK KK KK KK k k k k KK KK KK KK KK KKK KKK KKK KKK KK KK SLAVE ADD BTST 2 D6 Read SRW to verify slave Tx or Rx BEO NIT SRX If Rx initialise SLAVE receive count INIT STX OR B 10 MBCR Set transmit mode MOVE L DATABUF AO Pointer to data storage buffer MOVE B A0 MBDR First data byte transmit BRA END SLAVE INIT SRX AND B SE7 MBCR Set receive mode and TXAK MOVE L DATABUF AO Pointer to data storage buffer MOVE B BDR DO Start receive via Dummy byte read BRA END_SLAVE KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK K KK KKK Slave Data KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKKK KKK KKK K KKK ko SLAVE_DATA BTST 4 MBCR Read Tx or Rx mode BEQ SRX_DATA KK KK RK RK RK KK RK KK KK RK RK RK RK KK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KKK KKK KK KK Post Slave data Transmit Control KKK KKK KKK KKK KKK KKK KKK KKK KKK
15. ates arbitration lost as the interrupt source The first data byte transmitted by the M bus master is always the targeted slave address with the least significant bit determining whether the slave remains ready to receive or transmit subsequent bytes The addressed slave can then acknowledge the received byte or not depending upon the software protocol and acknowledge capability of the slave devices used Each acknowledge is like a 9th data bit asserted by the receiver as a handshake to successfully transmitted data Freescale Semiconductor Inc 2004 All rights reserved 9 So 2 freescale semiconductor 9 95 1995 All trademarks are recognised Freescale Semiconductor Inc A block transfer comprising a series of data bytes and acknowledges if used follows as commanded by the software protocol The bus remains busy throughout the block precluding all other masters from starting transfers At the end of the block the bus master relinquishes the bus by software placing a STOP condition onto the bus Ultimately the M bus master is responsible for starting and stopping transfers but the number of bytes transferred can be dictated by either the master or slave depending upon the desired software protocol For example a slave may acknowledge all bytes received until it saturates at which point the master STOPs the block transfer Alternatively the slave receiver may acknowledge received bytes until the master
16. ation of the M bus module refer to the MC68307 User Manual For the sake of clarity a brief overview of the software control mechanism is provided here The M bus communication is on a byte wide basis The components of the hardware transfer protocol are a START condition 8 data bits an acknowledge bit and a STOP condition Before starting a communication an M bus master should carry out a software check to ensure the bus is free and therefore all other M bus transfers are complete Thereafter the bus master initiates a transfer by software writing a START condition onto the bus This is an indicator to all connected M bus devices that this master is taking charge of the bus and that the address of the targeted slave is to follow For the 683xx M bus master writing the targeted slave address to the data register initiates the 8 bit transfer MSB first If a system has two or more M bus masters which poll the bus free and start a transfer at the same time then the collision detection arbitration throughout the transfer of the slave address transfer and subsequent data bytes decides which device gets charge of the bus If the 683xx M bus loses arbitration in this way it stops driving data onto the bus to prevent data corruption Furthermore it switches automatically into slave mode pre empting the alternate master addressing it as a slave If interrupts are enabled an interrupt is generated on the completion of that byte and a status bit indic
17. b 0 In the interrupt handler at the end of the slave address transmit byte the transmit mode is changed to receive Then to initiate the first byte receive operation the 683xx M bus master software carries out a dummy read of the data register No sensible data is read at this point but it is the action of this read which starts the data receive At the end of each received byte the interrupt generated is used to read the data register again for valid data and to start the next byte receive This continues until the master receiver STOPs the block transfer The receiver is always responsible for the generation of acknowledges The 683xx M bus receiver can be programmed to generate acknowledges automatically for each byte received if desired Most slave transmitters take an acknowledge from the master receiver to mean that further bytes are desired In fact for some slave transmitters it is necessary for the master receiver to acknowledge all received bytes except the last one to indicate that more data byte transmits are required This is not a requirement of the 683xx M bus slave M bus Slave Mode Operation Many of the principles discussed for the master operation also hold true for the slave 683xx M bus The main differences are that the M bus is no longer controlling the transfer STARTing and STOPping or the provider of the M bus clock but is instead following what the master dictates For slave operation again initialise the M b
18. bus as shown in Figure 1 Both are master mode processor systems each with the MC68307 processor core executing instructions prefetched from ROM This is not to be confused with the master and slave operation of the M bus modules within each processor 68 307 68307 System System Master SCL Slave MBus SDA MBus Figure 1 Hardware Setup Each MC68307 system has 128kB EPROM and 128kB SRAM and runs a debug monitor A complete description of the system hardware is provided in AN490 D Multiple Bus Interfaces using the MC68307 Using the monitor s download facility an M bus control program is downloaded into the SRAM of each board The code allows one system to control its M bus module as a master while the other implements an M bus slave Together the two software programs allow the MC68307 M bus master to write data to the M bus slave and later read it back for verification Software Flow The MC68307 master M bus controls the number of blocks transferred via START and STOP conditions In this example there are only two communication blocks one transmitting data to the slave master transmit block and one receiving data back from the slave for verification master receive block The master slave responsibilities during the master transmit block are outlined in Figure 2a and for the master receive block in Figure 3a On these diagrams note that for a given transfer byte the end of byte interrupts on the master and slave occur
19. ddress Tx Count Check if writing or reading slave f reading set to Master receive CHECK Data TX COUNT F NO MORE DATA THEN STOP BIT Reduce Tx Count Transmit next byte EXIT GENERATE STOP CONDITION EXIT Enable TXAK Set master Receive Mode SET MASTER MODE GENERATE START For More Information On This Product Go to www freescale com Freescale Semiconductor Inc KOK OK OK RK ROK RK RK RK RK RK RK RK RK RK RK RK RK RK RK RK RK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KEK Master RECEIVE KOK OK OK ROK OK RK OK ROK RK RK RK RK RK RK RK RK RK RK KKK RK RK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KK AK MASTRX NOTFIRST LAMAR ENMASR NXMAR READERR END SLAVE SUBO B 1 V_DRXCNT Decrement receive count MOVE B V_DRXCNT D1 CMP B DRXCNT 1 D1 First byte read Check BNE NOTFIRST If not first read and compare as usual MOVE B MBDR DO If first DUMMY read only to start Rx BRA END CMP B 0 D1 BEQ ENMASR LAST BYTE TO BE READ CHECK SUBO B 1 D1 LAST SECOND BYTE TO BE READ CHECK BNE NXMAR NOT LAST ONE OR LAST SECOND SO BRANCH BSET 3 MBCR LAST SECOND DISABLE ACK TRANSMITTING BRA NXMAR BCLR 5 MBCR LAST ONE GENERATE STOP SIGNAL MOVE B MBDR DO READ DATA CMP B A0 D0 COMPARE WITH WRITTEN DATA BEQ END If data as expected o k BRA READERR Else ERROR loop forever MOVE L A7 D1 MOVE L A7 DO RTE NOP BRA SLAVE POP D1 REGISTER FROM STACK POP DO REGISTER FROM STACK
20. ency is less than the master the slave can stretch the clock as necessary The number of transfer and receive blocks and the number of data bytes within each block can be altered in the master software The slave software remains the same throughout If the user desires detailed crosschecks on the software flow interrupt counts for number of bytes transferred or a flag passing mechanisms could be implemented For simplicity this is not used in the example software For More Information On This Product 4 Go to www freescale com Freescale Semiconductor Inc M bus Slave Receiver Activity M bus Master Transmitter Activity Set slave Rx mode Set master Tx mode START block transfer Write slave address to MBDR to initiate address Tx 66 slave is to Rx data so Isb 0 Rx slave address Tx slave address Auto Acknowledge address Interrupt on Slave address match Set Tx Rx mode to Rx Dummy read of MBDR ready Rx 1st data byte Interrupt at end of address Tx Verify Acknowledge Remain in Tx mode Write 1st data byte AA to MBDR to initiate Tx Auto Acknowledge data Interrupt at end of 1st data byte Rx Read 1st byte of valid data from MBDR AA and ready for next Rx Interrupt at end of 1st data byte Tx i Verify Acknowledge Write 2nd data byte 55 to MBDR to initiate Tx Auto Acknowledge data Interrupt at end of 2nd data byte Rx Read 2nd byte of valid data from MBDR 55 and ready for next Rx Inte
21. ess START BSR MBBUSY MOVE B 0 V_DRXCNT MOVE B ATXCNT V_ATXCNT MOVE B DTXCNT V_DTXCNT MOVE B 1 V_WRITE MOVE B S307_AD V_CHIPAD MOVE L S307_DATA AO BSR WRITE1 READ FROM SLAVE 68307 MBus Write Chip Address BSR MBBUSY MOVE B DRXCNT V_DRXCNT MOVE B ATXCNT V_ATXCNT MOVE B 0 V_DTXCNT MOVE B 0 V_WRITE AN496 D and Two bytes of data Poll the MBUS wait till bus free Data RECEIVE COUNT Address TRANSMIT COUNT Data TRANSMIT COUNT Set Write to slave var TRUE Slave 68307 Mbus receiver Address Pointer to stored data for transfer Send out the Chip Address and READ Two bytes of data Poll the MBUS wait till bus free Data RECEIVE COUNT Address TRANSMIT COUNT Data TRANSMIT COUNT Set Write to slave var FALSE For More Information On This Product Go to www freescale com MOVE OR B MOVE MOVE BSR Test Complete BSR FOREVER BRA B B L Freescale Semiconductor Inc S307_AD D6 01 D6 D6 V_CHIPAD S307_DATA AO WRITE1 MBBUSY FOREVER Alter chip address lsb for Slave transmit and write to chip address variable Pointer to data for memory 1 Send out the Chip Address Poll the MBUS wait till bus free Test complete amp passed loop forever KOK KK RK RK RK RK RK ck ckck ck ck ck ck ckck ck ck ckck ck ck ckck ck ck ck KK KK KK KK ck ck ck ck KK KK KK KK KK KK KK KKK KKK KKK KKK KK KKK KKK MBUS SETUP INITIALISATION KK KK RK RK RK RK RK KK KK RK RK R
22. injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part o freescale semiconductor
23. rrupt at end of 2nd data byte Tx Verify Acknowledge STOP block transfer Figure 2a Master Slave Responsibilities for the Master Transmit Block m Tx Slave Master Activity Address Slave to Rx M bus Rx Slave Rx 1st data Rx 2nd data Slave Activity Address byte byte Figure 2b Summary of M bus Activity for the Master Transmit Block AN496 D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M bus Slave Tranmitter Activity M bus Master Receiver Activity soot slave modo Set master Tx mode S TART block transfer Write dave address to MBDR to initate address T x 67 GlavetoRx so Isb 1 Tx slave address Auto Acknowl edge address Interrupt on Slave address match Set TX Rx mode to Tx Write 1st data byte AA to MBDR ready to Tx 4nterrupt at end of address Tx Verify Acknowledge Set Tx Rx mode to Rx Dummy read of MBDR toinitiate Rx of 1st data byte AA Rx data Auto Ac knowledge data Anterrupt at end of 1st data byte Rx Read of MBDR ready to Rx 2nd data byte 55 Tx data Interrupt at end of 1st data byte Tx Verify Acknowledge Write 2nd data byte AA to MBDR toinitiate Tx No Acknowledge dnterrupt at end of 2nd byte Rx STOP block transfer Interrupt at end of 2nd data byte Tx No Acknowledge so end Tx Switch to slave Rx mode ready for next slave address Figure 3a Master Slave Responsibilities for the Master Receive Block
24. s the number of bytes to transfer When the slave is transmitting the master E receiver acknowledges dictate whether the slave is to send further bytes or not Ed The Slave 1 Recognises its slave chip address and receives 2 data bytes E 2 Recognises its slave chip address and transmits the 2 bytes hi EXTERNAL REFERENCE DECLARATIONS XREF SCR System Control Reg XREF PBCNT Port B Control Reg XREF PIVR Peripheral Interrupt Vector Reg XREF PICR Peripheral Interrupt Control Reg XREF MADR MBUS Address Reg XREF MFDR MBUS Freq Divider Reg XREF MBCR MBUS Control Reg XREF MBSR MBUS Status Reg XREF MBDR MBUS Data Reg UVECBASE EQU 100 User Vector Base MBUSVEC EQU UVECBASE D 4 MBUS vector location MBUSHAN EQU 15000 MBUS Interrupt Handler location S307_AD EQU 66 Slave 68307 MBus Address ORG 10000 RANDOM LOCATION FOR ASSEMBLY AND L SFFFFFEFF SCR Clear SCR bit 8 MBUS CLock Active MOVE B 40 PIVR Vector 40 Vector 8 address 100 OR W 000D PICR MBUS Interrupt level 5 MOVE L MBUSHAN MBUSVEC Set up MBUS Interrupt Handler OR W 0003 PBCNT Enable MBUS Lines BSR INIT_MBS Initialise MBus as slave FINISH BRA FINISH Loop forever KOK OK OK OK RK RK RK RK RK RK RK RK RK RK RK RK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KKK KKK KKK KKK MBUS SETUP INITIALISATION KOK OK OK ROK ROK RK OK RK RK RK RK KK RK KK RK
25. us frequency M bus slave address interrupt handler and interrupt enable As the first transfer is always the receipt of the slave address slave receive mode should always be programmed initially All target slave addresses which are transmitted by the master first byte after START are then checked against the programmed 683xx M bus slave address for a match When they match an interrupt is generated if enabled and a status bit indicates the cause as M bus addressed as slave MAAS On entering the corresponding interrupt handler the software read write status indicator is read to determine whether the slave is to receive or transmit subsequent bytes and the transmit receive mode set accordingly If in transmit mode the first data byte transmit is initiated by writing to the data register If in receive mode the first receive byte is For More Information On This Product 2 Go to www freescale com Freescale Semiconductor Inc initiated by a dummy read of the data register There is no sensible data read at this point but having started the receive process data register reads in subsequent end of byte interrupts read valid data and initiate the next byte receive Again the software protocol determines the use of acknowledges For a fuller description of the M bus software and hardware features see the MC68307 users manual Description of Set up The hardware consists of two identical MC68307 systems connected together via the M
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