Manual - ICP DAS USA`s I
Contents
1. 5 1 4 Isolated or TTL Input The input signal can be either isolated or TTL input as follows JP1 JP8 in the DOWN position will select the isolated input 1 8 JP1 JP8 in the UP position will select the TTL input 1 8 JP1 for chO JP2 for chl e JP3 for ch2 JP4 for ch3 JP5 for ch4 JP6 for ch5 e JP7 for ch6 JP8 for ch7 Isolated input default TTL input I 8048 Hardware User s Manual Mar 2005 Rev 1 0 6 1 5 Digital Input amp LED indicators The LED and Digital Input mapping is shown as follows power LED i 8048 LILJECYE ETE IE The LED status and the digital input relation is listed as follows Isolated OPEN 1 Low OFF 0 1V 1 Low OFF 3 5 30V 0 High ON OPEN 1 Low OFF 0 0 8V 0 Low ON 2 5V 1 High OFF I 8048 Hardware User s Manual Mar 2005 Rev 1 0 7 1 6 Programmable Rising Falling interrupt Each channel of the 8048 can be programmed as one of the following types individually Rising edge interrupt input 2 Falling edge interrupt input 3 Rising edge and Falling edge interrupt input Following is the 8048 interrupt performance Performance 40M 0 024ms 15 8KHz 80M 0 01ms 35KHz T is the leading time between 8048 receives the input signal to CPU executes the interrupt service routine ISR The possible types are as follows T T gt Di2. 1 channel 0 1 Enable 28 9895 828 82 SE oek k HR A kk kk 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 23 SlotO s priority is 6 Slotl s priority is 7 Set priority Priority 0 8 O High 7 Low 8 disable S92 9 9 2 A 2 2 EA 2 EA 2 EA 2 EASE CA 18048_InstallISR O unsigned long amp ISR_Function_Slot0 6 18048_InstallISR 1 unsigned long amp ISR_Function_Slot1 7 for Print Rising SOCO0 d n r i8048_RisingEventCount 0 0 Print Rising 1C0 d n r i8048_RisingEventCount 1 0 PEE 2 K k ae k ae k akk ak ak k ak a ae a ak he fe fe fe fe fe fe K a ak 2K k ak 3k a ak 28 K a 3K 2K k ak 2K k ak 2 K ak 2 gt K K ak 2 k ak 2h K ak 2 K ee K he he he Ic Allow the other interrupt to execute Please don s use the Print or printCom1 function in ISR these function will cause the problem TEREFE E E EKRE ER 2h 2 2h 2h 2 2 2 E E EERE fe fe fe fe EE EREE EE R EERE ERR E EKRE EE E 2h 2 2 2 2 EERE EKRE void interrupt far ISR Function SlotO void if i8048_Read_RisingEvent 0 0 Add user s ISR code for channel 0 18048_UnFreezeCPU 0 18048 UnFreezeINT 0 X Clear interrupt status of 8048 void interrupt far ISR Function Slotl void if i8048_Read_RisingEvent 1 0 Add user s ISR code for channel 0 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 24 18048 UnFreezeCPU 1 18048 UnFreezeINT 1 Clear interrupt status of 8048 1 8048 Hardw
3. Hardware User s Manual Mar 2005 Rev 1 0 2 4 4 DI 7 7 2 2 ae ae ae LLL 2 2 2 a ee fe fe fe fe RERE 28 218 28 28 28 28 REER RER 2 22 2 2 ERRER 2 2 2 2 ae he he fe fe fe fe fe tL LLL DI c Reads DI Compiler BC 3 1 Turbo C 1 01 3 01 free from http community borland com museum MSC 6 0 MSVC 1 52 Compile mode large Project DI c Lib 8000E Lib 80001 Lib A HE SER 2 2 2 2 So sese oe oe ook ol ob oi o oi oe ee he he fe fe fe oe o o o oe o o o e s so SEE HER HE 2 2 sese pee pee bee 2 2 2c 2c ce he ie E include Lib1 8000E h include lib 8048 h void main void int iChannel iDI_ALL iDI_Ch iSlot InitLib Print Please selection Slot Scanf d n r amp iSlot for iDI_ALL i8048_DI_ALLGSlot Read all channel Print DI ALL status x n r iDI_ALL forG Channel 0 iChannel lt 8 iChannel iDI Chzi8048 DI Ch iSlotiChannel Read signle channel ifGDI_Ch 0 Print CH d gt Logic d LED ON n r iChannel iDI_Ch 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 28 else Print CH d gt logic d LED OFF n r iChannel iDI_Ch I 8048 Hardware User s Manual Mar 2005 Rev 1 0 29 Appendix I O Control Register of 8048 The BASE address for the 8000 series 1s as follows SlotO BASE 0x80 SlotAddr 0 Slotl BASEZOxAO SlotAddr 1 Slot2 BASE 0xCO SlotAddr 2 Slot3 BASE 0x 0 SlotAddr 3 The I O cont
4. I 8048 User s Manual Warranty All products manufactured by ICP DAS are warranted against defective materials for a period of one year from the date of delivery to the original purchaser Warning ICP DAS assumes no liability for damages consequent to the use of this product ICP DAS reserves the right to change this manual at any time without notice The information furnished by ICP DAS is believed to be accurate and reliable However no responsibility is assumed by ICP DAS for its use nor for any infringements of patents or other rights of third parties resulting from its use Copyright Copyright 2004 by ICP DAS All rights are reserved Trademark The names used for identification only maybe registered trademarks of their respective companies I 8048 Hardware User s Manual Mar 2005 Rev 1 0 1 1 General Introduction The I 8048 module is an 8 channel digital input module designed for interrupt applications The key features of the I 8048 are as follows 1 Digital input channels 8 2 Digital input type isolated differential or TTL 3 Digital input level isolated input Logic level 0 0 1V Logic level 1 4 30V TTL input Logic level 0 0 0 8V Logic level 1 2 5V 4 Isolated voltage 2000V pc 5 Built in isolated power supply 5V 200mA max 6 Interrupt specifics Max interrupt frequency CPU 40M 15 8 KHz max CPU 80M 35 KHz max Trigger type Rising falling edge programmable for each channe
5. Read FallingEvent iSlot 0 Add user s ISR code for channelO 1f 18048 Read FallingEvent iSlot 1 Add user s ISR code for channel1 1f 18048 Read FallingEvent iSlot 2 Add user s ISR code for channel2 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 21 18048 UnFreezeCPU i1Slot 18048 UnFreezeINT 1Slot Clear interrupt status of 8048 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 2 4 2 Int Slot Volt 2 2 ae ae ae LLL LL k k k ae k fe fe fe fe K k kK ak ak 2K K ak k K ak 28 K ak 3k 2K K ak K 2222 2 2 2K K ak 2h K k 2 K 2 2 K ee 2K he he he ke INT_Slot c Single channels as rising or falling edge interrupt in multi slots Compiler BC 3 1 Turbo C 1 01 3 01 free from http community borland com museum MSC 6 0 MSVC 1 52 Compile mode large Project INT Slot c Lib 8000E Lib 8000 Lib FKK ak ak 28 k ak 2k a ak 2 K 2 2 gt K k ak 2 2 ak 2 K 2 2 gt K k 2 2 E ee K fe fe fe fe fe K k ak 2K K ak 3K K ak k K A ak 28 K ak k K k k K 2 k 2K Kk K include Lib 8000E h include lib 8048 h void interrupt far ISR Function SlotO void void interrupt far ISR Function Slot1 void void main void InitLib 18048 Init 0 18048 Init 1 Slot 0 Enable channel 0 1 as rising edge interrupt 18048 Set RisingReg 0 0 1 slotO channel O 1 Enable Slot 1 Enable channel 0 1 as rising edge interrupt 18048 Set RisingReg 1 0 1 slot
6. are User s Manual Mar 2005 Rev 1 0 2 4 3 Int Int 75 7 2 2 ae ae ae ae ae 2g 2 2 2 ERRER fe ERR ERER ERRER REER RE ERER 2h 2h EERE REE REE EREKE fe fe fe oie ie RRR RRE INT_Int c CPU accept external interrupt request during ISR Compiler BC 3 1 Turbo C 1 01 3 01 free from http community borland com museum MSC 6 0 MSVC 1 52 Compile mode large Project INT_int c Lib 8000E Lib 8000 Lib AERE SEE SER 2 2 Sole sese sese seo o o oi oi oi oe oi o he he fe fe fe oie he o oe o o oe o e oo eR SEE HE EE 2 2 see pepe pee pee 2 2 2c ec he he EE include Lib 8000E h include lib 8048 h void interrupt far ISR_Function void int iSlot void main void InitLib Print Please selection slot 0 3 Scanf d n r amp iSlot 18048 Init 1Slot Enable channel 0 as rising edge interrupt 18048 Set RisingReg iSlot 0 1 O channel O 1 Enable Install ISR 18048 InstallISR iSlot unsigned long amp ISR Function 6 priority 6 paaano 2A E22 2 IC EH kk kkk 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 26 Please don s use the Print or printCom1 function in ISR these function will cause the problem void interrupt far ISR_Function void 18048_UnFreezeCPU iSlot _asm sti CPU accept other interrupt request 1f 18048 Read RisingEvent iSlot 0 Print INT n r 18048 UnFreezeINT 1Slot Clear interrupt status of 8048 1 8048
7. gital Input Logic value ISR x y Rising Edge Interrupt I 8048 Hardware User s Manual Mar 2005 Rev 1 0 8 Digital Input Logic value d a 5 E E vo z o ON E en E T es Digital Input Logic value Rising and falling Edge Interrupt I 8048 Hardware User s Manual Mar 2005 Rev 1 0 1 7 Clear Interrupt Referring to Section 1 2 the interrupt signal will be latched until a clear interrupt signal is activated Refer to the appendix for the addresses of clear interrupt signals The global interrupt Gi is shared by all eight signals If any single interrupt does not clear to LOW then all interrupts will be blocked and the CPU will not be able to receive any further interrupts That is to say the programmer should ensure that the code clears the interrupt and make sure that the global interrupt Gi is LOW in normal conditions Writing to BASE 0x0D will force the Gi to LOW for about 0 1uS The Gi will return to its previous state after writing This mechanism will ensure that the I 8048 works properly in a shared interrupt system The only way to clear the Gi 1s to clear all the Qfn and Qrn values listed in Section 1 2 Reading from BASE n will clear both Qfn and Qrn values Notes If any Qfn or Qrn value is Logic HIGH the Gi will be HIGH to block all further interrupts I 8048 Hardware User s Manual Mar 2005 Rev 1 0 10 2 Software In
8. ile mode large Project INT_Ch c Lib 8000E Lib 8000 Lib FKK ak ak aK k ak 2 2 ak 2 K ak 2h gt K 2 LLL ak 2K K 2 3K gt K ee he fe fe fe fe he 3K gt K 3K 3K gt K A 3K 2K K ak 2K K SK 2K K a 2 2 2 ak 2 K ak 2 K ak 2g K K ak K he he he K include lib 8000E h include lib 8048 h void interrupt far ISR_Function void int iSlot void main void InitLib Print Please selection slot 0 3 Scanf d n r amp iSlot 18048 _Init iSlot Enable channel 0 as rising edge interrupt 18048 Set RisingReg iSlot 0 1 O channel OQ 1 Enable Enable channel 0 1 2 as falling edge interrupt 18048 Set FallingReg 1Slot 0 1 0 channel 0 1 Enable 18048 Set FallingReg iSlot 1 1 0 channel O 1 Enable 18048 Set FallingReg iSlot 2 1 0 channel 0 1 Enable 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 20 Install ISR 18048 InstallISR iSlot unsigned long amp ISR Function 6 Priority 6 for Print Rising S dC0 d_ Falling S dCO0 d S dC1l d S dC2 d n r iSlot i8048_RisingEventCount iSlot 0 iSlot i8048_FallingEventCount iSlot 0 JS1ot 18048 FallingEventCount iSlot 1 JS1ot 18048 FallingEventCount iSlot 2 paaa o e o okk kkk Please don s use the Print or printCom1 function in ISR these function will cause the problem void interrupt far ISR_Function void 1f 18048 Read RisingEvent 1Slot 0 Add user s ISR code for channelO 1f 18048
9. l I 8048 Hardware User s Manual Mar 2005 Rev 1 0 2 1 1 Pin Assignment for the l 8048 The pin assignment for the I 8048 is shown as follows Terminal No 1 GND IN 0 IN 0 IN 1 IN 2 L 2 IN 4 IN 4 IN 5 IN 5 IN 7 e e e e e e e e e e e e e e e e e Pin 1 TTL GND ground for non isolated input signals Pin 2 N A Pins 3 18 8 channel digital input Pins 19 and 20 Isolated power supply 5V 200mA max I 8048 Hardware User s Manual Mar 2005 Rev 1 0 3 1 2 1 8048 Block Diagram The signal flow block diagram is shown as follows Rising D flipflop D flipflop Interrupt CPU 1 8048 8 ch interrupt I 8048 Hardware User s Manual Mar 2005 Rev 1 0 1 3 8000 Interrupt Block Diagram The 8000 series interrupt system block diagram is shown as follows SlotO s Int Slot1 s Int Slot2 s Int Slot3 s Int D filpflo Slot4 s int discs IntCir4 Slot5 s int lintCir5 Slot6 s int IntCir6 The CPU provides 4 interrupt inputs INTO INT4 for slotO slot3 and non masked interrupt input NMI for slot4 slot7 The NMI has Aslots totally 32 interrupt channels To provide a function let 32 channels share the NMI is hard Thus the library only supports 8048 plugged in slotO slot3 I 8048 Hardware User s Manual Mar 2005 Rev 1 0
10. ly the functions that don t use interrupt can be used in the ISR Can do Mathematics Accessing I O ports Accessing 8K series I O modules Accessing 7 segment LED of the SMMI The functions that relative to interrupt can t be used in the ISR Can t do Accessing COM ports Accessing 87K series I O modules Timer Accessing push buttons of the SMMI Ethernet communication But sometimes we need to enable the interrupt option during execution one ISR to allow CPU accept another interrupt request To do this the ISR need to do some modification like below Normal ISR void interrupt far ISR_Function void user s code 18048 UnFreezeCPU iSlot Telling CPU to end of interrupt 18048_UnFreezeINT iSlot I 8048 Hardware User s Manual Mar 2005 Rev 1 0 17 Normal ISR void interrupt far ISR Function void user s code 18048 UnFreezeCPU iSlot Telling CPU to end of interrupt asmsti enable interrupt option user s code Can accept other interrupt 18048 UnFreezeINT iSlot When the ISR is modified to be able to accept other interrupt service request the timing chart becomes as follows Only ISR A enable interrupt option s BE AMEE E Pods o dee CUP ability to accept interrupt request After calling asm sti in the ISR A the CPU can accept other interrupt reque
11. pt Priority to distinguish order of execution The request with higher interrupt priority will be serviced first The priority number of 80188 80186 CPU is Enabled 0 High 7 Low Disabled 8 For example A s priority is 2 B s priority is 6 CPU gets two requests A and B at the same time Because A s priority is higher than B CPU services A s request to execute ISR A first And ISR B will not be executed unless ISR_A is finished Ethernet COM2 3 4 5 When you assign an interrupt priority for the 8048 you need to consider all interrupt services of the system We suggest users to assign 8048 s priority to 6 or 7 Demo program INT Slot c 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 15 2 2 2 Requests from different channels All 8 channels of the 8048 share the same ISR That means the code for each channel are in the same ISR but different part The 8048 provides two interrupt event registers One is for rising edge interrupt and another for falling edge interrupt By reading the registers the program would know which channels triggered the ISR Function declaration int 18048 Read RisingEvent iSlot iChannel int 18048 Read FallingEvent iSlot i Channel If the return value is not zero that means the ISR was triggered by the channel Demo program INT Ch I 8048 Hardware User s Manual Mar 2005 Rev 1 0 16 2 4 What the ISR can do and can t do Normal
12. rol registers are as follows 0 Clear interrupt input 0 Clr0 N A 1 Clear interrupt input 1 Clrl N A 2 Clear interrupt input 2 Clr2 N A 3 Clear interrupt input 3 Clr3 N A 4 Clear interrupt input 4 Clr4 N A 3 Clear interrupt input 5 Clr5 N A 6 Clear interrupt input 6 Clr6 N A 7 Clear interrupt input 7 Clr7 N A 8 Read Rising Enable Register Set Rising Enable Register Er7 Er6 ErS ErA Er3 Er2 Erl ErO Er7 Er6 Er5 ErA Er3 Er2 Er1 ErO D7 Er7 DO Er0 D7 Er7 DO Er0 9 Read Falling Enable Register Set Falling Enable Register Ef7 Ef6 Ef5 Ef4 Ef3 Ef2 Efl Ef0 Ef7 Ef6 Ef5 Ef4 Ef3 Ef2 Ef1 Ef0 D7 Ef7 DO Ef0 D7 Ef7 DO Ef0 0x0A Read Global Interrupt Status Gi Force Interrupt to LOW state about 0 1uS ClrGi 0x0B Read Rising Interrupt Status N A Qr7 Qr6 Qr5 Qr4 Qr3 Qr2 Qr1 QrO 0x0C Read Falling Interrupt Status N A Qf7 Qf6 Qf5 QfA Qf 3 Qf2 Of L OfO Ox0D Read Digital Input N A Di7 Di6 Di5 Di4 Di3 Di2 Dil DiO 1 8048 Hardware User s Manual Mar 2005 Rev 1 0
13. signal enters the 8048 The function declaration 18048 InstallISR int Slot unsigned long ISR Function int Priority User s loop function User can design one s own function in this loop For example Checking DI status ISR When External signal enters 8048 the ISR will be executed I 8048 Hardware User s Manual Mar 2005 Rev 1 0 12 Users can design their own functions in the ISR The ISR function declaration void interrupt far ISR_Function void For example Sets an alarm immediately or gets an A D value when 8048 gets an interrupt signal I 8048 Hardware User s Manual Mar 2005 Rev 1 0 13 22 Recognize different interrupt service requests 8048 is an 8 channels rising falling edge programmable interrupt module It can plug into slot 0 slot 3 of the 8000 MCU The section introduces how to recognize interrupt requests from different slots and channels 2 2 1 Requests from different slots Each slot is assigned an interrupt pin of the CPU shown in section 1 3 So their ISRs are different CPU executes different ISR when the request is from different slot Considering when the interrupts occur the situations can be divided to two kinds Interrupted at different time CPU executes ISRs one by one in the order of when them occurred 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 14 Interrupted at the same time This situation CPU uses Interru
14. st When interrupt B occurs the CPU jumps from ISR A to execute ISR B And continues ISR A till ISR_B is finished Demo program INT INT c 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 18 2 4 Software Demo Program I INT Ch e One I 8048 is installed in slot0 e Multi channels are enabled e Multi channels active rising edge and falling edge e EOI at the end of ISR NO accept other interrupt to execution 2 INT Slot e Two I 8048 are installed in slotO and slotl e Single channel active rising edge or falling edge in slotO and slot1 The INT Slot s EOT at the end of ISR NO accept other interrupt to execution 3 INT INT e One I 8048 is installed in slotO e Single channel are enabled e Single channel active rising edge or falling edge e EOI at the beginning of ISR Accept other interrupt to execution 4 DI e The I 8048 is installed in slot 0 7 Reads 8048 DPs state Note Executing ISR can t use call of DOS and printf unless user puts the EOI in the beginning of ISR I 8048 Hardware User s Manual Mar 2005 Rev 1 0 19 2 4 1 Int Ch Volt LLL LLL 2 2 2h 2 2 a ee fe fe fe fe fe fe he 26 he 28 he 28 28 28 28 28 28 28 2s 2s 28 28222 22 2 2 2 2 2 2h 2 2h 2 2 2 2 2 ee he he he he he INT_Ch c Multi channels as rising or falling edge interrupt in single slot Compiler BC 3 1 Turbo C 1 01 3 01 free from http community borland com museum MSC 6 0 MSVC 1 52 Comp
15. troduction Users can follow the sections to understand the usage of 8048 s Library software We offer multi functions in the 8048 library and users can use these functions to develop 8048 s program 2 1 Software flow chart Initial 8048 Enable falling edge or rising edge Install Interrupt service routine ISR External signal ISR User s loop function Initial 8048 Gives all internal variables an initial value Any interrupt signal clear 1 8048 Hardware User s Manual Mar 2005 Rev 1 0 11 to low then all interrupt will not be blocked and CPU will be able to receive any further interrupts The function declaration 18048 Init int Slot Enable falling edge or rising edge 1 Each channel can set to Rising edge interrupt Falling edge interrupt gt Rising edge and Falling edge interrupt 2 User can enable one channel several channels or all channels as interrupt signal input The function declaration 18048_Set_FallingReg int Slot int Channel int Enable 18048_Set_RisingReg int Slot int Channel int Enable Install ISR We offer the variable of priority in this function and user can adjust it When two slots are interrupted at the same time the slot of higher priority executes ISR first then slot of lower priority does Priority is 0 to 8 O High 7 Low 8 disable The priority is recommend as 6 7 After installing an ISR the CPU will execute the ISR when External
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