Home

PUM IMAPCAR2 Video I/F Board

1. 24 4 4 7 Plug in phone jack for CHO differential motion J4 24 448 NISC input RCA Jack J5 tete 25 4 49 JNISCoulpub HOA Mack UD Zur Gus ento Da 25 JTAG 25 4 4 11 Power supply terminal stand 26 5 Mardware ComponeNi E UTER 27 FPGA ede ice ea ie dee ass 27 5 1 1 Irriage oysterm BIOCK y a 22 io a em 27 Gommunicallon system bug i Ese 31 obo RESOLDIOCK e 32 5 1 4 FM AS SIOMIMEM TM A puas aaah Suku aha 33 Preliminary User s Manual U19880EE1V0UM00 3 o2 FPGAIROMCOMNQUIAIION SSD Susu outs iine 39 5 3 High speed status random access memory 39 rS 39 5 5 au bonas en n utasa 40 56 R9485 transcelV fS om edam 41 5 7 Equipment connection 41 rcc T c PU 42 Preliminary
2. Ca B60 B31 B30 B1 CN6 Meaning of the IO field value is seen from Video IF board side ARTORX PD VDO UARTOTX PD VD SYNC LB 0 210 ch0_idata l 1 5811 PD V 4j ODDEVENT HSYNC IB 0 SCLK 10 ch0 idata 0 SR I0 1 gt 1 Lt bo 2 ChO chO Hata 0 Hata 0 0 iata 0 0 0 5 chl CAR2VN chl Hata chl chl chl chl chl chl CLK 12 ch2 ch2 CAR2 VN ch2 ch2 Hata ch2 Hata ch2 ch2 ch2 ch2 D vD 5 ODDEVENI p Vn 00 DDEVEN I 2 SYNC IB 2 SRI2 SR 14 SR 161 SR 18 SR 110 12 14 SR 112 SR 114 SR 16 SR 118 SR 120 SR 122 12 14 0 SR 124 2 SR 126 41 58 128 61 58 130 8 SR 1132 S R 1 34 12 SR 136 14 S R 138 e Ajo ICON DoT lt o 0 iata 0 ata 0 ata 0 xata 0 xata 3 S R 13 i5 SR I5 71 8 7 9 SR 19 5 CAR2 ChO Ca ee chO chO data 1 RX P 1 SYNCIB 1 151 LIE CLK2I 1 chl data chl chl data chl data chl data chl data
3. VALD Pi SYNC Pi CLK Pi OPi 2Pi 4Pi 6Pi 8Pi pare pare pare pare AM FRM VALID BDSYNC BDCLK D B 2 3 4 5 1 lls c m BD D b BD Do0 BD Do2 CU D8 CU D10 pare pare pare FRAME VALID Ni C Ni es 22 4 I WN PCL DON c bo DAN D6N D8N pare pare pare FRAME VALD Po HSYNC Po PCLK Po 0 2 4 6 8 Po VALID No HSYNC No PCLK No 0 No 2 4 No 6 No 8 No Spare 0 0 0 0 D Spae LT DOPo 140 D2Po D4Po OT D6Po OT D8Po 0 E EE DONo I D2No LO D4No OT D6No I 1394 B sp gt A PPPS co co co co Co o2 0 0 WILD o ol O O 1 FW N N la la c c gt Seas PN 3111 I Meaning of the IO field value is seen from 1394 board side ART TX Pi Reserved SYNC Pi CLK2Pi 1 1 3 P a 5 Pi 7Pi BD Do3 CU D9 CU DII pare pare ART Ni ART TX Ni VSYNC Ni PCLK2Ni ca
4. j j 5 2 2 gt 2 2 2 30 21 32 33 34 35 36 37 38 39 4 41 4 4 4 4 4 4 4 4 5 5 5 5 c 9 10 EN 51 092 33 34 35 36 37 38 ___39 40 57 GLOABAL SRESE 59 2V AL gt ary er COTO JEL 201 22 24 26 gt TO E CO 101 zT mE 1 eo 50 52 OBIBUSREQ V BUSREQ V BUSRESET 3 LOABAL R 5 STs 1 STs ale ops euiE lc 1 11 13 15 171 19 VD 21 AR2 PORTO AR2 PORTO AR2 PORTO AR2 PORTO AR2 PORTO AR2 PORTI PORTI AR2 PORTI NTP 1 CSICLK AR2CSITX AR2CSICS ICAR2DCONIO 2 REGON25 co 11 co lt ol 5 al Tes 1 J C3 VT Tr TT TT w kaum ea L 1 2 m eserve connection Reserve PFGA connection Reserve PFGA connection Reserve PFGA connection Reserve PFGA connection Reserve PFGA connection 27 15 16 17 p CPU Bus Address Ine CPU Bus Address Ine CPU Bus data Ines CPU Bus data Ines 22 24WATOB Reserve connection 20NATIB O CPUbus Waisgnal 26WAIT2D Reserwe connectb
5. Direction of the signal Signal Name Description from FPGA point of view CN1_RX LVDS differential motion reception line side CN1_RX LVDS differential motion reception line side UART1A Input Output RS485 differential signal side 9 4 CN1 Input LVDS differential motion transmission line side Preliminary User s Manual U19880EE1VOUMOO 23 IMAPCAR2 Video I F Board 4 4 6 Plug in phone jack for CH2 differential motion J3 Manufacturer Hirose Model TM24RSG 5A 88 Direction of the signal DAD Signal Name Description from FPGA point of view CN2_RX0 LVDS differential motion reception line side CN2_RX0 LVDS differential motion reception line side UART2A Input Output RS485 differential signal side CN2 RX1 LVDS differential motion transmission line side UART2B Input output RS485 differential signal side CN2 RX1 LVDS differential motion transmission line side DC12V NENNEN Power supply line DC12C 4 4 7 Plug in phone jack for CH3 differential motion J4 Manufacturer Hirose Model TM24RSG 5A 88 Direction of the signal um Signal Name Description from FPGA point of view CN3_TX0 LVDS differential motion reception line side CN3 TXO LVDS differential motion reception line side tom we Input Output RS485 differential signal side Preli
6. T ip icem xess2000766676 E EER eW IliGllTI 0liII2II IIIII Seer res e C357 SPACER RBS ALLEELE LLL PTHOBTZAQW e mm ir Hie uPD444015L Trad ma EB EB uPD444018L SSCS REESE BCT PETIT ET CET LAALLLLLLLLLLLLLILLLILIAIAOA SECS s s m s nn s sm is m m s ss amp EERE SS amp amp h s h B amp s s sns sm u s s mmn is sms h i ih S h B B h 8 h ih B 8 ih s s s s s h s s s s s sa sisa G as s s s s m ss E E S SUS 9 S S s amp B B is k 8 iB B k h iB B h R220 R255 Rid R233 Bose RA4T fide mum mm ma mu mm t TP38 TP78 94 1 Li Tpss o oO 0 72 5 z
7. mg SQUE C B Bass P jam n LEAN CRI E 24 tit E omm mar aam mm m m pee cn E T RII CE dk p on H UN M H EEN 17 1827 ee L P TM 14 50 16 50 16 50 16 50 17 50 Preliminary User s Manual U19880EE1V0UMOO 10 2 Video I F Board HRESET PRESET DC3 3V gt VideolO connector e E r Power supply E terminal stand Wi ws GND connector DC12V agree I af Ut J v 1 SW l 3 zu SRAM iiid si F LED2 LED8 P MIL n 2 n 2 amp i E LED4 24 DC1 2V T UN f a a olus We j 4 as Li c JTAG connector gt Graphic FPGA T i SV connector p LED9 f i p gt s NTSC 4 E _ 529 5 m 1g MAS 4 vos T LVDS Tx LVDS Tx 5 TE S a 44 ee 2 HT EN A des te P 5 a 9 Input e iani in phone jack for LVDS a RCA Jack Jack ava alla AAA Preliminary User s Manual U19880EE1VOUMOO 11 2 Video I F Board VideolO connector 1 92344 214 6345 8145
8. Preliminary User s Manual IMAPCAR2 Video I F Board Hardware Document No U19880EE1VOUMOO Date Published July 2009 NEC Electronics Europe GmbH Legal Notes The information in this document is current as of July 2009 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application exampl
9. IMAPCAR2 Video I F Board 3 General overview and block diagrams 3 1 Video Board IF overview The following figure is the general overview on the IMAPCAR2 video IF board Video2 connector IMAPCAR2 board Preliminary User s Manual 019880 1 00 00 6 IMAPCAR2 Video I F Board 3 2 Power Supply block diagram The following figure describes the block diagram of the power supply Power Module DC12V PTH08T240WAZ gt DC3 3V DC DC Converter EN5335Q DC1 2V Linear Regulator PQ1U181M2ZP DC2 5V Regulator LDO PQ1U181M2ZP DC1 8V Preliminary User s Manual U19880EE1VOUMOO IMAPCARe Video I F Board 3 3 Reset block diagram The following system describes the reset management of the entire system including the IMAPCAR2 300 evaluation board IMAPCAR2 board SV board VIDEO IO board G SRESET G HRESET Delay open Circuit x Vsy H RESET 3 3V opnerr C Voltage aes monitoring LL Q O q O PROG B 3 3 Voltage D monitoring om SW P RESET SW P RESET 3 3 Voltage P O 4 2 PRESET Green line Power reset line hard reset Blue Line Soft Reset The following figure describe
10. Color State after reset LED9 LED10 LED11 LED12 LED13 LED14 LVDS RX IC1 PLL LOCK ON PLL locked OFF PLL unlocked LVDS RX IC4 PLL LOCK ON PLL locked OFF PLL unlocked LVDS RX IC7 PLL LOCK ON PLL locked OFF PLL locked LVDS RX IC8 PLL LOCK ON PLL locked OFF PLL unlocked NTSC decoder ML86V7666 STATUS1 ON PLL locked OFF PLL unlocked NTSC decoder ML86V7667 STATUS2 ON PAL OFF NTSC LED9 indicates the status of receiving from J1 connector LED10 indicates the status of receiving from J2 connector LED11 indicates the status of receiving from J3 connector LED12 indicates the status of receiving from J4 connector For more details please check ML86V7666 user s manual For more details please check ML86V7667 user s manual Preliminary User s Manual U19880EE1VOUMOO 18 IMAPCAR2 Video I F Board The following table describes the LEDS related to graphic FPGA State after reset Color The following table describes the LEDS related to FPGA reconfiguration completion Color Normal State FPGA configuration completion LED23 ON config OK Check if the FPGA configuration is finished correctly OFF config not OK Preliminary User s Manual U19880EE1VOUMOO 19 IMAPCARe Video I F Board 4 4 Connector description 4 4 4 Video I O connector CN1 CN6 Manufacturer SAMTEC Model QTH 060 05 L D A QSH 060 01 L D A A60 A31 A30 A1 1
11. SILRX PD VD 12 CSI TX PO VDOll4 sd ICCSILCLK PDO VDO 16 C j C am era reset PD VD 18 NTSC decoder reset PD VD 20 generalpurpose port IV AR2VOUTcommo CAR2 VOUT ch0 c rer 1 1 ii CAR2 VOUT chl if if RN cn 20 ro f Lt if if 1 Ws NS oo ST font m 4 NIO Tr 1 OI lt gt 1 I nii i ni 2 VOUT ch2 rs TIT mi v n5 mA ss dE call Gl Goll el c RRE Bo G re O B B E e oo co 52 P2 B2 R2 i i i o i o 3 exl 9 o oo o o1 42 co Oo AJ O O1 CO 3 ODO 4 Co P2 i O0 13 Oo i generalpurpose port lt lt Preliminary User s Manual 019880 1 00 00 IMAPCARe Video I F Board 4 4 2 Supervisor connector CN2 CN7 Manufacturer SAMTEC Model QTH 060 05 L D A QSH 060 01 L D A A1 0 A31 A60 A60 A31A30 A1 ea E CN2 CN7 0 3 6l
12. 10 16 A23 DO D6 D15 CS Bl 2 PORTOO CAR2 7 CAR2 RESERVED 0 RESERVED 2 CHO CHO D 9 CHO D 15 HSYNCIBI CHI Do ODDEVEN P CH2 D9 VSYNCOOBD TCK GND 2 91 IMAPCAR2 Video I F Board a o n C8 DIZ ES D 10 G8 D8 Jo 3 3 015 GND D14 YOBIPORTI F14 CAR2CSICS H14 SCLKD 14 3 3V 015 GND L VSYNCIBO 15 5 20 K15 GND Preliminary User s Manual U19880EE1VOUMOO 36 IMAPCAR2 Video I F Board LIO GND 10 33V RIO GND L11 GND GND L12 GND 12 GND X fRI2 GND 12 GND L13 GND JRI3 GND C JUI3 33V 115 GND 5 R15 GND US GND 116 GND 6 GND R16 GND U6 GND L18 33V 18 33V R18 33V 18 12V L19 2 NI9 PD YDIO R19 TEST LEDI 019 33V 121 CH2 Do N21 CH2 D7 R21 TEST LED3 021 SV BUSBUSY L22 22 R22 TEST LED4 022 SV BUSREQ 123 CHOODoO J N23 004 R23 GND 023 SV BUSSTAT SV BUSRESET 125 CH20D4 25 CH20D6 25 DX DONE 26 SV BURST OOO I yo 1 2 DOT TOTO LOIN CO DOT I oO O1 lt Preliminary User s Manual U19880EE 1VOUMOO V 23 V 24 V 25 V 26 VIDEO 2 B37 VIDEO 2 VIDEOZ B38 V IDEO 2 A38 VIDEO 2 B39 V IDEO 2 A39 9 9 V 1 21 9
13. 300 Ohm A video amp is required when a TV monitor is connected Master Slave operation Slave only for ITU R BT 656 mode Color bar output 3 bit title graphic input interface Luminance adjustment RGB gain adjustment Expanded luminance range mode Preliminary User s Manual U19880EE1VOUMOO 40 IMAPCAR2 Video I F Board e Synchronization signal level adjustment CGMS WSS information adding function Supports Macrovision copyguard function only available in the ML86V7656 o Conforms to version 7 1 L1 for interlace o Conforms to version 1 2 for progressive I2C bus type serial interface e Supply voltage 3 3 V I O supply 2 5 V core supply SCL and SDA pins only 5 V tolerant e Package 100 pin plastic TQFP TQFP100 P 1414 0 5 K ML86V7655TB ML86V7656TB For more information please refer to the ML86V7666 ML86V7665 data sheet 5 6 RS485 transceivers Supplier Linear Technology Model LTC2850CS8 8 LEAD PLASTIC MSOP Features 3 3V Supply Voltage 20Mbps Maximum Data Rate No Damage or Latchup Up to 15kV HBM High Input Impedance Supports 256 Nodes C I Grade e Operation Up to 125 C H Grade e Current Limited Drivers and Thermal Shutdown Delayed Micropower Shutdown 5uA Maximum C I Grade Power Up Down Glitch Free Driver Outputs Low Operating Current 370pA Typical in Receive Mode e Compatible with TIA EIA 485 A Specifications For more information please refer to the LTC2850
14. 1 8 SW PRESET It is a button switch for hard reset By pushing this switch the following device will be reset NTSC decoder NTSC encoder and e FPGA internal circuit Preliminary User s Manual U19880EE 1VOUMOO 16 IMAPCAR2 Video I F Board 4 2 Jumper description Power supply 12V is supplied through the JP1 VideolO connector Please make it to OPEN when it is unnecessary o Initial condition when the board is shipped by NEC SHORT e Power supply 12V is supplied through the JP2 VideolO2 connector Please make it to OPEN when it is unnecessary o Initial condition when the board is shipped by NEC SHORT e Power supply 12V is supplied through the JP3 SV connector Please make it to OPEN when it is unnecessary o Initial condition when the board is shipped by NEC SHORT External connecting the 12 bus of JP4 IC13 NTSC decoder and IC14 NTSC encoder becomes possible o Initial condition when the board is shipped by NEC OPEN Preliminary User s Manual U19880EE1VOUMOO 17 IMAPCAR2 Video I F Board 4 3 LED description The following table describes the LEDS related to user FPGA State after Color reset PLL Lock ON PLL Lock status PLL unlock OFF LII Green 000 LEDA Green LEDS Green LED6 Green LED7 Green Of J LEDS Gen Of 20 The following table describes the LEDS related to user NTSC device
15. 9 V 9 9 V 9 9 V 9 9 V 9 9 V 9 9 V 1 2V 1 2V 9 9 V TEST SW 16 TP 48 2290 49 RESERVED 10 2 5 N IMAPCAR2 Video I F Board AF25 22 2 Y2o RESERVED D9 25 RESERVED D3 25 RESERVED EO _ AF25 2 91 26 RESERVED DE 26 RESERVED 2 26 CCLK AF26 GND Preliminary User s Manual U19880EE1VOUMOO 38 IMAPCAR2 Video I F Board 5 2 FPGA ROM configuration Supplier Xilinx Model XCFO8PVOG48C 48pinTSOP For more information please refer to the Platform Flash In System Programmable Configuration PROMS data sheet 5 3 High speed status random access memory Supplier NEC Model ML86V7655 uPD444016LG5 A8 7JF A 44pinTSOP Features e 262 144 words by 16 bits organization Fast access time 8 10 12 ns MAX Byte data control 1 01 1 08 UB 1 9 1 016 Output Enable input for easy application 3 3 V single power supply For more information please refer to the uPD444016L data sheet 5 4 LVDS Supplier Thine Model THCV213 48pinTQFP THCV214 48pinTQFP Features e Transmit 18bit data and 4bit control data through a e single differential cable Wide frequency range 5MHz to 40MHz e Support INIT pattern and LOCK indicator e Pre Emphasis Mode e Clock Edge Selectable e Dual Display Mode Power Down Mode e Low power single 3 3V CMOS design 48pin TQFP QFN For more information please refer to the THCV213 THC214 d
16. User s Manual U19880EE1VOUMOO 4 IMAPCAR2 Video Board 1 Introduction The Video I F board is to interface external imagers and display with the IMAPCARe evaluation board 2 Specification The Video I F board is composed by the following main components FPGA X XC 3S 2000 4 0 G 676C 676pnBG A S partan3 Xilnx XCFO8PVOG48C G8pnTSOP ROM forFPGA config EF LVDS THCV213 G8pnTQ FP Transm itter 18 bits X 20M Hz fixation use ne THCV214 48pinTQFP Receiver 18 bits X 20M Hz fixation use EM EN ME rium mec EC Y RS485 Lnear Techno LTC 2850M S8 SOP Transceiver 20M bps i iy NTSC PAL 86 7655 L00pnTQ NTSC PAL encoder OKIMLS6V 7666 00pnTQ FP NTSC PAL decoder IEEE e SRAM NEC uL PD444016LG 5 A8 7JF A G4pnTSOP 4M bit 256K word X 16b it a a Se 1 1 1 Dp SW COPAL CHS 10TB 0pnTSOP SWI COPAL CHS 8TB L6piTSOP SW6 7 8 9 10 CIE A M NNMERO S F MG S I I GN CNN M GM CR RN UC Push SW FUJSOKU SM T3 01 Z GMD 7X6 SW HRESET SW PRESET Ew w sI rPIrr P sIIIIA LED ROHM SML 210VTT86 RED LED 15 ROHM SML 210PTT86 GREEN LED 17 144 LED 16 23 Power suppl Ihput power suppl 12V Ihput range 4 5 14V and 1 orm ore Preliminary User s Manual U19880EE1VOUMOO 5
17. _ F22 NC B24 TCK b24 TDO J _ 124 Reserved B25 GND 025 RESERVED 25 Reserved Preliminary User s Manual U19880EE1VOUMOO 33 IMAPCAR2 Video I F Board L6 LVR3 SYNCO L7 LVR3SYNCI N7 LVTOD7 7 LVRODI4A 07 LVRODI LIO GND NIO 33V RIO GND amp uo 12 LII GND J NII GND GND L15 GND NI5 GND 5 GND 15 GND 116 GND NI6 GND J RIG6 GND JUl6 GND L17 GND Lis 3 V N18 3 3V 18 333V 18 12V L21 Reserved _ N21 L23 Reserved N23 Reserved M15 jPi5 GND Preliminary User s Manual U19880EE1V0UM00 34 IMAPCAR2 Video I F Board AC23 GND W23 VDEO2 A29 AA23 IDEO 2 B33 AC 23 GND AF23 V DEO2 48 W24 VDEO2 30 AA24 V DEO2 A39 AC24 DONE AF24 V DEO 2 A49 25 GND W25 VDEO2 A3l AA25 V DEO 2 A40 25 V DEO 2 B44 25 GND W26 VDEO2 32 AA26 V DEO2 A41 AC26 V DEO2 B45 AE26 25V YI LVRIDI6 ABI LVRIDT7 ADI LVRIDI AFI GND Y2 LVR1DIT7 AB2 LVRIDS AD2 LVRID2 AF2 2 5V 3 3 AB3 GND AF3 M2 AF9 25 Y9 LVR2 D17 9 2 D15 AD9 JLVR2D I9 APY 2 91 Preliminary User s Manual U19880EE1VOUMOO 35 2 0V CAR2Z PORTO 2 PORTOS CARZ PORT b SYS CLK YOBIPORT2 PI VDO CHO DI CHO D6 Z 9V VSYNCIBI CHI D2 PI VIS CH2 D6 ODDEVENOO TMS 2 0V GND Z 9V GND
18. 14 364 902706275 IE 2 92790276 I C349 P1686 em PIGS ESS RIS0W F 10394 85 4 347 C290 HEE HE x VideolO2 connector 0 139 6220 62 m 1035 C212 e RI C21 eu 209 181 6 A 128 gu LET B 22066 44 204 z B Mr j 162620 162850 1162850 LIC2850 fifties 111006 I E D 7 is 2 4 2 Et pem 7 81 119 y w d 3 3 LI se 48 37 48 12 T EN 2 4 1 44026 EJ ia 4 24 10 Pet m di 18 nn 3 Be 4924 os i snn 554 m mu 3 T T 445 24 4 ust EE 2 i 5 ts E 5 EE e Preliminary User s Manual U19880EE1VOUMOO 12 IMAPCARe Video I F Board 4 Board description 4 1 Switch description 4 1 1 SW1 NTSC decoder Initial Description Configuration Amplifier gain setting SW1 3 1 is active only if SW1 8 OFF SW1 3 1 Gain values x times OFF OFF OFF 0 55 OFF OFF 0 70 DFF ON OFF 0 93 OFF ON 1 21 OFF OFF 1 60 DN OFF 2 09 DN
19. 23 SCLKi2 SCLK2i2 VSYNCi2 HSYNCi2 SR 24 39 SCLKoO SCLKOiO VS YNCOO HS YNCOO S R 0 0 24 Internal composition of FPGA chart mode 1 image system Preliminary User s Manual U19880EE1VOUMOO 28 IMAPCAR2 Video I F Board Video IF Board Video2 connector Video Connector IMAPCAR2 board CN3 CN9 CN1 CN6 dus retta UserFPGA SCLKiO TRxO 8bit S 2 0 LVDS in VSYNCi2 HSYNCi2 LVDC out SCLKo1 TRx1 YEY NCI LVDS in HSYNCo1 LVDC out 580 12 23 SCLKi2 Rx2 16bit SCLK2i2 VSYNCi2 LVDS in HSYNCi2 LVDS in SR 24 39 NTS C in SCLKoO Tx2 SCLKOiO LVDS out I VSYNC00 LVDS out HS YNC OO SRO 0 24 NTSC ou SV connector CN2 C N7 Internal composition of FPGA chart mode 2 image system 2 board Video2 connector Video Connector CN3 CN9 CN1 CN6 UserFPGA Video IF Board Image FPGA SCLKiO in VSYNCi2 LVDS in HSYNCi2 LVDC out SRi 0 11 SCLKo1 TRx1 12bi VSYNCo1 LVDS in li HSYNCo1 LVDC out SRo 12 23 SCLKi2 16bit SCLK2i2 Rx2 VSYNCi2 LVDS in HSYNCi2 LVDS in S R 24 39 NTS C in SCLKoO Tx2 SCLKOiO LVDS out VSYNC00 LVDS out HSYNC00 SRO 0 24 NTSC ou SV connector CN2 C N7 Internal composition of FPGA chart mode 3 image system Preliminary User s Manual U19880EE1VOUMOO 29 2 Video I F Board Video IF Board
20. APCAR2 Mode2 OFF ON Input 2ch images from the progressive camera and the NTSC camera image to IMAPCAR2 Output the NTSC camera image from the NTSC encoder Mode OFF ON ON Input 1ch images from the progressive camera and the NTSC camera image to IMAPCAR2 Output the NTSC camera image from the NTSC encoder Output back the NTSC image for cascading the video interface boards for transmission For S ino the video interface boards for reception Preliminary User s Manual U19880EE1V0UM00 27 2 Video I F Board Video IF Board Image FPGA TRxO LVDS in LVDC out TRx1 LVDS in LVDC out Tx2 LVDS out LVDS out Video2 connector Video Connector CN3 CN9 CN1 CN6 User FPGA SV connector C 2 7 IMAP CAR 2 board SCLKiO SCLK2i0 VS YNCi2 HSYNCi2 SRi 0 11 SCLKol VSYNCol HSYNCo1 SRo 12 23 SCLKi2 SCLK2i2 VSYNCi2 HS YNCi2 SR i 24 39 SCLKoO SCLKOIO VS YNCOO HSYNCOO 580 0 24 Internal composition of chart mode 0 image system Video IF Board Image FPGA TRxO LVDS in LVDC out TRx1 LVDS in LVDC out R x2 LVDS in LVDS in NTSC in Tx2 LVDS out LVDS out NTSC oud Video2 connector Video Connector DIP SW CN3 CN9 CN1 CN6 User FPGA 8bit 8bit S V connector 2 7 IMAP CAR2 board SCLKiO SCLK2i0 VSYNCi2 HSYNCi2 SR 0 11 SCLKo1 VSYNCo1 HSYNCol SR 0 12
21. ON OFF 2 65 DN ON 3 45 XSW ON 1 OFFe 0 3 1 GAINS 2 0 Input mode Register 00 MRA 0 0 default value SW1 5 OFFeNTSC Invalid when register 02 MRC 7 1 NTSC PAL auto recognition SW1 4 OFF gt ITU R BT 601 ON gt Square Pixel Setting for NTSC 4fsc is available only by register 00 MRA 5 3 XSW ON 1 OFFe 0 5 4 MODE 1 0 External output pin configuration Register 00 MRA 0 0 default value OFF SW1 7 6 OFF OFF ITU R BT 656 10bit Y CbCr OFF ON 10bit Y CbCr 10bit Y CbCr Sync ON OFF 20bit Y CbCr 10bit Y 10bit CbCr Sync ON DN ON 24bit RGB YCbCr RGB orYCbCr 8 8 8bit Sync Register 10 CHRCB 1 0 24bitRGB 1 24bitYCbCr XSW ON 1 OFFe 0 Selecting method to set the amplifier gain and input terminal OFF External pin mode Amplifier gain setting use SW1 3 1 Input terminal setting use pin92 94 INS 2 0 ON Register mode Amplifier gain setting use register 1E ADC2 6 4 Input terminal setting use register 1D ADC1 2 0 m XSW ON 1 OFFe 0 2 Slave address selection OFF 1000 001X X 0 Write 1 Read ON 1000 011X X 0 Write 1 XSW ON 1 OFFe 0 OFF 7 6 MODE3 2 Preliminary User s Manual U19880EE1VOUMOO 13 IMAPCARe Video I F Board 4 1 2 SW6 user FPGA general purpose SW Initial Description Configuration 5 6 1 8 OF 41 3 SW7 user FPGA general p
22. Video2 connector Video Connector IMAPCAR 2 board CN3 CN9 CN1 CN6 Image FPGA UserFPGA SCLKiO mo von TE seth H 3 1 LVDS in HSYNCi2 LVDC out SR i 0 11 SCLKo1 TRx1 2221 VSYNCo1 LVDS in HSYNCo1 LVDC out SRo 12 23 SCLKi2 SCLK2i2 VSYNCi2 LVDS in HSYNCi2 LVDS in S R i 24 39 NTS SCLKoO Tx2 i SCLKOIO LVDS out J VS Y NCOO LVDS out 4 S R 0 0 24 NTSC oud SV connector CN2 CN7 Internal composition of FPGA chart mode 4 image system Video IF Board Video2 connector Video C onnector IMAPCAR2 board CN3 CN9 CN1 CN6 User FPGA Image FPGA SCLKiO LVDS VSYNCI2 RX HSYNCi2 LVDC out SR 0 11 SCLKo1 TRx1 VSYNCo1 LVDS in HSYNCo1 SRo 12 23 LVDC out p 12 23 SCLKi2 SCLK2i2 Rx2 VSYNCi2 LVDS in HSYNCi2 LVDS in SR 24 39 NTSC in SCLKoO Tx2 5 LVDS out VSYNCOO LVDS out HSYNCOO S R 0 0 24 NTSC oud SV connector CN2 C N7 Internal composition of FPGA chart mode 5 image system Preliminary User s Manual U19880EE1VOUMOO 30 IMAPCARe Video I F Board 5 1 2 Communication system block 1 Overview e Another equipment connected with the plug in phone jack can be controlled by the control and the I2C RS485 conversion function of NTSC encoder decoder device by 12 However the RS485 12C conversion function is needed on the connected e
23. ata sheet Preliminary User s Manual U19880EE 1VOUMOO 39 IMAPCAR2 Video I F Board 5 5 NTSC decoder encoder Supplier OKI Model ML86V7655 ML86V7656 100 Features Supported video type NTSC PAL Scanning method Interlace Progressive Single field signals Input data format o ITU R BT 656 4 type Y CbCr 4 2 2 10 bit multiplexing synchronization signal information added o ITU R BT 601 Y CbCr 4 2 2 20 bit non multiplexing Y CbCr 4 1 1 20 bit non multiplexing o Y CbCr 4 2 2 10 bit multiplexing without synchronization signal o YCbCr 4 2 2 20 bit non multiplexing progressive YCbCr 4 4 4 30 bit 24 bit non multiplexing interlaced progressive RGB 4 4 4 30 bit 24 bit non multiplexing interlaced progressive Input pixel frequency Input double speed clock frequency o 12 272727 MHz 24 545454 MHz NTSC Square Pixel o 13 5 MHz 27 MHz NTSC PAL ITU R BT 601 14 318182 MHz 28 636364 MHz NTSC 4fsc o 14 75 MHz 29 5 MHz PAL Square Pixel 18 2 86 MHz NTSC PAL ITU R BT 601 wide Output format o Composite CVBS o S Video Y C separate signals o Interlace Progressive YCbCr component Interlace Progressive Scan type conversion function Color space conversion function o lnterlace to Progressive Progressive to Interlace YCbCr to RGB RGB to YCbCr Built in 6ch 11 bit DAC Capable of simultaneous output of composite S video YCbCr or RGB Output load resistance
24. ca MAPCAR2 mage ChO z eserved eserved pare pare eserved eserved MAPCAR2in age Ch2 MAPCAR2 h age output sync sinal Common for Ch0 1 2 VSYNC Po PCLK2 Po 1 Po 621 621 621 62 lp lI MAPCAR2 mage output sync signal Comm on for Ch0 1 2 VSYNC No PCLK2No 1 5 No 7 No 9 No MAPCAR2 mahe F Ch0 call I Reserved Reset signal for NTSC encoder decoder dedicated signalto Video F Reserved Reset signal for paralel cam era dedicated signal to board Controlparalbeloutput 0 1394 board output V ideo F board output ControlNTSC output 1394 board output ideo F board output Reserved 5 RESET Reserved CAMERA RESET B Preliminary User s Manual U19880EE 1VOUMOO 22 IMAPCAR2 Video I F Board 444 Plug in phone jack for CHO differential motion J1 Manufacturer Hirose Model TM24RSG 5A 88 Direction of the signal Signal Name Description from FPGA point of view CNO_RX LVDS differential motion reception line side CNO_RX LVDS differential motion reception line side E 9 T WW 4 4 5 Plug in phone jack for CH1 differential motion 42 Manufacturer Hirose Model TM24RSG 5A 88
25. chl data chl ART2 RX P ART2 TX P SYNCIB 2 6 eise 45 1 SR 1113 3 SR 15 5 SR 107 7 1 58 1119 9 SR 121 111 56 123 15 CARZVN chl L3 CLK2II2 2 ch2 ch2 ch2 ch2 ch2 2 data ch2 iata 11 68 125 3 SR 1127 5 J SR 129 7 SR 131 9 SR 133 111 56 135 15 SR 139 CAR2 ch2 wwo sojo 0o ani col Q N pesya ee ae gt 52 gt ES e 90 9o mi L 1 LII V lt u L LS IPS p 1 DDEVENOO SYNCOOB 0 0 SRO ch0_odatal2 SRO Che CONT 0 odatal6 SRO ch1 0 SRO chl odata 2 SRO Cte VOUT chl 6 5 ch2 0 SRO ch2 2 SR0 PARA VOUT ch2 odatal6 SRO Sp RX PP VD i3 p 15 CLK PD VD 17 7 SDA SDA PD VD 19 7 SCL SCL PD VD 21 Power supply ART3 RX P D 7 ART3 TX P D V D 9 SYNCOOB CLK200 ch0 odatall SRO ch0 odata 3 SRO 0 odatal5 SRO ch0_odatal7 SRO chl odatall SRO chl odata 11 chl 5 SRO 13 chl odata 7 1 5680 15 ch2 1 SRO 17 ch2 3 SRO 19 ch2 5 SRO 21 ch2 odata 7 23
26. data sheet 5 7 Equipment connection cable NEC recommends using a category 7 Ethernet cable 7 600MHz 10GBASE T Preliminary User s Manual U19880EE1VOUMOO 41 IMAPCAR2 Video I F Board 6 Revision history Version Date Document Number July2009 U19880EE1VOUMOO o The following revision list shows all functional changes compared to the previous version Chapter Preliminary User s Manual U19880EE1VOUMOO 42
27. es The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances mach
28. ine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above Preliminary User s Manual U19880EE1VOUMOO 2 Table of Contents 1 teme rr M 5 ia aser eov ue dude d fed espe deu ot edu tuu e tesi 5 General overview and block diagrams nnns nnn 6 c Vide
29. minary User s Manual U19880EE1VOUMOO 24 4 4 8 NTSC input RCA Jack J5 Manufacturer Model Jack 4 4 9 NTSC output RCA Jack J6 Manufacturer Model Jack 4 4 10 JTAG connector Manufacturer Model GND 13 14 IMAPCARe Video I F Board CUI INC RCJ 013 White 4 e x CUI INC RCJ 01 1 Black 2 MOLEX 8 331 142 Ground 2 2 5V Power supply 2 5V GND TMS GND TCK GND Ground Test Mode Select 2 5V pull up Ground Test Clock 2 5V pull up Ground Test Data Output 2 5V pull up GND Ground ew ooo RAN EM rv NE We F Ww Wwe j 0 Preliminary User s Manual U19880EE1VOUMOO 25 IMAPCAR2 Video I F Board 4 4 11 Power supply terminal stand CN8 Manufacturer Sato Model ML 950 2 Signal Name Description 12V Power supply 12V 12V Power supply 12V Preliminary User s Manual U19880EE1VOUMOO 26 IMAPCAR2 Video I F Board 5 Hardware component 5 1 FPGA Supplier XILINX Model XC3S2000 4FGG676C 676pinBGA 5 1 1 Image System Block 1 Overview Image System Block is based on Thine IF and NTSC decoder encoder IF Six types of the configuration for the image can be selected by setting the DIP switch SW9 1 3 Description ESO Input 3ch images from the progressive camera to IMAPCAR2 Mode 1 OFF OFF ON Input 2ch images from the progressive camera 2ch color images to IM
30. n 27 YOBIBUSBUSY 28 SV BUSBUSY 29 SV BUSSTAT 30 5 BURST 31 G LOABAL PRESET 32 0 Unsed 3d 5pares KPGA connectins CPU bus W rite sgnal CPU Bus chp sekct VS Hard reset p lt lt V D 14 lt 1 11 42 4 4 4 4 4 4 4 5 5 16 18 VD 20 AR2 PORTO AR2 PORTO AR2 PORTO AR2 PORTO AR2 PORTO AR2 PORTI AR2 PORTI AR2 PORTI AR2 NTP 0 52 CAR2 NTP 2 53 2 CSIRX ___54 2 BB CAR2HDRSTB b6 CAR2DCONI9 b7 CARZ2FALDC 58 YOBIPORT 59 ooo lt lt N L JEL 1 Spares KPGA connections T Wr 1 1 1 L 1 lt C3 olepe ele I gt Spares KPGA connections Spares KPGA connections Spars connections Preliminary User s Manual U19880EE 1VOUMOO 21 IMAPCARe Video I F Board 4 4 3 Video I O connector 2 CN3 CN9 Manufacturer SAMTEC Model QTH 060 05 L D A QSH 060 01 L D A A60 A31 A30 1 ERO LT CN3 CN9 MAPCAR2 mage F ChO CU SJ2 control MAPCAR2 Image nput IF Chl Assign the CPU of ECU SV reserved MAPCAR2 mage F Ch2 MAPCAR2 Inage output F sync signal Common for Ch0 1 2 MAPCAR2 Page output Ch2 MAPCAR2 Ihn age output sync sgnal Common forCh0 1 2 2
31. o Board coger Wu uu m EM 6 3 2 Power Supply block 7 39 FRESCULDIOCK IACI ANN uuu u OTI STEPS 8 34 eroe deos Seife m m Um 9 39 PO B OV SVG W ERU m 10 A SOG CSCI metet 13 EE ieige edeue MR 13 4 1 1 ea PINTO CEC OCE M RE 13 41 2 SW6 user FPGA general purpose 14 4 1 3 SW7T user FPGA general purpose 5 nennen nennen nnns nna 14 214 OWS NTSC encoder uy u unu aee eon EL a ES Desa n tuc eae 15 4 1 5 SW9 general purpose SW for graphic FPGA 15 4 1 6 SW10 general purpose SW for graphic FPGA 16 A OWARE SE Tonene nudius 16 4 15 OW PRESE Terere Seta dius 16 W mperdescnplion c TE 17 4o E E 18 44 CONMECIOMCESCHDUOMN NEIN 20 4 4 1 Video I O connector GNT GN06 Q u uu L unu a un nais smua punapiqa 20 4 4 2 Supervisor connector 2 21 4 4 3 Video I O connector 2 22 444 Plug in phone jack for CHO differential motion J1 23 445 Plug in phone jack for CHO differential motion J2 23 4 4 6 Plug in phone jack for CHO differential motion J3
32. quipment side It is possible to reset camera IF board by the port control by Host SV microcomputer and 1394 boards This reset is done via the RS485 communication Communication route outline is shown below l2C to I2C RS485 Bridge NTSC Decoders l2C to l2C Bridge NTSC Encoders SV m icrocotro le Reset from M APCAR2 boa Internal composition of FPGA chart I2C RS485 communication system Preliminary User s Manual U19880EE 1VOUMOO 31 5 1 3 Reset block NTSC Decoder NTSC Encoders IMAPCARe Video I F Board The reset signal is generated in FPGA as follows is an equivalent signal to DX DONE 1394 reset NTSC Reset Preliminary User s Manual U19880EE 1VOUMOO 32 IMAPCAR2 Video I F Board 5 1 4 Pin assignment The following tables describes the user FPGA pin assign 21 VDEO2A55 C21 Reserved 21 Reserved A22 RESERVED C22 Reserved 22 Reserved Bl 25V JNECDO 1 NDBo5 LVT2SYNCI LVROSYNCO B2 GND 2 89 2 84 J H2 L LVT2SYNC2 2 LVROSYNCI JNEBLANKL GND 4 NDB2 4 LVT2SYNCO K4 LVRISYNCO B5 NEYDO 5 588 5 NDYO 5 LVTISYNCI K5 LVRISYNCI NEYDS 6 6 LVTOSYNCI B21 CAR2CSIRX D21 CAR2CSICLK F21 Reserved 22 Reserved 022
33. s the reset schematic for the IMAPCAR2 video I F board reset VIDEO SIDE FPGA DONE GROBAL PRESET IC XP PROG DX DONE 33V 25V Jc SWPRESET 3 3t02 5V ROM 3 3V SV Connector GROBAL_HRESET SWHRESET DX DONE Preliminary User s Manual U19880EE1VOUMOO 8 IMAPCAR2 Video I F Board 3 4 Clock block diagram The following figure describes the block diagram of the system clock VIDEO SIDE 32MHz FPGA NTSC DEC CLKX2 ND CLKX20 CLKX20 ND_CLKXO NTSC ENC CLKX2 NE_CLK A8MHz gt LVDS LVRO_CLKOUT LVDS LVTO CLKIN TX LVDS LVR1 CLKOUT RX LVDS LVT1 CLKIN TX LVDS LVR2_CLKOUT RX LVR3_CLKOUT 48MHz gt USER SIDE FPGA LVDS LVT2_CLKIN TX LVDS LVT3 CLKIN TX CLKXX 20MHz ND CLKX2O 32MHz ND CLKXO 16 2 NE CLK 27 2 Preliminary User s Manual U19880EE 1VOUMOO IMAPCARe Video I F Board 3 5 PCB overview The following figure shows a PCB overview 110 00 Y m w SW_HRESET_ PRESET ONE mmm C l ms T p DER RA AUS 122 RA60 01 LED23 EH 88 SEEREN RAi20 245 ER i RISS LA TP44 TP45 ze 9999 470444038 A 402
34. urpose SW Initial Description Configuration 7 Preliminary User s Manual U19880EE 1VOUMOO 14 IMAPCARe Video I F Board 4 1 4 SW8 NTSC encoder Initial Configuration 8 1 MOD2 0 Initial Configuration Select Mode Not used Not used Not used Description Input mode control XSW 1 OFFe 0 For more data please see ML86V7655 data sheet PAL NTSC mode select XSW 1 OFFe 0 ON PAL OFF NTSC RGB YCbCr Input select XSW ON 1 OFFe 0 ON RGB Input OFF YCbCr input Progressive Interlaced input select XSW ON 1 OFFe 0 ON Progressive input OFF interlaced input 4 2 2 4 4 4 input select XSW 1 OFFe 0 ON 4 4 4 input OFF 4 2 2 input Progressive Interlaced output select XSW ON 1 OFFe 0 ON Progressive output OFF interlaced output SW9 2 1 XSW ON O OFFe 1 ON Mode 0 ON OFF Mode 1 OFF ON Mode 2 OFF OFF Mode 3 For details of each mode please refer to figure 5 1 1 to 5 1 4 When connecting 1394 board mode is changed to mode 2 forcedly Preliminary User s Manual U19880EE1V0UM00 15 IMAPCARe Video I F Board 4 1 6 SW10 general purpose SW for graphic FPGA mem is a button switch for board reset By pushing this switch the following device will be reset and the FPGA will be reconfigured as well e NTSC decoder e NTSC encoder and e FPGA internal circuit 4
35. z o t1 EH553501 J F Hes t 17 1 TP78 ipes 898 5666 UU mm ee ers 2 8 EH g CE Titi T ni S i62 i E Fa a Ak s ssssqesssesssceseoessees Bad TILLLILLLLLLLLLLLLLLLLLLLI LEDS uir m E z E p m Ribs s s m vcf TTILLLLLLISTLITLILLLLLITIIT EI m S S eun PREPREBPETEREPPRPRPRRRPSRPREEEE 45 LEGI SHE B 75 Lj ins Eh more NU 50 sssssssesesssesensesesesos EOS lor NTS 4 TTI TAI HER 159 111118 aH ee TILILTLTILLUIIIIIITITTITITTIT ET icd 8 XG3520 ICE Pt zu 043 ma Jamu LC mm 5 Ek Hi CEZ S NN ida CAE Piel am o it mm 1 rir Sinir LIU re zi mmi ee m mm Emz m mmum pn m He gt m Ll gt m m

PUM IMAPCAR2 Video I/F Board

Contents

Download Pdf Manuals

Related Search

Related Contents