The design of a Master Test Controller for a system
Contents
1. clock frequency will be 12MHz an the minimum clock frequency will be 750 kHz The TCK clock can be turned on or off from the programming interface using a bit in the control register Table 13 TCK programmable clock frequencies RATE SEL TCK clock frequency Actual clock frequency MHz SYS CLK 4 SYS CLK 8 SYS CLK 16 SYS CLK 32 SYS CLK 64 MTC CONFIG The CONFIG block will be used to setup the different operating modes of the MTC The config register will be written from the PPC with the selected operating mode and will control the connections of signals between the MTC and the JTC and the JTAG test port Writing test programs for MTC The MTC will use a test program stored in the test program memory to run the actual JTAG testing This program consists of a number of tasks that will perform the test ing of the JTAG logic in the DBC other ASICs on the board or in the system Compiling the test program Before the test program can be loaded to the test program memory it must be com piled into a binary format 32 bit words This can be done in many different ways but a simple solution is to use the verilog simulator to generate the compiled code Every task is implemented as a verilog task and for every test program a verilog test case using the tasks are constructed see Appendix Running the verilog simulator with the testcase will generate the compiled code The compiled code will be s2. Compare TDO recorded to expected data 5 Conclusions The design of the MTC shows that a JTAG tester can easily be fitted into a system on chip design Having a JTAG tester on the board will open up many new testing opportunities during the whole product life cycle The definition of a simple JTAG test language JTL that can be used for writing all kind of JTAG tests will make the pro gramming of MTC an easy task The debugging features can be used in the lab to help the board designer in the prototype testing New test features can be added and controlled from the MTC The possibilities are infinite Acknowledgement would like to thank Gunnar Carlsson and Tom Stadler for their support and techni cal assistance during the MTC design phase References 1 On Chip Peripheral Bus Architecture Specifications v 2 1 2 IEEE Std 1149 1 1990 with supplements IEEE 1149 1 1993 and IEEE 1149 1b 1994 3 PPC440x6 Embedded Processor Core User s Manual SA14 2758 01 22 24 Appendix Test program example 1 Read identification code from the IDCODE register Load the IDCODE instruction and shift out the 32 bit identification code parameter INSTRUCTION LENGTH 4 parameter DATA LENGTH 32 parameter IDCODE 4 b0010 parameter ALL TDO DATA 290 parameter DEVICE IDCODE 32 h14012049 SetTdoRecordingMode ALL TDO DATA TestResetKeepingTrstzLow 10 Loadlnstruction INSTRUCTION LENGTH IDCODE SetExpect
3. M TDI TDO DEVICE 2 TDO TDI DEVICE 3 TDO TDI Figure 6 MTC external test setup DBC included BOARD1 BOARD2 DEVICE 1 TDI TDO TET DEVICE 3 DEVICE 2 TDO TDI TDO TDI Figure 7 MTC system test setup DBC included 7 24 1 3 Interface Description 1 3 1 Block Diagram O INTERRUPT CT I OPB SELECT I OPB FWXFEREO HWXFER b I OPB ABUS I OPB DBUS O_OPB_DBUSEN O OPB XFERACKC OPB interface OPB FWACK cH HWACK cH OPB ERR ACKch O OPB TOUTSU RETRY C O_OPB_DBUS lt I RESETS CEI OPB REGS MTC PROGRAM RA MTC TESTGEN MTC CONFIG MTC TDO EN MTC ENB STATUS MTC TDO TMSI MTC TMSO IMTC TCKI START STOP CONT MER MTC TCKO ms Tad TRSTZI TMS x TRSTZ unis 22 TDI EX ADDRESS Test result DATA fTC TDI STORE storage JTC TMS START STOP RESET TDO BITS TRSTZ NM IPC TDO E TDO ENB CONTROL REG STATUS_REG EXECUTE_REG DEBUG I RESETA Figure 8 MTC block diagram B IEEE 1149 1 Test Bus 8 24 1 4 1 4 1 Block Description MTC OPB REGS The MTC OPB REGS block has 4 addressable reg
4. Write to the execute register with the reset bit set bit 3 The TCK clock must be run ning for reset to fully reset the MTC Looping the MTC When the loop mode is enabled the MTC test will stay in a loop until the start bit or loop mode bit is cleared Test result comparison When the test has been stopped the result memory can be read and compared against expected data Read the status register bits 31 20 to find out how many bits of TDO data that have been stored Use the following sequence to find out if an error has occurred loop i 0 i lt ExpectedDataSize i errors i TestResult i xor ExpectedData i and MaskData i If the error array contains a 1 an error has occurred 19 24 4 1 Writing a software driver for MTC The MTC must operate in a number of testing application The software driver must be written to support all these application Table 15 page 21 The tests will be of two kinds automated tests and debug tests For every test application a test set will be generated When a test application is listed as destructive it will destroy the func tional setup of the board Test sets A test set is a set of test programs load modules that will be executed in sequence Every test application can have its own test set or share test set with another appli cation A test set is a list of addresses to the test programs used Figure 10 page 20 All test sets and load modules should be sto
5. Debug Start up test Used when powering up the system Automated Maintenance test Used when the system is up and running Automated Fault isolation Used during fault isolation in the system Debug Repair center test Short command Used in the board repair center Table 16 Debug command Description Select test set Automated debug Arguments N Register affected None Run complete test set N None Load test program Load module N None Reset MTC None Enable or disable clock ENB DIS Control reg 7 Select MTC operating mode BOARD INT EXTI EXTE SYSISYSE Control reg 3 0 Set TCK clock speed 48163264 Control reg 6 4 Enable or disable single step mode ENB DIS Control reg 8 Set TDO recording mode ALL INSTR DATA NONE Control reg 10 9 Enable or disable loop mode ENB DIS Control reg 11 Enable or disable interrupt ENB DIS Control reg 12 Read status register None Status reg 21 24 Table 16 Debug command Short command Description Arguments Register affected Read debug register Debug reg Read control register Control reg Start MTC Execute reg 0 Stop MTC Execute reg 0 Single step MTC test program Execute reg 1 Continue MTC execution after pause Execute reg 2 Read TDO recording RAM
6. 9 shows the tap controller states supported by the test generator The shaded states are not supported and will never be entered Dotted lines shows state transitions not supported The MTC TESTGEN block performs a reclocking of the TMS TDI and TRSTZ sig nals to provide save timing margins The negative edge of the TCK clock is used as the reclocking clock Table 6 MTC TESTGEN task format 1 Bit 31 Bit 30 Bits 29 4 Bits 3 0 Not used Instruction code Bits 29 16 Bits 15 4 Bits 3 0 Table 7 MTC_TESTGEN task format 2 Not used Number of TCK cycles 12 bits used Instruction code Bit 30 Bits 29 4 Bits 3 0 Table 8 MTC_TESTGEN task format 3 1 0 Number of TCK cycles 26 bits used Instruction code Table 9 MTC_TESTGEN task format 4 Bit 31 Bit 30 Bis Bits 27 16 Bits 15 4 Bits 3 0 29 28 j 1 1 Not used Number of shift data Number of shift instruction Instruction code 0 1 TDI test data 0 1 TDI data 0 0 Last TDI data bit 30 0 114 Table 10 TESTGEN Instruction Codes Value Description Task format 4 b0000 No operation 1 4750001 Generate test reset 1 TSTSZ low for x cycles 2 4 b0010 Generate test reset 2 TMS high for x cycles 2 4 b0011 Load JTAG instruction register 4 4 b0100 Load JTAG data register 4 Table 11 TESTGEN Instruction R
7. record Don t save TDO data during shiftir TDO no record Don t save TDO data during shiftdr Loop mode 1 enabled Interrupt enable 1 enabled Table 4 Status register description Bit Bit name Description Busy bit 0 Test generation stopped running Pause bit 0 not paused 1 paused Test finished 1 test have finished completed 6 3 Instruction code 4 bits Current loaded task Pause in shiftdr 1 when paused during shift data 13 8 Result RAM address 6 bits Last address written in TDO recording RAM 25 14 TDO bit counter 12 bits Counts the number of TDO bits received 31 26 Reserved For future use Table 5 Execute register description 0 Start stop of MTC 1 Single step MTC one task 2 Continue MTC after pause 3 Reset TESTGEN MTC TESTGEN The MTC TESTGEN block contains the JTAG test generator The test program will be read from the TESTPROGRAM RAM executed by the 10 24 TESTGEN test generator The test program is built from a number of tasks that will operate on different JTAG registers All tasks in the test program will be executed in sequence and the test execution will stop when the End of task instruction is ex ecuted or a stop signal is sent to TESTGEN Task comes two formats Task format 1 2 and 3 are used for tasks that do not use any TDI data and task format 4 for all tasks that use TDI data Figure
8. N_LENGTH 4 parameter BOUNDARY_SCAN_LENGTH 8 parameter TDO_SHIFTDR 2 b01 parameter SAMPLE 4700011 parameter BYPASS 4701111 SetTdoRecordingMode TDO_SHIFTDR TestResetKeepingTrstzLow 10 LoadInstruction 4 INSTRUCTION LENGTH BYPASS BYPASS SAMPLE BY PASS ReadWriteDataRegister 1 1 BOUNDARY SCAN LENGTH 1 11 b0 SetExpectedData 14 1 BOUNDARY SCAN LENGTH 1 11 bxx0110xxxxx EndOfTestProgram 24 24
9. The design of a Master Test Controller for a system level Embedded Boundary Scan Test architecture Sven Ake Andersson Ericsson AB Stockholm Sweden sven ake andersson ericsson com Abstract Boundary scan IEEE 1194 1 is today implemented in every ASIC and FPGA and is only used during production test of chips and boards It is then left unused for the rest of the product life cycle That is a waste of resources Adding an on board JTAG tester will change that scenario Tests can then be run at power up of the system or as maintenance tests when the system is up and running If the test program is stored on the board tests can also be run at a repair center The tester can also be used when debugging the board in the lab All tests controlled from the test access port TAP can be executed from the on board tester This paper describes an implementation of an on board JTAG tester called a Master Test Controller MTC The MTC has been designed as an IP block in an system on chip design The ASIC is manufactured in their 80nm CMOS process The design takes up no more than 60k gates and can easily be fitted into any ASIC or FPGA design The MTC is controlled from an embedded PowerPC microprocessor but can easily be adopted to use any type of processor To support the programming of the MTC a new JTAG test language JTL has been defined The test language uses the same syntax as verilog and test programs can be compiled using a sta
10. a specified number of TCK clock cycles Syntax TestResetKeepingTrstzLow TCK cycles TCK cycles is an integer between 1 and 4095 TestResetKeepingTmsHigh Generate a test reset by keeping TMS high for a specified number of TCK clock cy cles Syntax TestResetKeepingTmsHigh TCK cycles TCK cycles is an integer between 5 and 4095 LoadInstructionRegister Load JTAG instructions into all instruction registers in the scan chain Syntax LoadlInstructionRegister instruction length instruction code instruction length is an integer between 1 and 4095 instruction code is a verilog register value with maximum 4095 bits Examples 20 b10101101110111110000 64 h123456789abcdeO 10 b1111111111 5 00000 concatenation LoadDataRegister Load data into all data registers in the scan chain Syntax LoadDataRegister data length data content data length is an integer between 1 and 4095 data content is a verilog register value with maximum 4095 bits LoadDataRegisterPause Load data into all data registers in the scan chain Pause in Pause Dr state when finished This way a new testprogram can be loaded The new testprogram must start with LoadDataRegisterContinue Syntax LoadDataRegisterPause data length data content 16 24 2 3 6 2 3 7 2 3 8 2 3 9 2 3 10 data length is an integer between 1 and 4095 data content is a verilog register value with maximum 4095 bits LoadDataRegister Continue Load data int
11. edData INSTRUCTION LENGTH 4 b0001 ReadWriteDataRegister DATA LENGTH 32 h0 SetExpectedData DATA LENGTH DEVICE IDCODE EndOfTestProgram Test program example 2 Setup and run a MBIST test Load the 5 ENABLE instruction and enable all 8 MBISTs Load the RUNBIST instruction to start the MBISTs Wait in Run Test Idle state until the test has finished Load the instruction MBIST RESULT Read the re sult by shifting out the date from the MBIST RESULT data register Expect all bits set to one parameter INSTRUCTION LENGTH 4 parameter DATA LENGTH 8 parameter TDO_SHIFTDR 2 b01 parameter MBIST_ENABLE 4700100 parameter MBIST_RESULT 4 b0101 parameter RUNBIST 4700110 parameter MBIST_RUNTIME 1000000 SetTdoRecordingMode TDO_SHIFTDR TestResetKeepingTrstzLow 10 LoadInstruction INSTRUCTION LENGTH MBIST ENABLE ReadWriteDataRegister DATA LENGTH 8 b11111111 SetExpectedData DATA_LENGTH 8 bxxxxxxxx Loadinstruction INSTRUCTION_LENGTH RUNBIST WaitlnRunTestldle MBIST_RUNTIME LoadInstruction INSTRUCTION_LENGTH MBIST_RESULT ReadWriteDataRegister DATA LENGTH 8 b00000000 SetExpectedData DATA LENGTH 8 b11111111 EndOfTestProgram 23 24 TDI TDO Test program example 3 Setup a test to sample the inputs on device 3 in the board scan chain DEVICE 1 DEVICE 2 2330 BYPASS Lecce DEVICE 4 o BYPASS parameter INSTRUCTIO
12. eger between 0 and 1023 testcase identity is an integer between 0 and 1023 testcase revision is an integer between 0 and 4095 SetTdoRecordingMode Stores information about the TDO recording mode of the MTC The corresponding recording mode must be programmed in the control register setup Syntax SetTdoRecordingMode Mode Mode Recording 0 Record TDO data during instruction and data shift 1 Record TDO data during data shift only 2 Record TDO data during instruction shift only 1824 2 4 3 3 1 3 1 3 3 2 3 data recorded SetExpectedData Use the SetExpectedData task to specify the expected TDO data after every instruc tion that will generate a TDO output Syntax SetExpectedData number of bits expected data number of bits is an integer between 1 and 4095 expected data is a verilog register value with maximum 4095 bits X can be used to specify not known or don t care data bits Operating the MTC When the test program is loaded the MTC can be activated Perform the following steps to run a JTAG test using the MTC Setup the MTC Load the config register to set the TCK clock rate enable TCK disable saving of TDO data enable disable single step mode and loop mode Starting the MTC Write to the execute register with the start bit set bit O Stopping the MTC Write to the execute register with the start bit cleared bit O This will also clear the interrupt if set Resetting the MTC
13. egister task format 2 Bit Description 3 0 Instructions Code see above 15 4 Number of TCK cycles 29 16 Not used 30 0 more words of data follows for this task 3l 1 instruction word Table 12 TESTGEN Instruction Register task format 4 Bit Description 3 0 Instructions Code see above 15 4 Number of bits to load instruction 1224 Table 12 8 Instruction Register task format 4 Bit Description 27 16 Number of bits to load of TDI data 29 28 Not used 30 1 more words of data follows for this task 31 1 instruction word a Pe Figure 9 flow chart supported by TESTGEN 1 4 3 MTC TDO RECORD RECORD block is used as a recorder for data The data will be saved when in shiftir or shiftdr state TESTGEN block The saving of TDO data is enabled from the control register The TDO data will be stored into a 32 bit register right justified When the 32 bit register has been filled it will be saved in the MTC DATA RAM register array 1324 1 4 4 1 4 5 241 2 2 TCKGEN TCKGEN block generates the clock to be used as the JTAG test clock The TCK clock frequency can be programmed to six different frequencies With the SYS running at 48MHz the maximum
14. isabled MTC system test Active Test reset state Driven from MTC DBC excluded MTC system test Active Active Driven from MTC DBC included 1 2 1 External test The MTC can run external tests on other JTAG compliant device on the same board You can for example setup and run MBIST to test memories in other ASICs on the board To TDO output from the last device in the JTAG scan chain will be connected to the TDI EX pin Figure 5 page 6 In external test mode the DBC can be excluded or included in the JTAG board scan chain Figure 6 page 7 If the DBC is excluded the JTC will be kept in test reset state 3 24 Drivers enabled MTC TDI JTC 1 2 2 JTC TDI JTC TMS JTC TCK JTC TRSTZ JTC TDO ENB JTC TDO MTC MTC ENB MTC TCK MTC TMS MTC TRSTZ MTC TDO ENB 4 Figure 2 External Test Operating Mode Internal test v D gt TRSTZ K Ri TDI EX Driver enabled TDO TCK TMS BE The MTC can run internal JTAG tests on the DBC ASIC It is possible to setup and run MBIST to test memories read IDCODE sample boundary scan register and ex ecute other JTAG instructions When the MTC is used in internal mode the testbus drivers will be disabled When the testbus drivers are disabled by keeping MTC ENB low the pull down resistor on TRSTZ will hold TRSTZ low and thereby setting all other JTAG de
15. isters and two register arrays Table 2 MTC address map Register name Register Register 2 size OPB type of access Address bits hex MTC TESTPROGRAM RAM 64x32 WRITE 000 Ofc MTC DATA RAM 64x32 AD 100 1fc 2 RE Control 32 READ WRITE 00 Status 32 READ 204 Execute 32 READ WRITE 208 Debug 32 READ 20c The control register will be used for setting up the MTC operating mode before the test starts see table 5 The status register keeps track of the MTC status and can be read at any time The execute register controls the start stop continue after pause and single stepping of the test program The debug register can be used when debugging a failing test It will hold information about the internal logic of the MTC that can be of help when trying to isolate the failure One register array TESTPROGRAM RAM is used for storing the compiled test program and one other array DATA RAM is used for storing the test result Table 3 Control register description Bit Bit name Description 0 Config bit 0 Controls the CONFIG block 1 Config bit 1 See table 1 2 Config bit 2 3 Config bit 3 4 clock divide bit O Controls TCKGEN block 5 TCK clock divide bit 1 6 TCK clock divide bit 2 7 Enable Enables TCK clock 8 Single step mode 1 enabled 9 24 1 4 2 Table 3 Control register description Bit name Description TDO no
16. ndard verilog simulator There are 13 tasks that can be used to build any kind of JTAG test sequence 1 Introduction The Master Test Controller MTC is a fully IEEE 1149 1 compliant test generator that can be used for running JTAG test sequences both on internal logic and external devices The test sequence setup is controlled from the on chip microprocessor a PowerPC 440 The MTC and the IBM JTAG Test Controller JTC uses a common standard 5 pin bidirectional testbus plus one extra testpin TDI EX The ena ble signal ENB will only be activated when running the in external mode In all other cases this bus will look like a standard JTAG bus After power up reset the MTC will be deactivated and can only be activated by the programming in terface from the PowerPC microprocessor The MTC has been implemented in a SOC design called DBC Device Board Controller 1 24 5 TMSI JTC MTC TRSTZO TRSTZ MTC TRSTZI TDI G TDI EX TDO JTC TDI TDI JTC TMS MTC TDI EX MTC TDO ENB JTC TCK JTC TRSTZ JTC TDO ENB JTC TDO CE1 1 1 Figure 1 The Master Test Controller Running the MTC The MTC when activated can be used for running internal JTAG tests on the DBC or e
17. o all data registers in the scan chain Used after the loading has been paused Will continue from the Pause Dr state Syntax LoadDataRegisterPause data length data content data length is an integer between 1 and 4095 data content is a verilog register value with maximum 4095 bits LoadDataRegisterAgain Load data into all data registers in the scan chain Used after the loading has been paused Will continue from the Pause Dr state and will stop in pause dr Syntax LoadDataRegisterAgain data length data content data length is an integer between 1 and 4095 data content is a verilog register value with maximum 4095 bits LoadInstructionAndData Load JTAG instructions into all instruction registers in the scan chain and thereafter load all selected data registers without going to Run Test Idle state in between loads Syntax LoadInstructionAndData instruction length instruction code data_length data content instruction length is an integer between 1 and 4095 instruction code a verilog register value with maximum 4095 bits data length is an integer between 1 and 4095 data content is a verilog register value with maximum 4095 bits LoadDataAndInstruction Load all selected data registers and thereafter load JTAG instructions into all instruc tion registers in the scan chain without going to Run Test Idle state in between loads Syntax LoadDataAndInstruction instruction length instruction code da
18. red in a flash memory on the board This way the board will carry all its test application even when removed from the sys tem at a repair center Test set 1 Board test Test set 2 Lab test Test set 3 Start up test Test set 4 Maintenance test Test set 5 Repair center test Load module 1 identity Start address Load module 3 identity Load Module 1 Start address Load module 4 identity Start address Load Module 2 End of test set Load Module 3 Load Module 4 Figure 10 Flush memory data storage 20 24 4 2 4 3 Application Board test Automated test An automated test will run all tests in sequence after a start signal is issued The test result from the first test will be compared to expected data and if there is an error the test will stop and report the error If there is no error the next test will start and if no errors are reported this will go on until all tests have been run The end of test set word all zeros signals the end of the test set Debug test When used in debug mode the MTC will be controlled from a terminal Debug com mands will be issued to control the MTC behaviour All debug commands that are needed are listed in Table 16 page 21 Table 15 MTC test applications Description Used during production testing of the board Automated Destructive Lab test Used during debugging of the board in the lab
19. ta length data content instruction length is an integer between 1 and 4095 instruction code a verilog register value with maximum 4095 bits data length is an integer between 1 and 4095 data content is a verilog register value with maximum 4095 bits WaitInRunTestIdle Generate a wait Run Test ldle state for a specified number of clock cycles Syntax WaitlnRunTestldle TCK cycles 174 2 3 11 2 3 12 2 3 13 2 4 24 1 2 4 2 TCK cycles is an integer between 1 and 67108863 PauseInRunTestIdle Generate a pause in Run Test Idle state until the continue bit is set in the execute register Syntax PauselnRunTestldle EndOfTest The EndOfTest task should be the last task in the test program When encountered it generates an interrupt by setting the O INTERRRUPT signal high if the interrupt enable bit is set Syntax EndOfTest NoOperation The NoOperation task can be inserted anywhere in the test program It will generate a few clock cycles and the test generator will stay in Run Test Idle mode Syntax NoOperation Auxiliary tasks The following task will only put data into the load module file See Load Module de scription for more information about the data format LoadModuleldentity Stores information about the design the testcase in the first word in the load module Syntax LoadModuleldentity design identitytestcase identitytestcase revision design identy is an int
20. tored in a load module file ready to be loaded to the PPC program memory Load module description After compilation of the test program a load module will be generated see table be low The mask data will be calculated from the expected data When the expected data is 0 or 1 the mask data will be set to 1 When the expected data is x the mask data will be set to O 1424 Table 14 Load module Address Content 32 bit word Load module identification Load module size number of words TDO recording mode Number of TDO bits expected Number of TCK cycles to complete the test Address to test program Start test program Test program size number of words Address to expected data Start expected data Expected data size number of words 2 3 4 5 6 7 8 9 Address to mask data Start mask data 10 Mask data size number of words Start test program Compiled test program Start expected data Expected data Start mask data Mask data 0 2 mask 15 24 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 JTAG Test Language JTL The following 13 tasks should be sufficient for all kinds of JTAG tests that will be needed All tasks except for the test reset tasks will start from the Run Test ldle state and return to the Run Test Idle state when finished TestResetKeeping TrstzLow Generate a test reset by keeping TRSTZ low for
21. vices on the board in Test Logic Reset State 4 24 Drivers disabled PPC Y D TCK ENB 7 0 MTC TCK RI P ee cus gt MTC_TRSTZ y MTC TDO B D gt TRSTZ MTC TDO ENB MTC TDI i Ed JTC JTC Ri TDI JTC_TMS JTC TRSTZ Driver disabled JTC_TDI 3 TB6 al p JTC_TDO_ENB y Figure 3 Internal Test Operating Mode 1 2 3 System test In system test mode the MTC can control other boards in the system The JTAG scan chain can include any number of devices on any number of boards Figure 7 page 7 The limiting factor is the drive capability of the MTC In system test mode the DBC can be excluded or included in the JTAG board scan chain If the DBC is excluded the JTC will be kept in test reset state 1 2 4 Board test In board test mode the MTC is deactivated and all the 5 test signals will connect to the JTC only All JTAG compatible devices on the board will be connected into one scan chain Figure 4 page 6 An external JTAG tester will drive the JTAG test se quences 5 24 DEVICE 1 TDI TDO JTAG TESTER DEVICE 2 TDO DEVICE 3 TDO TDI TDI Figure 4 Board test setup DEVICE 1 TDI TDO DEVICE 3 DEVICE 2 TDO TDI TDO TDI Figure 5 MTC external test setup DBC excluded 6 24 DEVICE 1
22. xternal tests on other JTAG compliant devices on the board or in the system The device driver loads compiled test programs into the TESTPROGRAM RAM register array Figure 8 page 8 MTC TESTGEN reads the test program and executes the different tasks in se quence When the test is running the relevant TDO data will be recorded by the MTC TDO RECORD block and stored in the MTC DATA RAM register array When the test has finished the TDO data can be read by the PPC and compared to expected data The status register will hold the number of TDO bits recorded PPC to MTC data transfer The MTC exchanges information between the PPC device driver and the MTC using the On chip Peripheral Bus OPB see Ref 1 Interrupt handling The MTC will generate an interrupt pulling O INTERRUPT high when the test has finished An interrupt will also be generated after an pause shiftdr has occurred The status register should be read after an interrupt to find out the cause of the interrupt The interrupt is enabled by setting one bit in the control register 2 24 1 2 Operating Modes The MTC can be programmed to operate in the following modes Table 1 operating modes External Testbus Board test Inactive Active Driven from external tester MTC external test Active Test reset state Driven from MTC DBC excluded MTC external test Active Active Driven from MTC DBC included MTC internal test Active Active D
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