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1. Number of events pending 3 FED Mon iv FED Mon fedstop fedstop Event amp BX Counters are RESET fedstop FED data acquisition Run is STOPPED FED Mon fedstop Version 2 0 9 January 2001 FED Mon User Manual CMS FED PMC 2001 6 Advanced Operations 6 1 Updating Firmware in Flash EEPROM The FED PMC firmware for the Xilinx FPGA is stored onboard in a Flash EEPROM The Flash device is loaded prior to delivery with the standard firmware design file Alternative firmware designs are made available from the anonymous ftp server address ftp te rl ac uk directory cms fed fed pmc firmware The Flash contents can be updated with a new firmware file using the following procedure IMPORTANT Updating the firmware design is not a common practice and may considerably alter the functional behaviour of the FED PMC If in doubt consult an expert before doing it Once the Flash is reprogrammed the FPGA firmware is permanently updated The procedure is as follows i Reset the RIO2 ii First clear a block of memory for the new Xilinx file PPC Mon fm w 100000 200000 0 PPC Mon iii Load the Xilinx file rbt raw bit file from the tftp server into the cleared memory block PPC_Mon gt load le fpga filename 100000 network boot loading file fpgav0r2p rbt from server 130 246 40 163 ethernet local address 00 80 a2 00 8a 33 ethernet address of server 08 00 07 1e 2a c5 loading at address 100000 tft
2. CMS Front End Driver PMC FED Mon Manual Version 2 0 January 2001 F DO J Coughlan Rutherford Appleton Laboratory FED Mon User Manual CMS FED PMC 2001 1 Contents 1 2 3 4 7 8 CONTENTS A Oe eee ees A e 2 FOREWORD sessies sie esca area cine sees oe Gees ive 8 oles sedes vee E AAA AA 4 INTRODUCTION sees va A AS AA AAA A AAA 4 GETTING STARTED e n oie n eno revis tostis tosts n s rn ner gam de vee ARAS uvae ker ERE ai ee 5 4 1 GETTING A COPY OF THE FED MONPROGRAM ese ese se IH mese he esses esse essei ese se essei e esser enne 5 4 2 LOADING FED MON ONTO RIOZ 2 x scenes outa sos eene eem petuo a EG Oe ee ee sees Ove go ee ge eg ee Deer t deep 5 4 3 RUNNING EED MON eV eI euin n e ID EE E e NN e EE ye 6 DATA WiVSb CTm 8 5 1 RUNNING WITH THE PCI CLOCK AND SOFTWARE TRIGGERS ee se ee ee es ee ee ee se ee eme ehe sese ee etes sese e serene 8 ADVANCED OPERATIONS sesse sesse sies sees sed sees oe Seeds sie ee deed Tssa oe ee oos ve ee ve dee ee SS Ee see 10 6 1 UPDATING FIRMWARE IN FLASH EEPROM ee ee ee ee ee ese ee ee ee ee ee ee ee ee ee ese ee ee ee ee es ee esse ese ere nen 10 6 2 LOADING FPGA DIRECTLY FROM FILE ese se ee ee ese ee se ee ee ee ee ee ee ee ee ee ee ee ee ee ee esse eese e esse e sese ese e enne 12 TROUBLE SHOOTING WITH FED MON so sessssesese
3. 000000ab Clock source 0 Clock source PCI CLOCK Clock delay 0 Trigger source 0 Trigger source gt FRONT PANEL TRIGGER Trigger mode 0 Trigger mode START DIGITISATION adc chan mask aa ADC chans 0 amp 1 are lt lt ENABLED gt gt 2 amp 3 are lt lt ENABLED gt gt 4 amp 5 are lt lt ENABLED gt gt 6 amp 7 are lt lt ENABLED gt gt ADC Sample Freq 0 ADC Sample Size 256 Number of Filled Buffers 0 FED_Mon gt See also fedstat fedmem fedbrg Version 2 0 38 January 2001 FED Mon User Manual CMS FED PMC 2001 9 20 FEDLATFEP Name fedlatfep Send Lattice command to load Xilinx from Flash EEPROM Syntax fedlatfep Parameters none Description Sends the Lattice command to load Xilinx from Flash EEPROM WARNING This command is for Experts only Misuse can disrupt operation of card necessitating a hardware reset to recover E g should only be called if Xilinx is not already loaded Example Load Xilinx from Flash EEPROM FED Mon fedlatfep fedlatfep send Lattice command to load fpga from flash eeprom FED Mon See also Version 2 0 39 January 2001 FED Mon User Manual CMS FED PMC 2001 9 21 FEDLATRD Name fedlatrd Read bits via serial line connecting PCI bridge to Lattice CPLD Syntax fedlatrd fedlatrd number reads Parameters number reads gt
4. address offset gt offset from FED memory base number reads gt number of longs to read amp display Description Displays memory contents starting from base of DPM If no arguments are passed the first location in the DPM is displayed Example Display first 4 long words in DPM FED Mon feddp 0 4 read op 000 address c0000000 data 01030111 read op 001 address c0000004 data 01100110 read op 002 address c0000008 data 010e010f read op 003 address c000000c data 0110010d FED_Mon gt See also fedfp fedscp and PPC_Mon command dm Version 2 0 29 January 2001 FED Mon User Manual 9 12 FEDDPMFL Name Syntax Parameters Description Example See also Version 2 0 feddpmfl Fill entire DPM with identical value feddpmfl data data 32 bit data value to fill in all locations of dpm Fill entire DPM with identical value Fill entire DPM with beefface FED Mon feddpmfl beefface feddpmfl Fill entire DPM with identical value feddpmfl DPM filled everywhere with Sbeefface FED Mon check new contents of dpm using PPC Mon dp command dpm base address obtained with fedmap FED LR w c1200000 0xc1200000 00ef00ce 00ef00ce 00ef00ce 00ef00c 0xc1200010 00ef00ce 00ef00ce 00ef00ce 00ef00c 0xc1200020 O0ef00ce 00ef00ce 00ef00ce 00ef00c 0xc1200030 00ef00ce 00ef00ce 00ef00ce 00ef00c 0xc1200040 O0ef00ce 00ef00ce 00ef00ce 00ef00c
5. 9 35 FEDSTAT Name fedstat display FED PMC status Syntax fedstat fedstat option Parameters option 7 b show bridge status only r show fed registers status only Description Display status of FED PMC If no arguments are passed full settings are displayed Example Display full settings of FED PMC FED Mon fedstat fedstat fed pmc full status bridge config regs pci cfg base 80802000 vendor id 908010b5 bridge cmd status reg 02800007 dpm pci mem base rio c0000000 fifo pci mem base rio c0100000 bridge pci mem base rio c0100100 bridge local regs pci mem base c0100100 dpm local base 00000001 dpm window size Sfff00000 dpm descriptor 000301c3 regs local base 00100001 regs window size Sffffff00 regs descriptor 00000243 mode amp arbitration 01200000 eeprom cntrl 88000000 big endian 00000004 fedstat ATTENTION gt If we stop here the Xilinx is NOT Loaded fedstat reset default bridge configuration fedstat reset default bridge configuration fed regs 8 pci mem base c0100080 Digitisation is DISABLED Test mode is ENABLED Throttle is DISABLED throttle threshold 000000ab Version 2 0 60 January 2001 FED Mon User Manual Clock source 0 Clock source gt Clock delay 0 Trigger source 0 II Trigger source Trigger mode Trigger mode S
6. Sffffff00 PCI9080 LASIRR regs descriptor 00000243 PCI9080 LBRD1 mode amp arbitration 01200000 PCI9080 MARBR eeprom cntrl 98000070 PCI9080 CNTRL big endian 00000084 PCI9080 BIGEND INFO gt Xilinx FPGA status at start fedxlst Xilinx Load status INIT 1 DONE 0 INFO gt Loading Xilinx from Flash EEPROM takes approx 5 secs INFO gt End Xilinx load from Flash after 4559 msecs fedxlst Xilinx Load status INIT 1 DONE 1 fedbrg default values were set bridge local regs pci mem base c1300100 dpm local base 00000001 PCI9080_LASOBA dpm window size S fff00000 PCI9080 LASORR dpm descriptor 030300c3 PCI9080 LBRDO regs local base 00100001 PCI9080 LAS1BA regs window size Sffffff00 PCI9080 LASIRR regs descriptor 00000243 PCI9080 LBRD1 mode amp arbitration 01200000 PCI9080 MARBR eeprom cntrl 98020070 PCI9080 CNTRL Version 2 0 January 2001 FED Mon User Manual CMS FED PMC 2001 big endian 00000084 PCI9080 BIGEND INFO gt Setting up FED specific registers with defaults ATTENTION gt If we stop here the Xilinx is NOT Loaded fedinit using default values fedinit WARNING gt If Bus errors here the CLOCK may NOT be running fedinit WARNING gt If we stop here the Xilinx may NOT be loaded fedstat fed register status only fedstat ATTENTION gt If we stop here the Xilinx is NOT L
7. fedmem fedplxeper fedplxepfl fedplxeprd fedplxepwr fedresl fedres2 fedrev fedrout fedscp of scope Display Set ADC registers FED PMC Bridge PCI LOCAL registers Display number of occupied buffers in dpm Purge remaining occupied buffers in dpm Display FED program variables for debugging Enter Exit FPGA Clock configuration mode Display Set Clock source amp delay Reset Event and Bunch Crossing counters Display Set Digitisation mode Read from FED addresses Fill entire DPM with identical value Read from Flash EPROM Write to Flash EPROM Read FED fifo contents Fill FED addresses Read FED serial number Store FED serial number Initialise FED registers Read bits from Lattice serial line Write a bit to Lattice serial line Send Lattice command to load fpga from flash eeprom Load Xilinx rbt file from rio memory to FPGA Load Xilinx rbt file from rio memory to Flash EEPROM Display FED address map Initialise FED PMC Bridge PCI CFG registers Erase contents of PLX serial eprom Fill contents of PLX serial eprom with default values Read contents of PLX serial eprom Write to an individual location in PLX serial eprom Reserved command don t use Reserved command don t use Display revision info of FED h w and s w Readout and display fed event Continuous read or write from to FED Cl Gl GI Nb old meaning 1
8. 829232 nlines 1770 xp 1770 002ca905 total bytes 829701 nlines 1771 xp 1771 002caada total bytes 830170 nlines 1772 xp 1772 002cacaf total bytes 830639 nlines 1773 xp 1773 002cae84 total bytes 831108 nlines 1774 xp 1774 002cb059 total bytes 831577 nlines 1775 xp 1775 002cb22e total bytes 832046 nlines 1776 xp 1776 002cb403 total bytes 832515 nlines 1777 xp 1777 002cb410 total bytes 832528 xilinx file total lines 1777 xilinx file header length 40 bytes xilinx file total length including startup bits 832536 bytes fedldxf xfile 00200000 nlines 1777 bytes 832536 fedldxf OK correct number of bits found for Xilinx load fedldxf before loading status result 0 INIT 1 DONE 1 fedldxf loading xfile to fpga XC4036 XL fedldxf wrote xilinx header result 0 INIT 1 DONE O fedldxf Frame 1 INIT 1 DONE 0 fedldxf Frame 101 INIT 1 DONE 0 fedldxf Frame 201 INIT 1 DONE 0 fedldxf Frame 301 INIT 1 DONE 0 fedldxf Frame 401 INIT 1 DONE 0 fedldxf Frame 501 INIT 1 DONE 0 fedldxf Frame 601 INIT 1 DONE 0 fedldxf Frame 701 INIT 1 DONE 0 fedldxf Frame 801 INIT 1 DONE 0 fedldxf Frame 901 INIT 1 DONE 0 fedldxf Frame 1001 INIT 1 DONE 0 fedldxf Frame 1101 INIT 1 DONE 0 fedldxf Frame 1201 INIT 1 DONE 0 fedldxf Frame 1301 INIT 1 DONE 0 fedldxf Fra
9. Erase PLX eprom contents FED Mon fedplxeper fedplxeper Erase contents of PLX serial eprom fedplxeper WARNING This command erases contents of PLX serial eprom fedplxeper Do you really want to do this fedplxeper Type yes to continue any other character to abort gt fedplxeper OK continuing KKKKKKKK ERASING PLX Eprom FEDPMC_DEBUG gt Erased plx eprom done PLX serial eprom is erased FED_Mon gt See also fedplxepfl fedplxeprd fedplxepwr Version 2 0 49 January 2001 FED Mon User Manual CMS FED PMC 2001 9 28 FEDPLXEPFL Name fedplxepfl Fill contents of PLX serial eprom with default values Syntax fedplxepfl lt address gt data Parameters lt address gt short word location in serial eprom 0 63 0 data gt 16 bit valuel 0000 Description WARNING This command is for Experts only Overwrites the contents of the serial eprom attached to PLX PCI bridge chip with default values Eprom contains 64 x 16 bit locations Example Fill contents of PLX serial eprom with default values FED Mon fedplxepfl fedplxepfl Fill contents of PLX serial eprom with default values fedplxepfl WARNING This command overwrites contents of PLX serial eprom with default values fedplxepfl Do you really want to do this fedplxepfl Type yes to continue any other character to abort gt fedplxepfl OK continuing KKKKKKKK Writing to PLX Eprom Starting at location 0 for 64 locati
10. FED Mon User Manual 9 18 FEDIDWR CMS FED PMC 2001 number in Flash Name fedidwr Store FED serial number Syntax fedidwr serial nr Parameters lt serial nr number corresponding to label on PMC Description WARNING This command is for Experts only Stores the FED PMC serial number labelled on PMC in the Flash EEPROM Example Store FED serial number FED Mon fedidwr 004 fedidwr WARNING This command overwrites FED serial EEPROM fedidwr Do you really want to do this fedidwr Type yes to continue any other character to abort gt fedidwr OK continuing fedidwr Write Serial Number afed0004 to Flash EEPROM total flash writes 224 clocks 1731 FED Mon Check the value FED Mon fedidrd INFO gt FED Serial Number 004 dec FED Mon See also fedidrd Version 2 0 36 January 2001 FED Mon User Manual CMS FED PMC 2001 9 19 FEDINIT Name Syntax Parameters Description Example Version 2 0 fedinit set up FED specific registers fedinit fedinit clock source clock delay trigger source trigger mode adc chan mask cadc sample freq adc sample size trigger throttle enable trigger throttle threshold lt clock source gt 0 PCI 2 Front Panel 3 J4 LVDS lt clock delay 0d0 0d10 lt trigger source gt 0 Front Panel 2 J4 LVDS 3 J4 TTL trigger mode gt 0 Start Digitisation lt adc chan mask g
11. amp delay Reset Event and Bunch Crossing counters Display Set Digitisation mode Read from FED addresses Fill entire DPM with identical value Read from Flash EPROM Write to Flash EPROM Read FED fifo contents Fill FED addresses Read FED serial number Store FED serial number Initialise FED registers Read bits from Lattice serial line Write a bit to Lattice serial line Send Lattice command to load fpga from flash eeprom Load Xilinx rbt file from rio memory to FPGA Load Xilinx rbt file from rio memory to Flash EEPROM Display FED address map Initialise FED PMC Bridge PCI CFG registers Erase contents of PLX serial eprom Fill contents of PLX serial eprom with default values Read contents of PLX serial eprom rite to an individual location in PLX serial eprom Reserved command don t use Reserved command don t use Display revision info of FED h w and s w Readout and display fed event Continuous read or write from to FED Nb old meaning of scope Start FED data acquisition run Display FED status Stop FED data acquisition run Send Software triggers Test FED DPM Display Set Throttle mode Display Set Test mode Display Set Trigger source amp mode Display Lattice serial line FPGA status ACkCkCk ck ck kCk ck ck ck ck ck ck k ck kk Following FED Mon commands are ONLY valid for Firmware version 2 rev 34 or later AC
12. bitstream packed ptr 00000000 fedldxfep Xilinx packed bit stream loaded 8 00300000 number packed bytes 104068 fedldxfep WARNING Do you really want to change the contents of Flash EEPROM fedldxfep Type yes to continue any other character to abort fedldxfep OK continuing fedldxfep new number flash pages 407 Loading Flash gt page 0 source 00300000 size 00000100 Loading Flash gt page 100 source 00306400 size 00000100 Loading Flash gt page 200 source 0030c800 size 00000100 Loading Flash gt page 300 source 00312c00 size 00000100 Loading Flash gt page 400 source 00319000 size 00000100 now reloaded Power FED off and on and then fedldxfep Flash EEPROM contents are reload FPGA from Flash FED Mon 1 After the first user response the Xilinx file length and format are checked for consistency 2 After the second user response the Flash EEPROM is actually updated 3 Immediately after reloading the Flash the FED PMC should be powered OFF amp ON to ensure the FPGA is updated with the new design 6 2 Loading FPGA directly from file In unusual cirumstances e g to bootstrap the FED PMC during production the user may wish to update the FPGA directly i e without permanently changing the Flash EEPROM contents This is possible with the following procedure Load the Xilinx file into the RIO using the same procedure
13. gt yes fedfepwr OK continuing fedfepwr Write to Flash EEPROM source 00400000 npages 1 FEDPMC DEBUG gt fedpmc_fpga_eeprom_load npages 1 source 00400000 FEDPMC DEBUG gt fedpmc fpga eeprom write memory npages 1 source 00400000 FEDPMC DEBUG gt page 0 source 00400000 size 00000100 E ja H o B tal flash writes 2144 clocks 4257 D_Mon gt fedfeprd fedldxfep 32 January 2001 FED Mon User Manual 9 15 FEDFIFO fedfifo display contents of Event FIFO number reads number of reads from Event FIFO Reads a specified number of words from the FIFO If no arguments are passed a single word is read Note This command is only intended for debugging purposes extra reads from the FIFO will disrupt the normal readout routine sequence if o 6 00000000 00000000 00000000 00000000 00000000 00000000 Name Syntax fedfifo lt number_reads gt 1 Parameters Description Example Read 6 words from fifo FED Mon fedf fifo read 41 fifo read 2 fifo read 3 fifo read 4 fifo read 5 fifo read 6 FED_Mon gt See also fedrout Version 2 0 contents contents contents contents contents contents fedfifo read fifo 6 times 33 Won go dg do gu CMS FED PMC 2001 0003000 500030000 00035533 0003010 500030100 500039019
14. number of bits to read Description Reads and displays a specified number of bits via the serial line If no arguments are passed one bit is read WARNING This command is for Experts only Misuse can disrupt operation of card necessitating a hardware reset to recover Example Read 4 bits from Lattice via serial line FED Mon fedlatrd 4 fedlatrd read from lattice serial line 4 times read i 0 data 0 read i 1 data 0 read i 2 data 0 read i 3 data 0 total lattice reads 260 clocks 432 FED_Mon gt See also fedlatwr Version 2 0 40 January 2001 FED Mon User Manual CMS FED PMC 2001 9 22 FEDLATWR Name fedlatwr Send a single bit via serial line connecting PCI bridge to Lattice CPLD Syntax fedlatwr fedlatwr bit value Parameters bit value 0 1 Description WARNING This command is for Experts only Misuse can disrupt operation of card necessitating a hardware reset to recover Send a single bit of data via the serial line If no arguments are passed 0 is sent Example Send a 1 to Lattice via serial line FED Mon fedlatwr 1 FED Mon See also fedlatrd Version 2 0 41 January 2001 FED Mon User Manual CMS FED PMC 2001 9 23 FEDLDXF Name Syntax Parameters Description Example Version 2 0 fedldxf load Xilinx configuration file directly to FPGA fedldxf fedldxf source address dest address source address
15. set FED APV sync mode fedapvmod fedapvmod lt operation gt lt operation 0 Disable FED APV sync mode 1 Enable FED APV sync mode Enable or Disable APV sync mode If no parameter is passed display status Nb APV sync mode must be enabled for BOTH Header Finding AND New scope mode Enable APV sync mode FED Mon fedapvmod 1 fedapvmod APV Sync mode is lt lt ENABLED gt gt FED Mon fedapvscp fedapvthr 71 January 2001 FED Mon User Manual CMS FED PMC 2001 9 46 FEDAPVPARM Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedapvparm Display Set APV timeout parameters override values fedapvparm fedapvparm lt frame timeout lt tick timeout frame size frame timeout gt APV frame timeout ovveride tick timeout gt APV tick timeout ovveride frame size gt APV frame size ovveride Set APV timeout parameters ovveride values If no arguments are passed timeout parameter override values are displayed APV Timeout parameters control details of header finding and frame capture APV Timeout parameters override mode must be enabled with fedapvpov to enable the new values If APV Timeout parameters override mode is Disabled following reset defaults are used frame timeout 275 tick timeout 65 frame size 277 Set APV timeout parameters override values for sampling at 1 2 clock frequency FED Mon fedap
16. 00200cfb total bytes 3323 nlines 9 xp 9 00200ed0 total bytes 3792 nlines 100 xp 100 0020b587 total bytes 46471 nlines 200 xp 200 00216cbb total bytes 93371 nlines 300 xp 300 002223ef total bytes 140271 nlines 400 xp 400 0022db23 total bytes 187171 nlines 500 xp 500 00239257 total bytes 234071 nlines 600 xp 600 0024498b total bytes 280971 nlines 700 xp 700 002500bf total bytes 327871 nlines 800 xp 800 0025b7f3 total bytes 374771 nlines 900 xp 900 00266f27 total bytes 421671 nlines 1000 xp 1000 0027265b total bytes 468571 nlines 1100 xp 1100 0027dd8f total bytes 515471 nlines 1200 xp 1200 002894c3 total bytes 562371 42 January 2001 FED Mon User Manual CMS FED PMC 2001 nlines 1300 xp 1300 00294bf7 total bytes 609271 nlines 1400 xp 1400 002a032b total bytes 656171 nlines 1500 xp 1500 002aba5f total bytes 703071 nlines 1600 xp 1600 002b7193 total bytes 749971 nlines 1700 xp 1700 002c28c7 total bytes 796871 nlines 1768 xp 1768 002ca55b total bytes 828763 nlines 1769 xp 1769 002ca730 total bytes
17. 0xc1200050 00ef00ce 00ef00ce 00ef00ce 00ef00c 0xc1200060 00ef00ce 00ef00ce 00ef00ce 00ef00c 0xc1200070 00ef00ce 00ef00ce 00ef00ce 00ef00c FED Mon fedfp feddp and PPC Mon commands dm dp fm fp 30 CMS FED PMC 2001 January 2001 FED Mon User Manual CMS FED PMC 2001 9 13 FEDFEPRD Name Syntax Parameters Description Example See also Version 2 0 fedfeprd read contents of Flash EEPROM memory fedfeprd fedfeprd dest address number pages skip flag dest address gt in RIO system mempty 50 0000 number pages gt number of Flash EEPROM pages to dump 1 skip flag gt skip bits in memory not used by Xilinx file 0 Dumps the contents of the Flash EEPROM memory to a specified address in RIO memory Note Page size 264 bytes If skip flag is set only the first 256 bytes of each page used by Xilinx file are dumped If no arguments are passed defaults are used Display contents of first page in Flash EEPROM FED Mon fedfeprd fedfeprd Read Flash EEPROM contents dest 8 00500000 npages 1 FEDPMC DEBUG gt fedpmc fpga eeprom read memory npages 1 dest 00500000 total flash reads 2113 writes cmds 64 clocks 2177 FED Mon FED Mon dm w 500000 0x00500000 ff20cb40 9f5bffdf ddfddfdd fddfddfd 0x00500010 afVafddf db7 77 7 7 77f77f 6bdebdeb z w w k 0
18. 2001 FED Mon User Manual CMS FED PMC 2001 9 9 FEDCTR Name fedctr Reset Event and Bunch crossing counters Syntax fedctr Parameters none Description Resets the Event and Bunch crossing counters Switches in and out of test mode if necessary NB Counters are read from Event FIFO i e during readout process Example Reset counters e g before start of new run FED Mon fedctr fedctr event amp bunch counters are now reset FED Mon See also Version 2 0 27 January 2001 FED Mon User Manual CMS FED PMC 2001 9 10 FEDDIG Name Syntax Parameters Description Example See also Version 2 0 feddig display set FED Digitisation mode feddig feddig lt operation gt lt operation 0 Disable ADC Digitisation mode 1 Enable ADC Digitisation mode Sets Displays ADC Digitisation mode status If no argument is passed the status is displayed Enabling digitisation resets Buffer management logic New buffers are filled starting from base of DPM Note Event FIFO contents are not cleared by this command Use fedbufp Start ADC digitisation ED_Mon gt feddig 1 eddig Digitisation mode is lt lt ENABLED gt gt ED_Mon gt Fr ph rj 28 January 2001 FED Mon User Manual CMS FED PMC 2001 9 11 FEDDP Name feddp display FED address contents Syntax feddp feddp address offset number reads Parameters
19. 57 January 2001 FED Mon User Manual CMS FED PMC 2001 9 33 FEDSCP Name fedscp Scope mode test reads writes or toggles a single FED memory address Syntax fedscp fedscp lt address_offset gt lt operation gt Parameters address offset gt test address offset from FED memory base 0 lt operation gt 12 Read 2 Write 3 Toggle Description Continuously reads writes or toggles a specified memory address Useful for analysing lines on the scope If no arguments are passed the first location in the DPM is filled Actions are terminated by hitting any character on the keyboard Example Read long word continuously from first location in DPM FED Mon fedscp 0 1 fedscp CONTINUOUSLY READING 8 addr c0000000 type any character to stop fedscp stopped FED Mon See also feddp fedfp Version 2 0 58 January 2001 FED Mon User Manual CMS FED PMC 2001 9 34 FEDSTART Name fedstart Starts a data acquisition run Syntax fedstart fedstart trigger type Parameters lt trigger type gt O HW Triggers 1 5W Triggers Description Starts a data acquistion run by enabling ADC digitisation Example Start run with software triggers FED Mon fedstart 1 fedstart FED data acquisition Run is STARTED using SOFTWARE triggers FED Mon See also fedstop fedrout Version 2 0 59 January 2001 FED Mon User Manual CMS FED PMC 2001
20. January 2001 FED Mon User Manual CMS FED PMC 2001 9 16 FEDFP Name Syntax Parameters Description Example See also Version 2 0 fedfp fills FED address contents with a fixed pattern fedfp fedfp address offset number fills address offset gt offset from FED memory base 0 number reads gt number of longs to fill 1 Fills memory contents starting from base of DPM with a fixed pattern If no arguments are passed the first location in the DPM is filled NB ADC Digitisation must be disabled in order to write new values to DPM Fill first 4 long words in DPM and display updated contents FED Mon feddig 0 feddig set Digitisation mode DISABLED FED Mon fedfp 0 4 FED Mon feddp 0 4 read op 000 address c0000000 data 00000001 read op 001 address c0000004 data 00000002 read op 002 address c0000008 data 00000003 read op 003 address c000000c data 00000004 FED_Mon gt feddp fedscp feddpmfl 34 January 2001 FED Mon User Manual CMS FED PMC 2001 9 17 FEDIDRD Name fedidrd Read FED serial number Syntax fedidrd Parameters none Description Reads back the FED PMC serial number stored in the Flash EEPROM Example Display FED serial number FED Mon fedidrd INFO gt FED Serial Number 004 dec FED Mon See also fedidwr fedrev Version 2 0 35 January 2001
21. Xilinx load fedldxfep bitstream char ptr 00200000 bitstream packed ptr 00300000 fedldxfep 1 E bitstream char ptr 00000001 pitstream packed ptr Sffffffff fedldxfep ji 100000 A bitstream_char_ptr 500000000 bitstream_packed_ptr 00000000 fedldxfep a 200000 Ditstream char ptr 500000001 pitstream packed ptr Sffffffff fedldxfep i 300000 Ditstream char ptr 500000001 bitstream_packed_ptr 00000000 fedldxfep i 400000 Ditstream char ptr 500000001 pitstream packed ptr Sfffffff9 fedldxfep i 500000 Ditstream char ptr 00000001 pitstream packed ptr Sffffffff fedldxfep a 600000 L Ditstream char ptr 00000001 bitstream packed ptr 00000000 fedldxfep i 700000 Ditstream char ptr 00000001 bitstream packed ptr 00000000 fedldxfep i 800000 Ditstream char ptr 500000001 pitstream packed ptr Sffffffff fedldxfep Xilinx packed bit stream loaded 00300000 bytes 104068 number packed FEDPMC XILINX TRACE Load packed bytes to flash eeprom type any character to continue fedldxfep new number flash pages 407 FEDPMC DEBUG gt fedpmc fpga eeprom load npages 407 source 00300000 FEDPMC DEBUG gt fedpmc fpga eeprom write memory npages 407 source 00300000 FEDPMC DEBUG gt page 0 source 00300000 size 00000100 FEDPMC DEBUG gt page 100 sou
22. as described in section Updating Firmware FED Mon fedldxf fedldxf default rio addresses xilinx file source 00100000 dest 00200000 fedldxf WARNING This command reloads Xilinx fedldxf Do you really want to do this fedldxf Type yes to continue any other character to abort gt fedldxf OK continuing nlines 0 xp 0 00200000 total bytes 0 nlines 1 xp 1 00200028 total bytes 40 nlines 2 xp 2 002001fd total bytes 509 nlines 3 xp 3 002003d2 total bytes 978 nlines 4 xp 4 002005a7 total bytes 1447 nlines 5 xp 5 0020077c total bytes 1916 nlines 6 xp 6 00200951 total bytes 2385 Version 2 0 12 January 2001 FED Mon User Manual CMS FED PMC 2001 lines 7 xp 7 lines 8 xp 8 00200cfb total bytes 3323 lines 9 9 00200ed0 total bytes 3792 00200b26 total bytes 2854 n n n J nlines 100 xp 100 0020b587 total bytes 46471 nlines 200 xp 200 00216cbb total bytes 93371 nlines 300 xp 300 002223ef total bytes 140271 nlines 400 xp 400 0022db23 total bytes 187171 nlines 500 xp 500 00239257 total bytes 234071 nlines 600 xp 600 0024498b total bytes 280971 nlines 700 xp 700 002500bf total bytes 327871 nlines 800 xp 800 0025b7f3 total bytes 374771 nlines 900 xp 900 00266f27 tota
23. fm w fp w fill memory locations reset to return to PPC Mon WARNING The following commands are NOT available within FED Mon and should ONLY be called from PPC Mon Use the reset command to leave FED Mon and return to PPC Mon before using them set to set RIO2 NVRAM parameters show to display RIO2 NVRAM parameters load to load programs to RIO2 memory exec to run programs in RIO2 memory boot run boot code Please refer to the PPC Mon manual 3 for details of these and other commands Version 2 0 15 January 2001 FED Mon User Manual CMS FED PMC 2001 9 FED Mon Commands ACkCkCk ck ck kCk ck ck ck ck ck ck ck ck kk Standard FED Mon commands valid for ALL Firmware versions ROK Ok EK KOK KOK OK KOK Ok KOK OK KOK ck fedadc fedbrg fedbuf fedbufp fedbug fedckcfg fedclk fedctr feddig feddp feddpmfl fedfeprd fedfepwr fedfifo fedfp fedidrd fedidwr fedinit fedlatrd fedlatwr fedlatfep fedldxf fedldxfep fedmap fedmem fedplxeper fedplxepfl fedplxeprd fedplxepwr fedresl fedres2 fedrev fedrout fedscp fedstart fedstat fedstop fedswt fedtest fedthr fedtmod fedtrg fedxlst Display Set ADC registers FED PMC Bridge PCI LOCAL registers Display number of occupied buffers in dpm Purge remaining occupied buffers in dpm Display FED program variables for debugging Enter Exit FPGA Clock configuration mode Display Set Clock source
24. for DPM space 0000 0001 dpm desc gt descriptor for DPM space 030300c3 reg size gt size of window for register space ffff ff00 reg base gt local base for register space 0010 0001 reg desc descriptor for register space 00000243 Description Initialises the PMC bridge local registers If no arguments are passed defaults are used It maps PCI to local bus addresses Note User should NOT need to change defaults which are set on initialisation fedmem must have been called at least once before calling fedbrg Example Sets default local addresses FED Mon fedbrg fedbrg default values were set bridge local regs pci mem base c0100100 00000001 S 00000 000301c3 00100001 Sffffff00 00000243 01200000 88000000 00000004 dpm local base dpm window size dpm descriptor regs local base regs window size regs descriptor mode amp arbitration eeprom cntrl big endian FED Mon Won gm ow dw dw dw dog See also fedmem fedstat Version 2 0 21 January 2001 FED Mon User Manual CMS FED PMC 2001 9 4 FEDBUF Name fedbuf Display number of occupied buffers in DPM Syntax fedbuf Parameters none Description Gives the number of occupied buffers i e events pending to readout from the DPM Nb Number of occupied buffers is reset to O at new run start Example Display number of occupied buffers FED Mon fedbuf fedbuf number of occupied buffers pendin
25. lt operation gt Parameters lt operation 0 Enter clock configuration mode 1 Exit clock configuration mode Description Command for Experts only NB Entering Clock Configuration mode resets Xilinx to default settings Therefore user should reinitialise FED settings with fedinit afterwards Example Enter clock configuration mode FED Mon fedckcfg 1 fedckcfg ENTER FPGA Clock configuration mode FED Mon See also fedclk fedinit Version 2 0 25 January 2001 FED Mon User Manual CMS FED PMC 2001 9 8 FEDCLK Name fedclk display set FED clock source and delay Syntax fedclk fedclk clock source clock delay Parameters lt clock source gt 0 PCI 2 Front Panel 3 J4 LVDS lt clock delay 0d0 0d10 Description Initialises the FED clock source and delay Actual delay is clock delay x 2 5 nsec i e 0 25 nsec range If no arguments are passed the clock status is displayed WARNING If the selected clock is not present e g front panel clock subsequent card access will return bus errors Card may then require a hardware reset and reinitialisation in order to continue Example Use PCI clock Set clock skew delay to 10 nsec 4 x 2 5 nsec FED Mon fedclk 0 4 fedclk clock source PCI CLOCK fedclk clock delay 4 x 2 5 nsec fedclk WARNING gt If Bus errors after changing new CLOCK may NOT be running FED Mon See also fedckcfg fedinit Version 2 0 26 January
26. n word n word n word n word n word n word n word n word n word n word word n word erial Mon HS HS HS ds HS HS HS 63 i wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote wrote 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9080 10b5 Sffff Sff00 0010 0001 0000 0243 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMS FED PMC 2001 eprom is reprogrammed with default values fedplxeper fedplxeprd fedplxepwr Version 2 0 January 2001 FED Mon User Manual CMS FED PMC 2001 9 29 FEDPLXEPRD Name fedplxeprd Read contents of PLX serial eprom Syntax fedplxeprd Parameters none Description Display the contents of serial eprom attached to PLX PCI bridge chip Contents read OxFFFF if eprom is not present on PMC or if it is erased Eprom contains 64 x 16 bit locations Example Display PLX eprom contents following list shows default valu
27. 500bf total bytes 327871 nlines 800 xp 800 0025b7f3 total bytes 374771 nlines 900 xp 900 00266f27 total bytes 421671 nlines 1000 xp 1000 0027265b total bytes 468571 nlines 1100 xp 1100 0027dd8f total bytes 515471 nlines 1200 xp 1200 002894c3 total bytes 56237 nlines 1300 xp 1300 00294bf7 total bytes 60927 nlines 1400 xp 1400 002a032b total bytes 65617 nlines 1500 xp 1500 002aba5f total bytes 70307 nlines 1600 xp 1600 002b7193 total bytes 74997 nlines 1700 xp 1700 002c28c7 total bytes 79687 nlines 1768 xp 1768 002ca55b total bytes 828763 nlines 1769 xp 1769 002ca730 total bytes 829232 nlines 1770 xp 1770 002ca905 total bytes 829701 nlines 1771 xp 1771 002caada total bytes 830170 nlines 1772 xp 1772 002cacaf total bytes 830639 nlines 1773 xp 1773 002cae84 total bytes 831108 nlines 1774 xp 1774 002cb059 total bytes 831577 nlines 1775 xp 1775 002cb22e total bytes 832046 nlines 1776 xp 1776 002cb403 total bytes 832515 nlines 1777 xp 1777 002cb410 total bytes 832528 xilinx file total lines 1777 xilinx file header length 40 bytes xilinx file total length fedldxfep xfile 8 00200000 nlines including startup bits 1777 bytes 832536 bytes 832536 fedldxfep OK correct number of bits found for
28. 8 January 2001 FED Mon User Manual CMS FED PMC 2001 fedstart Start FED data acquisition run fedstat Display FED status fedstop Stop FED data acquisition run fedswt Send Software triggers fedtest Test FED DPM fedthr Display Set Throttle mode fedtmod Display Set Test mode fedtrg Display Set Trigger source amp mode fedxlst Display Lattice serial line FPGA status KKKKKKKKKKKKKKKKKKK Following FED_Mon commands are ONLY valid for Firmware version 2 rev 34 or later KKKKKKKKKKKKKKKKKKK fedapvctrd Display APV frame and trigger counters fedapvctrs Reset APV frame and trigger counters fedapvmod Display APV Sync status fedapvparm Display Set APV timeout parameters fedapvpov Display Set APV Timeout parameters override mod fedapvscp Display APV NEW Scope status fedapvthr Display Set APV Header thresholds fedfend Display FrontEnd to DPM status fedintfifo Display Internal FIFO status fedtrgflt Display Trigger Filter status Type help command for command syntax NB Type help to list in addition all PPC Mon commands Notes each command will use standard defaults if no arguments are passed argument default is Hex prefix 0d to specify decimal FED Mon Version 2 0 19 January 2001 FED Mon User Manual CMS FED PMC 2001 9 2 FEDADC Name fedadc set up FED ADC registers Sy
29. 9 total bytes 831577 nlines 1775 xp 1775 002cb22e total bytes 832046 nlines 1776 xp 1776 002cb403 total bytes 832515 nlines 1777 so 1777 002cb410 total bytes 832528 xilinx file total lines 1777 xilinx file header length 40 bytes xilinx file total length including startup bits 832536 bytes fedldxfep xfile 8 00200000 nlines 1777 bytes 832536 fedldxfep OK correct number of bits found for Xilinx load fedldxfep bitstream char ptr 00200000 bitstream packed ptr 00300000 fedldxfep i O bitstream char ptr 3500000001 bitstream packed ptr 00000001 fedldxfep i 100000 bitstream char ptr 00000000 bitstream packed ptr Sffffffff fedldxfep i 200000 bitstream char ptr 00000001 bitstream packed ptr 00000000 fedldxfep i 300000 bitstream char ptr 00000001 bitstream packed ptr Sffffffb5 Version 2 0 11 January 2001 FED Mon User Manual CMS FED PMC 2001 fedldxfep i 400000 bitstream char ptr 00000001 bitstream packed ptr Sffffffqd7 fedldxfep i 500000 bitstream char ptr 00000001 bitstream packed ptr Sffffffff fedldxfep i 600000 bitstream char ptr 00000001 bitstream packed ptr SEffffff fedldxfep i 700000 bitstream char ptr 00000001 bitstream packed ptr 00000000 fedldxfep i 800000 bitstream char ptr 00000001
30. MC 2001 2 Foreword This documents describes the monitor program used for testing the CMS Front End Driver FED PMC when used on a CES RIO2 carrier processor board This document can be obtained from the following anonymous ftp site address ftp te rl ac uk directory cms fed fed pmc docs manuals fedmon um pdf Please send any comments on the contents of this document to the author J Coughlan rl ac uk 3 Introduction FED Mon is a low level debugger amp monitor program for the CMS Front End Driver prototype FED PMC 1 when running them on the CES RIO2 including RTPC family of VME PowerPC Single Board Computers 2 FED Mon is designed to provide a convenient way of standalone testing of FED PMC modules in a test bench environment equipped with only a serial line and an ethernet connection to the RIO2 This manual assumes the user is familiar with the RIO2 and the commands of it s associated monitor program PPC Mon FED Mon provides a means of taking simple data acquisition runs to test the operation of the FED PMC It also allows the user to reconfigure the firmware design of the FED PMC Xilinx FPGA and provides several other low level testing and debugging operations Version 2 0 4 January 2001 FED Mon User Manual CMS FED PMC 2001 4 Getting Started 4 1 Getting a copy of the FED Mon program FED Mon is a PowerPC XCOFF executable text file which can be found on the anonymous ftp server address ftp te rl a
31. TART D Il o I CLOCK adc chan mask aa ADC chans 0 amp 1 are 2 amp 3 are 4 amp 5 are 6 amp 7 are ADC Sample Freg ADC Sample Size FED_Mon gt See also fedinit Version 2 0 Number of Filled Buffers gt FRONT PANEL TRIGGER GITISATION lt lt ENABLED gt gt lt lt ENABLED gt gt lt lt ENABLED gt gt lt lt ENABLED gt gt 0 256 7 61 CMS FED PMC 2001 January 2001 FED Mon User Manual CMS FED PMC 2001 9 36 FEDSTOP Name fedstop Stops a data acquisition run Syntax fedstop Parameters none Description Stops a data acquistion run by disabling ADC digitisation Example Stop run FED Mon fedstart 1 fedstart FED data acquisition Run is STARTED using SOFTWARE triggers FED_Mon gt fedstop fedstop FED data acquisition Run is STOPPED FED_Mon gt See also fedstart Version 2 0 62 January 2001 FED Mon User Manual 9 37 FEDSWT CMS FED PMC 2001 Name fedswt sends software triggers Syntax fedswt fedswt number triggers Parameters number triggers gt number of software triggers to generate Description Send software triggers If no arguments are passed a single trigger is sent Example Send 4 software triggers FED Mon fedswt 4 fedswt sent software trigger fedswt sent software trigger fedswt sent software trig
32. XEPRD EE ee ee eC MH vel ee Ge ed ee Soa ene SE e E EUR eN eves Gee Bee o 52 Version 2 0 2 January 2001 FED Mon User Manual CMS FED PMC 2001 9 30 FEDPLXEP d e NY 54 9 31 FEDRE VS io 55 9 32 FEDRO UT tc 56 9 33 FEDSCP EE EE diia 58 9 34 FEDSTAR To iia 59 9 35 FEDSTA up Tcu 60 9 36 FEDSTO EE eR WINE e WE Hae oye A ORE A N 62 9 37 FEDS EE N e EES EE a 63 9 38 PEDTBST ER BEE A RE De eg De wa De e e EN ies EH E EG ese 64 9 39 PED ITA aem T EN EE mE 65 9 40 FEDTMOD IE OE N EE EE EE N NE ON N ER ER OE N EA ERS 66 9 41 FED TRG TOR OR OE OES EE RA ER N OR da tdt OE 67 9 42 gib 68 9 43 FEDAPVCTRD FIRMWARE V2 ONLY dee GR eet ses e dee eo to ir tios 69 9 44 FEDAPVCTRS FIRMWARE V2 ONLY i ie ER dee e e VE ERA Urt epe 70 9 45 FEDAPVMOD FIRMWARE VZ ONLY ole BEE EST Ai da 71 9 46 FEDAPVPARM FIRMWARE V2 ONEY e ed ia ra pee Ve dee 72 9 47 FEDAPVPOV FIRMWARE V2 ONLY Si ll ue eg 73 9 48 FEDAPVSCP FIRMWARE V2 ONLY idee da 74 9 49 FEDAPVTHR FIRMWARE V2 ONLY sede soe eer see gese iii 75 9 50 FEDFEND FIRMWARE VZ ONLY AE Secs ee ee Tode od a ad CE Gens X CAO RAS EV ee e N 76 9 51 FEDINTFIFO FIRMWARE Ne IE SERE OE EE EE EE ER A EE EE EG 71 9 52 FEDTRGFLT FIRMWARE VZ ONLY E 78 10 DOCUMENT SERVERS ici a a Bee Ge DEE ee ro 79 11 REFERENCES eue I RR a A eden N EE e 80 Version 2 0 3 January 2001 FED Mon User Manual CMS FED P
33. c uk directory cms fed fed pmc software fedmon 4 2 Loading FED Mon onto RIO2 The standard way of running FED Mon is to load it from an tftp trivial ftp server into the RIO2 memory using the PPC Mon load command The FED Mon is XCOFF file relocated to run at the RIO2 system memory address 1 0000 NB The standard CES monitor PPC Mon 3 must first be running in order to load FED Mon from the server i If you are already in FED Mon use the reset command to return to PPC Mon FED Mon reset ii First ensure the RIO2 host and tftpd server addresses are setup correctly PPC Mon show inet These settings can be changed with the set command PPC Mon set inet host your RIO IPaddr PPC Mon set inet server your tftp server IPaddr iii Load FED Mon at 1 0000 PPC Mon load le fedmon filename 10000 network boot loading file fedmon from server 130 246 40 163 ethernet local address 00 80 a2 00 8a 33 ethernet address of server 08 00 07 1e 2a c5 loading at address 10000 tftp packet number 200 file length 0x46424 287780 transfer rate 29 kbyte sec PPC_Mon gt 1 It is also possible to store the FED_Mon program permanently in the FLASH Memory of the RIO2 The RIO2 can then be configured to boot up with FED_Mon See the RIO2 documentation for instructions Now FED Mon is ready to run tftp servers are available on most platforms Version 2 0 5 January 2001 FED Mon User Manual 4 3 Run
34. d Xilinx load status Syntax fedxlst Parameters none Description Reads the Xilinx load status via the Lattice serial line Example Read Xilinx load status FED Mon fedxlst fedxlst Xilinx Load status INIT 1 DONE 1 FED Mon See also Version 2 0 68 January 2001 FED Mon User Manual CMS FED PMC 2001 9 43 FEDAPVCTRD Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedapvctrd Display APV frame and trigger counters fedapvctrd none Display values of Frame and Trigger counters cf Event and BX counters read from external FIFO Display APV counters FED Mon fedapvctrd fedapvctrd APV Frame Counter 0 dec fedapvctrd APV Trigger Counter 0 dec FED Mon fedapvctrs 69 January 2001 FED Mon User Manual CMS FED PMC 2001 9 44 FEDAPVCTRS Firmware v2 only Name fedapvctrs Reset APV frame and trigger counters Syntax fedapvctrs Parameters none Description Reset APV frame and trigger counters cf Event and BX counters read from external FIFO Example Reset APV frame and trigger counters FED Mon fedapvctrs fedapvctrs APV Frame amp Trigger Counters Reset FED Mon See also fedapvctrd Version 2 0 70 January 2001 FED Mon User Manual CMS FED PMC 2001 9 45 FEDAPVMOD Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedapvmod display
35. e revision information fedrev none Show current hardware and software revisions Show revisions FED Mon fedrev fedrev Version information FIRMWARE Xilinx version 0 revison 2 prototype 0 SOFTWARE FED Mon Version of Dec 6 2000 at 11 05 34 FEDPMC s w library version 2 07 FED Mon fedidrd 55 January 2001 FED Mon User Manual CMS FED PMC 2001 9 32 FEDROUT Name Syntax Parameters Description Example Version 2 0 fedrout Readout and display FED next pending event in DPM fedrout fedrout dest address gt lt format flag gt dma flag gt lt display format gt dest address gt data destination in RIO memory 0030 0000 format flag gt FED data format 1 NO Formatting lt dma flag gt 0Q OFF 1 ON format flag gt display format l hex 2 decimal Read out the next pending event if present in DPM It performs the commands necessary for FED readout sequence and displays event data and associated fifo contents i e event amp bunch crossing numbers If no arguments are passed defaults are used Readout first event pending in DPM FED Mon fedstart 1 fedstart FED data acquisition Run is STARTED using SOFTWARE triggers FED_Mon gt fedswt 4 fedswt sent software trigger 1 fedswt sent software trigger 2 fedswt sent software trigger 3 fedswt sent software trigger 4 fedbuf number of f
36. es ED Mon fedplxeprd F KK KK KKK R eading from PLX Eprom PLX serial eprom contents location 00 Oxfed0 location 01 0x10dc location 0x0000 location 03 0x0000 location 04 0x0000 location 05 0x0000 location 06 0x0000 location 07 0x0000 location 08 0x0000 D N ll oll II location 09 0x0000 location 10 Oxfff0 location 11 0x0000 location 12 0x0000 location 13 0x0001 location 14 0x0000 location 15 0x0000 location 16 0x0000 location 17 0x0000 location 18 0x0000 location 19 0x0000 location 0x0000 location 21 0x0000 location 22 0x0303 location 23 0x00c3 location 24 0x0000 location 25 0x0000 location 26 0x0000 location 27 0x0000 location 28 0x0000 location 29 0x0000 location 30 0x0000 location 0x0000 location 32 0x0000 location 33 0x0000 Wood N O Il Wil oll LY ll Version 2 0 52 January 2001 FED Mon User Manual location location location location location location location location location location location location location location location location location location location location location location location location location location location location location location FED Mon See also fedplxeper fedplxepfl fedplxepwr Version 2 0 HS Hs ds ds HS HS HS 0x9080 0x10b5 Oxffff Oxff00 0x0010 0x0001 0x0000 0x0243 0x0000 II 0x0000 0
37. f 001000bc 001000cc 001000dc 001000ec fed00245 circa January 2001 FED Mon User Manual CMS FED PMC 2001 9 26 FEDMEM Name Syntax Parameters Description Example See also Version 2 0 fedmem set up FED PMC bridge PCI configuration registers fedmem fedmem pci cfg base pci mem base pci cfg base PCI configuration base address of PMC seen from RIO 8080 2000 pci mem base PCI memory base address for FED seen from RIO c000 0000 Initialise the PMC bridge configuration registers If no arguments are passed defaults are used Default settings assume FED is on RIO PMC lower slot no 1 Note User should NOT need to change defaults which are set on initialisation Use default settings FED Mon fedmem fedmem default values were set bridge config regs pci cfg base 80802000 vendor id 908010b5 bridge cmd status reg 02800007 dpm pci mem base rio c0000000 fifo pci mem base rio c0100000 bridge pci mem base rio c0100100 FED_Mon gt fedbrg fedstat 48 January 2001 FED Mon User Manual CMS FED PMC 2001 9 27 FEDPLXEPER Name fedplxeper Erase contents of PLX serial eprom Syntax fedplxeper Parameters none Description WARNING This command is for Experts only Erases the contents of serial eprom attached to PLX PCI bridge chip After erasing eprom contents readback as OxFFFF Example
38. f Nov 18 1998 at 14 23 50 INFO gt RUNNING FEDMON TEST VERSION PPC regs msr 0x00001030 hid0 0x8100c080 INFO gt SKIPPING VME SETUP INFO gt PMC Simulation is OFF fedrev Version information FED_Mon Version of Nov 18 1998 at 14 23 26 INFO gt Initialising FED PMC PCI Bridge with default settings fedmem set bridge pci cfg abs pci mem base 00000000 INFO gt Xilinx FPGA status at start fedlatst status register INIT 1 DONE 0 INFO gt Loading Xilinx from Flash EEPROM INFO gt start timeout counter 4 timeout 50000 timeout counter 10000 timeout counter 20000 timeout counter 30000 timeout counter 40000 timeout counter 50000 INFO gt end timeout counter 50001 ATTENTION gt gt gt gt gt The XILINX is NOT yet loaded lt lt lt lt lt FED_Mon gt Suggestion Try powering OFF and ON and repeating Suggestin Try reloading the Flash EEPROM see section 6 1 Version 2 0 14 January 2001 FED Mon User Manual CMS FED PMC 2001 8 Using PPC Mon commands PPC Mon is the default CES monitor debugger program which starts when the RIO2 is booted up FED Mon is based on PPC Mon and some of the PPC Mon commands are available within FED Mon Some useful ones include dm w dp w display memory locations
39. g readout 0 FED Mon See also Version 2 0 22 January 2001 FED Mon User Manual CMS FED PMC 2001 9 5 FEDBUFP Name Syntax Parameters Description Example See also Version 2 0 fedbufp Purge unread occupied buffers in DPM fedbufp none Purges the unread buffers pending in the DPM This is done by emptying the event FIFO Purge occupied buffers in DPM e g at the end of a run FED Mon fedbufp fedbufp purging remaining occupied buffers in dpm fedbufp started with 8 occupied buffers fedbufp Purged 8 buffers fedbufp finished with 0 occupied buffers FED Mon 23 January 2001 FED Mon User Manual CMS FED PMC 2001 9 6 FEDBUG Name fedbug display FED Mon program variables for debugging Syntax fedbug Parameters none Description Just for expert debugging of FED Mon commands Example Display monitor debugging information FED Mon fedbug fedbug OK FED PMC S W Simulation mode is OFF fedbug g pci cfg base 80802000 fedbug g pci mem base c0000000 fedbug pci mem base dpm c0000000 fedbug pci mem base fifo c0100000 fedbug pci mem base fed regs c0100080 fedbug pci mem base bridge c0100100 FED Mon See also fedmap Version 2 0 24 January 2001 FED Mon User Manual 9 7 FEDCKCFG CMS FED PMC 2001 Name fedckcfg enter exit FED FPGA clock configuration mode Syntax fedckcfg
40. ger fedswt sent software trigger fedswt number of filled buffers 4 FED Mon See also Version 2 0 63 January 2001 FED Mon User Manual CMS FED PMC 2001 9 38 FEDTEST Name fedtest test DPM contents Syntax fedtest fedtest address offset number reads max errors Parameters lt address offset gt start test at offset from FED memory base 0 lt number locations gt number of locations longs to test 2 max errors stop after number of bad locations 1 Description Tests DPM contents with a set of standard patterns and reports any errors found If no arguments are passed defaults are used Example Test first 16 locations in DPM Stop if any locations show errors FED Mon fedtest 0 16 1 fedtest begin addr 00000000 number locations 22 will stop after 1 bad locations fedtest tested location in dpm at offset 00000000 bad locations so far 0 fedtest stopped addr c0000058 locations 22 bad locs 0 errors 0 FED_Mon gt See also Version 2 0 64 January 2001 FED Mon User Manual 9 39 FEDTHR CMS FED PMC 2001 Name fedthr display set FED Trigger Throttle mode Syntax fedthr fedthr lt operation gt Parameters lt operation 0 Disable Trigger Throttle mode 1 Enable Trigger Throttle mode Description Set Display Trigger Throttle mode Example Enable Trigger Throttle FED Mon fedthr 1 fedthr Throttle
41. gt seen from RIO 10 0000 dest address gt seen from RIO 20 0000 The fedldxf command takes a Xilinx rbt formatted configuration file preloaded at source address in system memory verifies it and writes out formatted data for FPGA to lt dest address gt Finally it loads FPGA with formatted data If no arguments are passed defaults are used Care should be taken to ensure there is sufficient space above each address chosen depending on Xilinx file size if the defaults are not used e g 1 Mbyte for standard XC4036XL rbt file NB Xilinx configuration file must be already loaded in memory before calling fedldxf See section Updating Firmware Load Xilinx from configuration file preloaded in memory 10 0000 FED Mon fedldxf fedldxf default rio addresses xilinx file source 00100000 dest 00200000 fedldxf This command reloads Xilinx fedldxf Do you really want to do this fedldxf Type yes to continue any other character to abort gt fedldxf OK continuing nlines 0 xp 0 00200000 total bytes 0 nlines 1 xp 1 00200028 total bytes 40 nlines 2 xp 2 002001fd total bytes 509 nlines 3 xp 3 002003d2 total bytes 978 nlines 4 xp 4 002005a7 total bytes 1447 nlines 5 xp 5 0020077c total bytes 1916 nlines 6 xp 6 00200951 total bytes 2385 nlines 7 xp 7 00200b26 total bytes 2854 nlines 8 xp 8
42. igger Filter is lt lt ENABLED gt gt FED Mon 78 January 2001 FED Mon User Manual CMS FED PMC 2001 10 Document Servers Latest versions of all FED PMC documentation and software are available from the following web site hepwww rl ac uk CMS fed Default htm or alternatively directly at the following anonymous ftp server address ftp te rl ac uk directory cms fed fed pmc Version 2 0 79 January 2001 FED Mon User Manual CMS FED PMC 2001 11 References 1 FED PMC User Manual fto ftp te rl ac uk cms fed docs manuals fedpmc um pdf 2 CES RIO8062 http www ces ch Products Products html 3 CES AWX 3317C http www ces ch Products Products html Version 2 0 80 January 2001
43. iguration file See section Loading FPGA directly from file Load Flash EEPROM from configuration file preloaded in memory 10 0000 FED Mon fedldxfep fedldxfep default rio addresses xilinx file source 00100000 dest 00200000 fedldxfep This command overwrites contents of Flash EEPROM with new Xilinx file fedldxfep Do you really want to do this fedldxfep Type yes to continue any other character to abort gt yes nlines 0 xp 0 00200000 total bytes 0 nlines 1 xp 1 00200028 total bytes 40 nlines 2 xp 2 002001fd total bytes 509 nlines 3 xp 3 002003d2 total bytes 978 nlines 4 xp 4 002005a7 total bytes 1447 nlines 5 xp 5 0020077c total bytes 1916 nlines 6 xp 6 00200951 total bytes 2385 nlines 7 xp 7 00200b26 total bytes 2854 nlines 8 xp 8 00200cfb total bytes 3323 nlines 9 xp 9 00200ed0 total bytes 3792 nlines 100 xp 100 0020b587 total bytes 46471 nlines 200 xp 200 00216cbb total bytes 93371 nlines 300 xp 300 002223ef total bytes 140271 nlines 400 xp 400 0022db23 total bytes 187171 nlines 500 xp 500 00239257 total bytes 234071 44 January 2001 FED Mon User Manual CMS FED PMC 2001 nlines 600 xp 600 0024498b total bytes 280971 nlines 700 xp 700 002
44. ilinx header result 0 INIT 1 DONE O E II E fedldxf Frame 1 INIT 1 DONE O fedldxf Frame 101 INIT 1 DONE 0 fedldxf Frame 201 INIT 1 DONE 0 fedldxf Frame 301 INIT 1 DONE 0 fedldxf Frame 401 INIT 1 DONE 0 fedldxf Frame 501 INIT 1 DONE 0 fedldxf Frame 601 INIT 1 DONE 0 fedldxf Frame 701 INIT 1 DONE 0 fedldxf Frame 801 INIT 1 DONE 0 fedldxf Frame 901 INIT 1 DONE 0 fedldxf Frame 1001 INIT 1 DONE 0 fedldxf Frame 1101 INIT 1 DONE 0 fedldxf Frame 1201 INIT 1 DONE 0 fedldxf Frame 1301 INIT 1 DONE 0 fedldxf Frame 1401 INIT 1 DONE 0 fedldxf Frame 1501 INIT 1 DONE 0 fedldxf Frame 1601 INIT 1 DONE 0 fedldxf Frame 1701 INIT 1 DONE 0 fedldxf write_xilinx_footer result 0 INIT 1 DONE 1 fedldxf XC4036 XL loaded ok FED Mon Notes Version 2 0 13 January 2001 FED Mon User Manual CMS FED PMC 2001 1 After the FED PMC is powered OFF amp ON the FPGA will revert to the previous design stored in the Flash EEPROM 7 Trouble shooting with FED Mon The Xilinx may fail to load if the Flash EEPROM is not correctly loaded PPC Mon exec 10000 starting code execution at address 45f70 FEDMON Version o
45. illed buffers 4 FED_Mon gt fedrout readout time for 16 samples skip begin end 0 0 452 micro sec fedrout Readout Event data to RIO address 00300000 Event no 00000000 Bunch no 49148 Event size 256 bytes Number Samples 16 Skipped samples begin end 0 0 Buffer base in dpm 00000000 Unformatted data follows ADC Chant gt 0 1 2 3 4 5 6 7 Sample 000 0284 0278 0274 0277 0280 0280 0280 0279 Dec 001 0284 0278 0274 0277 0280 0280 0281 0279 Dec 002 0284 0279 0274 0277 0280 0280 0280 0279 Dec 003 0284 0278 0274 0277 0280 0279 0280 0278 Dec 004 0284 0278 0274 0277 0280 0280 0280 0279 Dec 005 0284 0278 0275 0277 0280 0280 0280 0279 Dec 006 0284 0279 0274 0277 0280 0280 0281 0279 Dec 007 0284 0279 0275 0277 0280 0280 0281 0279 Dec 56 January 2001 FED Mon User Manual CMS FED PMC 2001 008 0284 0279 0274 0277 0280 0280 0280 0279 Dec 009 0284 0279 0274 0277 0280 0280 0281 0279 Dec 010 0284 0278 0274 0277 0280 0280 0280 0279 Dec 011 0284 0278 0274 0277 0280 0280 0280 0279 Dec 012 0284 0278 0274 0277 0280 0280 0280 0278 Dec 013 0284 0278 0274 0277 0280 0280 0280 0278 Dec 014 0284 0279 0275 0277 0280 0280 0281 0279 Dec 015 0284 0279 0274 0277 0280 0280 0281 0279 Dec umber of events pending 3 ED Mon uz See also fedstart fedswt Version 2 0
46. kCkCk Ck Ck kCk ck ck ck ck ck Ck ck ck kk fedapvctrd fedapvctrs fedapvmod fedapvparm fedapvpov fedapvscp Version 2 0 Display APV frame and trigger counters Reset APV frame and trigger counters Display APV Sync status Display Set APV timeout parameters Display Set APV Timeout parameters override mod Display APV NEW Scope status 16 January 2001 FED Mon User Manual CMS FED PMC 2001 fedapvthr Display Set APV Header thresholds fedfend Display FrontEnd to DPM status fedintfifo Display Internal FIFO status fedtrgflt Display Trigger Filter status Notes 1 AII FED Mon command parameters are assumed to be HEXADECIMAL values To enter other types specify the appropiate prefix eg 0d10 for decimal value 10 Version 2 0 17 January 2001 FED Mon User Manual 9 1 FED Name Syntax Parameters Description Example Version 2 0 CMS FED PMC 2001 fed display list of all FED specific commands fed none List all FED Mon commands List FED Mon commands FED Mon fed ACkCkCk Ck ck kCk ck ck ck ck ck ck ck ck kk Standard FI ED Mon commands valid for ALL Firmware versions ACkCkCk Ck ck kCk ck ck ck ck k ck ck ck kk fedadc fedbrg fedbuf fedbufp fedbug fedckcfg fedclk fedctr feddig feddp feddpmfl fedfeprd fedfepwr fedfifo fedfp fedidrd fedidwr fedinit fedlatrd fedlatwr fedlatfep fedldxf fedldxfep fedmap
47. l bytes 421671 nlines 1000 xp 1000 0027265b total bytes 468571 nlines 1100 xp 1100 0027dd8f total bytes 515471 nlines 1200 xp 1200 002894c3 total bytes 562371 nlines 1300 xp 1300 00294bf7 total bytes 609271 nlines 1400 xp 1400 002a032b total bytes 656171 nlines 1500 xp 1500 002aba5f total bytes 703071 nlines 1600 xp 1600 002b7193 total bytes 749971 nlines 1700 xp 1700 002c28c7 total bytes 796871 nlines 1768 xp 1768 002ca55b total bytes 828763 nlines 1769 xp 1769 002ca730 total bytes 829232 nlines 1770 xp 1770 002ca905 total bytes 829701 nlines 1771 xp 1771 002caada total bytes 830170 nlines 1772 xp 1772 002cacaf total bytes 830639 nlines 1773 xp 1773 002cae84 total bytes 831108 nlines 1774 xp 1774 002cb059 total bytes 831577 nlines 1775 xp 1775 002cb22e total bytes 832046 nlines 1776 xp 1776 002cb403 total bytes 832515 nlines 1777 xp 1777 002cb410 total bytes 832528 xilinx file total lines 1777 xilinx file header length 40 bytes xilinx file total length including startup bits 832536 bytes fedldxf xfile 00200000 nlines 1777 bytes 832536 fedldxf OK correct number of bits found for Xilinx load fedldxf before loading status result 0 INIT 1 DON fedldxf loading xfile to fpga XC4036 XL fedldxf wrote x
48. me 1401 INIT 1 DONE 0 fedldxf Frame 1501 INIT 1 DONE 0 fedldxf Frame 1601 INIT 1 DONE 0 fedldxf Frame 1701 INIT 1 DONE 0 fedldxf write_xilinx_footer result 0 INIT 1 DONE 1 fedldxf XC4036_XL loaded ok FED Mon See also fedldxfep Version 2 0 43 January 2001 FED Mon User Manual CMS FED PMC 2001 9 24 FEDLDXFEP Name Syntax Parameters Description Example Version 2 0 fedldxfep load Xilinx configuration file to Flash EEPROM fedldxfep fedldxfep source address dest address packed address source address gt seen from RIO 10 0000 dest address gt seen from RIO 20 0000 lt packed address gt seen from RIO 30 0000 WARNING This command is for Experts only It PERMANENTLY changes the FED PMC firmware The fedldxf command takes a Xilinx rbt formatted configuration file preloaded at source address in system memory verifies it and writes out formatted data for Flash EEPROM to lt packed address gt Finally it loads Flash EEPROM with formatted data If no arguments are passed defaults are used Care should be taken to ensure there is sufficient space above each address chosen depending on Xilinx file size if the defaults are not used e g 1 Mbyte for standard XC4036XL rbt file NB Xilinx configuration file must be already loaded in memory before calling fedldxf Flash EEPROM is preloaded at delivery with standard FED Xilinx conf
49. mode is lt lt ENABLED gt gt FED Mon See also Version 2 0 65 January 2001 FED Mon User Manual 9 40 FEDTMOD Name Syntax Parameters Description Example See also Version 2 0 fedtmod display set FED Test mode fedtmod fedtmod lt operation gt lt operation 0 Disable FED Test mode 1 Enable FED Test mode Enable or Disable Test mode If no parameter is passed display status Enable test mode ED Mon fedtmod 1 edtmod Test mode is lt lt ENABLED gt gt ED Mon Fx Fe in 66 CMS FED PMC 2001 January 2001 FED Mon User Manual CMS FED PMC 2001 9 41 FEDTRG Name Syntax Parameters Description Example See also Version 2 0 fedtrg display set External trigger source and mode fedtrg fedtrg trigger source trigger mode lt trigger source gt 0 Front Panel 2 J4 LVDS 3 J4 TTL trigger mode gt 0 Start Digitisation Set Display External trigger source and mode If no arguments are passed the trigger status is displayed NB fedswt can be used to generate software triggers Select front panel external triggers FED Mon fedtrg 0 0 fedtrg trigger source FRONT PANEL TRIGGER fedtrg trigger mode START DIGITISATION FED Mon fedswt 67 January 2001 FED Mon User Manual CMS FED PMC 2001 9 42 FEDXLST Name fedxlst Rea
50. ning FED Mon To run FED Mon PPC Mon exec 10000 starting code execution at address 4a614 FEDMON Version of Dec 6 2000 at 10 29 49 WARNING RUNNING FEDMON TEST VERSION PPC regs msr 0x00001030 hid0 0x80000080 INFO gt DOING VME SETUP FED PMC VME A32 base len 2 MB SYS MEM start VME A32 base 200000 len 4 RIO A24 base for CSR xx460000 RIO A32 base for System Memory 08000000 QUESTION gt Which PMC Slot is FED in 1 upper 2 INFO gt OK Using PMC Slot 2 WARNING gt PCI CFG is using RIO2 MAPPING MB 2 fedmem pci_cfg_base 80802000 fedmem pci mem base abs 01200000 fedmem pci device number 03 bridge config regs pci cfg base 80802000 vendor id fed010dc PCI9080 PCIIDR bridge cmd status reg 00000006 PCI9080 PCICR dpm pci mem base 01200000 PCI9080 PCIBAR2 reg fifo pci mem base 01300000 PCI9080 PCIBAR3 bridge pci mem base 01300100 PCI9080_PCIBARO fedbrg default values were set CMS FED PMC 2001 lower default CR gt bridge local regs pci mem base c1300100 dpm local base 00000001 PCI9080 LASOBA dpm window size S fff00000 PCI9080 LASORR dpm descriptor 030300c3 PCI9080 LBRDO regs local base 00100001 PCI9080 LAS1BA regs window size
51. ntax fedadc fedadc adc chan mask adc sample freq adc sample size Parameters lt adc chan mask gt 0 f adc sample freq gt 0d0 0d255 adc sample size gt 0d16 0d256 0d32768 Description Initialises the FED ADC registers If no arguments are passed the status is returned adc chan mask 0 f bit 0 1 0 enables disables ADC pair 0 amp 1 bit 41 1 0 enables disables ADC pair 2 amp 3 bit 42 1 0 enables disables ADC pair 4 amp 5 bit 3 1 0 enables disables ADC pair 6 amp 7 adc sample freq 0 Sample at clock frequency 1 Sample at 1 2 clock frequency event size Number of samples to readout per event allowed values 2 where 4 n lt 15 Example Enable all ADC channels Sample at the clock frequency Readout 256 samples per trigger FED Mon fedadc f 0 0d256 adc chan mask aa adc chans 0 amp 1 are ENABLED 2 amp 3 are gt gt ENABLED lt lt 4 amp 5 are gt gt ENABLED lt lt 6 amp 7 are gt gt ENABLED lt lt adc sample freq 0 adc sample size 256 decimal FED Mon See also fedinit fedstat Version 2 0 20 January 2001 FED Mon User Manual CMS FED PMC 2001 9 3 FEDBRG Name fedbrg set up fed PMC bridge PCI local registers Syntax fedbrg fedbrg dpm size dpm base dpm desc reg size reg base reg desc Parameters dpm size gt size of window for DPM space fff0 0000 lt dpm base gt local base
52. oaded fedstat reset default bridge configuration fedstat reset default bridge configuration fed regs 8 pci mem base c1300080 Digitisation is DISABLED Test mode is DISABLED Throttle is DISABLED throttle threshold 000000ab Clock source 0 Clock source PCI CLOCK Clock delay 0 Trigger source 0 Trigger source gt FRONT PANEL TRIGGER Trigger mode 0 Trigger mode START DIGITISATION adc chan mask aa ADC chans 0 amp 1 are lt lt ENABLED gt gt 2 amp 3 are lt lt ENABLED gt gt 4 5 are lt lt ENABLED gt gt 6 amp 7 are lt lt ENABLED gt gt ADC Sample Freq 0 ADC Sample Size 16 Number of Filled Buffers 0 INFO gt The FED PMC is Initialized and ready to take data INFO gt FED Serial Number 004 dec fedrev Version information FIRMWARE Xilinx version 0 revison 2 prototype 0 SOFTWARE FED Mon Version of Dec 6 2000 at 11 05 34 FEDPMC s w library version 2 07 INFO gt Type fed for a full list of FED Mon commands FED Mon Notes 1 FED Mon begins by asking the user for the PMC slot number and then configures the FED PMC PCI Bridge 2 It then checks if the Xilinx FPGA is initialized and if not it tries to load it from the onboard Flash EEPROM The Flash EEPROM is loaded prio
53. ons prom word 4 00 wrote Sfed0 prom word 01 wrote 10dc orom word 4 02 wrote 0000 prom word wrote 0000 E E E E Eprom word 4 04 wrote 0000 Eprom word 4 05 wrote 0000 Eprom word 4 06 wrote 0000 Eprom word 07 wrote 0000 Eprom word 4 08 wrote 0000 Eprom word 4 09 wrote 0000 Eprom word 10 wrote Sfff0 Eprom word 11 wrote 0000 Eprom word 12 wrote 0000 Eprom word 13 wrote 0001 Eprom word 14 wrote 0000 Eprom word 15 wrote 0000 Eprom word 4 16 wrote 0000 Eprom word 17 wrote 0000 Eprom word 18 wrote 0000 Eprom word 19 wrote 0000 Eprom word 4 20 wrote 0000 Eprom word 21 wrote 0000 Eprom word 22 wrote 0303 E prom word wrote 00c3 Version 2 0 50 January 2001 FED Mon User Manual prom prom O O O O O O BBBBS O OOO m ES Hy DO HOG GOOD O BBR BAB BRB KRR RR T O 0 0 00 0O00 0O SS A E OX 4 A SE DA de BB HR 00 90 tg K K O OOOO E Ad od Ed f O 5 O 3 O O O O O K O rom FOL Db py pep pep Hd pub Hd buf El 606 DE id Deb td Dep El El pxf Dub xf Ed pub Ed Def pub DEP pu Lu pu bd Ed PED E Deb Ed Deb Ed Ld See also n word n word n word n word n word n word word n word n word n word word n word n word n word n word n word n word n word n word n word n word n word n word n word n word n word n word n word
54. p 8 00200cfb total bytes 3323 nlines 9 xp 9 00200ed0 total bytes 3792 nlines 100 xp 100 0020b587 total bytes 46471 nlines 200 xp 200 00216cbb total bytes 93371 nlines 300 xp 300 002223ef total bytes 140271 nlines 400 xp 400 0022db23 total bytes 187171 nlines 500 xp 500 00239257 total bytes 234071 nlines 600 xp 600 0024498b total bytes 280971 nlines 700 xp 700 002500bf total bytes 327871 nlines 800 xp 800 0025b7f3 total bytes 374771 nlines 900 xp 900 700266f27 total bytes 421671 nlines 1000 e 0027265b total bytes 468571 nlines 1100 xp 1100 0027dd8f total bytes 515471 nlines 1200 xp 1200 002894c3 total bytes 562371 nlines 1300 xp 1300 00294bf7 total bytes 609271 nlines 1400 xp 1400 002a032b total bytes 656171 nlines 1500 xp 1500 002aba5f total bytes 703071 nlines 1600 xp 1600 002b7193 total bytes 749971 nlines 1700 xp 1700 002c28c7 total bytes 79687 nlines 1768 xp 1768 002ca55b total bytes 828763 nlines 1769 xp 1769 002ca730 total bytes 829232 nlines 1770 xp 1770 002ca905 total bytes 829701 nlines 1771 xp 1771 002caada total bytes 830170 nlines 1772 xp 1772 002cacaf total bytes 830639 nlines 1773 xp 1773 002cae84 total bytes 831108 nlines 1774 xp 1774 002cb05
55. p packet number 640 file length Oxcbbb9 834489 transfer rate 11 kbyte sec PPC_Mon gt iv Reload and run FED_Mon PPC_Mon gt exec 10000 starting code execution at address 46930 uu bd more printout FIRMWARE Xilinx version 0 revison 2 prototype 0 SOFTWARE FED Mon Version of Dec 6 2000 at 11 05 34 FEDPMC s w library version 2 07 INFO gt Type fed for a full list of FED Mon commands FED Mon Version 2 0 10 January 2001 FED Mon User Manual CMS FED PMC 2001 v Reload Flash EEPROM contents from file NB The user is given a couple of chances to abort the action FED Mon fedldxfep fedldxfep default rio addresses xilinx file source 8 00100000 dest 00200000 fedldxfep WARNING This command overwrites contents of Flash EEPROM with new Xilinx file fedldxfep Do you really want to do this fedldxfep Type yes to continue any other character to abort gt fedldxfep OK continuing nlines 0 xp 0 00200000 total bytes 0 nlines 1 xp 1 00200028 total bytes 40 nlines 2 xp 2 002001fd total bytes 509 nlines 3 xp 3 002003d2 total bytes 978 nlines 4 xp 4 002005a7 total bytes 1447 nlines 5 xp 5 0020077c total bytes 1916 nlines 6 xp 6 00200951 total bytes 2385 nlines 7 xp 7 00200b26 total bytes 2854 nlines 8 x
56. r is passed display status Nb APV new Scope mode must be DISABLED for APV header finding Enable APV new Scope mode FED_Mon gt fedapvscp 1 fedapvscp APV NEW Scope mode is lt lt ENABLED gt gt FED_Mon gt fedapvmod 74 January 2001 FED Mon User Manual CMS FED PMC 2001 9 49 FEDAPVTHR Firmware v2 only Name fedapvthr Display Set APV Header thresholds Syntax fedapvthr fedapvthr high threshold low threshold Parameters high threshold gt APV header threshold high lt low threshold gt APV header threshold low Description Set high and low thresholds for APV header finding If no arguments are passed threshold values are displayed Example Set high threshold 100 and low threshold 50 FED Mon fedapvthr 0d100 0d50 fedapvthr Set APV header thresholds fedapvthr APV frame thresh high 0d100 thresh low 0d50 FED Mon See also Version 2 0 75 January 2001 FED Mon User Manual CMS FED PMC 2001 9 50 FEDFEND Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedfend display set FED FrontEnd ADCs to DPM mode fedfend fedfend lt operation gt lt operation 0 Disable FrontEnd ADCs to DPM 1 Enable FrontEnd ADCs to DPM Enable or Disable FrontEnd ADCs to DPM If no parameter is passed display status The FrontEnd ADCs to DPM can be disabled ie BYPASSED for pattern genera
57. r to delivery with standard Xilinx configuration file Version 2 0 7 January 2001 FED Mon User Manual CMS FED PMC 2001 NB Once the Xilinx is loaded the red LED which came on when power was applied should now go OFF the Xilinx loading takes 5 seconds 3 The FED PMC registers are then initialized to some standard default values and their status displayed Note that the FED PMC serial number and the Xilinx FPGA firmware version are displayed The FED PMC is now ready to take data 5 Data taking After startup FED Mon initialises the FED PMC with default settings which can be changed using appropiate commands e g ADC sample size clock source etc NB After intialisation the default settings use the internal PCI bus clock 33 MHz 5 1 Running with the PCI clock and software triggers IMPORTANT These data taking examples assume the FED PMC FPGA is loaded with firmware version vOr2 i e old Scope mode For firmware version v2rNN i e Header Finding mode additional commands are required The following example sends 4 software triggers and displays the start of the ADC contents for the first event only in this example there are no connections to the data inputs hence the values 1 2 full scale i FED Mon fedstart 1 fedstart FED data acquisition Run is STARTED using SOFTWARE triggers ii FED Mon fedswt 4 fedswt sent software trigger 1 fedswt sent software trigger 2 fedswt sent
58. rce 00306400 size 00000100 FEDPMC DEBUG gt page 200 source 0030c800 size 00000100 FEDPMC DEBUG gt page 300 source 00312c00 size 00000100 FEDPMC DEBUG gt page 400 source 00319000 size 00000100 FED Mon See also Version 2 0 45 January 2001 FED Mon User Manual fedldxf Version 2 0 46 CMS FED PMC 2001 January 2001 FED Mon User Manual 9 25 FEDMAP Name Syntax Parameters Description Example See also Version 2 0 fedmap display FED address map fedmap none Just for expert debugging of register contents CMS FED PMC 2001 Useful if used with PPC MON dm amp dp commands Nb Address values may vary according to PMC slot number and FED Mon version Display FED base addresses FED Mon fedmap fedmap Memory Map for FED PMC pci mem base dpm c0000000 pci mem base fifo c0100000 pci mem base fed regs c0100080 pci mem base bridge c0100100 FED Mon then to display fed regs status FED Mon dp w c1000080 0xc1000080 0000aa00 000000ab 00000100 0xc1000090 00000000 000003ff 000003ff 0xc10000a0 00100000 00000000 00000000 0xc10000b0 000000ff 000000ff 00100058 0xc10000cO0 001000cO0 001000c4 001000c8 Oxc10000d0 001000d0 001000d4 00100088 0xc10000e0 001000e0 001000e4 001000e8 0xc10000f0 001000f0 001000f4 00000001 FED Mon fedbug 47 0000000 00000000 000000f
59. seseses sesse se se sesse se se ses ee ee se se se sesse 14 USING PPC MON COMMANDS reete see ss sina oie Fees Es See ro ese Sai Gee see dee ses keines Vow e a Ee eo 15 FED MON COMMANDS esse se ese see sees he herr sesse Ses ve EE ue ss soss Sob ele sss seg ases en cae GE sie 16 9 1 FEEDS EID canes ete e eer ue 18 9 2 IdsiD Vcn 20 9 3 EEDBRG eie Ren eie voee EVEN E IM eM EN De HE ET 21 9 4 oie Bed dia ER ie E N RO eet o eti eee onte one adh ees Moved dias 22 9 5 FEDBUE E UII VQ 23 9 6 FEDBUG H P 24 9 7 FED GR GEG LEE 25 9 8 FEDCIK 2 suas dak ns A ice 26 9 9 do Ein do 27 9 10 BED DIG iis feted DER 28 9 11 FEDDP 22255 Ree Ev eie e rede I AR De EE UR EE E 29 9 12 FEDDEMEL T ER EE OE N GE EE EN RE EO EE EE N OE 30 9 13 EBDEEPRD uU Iu a e Ee Ge Ge E a e ech ee e E SE De UE 31 9 14 FEDEEPW SE EE OE EE EE nV Sew dtc oe OE Soa EO EK 32 9 15 FEDFIFO EE 33 9 16 FEDER N SE ER EE OR DAN EE EE OE OE N n MEN 34 9 17 EEDIDRD SEE 35 9 18 ie BAR dE 36 9 19 EEDINTT EET 37 9 20 FEDIZATEBDB 5 1 N ER ET eed RE N N EO EE OE EE ONE 39 9 21 FEDLEXTRD ee ME IM Or e E EU M 40 9 22 io DIPL NAVI Hv 41 9 23 IN O 42 9 24 FEDEDXFEP EE OE NE OE N OE OE ss 44 9 25 EEDMA V UEM 47 9 26 FED MEM dtt ente ree ee reete teret dexter nee ce wed doc tete dos dine eee netus td Dees Rese 48 9 277 EEDPLEXBEPER ee A eie eee ere ERN de ve Gee EIE 49 9 28 FEDPEXEPEL 20 OE EE a EE EE EE EO N OE OE HE OIE 50 9 29 EEDPL
60. software trigger 3 fedswt sent software trigger 4 fedbuf number of filled buffers 4 iii FED Mon fedrout readout time for 16 samples skip begin end 0 0 452 micro sec fedrout Readout Event data to RIO address 00300000 Event no 00000000 Bunch no 49148 Event size 256 bytes Number Samples 16 Skipped samples begin end 0 0 Buffer base in dpm 00000000 Unformatted data follows ADC Chant gt 0 T 2 3 4 5 6 7 Sample 000 0284 0278 0274 0277 0280 0280 0280 0279 Dec 001 0284 0278 0274 0277 0280 0280 0281 0279 Dec 002 0284 0279 0274 0277 0280 0280 0280 0279 Dec 003 0284 0278 0274 0277 0280 0279 0280 0278 Dec 004 0284 0278 0274 0277 0280 0280 0280 0279 Dec 005 0284 0278 0275 0277 0280 0280 0280 0279 Dec Version 2 0 8 January 2001 FED Mon User Manual CMS FED PMC 2001 006 0284 0279 0274 0277 0280 0280 0281 0279 Dec 007 0284 0279 0275 0277 0280 0280 0281 0279 Dec 008 0284 0279 0274 0277 0280 0280 0280 0279 Dec 009 0284 0279 0274 0277 0280 0280 0281 0279 Dec 010 0284 0278 0274 0277 0280 0280 0280 0279 Dec 011 0284 0278 0274 0277 0280 0280 0280 0279 Dec 012 0284 0278 0274 0277 0280 0280 0280 0278 Dec 013 0284 0278 0274 0277 0280 0280 0280 0278 Dec 014 0284 0279 0275 0277 0280 0280 0281 0279 Dec 015 0284 0279 0274 0277 0280 0280 0281 0279 Dec
61. t 0 f adc sample freq gt 0 ff lt adc sample size gt 0d16 0d256 0d32768 lt trigger throttle enable gt 0O OFF 1 ON lt trigger throttle threshold gt 0 3 f Initialises the FED specific registers If no arguments are passed defaults are used Actual clock delay is clock delay x 2 5 nsec i e 0 25 nsec range adc chan mask 0 f bit 0 1 0 enables disables ADC pair 0 amp 1 bit 1 1 0 enables disables ADC pair 2 amp 3 bit 2 1 0 enables disables ADC pair 4 amp 5 bit 3 1 0 enables disables ADC pair 6 amp 7 adc sample freq Number of clock cycles between samples event size Number of samples to readout per event granularity 16 samples event Initialise FED PMC with defaults FED_Mon gt fedinit fedinit using default values fedinit WARNING gt If Bus errors here the CLOCK may NOT be running fedinit WARNING gt If we stop here the Xilinx may NOT be loaded fedstat fed register status only fedstat ATTENTION gt If we stop here the Xilinx is NOT Loaded fedstat reset default bridge configuration fedstat reset default bridge configuration fed regs 8 pci mem base c0100080 Digitisation is DISABLED Test mode is DISABLED Throttle is DISABLED 37 January 2001 FED Mon User Manual CMS FED PMC 2001 throttle threshold
62. tion tests to DAQ Normally FrontEnd ADCs to DPM should be enabled for ADC capture Enable FrontEnd ADCs to DPM ED_Mon gt fedfend 1 edfend Frontend is lt lt ENABLED gt gt ED_Mon gt Hr eso feddpmfl 76 January 2001 FED Mon User Manual CMS FED PMC 2001 9 51 FEDINTFIFO Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedintfifo display enable FED Internal FIFO fedintfifo fedintfifo lt operation gt operation gt 0 Disable FED Internal FIFO 1 Enable FED Internal FIFO Enable or Disable Internal FIFO If no parameter is passed display status Internal FIFO is needed to handle triggers with separation lt 7 BX Enable Internal FIFO FED_Mon gt fedintfifo 1 fedintfifo Internal FIFO is lt lt ENABLED gt gt FED_Mon gt 77 January 2001 FED Mon User Manual CMS FED PMC 2001 9 52 FEDTRGFLT Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedtrgflt display enable FED Trigger filter fedtrgflt fedtrgflt lt operation gt lt operation 0 Disable FED Trigger Filter 1 Enable FED Trigger Filter Enable or Disable Trigger Filter If no parameter is passed display status Filter rejects External Triggers with illegal patterns eg 101 Enable Trigger Filter FED Mon fedtrgflt 1 fedtrgflt Tr
63. vparm 0d275 0d65 0d139 fedapvparm Set Read APV timeout parameters fedapvparm APV frame parms frame timeout 0d275 tick timeout 0d65 frame size 0d139 FED Mon fedapvpov 72 January 2001 FED Mon User Manual CMS FED PMC 2001 9 47 FEDAPVPOV Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedapvpov display set FED APV Timeout parameters override mode fedapvpov fedapvpov lt operation gt lt operation 0 Disable APV Timeout parameters override 1 Enable APV Timeout parameters override Enable or Disable APV Timeout parameters override If no parameter is passed display status APV Timeouts must be overridden before new values set by fedapvparm become active If APV Timeout parameters override mode is Disabled following reset defaults are used Enable APV Timeout parameters override ED Mon fedapvpov 1 edapvpov APV Timeout parameters override is ENABLED ED Mon ks Pk ih fedapvparm 73 January 2001 FED Mon User Manual CMS FED PMC 2001 9 48 FEDAPVSCP Firmware v2 only Name Syntax Parameters Description Example See also Version 2 0 fedapvscp display set FED APV new Scope mode fedapvscp fedapvscp lt operation gt lt operation gt 0 Disable FED APV new Scope mode 1 Enable FED APV new Scope mode Enable or Disable APV new Scope mode If no paramete
64. x0000 0x0000 0x0000 0x0000 0x0000 ll 0x0000 0x0000 0x0000 0x0000 0x0000 ll ll 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 53 CMS FED PMC 2001 January 2001 FED Mon User Manual CMS FED PMC 2001 9 30 FEDPLXEPWR Name fedplxepwr Write to an individual location in PLX serial eprom Syntax fedplxepwr Parameters none Description WARNING This command is for Experts only Overwrites the contents of a single 16 bit location in the serial eprom attached to PLX PCI bridge chip with specified value 1st location is at address 0 Example Fill contents of 2nd location in PLX serial eprom with value beef FED Mon fedplxepwr 1 beef fedplxepwr Write to an individual location in PLX serial eprom fedplxepwr WARNING This command overwrites contents of PLX serial eprom fedplxepwr Do you really want to do this fedplxepwr Type yes to continue any other character to abort gt fedplxepwr OK continuing KKKKKKKK Writing to PLX Eprom Starting at location 1 for 1 locations Eprom word 01 wrote Sbeef PLX serial eprom is reprogrammed with new value FED Mon See also fedplxeper fedplxepfl fedplxeprd Version 2 0 54 January 2001 FED Mon User Manual 9 31 FEDREV Name Syntax Parameters Description Example See also Version 2 0 CMS FED PMC 2001 fedrev display FED hardware and softwar
65. x00500020 debdfebf ebdebdeb deffeffe bfebdefd 0x00500030 eaf7affb fTbffbff bdfafffd ddfdffeb 0x00500040 bffdffdf fdffdffd ffdfffff ff7dfff7 0x00500050 ff7ff7ff 7ff7ffed Tedledle dffed7ed 0x00500060 fedfedfe d7ed7ed7 edfedffb 7fb5fb7f 0x00500070 35f35f5d ffdddfdf fffebfff ffffffff 5 FED Mon fedfepwr fedldxfep 31 January 2001 FED Mon User Manual CMS FED PMC 2001 9 14 FEDFEPWR Name Syntax Parameters Description Example See also Version 2 0 fedfepwr write to Flash EEPROM memory fedfepwr fedfepwr source address number pages source address gt in RIO system mempty 40 0000 number pages gt number of Flash EEPROM pages to fill 1 WARNING This command is for Experts only Fill Flash EEPROM memory from contents at a specified address in RIO memory Note Page size 264 bytes If no arguments are passed defaults are used Flash EEPROM is preloaded at delivery with standard FED Xilinx configuration file To load new configuration file use fedldxfep Writing to the Flash EEPROM will overwrite the existing Xilinx file in memory Overwrite first page in Flash EEPROM FED Mon fedfepwr fedfepwr This command overwrites contents of Flash EEPROM fedfepwr Do you really want to do this fedfepwr Type yes to continue any other character to abort

fedmon

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