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TM87P08 User`s Manual

1. Name Symb Condition Port Min Typ Max Unit Output H Voltage Voh3c loh 1mA 3 1 5 1 8 V Voh4c 3 4 5 9 2 5 3 0 V EG1 41 Output L Voltage Vol3c 2 3 SEG 0 6 0 9 V Voldc lol 6mA zt4 1 0 1 5 V Segment Driver Output Characteristics Name Symb Condition For Min Typ Max Unit 1 2 Bias Display Mode Output H Voltage Voh3f loh 1uA 23 2 2 V Voh4f loh 1uA Z4 SEG n 3 8 V ET Vol3f lol 1uA 3 0 2 V Output L Voltage Vol4f lol 1uA 4 0 2 V Output H Voltage Voh3g loh 10uA Z3 COM n 2 2 V Voh4g loh 10uA Z4 3 8 V Output M Voltage Vom3g_ lol n 10uUA 3 1 0 1 4 V Vom4g_ lol h 10UA 4 COM n 1 8 2 2 V Vol3g lol 10uA 3 0 2 V Output L Voltage Voldg ol210uA Z4 0 2 V 1 3 Bias display Mode Output H Voltage loh 1uA 3 3 4 V Vohdi loh 1uA Z4 5 8 V Output M1 Voltage venus lol h 10UA 3 1 0 1 4 V Vom14i lol h 10UA 4 SEG n 1 8 2 2 V M Vom23i lol h 10uA 3 2 2 2 6 Output M2 Voltage Vom24i_ lol h 10uA 4 3 8 4 2 V Vol3i lol 1uA 3 0 2 V Output L Volt UP O99 Woli iol 1uA 4 0 2 V Output Voltage won loh 10uUA 3 3 4 V Voh4j loh 10uA Z4 5 8 V Vom13j lol h 1 Output M1 Voltage om 3 ol h 10UA 3 1 0 1 4 V Vom14j lol h 7 10uA Z4 COM n 1 8 2 2 V Output M2 Voltage Vom23j lol h 10UA 3 2 2 2 6 V Vom24j lol h 10uA 4 3 8 4 2 V Ou
2. SCA intruction Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOC1 is changed from L level to H level or from H level to L level and the remaining pins ex IOC2 to IOCA are held at L level When the signal changes at the input pins of IOC port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF1 At that time the chattering prevention clock will stop due to the delivery of SCF1 The SCF1 will be reset to O by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF1 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOC interrupt enable mode IEFO is provided the interrupt is accepted 63 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Since no flip flop is available to hold the information of the signal at the input pins IOC1 to IOCA the input data at the port IOC must be read into the RAM immediately after the halt mode is released 3 5 4 IOD PORT IOD1 1004 pins are MUXed with SEG36 SEG37 SEG38 and SEG39 pins respectively by mask option MASK OPTION table Mask O
3. 5 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 1 5 PAD COORDINATE z o Name X Y Name X XIN 102 70 1732 00 SEG10 K10 2587 30 XOUT 102 70 1610 20 SEG11 K11 2587 30 FRIN 102 70 1495 20 SEG12 K12 2587 30 FROUT 102 70 1373 40 SEG13 K13 2587 30 CFIN 102 70 1258 40 SEG14 K14 2587 30 CFOUT 102 70 1136 60 SEG15 K15 2587 30 GND 102 70 1018 85 SEG16 K16 2587 30 RESET 102 70 901 10 SEG17 2587 30 INT 102 70 779 10 SEG18 2587 30 VDD1 102 70 662 00 SEG19 2587 30 VDD 2 102 70 547 00 SEG20 2587 30 VPP 102 70 341 50 SEG21 2587 30 VDD3 145 60 106 70 SEG22 2301 15 CUP1 283 05 102 70 SEG23 2156 95 CUP2 425 35 102 70 SEG24 IOA1 CX 1987 05 COM 569 75 102 70 25 2 1842 85 COM2 740 15 102 70 SEG26 IOA3 RT 1640 45 910 55 102 70 SEG27 IOAM RH 1496 25 COM4 1080 95 102 70 SEG28 IOB1 1326 35 COMS DC5 OD5 1251 35 102 70 29 2 1182 15 COMG DC6 OD6 1421 75 102 70 DC30 0D30 I0B3 BZB 1053 45 COM7 DC7 OD7 1592 15 102 70 SEG31 IOB4 BZ 902 15 COM8 DC8 OD8 1762 55 102 70 lOC1 KI1 763 45 DC9 OD9 1907 45 102 70 IOC2 KI2 616 25 SEG1 K1 2038 55 102 70 lOC3 KI3 496 25 SEG2 K2 2182 75 102 70 IOC4 KI4 349 05 SEG3 K3 2320 15 102 70 IOD1 102 70 SEG4 K4 2587 30 256 50 IOD2 102 70 SEG5 K5 2587 30 400 70 IOD3 102 70 SEG6 K6 2587 30 538 10 IOD4 102 70 Q SEG7 7 2587 30 682 30 SEG40 102 70 SEG
4. 23 2 7 Data Memory RAM Ree Ae 24 2 8 Working Register 2262 25422 2 2 42242424424424224224242 424424254044242544424254244442423232 25 2 9 Accumulator AG ecce a A SASA D Dd d 25 2 10 ALU Arithmetic and Logic Unit a tenets 25 2 11 Hexadecimal Convert to Decimal HCD 25 723 10 20 Timer eoo Pete Pe Uo ON RAD eee on Eevee Sere 27 22413 mer 2 CTMR2 2 2u TENUIS 30 2 14 Stat s Register STS uuu uuu nene uqusqa ia ataqa 34 2 15 Control Register To us us 39 246 HALT FUNCION oss ORO PUEDEN DROP 42 2 17 Back up Function a es qartul stutenda da 43 1 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual DATO OTOP FUNCION eee eee 43 CHAPTER Control Function J 45 3 1 Interrupt 0 1 metr 45 3 2 aa 48 3 3 Clock Generator Frequency Generator and 52 3 4 Buzzer Output PINS inadecuado casae mid cate dide od qid idee 55 3 5 Input cat taedet cat eio ato at tat n
5. 2 AC1 ACO Rx3 R2 SPK HL T HL7 TGHL6 T HL5 T HL4 T HL3 T HL2 T HL1 T HLO The following description shows the bit definitions in the operand of the SPKX instruction 72 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Xs 0 when HEF5 is set to 1 the HALT release request HRF5 will be set to 1 after the key depressed on the key matrix and then SCF7 will be set to 1 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle regardless of key depression and then SCF7 will be set to 1 X7Xs5X4 000 in this setting each scanning cycle only checks one specified column K1 K16 on the key matrix The specified column is defined by the setting of Xo Xo 0000 activates K1 column Xo 0001 activates K2 column Xo 1110 activates K15 column Xo 1111 activates K16 column X7X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle Xs Xo are not a factor X7X5Xq4 010 in this setting the key matrix scanning function will be disabled Xo are not a factor X7X5X4 10X in this setting each scanning cycle checks 8 specified columns on the key matrix The specified column is defined by the setting of X3 Xs 0 activates K1 K8 columns simultaneously Xs 1 activates K9 K16 columns simultaneously X
6. 1 The CF is set to 1 X1 1 The chip enters backup mode and BCF is set to 1 X4 1 The watchdog timer is initiated and active XT 1 Enables the re load function of timer 1 X6 5 is reserved RF X machine code 1111 0100 X700X4 00X1Xo function Resets flag description Description of each flag 1 The CF is reset to 0 X1 1 The chip is out of backup mode and BCF is reset to 0 X4 1 The watchdog timer is inactive XT 1 Disables the re load function of timer 1 X6 5 3 is reserved SF2 X function Sets flag description Description of each flag X4 1 Enable low battery detected function X3 1 Enable INT powerful pull low X2 1 Disables the LCD segment output X1 1 Sets the DED flag Refer to 2 12 3 for detail 1 Enables the re load function of timer 2 118 tenx technology inc Rev 1 0 2004 2 2 RF2 X function description PLC Function Description TM87P08 User s Manual X7 6 is reserved Resets flag Description of each flag X4 1 Disable low battery detected function 1 Disable INT powerful pull low X2 1 Enables the LCD segment output X1 1 Resets the DED flag Refer to 2 12 3 for detail 1 Disables the re load function of timer 2 X7 6 is reserved Pulse control The pulse corresponding to the data specified by X is generated 1 Halt release request flag HRFO caused by the signal at I O port C is reset
7. XXXX lt Rx 1 INC HL 0100 0000 1000 0000 AC HL lt QHL 1 CF INC HL 0100000 1100 0000 AC HL lt HL 1 CF 123 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual HL HL 1 DEC Rx 0100 0001 OXXX XXXX AC Rx Rx 1 CF DEC 0100 0001 1000 0000 AC HL lt HL 1 CF DEC HL 01000001 1100 0000 AC QHL lt QHL 1 CF HL lt HL 1 IPA Rx 0100 0010 OXXX XXXX AC Rx Port A IPB Rx 0100 0100 OXXX XXXX AC Rx Port B IPC Rx 0100 0111 OXXX XXXX JAC Rx lt Port C IPD Rx 0100 1000 XXXX Port D MAF 0100 1010 OXXX XXXX JAC Rx lt STS1 B3 CF B2 ZERO B1 No use BO No use MSB 0100 1011 OXXX XXXX JAC Rx lt STS2 B3 SCF3 DPT B2 SCF2 HRx B1 SCF1 CPT BO BCF MSC 0100 1100 OXXX XXXX JAC Rx 5153 B3 SCF7 PDV B2 PH15 B1 SCF5 TM1 BO SCFA INT MCX 0100 1101 OXXX XXXX JAC Rx lt STS3X SCF9 RFC B2 unused B1 SCF6 TM2 BO SCF8 SKI MSD Rx 0100 1110 OXXX XXXX JAC Rx STS4 B3 No use B2 FROVF B1 WDF BO CSF SRO Rx 0101 0000 OXXX XXXX ACn Rxn 1 Rx3 _0 581 Rx 0101 0001 OXXX XXXX ACn Rxn 1 Rx3 lt 4 SLO Rx 0101 0010 OXXX XXXX Rxn Rx n 1 ACO Rx0 90 SL1 Rx 0101 0011 OXXX Rxn lt Rx n 1
8. 2 12 1 NORMAL OPERATION TMR1 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TMS or TMSX instruction Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request flag1 HRF 1 to 1 and then stop to count down When 1 1 and the TMR1 interrupt enable flag IEF1 1 the interrupt is generated When 1 1 if the IEF1 0 and the TMR1 halt release enable HEF 1 1 program will escapes from halt mode if CPU is in halt mode and then set the start condition flag 5 SCF5 to 1 in the status register 3 STS3 After power on reset the default clock source of TMR1 is PH3 If watchdog reset occurred the clock source of TMR1 will still keep the previous selection The following table shows the definition of each bit TMR1 instructions OPCODE Select clock TMSX X TMS 0 AC2 AC1 ACO Rx3 R2 Rx1 Rx0 TMS QHL bit7 bit6 bits Bit4 bits bit2 bit bito 27 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The following table shows the clock source setting for TMR1 0 0 E90 PH gt Y 0011 PH Eon 0 _ PHs5 0 11 1 FREQ l O 0 PHS __ ip m w sss 7 Notes 1 When the TMR1 clock is PH3 TMR1 set time Set value error 8 1 fosc KHz ms 2 When the TMR1 clock is PH9 TMR1 set time Set value error 512 1 fosc KHz
9. TM87P08 User s Manual AC lt R HL 1 HL HL 1 Substrates 1 from the content of HL the result is loaded to the data memory HL and AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory AC lt RX AC CF The contents of Rx AC and CF are binary added the result is loaded to AC Carry flag CF will be affected AC lt R HL AC CF The contents of data memory specified by HL AC and CF are binary added the result is loaded to AC Carry flag CF will be affected lt HL AC CF HL lt HL 1 Binary adds the contents of HL AC and CF the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory AC Rx RX AC CF The contents of Rx AC and CF are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected AC R HL lt R HL AC CF The contents of data memory specified by HL AC and CF are binary added the result is loaded to AC and data memory specified by HL Carry flag CF will be affected AC GHL HL AC CF HL 1 94 tenx technology inc Rev 1 0 2004 2 2 Description SBC Rx function
10. is set to 1 the oscillator operates with an extra buffer in parallel in order to shorten the oscillator start up time but this will increase the power consumption Therefore the backup flag should be reset unless required otherwise If XIIN pin is unused it must be connected to VDD2 The following table shows the power consumption of Crystal oscillator in different conditions Li power option EXT V power option BCF 1 BCF 0 Initial reset Increased Increased After reset Normal Increased 2 2 2 CONNECTION DIAGRAM OF FAST CLOCK OSCILLATOR CF CLOCK The CF clock is a multiple type oscillator mask option which provide a faster clock source to system In single clock operation fast only this oscillator will provide the clock to the system clock generator pre divider timer I O port chattering prevention clock and LCD circuitry In dual clock operation CF clock provides the clock to system clock generator only When the dual clock option is selected by mask option this oscillator will be inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BCLK of the system clock generator will be switched to CF clock and the clock source for other functions will still come from XT clock Halt mode stop mode or SLOW instruction execution will stop this oscillator and the system clock BCLK will be switched to XT clock There are 2 type oscillators can be used i
11. CF D represents the immediate data Binary subtracts the CF and immediate data D from the working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH lt Ry D CF D represents the immediate data Binary subtracts the CF and immediate data D from the working register Ry the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC lt Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The carry flag CF will be affected 101 tenx technology inc Rev 1 0 2004 2 2 ADDI Ry D Function Description SUBI Ry D Function Description SUBI Ry D Function Description ADNI Ry D Function Description ADNI Ry D Function Description ANDI Ry D Function Description TM87P08 User s Manual D 0H FH AC Ry lt Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC lt Ry D 1 D represents the immediate data Binary subtracts the immediate data D from the working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry Ry Y 1 D represents the immediate data Binary subtracts the immediate data D fr
12. Rx The content of Rx is outputted to I OA port 1 2 Rx IOA3 D IOA4 lt pulse Content of Rx is outputted to IOA port D is outputted to pulse is outputted to IOA4 D 0or1 Rx AC IOA The data of I OA port is loaded to AC and data memory Rx Defines the input output mode of each pin for IOB port and enables disables the pull low device Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode 86 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The meaning of each bit of X X3 X2 X1 X0 is shown below X4 1 Enable IOB pulllowR X4 0 Disable IOB pull low R X3 1 lOB4asoutputmode X3 0 4 mode X2 1 IOB3 as output mode X2 0 IOB3 as input mode X1 1 lOB2asoutputmode 1 0 IOB2 as input mode X0 1 IOB1 as output mode X0 0 IOB1 as input mode OPB Rx function I OB lt Rx description The contents of Rx are outputted to I OB port IPB Rx function Rx AC IOB description The data of I OB port is loaded to AC and data memory Rx SPC X function Defines the input output mode of each pin for IOC port and enables disables the pull low device or low level hold device description Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each b
13. Rx n Bitn content of Rx 7SEG 7 segment decoder for LCD Ry Address Y of working register BCLK System clock for instruction Address of data RAM specified by HL IEFn Interrupt Enable Flag BCF Backup flag HRFn HALT Release Flag Generic Index address register HEFn HALT Release Enable Flag Content of generic Index address register Lz Address of LCD PLA Latch QL Content of lowest nibble Index register SRFn STOP Release Enable Flag Content of middle nibble Index register SCFn Start Condition Flag QU Content of highest nibble Index register Cch Clock Source of Chattering prevention ckt T HL_ Address of Table ROM Cfq Clock Source of Frequency Generator H T HL High Nibble content of Table ROM SEFn Switch Enable Flag L T HL Low Nibble content of Table ROM FREQ Frequency Generator setting Value TMR _ Timer Overflow Release Flag CSF Clock Source Flag Ctm Clock Source of Timer P Program Page PDV Pre Divider RFOVF Overflow Flag STACK Content of stack RFC Resistor to Frequency counter TM1 Timer 1 RFC n Bit data of Resistor to Frequency counter TM2 Timer 2 129 tenx technology inc Rev 1 0 2004 2 2
14. X1 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 X2 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset 1 Halt release request flag HRF3 caused by overflow from the predivider is reset X4 1 Halt release request flag HRF4 caused by underflow from the timer 2 is reset and stops the operating of timer 2 TM2 X5 1 Halt release request flag HRF5 caused by the signal change to L on KI1 4 in scanning interval is reset X6 1 Halt release request flag HRF6 caused by overflow from the RFC counter is reset X8 1 The last 5 bits of the predivider 15 bits are reset When executing this instruction X3 must be set to 1 simultaneously 119 tenx technology inc Rev 1 0 2004 2 2 IN TM87P08 User s Manual Chapter 6 Programming Waveform VPP 1 K 16 PULSES 17 PULSES 16PUsES k 2PuLses 4 16PULSES f eee C99 98C 99 98x mK Hn INT Ax F Inernal vu is Pons 0000H 0001H y PGM y 2 AB69H Password in k Password retum out 0000H Data in 0001H Data in out This programming application circuit is simply an example CUP1 C
15. Xo don t care X7 X5X4 110 in this setting each scanning cycle checks four specified columns on key matrix The specified columns are defined by the setting of X3 and X X3X2 00 activates K1 K4 columns simultaneously X3X2 01 activates K5 K8 columns simultaneously X3X2 10 activates K9 K12 columns simultaneously X3X2 11 activates K13 K16 columns simultaneously X1 Xo don t care X7X5X4 111 in this setting each scanning cycle checks two specified columns on key matrix The specified columns are defined by the setting of X gt and X4 X3X2X1 000 activates K1 K2 columns simultaneously X3X2X1 001 activates K4 columns simultaneously X3X2X1 110 activates K13 K14 columns simultaneously X3X2X1 111 activates K15 K16 columns simultaneously Xo is not a factor When Kl1 4 is defined for the Key matrix scanning input by mask option it is necessary to execute the SPC instruction to set the internal unused IOC port to output mode before the key matrix scanning function is activated Fig 2 27 shows the organization of the Key matrix scanning input port Each one of the SKI1 4 changed to High will set HRF5 to 1 If HEF5 has been set to 1 beforehand this will cause SCF7 to be set as well as releasing the HALT mode After the key scanning cycle the states of SKI1 4 will be latched and executing the IPC instruction could store these states into data RAM Executing the PLC 20h instruction clears the HRF5 f
16. 1 2 BIAS The backup falg flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin TM87P08 Application Circuit Internal Logic MASK OPTION table Mask Option name Selected item LCD BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 The backup flag BCF is set in the initial clear mode When thebackup flag flag is set the oscillator circuit becomes large in driver size When the backup flag is set the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 2 17 2 1 2 2 1 3 BIAS 12 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual TM87P08 Application Circuit Internal Logic 8 0V 0 1uF MASK OPTION table Mask Option name Selected item LCD BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 The backup flag BCF is set in the initial clear mode When thebackup flag flag is set the oscillator circuit becomes large in driver size When the backup flag is set the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 2 17 13 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 2 S
17. Maximum output Voltage Vout1 0 3 to VDD1 2 0 3 V Vout2 0 3 to VDD3 0 3 V Maximum Operating Temperature Topg 20 to 70 18 Maximum Storage Temperature Tstg 25 to 125 POWER CONSUMPTION at VDD2 3 0V Ta 20 C to 70 C GND 0V Name Sym Condition Min Typ Max Unit Only 32 768KHz Crystal oscillator operating without loading 0 1 4 duty phO BCLK STOP mode ISTOP 1 uA Only 32 768KHz Crystal oscillator operating HALT mode IHALT Norma Moas without loading 0 1 4 duty phO BCLK ui R 150K oscillator operating without loading BCF 0 4 4 duty phO BCLK idi nd 3 58MHz ceramic Only 3 58MHz ceramic resonator operating 480 uA resonator 355Me Without loading BCF 0 1 4 duty phO BCLK Note When External R oscillator function is operating the current consumption will depend on the frequency of oscillation TM87P08 Extrnal V S Freq amp Power Consumption 400 uA 1 6MHz 50 uA 1 4MHz 1 2MHz SOO uA 1 0MHz 250 uA 0 8MHz 200 uA 0 6MHz 150 uA 0 4MHz 100 uA 0 2MHz 50 uA 0 0MHz 0 uA 10K 49K 100K 120K 150K 300K 499K 3 0V 25 8 tenx technology inc Rev 1 0 2004 2 2 ALLOWABLE OPERATING CONDITIONS at Ta 20 C to 70 C GND 0V TM87P08 User s Manual Name S
18. The carry flag CF will be affected AC HL lt BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution O lt AC lt 9 6 lt AC lt F 5 8 JUMP INSTRUCTIONS JBO X function description JB1 X function description JB2 X function description JB3 X function description Program counter jumps to X if ACO 1 If bitO of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC1 1 If bit of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC2 1 If bit2 of AC is 1 jump occurs If O the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC3 1 If bit3 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH 112 tenx technology inc Rev 1 0 2004 2 2 JNZ X function description JNC X funct
19. inc Rev 1 0 2004 2 2 TM87P08 User s Manual Internal reset cycle time is PH15 2 MASK OPTION table Mask Option name Selected item RESET TIME 1 PH15 2 In this option the reset cycle time will be extended 16384 clocks clock source comes form pre divider long at least Internal reset cycle time is PH12 2 MASK OPTION table Mask Option name Selected item RESET TIME 2 PH12 2 In this option the reset cycle time will be extended 2048 clocks clock source comes form pre divider long at least 3 2 1 RESET PIN RESET When H level is applied to the reset pin the reset signal will issue Built in a pull down resistor on this pin Two types of reset method for RESET pin and the type could be mask option the one is level reset and other is pulse reset It is recommended to connect a capacitor 0 1uf between RESET pin and VBAT This connection will prevent the bounce signal on RESET pin 3 2 1 1 Level Reset Once a 1 signal applied on the RESET pin TM87P08 will not release the reset cycle until the signal on RESET pin returned to 0 After the signal on reset pin is cleared to 0 TM87P08 begins the internal reset cycle and then release the reset status automatically MASK OPTION table Mask Option name Selected item RESET PIN TYPE 1 LEVEL 3 2 1 2 Pulse Reset Once a 1 signal applied on the RESET pin TM87P08 will escape from reset state and begin the
20. the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory 99 tenx technology inc Rev 1 0 2004 2 2 EOR Rx Function Description EOR HL Function Description EOR HL Function Description OR Rx Function Description OR HL Function Description OR HL Function Description OR Rx Function Description OR HL Function Description TM87P08 User s Manual AC Rx lt Rx AC Exclusive Ors the contents of Rx and AC the result is loaded to AC and the data memory Rx AC HL HL AC Exclusive Ors the contents of HL and the result is loaded to AC and the data memory HL HL indicates an index address of data memory AC HL HL AC HL 1 Exclusive Ors the contents of HL and AC the result is loaded to AC and the data memory QHL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC lt Rx AC Binary Ors the contents of Rx and AC the result is loaded to AC AC lt HL AC Binary Ors the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory AC lt HL AC HL HL 1 Binary Ors the contents of HL and AC the result is load
21. 0 initiate the underflow counting register PLC 2 SHE 2 enable the HALT release caused by TMR1 TMSX 34h initiate the TMR1 value 52 and clock source is 9 SF 80h enable the re load function RE LOAD HALT INC 0 increase the underflow counter PLC 2 clear HRF1 JB3 END_TM1 if the TMR1 underflow counter is equal to 8 exit subroutine JMP RE_LOAD END_TM1 RF 80h disable the re load function 29 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 13 TIMER 2 TMR2 The following figure shows the TMR2 organization Re load RL2 TM2 instruction IEF Initial reset Interrupt 6 bit binary down counter FREQ 3 5 d HRF4 SE 49 6 Halt release HEF Operand Data 4 X5 X0 Operand Data X8 X7 X6 TM2 instruction TM2 instruction VT Interrupt accept signal R PLC 10h instruction Qu TENX Initial reset DED S Control signal of RFC counter falling edge of the 1st clock after TM2 is enabled 2 13 1 NORMAL OPERATION TMR2 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TM2 or TM2X instruction Once the TMR2 counts down to 3Fh it stops counting then generates an underflow signal and the halt release request flag 4 HRF4 will be set to 1 When HRF4 1 and the TMR2 interrupt enabler IEF4 is set to 1 the interrupt occurred When HRF
22. 2 1 40 1 1 4 Note DBUSF of decoded output can be selected as 0 or 1 by mask option The LCD pattern of this option is shown below DBUSA DBUSA DBUSB i DBUSB lt pause gt lt pause gt DBUSE 171 DBUSC DBUSE DBUSC S O lt 2 O DBUSD DBUSH DBUSD DBUSH DBUSF 0 DBUSF 1 The following table shows the options table for displaying the digit 7 pattern MASK OPTION table Mask Option name Selected item F SEGMENT FOR DISPLAY 7 1 ON F SEGMENT FOR DISPLAY 7 2 OFF Both LCT and LCB instructions use the data decoder table to decode the content of the specified data memory location When the content of the data memory location specified by the LCB instruction is 0 the decoded outputs of DBUSA DBUSH are all 0 this is used for blanking the leading digit 0 on the LCD panel The LCP instruction transfers data about the RAM Rx and accumulator AC directly from DBUSA to DBUSH without passing through the data decoder The LCD instruction transfers the table ROM data T HL directly from DBUSA to DBUSH without passing through the data decoder Table 2 2 The mapping table of LCP and LCD instructions 79 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual _ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH There 8 data decoder outputs from DBUSA to DBUSH and 32 LO to L4 decode
23. 2 is accepted and the instruction at address10H is executed automatically It is necessary to apply level L before the signal rises and level H after the signal rises to the INT pin for at least 1 machine cycle 2 port IOC IOD interrupt request An interrupt request signal HRFO is delivered when the input signal changes at I O port IOC IOD specified by the SCA instruction In this case if the interrupt enabled by flag 0 IEFO is set to 1 interrupt O is accepted and the instruction at address 14H is executed automatically 3 Key matrix Scanning interrupt request An interrupt request signal HRF5 is delivered when the input signal is generated in the scanning interval If the interrupt enable flag 5 IEF5 is set to 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 3 1 1 2 Internal interrupt factor The internal interrupt factor involves the use of timer 1 TMR1 timer 2 TMR2 RFC counter and the pre divider 1 Timer1 2 TMR1 2 interrupt request An interrupt request signal HRF 1 4 is delivered when timer1 2 1 2 underflows In this case if the interrupt enable flag 1 4 IEF1 4 is set interrupt 1 4 is accepted and the instruction at address 18H 20H is executed automatically 2 Pre divider interrupt request An interrupt request signal HRF3 is delivered when the pre divider overflows In this case if the interrupt enable flag3 IEF3 is set int
24. EOR AC EOR 0010 1100 1000 0000 lt HL EOR AC EOR HL 0010 1100 1100 0000 AC lt HL EOR AC HL lt HL 1 EOR Rx 0010 1101 XXXX AC Rx Rx EOR AC EOR HL 0010 1101 1000 0000 AC HL lt HL EOR AC EOR HL 0010 1101 1100 0000 AC HL lt HL EOR AC HL lt HL 1 OR 0010 1110 XXXX AC Rx ORAC OR 0010 1110 1000 0000 AC lt HL OR AC ORA 0010 1110 1100 0000 AC lt HL OR AC HL lt HL 1 OR Rx 0010 1111 OXXX XXXX AC Rx lt Rx OR AC OR 0010 1111 1000 0000 AC HL lt HL ORAC OR HL 0010 1111 1100 0000 AC HL lt HL OR AC HL lt HL 1 ADCI RyD 0011 0000 DODD YYYY lt Ry D CF ADCI Ry D 10011 0001 DDDD YYYY AC Ry lt Ry D SBCI RyD 00110010 DDDD YYYY lt Ry DB CF SBCI Ry D 0011 0011 DDDD YYYY lt Ry DB CF ADDI RyD 0011 0100 DDDD YYYY lt D ADDI RyD 10011 0101 DDD YYYY AC Ry lt Ry D SUBI RyD 00110110 DDD YYYY Ry DB 1 SUBI Ry D 0011 0111 DDOD YYYY AC Ry lt Ry DB 1 ADNI RyD 0011 1000 DDDD YYYY Ry D ADNI RyD 10011 1001 DDDD YYYY AC Ry lt Ry D ANDI RyD 0011 1010 DODD YYYY lt Ry AND D ANDI RyD 0011 1011 DDDD YYYY AC Ry lt Ry AND D EORI RyD 0011 1100 DDDD YYYY Ry EOR D EORI Ry D 0011 1101 DDDD YYYY AC Ry lt Ry EOR D ORI Ry D 0011 1110 DDDD YYYY AC Ry ORD ORI Ry D 0011 1111 DDDD YYYY AC Ry lt Ry ORD INC Rx 0100 0000
25. LCD segments 32112 Maximum Number of System Driving LCD Segments Remarks 1 2 bias 1 4 duty 128 Connect VL3 to VL2 1 2 bias 1 8 dut 256 re VL3 to VL2 1 3 bias 1 4 duty 1 3 bias 1 8 duty e When choosing the LCD frame frequency it is recommended to chose a frequency higher than 24Hz If the frame frequency is lower than 24Hz the pattern on the LCD panel will start to flash 4 2 DC OUTPUT TM87P08 permits LCD driver output pins COM5 DC9 and DC30 to be defined as CMOS type DC output or P open drain DC output ports by mask option In these cases itis possible to use some LCD driver output pins as DC output and the rest of the LCD driver output pins as LCD drivers Refer to 4 3 4 The configurations of CMOS output type and P open drain type are shown below When the LCD driver output pins SEG are defined as DC output ports the output data on those ports will not be affected when the program enters stop mode or LCD turn off mode Figure 5 1 CMOS Output Type Figure 5 2 P Open Drain Output Type Only unused COM and SEG pads can be defined as DC output pins The COM pad sequence for LCD drivers cannot be interrupted when the COM pads are defined as DC output ports For example when the LCD lighting system is specified as 1 4 duty the COM pad used for LCD driver must COM1 Each of COM6 8 DC9 pad can be defined as DC output ports 77 tenx technology inc Rev
26. OPERATION INSTRUCTIONS INC Rx function description INC HL function description INC HL Function Description DEC Rx function description DEC HL function description Rx AC lt Rx 1 Add 1 to the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected R HL AC lt R HL 1 Add 1 to the content of data memory specified by HL the result is loaded to data memory specified by HL and AC Carry flag CF will be affected HL AC R HL 1 HL 1 Adds 1 to the content of HL the result is loaded to the data memory HL and AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected OHL indicates an index address of data memory Rx AC 1 Substrate 1 from the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected AC R HL 1 Substrate 1 from the content of data memory specified by the result is loaded to data memory specified by HL and AC Carry flag CF will be affected 93 tenx technology inc Rev 1 0 2004 2 2 OHL Function Description ADC Rx function description ADC HL function description ADC HL Function Description ADC Rx function description ADC HL function description ADC HL Function
27. PC loads the specified address in the operand of instruction PC current page PC11 specified address in operand Return instruction RTS PC content of stack specified by the stack pointer Stack pointer stack pointer 1 20 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Table 2 1 uo INT pin input port C amp D timer 1 interrupt pre divider interrupt timer 2 interrupt Key Scanning interrupt RFC counter interrupt Jump instruction P11 P10 P9 P8 P7 Pe P5 P4 P3 P2 P1 PO Subrouinecall P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO P10 to PO Low order 11 bits of instruction operand When executing the subroutine call instruction or interrupt service routine the contents of the program counter PC are automatically saved to the stack register STACK KE 2 4 PROGRAM TABLE MEMORY ROM The built in mask ROM is organized with 4096 x 16 bits The partition formula for PROM and TROM is shown below Note The data width of table ROM is 8 bit I 16 bits 000h FFFh 21 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The partition of memory space is defined by mask option the table is shown below 2 4 1 INSTRUCTION ROM PROM There are some special locations that serve as the interrupt service routines such as reset address 000H interrupt O address 014H interrupt 1 address 018H interrupt 2
28. Rev 1 0 2004 2 2 TM87P08 User s Manual disable the low level hold device executing SPC Oh to disable the pull low device and enable the low level hold device When the low level hold device is enabled by mask option the initial reset will enable the pull low device and disable the low level hold device When the IOC pin has been defined as the output mode both the pull low and low level hold devices will be disabled Low level hold function option Mask Option name Selected item C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO USE 3 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing high low chattering of the switch signal applied on IOC1 to IOCA pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOC port are defined as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry 2 IEFO Interrupt prep HREO t SPC 4 Edge s Q reques SPC 8 detect R 10C1 10C2 edge dectect amp 5 J SCF1 HALT released chattering Q request 10C4 mR chattering PHO prevention PHB PLC 1 PH6 clcok SCC S Interrupt accept intruction R
29. SPB instruction to define the I O pins as output the OPB instruction must be executed to output the data to the output latches This will prevent the chattering signal on the I O pin when the I O mode changed IOB port had built in pull down resistor and executing SPB instruction to enable disable this device 3 5 3 IOC PORT IOC1 IOC4 pins are MUXed with SEG32 KI1 SEG33 KI2 SEG34 KI3 and SEG35 KI4 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG32 IOCA KI1 2 IOC1 SEG33 IOC2 KI2 2 IOC2 SEG34 IOC3 KI3 2 1OC3 SEG35 IOCA KIA 2 IOC4 After the reset cycle the IOC port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPC instruction Executed OPC instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IPC instructions may store the signals applied to the IOC pins in the specified data memory When the IOC pins are defined as the output executing IPC instruction will save the data stored in the output latches in the specified data memory Before executing SPC instruction to define the IOC pins as output the OPC instruction must be executed to output the data to those output latches This will prevent the chattering signal when the IOC pins change to output mode 61 tenx technol
30. ScCF7 EF 3 SHE 5 36 IEFA des SIE 10h Timer 2 underflow N 8 6 s HEF 4 SHE 7 IEF5 SIE 20h Scanning HRF 5 r E SCF7 overflow IEFG Initial reset Interrupt accept Halt release request SCF2 Interrupt 1 Interrupt 2 Interrupt 3 Interrupt 4 Interrupt 5 SIE 40h FRC counter Interrupt 6 overflow HRF6 r 6 E SCF9 HEF 6 SHE 4 e tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 14 1 STATUS REGISTER 1 STS1 Status register 1 STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the result of the carry or borrow during the arithmetic operation 2 Zero flag Z Indicates the accumulator AC status When the content of the accumulator is 0 the Zero flag is set to 1 If the content of the accumulator is not 0 the zero flag is reset to 0 3 The MAF instruction can be used to transfer data in status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction can be used to transfer data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 Bit 1 BitO Carry flag AC Zero flag Z Read only Read only Read only 2 14 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 3 SCF1 SCF2 SCF3 and the backup flag The MSB instruction can be
31. X X7 0 to specify the key matrix scanning output state for each SEGn pin in the scanning interval Xs 0 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after the key is depressed on the key matrix and then SCF7 will be set to 1 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle regardless of key depression and then SCF7 will be set to 1 X7X5X4 000 in this setting each scanning cycle only checks one specified column K1 K16 on the key matrix The specified column is defined by the setting of X3 Xo 7 Xo 0000 activates the K1 column X3 Xo 0001 activates the K2 column Xo 1110 activates the K15 column Xo 1111 activates the K16 column 88 tenx technology inc Rev 1 0 2004 2 2 SPK Rx Function Description TM87P08 User s Manual X7X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle Xs Xo are not a factor X7X5X4 010 in this setting the key matrix scanning function will be disabled Xo are not a factor X7X5X4 10X in this setting each scanning cycle checks 8 specified columns on the key matrix The specified column is defined by the setting of 0 activates the K1 K8 columns simultaneously X3 1 activates the K9 K16 columns simultaneously X2 Xo are not a factor X7X5X4 110 in th
32. X7 X6 X5 4 X3 X2 X1 XO SPK HL Function Sets the Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s sets the content of table ROM HL to specify the key matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit pattern of the table ROM corresponding to SPKX is shown below Instruction Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SPK HL T HL 7 T HL 6 T HL 5 T HL 4 T HL 3 T HL 2 T HL 1 T HL O SPKX X XT X6 X5 X4 X3 X2 X1 XO ALM X function Sets buzzer output frequency description The waveform specified by X X8 X0 is delivered to the BZ and BZB pins The output frequency could be any combination in the following table The bit pattern of X for higher frequency clock source clock source higher frequency FREQ 1 FREQ 1 03 4 2 0 1 clock source lower frequency 015 1 2 Notes 1 FREQ is the output of frequency generator 2 When the buzzer output does not need the envelope waveform X5 should be set to 0 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 The frequency inside the bases on the 0 is 32768Hz SRF X function The operation control for RFC description The meaning of each control bit X5 X0 is shown below the 16 bit counter X3 must mii seti 1 whan this Bitis set to
33. XXX lt Rx MRW HL Rx 0110 1110 IXXX XXX AC QHL lt Rx HL lt HL 1 MWR RXxGHL 0110 1111 XXXX AC Rx HL MWR Rx HL 0110 1111 IXXX XXXX AC Rx lt HL HL lt HL 1 MRW Ry Rx 0111 OYYY YXXX AC Ry lt Rx MWR Rx Ry 0111 1YYY YXXX XXXX JBO X 1000 XXXX XXXX PC X if ACO 1 JB1 X 1000 1XXX XXXX PC X 1 1 2 X 1001 XXXX PC X if AC2 1 JB3 X 1001 1XXX XXXX PC X if AC3 1 JNZ X 1010 OXXX XXXX XXXX PC X if AC 0 125 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual JNC 1010 1XXX XXXX XXXX PC lt X if CF 0 JZ 1011 XXXX XXXX X if AC 0 JC 1011 1XXX XXXX XXXX PC X if CF 1 CALL 1100 PXXX XXXX XXXX STACK PC PC 1 JMP 1101 PXXX XXXX PC X TMS 1110 0000 OXXX XXXX AC3 2 11 AC3 2 10 AC3 2 01 AC3 2 00 AC1 0 PB3 0 Ctm FREQ Ctm PH15 Ctm PH3 Ctm PH9 Set Timer1 Value TMS HL 1110 0001 0000 0000 TD7 6 11 TD7 6 10 TD7 6 01 TD7 6 00 TD5 0 Ctm FREQ Ctm PH15 Ctm PH3 Ctm PH9 Set Timer1 Value TMSX TM2 1110 001X XXXX XXXX 1110 0100 OXXX XXXX X8 7 6 111 X8 7 6 110 X8 7 6 101 X8 7 6 100 X8 7 6 011 X8 7 6 010 X8 7 6 001 X8 7 6 000 X5 0 Time
34. clock to low speed clock and then stops the CFOSC 107 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual MSB Rx function AC Rx lt SCF3 SCF1 SCF2 BCF description The SCF1 SCF2 and BCF flag contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition Backup flag flag 3 flag 2 flag 1 SCF 3 SCF2 SCF1 Halt release Halt release caused Halt release The Backup caused by the by SCF4 5 6 7 8 9 caused by the mode status in IOD port IOC port TM87P08 MSC Rx function AC lt SCF4 7 description The SCF4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 SCF7 stage of the predivider SCF5 SCF4 predivider overflow TM1 underflow caused by INT pin MCX Rx function AC Rx lt SCF8 SCF6 SCF9 description The SCF8 SCF6 SCF9 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 SCF9 SCF6 SCF8 Halt release Halt release Halt release caused caused by RFC caused by TM2 by the signal change counter overflow underflow to L applied on KI1 4 in scanning interval MSD Rx func
35. combination of one signal of FREQ PH3 4096Hz PH4 2048Hz PH5 1024Hz and multiple signals of PH10 32Hz PH11 16Hz PH12 8Hz 13 4 2 PH14 2Hz PH15 1Hz The ALM instruction is used to specify the combination The higher frequency clock is the carrier of modulation output and the lower frequency clock is the envelope of the modulation output 55 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Note 1 The high frequency clock source should only be one of PH3 PH4 PH5 or FREQ and the lower frequency may be any all of the combinations from PH10 PH15 2 The frequencies in corresponding to the input clock of the pre divider PHO is 32768Hz 3 The BZ and BZB pins will output DCO after the initial reset Example Buzzer output generates a waveform with 1KHz carrier and PH15 PH14 envelope LDS 20h 0Ah ALM 70h Output the waveform In this example the BZ and BZB pins will generate the waveform as shown in the following figure PH15 1HZ e a 5 1 2 BZ BZ Piste TEE er arsi e ag 3 4 2 THE CARRIER FOR REMOTE CONTROL If buzzer output combines with the timer and frequency generator the output of the BZ pin may deliver the waveform for the IR remote controller For remote control usage the setting value of the frequency generator must be greater than or equal to 3 and the ALM instruc
36. data memory it is necessary to initiate the content of data memory because the initial value is unknown The working registers are part of the data memory RAM and the relationship between them can be shown as follows The absolute address of working register Rx Ry 70H Note Ry Address of working register the range of addresses specified by Rx is from 70H to 7FH Rx Address of data memory the range of addresses specified by Ry is from OH to FH Ry use for LCD instruction only OH 7H Address of working registers Absolute address of data memory specified by Ry Rx Lz represents the address of the latch of LCD PLA the address range specified by Lz is from OOH to 1FH 5 1 INPUT OUTPUT INSTRUCTIONS LCT Lz Ry function description LCB Lz Ry function description LCP 12 Ry function description LCD Lz HL function LCD latch Lz lt data decoder lt Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder LCD latch Lz lt data decoder lt Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is 0 the outputs of the data decoder are all 0 LCD latch Lz lt Ry AC The working register contents specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz LCD latch Lz T HL 84 tenx technology inc R
37. description SBC QHL function description SBC HL Function Description SBC Rx function description SBC HL function description SBC HL Function Description TM87P08 User s Manual Binary adds the contents of HL AC and CF the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory AC lt Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected AC lt R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC Carry flag CF will be affected AC lt HL AC B CF HL HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC Rx lt Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC and data memory Rx Carry flag CF will be affected AC R HL lt R HL AC B CF The contents of AC and CF are binary subtracted f
38. interrupt service is concluded SIE 55h Enable the interrupt request except the predivider and TMR1 Interrupt caused by the TM2 underflow occurs and interrupt service is concluded SIE 45h Enable the interrupt request except the predivider TMR1 and TMR2 Interrupt caused by the RFC counter overflow occurs and interrupt service is concluded SIE 05h Enable the interrupt request except the predivider TMR1 2 and the RFC counter Interrupt caused by the IOC port and interrupt service is concluded SIE 04h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter and IOC IOD port Interrupt caused by the INT pin and interrupt service is concluded interrupt requests have been processed 47 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction at the interrupt service address is executed automatically Refer to Table 3 1 In this case the CPU performs the following services automatically 1 As for the return address of the interrupt service routine the addresses of the program counter PC installed before interrupt servicing began are saved in the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the interrupt accepted is reset and
39. lt 4 DAA 0101 0100 0000 0000 AC lt BCD AC CF DAA Rx 0101 0101 OXXX XXXX AC Rx BCD AC CF DAA HL_ 0101 0101 1000 0000 AC HL lt BCD AC CF DAA HL_ 0101 0101 1100 0000 AC HL lt BCD AC CF HL 124 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual lt HL 1 DAS 0101 0110 0000 0000 JAC lt BCD AC CF DAS Rx 0101 0111 XXXX AC Rx BCD AC CF DAS HL 0101 0111 1000 0000 AC HL lt BCD AC CF DAS HL 0101 0111 1100 0000 AC HL lt BCD AC CF HL lt HL 1 LDS RxD 0101 IDDD DXXX XXXX AC Rx D LDH 0110 0000 OXXX XXXX AC Rx H T HL LDH Rx HL 0110 0001 OXXX XXXX JAC Rx H TQHL HL HL 1 LDL 0110 0010 XXXX AC Rx L T HL LDL Rx QHL 0110 0011 XXXX AC Rx lt L TQHL HL HL 1 MRF1 0110 0100 OXXX XXXX AC Rx RFC3 0 MRF2 0110 0101 XXXX RFC7 4 MRF3 0110 0110 XXXX AC Rx RFC11 8 MRF4 Rx 0110 0111 XXXX AC Rx RFC15 12 STA Rx 0110 1000 OXXX XXXX Rx AC STA QHL 0110 1000 1000 0000 HL AC STA HL 0110 1000 1100 0000 HL AC HL lt HL 1 LDA 0110 1100 OXXX XXXX AC lt Rx LDA QHL 0110 1100 1000 0000 AC lt HL LDA HL 0110 1100 1100 0000 AC HL HL lt HL 1 MRA Rx 0110 1101 OXXX XXXX CF Rx3 MRW HL Rx 0110 1110 OXXX
40. oet a eate ur 57 0 84422125 TT 67 3 7 Resistor to Frequency Converter 68 3 7 Key Martix Scanning ck pecs sia et area eases e Da sae le 72 CHAPTER 4 LCD Driver Output 76 4 1 LCD Lighting System in 8706 76 4 2 DO h uh uuu auqa TT 4 3 Segment PLA Circuit for LCD Display a 82 CHAPTER 5 Detail Explanation of TM87P08 Instructions 84 5 1 Input Output 0 6 84 5 2 Accumulator Manipulation Instructions and Memory Manipulation MUS UPRICTIONNS MEOS 91 5 3 Operation Instr ctloris eter rere 93 5 4 Load Store Instructions 103 5 9 CPU Control Instructions La iis 106 5 6 Index Address Instructioris uu u ota iioi pta pi pt ede od ade pe rece onu edu depu 110 5 7 Decimal Arithmetic Instructions 110 5 9 5 3 55 05 cce
41. output port by executing OPAS instruction IOA port must be defined as the output mode before executing OPAS instruction 1 BITO and BIT1 of the port deliver RAM data 2 BIT2 of the port delivers the constant value of the OPAS 3 BIT3 of the port delivers pulses Shown below is a sample program using the OPAS instruction 1 105 OAH 0 2 OPA OAH SPA OFH LDS 1 5 3 OPAS 1 1 Bit 0 output shift gate open 58 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual SRO 1 5 45 bit 1 to bit O OPAS 1 1 Bit 1 output SRO 1 Shifts bit2 to bit 0 OPAS 1 1 Bit 2 output SRO 1 Shifts bit 3 to bit 0 OPAS 1 1 Bit output 10 1 1 Lastdata 11 OPAS1 0 Shift gate closes The timing chart below illustrates the above program 1 2 3 4 5 6 7 8 9 10 11 AC 0 5 AC 2 AC 1 1 for Rx 5 Bit1 for Rx 5 Bit2 for Rx 5 for Rx 5 M M IOA2 M M M IOA3 M IOA4 LO M M lt t BCLK 2 If IOA1 pin is used as the CX pin for RFC function and the other pins IOA2 IOA3 are used for normal IO pins IOA1 pin must always be defined as the output mode to avoid the influence from the CX when the input chattering prevention function is active On the other hand the RFC counter can receive the signal changes on IOA1 when the RFC counter is enabled 59 tenx technology inc Rev 1 0 2004 2
42. the interrupt enable flags are all reset When the interrupt occurs the TM87P08 will follow the procedure below Instruction 1 In this instruction interrupt is accepted NOP TM87P08 stores the program counter data into the STACK At this time no instruction will be executed as with NOP instruction Instruction A The program jumps to the interrupt service routine Instruction B Instruction C RTS Finishes the interrupt service routine Instruction 1 re executes the instruction which was interrupted Instruction 2 Note If instruction 1 is halt instruction the CPU will return to halt after interrupt When an interrupt is accepted all interrupt enable flags are reset to 0 and the corresponding HRF flag will be cleared the interrupt enable flags IEF must be set again in the interrupt service routine as required 3 2 RESET FUNCTION TM87P08 contains four reset sources power on reset RESET pin reset IOC port reset and watchdog timer reset When reset signal is accepted TM87P08 will generate a time period for internal reset cycle and there are two types of internal reset cycle time could be selected by mask option the one is PH15 2 and the other is PH12 2 Reset signal h UU t Hold 16384 or 2048 clocks for pla Normal operation gt internal reset cycle 48 tenx technology
43. these networks are disabled 3 Execute SRF 8 SRF 18h or SRF 28h instructions to enable the RC oscillation network and 16 bit counter The RC oscillation network will not operate if these instructions have not been executed and the RR RT RH pins output 0 state at this time To get a better oscillation clock from the CX pin activate the output pin for each RC network before the counter is enabled The RFC function provides 3 modes for the operation of the 16 bit counter Each mode will be described in the following sections 3 7 2 Enable Disable the Counter by Software The clock input of the 16 bit counter comes from the CX pin and is enabled disabled by the S W When SRF 8h instruction is executed the counter will be enabled and will start to count the signals on the CX pin The counter will be disabled when SRF 0 instruction is executed Executing MRF 1 4 instructions may load the result of the counter into the specified data memory and AC Each time the 16 bit counter is enabled the content of the counter will be cleared automatically Example If you intend to count the clock input from the CX pin for a specified time period you can enable the counter by executing SRF 8 instruction and setting timer1 to control the time period Check the overflow flag RFOVF of this counter when the time period elapses If the overflow flag is not set to 1 read the content of the counter if the overflow flag has been set to 1 you must redu
44. used to transfer data of status register 2 STS2 to the accumulator AC and the data memory RAM but it is impossible to transfer data of the data memory RAM to status register 2 STS2 The following table shows the bit pattern of each flag in status register 2 STS2 Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 3 Start condition flag 2 Start condition flag 1 Backup flag SCF3 SCF2 SCF1 BCF Halt release caused Halt release caused Halt release caused by The backup mode by the IOD port by SCF4 5 6 7 9 the IOC port status Read only Read only Read only Read only Start condition flag 1 SCF1 When the SCA instruction specified signal change occurs at port IOC to release the halt mode SCF1 will be set Executing the SCA instruction will cause SCF 1 to be reset to 0 Start condition flag 2 SCF2 When a factor other than port IOC causes the halt mode to be released SCF2 will be set to1 In this case if one or more start condition flags in SCF4 5 6 7 9 is set to 1 SCF2 will also be set to 1 simultaneously When all of the flags in SCF4 5 6 7 9 are clear start condition flag 2 SCF 2 is reset to 0 Note If start condition flag is set to 1 the program will not be able to enter halt mode Start condition flag 3 SCF3 35 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual When the SCA instruction specified signal change occurs at port IOD to release the halt mode SCF3 will be set Executi
45. will output L level In this mode TM87P08 does not dissipate any power in the stop mode Because the stop mode will set the BCF flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the pins defined as input mode of IOC port must be in the L state and no stop release signal SRFn should be delivered The CPU will then enter the stop mode The following conditions cause the stop mode to be released One of the signals on the input mode pin of IOC port is H state and holds long enough to cause the CPU to be released from halt mode signal change in the INT pin The stop release condition specified by the SRE instruction is met INT pin is exclusive 43 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual When the TM87PO68 is released from the stop mode the TM87P08 enters the halt mode immediately and will process the halt release procedure If the signal on the IOC port does not hold long enough to set the SCF1 once the signal on the IOC port returns to L the TM87P08 will enter the stop mode immediately The backup flag will be set to 1 automatically after the program enters the stop mode The following diagram shows the stop release procedure STOP HALT MODE STOP Yes released release Figure 3 16 The stop release state machine Before th
46. 0 overflow flag of 16 bit Watchdog timer System clock counter of RFC awe ee Enable flag WDF selection flag CSF Read Read Readony Read only Read only 2 14 6 START CONDITION FLAG 11 SCF11 Start condition flag 11 SCF 11 will be set to 1 in STOP mode when the following conditions are met Ahigh level signal comes from the OR ed output of the pins defined as input mode in IOC port which causes the stop release flag of IOC port CSR to output and stop release enable flag 4 SRF4 is set beforehand A high level signal comes from the OR ed output of the pins defined as input mode in IOD port which causes the stop release flag of IOD port DSR to output The stop release enable flag3 SRF 3 must be set beforehand The signal change from the INT pin causes the halt release flag 2 HRF2 to output and the stop release enable flag 5 SRF5 is set beforehand The following figure shows the organization of start condition flag 11 SCF 11 11 Stop release request SRF3 The stop release flags SKI CSR DSR HRF2 were specified by the stop release enable flags SRFx These flags should be clear before the chip enters stop mode All of the pins in the IOA and IOC ports have to be set in input mode and keep in 0 state before the chip enters the STOP mode otherwise the program can not enter STOP mode Instruction SRE is used to set or reset the stop release enabl
47. 1 0 2004 2 2 TM87P08 User s Manual 4 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY 4 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION The explanation below explains how the LCD driver section operates when the instructions are executed HL gt Table ROM AC amp RAM data memory Data decoder Data bus Strobe data Decoder of strobe LO to related 14 NES instruction Multiplexer laten amp LCD circuit driver circuit LCD output Segment PLA Figure 5 3 Principal Drawing of LCD Driver Section The LCD driver section consists of the following units Data decoder to decode data supplied from RAM or table ROM Latch circuit to store LCD lighting information LO to L4 decoder to decode the Lz specified data in LCD related instructions which specifies the strobe of the latch circuit Multiplexer to select 1 4 duty and 1 8 duty LCD driver circuitry Segment PLA circuit connected between data decoder LO to L4 decoder and latch circuit The data decoder is used for decoding the contents of the working registers as specified in LCD related instructions They are decoded as 7 segment patterns on the LCD panel The decoding table is shown below 78 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Content Output of data decoder DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH id
48. 11 0101 110X XXXX X4 Set C4 1 Pull Low 1 low 0 LLH Low Level Hold X3 0 Set C4 1 I O 1 Output 0 Input SPD 1111 0101 111X XXXX X4 Set D4 1 Pull Low 1 Pull low X3 0 Set D4 1 I O 1 Output 0 Input SF 1111 0110 X00X 00XX X7 Reload 1 Set X4 WDT Enable X1 BCF Set XO CF Set RF X 1111 0111 X00X OOXX X7 Reload 1 Reset X4 WDT Reset X1 BCF Reset XO CF Reset ALM X 1111 110X XXXX XXXX X8 7 6 111 FREQ X8 7 6 100 DC1 X8 7 6 011 PH3 X8 7 6 010 PH4 X8 7 6 001 PH5 X8 7 6 000 DCO 128 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual X5 0 lt PH15 10 SF2 X 1111 1110 0000 XXXX X3 Enable INT powerful Pull low X2 Close all Segments X1 Dis ENX Set XO Reload 2 Set RF2 X 1111 1110 1000 XXXX X3 Disable INT powerful Pull low X2 Release Segments X1 Dis ENX Reset XO Reload 2 Reset HALT 1111 1111 0000 0000 Halt Operation STOP 1111 1111 1000 0000 Stop Operation Symbol Description Symbol Description Symbol Description Content of Register D Immediate Data AC Accumulator D B Complement of Immediate Data AC n Content of Accumulator bit n PC Program Counter AC B Complement of content of Accumulator CF Carry Flag X Address of program or control data ZERO _ Zero Flag Rx Address X of data RAM WDF _ Watch Dog Timer Enable Flag
49. 1Fh Refer to Chapter 5 for detailed description of these instructions PSTBO PSTB3Fh DBUSA DBUSH driver Figure 4 3 Sample Organization of Segment PLA Option 82 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 4 3 4 THE CONFIGURATION FORMAT FOR FIXED PLA MAPPING The TM87P08 is fixed PLA structure PLA table is shown below 1 8 Dut 1 4 Duty SEGx iz COML coe COM 00H DBUSD DBUSH DBUSD DBUSH ENTRE seua HE DER DBUSD SEGG DBUSH EEN oe oss DBUSD DBUSH DBUSA DBUSB DBUSC DBUSD COMB coms COW DBUSA DBUSB DBUSC DBUSD EI 14H DBUSE DBUSF DBUSG DBUSH DBUSE DBUSF DBUSG DBUSH DBUSH Ex 08050 iu DBUSH SEB 0818 0858 Fouse 08180 iy SEGIS DBUSH qo ORUSA Duse 050 ig SEGIB DBUSH qo 2853 0658 neue 0850 Ez DBUSH SEGA DBUSD DBUSH 21 08050 DBUSH ISEGS 08050 c SEG2S DBUSH T DBUSD DBUSH Eom DBUSD ic DBUSH sss 08050 DBUSH 1 4 Duty 1 8 Duty DC5 OD5 DC6 OD6 DC7 OD7 DBUSA DBUSB DBUSC DC8 OD6 DC9 OD9 DC3y OD80 DBUSD DBUSE DBUSH DC9 OD9 DC30 OD30 DBUSE DBUSH 83 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Chapter 5 Detail Explanation of TM87P08 Instructions Before using the
50. 2 TM87P08 User s Manual 3 5 2 IOB PORT IOB1 IOB4 pins are MUXed with SEG28 SEG29 BZB SEG30 and BZ SEG31 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 2 IOB1 SEG29 IOB2 2 IOB2 SEG30 IOB3 BZB 2 IOB3 SEG31 IOBA BZ 2 IOB4 The following figure shows the organization of IOB port Initial clear BG 581 L IOB1 Initial clear SPB2 bit1 2 Initial clear SPB 4 bit2 Initial clear SPB8 SPB T 10 Pull low 1 option V bit3 Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state After the reset cycle the IOB port is set as input and each bit of port can be defined as input or output individually by executing SPB instructions Executing OPB instructions may 60 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual output the content of specified data memory to the pins defined as output mode the other pins which are defined as the input will still be input Executed IPB instructions may store the signals applied on the IOB pins into the specified data memory When the IOB pins are defined as the output executing IPB instruction will save the data stored in the output latch into the specified data memory Before executing
51. 2 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual U register H register L register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Bit3 Bit2 Bit1 BitO IDBF11 IDBF10 IDBF9 IDBF8 IDBF7 IDBF6 IDBF5 IDBFA IDBF3 IDBF2 IDBF1 IDBFO The index address register can specify the full range addresses of the table ROM and data memory bit3 MVU index Rx addressing bito DATA RAM bit3 MVH bitO TABLE ROM index addressing This figure shows the diagram of the index address register 2 6 STACK REGISTER STACK Stack is a special design register following the first in last out rule It is used to save the contents of the program counter sequentially during subroutine call or execution of the interrupt service routine The contents of stack register are returned sequentially to the program counter PC while executing return instructions RTS The stack register is organized using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine call or interrupt are allowed If the stacks are full and either interrupt occurs or subroutine call executes the first level will be overwritten Once the subroutine call or interrupt causes the stack register STACK overflow the stack pointer will return to 0 and the content of the level 0 stack will be overwritten by the PC value The contents of the stack regi
52. 4 1 IEF4 0 and the TMR2 halt release enabler HEF4 is set to 1 program will escapes from halt mode if CPU is in halt mode and then HRF4 sets the start condition flag 6 SCF6 to 1 in the status register 4 STS4 After power on reset the default clock source of TMR2 is PH7 If watchdog reset occurred the clock source of TMR2 will still keep the previous selection The following table shows the definition of each bit in TMR2 instructions 2 0 AC2 AC1 ACO Rx3 R2 Rx1 M2 QHL O bit bit Bit4 bit3 bit2 bito 30 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The following table shows the clock source setting for TMR2 Notes 1 When the TMR2 clock is PH3 TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is PH11 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of se
53. 4 INT pin Port IOC IOD amp KI input e Internal factor 4 Pre Divider Timer1 Timer2 RFC 6 Built in Alarm Frequency or Melody generator 7 BZB BZ Mux with IOB3 8 Built in R to F Converter circuit e RR RT RH Mux with IOA1 IOA4 9 Built in KEY BOARD scanning function e K1 K16 Share with SEG1 SEG16 e Kl1 Kl4 Mux with IOC1 1OCA 10 Two 6 bit programmable timers with programmable clock source 3 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 11 Watch dog timer 12 LCD driver output 32 LCD LED driver outputs up to 128 or 256 LCD segment drivable 1 4 or 1 8 Duty for LCD LED 1 2 Bias or 1 3 Bias for LCD LED selected by option Single instruction to turn off all segments Option is used to select COM5 8 DC9 OD9 DC30 OD30 as DC outputs P open drain e 32 LCD address 13 Built in Voltage doubler halve charge pump circuit 14 Dual clock operation and X tal type slow oscillation and fast oscillation can set 3 58MHz ceramic resonator or external R by switch option 15 HALT function 16 STOP function 17 ROM code protect fuse APPLICATION B Timer Calendar Calculator 1 3 BLOCK DIAGRAM D1 4 COM1 8 DC9 DC30 SEG1 29 31 40 41 VDD1 3 LCD
54. 4 input latch state JBO ki1_release JB1 ki2_release JB2 ki3 release JB3 ki4 release ki1 release SPKX 40h Checks the key depressed on K1 column PLC 20h Clears HRF5 to avoid the false HALT release CALL wait scan again Waits for the next key matrix scanning cycle The waiting period must be longer than the key matrix scanning cycle IPC 10h Reads the KI1 input latch state JBO ki seg1 SPK 4fh Enables only the SEG16 scanning output PLC 20h Clear HRF5 to avoid the false HALT released CALL wait scan again X Waits for the time over the halt LCD clock cycle to ensure and scans again IPC 10h Reads the KI1 input latch state JBO kil seg16 wait scan again HALT PLC 20h RTS 75 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual CHAPTER 4 LCD DRIVER OUTPUT There are 41 segment pins with 9 common pins the LCD driver outputs in TM87P08 All of these output pins can also be used as DC output ports through the mask option MASK OPTION table During the initial reset cycle the LCD lighting system may be lit or extinguished by mask option All of the LCD or DC output will remain in the initial setting until instructions relative to the LCD are executed to change the output data MASK OPTION table Mask Option name Selected item LCD DISPLAY IN RESET CYCLE 1 ON LCD DISPLAY IN RESET CYCLE 2 OFF 4 1 LCD LIGHTING SYSTEM IN TM87P08 There are several LCD lighting sy
55. 6 bit counter is enabled the content of the counter will be cleared automatically SRF 18h SRF 02h Y SRF control Counter active Timer 2 3Fh 20n h X 18h X Oh 3Fh Content of the counter 0 X 1 YX 2 X 3 N 1 N NX N 1 e 400 e 111 01111 0 Halt release request counter starts Counting stops caused to count by the Timer 2 underflow This figure shows the timing of the RFC counter controlled by timer 2 Example In this example use the RT network to generate the clock source SRF 1Ah Build up the RT network and enable the counter controlled by TM2 SHE 10h enable the halt release caused by TM2 TM2X 20h set the PH9 as the clock source of TM2 and the down 70 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual count value is 20h HALT PLC 10h Clear the halt release request flag of TM2 MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h 3 7 4 Enable Disable the Counter by CX Signal This is another use for the 16 bit counter In previous modes CX is the clock source of the counter and the program must specify a time period by timer or subroutine to control the counter In this mode however the counter has a different operation method CX pin becomes the controlled signal to enable disable the counter and the clock source of the counter comes from the output of the frequency generator FREQ The counter will start to count th
56. 8 K8 2587 30 819 70 SEG41 102 70 SEG9 K9 2587 30 963 90 TEST 102 70 6 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 1 6 PIN DESCRIPTION VDD1 2 3 LCD supply voltage and positive supply voltage Connect 3 0V battery positive pin to VDD2 Above 4 0V is need to VDD2 for Serial Program Read Input pin from LSI reset request signal with internal pull down resistor Instruction Reset Time can select PH15 2 or PH12 2 by option RESET DON Reset Type can select Level or Pulse by option Control Signal for Serial Program Read Mode Input pin for external INT request signal Falling edge or rising edge triggered by INT option Internal pull down or pull up resistor is selected by option O Serial Data for Serial Program Read Mode TEST Test signal input pin No Connected Switching pins for supply the LCD driving voltage to the VDD1 2 3 pins CUP1 2 Connect the CUP1 and CUP2 pins with non polarized electrolytic capacitor if 1 2 or 1 3 bias mode has been selected In no BIAS mode these pins should be open Ui 2777 7 XOUT to VDD2 CENE 7 lille CFOUT be connected to VDD Eus FROUT to GND come O Pos is moea min DOOpen Drein ana set mask option COM5 8 is muxed with DC Open Drain and set mask option Dco DC Open Drain 1 0 0 O a Output pins for driving the LCD or LED panel
57. A SRE AS 9 ER ZX tenx technology inc TM87P08 4 Bit Micro Controller with LCD Driver User s Manual tenx technology inc tenx technology inc Rev1 0 2004 2 2 TM87P08 User s Manual CONTENTS CHAPTER 1 General Description 3 4 4 General DescripllOEy qi cese perse ru Foe E FEE FEE 3 152 Features TAX TAL 3 153 5166 Diagrami siia ion ime iei irt pa e a iet 256524 a kaa a a a 2 a totem 4 144 ean eta eat et 246125 82465401 ead 246401 2462 82465401 448 82444200 22034 5 1 5 Pad E PCs 6 1 5 PITE DSOSCTPIDUORS dod GU COR catches CEN QUERER IN GRE S CoL ul eas chat 7 1 7 Characterizatl f u uu u ERE 8 Tae Typical Application Edo bei tu bre 11 CHAPTER 2 TM87P08 Internal System Architecture 12 241 odio tee lag aaa dod eui ond ed od fon tod Na fea oss 12 222 SYSIEIM COCK SM M H 14 2 3 Program Counter 35265235 sontes sontes oues 20 2 4 Program Table Memory sse 21 2 5 Index Address Register 22 2 6 Stack Register STACI uma
58. AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC Rx Rx AC B 1 Binary subtracts the content of AC from the content of Rx the result is loaded to AC and Rx The carry flag CF will be affected AC HL HL AC B 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC and the data memory HL HL indicates an index address of data memory The carry flag CF will be affected AC HL HL AC B 1 HL HL 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC 97 tenx technology inc Rev 1 0 2004 2 2 ADN HL Function Description ADN HL Function Description ADN Rx Function Description ADN HL Function Description ADN HL Function Description AND Rx Function Description AND HL Function Description TM87P08 User s Manual The result will not affect the carry flag CF AC lt HL AC Binary add
59. DAS DAS DAS HL can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 AC data before DAS data before DAS AC data after DAS CF data after DAS execution execution execution execution 0s ACx9 6 lt AC lt F AC Example 2 LDS 10h 1 Load immediate data 1 to the data memory address 10H LDS11h 2 Load immediate data 2 to the data memory address 11H and AC SF 1h Set CF to 1 which means no borrowing has occurred SUB 10h Content of data memory address 10H is binary subtracted the result loads to data memory address 10H Rio AC CF 0 DAS 10h Convert the content of the data memory address 10H to decimal format The result in the data memory address 10H is 9 and in the CF is 0 This represents the decimal number 1 26 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 12 TIMER 1 TMR1 Re load RL1 p S TMS instruction IEF1 Q Initial reset FREQ 6 bit binary down PH3 ___ counter Set S PH9 1 Reset TMR1 Interrupt SCF5 Halt release PH15 HEF1 Operand data x5 x0 TMS instruction Interrupt accept signal e a 2 instruction VN TMS instruction Initial reset This figure shows the TMR1 organization
60. DRIVER FIXED SEGMENT PLA 4 BITS DATA BUS FREQUENCY ALU DATA RAM INDEX ROM GENERATOR 256 X A BITS Es zd E 6 BITS PRESET 8LEVELS INSTRUCTION PRE DIVIDER TIMER1 amp 2 STACK DECODER 4096 X 8 BITS H CONTROL 12 BITS PROGRAM ROM CIRCUIT OSCILLATOR ees 4096 X 16 BITS LJ RESET INT TM87P08 BLOCK DIAGRAM 4 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 1 4 PAD DIAGRAM 003 SEG40 SEG41 TEST XIN XOUT FRIN FROUT CFIN CFOUT GND RESET INT VDD1 VDD2 VPP l0C4 10C3 1002 1061 SEG31 DC30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 wo e o SEG18 5 17 SEG16 SEG15 SEG14 TM87P08 Die Size 2690 x 2890 um Pad Size 90 x 90 um Substrate has to connect to GND SEG12 SEG11 wo e SEG9 SEG8 SEG SEG6 SEG5 SEGA VDD3 CUP1 CUP2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 DC9 5 1 SEG2 SEG3
61. P08 User s Manual 2 8 WORKING REGISTER WR The locations 70H to 77H of the data memory RAM are not only used as general purpose data memory but also as the working register WR The following will introduce the general usage of working registers 1 Be used to perform operations on the contents of the working register and immediate data Such as ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI EORI ORI ORI 2 Be transferred the data between the working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 3 Decode or directly transfer the contents of the working register and output to the LCD PLA circuit Such as LCT LCB LCP 2 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and Logic Unit data transfer between the accumulator and other registers or data memory can be performed 2 10 ALU Arithmetic and Logic Unit This is a circuitry that performs arithmetic and logic operation The ALU provides the following functions Binary addition subtraction INC DEC ADC SBC ADD SUB ADN ADCI SBUI ADNI Logic operation AND EOR OR ANDI EORI ORI Shift SRO SR1 SLO SL1 Decision JBO JB1 JB2 JB3 JC JNC JZ and JNZ BCD operation DAA DAS 2 11 HEXADECIMAL CONVERT TO DECIMAL HCD Decimal format
62. Rx Function Description AND HL Function Description AND HL Function Description EOR Rx Function Description EOR HL Function Description EOR HL Function Description TM87P08 User s Manual HL indicates an index address of data memory AC 8 AC HL 1 Binary ANDs the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC Rx lt Rx amp AC Binary ANDs the contents of Rx and AC the result is loaded to AC and the data memory Rx AC HL HL amp AC Binary ANDs the contents of HL and AC the result is loaded to AC and the data memory QHL HL indicates an index address of data memory AC HL HL amp AC HL HL 1 Binary ANDs the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC lt Rx AC Exclusive Ors the contents of Rx and AC the result is loaded to AC AC lt HL Exclusive Ors the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory AC lt Q HL AC HL 1 Exclusive Ors the contents of HL and AC
63. TM87PO08 User s Manual After executing SLOW instruction the system clock generator will hold 2 XT clocks and then switches XT clock to BCLK Fast clock stops operating clock XT clock SLOW BCLK This figure shows the System Clock Switches from Fast to Slow 2 2 3 2 SINGLE CLOCK MASK OPTION table For Fast clock oscillator only Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY For slow clock oscillator only Mask Option name Selected item CLOCK SOURCE 2 SLOW ONLY The operation of the single clock option is shown in the following figure Either XT or CF clock may be selected by mask option in this mode The FAST and SLOW instructions will perform as the NOP instruction in this option The backup flag BCF will be set to 1 automatically before the program enters the stop mode This could ensure the Crystal oscillator would start up in a better condition Halt Normal mode Halt Halt mode OSC active released OSC active Stop Reset Reset release Stop Release Stop mode OSC stop Reset mode OSC active Reset pin reset Watchdog timer reset Key reset 18 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual This figure shows the State Diagram of Sin
64. The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOD1 is changed from L level to H level or from H level to L level and the remaining pins ex IOD2 to IOD4 are held level When the signal changes at the input pins of IOD port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF3 At that time the chattering prevention clock will stop due to the delivery of SCF3 The SCF3 will be reset to O by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF3 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOD interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOD1 to IODA the input data at the port IOD must be read into the RAM immediately after the halt mode is released 66 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 6 EXTERNAL INT PIN The INT pin can be selected as pull up or pull down or open type by mask option The signal change either rising edge or falling edge by mask option sets the interrupt flag delivering the halt release request flag 2 HRF2 In this case if th
65. UP2 MPD 12 0V 5 0V TM87P08 RESET 4 PROGRAMMING CLOCK INF 4 PROGRAMMING 1 0 120 tenx technology inc Rev 1 0 2004 2 2 Appendix TM87P08 Instruction Table TM87P08 User s Manual Instruction Machine Code Function Flag Remark NOP 0000 0000 0000 0000 No Operation LCT LzRy 0000 001Z ZZZZ YYYY lt TSEG lt Ry Ry 70H 7FH LCB LzRy 0000 010Z ZZZZ YYYY Lz lt 7SEG lt Ry Ry 70H 7FH Blank Zero LCP jLz Ry 0000 0117 ZZZZ YYYY Lz lt Ry amp AC Ry 70H 7FH LCD Lz HL 0000 100Z ZZZZ 0000 Lz T HL LCT Lz HL 0000 100Z 7777 0001 Lz SEG lt HL LCB Lz QHL 0000 1007 ZZZZ 001012 lt TSEG lt HL Blank Zero LCP Lz HL 00001007 ZZZZ 0011 Lz HL amp AC LCDX D 0000 100D 0000 0100 Multi Lz T HL D 0 1 D 00 Multi Lz 00H OFH D 01 Multi Lz 10H 1FH LCTX D 0000 100D D000 O101 Multi Lz lt TSEG QHL D 0 1 LCBX D 0000 100D D000 0110 Multi Lz lt 7ZSEG QHL D 0 1 Blank Zero LCPX D 0000 100D D000 0111 Multi Lz lt HL amp AC D 0 1 OPA 0000 1010 XXXX Port A Rx OPAS RxD 0000 1011 DXXX XXXX A1 2 3 4 lt Rx0 Rx1 D Pulse OPB Rx 0000 1100 OXXX XXXX Port B lt Rx OPC Rx 0000 1101 OXXX XXXX Port C lt Rx OPD Rx 0000 1110 OXXX XXXX Port D lt Rx FRQ D Rx 0001 OODD XXXX FREQ lt Rx amp AC D 00 1 4 D
66. YSTEM CLOCK XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below Stop Halt Fast instruction Slow instruction XT Clock CF Clock BCLK T1 T2 T3 T4 Sclk Clock switch circuit System clock generator Clock switch circuit Single clock option Dual clock option The system clock generator provided the necessary clocks for execution of instruction The pre divider generated several clocks with different frequencies for the usage of LCD driver frequency generator etc The following table shows the clock sources of system clock generator and pre divider in different conditions C j PH Halt mode dual clock option XT clock XT clock Slow mode dual clock option XT clock XT clock Fast mode dual clock option XT clock CF clock 2 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR XT CLOCK This clock oscillation circuitry provides the lower speed clock to the system clock generator pre divider timer chattering prevention of IO port and LCD circuitry This oscillator will be disabled when the fast clock only option is selected by mask option or it will be active all the time after the initial reset In stop mode this oscillator will be stopped 32168Hz Crystal 1 X tal 14 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual When backup flag
67. address 010H interrupt 3 address 01CH interrupt 4 address 020H interrupt 5 address 024H and interrupt 6 address 028H in the program memory Address Address 000h Initial reset 000h 010h Interrupt 2 014h Interrupt 0 018h Interrupt 1 01Ch Interrupt 3 High Low Nibble Nibble 020h Interrupt 4 024h Interrupt 5 028h Interrupt 6 FFFh 8 Bits 7 I 16bts gt Instruction ROM PROM organization Table ROM TROM organization This figure shows the Organization of ROM 2 4 2 TABLE ROM TROM This memory space stores the constant data or look up table for the usage of main program All of the table ROM addresses are specified by the index address register HL The data width could be 8 bits or 4 bits which depends on the different usage Refer to the explanation of instruction chapter 2 5 INDEX ADDRESS REGISTER HL This is a versatile address pointer for the data memory RAM and table ROM TROM The index address register HL is a 12 bit register and the contents of the register can be modified by executing MVU MVH and MVL instructions Executed MVL instruction will load the content of specified data memory to the lower nibble of the index register L In the same manner executed MVH and instructions will load the contents of the data RAM Rx to the higher nibble of the register and QU respectively 2
68. ble flag 5 SRF5 is set to 1 the input signal change at the INT pins causes the stop mode to be released In the same manner when SRF4 SRF3 is set to 1 the input signal change at the input mode pins of IOC port and the signal changed on INT pin causes the stop mode to be released respectively Example This example illustrates the stop mode released by port IOC and INT pin Assume all of the pins in IOD and IOC have been defined as input mode 41 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual PLC 05h Reset the HRFO and HRF2 SHE 04h HEF2 and HEF5 is set so that the signal change at INT pin causes start condition flag 4 or 8 to be set SCA 18h SEF4 is set so that the signal changes at port IOC and IOD cause the start conditions SCF1 to be set SRE 038h SRF5 4 are set so that the signal changes at port IOC IOD and INT pin cause the stop mode to be released STOP Enter the stop mode Im STOP release MSC 10h Check the signal change at INT pin that causes the stop mode to be released MSB 11h Check the signal change at port IOC IOD that causes the stop mode to be released 2 16 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM87P08 when LCD is operating During the halt mode the program memory ROM is not in operation and only the oscillator circuit pre divider circuit sound circuit I O port chattering prevention circuit and LCD driv
69. by the CX signal release is caused by the 2 rising edge on CX and then clear the halt release request flag read the content of the counter 3 8 Key Matrix Scanning TM8706 shares the timing of the LCD waveform to scan the key matrix circuitry These scanning output pins are SEG1 16 for easy to understand named these pins as K1 K16 The time sharing of the LCD waveform will not affect the display of the LCD panel The input port of the key matrix circuitry is composed of KI1 KI4 pins these pins are muxed with SEG32 SEG35 pins and selected by mask option MASK OPTION table Mask Option name Selected item SEG32 IOC1 KM 3 SEG33 IOC2 KI2 3 KI2 SEG34 IOC3 KI3 3 KI3 SEG35 IOCA KI4 3 Kl4 The typical application circuit of the key matrix scanning is shown below Executing SPKX X SPK Rx and SPK instructions could set the scanning type of K16 K15 K14 K13 K12 K11 K10 KO K8 K7 K6 K5 K4 K2 K1 KH Q 0 0 0 O0 O L o 0 0 0 0 0 0 0 0 0 0 L o 0 0 40 0 0 0 0 0 0 0 Kd L o 0 0 0 0 0 0 the key matrix The bit pattern of these 3 instructions are shown below Instruction Bi Bite Bib Bits Bito SPKX X X7 X6 X5 X4 KS X2 1X4 X0 SPK Rx
70. caused by RFC counter finish TMR2 underflow SKI underflow Read only Read only Read only Read only 2 14 5 STATUS REGISTER 4 STS4 Status register 4 STS4 consists of 3 flags 1 System clock selection flag CSF The system clock selection flag CSF indicates which clock source of the system clock generator SCG is used Executing SLOW instruction will change the clock source BCLK of the system clock generator SCG to the slow speed oscillator XT clock and the system clock selection flag CSF is reset to 0 Executing FAST instruction will change the clock source BCLK of the system clock generator SCG to the fast speed oscillator CF clock and the system clock selection flag CSF is set to 1 For the operation of the system clock generator refer to 3 3 2 Watchdog timer enable flag WTEF The watchdog timer enable flag WDF indicates the operating status of the watchdog timer 3 Overflow flag of 16 bit counter of RFC RFOVF The overflow flag of 16 bit counter of RFC RFOVF is set to 1 when the overflow of the 16 bit counter of RFC occurs The flag will reset to 0 when this counter is initiated by executing SRF instruction The MSD instruction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 4 STS4 37 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Bit 3 Bit 2 Bit 1 Bit
71. ce the time period and repeat the previous procedure again In this example use the RR network to generate the clock source Timer 1 is used to enable disable the counter LDS 0 0 Set the TMR1 clock source PH9 LDS 13 initiate TMR1 setting value to LDS 2 OFh SHE 2 enable halt release by TMR1 RE LDA 0 OR 1 combine the 1 setting value TMS 2 enable the TMR1 SRF 9 build up the RR network and enable the counter HALT SRF 1 stop the counter when TMR1 underflows MRF1 10h read the content of the counter MRF2 11h MRF3 12h 69 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual MRF4 13h MSD 20h JB2 CNT1_OF check the overflow flag of counter JMP DATA_ACCEPT CNT1_OF DEC 2 decrease the TM1 value LDS 20h 0 SBC 1 JZ CHG RANGE change the clock source of TMR1 PLC 1 clear the halt release request flag of TMR1 JMP RE_CNT 3 7 3 Enable Disable the Counter by Timer 2 TMR2 will control the operation of the counter in this mode When the counter is controlled by SRF 18 instruction the counter will start to operate until TMR2 is enabled and the first falling edge of the clock source gets into TMR2 When the TMR2 underflow occurs the counter will be disabled and will stop counting the CX clock at the same time This mode can set an accurate time period with which to count the clock numbers on the CX pin For a detailed description of the operation of TMR2 please refer to 2 12 Each time the 1
72. d timer 2 to control the 16 bit counter The 16 bit counter is controlled by the signal X5 1 on CX pin must be set to 1 when this bitis X520 nn counter Note X4 and X5 can not be set to 1 at the same time 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx function Rx lt Rx description The content of Rx is loaded to AC and the working register specified by Ry MRW HL Rx function AC lt Rx description The content of data memory specified by Rx is loaded to AC and data MRW HL Rx Function memory specified by HL AC RIGHL Rx HL HL 1 Description The content of data memory specified by Rx is loaded to AC and the data memory specified by HL The content of the index register QHL will be incremented automatically after executing this instruction MWR Rx Ry function AC Rx lt Ry description The content of working register specified by Ry is loaded to AC and data memory specified by Rx 91 tenx technology inc Rev 1 0 2004 2 2 MWR Rx HL function description MWR Rx HL Function Description SRO Rx function description SR1 Rx function description SLO Rx function description SL1 Rx function description MRA Rx function description TM87P08 User s Manual Rx lt R HL The content of data memory specified by HL is loaded
73. de individually by executing SPA instructions Executing OPA instructions may output the content of specified data memory to the pins defined as output mode the pins defined as the input mode will still remain the input mode Executing IPA instructions may store the signals applied to the IO pins into the specified data memory When the IO pins are defined as the output mode executing IPA instruction will store the content that stored in the latch of the output pin into the specified data memory Before executing SPA instruction to define the I O pins as the output mode the instruction must be executed to output the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changed IOA port had built in pull down resistor and executing SPA instruction to enable disable this device 57 tenx technology inc Rev 1 0 2004 2 2 TM87PO08 User s Manual Initial clear bitO SPA 1 lt Q L IOA1 Initial clear SPA 2 Initial clear SPA 4 Initial D PA 8 lt V bit3 as 4 1 isa p OPA OPAS OPA IPA option IOA3 This figure shows the organization of IOA port Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 3 5 1 1 Pseudo Serial Output IOA port may operate as a pseudo serial
74. derflow counter PLC 10h clear HRF4 LDS 20h 7 SUB 0 when halt is released for the 7 time reset DED flag JNZ NOT RESET DED RF2 2 reset DED flag NOT_RESET_DED LDA 0 store underflow counter to AC JB3 TM1 if the TM2 underflow counter is equal to 8 exit this subroutine JMP RE LOAD END 1 RF2 1 disable the re load function 2 Eh po lt Sape u count count count 08 count NE count IN count Sant HRF4 TM2 PLC 4 Re load DED TENX This figure shows the operating timing of TMR2 re load function for RFC 33 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 14 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start condition flags for TM87P08 IEFO PLC SIE ly pakka 0 r prevention output of IOC SCF 1 PLC 1h HRFO SEF4 SCA 10h Chattering prevention output of IOD SEF3 SCF3 IEF1 SCA 8h SIE 2h Timer1 underflow NES SCF5 IEF2 SIE 4h Signal changed 2 1 0 SCF4 on HEF 2 SHE 4 L IEF3 SIE 8h HRF3 Predivid overilo UN
75. derflows but HRF4 will be set to1 The DED flag must be cleared to 0 by executing RF2 2h instruction before the last HRF4 occurs thus the TENX flag will be reset to 0 when the last HRF4 flag delivery After the last underflow HRF4 of TMR2 occurred disable the re load function by executing RF2 1h instruction For example if the target set value is 500 it will be divided as 52 7 64 1 Setthe initiate value of TMR2 to 52 and start counting 2 Enable the TMR2 halt release or interrupt function 3 Before the first underflow occurs enable the re load function and set the DED flag The TMR2 will continue counting even if TMR2 underflows 4 When halt release or interrupt occurs clear the HRF4 flag by PLC instruction and increase the counting value to count the underflow times 5 When halt release or interrupt occurs for the 7 time reset the DED flag 6 When halt release or interrupt occurs for the 8 time disable the re load function and the counting is completed In the following example S W enters the halt mode to wait for the underflow of TM2 LDS 0 0 initiate the underflow counting register PLC 10h 32 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual SHE 10h enable the halt release caused by TM2 SRF 19h enable RFC and controlled by TM2 TM2X 34h initiate the TM value 52 and clock source is 9 SF2 3h enable the re load function and set DED flag to 1 RE LOAD HALT INC 0 increase the un
76. dog timer organization mask option 9 bit counter PH10 HALT WDF Edge detector WBEST to reset TM8706 Reset pin POR RF 10H 51 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual During initial reset power on reset POR or reset pin the timer is inactive and the watchdog flag WDF is reset Instruction SF 10h will enable the watchdog timer and set the watchdog flag WDF to 1 At the same time the content of the timer will be cleared Once the watchdog timer is enabled the timer will be paused when the program enters the halt mode or stop mode When the TM87P08 wakes up from the halt or stop mode the timer operates continuously It is recommended to execute SF 10h instruction before the program enters the halt or stop mode in order to initialize the watchdog timer Once the watchdog timer is enabled the program must execute SF 10h instruction periodically to prevent the timer overflowed The overflow time interval of watchdog timer is selected by mask option MASK OPTION table Mask Option name Selected item WATCHDOG TIMER OVERFLOW TIME INTERVAL 1 8 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 2 64 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 3 512 x PH10 Note timer overflow time interval is about 16 seconds when PHO 32 768KHz 3 3 CLOCK GENERATOR 3 3 1 FREQUENCY GENERATOR The Frequency Generator is a versatile programmable divider that is capab
77. ds of frequency of PHO could be selected by mask option MASK OPTION table Mask Option name Selected item PHO lt gt BCLK FOR FAST ONLY 1 PHO BCLK PHO lt gt BCLK FOR FAST ONLY _ 2 PHO BCLK 4 To sound circuit 19 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual PHO BCLK FOR FAST ONLY 3 PHO BCLK 8 PHO lt gt BCLK FOR FAST ONLY 4 PHO BCLK 16 2 2 5 SYSTEM CLOCK GENERATOR For the system clock the clock switch circuit permits the different clock input from XTOSC and CFOSC to be selected The FAST and SLOW instructions can switch the clock input of the system clock generator SGC The basic system clock is shown below SCLK T1 T2 T3 1 Machine 2 Cycle Instruction Cycle 2 3 PROGRAM COUNTER PC This is an 11 bit counter which addresses the program memory ROM up to 2048 addresses The program counter PC is normally increased by one 1 with every instruction execution PC PC 1 When executing JMP instruction subroutine call instruction CALL interrupt service routine or reset occurs the program counter PC loads the specified address corresponding to table 2 1 PC specified address shows in When executing a jump instruction except JMP and CALL the program counter
78. e clock FREQ after the first rising edge signal applied on the CX pin when the counter is enabled Once the second rising edge is applied to the CX pin after the counter is enabled the halt release request HRF6 will be delivered and the counter will stop counting In this case if the interrupt enable mode IEF6 is provided the interrupt is accepted and if the halt release enable mode HEF6 is provided the halt release request signal is delivered setting the start condition flag 9 SCF9 in status register 4 STS4 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF 28h SRF Oh SRF control Enable counter BEEN Content of the counter Xo EMO S Xo EMO S N 1 X NX x FREGE 8 4 1151 HALT released Counter starts Counter stops to count caused by the 2nd rising edge This figure shows the timing of the counter controlled by the CX pin Example SCC Oh Select the base clock of the frequency generator that comes from PHO XT clock FRQX 1 5 set the frequency generator to FREQ PH0 6 71 tenx technology inc Rev 1 0 2004 2 2 SHE 40h SRF 28h HALT PLC 40h MRF1 10h MRF2 11h MRF3 12h MRF4 13h TM87P08 User s Manual the setting value of the frequency generator is 5 and FREQ has 1 3 duty waveform enable the halt release caused by 16 bit counter enable the counter controlled
79. e contents of Rx and AC the result is loaded to AC and the data memory Rx The carry flag CF will be affected AC HL HL AC Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL HL indicates an index address of data memory The carry flag CF will be affected AC HL HL AC HL HL 1 Binary adds the contents of QHL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected 96 tenx technology inc Rev 1 0 2004 2 2 Function Description SUB HL Function Description SUB OHL Function Description SUB Rx Function Description SUB HL Function Description SUB HL Function Description ADN Rx Function Description TM87P08 User s Manual AC Rx AC B 1 Binary subtracts the content of AC from the content of Rx the result is loaded to AC The carry flag CF will be affected AC lt HL AC B 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC HL indicates an index address of data memory The carry flag CF will be affected AC lt HL AC B 1 HL HL 1 Binary subtracts the content of AC from the content of HL the result is loaded to
80. e flags SRF4 5 7 The following table shows the stop release request flags The OR ed latched The OR ed input mode The rising or falling signals for 1 4 pins of lOC IOD port edge on INT pin Stop release request flag CSR DSR HRF2 Stop release enable flag SRF7 SRFA SRF3 SRF5 38 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 15 CONTROL REGISTER CTL The control register CTL comes in 4 types control register 1 CTL1 to control register 4 CTLA 2 15 1 CONTROL REGISTER 1 CTL1 The control register 1 CTL 1 being a 1 bit register 1 Switch enable flag 4 SEF4 Stores the status of the input signal change at pins of IOC set in input mode that causes the halt mode or stop mode to be released 2 Switch enable flag 3 SEF3 Stores the status of the input signal change at pins of IOD set in input mode that causes the halt mode or stop mode to be released Executed the SCA instruction may set or reset these flags The following table shows Bit Pattern of Control Register 1 1 Bit 4 Bit 3 Switch enable flag 4 SEF 4 Switch enable flag 3 SEF 3 Enables the halt release caused by the Enables the halt release caused by the signal change on IOC port signal change on IOD port Write only Write only The following figure shows the organization of control register 1 CTL1 HALT loc Released SEF4 Request SCA 10h Interrupt 0 request Interrupt accept 2 15 1 1 T
81. e halt release enable flag HEF2 is provided the start condition flag 2 is delivered If the INT pin interrupt enable mode IEF2 is provided the interrupt is accepted MASK OPTION table For internal resistor type Mask Option name Selected item INT PIN INTERNAL RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTOR 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE For input triggered type Mask Option name Selected item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE IEF2 Interrupt request HEF2 SCF2 Halt release request Mask option HRF2 PLC 4h Initial clear pulse Mask option Interrupt 2 receive signal Open type This figure shows the INT Pin Configuration 67 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 7 Resister to Frequency Converter RFC The resistor to frequency converter RFC can compare two different sensors with the reference resister separately This figure shows the block diagram of RFC SRF 8h IL Controlled by Timer 2 72 SRF 18h SRF 28h gt CX pin signal interrupt request SCF9 counter over nable CNT HRF6 CLKIN 16 bit counter flow flag MRF1 4 4 bit data bus SRF 18h IEF6 i gt SRF 28h FREQ output from frequency generator to data memory and AC This RFC contains four exter
82. e stop instruction is executed the following operations must be completed Specify the stop release conditions by the SRE instruction Specify the halt release conditions corresponding to the stop release conditions if needed Specify the interrupt conditions corresponding to the stop release conditions if needed When the stop mode is released by an interrupt request the TM87P08 will enter the halt mode immediately While the interrupt is accepted the halt mode will be released by the interrupt request The stop mode returns by executing the RTS instruction after completion of interrupt service After the stop release it is necessary that the MSB MSC or MCX instruction be executed to test the halt release signal and that the PLC instruction then be executed to reset the halt release signal Even when the stop instruction is executed in the state where the stop release signal SRF is delivered the CPU does not enter the stop mode but the halt mode When the stop mode is released and an interrupt is accepted the halt release signal HRF is reset automatically HALT released decision 44 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Chapter 3 Control Function 3 1 INTERRUPT FUNCTION There are 7 interrupt resources 3 external interrupt factors and 4 internal interrupt factors When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service ro
83. eO le UID DONO 112 5 9 Miscellaneous InstruellOnss ee eere ae tabe kde eoe Fare des FREE PESE FERE ERER ERE PEDE FEER 114 CHAPTER 6 Programming Wavetform 120 APPNDIX A TM87P08 Instruction Table 121 2 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Chapter 1 General Description 1 1 GENERAL DESCRIPTION The TM87P08 is an EPROM embedded high performance 4 bit micro controller with LCD LED driver It contains all the functions in TM87 series for 3V 5V application except fixed LCD PLA configuration 1 2 FEATURES 1 Powerful instruction set 178 instructions e Binary addition subtraction BCD adjusts logical operation in direct and index addressing mode Single bit manipulation set reset decision for branch Various conditional branches 16 working registers and manipulation Table look up LCD driver data transfer 2 Memory capacity Program ROM capacity 4096 x 16 bits Index ROM capacity 4096 x 8 bits Data RAM capacity 256 x4 bits 3 Input output ports Port IOA 4 pins with internal pull low Port IOB 4 pins with internal pull low Port IOC 4 pins with internal pull low low level hold chattering prevention clock Port IOD 4 pins with internal pull low chattering prevention clock 4 8 level subroutine nesting 5 Interrupt function External factor
84. ed to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC Rx Rx AC Binary Ors the contents of Rx and AC the result is loaded to AC and the data memory Rx AC HL HL AC Binary Ors the contents of HL and AC the result is loaded to AC and the data memory QHL 100 tenx technology inc Rev 1 0 2004 2 2 OR HL Function Description ADCI Ry D Function Description ADCI Ry D Function Description SBCI Ry D Function Description SBCI Ry D Function Description ADDI Ry D Function Description TM87P08 User s Manual HL indicates an index address of data memory AC HL HL AC HL HL 1 Binary Ors the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC lt Ry D CF D represents the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC The carry flag CF will be affected D 0H FH Ry lt Ry D CF D represents the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC Ry D
85. er output circuit are in operation If the timer has started operating the timer counter still operates in the halt mode After the HALT instruction is executed and no halt release signal SCF1 SCF3 HRF1 6 is delivered the CPU enters the halt mode The following 3 conditions are available to release the halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter halt mode again by executing the RTS instruction after completion of the interrupt service When the halt mode is released and an interrupt is accepted the halt release signal is reset automatically 2 The signal change specified by the SCA instruction is applied to port IOC SCF1 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When the halt mode is released in either 2 or 3 it is necessary that the MSB MSC or MCX instruction is executed in order to test the halt release signal and that the PLC instruction is then executed to reset the halt release signal HRF Even when the halt instruction is executed in the state where the halt release signal is delivered the CPU does not enter the halt mode 42 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 17 BACK UP FUNCTION TM87P08 provides a back up mode to avoid system malfunction when heavy loading occurs such as buzzer activation LED illumination etc Since heavy loading wi
86. errupt 3 is accepted and the instruction at address 1CH is executed automatically 3 16 bit counter of RFC CX pin control mode interrupt request An interrupt request signal HRF6 is delivered when the 2 falling edge applied on CX pin and 16 bit counter stops to operate In this case if the interrupt enable flag6 IEF6 is set interrupt 6 is accepted and the instruction at address 28H is executed automatically 46 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 1 2 INTERRUPT PRIORITY If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are held When the interrupt service routine is initiated all of the interrupt enable flags IEFO IEF6 are cleared and should be set with the next execution of the SIE instruction Refer to Table 3 1 Example Assume all interrupts are requested simultaneously when all interrupts are enabled and all of the the pins of IOC have been defined as input mode PLC 7Fh Clear all of the flags SCA 18h enable the interrupt request of IOC IOD SIE 5Fh enable all interrupt requests diui all interrupts are requested simultaneously Interrupt caused by the predivider overflow occurs and interrupt service is concluded SIE 57h Enable the interrupt request except the predivider Interrupt caused by the TM1 underflow occurs and
87. eset the halt release request flag 5 HRF5 or the SHE instruction must be used to reset the halt release enable flag 5 HEF5 2 Start condition flag 6 SCF6 SCF6 is set to 1 when an underflow signal from timer 2 TMR2 causes the halt release request flag 4 HRF4 to be outputted and the halt release enable flag 4 HEF4 is set beforehand To reset the start condition flag 6 SCF6 the PLC instruction must be used to reset the halt release request flag 4 HRF4 or the SHE instruction must be used to reset the halt release enable flag 4 HEF4 3 Start condition flag 9 SCF9 is set when a finish signal from mode of RFC function causes the halt release request flag 6 HRF6 to be outputted and the halt release enable flag 9 HEF9 is set beforehand In this case the 16 counter of RFC function must be controlled by CX pin please refer to 2 16 9 To reset the start condition flag 9 SCF9 the PLC instruction must be used to reset the halt release request flag 6 HRF6 or the SHE instruction must be used to reset the halt release enable flag 6 HEF6 The MCX instruction can be used to transfer the contents of status register 3X STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3X STS3X Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 9 Start condition flag 6 Start condition flag 8 SCF9 SCF6 SCF8 Halt release caused by NA Halt release caused by Halt release
88. ev 1 0 2004 2 2 description LCT Lz HL function description LCB Lz HL function description LCP Lz HL function description LCDX D Function Description LCTX D Function Description LCBX D Function Description TM87P08 User s Manual HL indicates an index address of table ROM The contents of table ROM specified by HL are loaded to the LCD latch specified by Lz directly LCD latch Lz lt data decoder lt R HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder LCD latch Lz lt data decoder lt R HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder If the content of HL is 0 the outputs of the data decoder are all 0 LCD latch Lz lt R HL AC The contents of index RAM specified by HL and the contents of AC are loaded to the LCD latch specified by Lz Mullti LCD latches Lz s TAB HL HL indicates an index address of table ROM The content of table ROM specified by HL are loaded to several LCD latches Lz simultaneously Refer to Table 5 2 The range of multi Lz is specified by data D 0 3 Multi LZ OOH OFH Multi Lz 10H 1FH The range of multi Lz latches Table 5 2 Mullti LCD latch Lz data decoder lt HL The contents of index RAM specified by HL are loaded to several LCD latches Lz simultaneousl
89. frequency During the application of melody output sound effect output or carrier output of remote control the frequency generator needs to combine with the alarm function BZB BZ For detailed information about this application refer to section 3 4 54 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 3 3 Halver Doubler Tripler The halver doubler tripler circuits are used to generate the bias voltage for LCD and are composed of a combination of PH2 PH3 PH4 PH5 3 3 4 Alternating Frequency for LCD The alternating frequency for LCD is a frequency used to make the LCD waveform 3 4 BUZZER OUTPUT PINS There are two output pins BZB and BZ Each are MUXed with IOB3 and IOB4 by mask option respectively BZB and BZ pins are versatile output pins with complementary output polarity When buzzer output function combined with the clock source comes from the frequency generator this output function may generate melody sound effect or carrier output of remote control MASK OPTION table Mask Option name Selected item SEG30 IOB3 BZB 3 BZB SEG31 IOB4 BZ 3 BZ MUX 05 MUX ALM X X8 X7 This figure shows the organization of the buzzer output 3 4 1 BASIC BUZZER OUTPUT The buzzer output BZ BZB is suitable for driving a transistor for the buzzer with one output pin or driving a buzzer with BZ and BZB pins directly It is capable of delivering a modulation output in any
90. g this operation the program must use the halt release request flag or interrupt to check the wanted counting value t is necessary to execute the TMS or instruction to set the down count value before the re load function is enabled because TMR1 will automatically count down with an unknown value once the re load function is enabled Never disable the re load function before the last expected halt release or interrupt occurs If TMS related instructions are not executed after each halt release or interrupt occurs the TMR1 will stop operating immediately after the re load function is disabled For example if the expected count down value is 500 it may be divided as 52 7 64 First set the initiate count down value of TMR1 to 52 and start counting then enable the TMR1 halt release or interrupt function Before the first time underflow occurs enable the re load function The TMR1 will continue operating even though TMR1 underflow occurs When halt release or interrupt occurs clear the HRF1 flag by PLC instruction After halt release or interrupt occurs 8 times disable the re load function and the counting is completed pr E 7th 8th 64 64 21 count lt count TMS HRF1 lt PLC Re load uM In the following example S W enters the halt mode to wait for the underflow of TMR1 LDS 0
91. gle Clock Option 2 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock from the output of clock switch circuitry PHO as input When PHO is changed from H level to L level the content of this counter changes The PH11 to PH15 of the pre divider are reset to 0 when the PLC 100H instruction is executed or at the initial reset mode The pre divider delivers the signal to the halver tripler circuit alternating frequency for LCD display system clock sound generator and halt release request signal I O port chattering prevention clock Frequency Interrupt request Generator BCLK x Initial T1 T2 T3 T4 Sclk PLC 8H Interrupt HALT release Clock Fall edge HRF3 request flag Switch detector circuit instruction _1 bus 2 Clock a switch To timer circuit circuit PLC 100H initial Single clock option Dual clock option cl oc L I 1 Halver tribler circuit This figure shows the Pre divider and its Peripherals The PH14 delivers the halt mode release request signal setting the halt mode release request flag HRF3 In this case if the pre divider interrupt enable mode IEF3 is provided the interrupt is accepted and if the halt release enable mode HEF3 is provided the halt release request signal is delivered setting the start condition flag 7 SCF7 in status register 3 STS3 The clock source of pre divider is PHO and 4 kin
92. he Setting for Halt Mode If the SEF4 is set to 1 the signal changed on IOC port will cause the halt mode to be released and set SCF1 to 1 Because the input signal of IOC port were ORed so it is necessary to keep the unchanged input signals at 0 state and only one of the input signal could change state 39 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 15 1 2 The Setting for Stop Mode If SRF4 and SEF4 are set the stop mode will be released to set the SCF1 when a high level signal is applied to one of the input mode pins of IOC port and the other pins stay in O state After the stop mode is released TM87P08 enters the halt condition The high level signal must hold for a while to cause the chattering prevention circuitry of IOC port to detect this signal and then set SCF 1 to release the halt mode or the chip will return to the stop mode again 2 15 1 3 Interrupt for CTL1 The control register 1 CTL 1 performs the following function in the execution of the SIE instruction to enable the interrupt function The input signal changes at the input pins in IOC port will deliver the SCF1 when SEF4 has been set to 1 by executing SCA instruction Once the SCF1 is delivered the halt release request flag HRFO will be set to 1 In this case if the interrupt enable flag IEFO is set to 1 by executing SIE instruction the interrupt request flag O interrupt 0 will be delivered to interrupt the program If t
93. he interrupt O is accepted by SEF4 and IEFO the interrupt O request to the next signal change at IOC will be inhibited To release this mode SCA instruction must be executed again Refer to 2 16 1 1 2 15 2 CONTROL REGISTER 2 CTL2 Control register 2 CTL2 consists of halt release enable flags 1 2 3 4 5 6 HEF1 2 3 4 5 6 and is set by SHE instruction The bit pattern of the control register CTL2 is shown below Halt release HEF6 HEF5 HEF4 enable flag Enable the halt release Enable the halt release Enable the halt release caused by RFC counter caused by Key caused by TMR2 to be finished HRF6 Scanning HRF5 underflow HRF4 Halt release condition Halt release HEF3 HEF2 HEF1 enable flag Enable the halt release Enable the Enable the halt release caused by pre divider caused by INT pin HRF2 caused by TM1 overflow HRF3 underflow HRF 1 When the halt release enable flag 6 HEF6 is set a finish signal from the 16 bit counter of RFC causes the halt mode to be released In the same manner when HEF1 to HEF4 are set to 1 the following conditions will cause the halt mode to be released respectively an underflow signal from TMR1 the signal change at the INT pin an overflow signal from the pre divider and an underflow signal from TMR2 When the stop release enable flag 5 SRF5 and the HEF2 are set the signal change at the INT pin can cause the stop mode to be released Halt release condition 40 te
94. he preset letter D Preset Letter D Dutv Cvcle orj Do u o 0 1 4 duty 0 1 f 3duy 1 0 f 2duy The following diagram shows the output waveform for different duty cycles clock 1 LT LI LI LI LI LI LII 1 4 duty carrier out 1 3 duty carrier out 1 2 duty carrier out scudo 1 1 duty carrier out 53 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 3 2 Melody Output The frequency generator may generate the frequency for melody usage When the frequency generator is used to generate the melody output the tone table is shown below 1 The clock source is PHO i e 32 768KHz 2 The duty cycle is 1 2 Duty D 2 3 FREQ is the output frequency 4 ideal is the ideal tone frequency 5 96 is the frequency deviation The following table shows the note table for melody application N FREQ Ideal Tone N FREQ Ideal 9 C2 249 65 5360 65 4064 0 19 C4 62 260 063 261 626 0 60 0 64 198 82 3317 82 4069 0 09 E4 49 327 680 329 628 0 59 0 18 0 07 0 64 0 48 1 16 0 64 0 42 0 53 2 1 01 1 1 48 111 0 37 0 31 1 27 98 165 495 164 814 0 41 0 59 1 99 0 64 0 48 1 37 0 64 2 01 69 234 057 233 082 0 42 A5 17 910 222 932 328 2 37 Note 1 Above variation does not include X tal variation 2 If PHO 65536Hz C3 B5 may have more accurate
95. ified by Lz The to DBUSH are all set to 0 when the input data of the data decoder is 0 7 LCP Lz HL The data of the index RAM and accumulator AC are transferred directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown below Table 2 4 The mapping table of LCP and LCD instructions _ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH T HLO T HL1 T HL2 T HL3 T HL4 T HL5 T HL6 T HL7 5 SF2 4h Turns off the LCD display 6 RF2 4h Turns on the LCD display 4 3 3 CONCRETE EXPLANATION Each LCD driver output corresponds to the LCD 1 98duty panel and has 8 latches refer to Figure 4 3 Sample Organization of Segment PLA Option Since the latch input and the signal to be applied to the clock strobe are selected with the segment PLA the combination of segments in the LCD driver outputs is fixed In other words one of the data decoder outputs from DBUSA to DBUSH is applied to the latch input L and one of the PSTBO to PSTB 1Fh outputs is applied to clock CLK 81 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual TM87P08 provide a flash type instruction to update the LCD pattern When the LCTX D LCBX D LCPX D and LCDX D instructions are executed the pattern of DBUS will be outputted to the 16 latches Lz specified by D simultaneously Specified range of latched 00 Lz 00h OFh 01 Lz 10h
96. ing of X X4 is shown below Bit pattern Description Halt mode is released when signal applied to IOC X7 5 X3 0 is reserved 106 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual SIE X function Set Reset interrupt enable flag description Ps IEFO is set so that interrupt 0 Signal change at port IOC specified by SCA X071 is accepted X1 1 The IEF1 is set so that interrupt 1 underflow from timer 1 is accepted X2 1 The IEF2 is set so that interrupt 2 the signal change at the INT pin is accepted X3 1 The IEF3 is set so that interrupt 3 overflow from the predivider is accepted 4 1 The IEF4 is set so that interrupt 4 underflow from timer 2 is accepted X6 1 The IEF6 is set so that interrupt 6 overflow from the RFC counter is accepted XT is reserved SHE X function Set Reset halt release enable flag description XT is reserved SRE X function Set Reset stop release enable flag description 4 1 The SRF4 is set so that the stop mode is released by the signal changed on IOC port 5 1 The SRF5 is set so that the stop mode is released by the signal changed on INT pin X6 X3 0 is reserved FAST function Switches the system clock to CFOSC clock description Starts up the CFOSC high speed osc and then switches the system clock to high speed clock SLOW function Switches the system clock to XTOSC clock low speed osc description Switches the system
97. ion description JZ X function description JC X function description JMP X function description CALL X function description RTS function description TM87P08 User s Manual Program counter jumps to X if AC 0 If the content of AC is not 0 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if CF 0 If the content of CF is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC 0 If the content of AC is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if CF 1 If the content of CF is 1 jump occurs If O the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X Unconditional jump The range of X is from OOOH to FFFH STACK lt 1 Program counter jumps to X A subroutine is called The range of X is from 000 to FFFH PC lt STACK A return from a subroutine occurs 113 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 5 9 MISCELLANEOUS INSTRUCTIONS SCC X function Setting the clock source for IOC IOD chattering prevention PWM output and frequency generator description The following table shows the meaning of each bit for this instruction Bit patter
98. is another number format for TM87P08 When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is processing all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA DAA HL can convert the data from hexadecimal to decimal format after any addition operation The conversion rules are shown in the following table and illustrated in example 1 25 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution OxAC 9 CF 0 lt lt 6 0 lt lt 3 AC ACH 6 Example 1 LDS 10h 9 Load immediate data 9 to data memory address 10H LDS 11h 1 Load immediate data 1 to data memory address 11H and AC RF 1h Reset CF to O ADD 10h Contents of the data memory address 10H and AC are binary added the result loads to AC amp data memory address 10H Rio AC CF 0 DAA 10h Convert the content of AC to decimal format The result in the data memory address 10H is O and in the CF is 1 This represents the decimal number 10 Instructions
99. is setting each scanning cycle checks four specified columns on the key matrix The specified columns are defined by the setting of X3 and X X3X2 00 activates the K1 K4 columns simultaneously X3X2 01 activates the K5 K8 columns simultaneously X3X2 10 activates the K9 K12 columns simultaneously X3X2 11 activates the K13 K16 columns simultaneously X4 Xo are not a factor X7X5X4 111 in this setting each scanning cycle checks two specified columns on the key matrix The specified columns are defined by the setting of X gt and X1 X3X2X1 000 activates the K1 K2 columns simultaneously X3X2X1 001 activates the K4 columns simultaneously X3X2X1 110 activates the K13 K14 columns simultaneously X3XoX1 111 activates the K15 K16 columns simultaneously Xo is not a factor Sets the Key matrix scanning output state When SEG1 16 is are used for LCD driver pin s sets the contents of AC and Rx to specify the key matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit patterns of AC and Rx corresponding to SPKX are shown below 89 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Instruction Bit Bits Bit4 Bit2 Bit1 BitO SPKRx AC2 AC1 ACO Rx3 Rx2 1 SPKX X
100. it of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting Enables all of the pull low and Disables all of the pull low and X4 1 ddisables the low level hold X4 0 enables the low level hold devices devices X3 0 X1 0 X0 0 OPC Rx function lt Rx description The content of Rx is outputted to I OC port IPC Rx function Rx lt IOC description The data of I OC port is loaded to AC and data memory Rx SPD X 87 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Function Defines the input output mode of each pin for IOD port and enables or disables the pull low device Description Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting X4 1 Enable the pull low device on X4 0 Disable the pull low device on 1001 1004 simultaneously 1001 0004 simultaneously IOD4 as output mode IOD4 as input mode IOD3 as output mode IOD3 as input mode IOD2 as output mode IOD2 as input mode IOD1 as output mode IOD1 as input mode OPD Rx Function 1 lt Rx Description The content of Rx is outputted to I OD port IPD Rx Function Rx AC lt Description The data of the I OD port is loaded to AC and data memory Rx SPKX X Function Sets the Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s set
101. lag 73 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Since the key matrix scanning function shares the timing of LCD waveform the scanning frequency corresponds to the LCD frame frequency and the LCD duty cycle The formula for the key matrix scanning frequency is shown below key matrix scanning frequency Hz LCD frame frequency x LCD duty cycle x 2 Note 2 is a factor For example if the LCD frame frequency is 32Hz and duty cycle is 1 5 duty the scanning frequency for the key matrix is 320Hz 32 x 5 x 2 key scanning SKI input amp latch key scanning input amp latch key scanning Dis i input amp latch Rising edge strobe Q HRF5 n 23 key scanning 5 input amp latch 2 1 key scanning enable signal IPC PLC 20h Initial Reset Interrupt 5 request This figure shows the organization of Key matrix scanning input Example SPC Ofh Disables all the pull down devices on the internal IOC port Sets all of the IOC pins as the output mode SPKX 10h Generates HALT release request when a key is depressed 74 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Scanns every column simultaneously in each cycle PLC 20h Clears HRF5 SHE 20h Sets HEF5 HALT waits for the halt release caused by the key matrix MCX 10h Checks SCF8 SKI JBO ski_release ski_release IPC 10h reads the KI1
102. le of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter The following shows the organization of the frequency generator BCLK 8 bit Programmable Duty Cycle Ne Frequency output iis FREQ C AC1 ACO Rx3 RxO SC FRQ D Rx SCC instruction may specify the clock source selection for the frequency generator The frequency generator outputs the clock with different frequencies and duty cycles corresponding to the presetting data of FRQ related instructions The FRQ related instructions preset a letter N into the programming divider and letter D into the duty cycle generator The frequency generator will then output the clock using the following formula FREQ clock source N 1 X Hz X 1 2 3 4 for 1 1 1 2 1 3 1 4 duty This letter N is a combination of data memory and accumulator AC or the table ROM data or operand data specified in the FRQX instruction The following table shows the bit pattern of the combination 52 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The following table shows the bit pattern of the preset letter N a The bit pattern of preset letter Programming divider FRQ_D Rx Notes 1 TO T7 represents the data of table ROM 2 X7 represents the data specified in operand X The following table shows the bit pattern of t
103. lected by mask option When IOC port is in used the 0 signal applied to all these pins that had be set as input mode in the same time reset signal is delivered MASK OPTION table IOC or KI pins are used as key reset Mask Option name Selected item IOC1 FOR KEY RESET 1 USE IOC2 FOR KEY RESET 1 USE IOC3 FOR KEY RESET 1 USE IOC4 FOR KEY RESET 1 USE 50 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual IOC pins aren t used as key reset Mask Option name Selected item 1 1 FOR KEY RESET 2 NO USE 2 FOR KEY RESET 2 NO USE FOR KEY RESET 2 NO USE IOC4 FOR KEY RESET 2 NO USE The following figure shows the key reset organization 10c1 Le D IOC2 h nr n p I IOC r IOC3 MDP IOC4 L 3 2 4 WATCHDOG RESET The timer is used to detect unexpected execution sequence caused by software run away The watchdog timer consists of a 9 bit binary counter The timer input PH10 is the 10th stage output of the pre divider When the watchdog timer overflows it generates a reset signal to reset TM87P08 and most of the functions in TM87P08 will be initiated except for the watchdog timer which is still active WDF flag will not be affected and PHO PH10 of the pre divider will not be reset The following figure shows the watch
104. ll cause a large voltage drop in the supply voltage the system will malfunction in this condition Once the program enters back up mode 1 32 768KHz Crystal oscillator will operate in a large driver condition and the internal logic function operates with a higher supply voltage TM87P08 will get a higher power supply noise margin while back up mode is active but it will also receive an increase in power consumption The back up flag BCF indicates the status of the back up function BCF flag can be set or reset by executing the SF or RF instructions respectively The back up function has different performance corresponding to different power mode options shown in the following table aeons Initial reset cycle BCF 1 hardware controlled After initial reset cycle BCF 1 hardware controlled Executing SF 2h instruction BCF 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode 1 hardware controlled 3V battery or higher mode BCF 0 BCF 1 32 768KHz Crystal Oscillator Small driver Large driver TM87P08 Oscillation Note For power saving reasons it is recommended to reset BCF flag to 0 when back up mode is not used 2 18 STOP FUNCTION STOP The stop function is another solution to minimize the current dissipation for TM87P08 In stop mode all of functions in TM87P08 are held including oscillators All of the LCD corresponding signals COM and Segment
105. loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory Rx AC lt H T HL The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx Rx AC lt H T HL amp HL QHL 1 The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx and then is increased in HL Rx AC lt L T HL The lower nibble data of Table ROM specified by HL is loaded to the data memory specified by Rx 104 tenx technology inc Rev 1 0 2004 2 2 LDL Rx HL function description MRF1 Rx function description MRF2 Rx function description MRF3 Rx function description MRF4 Rx function description TM87P08 User s Manual Rx AC lt L T HL HL HL 1 The lower nibble data of Table ROM specified by QHL is loaded to the data memory specified by Rx and then incremented the content of HL Rx AC lt RFOC 3 0 Loads the lowest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 3 Bit 2 RFC 2 Bit 1 RFC 1 Bit 0 RFC O Rx AC lt RFC 7 4 Loads the 2 nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 7 Bit 2 RFC 6 Bit 1 RFC 5 Bit 0 RFC 4 Rx AC lt RFC 11 8 Loads the 3 nibble data of 16 bit c
106. lt release enable flag 3 HEF3 is set beforehand To reset start condition flag 7 SCF7 the PLC instruction must be used to reset the halt release request flag 3 HRF3 or the SHE instruction must be used to reset the halt release enable flag 3 HEF3 4 The 15th stage s content of the pre divider The MSC instruction is used to transfer the contents of status register 3 STS3 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3 STS3 Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 7 15th stage ofthe Start condition flag 5 Start condition flag 4 SCF7 pre divider SCF5 SCF4 Halt release caused Halt release caused Halt release caused by TMR1 underflow by INT pin by pre divider overflow Read only Read only Read only Read only 2 14 4 STATUS REGISTER 3X STS3X When the halt mode is released with start condition flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode Status register 3X STS3X consists of 3 flags 1 Start condition flag 8 SCF8 SCF8 is set to 1 when any one of KI1 4 1 0 KI1 4 1 in LED mode KI1 4 0 in LCD mode causes the 36 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual halt release request flag 5 HRF5 to be outputted and the halt release enable flag 5 HEF5 is set beforehand To reset the start condition flag 8 SCF8 the PLC instruction must be used to r
107. ms 3 When the TMR1 clock is PH15 TMR1 set time Set value error 32768 1 fosc KHz ms 4 When the TMR1 clock is PH5 TMR1 set time Set value error 32 1 fosc KHz ms 5 When the TMR1 clock is PH7 TMR1 set time Set value error 128 1 fosc KHz ms 6 When the TMR1 clock is PH11 TMR1 set time Set value error 2048 1 fosc KHz ms 7 When the TMR1 clock is PH13 TMR1 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error lt 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider 7 The 7th stage output of the predivider PH9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR1 clock is FREQ TMRI set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 28 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 12 2 RE LOAD OPERATION TMR1 provides the re load function which can extend any time interval greater than 3Fh The SF 80h instruction enables the re load function and RF 80h instruction disables it When the re load function is enabled the TMR1 will not stop counting until the re load function is disabled and TMR1 underflows again Durin
108. n Clock source setting Bit pattern Clock source setting X621 The clock source comes from X6 0 The clock source comes from the the system clock BCLK 00 Refer to section 3 3 4 for 00 v pattern Clock source setting a SL Clock source setting X1 clock of IOD port PHO X1 0 001 of IOC port PHO_ e X1 X0 e clock of IOD port _ 8 e X1 010 of IOC port PH8_ 221010 clock of IOD port PH6 X106 of IOC port PH6 FRQ D Rx function Frequency generator lt D Rx description Loads the content of AC and data memory specified by Rx and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting GW The bit pattern of preset letter N Programming divider i FRQ D Rx 2 1 og 1 4 duty O 1 Nay 1 0 ty FRQ HL function Frequency generator D T HL description Loads the content of Table ROM specified by HL and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting a The bit pattern of preset letter N Programming divider FRQ D HL Note TO T7 represents the data of table ROM 114 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Preset Letter D Duty Cycle D1 0 0 1 4 duty 0 1 134 1 0 FRQX D X function Frequency generato
109. n fast clock oscillator selected by mask option 2 2 2 1 RC OSCILLATOR WITH EXTERNAL RESISTOR CF CLOCK This kind of oscillator could only be used in FAST only option the fast clock source of dual clock mode can t use this oscillator When this oscillator is used the frequency option of the RC oscillator with internal RC is not cared If FRIN pin is unused it must be connected to GND MASK OPTION table Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY or 3 DuaL Mask Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 1 EXTERNAL RESISTOR 15 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual External Resistor 2 2 2 2 External 3 58MHz Ceramic Resonator oscillator MASK OPTION table Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY or 3 DUAL Mask Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 2 3 58MHz CERAMIC RESONATOR 3 58MHz Ceramic Resonator Notes 1 When the program has to reset the BCF flag to 0 in Li battery power mode don t use a 3 58MHz Ceramic Resonator as the oscillator 2 2 3 THE COMBINATION OF THE CLOCK SOURCES There are three types of combination of the clock sources that can be selected by mask option 2 2 3 1 DUAL CLOCK MASK OPTION table Mask Option name Selected item CLOCK SOURCE 3 DUAL The operation of the dual clock option is sh
110. nal pins CX the oscillation Schemmit trigger input RR the reference resister output pin RT the temperature sensor output pin RH the humidity sensor output pin this can also be used as another temperature sensor or can even be left floating These CX RR RT and RH pins are MUXed with IOA1 SEG37 to IOA4 SEG40 respectively and selected by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX 3 CX SEG25 IOA2 RR 3 RR SEG26 IOA3 RT 3 RT SEG27 IOA4 RH 3 RH 3 7 1 RC Oscillation Network The RFC circuitry may build up 3 RC oscillation networks through RR RT or RH and CX pins with external resistors Only one RC oscillation network may be active at a time When the oscillation network is built up executing SRF 1h SRF 2h SRF 4h instructions to enable RR RT RH networks respectively the clock will be generated by the oscillation network and transferred to the 16 bit counter through the CX pin It will then enable or disable the 16 bit counter in order to count the oscillation clock Build up the RC oscillation network 68 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 1 Connect the resistor and capacitor on the RR RT RH and CX pins Fig 2 24 illustrates the connection of these networks 2 Execute SRF 1h SRF 2h or SRF 4h instructions to activate the output pins for RC networks respectively The RR RT RH pins will become of a tri state type when
111. nd the CPHL instruction will be forced as NOP If the compared result is not equal the next executed instruction that is behind CPHL instruction will operate normally The comparison bit pattern is shown below CPHL X XT X6 X5 X4 X3 X2 X1 X0 HL IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO 5 7 DECIMAL ARITHMETIC INSTRUCTIONS DAA function description DAA Rx function description AC lt BCD AC Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected Rx lt BCD AC Converts the content of AC to binary format and then restores to AC and data memory specified by Rx 110 tenx technology inc Rev 1 0 2004 2 2 TM87PO08 User s Manual DAA HL function description When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC R HL lt BCD AC Converts the content of AC to decimal format and then restores to AC and data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC data before DAA CF data before DAA 0 lt lt 3 AC 6 DAA OHL Function Description AC HL BCD AC HL 1 Converts
112. ng the SCA instruction will cause SCF3 to be reset to 0 Backup flag BCF This flag could be set reset by executing the SF 2h RF 2h instruction 2 14 3 STATUS REGISTER 3 STS3 When the halt mode is released caused by the start condition flag 2 SCF2 status register 3 STS3 will store the status of the factor in the release of the halt mode Status register 3 STS3 consists of 4 flags 1 Start condition flag 4 SCF4 Start condition flag 4 SCF4 is set to 1 when the signal change at the INT pin causes the halt release request flag 2 HRF2 to be outputted and the halt release enable flag 2 HEF2 is set beforehand To reset start condition flag 4 SCF4 the PLC instruction must be used to reset the halt release request flag 2 HRF2 or the SHE instruction must be used to reset the halt release enable flag 2 HEF2 2 Start condition flag 5 SCF5 Start condition flag 5 SCF5 is set when an underflow signal from Timer 1 TMR1 causes the halt release request flag 1 HRF1 to be outputted and the halt release enable flag 1 HEF 1 is set beforehand To reset start condition flag 5 SCF5 the PLC instruction must be used to reset the halt release request flag 1 HRF 1 or the SHE instruction must be used to reset the halt release enable flag 1 HEF1 3 Start condition flag 7 SCF7 Start condition flag 7 SCF7 is set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be outputted and the ha
113. normal operation after internal reset cycle automatically no matter what the signal on RESET pin returned to 0 or not MASK OPTION table Mask Option name Selected item RESET PIN TYPE 2 PULSE 49 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The following table shows the initial condition of TM87P08 in reset cycle Program counter Start condition flags 1 to 7 Backup flag Stop release enable flags 4 5 7 Switch enable flags 4 Halt release request flag Halt release enable flags 1 to 3 Interrupt enable flags 0 to 3 Alarm output Pull down flags in 1 I OD port Input output ports 1 I OB VOD I OD port chattering clock Frequency generator clock source and duty cycle Resistor frequency converter LCD driver output Timer 1 2 Watchdog timer Clock source Notes PH3 the 3rd output of predivider 3 2 3 IOC Port RESET PC SCF1 7 BCF SRF3 4 5 7 SEF3 4 HRF 0 6 HEF 1 6 6 ALARM PORT I OA l OB I OD Cch Cfq RFC WDT BCLK PH10 the 10th output of predivider Mask option can unlighted all of the LCD output Address 000H 1 Li B option DC 0 1 with pull down resistor Input mode PH10 PHO duty cycle is 1 4 output is inactive Inactive RR RT RH output 0 All lighted mask option Inactive Reset mode WDF 0 XT clock slow speed clock in dual clock option Key reset function is se
114. nx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 2 15 3 CONTROL REGISTER 3 CTL3 Control register 3 CTL3 is organized with 6 bits of interrupt enable flags IEF to enable disable interrupts The interrupt enable flag IEF is set reset by SIE instruction The bit pattern of control register 3 CTL3 is shown below Enable flag Request lag Enable the interrupt request caused by RFC counter to be finished HRF6 by TMR2 underflow HRF4 nterrupt No Interrupt 4 Enable flag IEF2 Enable the interrupt request caused by predivider overflow HRF3 by INT pin HRF2 nterrupt No Interrupt 2 Enable flag IEFO by TM1 underflow HRF 1 100 port signal to be changed HRF0 Interrupt No When any of the interrupts are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to 0 automatically Therefore the desirable interrupt enable flag IEFx must be set again before exiting from the interrupt routine 2 15 4 CONTROL REGISTER 4 CTL4 Control register 4 CTL4 being a 3 bit register is set reset by SRE instruction The following table shows the Bit Pattern of Control Register 4 CTL4 1007919888 SRF5 SRF4 SRF3 enable flag Opa BaSe Enable the stop release Enable the stop release Enable the stop release re den fla request caused by signal request caused by signal request caused by signal q 9 change on INT pin HRF2 change on IOC change on IOD When the stop release ena
115. ogy inc Rev 1 0 2004 2 2 TM87P08 User s Manual D bitO lt Q CLK bitO OC 1 nono iod bit1 lt MG CLK bit1 Ic no gt gt H Initial edge dectect amp SCF spc 8 chattering Data low option pus bit2 CLK qe bit3 I bit3 IOC Control 2 IPC v This figure shows the organization of IOC port Note If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 1 port had built in pull down resistor and executing SPC instruction to enable disable this device IOC port also built in the pull low device for each pin but these devices are enable by mask option The pull down resistor and low level hold device in each IOC pin can t exist in the same time When the pull down resistor is enabled the low level hold device will be disable vise versa Executing SPC 10h instruction to enable the pull low device and 62 tenx technology inc
116. om the working register Ry the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH AC Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The result will not affect the carry flag CF D 0H FH AC Ry lt Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The result will not affect the carry flag CF D 0H FH AC lt Ry amp D D represents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC 102 tenx technology inc Rev 1 0 2004 2 2 ANDI Ry D Function Description EORI Ry D Function Description EORI Ry D Function Description ORI Function Description ORI Ry D Function Description TM87P08 User s Manual D 0H FH lt Ry amp D D represents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH lt Ry EOR D D represents the immediate data Exlusive Ors the contents of Ry and D the result is loaded to AC D 0H FH AC Ry lt Ry D D represents the immediate data Exclusive Ors the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH AC Ry D D
117. orce if X7 0 IDBF7 0 SPK Rx 1111 0000 OXXX KO1 16 RX amp AC SPK 1111 0001 0000 0000 KO1 16 lt T HL SPKX X 1111 0010 XXXX XXXX X671 KEY S release by scanning cycle X6 0 KEY_S release by normal key scanning X7 5 4 000 Set one of KO1 16 1 by X3 0 X7 5 4 001 Set all 1 X7 5 4 010 Set all Hi z X7 5 4 10X Set eight of KO1 16 1 by 0 gt KO1 8 1 gt KO9 16 X7 5 42110 Set four of KO1 16 1 X32 X3 2 00 gt KO1 4 X3 2 01 gt KO5 8 X3 2 10 gt KO9 12 X3 2 11 gt KO13 16 127 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual X7 5 4 111 Set two of KO1 16 1 by X3 2 1 1 000 1 2 X3 1 001 gt KO3 4 1 010 5 6 X3 1 011 gt KO7 8 X3 1 100 gt KO9 10 X3 1 101 gt KO11 12 1 110 13 14 X3 1 111 gt KO15 16 RTS 1111 0100 0000 0000 PC lt STACK CALL Return SCC X 1111 0100 1 0 XXXX 1 Cfq BCLK X670 Cfq PHO 1 Set P C Cch X321 Set P D Cch X2 1 0 001 Cch PH10 X2 1 02010 Cch PH8 2 1 0 100 Cch PH6 SCA X 1111 0101 000X X000 X4 Enable SEF4 C1 4 X3 Enable SEF3 D1 4 SPA X 1111 0101 100X XXXX X4 Set A4 1 Pull Low 1 low X3 0 Set A4 1 I O 1 Output 0 Input SPB X 1111 0101 101X XXXX X4 Set B4 1 Pull Low 1 Pull low X3 0 Set B4 1 I O 1 Output 0 Input SPC X 11
118. ounter of RFC to AC and data memory specified by Rx Bit 3 RFC 11 Bit 2 RFC 10 Bit 1 RFC 9 Bit 0 RFC 8 Rx AC lt RFC 15 12 Loads the highest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 15 Bit 2 RFC 14 Bit 1 RFC 13 Bit 0 RFC 12 105 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 5 5 CPU CONTROL INSTRUCTIONS NOP function description HALT function description STOP function description SCA X function description no operation no operation Enters halt mode The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted 2 The signal change specified by the SCA instruction is applied to IOC 3 The halt release condition specified by SHE instruction is met When an interrupt is accepted to release the halt mode the halt mode returns by executing the RTS instruction after completion of interrupt service Enters stop mode and stops all oscillators Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 1 One of the signal on KI1 4 is H L LED LCD in scanning interval 2 A signal change in the INT pin 3 One of the signals on IOC port is H The data specified by X causes the halt mode to be released The signal change at port IOA IOC is specified The bit mean
119. own in the following figure When this option is selected by mask option the clock source BCLK of system clock generator will switch between XT clock and CF clock according to the user s program 16 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual When the halt and stop instructions are executed the clock source BCLK will switch to XT clock automatically The XT clock provides the clock to the pre divider timer I O port chattering prevention and LCD circuitry in this option Halt Halt Halt mode Slow mode Slow Fast mode XTOSC active XTOSC active XTOSC active CFOSC stop HALT CFOSC stop Fast CFOSC active released Stop ul Sto released Reset P release Reset Reset state Reset Stop mode Power on resa pus 4 XTOSC stop Reset pin reset Stop Watchdog timer reset Key reset CFOSC stop State Diagram of Dual Clock Option was shown on above figure After executing FAST instruction the system clock generator will hold 12 CF clocks after the CF clock oscillator starts up and then switches CF clock to BCLK This will prevent the incorrect clock from delivering to the system clock in the start up duration of the fast clock oscillator n4 FAST BCLK HOLD 12 CLOCKS This figure shows the System Clock Switches from Slow to Fast 17 tenx technology inc Rev 1 0 2004 2 2
120. ption name Selected item SEG36 IOD1 2 IOD1 SEG37 IOD2 2 1002 SEG38 IOD3 2 IOD3 SEG39 IOD4 2 IOD4 After the reset cycle the IOD port is set to input mode each bit of port can be set to input or output mode individually by executing SPD instructions Executing the OPD instruction outputs the contents of specified data memory locations to the pins set as output the other pins which are set as input will still remain the in the input mode Executing IPD instructions will store the signals applied to the IOD pins in the specified data memory locations When the IOD pins are set as output executing IPD instructions will save the data stored in the output latches in the specified data memory locations Before executing SPD instructions to define the IOD pins as output the OPD instructions must be executed to output the data to those output latches This will prevent the chattering signal when the IOD pins change to output mode IOD port has a built in pull low device for each pin that is selected by mask option To enable or disable this device execute the SPD instruction When the IOD pin has been set to the output mode the pull low device will be disabled MASK OPTION table Pull low function option Mask Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE Note If the input level is in the floating state a large current straight through current flow
121. r D X description Loads the data X X7 and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bit pattern of preset letter Programming divider Note X0 X7 represents the data specified in operand X x Dj D 0 0 Adi _ wo 1 J 3qt x 1 10 12 1 FRQ D Rx The content of Rx and AC as preset data N 2 FRQ D HL The content of tables TOM specified by index address buffer as preset data N 3 FRQX D X The data of operand in the instruction assigned as preset data N TMS Rx function Select timer 1 clock source and preset timer 1 description The content of data memory specified by Rx and AC are loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction jSelectclock Settingvalue The clock source option for timer 1 pHgcc x oJ P 115 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual EREA PH15 FREQ TMS HL function Select timer 1 clock source and preset timer 1 description The content of table ROM specified by HL is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock Setting value The clock source option for timer 1 20 1 0 1 ee 0 100 C PS 104 1 0 PHS TMSX X function Selects time
122. r outputs from PSTB Oh to PSTB 1Fh The input data and clock signal of the latch circuit are DBUSA to DBUSH and PSTB Oh to PSTB 1Fh respectively Each segment pin has 8 latches corresponding to COM 1 8 The segment PLA performs the function of combining DBUSA outputs to DBUSH inputs and then sending them to each latch and strobe PSTB Oh to PSTB 1Fh is selected freely by mask option Of the 512 signals obtainable by combining DBUSA to DBUSH and PSTB Oh to PSTB 1Fh any one of 256 corresponding to the number of latch circuits incorporated in the hardware signals can be selected by programming the aforementioned segment PLA Table 2 7 shows the PSTB Oh to PSTB 1Fh signals Table 2 3 Strobe Signal for LCD Latch in Segment PLA and Strobe in LCT Instruction strobe signal for Strobe in LCT LCB LCP LCD LCD latch instructions The values of Lz in LCT Lz 0012 02 00 ce PSTBO 5 PSTB4 PSTB5 58 ee rr 1 Note The values of Q are the addresses of the working register in the data memory RAM In the LCD instruction Q is the index address in the table ROM The LCD outputs can be turned off without changing segment data The execution of the SF2 4h instruction may turn off the displays simultaneously The execution of the RF2 4h instruction may turn on the display with the patterns turned off These two instructions will not affect the data stored in the latch circuitry When executing the RF2 4h inst
123. r 1 clock source and preset timer 1 description The data specified by X X8 is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Initiate value of timer TMSX X X2 The clock source setting for timer 1 116 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual TM2 Rx function Selects timer 2 clock source and preset timer 2 description The content of data memory specified by Rx and AC is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction The clock source setting for timer 2 10 11 02 PH ofif FPF T 1 0 PH5 TM2 HL function Selects timer 2 clock source and preset timer 2 description The content of Table ROM specified by HL is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction The clock source setting for timer 2 oO of PH BEIDE NEUE 117 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual TM2X X function Selects timer 2 clock source and preset timer 2 description The data specified by X X8 is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction Initiate value of timer x2 The clock source setting for timer 2 SF X function Sets flag description Description of each flag
124. r2 Ctm PH13 Ctm PH11 Ctm PH7 Ctm PH5 Ctm FREQ Ctm PH15 Ctm PH3 Ctm PH9 Set Timer1 Value lt Rx amp AC TM2 1110 0101 0000 0000 Timer2 TQHL TM2X x 20 1110 011X XXXX XXXX X8 7 6 111 X8 7 6 110 X8 7 6 101 X8 7 6 100 X8 7 6 011 X8 7 6 010 X8 7 6 001 X8 7 6 000 X5 0 Ctm PH13 Ctm PH11 Ctm PH7 Ctm PH5 Ctm FREQ Ctm PH15 Ctm PH3 Ctm PH9 Set Timer2 Value SHE 1110 1000 XXXO Enable HEF6 Enable HEF5 Enable HEF4 Enable HEF3 Enable HEF2 Enable HEF 1 126 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual SIE X 1110 1001 OXXX XXXX X6 Enable IEF6 RFC X5 Enable IEF5 KEY S X4 Enable IEF4 TMR2 X3 Enable IEF3 PDV X2 Enable IEF2 INT X1 Enable IEF1 TMR1 X0 Enable IEFO C DPT PLC X 1110 101X OXXX XXXX X8 Reset PH15 11 X6 0 Reset HRF6 0 SRF X 1110 1100 00XX XXXX 5 Enable Cx Control X4 Enable TM2 Control X3 Enable Counter ENX X2 Enable RH Output EHM X1 Enable RT Output ETP XO Enable RR Output ERR SRE X 1110 1101 XOXX X000 X7 Enable SRF7 key s X5 Enable SRF5S INT X4 Enable SRF4 C port X3 Enable SRF3 D port FAST 1110 1110 0000 0000 SCLK High Speed Clock SLOW 1110 1110 1000 0000 SCLK Low Speed Clock CPHL X 1110 1111 XXXX PC 1 lt f
125. represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC D 0H FH AC Ry lt Ry D D represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH 5 4 LOAD STORE INSTRUCTIONS STA Rx function description STA HL function Rx lt AC The content of AC is loaded to data memory specified by Rx R HL lt AC 103 tenx technology inc Rev 1 0 2004 2 2 description STA HL Function Description LDS function description LDA Rx function description LDA HL function description LDA HL Function Description LDH Rx HL function description LDH Rx HL function description LDL Rx HL function description TM87P08 User s Manual The content of AC is loaded to data memory specified by HL HL AC HL HL 1 The content of AC is loaded to the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AC Rx lt D Immediate data D is loaded to the AC and data memory specified by Rx D 0H FH AC lt Rx The content of Rx is loaded to AC lt R HL The content of data memory specified by HL is loaded to AC AC lt Q HL HL HL 1 The content specified by HL is
126. rom content of data memory specified by HL the result is loaded to AC and data memory specified by HL Carry flag CF will be affected AC HL HL AC B CF HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC and the data memory HL The content of 95 tenx technology inc Rev 1 0 2004 2 2 ADD Rx Function Description ADD HL Function Description ADD HL Function Description ADD Rx Function Description ADD HL Function Description ADD HL Function Description SUB Rx TM87P08 User s Manual the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC The carry flag CF will be affected AC lt HL AC Binary adds the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory The carry flag CF will be affected AC lt HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected AC Rx Rx AC Binary adds th
127. ruction to turn off the LCD the program can still execute LCT LCB LCP and LCD instructions to update the data in the latch circuitry The new content will be outputted to the LCD while the display is being turned on again In the stop state all COM and SEG outputs of LCD drivers will automatically switch to the GND state to avoid DC voltage bias on the LCD panel 80 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 4 3 2 Relative Instructions 1 LCT Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA to the LCD latch specified by Lz 2 LCB Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA to the LCD latch specified by Lz DBUSA to DBUSH are all set to 0 when the input data of the data decoder is O 3 LCD Lz HL Transfers the table ROM data specified by HL directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown in table 2 32 4 LCP Lz Ry The data in the RAM and accumulator AC are transferred directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown below 5 LCT Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers DBUSA H to the LCD latch specified by Lz 6 LCB Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to the LCD latch spec
128. s the contents of HL and AC the result is loaded to AC The result will not affect the carry flag CF HL indicates an index address of data memory AC lt HL AC HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction The result will not affect the carry flag CF HL indicates an index address of data memory AC Rx Rx AC Binary adds the contents of Rx and AC the result is loaded to AC and data memory Rx The result will not affect the carry flag CF AC HL HL AC Binary adds the contents of QHL and AC the result is loaded to AC and the data memory QHL The result will not affect the carry flag CF HL indicates an index address of data memory AC HL HL AC HL 1 Binary adds the contents of QHL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction The result will not affect the carry flag CF HL indicates an index address of data memory AC lt Rx amp AC Binary ANDs the contents of Rx and AC the result is loaded to AC AC HL 8 AC Binary ANDs the contents of HL and AC the result is loaded to AC 98 tenx technology inc Rev 1 0 2004 2 2 AND HL Function Description AND
129. s to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 64 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual bitO bitO IOD1 bit1 bit1 IOD2 Initial clear 9 5 SCF1 SPD 8 Data IOD Pull Bus low option bit2 bit2 IOD3 bit3 bit3 IOD4 Control 2 IPD OPD This figure shows the organization of IOD port 65 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 5 4 1 Chattering Prevention Function and Halt Release The port IOD is capable of preventing high low chattering of the switch signal applied on the IOD1 to IOD4 pins Chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing the SCC instruction the default selection is PH10 after the reset cycle When the pins of the IOD port are set as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry SPD 1 Edge detect Interrupt request SPD 2 SPD 4 SPD 8 IOD1 IOD2 IOD3 IOD4 SCF3 HALT released request chattering PH10 chattering e prevention clcok PLC 1 Interrupt accept 2 3 i intruction SCA intruction This figure shows the organization of chattering prevention circuitry Note
130. segment IOA1 4 Output port A can use software to define internal pull low Resistor This port is muxed with SEG24 27 and set by option Output port B can use software to define internal pull low Resistor This port is muxed with SEG28 31 BZB BZ and set by option Input Output port C can use software to define internal pull low low level hold IOC1 4 I O Resistor and Chattering clock to reduce input bounce This port is muxed with 1 4 and set by option and Chattering clock to reduce input bounce 1 input pin and 3 output pins for RFC application This port is muxed with SEG24 27 IOA1 4 and set by option RR RT RH ALM Output port for alarm frequency or melody generator This port is muxed with DC30 SEG31 IOB3 4 and set by option KI1 4 Keyboard scanning input port This port is muxed with SEG32 35 IOC1 4 and set by option GND Negative supply voltage Connect for Serial Program Read Mode VPP P Above 11 5V is connected to VPP for Program Mode Serial Program Read Connect Pins VPP VDD2 VDD3 GND RESET INT 7 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 1 7 CHARACTERIZATION ABSOLOUTE MAXIMUM RATINGS GND OV Name Symbol Range Unit VDD1 0 3 to 5 5 V VDD2 0 3 to 5 5 V Maximum Supply Voltage VDD3 031085 VPP 0 3 to 13 5 V Maximum Input Voltage Vin 0 3 to VDD1 2 0 3 V
131. stems that can be selected by mask option in TM87P08 they 1 2 bias 1 4 duty 1 2 bias 1 8 duty e 1 3 bias 1 4 duty 1 3 bias 1 8 duty All of these lighting systems are combined with 2 kinds of mask options one is LCD DUTY CYCLE and the other is BIAS MASK OPTION table LCD duty cycle option Mask Option Name Selected Item LCD DUTY CYCLE 4 1 4 DUTY LCD DUTY CYCLE 8 1 8 DUTY LCD bias option Mask Option name Selected item BIAS 2 1 2 BIAS BIAS 3 1 3 BIAS The frame frequency for each lighting system is shown below these frequencies can be selected by mask option All of the LCD frame frequencies in the following tables are based on the clock source frequency of the pre divider PHO is 32768Hz 76 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The LCD alternating frequency in 1 4 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64Hz The LCD alternating frequency in 1 8 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 32Hz LCD frame frequency 2 TYPICAL e4Hz LCD frame frequency 2 FAST 128Hz The following table shows the relationship between the LCD lighting system and the maximum number of driving
132. ster STACK are returned sequentially to the program counter PC during execution of the RTS instruction Once the RTS instruction causes the stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter 23 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual The following figure shows the diagram of the stack Stack pointer CALL instruction Interrupt accepted lt q RTS NS STACK ring with first in last out function 2 7 DATA MEMORY RAM The static RAM is organized with 256 addresses x 4 bits and is used to store data The data memory may be accessed using two methods 1 Direct addressing mode The address of the data memory is specified by the instruction and the addressing range is from OOH to 7FH 2 Index addressing mode The index address register HL specifies the address of the data memory and all address space from 00H to can be accessed The 8 specified addresses 70H to 77H in the direct addressing memory are also used as 8 working registers The function of working register will be described in detail in section 2 8 00H DATA RAM Direct Address Access 70H 7 77H Working Register 80H Index Address Access FFH k 4 Bits J This figure shows the Data Memory RAM and Working Register Organization 24 tenx technology inc Rev 1 0 2004 2 2 TM87
133. t Rx AC CF ADD HL 0010 0101 1000 0000 AC QHL lt QHL AC CF ADD BHL 0010 0101 1100 0000 AC QHL lt QHL AC CF HL lt HL t 1 SUB Rx 0010 0110 XXXX AC Rx ACB 1 CF SUB HL 0010 0110 1000 0000 AC lt HL ACB 1 CF SUB 0010 0110 1100 0000 IAC lt HL ACB 1 HL lt HL 1 SUB Rx 0010 0111 XXXX Rx ACB 1 CF SUB HL 0010 0111 1000 0000 AC HL lt HL ACB 1 CF SUB HL 0010 0111 1100 0000 AC HL lt HL ACB 1 CF HL lt HL 1 ADN Rx 0010 1000 AC Rx AC ADN HL 0010 1000 1000 0000 AC lt HL AC ADN HL_ 0010 1000 1100 0000 lt QHL AC HL lt HL 1 ADN Rx 0010 1001 XXXX AC Rx lt Rx AC ADN HL 0010 1001 1000 0000 AC HL lt HL AC ADN BHL 10010 1001 1100 0000 lt HL HL lt HL 1 AND 0010 1010 XXXX AC Rx AND AC AND HL 4 0010 1010 1000 0000 AC HL AND AC AND HL 10010 1010 1100 0000 AC HL AND AC HL 1 122 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual AND Rx 0010 1011 XXXX AC Rx Rx AND AC AND HL 0010 1011 1000 0000 AC QHL lt HL AND AC AND HL 0010 1011 1100 0000 AC QHL lt HL AND AC HL lt HL 1 EOR Rx 0010 1100 OXXX XXXX AC lt Rx
134. t value 0 error 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PHn The nth stage output of the predivider n 5 7 9 11 13 8 When the TMR2 clock is FREQ TMR2 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 13 2 RE LOAD OPERATION TMR2 also provides the re load function is the same as TMR1 The instruction SF2 1 enables the re load function the instruction RF2 1 disables it 2 13 3 TIMER 2 TMR2 IN RESISTOR TO FREQUENCY CONVERTER RFC 31 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual TMR2 also controlled the operation of RFC function TMR2 will set TENX flag to 1 to enable the RFC counter once the TMR2 underflows the TENX flag will be reset to O automatically In this case Timer 2 could set an accurate time period without setting a value error like the other operations of TMR1 and TMR2 Refer to 2 16 for detailed information on controlling the RFC counter The following figure shows the operating timing of TMR 2 in RFC mode Clock source of ME SEM P NE M Timer 2 TM2X X Content of 3Fh 1 1 N 1 1 N 2 1 0 3Fh Timer2 pe gt 5 BE TMR2 also provides the re load function when controlled the RFC function The SF2 1h instruction enables the re load function and the DED flag should be set to 1 by SF2 2h instruction Once DED flag had been set to 1 TENX flag will not be cleared to 0 while TMR2 un
135. the content of AC to binary format and then restores to AC and the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt AC lt 9 no change no change lt lt 0 lt AC lt 3 DAS Function Description DAS Rx function description CF 1 AC BCD AC Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC Rx lt BCD AC Converts the content of AC to decimal format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected 111 tenx technology inc Rev 1 0 2004 2 2 DAS HL Function Description DAS HL Function Description TM87P08 User s Manual AC HL lt BCD AC Converts the content of AC to binary format and then restores to AC and the data memory HL When this instruction is executed the AC must be the result of any subtracted instruction
136. tion Rx AC WDF CSF RFOVF 108 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual description The watchdog flag system clock status overflow flag of RFC counter and low battery detected flag are loaded to data memory specified by Rx and AC The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 The overflow flag of Watchdog timer System clock NA 16 bit counter of enable flag selection flag RFC RFVOF WDF CSF 109 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 5 6 INDEX ADDRESS INSTRUCTIONS MVU Rx Function Description MVH Rx function description MVL Rx function description CPHL X Function Description GU lt Rx Loads content of Rx to the index address buffer QU U3 Rx 3 U2 Rx 2 U1 Rx 1 U0 Rx 0 H lt Rx Loads content of Rx to higher nibble of index address buffer H H3 Rx 3 H2 Rx 2 H1 Rx 1 HO2 RX O L lt Rx Loads content of Rx to lower nibble of index address buffer L L3 Rx 3 L2 Rx 2 L1 Rx 1 LO Rx O If HL X force the next instruction as NOP Compare the content of the index register HL in lower 8 bits h and L with the immediate data X Note In the duration of the comparison of the index address all the interrupt enable flags IEF have to be cleared to avoid malfunction If the compared result is equal the next executed instruction that is behi
137. tion must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin as the carrier for IR remote controller Example SHE 2 Enable timer 1 halt release enable flag TMSX 3Fh Set value for timer 1 is 3Fh and the clock source is PHY SCC 40h Setthe clock source of the frequency generator as BCLK FRQX 2 3 FREQ BCLK 4 2 setting value for the frequency 56 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual generator is and duty cycle is 1 2 ALM 1COh FREQ signal is outputted This instruction must be executed after the FRQ related instructions HALT Wait for the halt release caused by timer 1 Me se quede h tea umaman Halt released ALM 0 Stop the buzzer output 3 5 INPUT OUTPUT PORTS Three I O ports are available in TM87P08 IOA IOB and IOC Each I O port is composed of 4 bits and has the same basic function When the 1 pins are defined as non IO function by mask option the input output function of the pins will be disabled 3 5 1 IOA PORT IOA1 IOA4 pins are MUX with CX SEG24 RR SEG25 RT SEG26 and RH SEG27 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX 2 IOA1 SEG25 IOA2 RR 2 IOA2 SEG26 IOA3 RT 2 IOA3 SEG27 IOA4 RH 2 IOA4 In initial reset cycle the IOA port is set as input mode and each bit of port can be defined as input mode or output mo
138. to AC and data memory specified by Rx AC Rx lt R HL HL 1 The content of the data memory specified by HL is loaded to AC and the data memory specified by Rx The content of the index register HL will be incremented automatically after executing this instruction Rxn ACn Rx n 1 AC n 1 Rx3 0 The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC 0 Rx3 gt Rx2 5 Rx1 gt Rx0 gt Rxn ACn 1 1 Rx3 AC3 lt 1 The Rx content is shifted right and 1 is loaded to the MSB The result is loaded to the AC 1 gt Rx3 5 Rx2 5 Rx1 gt Rx0 gt Rxn ACn Rx n 1 AC n 1 Rx0 ACO lt 0 The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC lt Rx3 lt Rx2 Rx1 Rx0 lt 0 Rxn ACn Rx n 1 AC n 1 Rx0 ACO lt 1 The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC lt Rx3 lt Rx2 lt Rx1 Rx0 lt 1 CF lt Rx 8 Bit3 of the content of Rx is loaded to carry flag CF 92 tenx technology inc Rev 1 0 2004 2 2 MAF Rx function description TM87P08 User s Manual AC Rx lt CF The content of CF is loaded to AC and Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 CF Bit 2 AC 0 zero flag Bit 1 No Use Bit 0 No Use 5 3
139. tput L Voltage Vol3j lol210uA 73 0 2 V Vol4j 101 100 4 0 2 V 10 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 1 8 TYPICAL APPLICATION CIRCUIT This application circuit is simply an example and is not guaranteed to work LCD Panel 3 58MHz d Certe COM1 8 SEG1 23 SEG40 41 9 9 ix 8 2 Crystal 15 XOUT 01u CUP2 RH VDD3 VPP Cons i 2 H VDD1 1 1 010 0 10 an GND 1 1 01 TM87P08 Ji RESET External INT INT 10 Port IOB IOC IOD a Choke amp Buzzer SEG1 16 K1 K4 BZ BZB Key Scaning I Key Matrix 1 3 Bias 1 8Duty 11 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual Chapter 2 TM87P08 Internal System Architecture 2 1 Power Supply TM87P08 could operate at Li and ExtV 2 types supply voltage all of these operating types are defined by mask option The power supply circuitry also generated the necessary voltage level to drive the LCD panel with different bias Shown below are the connection diagrams for 1 2 bias 1 3 bias application 2 1 1 LI BATTERY and ExtV POWER SUPPLY Operating voltage range 2 4V 5 25V For different LCD bias application the connection diagrams are shown below 2 1 1 1
140. utine specified by a fix address in the program memory ROM is called The following table shows the flag and service of each interrupt Table 3 1 Interrupt information port underflow overflow underflow overflow The following figure shows the Interrupt Control Circuit Interrupt 0 Specified signal change at IO C or IOD port Priority control circuit Interrupt 1 Tim er TM underflow Interrupt request signal Specified signal Interrupt 2 change at INT pin Interrupt vector address generator Interrupt 3 Predivider overflow Interrupt 4 TM2 underflow Specified signal enable at Key matrix Scanning Interrupt 5 RFC counter Interrupt 6 overflow Y Interrupt accept signal SIE instruction Initial clear 45 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual 3 1 1 INTERRUPT REQUEST AND SERVICE ADDRESS 3 1 1 1 External interrupt factor The external interrupt factor involves the use of the INT pin IOC ports IOD ports 1 External INT pin interrupt request By using mask option either a rise or fall of the signal at the INT pin can be selected for applying an interrupt If the interrupt enable flag 2 IEF2 is set and the signal on the INT pin change that matches the mask option will issue the HRF2 interrupt
141. uty D 01 1 3 Duty D 10 1 2 Duty D 11 1 1 Duty FRQ D QHL 0001 01DD 0000 0000 FREQ lt T HL FRQX D X 0001 10DD XXXX XXXX FREQ X MVL Rx 0001 1100 OXXX XXXX IDBF0 3 lt MVH Rx 0001 1101 OXXX XXXX IDBF4 7 lt MVU Rx 0001 1110 XXXX IDBF8 11 lt Rx ADC Rx 0010 0000 OXXX AC Rx AC CF CF ADC HL 010 0000 1000 0000 AC lt HL AC CF ADC HL 10010 0000 1100 0000 AC lt HL AC CF HL lt HL t 1 ADC Rx 0010 0001 OXXX XXXX AC Rx lt Rx AC CF CF 121 tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual ADC QHL 10010 0001 1000 00000AC QHL lt HL AC CF CF ADC BHL 10010 0001 1100 0000 AC HL lt HL AC CF CF HL 1 SBC Rx 0010 0010 AC lt CF SBC amp HL 0010 0010 1000 0000 AC lt gHL SBC amp HL 0010 0010 1100 0000 IAC lt HL HL lt HLt 1 SBC Rx 0010 0011 XXXX AC Rx Rx ACB CF CF SBC HL 0010 0011 1000 0000 AC HL lt HL ACB CF SBC HL 0010 0011 1100 0000 AC HL_ lt HL ACB CF CF HL lt HL 1 ADD Rx 0010 0100 XXXX AC Rx AC CF ADD HL 010 0100 1000 0000 AC gHL AC CF ADD HL 00100100 1100 0000 AC gHL AC CF HL lt HLt 1 ADD Rx 0010 0101 XXXX AC Rx l
142. y The range of multi Lz is specified by data Refer to Table 5 2 D 0 3 Mullti LCD latch Lz data decoder lt HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder The range of multi Lz is specified by data Refer to Table 5 2 85 tenx technology inc Rev 1 0 2004 2 2 LCPX D Function Description SPA X function description TM87P08 User s Manual D 0 3 Mullti LCD latch Lz lt HL AC The contents of index RAM specified by HL and the contents of AC are loaded to several LCD latches Lz simultaneously Refer to Table 5 2 The range of multi Lz is specified by data D 0 3 Defines the input output mode of each pin for IOA port and enables disables the pull low device Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each bit of X X3 X2 X1 X0 is shown below 4 1 EnablelOA pulllowR 4 0 Disable IOA pull low R 3 1 OA4asoutputmode X3 0 VE IIOA4 as input mode X2 1 JIOA3asoutputmode X2 0 IOA3 as input mode X1 1 IOOA2asoutputmode X1 0 2 as input mode X0 1 1 X0 0 1 as input mode OPA Rx function description OPASRx D function description IPA Rx function description SPB X function description 1 lt
143. ymb Condition Min Max Unit VDD2 2 4 5 25 Supply Voltage VDD3 24 8 0 V VPP 24 12 5 V VDDstu Voltage 3 58 ceramic resonator Mode 1 8 V Oscillator Sustain VDD 32 768KHz Crystal Mode 1 3 V Voltage S 3 58 ceramic resonator Mode 1 55 V Supply Voltage VDD2 EXT V Li Mode 24 5 25 V H i Input H Voltage Li Battery Mode VDD2 0 7 VDD2 0 7 V Input L Voltage Vil 0 7 0 7 V Input Volt Vih2 SxVDD2 VDD2 V i 888 OSCIN at Li Battery Mode Oi Input L Voltage Vil2 0 0 2xVDD2 Input H Voltage CFIN at Li Battery EXT V Mode 0 8xVDD2 VDD2 V Input L Voltage Vil3 0 0 2xVDD2 V Operating Freq Fopg1 32 768KHz Crystal Mode 32 KHZ Fopg2 External R mode 10 1000 KHZ ELECTRICAL CHARACTERISTICS at 1 VDD2 3 0V Li at 2 VDD2 5 0V Ext V Input Resistance Name Symb Condition Min Typ Max Unit L Level Hold Tr IOC Rilh1 LO ea 10 40 100 KO RIIh2 Vi 0 2VDD2 2 5 20 50 KO IOA B C Pull Down Tr Rmad1 SAND 200 500 1000 KO Rmad2 Vi VDD2 2 100 250 500 KO INT Pull up Tr Pintu 28 200 500 1000 KQ Rintu2 Vi VDD2 2 100 250 500 KO INT Pull Down Tr 200 500 1000 KO Rintd2 Vi GND 2 100 250 500 KO Rres1 Vi GND or VDD2 1 KO RES Pull Down R es eee 2 D 2 Rres2 Vi GND or VDD2 2 5 18 45 KO at 3 VDD2 2 4V Li at 4 VDD2 4 0V Ext V tenx technology inc Rev 1 0 2004 2 2 TM87P08 User s Manual DC Output Characteristics

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