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Curtiss-Wright / Synergy Microsystems VSS4 Manual

1. Memory module connector PM1 amp PM2 locations 250 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Memory module connector PM1 pinouts Appendix A Cables amp Connectors Memory module connectors PM1 amp PM2 Odd Row Function Even Row Function Pin No Pin No 1 Gnd 2 PpcDP0 3 PpcDP1 4 Vec3V 5 PpcDP2 6 PpcDP3 7 Gnd 8 PpcDP4 9 PpcDP5 10 Vec3V 11 PpcDP6 12 PpcDP7 13 Gnd 14 PpcDHO 15 PpcDH1 16 Vec3V 17 PpcDH2 18 PpcDH3 19 Gnd 20 PpcDH4 21 PpcDH5 22 Vec3V 23 PpcDH6 24 PpcDH7 25 Gnd 26 PpcDH8 27 PpcDH9 28 Vec3V 29 PpcDH10 30 PpcDH11 31 Gnd 32 RamClk7 33 RamClk3 34 Vec3V 35 PpcDH12 36 PpcDH13 37 Gnd 38 PpcDH14 39 PpcDH15 40 Vec3V 41 PpcDH16 42 PpcDH17 43 Gnd 44 PpcDH18 45 PpcDH19 46 Vec3V 47 PpcDH20 48 PpcDH21 49 Gnd 50 PpcDH22 51 PpcDH23 52 Vcc3V 53 PpcDH24 54 PpcDH25 55 Gnd 56 PpcDH26 57 PpcDH27 58 Vec3V 59 PpcDH
2. O o O E p lo lo lo SS l CTT TT rCItiItiI augers S _E Ears IMINO f g AATA AANO VSS4 DIP EPROM socket location Boot options The Boot EPROM Enable jumper at JO2L pins 1 amp 2 selects the boot device as follows o Jumper ON boot from DIP EPROM o Jumper OFF boot from Boot Flash Refer to the configuration discussion in Section 2 Getting Started page 23 for ajumper diagram and detailed configuration information To boot from onboard Flash boot from DIP EPROM and program the Flash memory with the reset vector and boot code Once this is done remove the Boot ROM Enable jumper from JO2L pins 1 amp 2 With this jumper removed a power cycle or local reset directs the CPU to look for its reset vector at the base of Boot Flash OxFFFO_OOOO instead of the EPROM 146 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM DIP EPROM use The PowerPC processor fetches its reset vector from the default address OxFFFO_0100 It is possible to use either the DIP EPROM or the soldered down Boot Flash to contain the reset
3. 32 pin DIP JEDEC standard EPROM VSS4 DIP EPROM socket location VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing a monitor PROM Power down and remove the CPU motherboard from the card cage if necessary Power down the system and remove the VSS4 CPU board from the card cage Synergy SBCs contain static sensitive devices Make sure you are properly grounded by putting on a ground strap touching a system ground such as a metallic chassis or case etc before removing and handling the board Use an ESD protected workstation for module removal and installation work Locate the current monitor PROM or DIP socket on the CPU board and remove the current monitor PROM if necessary The figure on the previous page shows the location of the DIP EPROM socket o
4. Pin Function Pin Function 1 Reserved 2 Gnd 3 Gnd 4 CBE7 5 CBE6 6 CBE5 7 CBE4 8 Gnd 9 VI O 5V 10 Par64 11 AD63 12 AD62 13 AD61 14 Gnd 15 Gnd 16 AD60 17 AD59 18 AD58 19 AD57 20 Gnd 21 VI O 5V 22 AD56 23 AD55 24 AD54 25 AD53 26 Gnd 27 Gnd 28 AD52 29 AD51 30 AD50 31 AD49 32 Gnd 33 Gnd 34 AD48 35 AD47 36 AD46 37 AD45 38 Gnd 39 VI O 5V 40 AD44 41 AD43 42 AD42 43 AD41 44 Gnd 45 Gnd 46 AD40 47 AD39 48 AD38 49 AD37 50 Gnd 51 Gnd 52 AD36 53 AD35 54 AD34 55 AD33 56 Gnd 57 VI O 5V 58 AD32 59 Reserved 60 Reserved 61 Reserved 62 Gnd 63 Gnd 64 Reserved V554 User Guide 241 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PMC connectors P11 P15 PMC connector P14 pinouts Pin Function Pin Function 1 UsrlO1 2 UsrlO2 3 UsrlO3 4 UsrlO4 5 UsrlO5 6 UsrlO6 7 UsrlO7 8 UsrlO08 9 UsrlO9 10 UsrlO10 11 UsrlO11 12 UsrlO12 13 UsrlO13 14 UsrlO14 15 Usrl015 16 UsrlO16 17 UsrlO17 18 UsrlO18 19 Usrl019 20 Usrl020 21 UsrlO21 22 UsrlO22 23 UsrlO023 24 UsrlO024 25 Usrl025 26 Usrl026 27 UsrlO27 28 UsrlO28 29 Usrl029 30 Usrl030 31 Usrl031 32 Usrl032 33 Usrl033 34 Usrl034 35 Usrl035 36 Usrl036 37 Usrl037 38 Usrl038 39 Usrl039 40 Usrl040 41
5. Address Register b7 b6 b5 b4 b3 b2 b1 b0 Offset Default R W General Register Set 0x0 RHR XX R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0 THR XX W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1 IER Ww CTS RTS Xoff Sleep modem receive transmit receive 0x00 interrupt interrupt mode status line holding holding interrupt status interrupt register interrupt 0x2 FCR W RCVR RCVR TX TX DMA XMIT RCVR FIFO trigger trigger trigger trigger mode FIFO FIFO enable MSB LSB MSB LSB select reset reset 0x2 ISR R FIFO s FIFO s INT INT INT INT INT INT 0x01 enabled enabled priority priority priority priority priority status bit 4 bit 3 bit 2 bit 1 bit 0 0x3 LCR Ww divisor set set even parity stop bits word word 0x00 latch break parity parity enable length length enable bit 1 bit 0 0x4 MCR W Clock IR Xon Any loop OP2 OP1 RTS DTR 0x00 select enable back INTX enable 0x5 LSR R FIFO trans trans break framing parity overrun receive 0x60 data empty holding interrupt error error error data error empty ready 0x6 MSR R cD RI DSR CTS delta delta delta delta 0xX0 CD RI DSR CTS 0x7 SPR RW bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OxFF Baud Rate Register Set 0x0 DLL XX RW bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1 DLM XX RW bit 15 bit 14 bit 13 b
6. Pin Function Pin Function 1 UsrlO1 2 Usrl02 3 UsrlO3 4 UsrlO4 5 UsrlO5 6 UsrlO6 7 UsrlO7 8 UsrlO8 9 UsrlO9 10 Usrl0O10 11 UsrlO11 12 Usrl012 13 UsrlO13 14 Usrl014 15 Usrl015 16 UsrlO016 17 UsrlO17 18 Usrl018 19 Usrl019 20 Usrl020 21 Usrl021 22 Usrl022 23 Usrl023 24 Usrl024 25 Usrl025 26 Usrl026 27 Usrl027 28 Usrl028 29 Usrl029 30 Usrl030 31 UsrlO31 32 Usrl032 33 Usrl033 34 Usrl034 35 Usrl035 36 Usrl036 37 Usrl037 38 Usrl038 39 Usrl039 40 Usrl040 41 UsrlO41 42 Usrl042 43 Usrl043 44 Usrl044 45 Usrl045 46 Usrl046 47 Usrl047 48 Usrl048 49 Usrl049 50 Usrl050 51 UsrlO51 52 Usrl052 53 Usrl053 54 Usrl054 55 Usrl055 56 UsrlO56 57 Usrl057 58 Usrl058 59 Usrl059 60 UsrlO60 61 UsrlO61 62 Usrl062 63 Usrl063 64 Usrl064 Note 1 The function of pins labeled UsrlOxxx depends on the add on card installed on the board Space is provided in these columns to write the assigned signals if desired VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 293 Appendix D PEX3 PMC expansion option PMC connector P24 PMC 2 amp P34 PMC 3 pinouts Pin Function P24 P34 Pin Function P24 P34 1 UsrlO65 2 UsrlO66 3 UsrlO67 4 UsrlO68 5 UsrlO69 6 UsrlO70 7 UsrlO71 8 UsrlO72 9 U
7. Bit assignments Bit s Function Values b7 b6 Reserved b5 b3 DRAM Chip Size 0x0 2x64Mb chips or 16 MB per bank 0x1 2x128Mb chips or 32 MB per bank 0x2 2x256Mb chips or 64 MB per bank 0x3 Reserved for future use b3 b2 Reserved b1 b0 Number of DRAM banks installed 0x0 No DRAM installed 0x1 1 bank installed 0x2 2 banks installed 0x3 4 banks installed Init code is to read the contents of this register to determine how DRAM if installed is to be set up VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 285 286 Appendix D PEX3 PMC expansion option Using PEX3 memory The PEX3 s Flash and SDRAM each have a PCI window pointed to by the 9080 s PCI Base Address Registers BAR 2 and 3 respectively Upon reset the device reads its configuration EEPROM to get the initial values for all of its registers The PCI windows are then normally assigned to particular addresses by PCI auto initialization code such as that run by SMon the Synergy ROM monitor Software can then determine where the PCI windows have been allocated by issuing a find PCl device or similar system call and reading the device s BARs Once the memory is mapped into PCI space it is accessible to the host processor s and other PCI devices in the system The dual DMA channels of the PCI interfac
8. Pin No Function Pin No Function 1 Gnd 35 Datat2 2 Gnd 36 Data13 3 Gnd 37 Data14 4 Gnd 38 Data15 5 Gnd 39 Parity1 6 Gnd 40 Data0 7 Gnd 41 Datat 8 Gnd 42 Data2 9 Gnd 43 Data3 10 Gnd 44 Data4 11 Gnd 45 Data5 12 Gnd 46 Data6 13 Gnd 47 Data7 14 Gnd 48 Parity0 15 Gnd 49 Gnd 16 Gnd 50 Gnd 17 Term Power 51 Term Power 18 Term Power 52 Term Power 19 53 20 Gnd 54 Gnd 21 Gnd 55 Atn 22 Gnd 56 Gnd 23 Gnd 57 Bsy 24 Gnd 58 Ack 25 Gnd 59 Rst 26 Gnd 60 Msg 27 Gnd 61 Sel 28 Gnd 62 C D 29 Gnd 63 Req 30 Gnd 64 I O 31 Gnd 65 Data8 32 Gnd 66 Data9 33 Gnd 67 Data10 34 Gnd 68 Data11 254 V554 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Fast Ethernet connector P240 Fast Ethernet connector P240 The VSS4 board s Fast Ethernet port connects to the Ethernet 10 100Base T network via the front panel RJ 45 jack as shown in the figure below This chapter lists the pinout for this connector The Ethernet connector provided on the VSS4 may be connected to a hub using a standard straight wired cable or to another Ethernet port using a crossover cable A crossover cable has the Transmit and Receive pairs swapped on one end SBC Front Panel lenas Fast Ethernet Port P240 EEE Fast Ethernet front panel cable connector
9. Pin Function P11 P21 P31 Pin Function P11 P21 P31 1 Gnd 2 12V 3 Gnd 4 IntB IntC IntD 5 IntC IntD IntA 6 IntD IntA IntB 7 8 5V 9 IntA IntB IntC 10 11 Gnd 12 13 Clk 14 Gnd 15 Gnd 16 Gnt 17 Req 18 5V 19 VI O 20 AD31 21 AD28 22 AD27 23 AD25 24 Gnd 25 Gnd 26 CBE3 27 AD22 28 AD21 29 AD19 30 5V 31 VI O 32 AD17 33 Frame 34 Gnd 35 Gnd 36 IRdy 37 DevSel 38 5V 39 Gnd 40 Lock 41 42 43 Par 44 Gnd 45 VI O 46 AD15 47 AD12 48 AD11 49 AD9 50 5V 51 Gnd 52 CBE0 53 AD6 54 AD5 55 AD4 56 Gnd 57 VI O 58 AD3 59 AD2 60 AD1 61 ADO 62 5V 63 Gnd 64 Req64 Note 1 PMC interrupts set in hardware as follows PEX3 PMC 1 Int rotates by 1 e g IntA IntB PEX 3 PMC 2 rotates by 2 e g IntA IntC PEX 3 PMC 3 rotates by 3 e g IntA IntD See page 280 290 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option PMC connector P12 P22 amp P32 pinouts Pin Function P12 P22 P32 Pin Function P12 P22 P32 1 12V 2 Gnd 3 3 3V 4 5 3 3V 6 Gnd 7 Gnd 8 9 10 11 3 3V 12 3 3V 13 Rst 14 Gnd 15 3 3V 16 Gnd 17 18 Gnd 19 AD30 20 AD29 21 Gnd 22 AD26 23 AD24 24 3 3V 25 AD16 A
10. SCSI Hard Disk SCSI CD ROM Drive Drive Single Host initiator Multiple Controllers targets 70 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions SCSI bus Host Host Host Computer Computer Computer SCSI Host Bus SCSI Host Bus SCSI Host Bus Adapter Adapter Adapter U U Il DA SCSI CD ROM Drive Multiple Hosts initiators Single Controller target Host Host Host Computer Computer Computer SCSI Host Bus SCSI Host Bus SCSI Host Bus Adapter Adapter Adapter l Y U lt a gt l SCSI Tape SCSI Hard Disk SCSI CD ROM Drive Drive Drive Multiple Hosts initiators Multiple Controllers targets VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 72 Section 3 Basic Bus Descriptions SCSI bus Electrical connections Electrical connections on the SCSI bus are either single ended or differential Single eended SCSI connections use TTL level signals to drive a cumulative cable length of up to 6 meters 20 feet while differential connections use either EIA 485 high voltage differential or HVD or EIA 644 low voltage differential signaling or LVD to drive a maximum cumulative cable l
11. Note 1 The function of pins labeled UsrlOxxx depends on the add on card installed on the board Space is provided in these columns to write the assigned signals if desired VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 243 Appendix A Cables amp Connectors PMC connectors P11 P15 244 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PO PCI bus connector PO PO PCI bus connector PO The VSS4 s PO PCI connector provides an additional PCI bus connection to the VSS4 s PCI bus for board to board communications and additional expansion of PCI devices Boards with the PO PCI interface option require installation in a VME64x compatible backplane that includes the PO backplane connector VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Because the VME64x PO connector has user defined pins make sure that your backplane s PO connections are compatible with the VSS4 s secondary PCI bus connector before plugging the board in Failure to observe this warning can cause the complete destruction of many on board components and also voids the product warranty 245 Section A Cables amp Connectors PO PCI bus connector PO The drawing belo
12. A byte read of this register indicates board type Revision and ECO level register OxCOOO_O004 RO Bit 7 6 5 4 3 2 1 0 Reset value Bit assignments Bit s Function Values b7 b4 Board Revision 0x0 a 0x1 b 0x2 c J OxF p b3 b0 ECO Level 0x0 none Ox1 1 0x2 2 l OXF 15 A byte read of this register reveals the board revision level higher order nibble and ECO level lower order nibble 284 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PIMC expansion option Flash configuration register OxCOOO_OO08 RO Bit 7 6 5 4 3 2 1 0 0 O xix 0 O x x Reset value Bit assignments Bit s Function Values b7 b6 Reserved b5 b3 Flash ROM Chip Size 0x0 2x16Mb chips or 4 MB per bank 0x1 2x32Mb chips or 8 MB per bank 0x2 2x64Mb chips or 16 MB per bank 0x3 2x128Mb chips or 32 MB per bank b3 b2 Reserved b1 b0 Number of Flash ROM banks installed 0x0 No Flash installed 0x1 1 bank installed 0x2 2 banks installed 0x3 4 banks installed Init code is to read the contents of this register to determine how Flash if installed is to be set up DRAM configuration register OxCOOO_OOOC RO Bit 7 6 5 4 3 2 1 0 00 xix 0 O x x Reset value
13. Processor bus In addition to the 60x bus the 7400 supports a higher performance processor bus called the MPX bus not supported by VSS4 7410 G4 Processor Later revisions of the VSS4 SBC use the 7410 a 2nd generation G4 PowerPC processor In comparison to the 7400 the 7410 has lower power consumption and higher processor speeds Other major differences between the two G4 processors Private memory can use L2 SRAM as direct mapped private memory 2 data bus width can use either a 32 or 64 bit L2 data bus Processor version register PVR data for 7410 0x800C_1xxx PVR data for 7400 0x000C_Oxxx VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC MPC106 PCI bridge memory controller MPC106 PCI bridge memory controller General description The MPC106 PCI bridge memory controller aka Grackle is an integrated high bandwidth high performance interface for PowerPC processor s Secondary L2 cache Memory EDO DRAM SDRAM ROM o PCl bus In addition to interface support the MPC106 provides hardware support for power management functions via register programming ve For detailed information about the Zi MPC106 refer to the Motorola MPC106 User Manual MPC106UM AD This can be obtained by contacting Motorola Literature Distribution Center P O Box 20912 Phoenix AZ 85036 Docu
14. 24 Gnd 3 3V 25 26 Gnd 3 3V 27 28 Gnd 3 3V 29 30 Gnd 3 3V 31 12V 12V Gnd 32 Gnd 5V 5V 5V Notes 1 This row present only with optional wide 160 pin VMEbus P1 amp P2 connectors VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PIMC expansion option VMEbus P2 connector pinouts Pin Row Z Row A Row B Row C Row D 1 UsrlO66 UsrlO2 45V UsrlO1 Usrl065 2 Gnd UsrlO4 Gnd UsrlO3 Usrl067 3 UsrlO69 UsrlO6 UsrlO5 UsrlO68 4 Gnd UsrlO8 UsrlO7 Usrl070 5 UsrlO72 UsrlO10 UsrlO9 UsrlO71 6 Gnd UsrlO12 UsrlO11 Usrl073 7 Usrl075 Usrl014 Usrl013 Usrl074 8 Gnd Usrl016 Usrl015 Usrl076 9 UsrlO78 UsrlO18 UsrlO17 Usrl077 10 Gnd Usrl020 Usrl019 Usrl079 11 Usrl081 Usrl022 Usrl021 Usrl080 12 Gnd Usrl024 Gnd Usrl023 Usrl082 13 Usrl084 Usrl026 45V Usrl025 Usrl083 14 Gnd Usrl028 Usrl027 Usrl085 15 Usrl087 Usrl030 Usrl029 UsrlO86 16 Gnd Usrl032 Usrl031 Usrl088 17 Usrl090 Usrl034 Usrl033 UsrlO89 18 Gnd UsrlO36 Usrl035 Usrl091 19 UsrlO93 Usrl038
15. SCSI Type per STA Bus Speed MBytes Sec Bus Width Bits Device Support Maximum including Host SCSI 1f 5 8 8 Fast SCSIt 10 8 8 Fast Wide SCSI 20 16 16 Ultra SCSIt 20 8 8 Wide Ultra SCSI 40 16 16 Ultra2 SCSI t 40 8 8 Wide Ultra2 SCSI 80 16 16 Ultra3 SCSI or 160 16 16 Ultra160 SCSI Ultra320 SCSI 320 16 16 Ultra640 SCSI 640 16 16 tUse of the word narrow preceding SCSI Ultra SCSI or Ultra2 SCSI is optional SCSI specifications and publications For a complete list of SCSI related specifications draft and approved and other publications refer to the T10 publications list on the web http www t10 org pubs htm Device connections The SCSI bus supports up to eight devices including the host s A SCSI device is either an initiator host or target device that responds to the requests of an initiator to perform an operation The bus protocol accommodates four types of SCSI device configurations as shown in the following figures VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 69 Section 3 Basic Bus Descriptions SCSI bus Host Computer SCSI Host Bus Adapter i lt SCSI BUS J SCSI Hard Disk Drive Single Host initiator Single Controller target Host Computer ll SCSI Host Bus Adapter l J lt SCSI BUS 2 U U SCSI Tape Drive
16. The block diagram below shows the functional blocks that make up the VSS4 VMEbus interface Universe II VME Interface System controller PowerPC Interrupt generation handling CPUs Master Slave Single transfers Master Slave Block transfers BLT32 amp BLT64 Data broadcast slave 4 PowerPC Bus PowerPC to PCI Bridge Mem Ctrlr PCI VME Bridge VME Bus Transceivers waw Block diagram VSS4 VMEbus interface VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 59 60 Section 3 Basic Bus Descriptions VME64 bus VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions PCI bus PCI bus Introduction PCI or Peripheral Component Interconnect is a computer industry specification for interconnecting peripherals with both the system memory and the CPU Though often referred to as a local bus since it accesses the CPU and system memory directly PCI is actually a separate bus isolated from the CPU At the early stages of PCI bus use this processor independence was typically provided by a PCI bridge chip with a 32 bit PCI bus running at 33 MHz for a maximum data transfer rate of 132 MB sec With the PCI 2 1 specification both
17. UPMC3 SPR 941 Exception Handling Registers UPMC4 SPR 942 FPR31 Data Address Save and Restore Sampled Instruction R 272 Register Registers Address Condition DAR SPR 19 SRRO SPR26 Register R 273 USIAR SPR 939 on R274 DSISR SRR1 SPR 27 R 275 DSISR SPR 18 Monitor Control UMMCRO SPR 936 Floating Point Status and Performance Monitor Registers UMMCR1 SPR 940 Control Register Performance Counters Sampled Instruction Monitor Control FPSCR Address aren PMC1 SPR 953 MMCRO_ SPR 952 reakpoin ress IAR PR 955 Mask Register PMC2 SPR 954 SPR 95 MMCR1 SPR 956 PMC3 SPR957 Breakpoint Address MMCR2 SPR 944 UBAMR SPR 935 Mask Register PMC4 SPR 958 AltiVec Registers BAMR SPR 951 Vector Save Restore Vector Registers Register VRO Miscellaneous Registers VRSAVE SPR 256 External Address Time Base Decrementer VRI ister iti Register For Writing DEC SPR22 Vector Status and EAR SPR 282 TBL _ TBR 284 Control Register ee TBU TBR 285 VSCR UMMCR2_ SPR 928 Data Address L2 Control Instruction Address Breakpoint Register Register 2 Breakpoint Register Memory Subsystem Registers DABR SPR 1013 L2CR SPR 1017 IABR SPR 1010
18. A rtisan Artisan Technology Group is your source for quality TecmoogyGroup new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED D a gaa tia Contact us 888 88 SOURCE sales artisantg com www artisantg com VMEbus Technology oN A VMEbus Quad G3 G4 PowerPC Single Board Computer for DSP USER GUIDE Revision 4 0 April 29 2003 Og YNERGY MICROSYSTEMS 9605 Scranton Road 3895 N Business Center Drive Suite 700 Suite 100 San Diego CA 92121 1773 Tucson AZ 85705 6909 858 452 0020 858 452 0060 FAX Web www synergymicro com 99 0062 UG VSS4 04 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com WSS4 U
19. Memory Subsystem Control Register 0 Power Thermal Management Registers MSSCRO_ SPR1014 Thermal Assist Registers Instruction Cache Throttling Control Register 1 These MPC7400 specific registers may not be supported THRM1 SPR 1020 by other PowerPC processors THRM2 SPR 1021 2 Optional register defined by the PowerPC architecture 3 These registers are defined by the AltiVec technology THRM3 SPR 1022 ICTC SPR 1019 PowerPC programming model 7400 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC PowerPC architecture Register set The PowerPC architecture defines register to register operations for most computational instructions For example there are no instructions that modify storage directly For a storage operand to be used in a computation that modifies the same or another location the content of storage must be loaded into a register modified and then stored back to the target location The PowerPC programming model includes 32 general purpose registers GPRs 32 floating point registers FPRs special purpose registers SPRs and several miscellaneous registers A PowerPC processor also includes several processor specific registers that are excluded from the PowerPC programming model These registers provide functions unique to the processor and thus ma
20. Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Introduction to Universe Il 188 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Universe II register reference Universe I register reference Overview The Universe II registers are collectively known as the Universe II Control and Status Registers UCSR These registers occupy 4KBytes of internal memory This space is divided into three logical groups PCI Configuration Space PCICS o Universe Il Device Specific Registers UDSR VMEbus Control and Status Registers VCSR X The register access mechanism depends on whether the register space is accessed from the PCI bus or the VMEbus This chapter provides a reference overview of the Universe II registers Refer to Tundra Semiconductor s Universe II User Manual and or other supporting documentation for detailed information Register access Below is a brief description of Universe II register access Universe Il base address The operating system PCI discovery routines dynamically set up the Universe II base address by writing to the appropriate registers in PCI configuration address space VSS4 User Guide 189 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 190 Section 7 PCI VME64 Bridge U
21. Section 3 Basic Bus Descriptions PCI bus Devices are detected by reading the Vendor and Device IDs in all possible device locations via IDSEL reads from PCI Configuration Data space If a location is empty the read returns all 1s OxFFFFFFFF and the system goes on to read the next location A valid Vendor and Device ID results in the system narrowing down the capabilities by reading additional device configuration data If a device indicates a multifunction device such as the Symbios 53C885 a read of all locations every 0x100 is done to tally up all the sub functions After all functions are identified the device base address registers BARs and other miscellaneous configuration registers if any are set up per the programming for that type device writes to PCI Configuration Address space To find out just how much of each address space a given BAR is requesting all 1s are written to the register and the result read back The device will return zeros in the don t care address bits effectively specifying the address space required This design implies that all address spaces used are a power of two and are naturally aligned For example when you initialize the Symbios Logic Fast Ethernet device it tells you that it needs 0x100 bytes of space of either PCI I O or PCI Memory The initialization code allocates it space The moment that it allocates space the Fast Ethernet device s control and status registers can be seen at t
22. Usrl0109 31 Usrl0110 Usrl062 Gnd Usrl061 Gnd 32 Gnd Usrl064 5V Usrl063 5VPrecharge Notes 1 Pins in this row connect to the P14 or P15 PMC connector pin indicated in parentheses Space is provided in these columns to write in the assigned signals if desired Refer to the applicable PMC module documentation for P2 pin assignments VSS4 User Guide 235 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors VMEbus connectors P71 amp P2 236 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PMC connectors P11 P15 PMC connectors P117 P75 The PMC connectors provide the connection of an add on PMC PCI mezzanine card card or PMC expansion board for various types of I O options These connectors have the following functions P11 P12 32 64 bit PCI P13 64 bit PCI provided as an option P14 standard PCI I O P15 Synergy proprietary stacking and I O provided as an option Synergy Microsystems has made a few minor changes to the standard PMC connector pinout to support the PEX3 PMC Expansion card These changes are o The JTAG test port is not supported These pins are used for the bus request grant and clock connections to the PEX3 The DSel pin is wired to AD13 on the PMC connector o VI O
23. VME64 Auto System Controller Disable When installed the on board auto system controller function is disabled Section 3 VME64 bus 9 amp 10T Flash Write Protect When installed all Flash Boot Flash User Flash DIP Flash EPROM is protected from writes Section 4 Onboard registers Section 4 Boot Flash ROM DIP EPROM Section 4 User Flash memory VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 25 Section 2 Getting Started Setting up the VSS4 hardware Jumper JO2L functions continued 9 amp 10tt User Defined Slot Number When See text below installed indicates that the slot number has been set by the user installing jumpers in positions 6 10 When not installed the slot number is determined from the geographical address pins on VME64x P1 11 amp 12 t Jumper for GA4 slot number 13 amp 14tt Jumper for GAS slot number See Table Below 15 amp 16 tt Jumper for GA2 slot number For Jumper Settings 17 amp 18 tt Jumper for GA1 slot number 19 amp 20 tt Jumper for GAO slot number 21 amp 22 t Flash Write Protect When installed all Section 4 Onboard registers Flash Boot Flash User Flash DIP Flash Section 4 Boot Flash ROM DIP EPROM is protected from writes EPROM Section 4 User Flash memory Notes t This jumper present on Rev B or lower boards tt This jum
24. 300 P2 VME PEX3 pinout 289 P24 P34 PEX3 pinout 294 P240 pinout 256 P264 pinout 254 P346 pinout 258 PM1 pinout 251 PM2 pinout 252 control mode registers 120 CPU defined 296 CRT defined 297 customer service 230 267 data broadcasting defined 297 DB 25 defined 297 DB 9 defined 297 DCE defined 297 VSS4 User Guide Artisan Technology Group Quality Instrumentation differential defined 297 dimensions board 263 DMA defined 297 DRAM defined 297 RGS3 installation 33 DTE defined 297 dual port defined 297 ECO defined 297 empty slot placement managing 51 Endian defined 298 endian issues 65 EPROM defined 298 EPROM boot enable jumper 146 EPROM type configuration 31 147 Ethernet defined 298 Ethernet interface CSMA CD 80 data transmission 79 Ethernet ID 80 Ethernet network connections 78 Interchange signals 81 LED indicators 82 Fast Ethernet connector P240 255 FIFO defined 298 Flash additional info 151 156 block organization boot Flash 149 block organization User Flash 154 boot ROM 145 booting from 146 User Flash memory 153 write protect jumper PEX3 273 Guaranteed 888 88 SOURCE www artisantg com write protection 25 26 149 156 Flash memory defined 298 floating point defined 298 FPU defined 298 front panel PEX3 layout 272 front panel layout 17 GPS receiver defined 298 hardware
25. Architect remo dels aisssssssdcsossucavesessicssdutcessscesncscestesibateassacosioicepavicisyessqeaitstcavanten E A 86 Register S t ceeseeeeeees 88 Instruction set overview PowerPC G4 processottic iisssisciscsasiicnssecoasssssascssveacvaseccssseseoansasvass Summary of differences 750 vs 7400 Processor 7410 G4 ProCessOl eceesessecessecessecsectseseeseeeeseesseeeseenees oF MPC106 PCI bridge memory controller sssessessecsesstecsssseecsecsesssecnecssessecsesssecsssssecnessesssecnscesecesesosecuseaseensesseesteeaseenees General description csssvisssscasessecessssosvesssssnsestecasvassssessstsevsstaccossstenisestssestcdesustonnsessueadenassabsnsacantssssuevedeniessenstnaanioeansaes PowerPC processor interface Secondary L2 cache interface MeimiOry InteaCes A E A E A PCI bus interface u s Power management functions Programming the MPC106 MPC106 registers Address map5 Configuration registers Power management configuration registers Error handling registers s es need Memory interface registers ssscssecsesssescssecseecseecseesnessetecseecsecessecsucesuceeaecnsessseesueesueecaecarecsusecnseesnsees Processor interface Configuration reQiSters cseesseessecsecseesnessueeseeesseeseeesecenseessessuessueeseeeseeseeeseees Alternate OS Visible parameters registers e Emulation support Configuration registers essecssesscsessecesneeseessecneesees
26. Cables amp Connectors Serial I O cabling Serial l O cabling As described in the previous chapter the VSS4 provides a front panel RJ 50 RJ 69 modular jack for connection of the four serial channels A single 10 conductor modular cable along with Synergy s CRJ4 4 port serial interface adapter breaks out the front panel connector to 4 RJ 50 RJ 69 jacks The external serial devices are connected as required to these jacks The drawing below shows how the CRJ4 4 port serial interface adapter is used in the system VSS4 User Guide 259 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Serial I O cabling VSS4 Serial Interface Jack P346 H a 10 conductor straight thru flat cable with RJ 69 RJ 50 plug on both ends Jack for VSS4 Connection P0 CRJ4 Serial Interface Adapter 7a Serial Port D P5 Serial Port C P4 Serial Port B Serial Port A P3 P2 Using the CRJ4 4 port serial interface adapter 260 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Serial I O cabling 2 4_6_8 10 35 79 PAPI 1 PO P2 P3 P4 P5 connector pin numbering PO to from SBC pin assignments D 5 Func
27. Glossary SDRAM SIMD single ended Slave SMI spurious interrupt SRAM supervisor SysClk SysFail SysRes system controller terminal triple access VSS4 User Guide Synchronous Dynamic Random Access Memory a type of DRAM that operates in step with the CPU clock which allows the processor to perform more instructions over a given time Single Instruction Multiple Data a processor performance enhancement that speeds multimedia applications by letting one microinstruction operate at the same time on multiple data items a method of signaling in which one wire is used per signal referenced to a common Ground signal This is the most cost efficient signaling method for short cable runs See differential a device connected to a bus that responds to commands from a Master System Management Interrupt for PowerPC an asynchronous maskable exception that is signaled to the processor by assertion of the SMI signal On Synergy PowerPC SBCs this interrupt is asserted via the front panel SMI switch an interrupt whose acknowledge cycle received no response Usually caused by late acknowledgement of periodic interrupters such as timers But may be caused by interrupt request that was aborted before being acknowledged Static Random Access Memory a memory storage media that needs no refresh cycle SRAM is faster and of lower density than DRAM supervisor mode a Motorola processor execut
28. PMCR2 Power Management Configuration 0x70 Memory Starting Address 0x80 Memory Starting Address 0x84 Extended Memory Starting Address 0x88 Extended Memory Starting Address 0x8C Memory Ending Address 0x90 Memory Ending Address 0x94 Extended Memory Ending Address 0x98 Extended Memory Ending Address 0x9C Pg Mode Cntr Timer Hil IIH Memory Enable 0xA0 IILL 0xA4 Processor Interface Configuration 1 0xA8 Processor Interface Configuration 2 0xAC Alternate OS Visible Alternate OS Visible ECC Single Bit ECC Single Bit 0xB8 Params 2 Params 1 Trigger Counter 60x Bus Error Status ILLI Error Detection 1 Error Enabling 1 0xC0 PCI Bus Error Status ILLL Error Detection 2 Error Enabling 2 0xC4 60x PCI Error Address 0xC8 Emulation Support Configuration 1 0xE0 Modified Memory Status No Clear 0xE4 Emulation Support Configuration 2 0xE8 Modified Memory Status Clear OxEC Memory Control Configuration 1 OxFO Memory Control Configuration 2 OxF4 Memory Control Configuration 3 OxF8 Memory Control Configuration 4 OxFC Note Bit 1 of the PCI command register when set to a 1 enables MPC106 to respond to accesses to the PCI Memory Address space Power management configuration registers The power management configuration registers PMCRs control power management functions of the MPC106 Register Name Size Address Offset PMCR1 half word 16 bits 0x70 PMCR2 byte 0x72 V554 User Guide 97 Artisan Technology Group Q
29. Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller SYM53C885 registers SYM53C885 Ethernet registers address and descriptions cont Addr Offset R W Description 0xA8 0xA9 R W MII Address or TP_PMD Control 0xAA 0xAB R W MII Write Data 0xAC 0xAD R W MII Read Data OxAE 0xAF R W MII Indicators 0xB0 0xCF R W Reserved 0xD0 0xD1 R W Address Filter 0xD2 0xD3 R W Station Address 0 0xD4 0xD5 R W Station Address 1 0xD6 0xD7 R W Station Address 2 0xD8 0xD9 R W Hash Table 0 0xDA 0xDB R W Hash Table 1 OxDC 0sDD R W Hash Table 2 0xDE 0xDF R W Hash Table 3 0xE0 0xE3 Reserved 0xE4 0xE5 R W PHY Identifier 0 OxE6 0xE7 R W PHY Identifier 1 0xE8 0xEB Reserved 0xEC 0xEF Reserved OxFO R W EE Status OxF1 R W EE Control OxF2 R W EE Word Address OxF3 R W EE Read Data OxF4 R W EE Write Data 0xF5 R W EE Feature Enable 0xF6 0xF7 Reserved 0xF8 0xFB Reserved 0xFC 0xFF Reserved VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 277 Section 8 SCSI Ethernet controller SYM53C885 registers 212 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller Programming notes SY M53C885 Programming n
30. VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions Fast Ethernet interface Ethernet network connections The VSS4 provides a 10Base 100Base TX Ethernet Fast Ethernet port at the front panel This type of Ethernet uses a star topology in which each DTE data terminal equipment is connected to a shared hub through a single 4 pair unshielded twisted pair UTP cable The UTP cable is similar to modular telephone cable For network use however a higher grade or category of cable is typically used For 10Base T Category 3 is the minimum but Category 4 or 5 is more often recommended For 100Base TX no less than Category 5 cable is recommended Cable connections are made to an 8 pin RJ 45 modular jack The maximum distance between DTE and hub is 100 m 328 ft for both 10Base T and 100Base TX The figure below shows a typical 10Base 100Base TX Ethernet single hub network DTEs cay a cay cay J Yo R sE a a HUB 10Base 100Base TX Ethernet single hub network VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions Fast Ethernet interface Data transmission Both clock and NRZ data information is Manchester en
31. VSS4 User Guide 255 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section A Cables amp Connectors Fast Ethernet connector P240 The figure and table below identify the pinout numbers and signals for the VSS4 front panel Fast Ethernet connector P240 The VSS4 s Fast Ethernet port supports 10Base T and 100Base TX The other two variations in the 100Base T standard are not supported 100Base T4 and 100Base FX For a 10Base T Ethernet network use a Category 3 or higher UTP unshielded twisted pair cable to connect the VSS4 to the 10Base T hub For a 100Base TX Ethernet network use a Category 5 UTP or Type 1 STP shielded twisted pair cable to connect the VSS4 board to the Fast Ethernet hub Pre assembled twisted pair Ethernet cables in a variety of lengths and colors are available from various electronic and computer supply houses i357 Ethernet 10 100Base T connector pin numbering Ethernet 10 100Base T port P240 pin assignments D 5 Function Transmit Data Transmit Data Receive Data Shield Shield Receive Data Shield Shield oN oA IN N 256 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Asynchronous serial connector P346 Asynchronous serial connector P346
32. in the month are made automatically These registers are not the actual clock counters but BiPort read write static RAM memory locations The M48T201Y includes a clock control circuit that once a second dumps the counters into the BiPort RAM Clock operations Updates to the Timekeeper registers should be temporarily suspended before clock data is read to prevent reading of data in transition Because the BiPort Timekeeper cells in the RAM array are only data registers and not the actual counters updating the registers can be suspended without disturbing the clock itself Updating the data registers is suspended when a 1 is written into the Read bit the seventh most significant bit in the Control register As long as a 1 remains in that position data register updates are suspended After the Read bit is set the registers reflect the count i e the day date and time that were current at the moment the Read command was issued All of the Timekeeper registers are updated simultaneously The Read command will not interrupt an update in progress Registers are again updated in a normal fashion within a second after the Read bit is reset to a 0 Setting the clock The eighth bit of the Control register is the Write bit Setting the Write bit to a 1 like the Read bit suspends updates to the Timekeeper registers The user can then load them with the correct day date and time data in 24 hour BCD format Resetting the Write bit to a O
33. pSOS OxFFE9_F500 OxFFE9_F7FF 768B unassigned OxFFE9_F800 OxFFE9 FCFF 1 25KB SMon OxFFE9_FDO00 OxFFE9_FFCF 720B unassigned OxFFE9_FFDO 0xFFE9_FFEF 32B Reserved factory testing Note 1 Board s 7 digit serial no is encoded as a three byte value leading 1 in board serial number ignored OxFFE9_E778 single processor or CPU X and OxFFE9_E774 CPU Y These three bytes are part of the 6 byte 12 digit Ethernet ID also called Physical Address that uniquely identifies the board s Ethernet node s Refer to the Ethernet ID discussion in Section 3 page 80 for more information about the Ethernet ID Battery The VSS4 s NVRAM Clock battery is a lithium button type that is soldered onto the board Should the battery need replacing the board must be returned to the factory for a new battery to be installed Contact Customer Service for details VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM Boot Flash ROM DIP EPROM The VSS4 board can boot from DIP EPROM or Boot Flash ROM The VSS4 comes with one 32 pin socket 6 inches wide at UE10 This socket accepts one of the following types of JEDEC standard byte wide DIP EPROM Flash memoriest 27C010 27C020 27C040 28F020 29C040 1 Mbit DIP EPROM 128 KB 2 Mbit DIP EPROM 256 KB 4 Mbit DIP EPROM 512
34. slave interface 263 connectors on board pinout 233 defined 303 overview 57 SysReset 161 VME64 57 VSS4 implementation 58 voltages 15 263 VSS4 block diagram 6 dimensions 263 minimum system requirements 13 operating environment 264 power requirements 263 repair 230 revision levels 267 rework upgrades 267 VMEbus compliance 263 voltages 15 warranty 227 230 weight 263 warranty 227 230 watchdog defined 303 watchdog timer 162 weight 263 window size defined 303 word defined 303 Write posting to ROM Space 102 WWV defined 303 Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for quality TecmoogyGroup new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manu
35. 131 SIMD defined 302 single ended defined 302 slave defined 302 slave image Universe Il 193 194 slot location 51 slot number manual settings 26 SMI 19 defined 302 sockets UE10 145 soft reset 163 software readable switch see switches ID switch specifications dimensions 263 environmental 264 power requirements 263 weight 263 spurious interrupt defined 302 SRAM defined 302 SRAM 128K x 8 143 ST16C654 131 registers 131 start up vectors 147 status registers 118 supervisor defined 302 309 Guaranteed 888 88 SOURCE www artisantg com Index switches ID switch software readable 18 RESET toggle 19 SYM53C885 203 general description 203 registers 205 SysClk defined 302 SysFail defined 302 SysRes defined 302 system controller defined 302 system requirements 13 temperature requirements 264 terminal defined 302 Type 0 PCI configuration 108 222 Type 1 PCI configuration 222 U2SPEC register Universe II adjustable VME timing parameters 196 register bit assignments 197 UART defined 303 Universe II base address 189 registers access 189 map 190 overview 189 slave image programming note 199 U2SPEC 195 user configuration jumpers JO2L 24 VME 6U 263 VSS4 User Guide Artisan Technology Group Quality Instrumentation VMEbus compliance 263 interrupt handler 263 interrupter 263 master interface 263
36. 27Cxxx EPROM 486 5 s 7 2 5 8 183 aHa i 28F020 Flash write enabled amp g M 7 of 2 Ta ui 28F020 Flash write prot 688 ac P Ef 140 5 2 29C040 Flash ssy si 7 CH 100 c Boot Flash 182 3 jo ol4 2 write enabled 5 e oje L 7 G8 doo 2 8 Boot Flash None f a ol4 write protected 1 amp 2 5 jo ofe 7 E ole PEEN oO 9 DIP EPROM Boot Flash z Configuration 0 Jumpers J902 0 li o ES e i 99 0130b s ONOOONOONOOONNONNOONNANII al DIP EPROM Boot Flash configuration jumpers J902 Boot Flash use Boot Flash memory is made up of 1 ea 8 bit Flash memory chip with 1 MB total space Boot Flash device Onboard Flash size Manufacturer Part Number Organization 1 MB Intel 28F008SA 1 MB x8 The 1 MB space provided by this device is split in half in two different memory locations if the board is configured to boot from DIP EPROM If the board is configured to boot from Flash the 1 MB space is contiguous See table below 148 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM Boot Flash memory address location Address Data width Description OxFFE0_0000 OxFFE7_FFFF D8 D64 Boot Flash lowe
37. 888 88 SOURCE www artisantg com J Basic Bus Descriptions This section provides basic background information about the various buses interfaces used in the VSS4 board PowerPC bus o ME64 bus PCI bus o SCSI bus Fast Ethernet interface VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 53 54 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions PowerPC bus PowerPC bus The system communicates with the PowerPC processor s through the MPC106 Grackle PCI Bridge Memory controller The Grackle connects all memory front panel switches LEDs serial ports RTC NVRAM User Flash and mailboxes to the PowerPC bus Moreover the Grackle interfaces the PowerPC bus to the SBC s local PCI bus The PowerPC processor uses separate address and data buses plus various control and status signals for performing reads and writes The address bus is 32 bits wide and the data bus is 64 bits wide For memory accesses the address and data buses are independent to support pipelining and split transactions The bus interface is synchronous with all inputs sampled and all outputs driven from the rising edge of the bus clock The bus runs at 66 MHz The PowerPC chip s internal multiplier boosts this frequency to its rated speed The multiplier ratio is c
38. A B C amp D RJ 50 Ru 69 Jack Teves Fast Ethernet RJ 45 Jack yousauyiy PMC Module Front Panel Cutout Filler Panel 99 0149 VSS4 User Guide VSS4 front panel Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 17 18 Section 2 Getting Started Front panel 8 bit user switch The eight position switch on the front panel of the VSS4 provides an 8 bit software readable switch Readable switches can be very useful in target applications where applications programs can read the switch to discover what their function should be the nature of their peripherals etc The CPU reads the switch setting by performing a byte wide read from the 8 bit User Switch register at memory location OxFFEF_FD00 The figure below shows the register bits corresponding to each of the eight switch positions A Bit 0 UP i with board Bit 1 in card cage Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 T Bit 7 Ell Position switch gt Push left S eWied buch right for Logic 0 for Logic 1 91 0011 8 bit user switch polarity Numbering may appear on the switch component itself that conflicts with the numbering shown above Ignore all numbering schemes except what is shown above and on the Quick Reference Card VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www arti
39. Bit 7 6 5 4 3 2 1 0 0 0 0 1 Reset value Bit assignments Bit s Function Values b7 b4 Board Family 0 VGM Series 1 VSS Series 2 KGM Series 3 VGR Series b3 b0 Reserved A byte read of this register reveals the board s special features if any and the board family to which it belongs VSS4 User Guide 115 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 116 Section 4 Programming the PowerPC Onboard registers L2 cache register OxFFEF_FE30 RO Bt7 6 5 4 3 2 1 0 00 0 00000 Reset value Bit assignments Bit s Function Values b7 b2 Reserved b1 b0 L2 Clock Ratio CPU core to L2 frequency 0 1 1 0 divider 1 1 1 5 2 1 2 0 3 Reserved This read only register returns the CPU s L2 clock ratio based on the relative clock speed of the processor and L2 SRAM parts that are installed on the board This value must then be programmed into the CPU s L2 cache control registers for the L2 cache to function properly Memory register OxFFEF_FE38 RO Bt7 6 5 4 3 2 1 0 Reset value Bit assignments Bit s b7 b6 Values 0 SDRAM 15nS CL 2 Flow Thru 1 SDRAM 15nS CL 2 Registered 2 reserved 3 reserved 0 8MB 1 16 MB 2 32 MB 3 64MB 4 128 MB 0 no me
40. Completion queue 750 has 6 entry completion queue vs 7400 s 8 entry completion queue G4 s extra completion queue entries reduce the opportunity for bottlenecks from the G4 s additional execution units Floating point 750 has 4 cycle latency for double precision floating point multiply and 3 cycle latency for all other floating point add and multiply 7400 has 3 cycle latency for all floating point add and multiply As a result the 7400 has equal latency for double precision and single precision operations AltiVec 7400 has special vector execution units to implement the AltiVec instruction set which speeds high bandwidth applications via parallel processing SIMD Memory subsystem 7400 improves data flow with increased queue sizes and queue additions L1 cache block allocation policy 750 has allocate on miss policy 7400 has allocate on reload policy 7400 s block allocation occurs in parallel with reload which uses the cache more efficiently 5 cycles for 7400 vs 6 cycles for 750 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 91 92 Section 4 Programming the PowerPC PowerPC architecture 2 cache 750 supports 1 MB max L2 cache 7400 supports 2 MB max L2 cache 7400 has fewer sectors per tag than the 750 allowing for more efficient caching Moreover the L2 cache reload policy was changed in the 7400 to improve performance
41. DIN 41612 connectors an on board timer that can automatically reset the board if not accessed on a regular basis Used to reset the board in response to a software loop and or malfunction or a CPU halt the range of contiguous addresses that the board responds to is called the window The number of addresses in the window is called the window size The board will respond to addresses from base to baset window size typically a unit of data 16 bits in length In the PowerPC environment however a word is 32 bits while a half word is 16 bits and a double word is 64 bits call letters for the National Bureau of Standards radio station in Ft Collins Colorado WWV broadcasts technical services including timing signals audio frequencies and radio propagation disturbance warnings at the 2 5 5 10 15 and 25 MHz carrier bands Canada provides similar services on CHU Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 303 Glossary 304 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Index us defined 100BASE T defined 10BASE T defined 299 295 295 21554 PCI PCI bridge configuration 221 general description 217 register overview 219 27C010 29 145 27C020 29 145 27C040 29 145 28F020 29 145 29C040 29 145 address map PEX3 280 address map VSS4 109 AM co
42. DMA Byte Counter 0x27 R W DCMD DMA Command 0x28 0x2B R W DNAD DMA Next Address For Data 0x2C 0x2F R W DSP DMA Scripts Pointer VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 207 Section 8 SCSI Ethernet controller SYM53C885 registers SYM53C885 SCSI registers address and descriptions cont Addr Offset R W Label Description 0x30 0x33 R W DSPS DMA Scripts Pointer Save 0x34 0x37 R W SCRATCHA General Purpose Scratch Pad A 0x38 R W DMODE DMA Mode 0x39 R W DIEN DMA Interrupt Enable 0x3A R W SBR Scratch Byte Register 0x3B R W DCNTL DMA Control 0x3C 0x3F R ADDER Sum Output of Internal Adder 0x40 R W SIENO SCSI Interrupt Enable 0 0x41 R W SIEN1 SCSI Interrupt Enable 1 0x42 R SISTO SCSI Interrupt Status 0 0x43 R SIST1 SCSI Interrupt Status 1 0x44 R W SLPAR SCSI Longitudinal Parity 0x45 R SWIDE SCSI Wide Residue Data 0x46 R W MACNTL Memory Access Control 0x47 R W GPCNTL General Purpose Control 0x48 R W STIMEO SCSI Timer 0 0x49 R W STIME1 SCSI Timer 1 0x4A R W RESPIDO Response ID 0 0x4B R W RESPID1 Response ID 1 0x4C R STESTO SCSI Test 0x4D R STEST1 SCSI Test 0x4E R W STEST2 SCSI Test 0x4F R W STEST3 SCSI Test 0x50 0x51 R SIDL SCSI Input Data Latch 0x52 0x53 Reserved 0x54 0x55 R W SODL SCSI Output Data Latch 0x56 0x57 Reserved 0x58 0x59 R
43. E Sate Y_ a ay l s ois og 1 OW Nd Md abpug a Ga ai abpug aINA0d Sone Beng eens a eae En lod 10d Japuedxy Jid jeuondo sng ld INOvY9 INA WaN 13 10 U09 13110 4U09 m 5 abpiig 19d peel o dlduedo owes ayezi ae an an Senoi NSOS WVYAN use WOuda4 WOU yseld MEDPD 42SM 110 8 dia 100g A A A 1 sng ddiamog p M Z A X saat anz s ze ap JEsus s xoq en Kiowan t9 9 Idd t9 9 Idd t9 9 Idd t9 9 Idd ry A k ry aN2 aiNt aiN2 aiNt aIN2 aiNI aiN2 aiNt i ayoed apis ayoed apis ayoed apis ayoed apis Jaued U1 yoeg 71 yoeg 271 yoeg 271 yoeg 271 VSS4 functional block diagram ide ul VSS4 User Gi Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation Section 1 Overview VSS4 features Feature summary The VSS4 provides the following list of powerful features and functions SMP compliant PCI to VME64 bridge with auto system controller rated at 50MB sec OpenPIC compliant any interrupt source can be routed to any CPU at any priority Four 32 bit counters can be read at any time as well as generate interrupts Quad G3 750 PowerPC processors or Quad G4 7410 PowerPC processors Rev C or higher assy Dual versions available 2 MB backside L2 cache 1 MB backside L2 cache Rev B or lower assy 32 512 MB of high performance SDRAM supporting parity 1 MB
44. Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Clock calendar 142 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Non volatile 128K x 8 SRAM Non volatile 128K x 8 SRAM VSS4 boards provide 128K bytes of general use non volatile SRAM The contents of this non volatile SRAM are backed up by a lithium battery that has a service life of about 5 10 years For high altitude applications gt 10 000 ft a capacitor backup option is available to back up the NVRAM in lieu of the regular lithium battery which can leak in a high altitude environment The capacitor backup option provides 12 days typical of backup and raises the board s maximum operating altitude to approximately 39 000 ft wae Configuration data in NVRAM may be zj lost in a capacitor backup equipped board that is stored unused or plugged into an unpowered system in excess of 12 days A reprogramming of the NVRAM is required if this occurs Consult the factory if your capacitor backup equipped board requires storage or inactivity prior to being placed in service Each SRAM location must be accessed on successive byte aligned boundaries in the address range shown in the table below Non volatile SRAM address location Address Data width Description OxFFE8_0000 OxFFE9_FFFO D8
45. ID and configuration information Status registers are read only registers that indicate the status or condition of on board devices or processes Using these registers involves reading the register and interpreting the bit pattern found there Control Mode registers are read write registers that set up the board to perform a given operation or function Using a Control Mode register involves writing a particular hex value to the register s address location A read of the control mode address location gives the current value of the register X The following register descriptions include address location access mode read write RW write only WO or read only RO bit description and a brief summary of what it does The register bit description uses the notation listed below in each bit position to show the register s value after a board reset i e power cycling or system reset VSS4 User Guide 113 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers Register bit description notations for reset value Notation What it means x Unused bit set to 0 for future compatibility Read only bit 1 Set to 1 upon reset 0 Set to 0 upon reset Board information registers VSS4 board information registers include Board type and revision register Special mod and ECO level
46. KB 2 Mbit DIP Flash EPROM 256 KB 4 Mbit DIP Flash EPROM 512 KB VSS4 boards also come with 1 MB of onboard boot Flash memory The figure below shows the location of the DIP EPROM socket on VSS4 boards The Boot Flash ROM itself is under this socket ote VA A DIP EPROM is limited to a maximum size of 512 KB If a larger ROM space is desired use the Boot Flash 1 MB Use a DIP extractor tool OK Industries model EX 2 or equivalent to remove the EPROM from its socket This will avoid damaging the parts underneath and voiding the warranty TT brand EPROMs cannot be used Their requirement for Vcc on unused pins prevents a TI PROM from being used in a general purpose socket EPROMs from other manufacturers such as Intel AMD etc work without problem VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 145 Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM oJ O O G T E m fP Pin 4 y 5 000 e o o 5 e e 32 pin DIP JEDEC p P P standard EPROM Tt Bi LI C O O O
47. Note that any web page address URL is subject to change without notice If the listed web page address in the manual doesn t work do a site search or use your favorite search engine to find the information you need Over time some information may no longer be posted online In this case contact the manufacturer directly using the contact information usually provided in the home page Manual comments Synergy invites your comments or corrections to this manual Email comments corrections to doc synergymicro com VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Getting Started This section provides configuration setup and general information for the VSS4 SBC Minimum system requirements Front panel Setting up the VSS4 hardware o Installing a monitor PROM o Installing the RGS3 memory module o Installing PMC cards o Installing the PO overlay Installation notes VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 17 12 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Minimum system requirements Minimum system requirements The following system components are required to install and test VSS4 boards o 6U VMEbus compatible card cage with VME64x compatible P1 and
48. P2 backplanes installed with PO connector A card cage with forced air cooling is required minimum 400 LFM e recommended 600 LFM Note the recommended airflow rating in zj linear ft min This is the rate of air flowing over the component side of the SBC in its chassis and not the air moved through the chassis CFM rating LFM can be measured using a hand held anemometer such as the Kestrel 1000 Pocket Wind Meter by Nielsen Kellerman www nkelectronics com VSS4 boards feature state of the art high speed transfers across the VME bus that in some cases may approach the maximum VME specifications for transfer speeds To support these transfers the underlying connectors circuitry and printed circuit boards used in the VME card cage must be constructed of high quality materials that are fully compliant with VME specifications For example VME card cages containing 10 layer PCB boards are normally re VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 14 Section 2 Getting Started Minimum system requirements VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com quired to support high speed VME trans fers Older style card cages containing 6 layer boards may have some difficulty conducting these signals without generat ing excessive noise Pin row B of t
49. Programmable Read Only Memory a memory storage media that can be programmed using electrical pulses Once programmed the PROM is read only but does not need power or refresh to maintain the stored data Random Access Memory high speed randomly accessible memory that can be easily read and written to by the processor a circuit that requests Mastership of a bus Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com read madify write RMA RMW ROAK ROR RORA round robin RS 232 RWD SBC SCSI VSS4 User Guide Glossary see RMW Return Merchandise Authorization a number assigned by Synergy for returning defective products Read Modify Write a read memory access followed by a write access performed in such a way that no other access is allowed to the location between the read and write Release On AcKnowledge a type of VMEbus Interrupter module that deasserts its Interrupt Request to the VMEbus during reception of a valid IACK cycle for its interrupt level Release On Request a requester strategy that once granted the bus asserts continued Mastership of the bus even if not currently needed until another requestor requests the bus Opposite of RWD Release On Register Access a type of VMEbus Interrupter module that deasserts its Interrupt Request to the VMEbus during reception of a VME slave access cycle to one of its vendor specific co
50. SIMD single instruction multiple data which speeds high bandwidth applications such as 3 D imaging video processing scientific array processing speech processing etc The vector unit has 32 128 bit registers Depending on data size each register can hold sixteen 8 bit elements eight 16 bit elements or four 32 bit elements The vector unit s ALU can operate on three source vectors and produce a single result vector on each instruction there are 162 AltiVec specific instructions Hence the smaller the data size the more data that can be processed in a single clock cycle Below is a simplified block diagram of PowerPC with AltiVec technology VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC PowerPC architecture Branch Unit INST INST INST Integer Floating Point Vector Aus mus Unit VRs DATA ADDR DATA DATA Memory INST INST ADDR Overview PowerPC with AltiVec technology Though there are numerous differences between G3 and G4 CPUs G4 for example supports a 2 MB L2 cache the G4 is still compatible with the industry standard PowerPC architecture For more detailed information on the PowerPC 74xx and AltiVec refer to Motorola s SPS website http e www motorola com Summary of differences 750 vs 7400 Processor O X X X X
51. Section 4 Programming the PowerPC Address map PCI Memory Space Address Map Address Device address space description Access 0000_0000 OOFF_FFFF RAM 16 MB D8 D64 RW 0000_0000 01FF_FFFF RAM 32 MB D8 D64 RW 0000_0000 03FF_FFFF RAM 64 MB D8 D64 RW 0000_0000 O7FF_FFFF RAM 128 MB D8 D64 RW 0000_0000 OFFF_FFFF RAM 256 MB D8 D64 RW 0000_0000 1FFF_FFFF RAM 512 MB D8 D64 RW 0000_0000 3FFF_FFFF RAM 1GB D8 D64 RW 0000_0080 Mailbox A Write D8 WO Note 2 0000_00A0 Mailbox B Write D8 WO Note 2 0000_00C0 Mailbox C Write D8 WO Note 2 0000_00E0 Mailbox D Write D8 WO Note 2 4000_0000 7FFF_FFFF unused 1 GB 8000_0000 FOFF_FFFF PCI Memory Space 2 GB 48 MB D8 D16 D32 RW FD00_0000 FEFF_FFFF Reserved 32 MB FF00_0000 FF7F_FFFF Reserved 8 MB FFE0_0000 FFE7_FFFF Boot Flash ROM lower 512 KB ROMBoot D8 RO D64 RO Note 1 FFEO_0000 FFE7_FFFF EPROM 512 KB FlashBoot D8 RO D64 RO Note 1 FFE8_ 0000 FFEF_FFFF Reserved FFFO_0000 FFF7_FFFF EPROM 512 KB ROMBoot D8 RO D64 RO Note 1 FFFO_0000 FFFF_FFFF Boot Flash ROM 1 MB FlashBoot D8 RO D64 RO Note 1 FFF8_0000 FFFF_FFFF Boot Flash ROM upper 512 KB ROMBoot D8 RO D64 RO Note 1 FFF8_0000 FFFF_FFFF User Flash Bank 512 KB D8 RO D64 RO Note 3 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 88
52. Section 4 Programming the PowerPC PowerPC architecture PowerPC architecture Introduction The PowerPC processor is a RISC Reduced Instruction Set Computer design of which development can be traced to IBM s introduction of the POWER Performance Optimization With Enhanced RISC architecture of the RISC System 6000 in early 1990 The multi chip approach used by the microprocessor in this system lead to discussions among IBM Apple and Motorola to collaborate on the design and production of a more economical single chip solution Thus was born the PowerPC PC stands for Performance Computing family of RISC processors starting with the 601 chip The PowerPC architecture is scalable so that it can take advantage of new technological breakthroughs The PowerPC architecture defines the following features e Separate registers for integer and floating point operations Integer data uses the general purpose registers GPR while floating point data uses the floating point registers FPR e Instructions for moving integer and floating point data between the registers GPR and FPR and memory e Multiple execution units for parallel processing e Uniform length instructions for easy instruction pipelining and parallel processing e Liberal use of registers up to four during arithmetic operations e An exception handling mechanism IEEE 754 floating point support Single and double precision floating point operations VSS
53. The VSS4 board s four asynchronous serial ports are brought out to a single 10 pin RJ 50 RJ 69 modular front panel connector as shown in the figure below This chapter lists the pinout for this connector See the next chapter in this appendix for serial interface cabling Async Serial I O Ports P346 Serial Ports A B C amp D RS 232 only SBC Front Panel yeas joule Front panel serial I O ports cable connector 257 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Asynchronous serial connector P346 The figure and table identify the pin numbers and signals for the serial port RJ 50 RJ 69 connector on the VSS4 front panel 2 4_6_8 10 35 79 PENT 1 Asynchronous serial connector pin numbering Serial Ports A B C amp D P346 pin assignments y 5 Function Transmit Data Serial Port D Transmit Data Serial Port C Transmit Data Serial Port B Transmit Data Serial Port A Ground Gnd Ground Gnd Receive Data Serial Port A Receive Data Serial Port B Receive Data Serial Port C Receive Data Serial Port D O MWINID a A OJN a Oo 258 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A
54. The capacitor backup option provides 12 days typical of backup and raises the board s maximum operating altitude to approximately 39 000 ft ye For more information about this device yy see the M48T201Y Timekeeper Controller datasheet which is available as a PDF file from the SGS Thomson website http www st com stonline books index htm VSS4 User Guide 137 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Clock calendar Clock address locations The M48T201Y Clock SRAM is an 8 bit peripheral Each M48T201Y memory location must be accessed on successive byte boundaries as illustrated in the table below Clock calendar registers Register Data bits 0 7 Range address b7 b6 b5 b4 b3 b2 bi b0 FFE9_FFFF 10 Years Year Year 00 99 FFEQ_FFFE 0 0 0 10M Month Month 01 12 FFE9_FFFD 0 0 10 Date Day of Month Day of Month 01 31 FFE9_FFFC 0 FT 0 0 0 Day of the Week Day of Week 01 07 FFE9_FFFB 0 0 10 Hours Hours 24 hr Format Hour 00 23 FFE9_FFFA 0 10 Minutes Minutes Minutes 00 59 FFE9_FFF9 ST 10 Seconds Seconds Seconds 00 59 FFE9_FFF8 Ww R S Calibration Control FFE9_FFF7 WDS BMB BMB BMB BMB BMB RB1 RBO Watchdog 4 3 2 1 0 FFE9_FFF6 AFE sawe ABE Al Alarm Month Al Month 01 12 10M FF
55. UsrlO41 42 Usrl042 43 Usrl043 44 Usrl044 45 Usrl045 46 Usrl046 47 UsrlO47 48 Usrl048 49 Usrl049 50 Usrl050 51 UsrlO51 52 Usrl052 53 Usrl053 54 Usrl054 55 Usrl055 56 UsrlO56 57 Usrl057 58 Usrl058 59 Usrl059 60 UsrlO60 61 UsrlO61 62 Usrl062 63 Usrl063 64 Usrl064 Note 1 The function of pins labeled UsrlOxxx depends on the add on card installed on the board Space is provided in these columns to write the assigned signals if desired 242 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PMC connectors P11 P15 PMC connector P15 pinouts Pin Function Pin Function 1 UsrlO65 2 UsrlO66 3 Usrl067 4 Gnd 5 Usrl068 6 Usrl069 7 UsrlO70 8 9 UsrlO71 10 Usrl072 11 Usrl073 12 Gnd 13 UsrlO74 14 UsrlO75 15 UsrlO76 16 17 UsrlO77 18 Usrl078 19 Usrl079 20 Gnd 21 UsrlO80 22 Usrl081 23 Usrl082 24 25 Usrl083 26 Usrl084 27 UsrlO85 28 Gnd 29 UsrlO86 30 Usrl087 31 Usrl088 32 33 Usrl089 34 Usrl090 35 Usrl091 36 Gnd 37 Usrl092 38 Usrl093 39 Usrl094 40 41 Usrl095 42 UsrlO96 43 Usrl097 44 Gnd 45 Usrl098 46 Usrl099 47 Usrl0100 48 49 UsrlO101 50 Usrl0102 51 Usrl0103 52 Gnd 53 Usrl0104 54 Usrl0105 55 UsrlO106 56 57 Usrl0107 58 UsrlO108 59 Usrl0109 60 Gnd 61 Gnd 62 UsrlO110 63 5V 64
56. VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 79 Section 3 Basic Bus Descriptions Fast Ethernet interface Ethernet ID or physical address An Ethernet board is typically designed with a unique Ethernet ID also called physical address in ROM by default any Ethernet packet sent to this ID will be received by the board and passed to the host Packets addressed to other Ethernet IDs will be seen by the board but ignored by default The Ethernet ID is a 12 digit number This number is made up of three bytes of manufacturer s ID followed by another three bytes of a unique identifier number The Ethernet ID is what s contained in the Destination and Source fields of the Ethernet packet For Synergy boards Synergy s 3 byte manufacturer s ID 00 80 F6 is compiled into the Ethernet driver code as a macro The second half of the Ethernet ID is made up of the 7 digit SBC serial number that is stored as 3 bytes of BCD leading 1 in board serial number ignored in these NVRAM locations NVRAM address OxFFE9_E778 single processor CPU X NVRAM address OxFFE9_E774 dual processor CPU Y Synergy s 3 byte manufacturer s ID is combined with the board serial number to produce the Ethernet ID of the board s Ethernet interface For example for a board serial number of 1123456 the Ethernet ID is 00 80 F6 12 34 56 For more informa
57. below al O ring Gasket i E Place o ring gasket in front panel groove f Groove Slot 2 Position PMC card 4 PMC CARDS 3 max PMC CARD i 2 PMC Connectors 1 0 PEX3 EXPANSION BOARD 99 0031 PMC card PEX3 expansion board installation VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 275 276 Appendix D PEX3 PMC expansion option F Rubber o ring gasket in place PMC Card Screw M2 5 thread 12mm pan head slot 8 places Tilt PEX3 PMCassy to PEX3 Expansion Board engage front panel s into SBC al E E cutout s s T Rubber o ring gasket in place PMC Card VMEbus connectors gt Tilt front panel into SBC cutout n SBC PMC is T Hi 1 f L Screw M2 5 thread 6mm E Eject Lever l pan head slot 4 places i Screw M2 5 thread 14mm Screw M2 5 thread pan head slot 4 places 12mm pan head slot 4 places 99 0033 View A A Side View PMC card PEX3 expansion board installation Power down and remove SBC from card cage Power down the system and remove the VSS4 SBC from the card cage Synergy SBCs contain static sensitive devices Make sure you are properly grounded by putting on a ground strap touching a system ground such as a metallic chassis or case
58. bus bandwidth 132 MB sec and 264 MB sec for 32 bit and 64 bit PCI respectively 33 MHz The VSS4 PCI interface is provided by the MPC106 Grackle chip It provides a 33 MHz PCI bus interface that is compliant with the PCI 2 1 specification which is backwards compatible with PCI 2 0 The MPC106 however supports only 32 bit PCI connections Refer to the Grackle chip discussion in Section 4 page 93 for more information PMC cards The PCI Mezzanine Card PMC is an industry standard design that allows PCI based I O cards to be used in VMEbus and CompactPCI motherboard designs The IEEE P1386 CMC Common Mezzanine Card standard defined the available PMC card sizes The table below lists the PMC sizes typically used for VMEbus and CompactPCI systems Typical PMC card size designations and dimensions Designation Width in mm Depth in mm Single 74 0 149 0 Double 149 0 149 0 PMC cards come in 32 and 64 bit designs With 64 bit designs additional connectors are required over the standard 32 bit design The VSS4 boards come with these extra connectors allowing 64 bit PMC cards to be used PCI implementation details The following is a nuts and bolts description of how PCI is implemented in a system from a software standpoint PCI address spaces PCI devices are accessed by the CPU from three address spaces PCI 1 O PCI Memory and PCI Configuration space The PCI I O and PCI VSS4 User Guide Artisa
59. by the PCI Special Interest Group PCI SIG an industry standards organization formed in 1992 to develop and manage the PCI standard PCI specification documents are available for purchase from The PCI SIG PCI SIG Specification Distribution 5440 SW Westgate Drive Suite 217 Portland OR 97221 USA 1 800 433 5177 Domestic Only 425 803 1191 International WWW http www pcisig com Global Engineering Documents Global Engineering Documents 15 Inverness Way East Englewood CO 80112 E Mail global ihs com Phone 1 800 854 7179 FAX 1 303 397 2740 WWW http www global ihs com 66 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions SCSI bus SCSI bus Overview The Small Computer Systems Interface SCSI is a parallel 1 O bus that lets a host computer access various peripheral devices without the need for specialized hardware and software commands for each device The host s SCSI interface acts as a translator between the host and a particular type of peripheral which provides the host with device independence For example one vendor s SCSI disk drive could be replaced with another vendor s SCSI disk drive with no changes to the existing driver code In addition because SCSI is a general purpose interface tape drives hard disks CD ROMs and a variety of other peripherals can quickly be added to the SCSI bus sin
60. code Since the reset address is fixed the address mapping of the two boot devices must be changed to change the boot device Consequently the DIP EPROM appears in one of two address space locations depending on whether the board is configured to boot from DIP EPROM or Boot Flash f the board is configured to boot from EPROM the EPROM is accessed in the range OxFFFO_OOOO OxFFF7_FFFF X If the board is configured to boot from Boot Flash the EPROM is accessed in the range OxFFE0_0000 OxFFE7_FFFF Refer to the Address Map chapter in this section EPROM type configuration Jumper J902 is used to configure the type device used in the DIP EPROM socket Set the jumpers as required for your application as shown in the drawing below See also Installing a monitor PROM in Section 2 page 29 VSS4 User Guide 147 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM Device Jumpers Installed on Pins ido oj2 3 amp 5 AR 4
61. comments or suggestions You can contact our customer service department by writing or calling Synergy Microsystems Inc 9605 Scranton Rd Suite 700 San Diego CA 92121 1773 858 452 0020 858 452 0060 FAX Web http www synergymicro com E mail sales info synergymicro com Reporting problems If you encounter any difficulty with your VSS4 board call Synergy customer service If possible please have the following information available to assist our staff in assessing your problem o VSS4 model number silk screened on solder side of board Serial number marked on solder side of board VSS4 revision level silk screened on the solder side of board o ECO level marked on solder side of board Revision level of the Monitor PROM VSS4 User Guide 229 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 230 Section 10 Warranties amp Service Customer service Return policies and procedures Should it become necessary to return a board to Synergy for repair please take the following steps o 2 Call Synergy Microsystems Inc customer service for a Return Merchandise Authorization RMA number Use this number in all communications regarding the problem boards Provide the following information with all returned items 9209090909 9 S VSS4 model number solder side of the board Serial number solder side of board VSS4 r
62. configuration see configuration humidity specification 264 I O defined 299 lAck defined 298 IBM defined 298 ID switch software readable 18 installation installing the RGS3 memory module 33 minimum system requirements 13 PO overlay 45 PMC 41 slot recommendations 51 installation notes about 9 Hybricon VME64x backplanes 52 slot installation recommendations 51 interrupt controller 167 interrupt handler defined 299 interrupter defined 299 ISP defined 299 JEDEC defined 299 VSS4 User Guide Artisan Technology Group Quality Instrumentation Index jumpers JO2L configuration 23 J902 EPROM 32 JGO2 PEX3 Flash Write Protect 273 jumper functional summary 25 26 L1 cache defined 299 L2 backside cache controller 127 L2 cache defined 299 lamp test 22 LED 0 7 application 21 defined 299 VSS4 status 20 M48T201Y 138 mailbox 129 defined 299 main board VSS4 revisions 267 master defined 299 memory module revisions 268 memory protection defined 299 MMU defined 299 monitor PROM installing 29 MPC106 registers 96 MPC106 general description 93 MPIC 167 MPIC base address 169 ms defined 299 MSB defined 300 multi port defined 300 307 Guaranteed 888 88 SOURCE www artisantg com 308 Index ns defined 300 NVRAM defined 300 NVRAM space allocation 144 object code defined 300 onboard registers 11
63. describes a hard reset or cold start The VSS4 is also capable of a warm start in which only the CPU s is are reset using the MPIC Processor Init register Refer to the Soft reset discussion below VSS4 User Guide 159 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 5 Reset Reset information PCI reset The PCI reset RST line is driven only by a board level reset It is not allowed to be driven by any onboard PCI device On the VSS4 the Universe II PCI reset facility SW_LRST bit in MISC_CTL register is not usable to reset the PCI bus Hard reset sources There are five reset sources each of which produces a hard reset Power monitors Front panel switch o External VME SysReset signal o Watchdog timer o Universe II software SysReset The functional block diagram below shows the VSS4 reset sources VMEbus 2 Hardware SysReset if SysCon H S Reset Generator Peripheral 3 Chips Software Reset oY l i Universell _ Registers SWSYSRST bit 22 MISC_CTL VSS4 hard reset sources 160 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 5 Reset Reset information Power monitor The VSS4 power monitor is based on the Max924 low power comparator The following bus voltages are monitore
64. each network node connects to a common hub Data rate is the same as standard Ethernet 10 Mbps 100Base T similar to 10Base T except that the data rate is 100 Mbps 100Base TX uses two pairs of a Category 5 cable 100Base T4 uses 4 pairs of a Category 3 cable Also called Fast Ethernet A16 D16 specifies a microprocessor bus address and data bus size This value specifies a 16 bit wide address bus and 16 bit wide data bus A16 D32 oe a 16 bit wide address bus and 32 bit wide data us A24 D16 ae a 24 bit wide address bus and 16 bit wide data us A24 D32 ne a 24 bit wide address bus and 32 bit wide data us A32 D16 aia a 32 bit wide address bus and 16 bit wide data us A32 D32 e a 32 bit wide address bus and 32 bit wide data us AM code bits Address Modifier code bits AMO AM5 used by the VMEbus to identify the size of address being expressed A16 A24 A32 A40 or A64 and the type of transfer Address only program data BLT32 BLT64 or IAck being performed VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 295 Glossary banner base address BCD Big Endian bit BLT bridge byte cache line cache memory category 3 category 5 clock calendar collision CPU VSS4 User Guide a message displayed on a CRT screen when a debug monitor or operating system is starting the lowest address in a range of addresses Us
65. functions disabled except RAM refresh This mode not supported by VSS4 boards Programming the MPC106 The Grackle must be programmed in order to Access RAM Access PCI Write to the serial ports Write to the LEDs Write to the board configuration registers o Enable CPU Y Z and W Enable and diagnose certain memory and PCI error conditions VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 95 Section 4 Programming the PowerPC MPC106 PCI bridge memory controller MPC106 registers The following is an overview of the MPC106 registers For in depth register programming information refer to the MPC106 User s Manual by Motorola Address maps The MPC106 supports three address mapping configurations designated address map A address map B and emulation mode address map Address map A conforms to the now obsolete PowerPC Reference Platform Specification PREP Address map B conforms to the Common Hardware Reference Platform Architecture CHRP The emulation mode address map which is not used for VSS4 boards supports software emulation of x86 hardware On reset onboard hardware selects address map B by default After reset the address map can be changed by programming bit 16 in the MPC106 s Processor Interface Configuration register 1 PICR1 VSS4 boards default to address map B for all models Refer to the next ch
66. in each mailbox This provides buffering for multiple near simultaneous messages from many different processes Messages written to the mailbox will be read by the CPU in the order they were received wa For proper operation of the mailbox Yi write function set memory page 0x0000_0000 to non cacheable mode in the MMU Any processor but no other device e g a PMC card is allowed to read a mailbox This restriction is in place to prevent CPU interrupts from being mishandled Reading the mailbox will return the least recently written value and will cause that entry to be removed from the FIFO When all pending mailbox data has been read the interrupt will be cleared The ISR does not need to read all data from the FIFO in fact it s best to have the interrupt routine read one entry from the VSS4 User Guide 129 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 130 Section 4 Programming the PowerPC Mailboxes mailbox and return to program execution If additional data is in the mailbox the interrupt will still be active and the ISR will be entered again automatically Mailbox addresses are listed below Mailbox read write addresses Mailbox Write Read Mailbox A 0x0000_0080 OxFFEF_FC00 Mailbox B 0x0000_00A0 OxFFEF_FC08 Mailbox C 0x0000_00C0 OxFFEF_FC10 Mailbox D 0x0000_00E0 OxFFEF_FC18 The mailbox write may be any data size but only
67. information on the Flash write protect jumper and the Boot ROM enable jumper Flash Window register OxFFEF_FE50 WO Bt 7 6 5 4 3 2 1 0 00 0 00000 Reset value Bit assignments Bit s Function Values b7 User Flash Select 0 Boot Flash 1 User Flash b6 b0 User Flash 512K Bank Select 4MB 0x00 0x87 8 banks 8MB 0x00 0x8F 16 banks 16 MB 0x00 0x9F 32 banks 32 MB 0x00 0xBF 64 banks 64 MB 0x00 OxEF 128 banks This write only register selects which Flash memory User Flash or Boot Flash appears at address range OxFFF8_OOOO OxFFFF_FFFF 512 KB When User Flash is selected b7 1 a particular 512 KB bank or window of that memory is addressed by bits b6 b0 As shown in the diagram above the total available 512 KB banks of Flash memory depend on the amount of User Flash installed on the board With User Flash selected only the lower 512 KB of Boot Flash is accessible With Boot Flash selected the entire 1 MB of Boot Flash is available for use This register returns an undefined value when read Refer to the User Flash memory chapter in this section page 153 for more information VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers PCI error register OxFFEF_FE7O RO Bit 7 6 5 4 3 2 1 0 x x x x xi xi Reset v
68. is connected to 5V This means that all PMC signals are at 5V logic levels VSS4 User Guide 237 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PMC connectors P11 P15 The drawing below shows the locations of the VSS4 PMC connectors The tables that follow list the pin assignments of these connectors Refer to Section 2 for PMC card installation instructions PMC connector P11 P15 locations 238 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PMC connectors P11 P15 PMC connector P11 pinouts Pin Function Pin Function 1 PEX3_Gnt TCK 2 12V 3 Gnd 4 IntA 5 IntB 6 IntC 7 8 5V 9 IntD 10 Reserved 11 Gnd 12 Reserved 13 Clk2b 14 Gnd 15 Gnd 16 Gnt 17 Req 18 5V 19 VI O 5V 20 AD31 21 AD28 22 AD27 23 AD25 24 Gnd 25 Gnd 26 CBE3 27 AD22 28 AD21 29 AD19 30 5V 31 VI O 5V 32 AD17 33 Frame 34 Gnd 35 Gnd 36 IRdy
69. its own SysReset This bit is in the VME64 SysReset onboard register at address OxFFEF_FF38 see page 125 Its default value is 1 board responds to its own SysReset Use this register to program the board to reset only the other VMEbus boards in the system without resetting itself To reset the VMEbus without resetting the VSS4 VSS4 User Guide 161 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 162 Section 5 Reset Reset information 1 Temporarily disable board s VMEbus reset from resetting CPU by writing O to OxFFEF_FF38 bO 2 Start VMEbus reset by setting Universe SysReset bit write 1 Stop VMEbus reset by clearing Universe SysReset bit write 0 4 Re enable board s VMEbus reset to also reset the CPU by writing 1 to OxFFEF_FF38 bO This last step is needed to put the system back into normal operating mode in case it is desired to have other VME boards reset this CPU Allow time for the reset signal to settle add a 0 1 second delay between each of the above operations The VME64 SysReset register is readable which lets the system check its status at anytime by a simple read of the register Watchdog timer For Rev C or higher boards a watchdog timer circuit based on the Dallas Semiconductor DS1232LP low power micromonitor chip provides a means for the hardware to automatically reset the board when it is no longer executing code properly The
70. memory cycles All of these registers are 32 bits wide located on 16 byte boundaries VSS4 User Guide 169 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 6 MPIC Interrupt Controller MPIC registers Overall Address map MPIC Address Offset Register 0x0_0000 Reserved 0x0_1000 Global Registers 0x1_ 0000 Interrupt Source Configuration Registers 0x2_0000 Processor 0 Per Processor Registers 0x2_1000 Processor 1 Per Processor Registers 0x2_2000 Processor 2 Per Processor Registers 0x2_3300 Processor 3 Per Processor Registers 0x3_F000 Reserved Note Add to base address set during PCI configuration The following paragraphs describe the three major MPIC register groups Global registers Interrupt Source Configuration registers Per Processor registers Global registers The table below lists the address map locations of the global registers Address map global registers Address Offset Register Access 0x0_ 1000 Feature Reporting register RO 0x0_1020 Global Configuration register R W 0x0_1080 Vendor Identification register RO 0x0_1090 Processor Init register R W 0x0_1000 0x0_10A0 IPI Vector Priority registers R W 0x0_10E0 Spurious Vector register R W 0x0_10F0 0x0_11F0 Global Timer registers Note Add to base address set during PCI configuration 170 V554 User Guide Artisan Technolog
71. module connector is properly aligned with SBC connector before fully seating module Module connector below engages motherboard s PM1 and PM2 connector Memory Module Standoff securing screws RGS3 32 512 MB red paint on head DO NOT REMOVE 4 places CPU MOTHERBOARD 4 ea securing screws engage memory module standoffs Memory Module RGS3 up to 512MB Ne O Top Eject VME P1 Knob conn CPU Motherboard PM1 and PM2 i connectors i i i l Screw M2 5 thread ie 6mm pan head slot L 4 places Top Processor End of Motherboard VIEW A A Side View Memory Module Installation 99 0028 RGS3 module installation VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing the RGS3 memory module Memory module securing screws To aid in installation the location of the memory module securing screws on the VSS4 is shown in the drawing below SBC solder side Memory module securing screws 99 0029 Location memory module securing screws VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 38 Section 2 Getting Started Installing the RGS3 memory module VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88
72. of DS to DTAck for prefetch read 0 Default 1 Faster Bits marked as Universe Reserved Zi must be set to zero 0 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 197 Section 7 PCI VME64 Bridge Improving VME performance 198 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Programming notes Universe Il Programming notes Universe Il Writing to non existent VME locations Problem The Universe II chip has a problem dealing with non existent VME locations The problem is that the Grackle will not return a machine check exception to the CPU when a VME write fails with a Bus Error Solutions Workaround 1 First perform a read of the location to verify its existence Workaround 2 Program the Universe Il to generate an interrupt upon VME Bus Error and have this interrupt report a fatal error Slave image programming Problem Updating a Universe II slave window while VME traffic is using that window results in data errors even if the register contents are the same VSS4 User Guide 199 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Programming notes Universe Il Solution Avoid programming a slave s image registers while VME is accessin
73. of system boot Flash loadable via a 32 pin JEDEC socket Four RS 232D serial ports up to 115 2Kbps Four 8 bit CPU mailboxes Real time clock calendar 4 digit year 128 KB of NVRAM 4 64 MB 8 bit User Flash memory o Fast 20 SCSI 8 16 bit wide o Fast Ethernet 10Base T 100Base TX 64 bit PMC compliant slot with front panel and rear VME P2 I O access Optional 6U expansion board provides up to 3 additional PMC slots Geographical addressing support Rev C or higher assy Eight status LEDs eight user programmable LEDs an 8 bit software readable switch one CPU reset interrupt switch PO PCI sub bus interface goes beyond VMEbus bandwidth limitations by providing an aggregate 266 MB sec theoretical maximum transfer rate for up to 8 boards 4 pair in a system VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 1 Overview VSS4 features VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 1 Overview Manual conventions Manual conventions Typographical conventions This manual observes the following typographical conventions The term PowerPC Series is used in conjunction with informa tion that applies to ALL models of Synergy s PowerPC based SBCs When differences among models exist specific model numbers are used to describe any s
74. pins 21 amp 22 Rev C or higher and clear bit O of the Flash ROM register at OxFFEF_FE40 VSS4 User Guide 149 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 150 Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM To protect Flash from writes install the Flash Write Protect jumper JO2L pins 9 amp 10 Rev B or lower or pins 21 amp 22 Rev C or higher or set bit O of the Flash ROM register at OxFFEF_FE40 or take both actions if desired Additional write protection of Boot Flash Some VSS4 boards incorporate a retrofit of a Boot Flash Write Protect jumper on J902 pins 1 and 2 Listed below are the affected board revisions and the ECO level incorporating the change VSS4 Rev E with ECO 6 VSS4 Rev F with ECO 5 The new jumper function provides Boot Flash with additional write protection for data security during board startup Refer to the J902 jumper diagram on page 148 o To write protect Boot Flash remove jumper from J902 pins 1 amp 2 With this jumper removed Boot Flash has unconditional write protection regardless of the JO2L jumper and or Flash ROM register OxFFEF_FE40 Flash write enable configuration o To write enable Boot Flash install jumper J902 pins 1 amp 2 and remove jumper if installed from JO2L pins 21 amp 22 On other VSS4 revisions this jumper zj has no function other than to serve as a place to store a jumper whe
75. register Board family and feature register 2 cache register Memory register Secondary PCI slot register o VME64 slot register Board type and revision register OxFFEF_FEOO RO Bit 7 6 5 4 3 2 1 0 0 1 0 0 Reset value Bit assignments Bit s Function Values b7 b4 Board Type 0x1 VGM1 0x2 VGM2 0x4 VSS4 0x5 VGM5 0xC VGMC 0xD VGMD b3 b0 Revision Level Ox0 a 0x1 b Ox2 c J OxF p A byte read of this register reveals the board type higher order nibble and board revision level lower order nibble 114 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers Special mod and ECO level register OxFFEF_FEO8 RO Bit 7 6 5 4 3 2 1 0 Reset value Bit assignments Bit s Function Values b7 b4 Special Mod 0x0 none 0x1 0x2 0x4 0x5 0x6 b3 b0 ECO Level 0x0 none Ox1 1 0x2 2 Hl i 0xF 15 A byte read of this register reveals the special modification code higher order nibble and ECO level of the board lower order nibble Space is provided above to write in the special mod to the code that applies to your board Board family and feature register OxFFEF_FE10 RO
76. register LSI5_BD 1C0 PCI Target Image 5 Translation Offset register LSI5_TO 104 Reserved 1C8 PCI Target Image 6 Control register LSI6_CTL 1CC PCI Target Image 6 Base Address register LSI6_BS 1D0 PCI Target Image 6 Bound Address register LSI6_BD 1D4 PCI Target Image 6 Translation Offset register LSI6_TO 1D8 Reserved 1DC PCI Target Image 7 Control register LSI7_CTL 1E0 PCI Target Image 7 Base Address register LSI7_BS 1E4 PCI Target Image 7 Bound Address register LSI7_BD 1E8 PCI Target Image 7 Translation Offset register LSI7_TO 1EC 1FC Reserved 200 DMA Transfer Control register DCTL 204 DMA Transfer Byte Count register DTBC 208 DMA PCI Bus Address register DLA 20C Reserved 210 DMA VMEbus Address register DVA 214 Reserved 218 DMA Command Packet Pointer register DCPP 21C Reserved 220 DMA General Control and Status register DGCS 224 DMA Linked List Update Enable register D_LLUE 228 2FC Reserved 300 PCI Interrupt Enable register LINT_EN 304 PCI Interrupt Status register LINT_STAT 192 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Universe I register reference Universe Il register map continued Offset Hex Register Name 308 PCI Interrupt Map 0 register LINT_MAPO 30C PCI Interrupt Map 1 register
77. register set 88 processor init register MPIC 172 programming notes about 9 MPC106 101 SYM53C885 213 Universe ll 199 PROM see also monitor PROM EPROM defined 300 RAM defined 300 registers 21554 219 board information 114 control mode 120 PCI configuration PEX3 281 Guaranteed 888 88 SOURCE www artisantg com PEX3 283 board type capability 284 DRAM configuration capability 285 Flash configuration capability 285 revision amp ECO level capability 284 PowerPC register set 88 status 118 VSS4 onboard 113 repair 230 requester defined 300 RESET 19 159 hard reset sources 160 power monitor reset 161 soft reset 163 172 software reset 163 toggle front panel 19 161 VME SysReset 161 rework upgrades 267 RMA 230 defined 301 RMW defined 301 ROAK defined 301 ROR defined 301 round robin defined 301 RS 232 defined 301 RWD defined 301 SBC defined 301 SCSI defined 301 SCSI interface Bus communication control 74 Bus terminations 74 Data transfer options 75 Electrical connections 72 History 67 Overview 67 Physical topology 73 Artisan Technology Group Quality Instrumentation VSS4 User Guide Index termination disable jumper 25 SCSI Ethernet controller interface 201 SDRAM defined 302 serial interface 131 connector 136 257 CRJ4 serial port adapter 136 259 ST16C654 registers
78. resume paying attention to other pending Grackle accesses Bottom line If frequent writes to ROM space are needed intersperse ROM space writes with ROM space reads whether or not you need the data being read It makes the Grackle give fairer access to the onboard memory to the various competing sources of memory access requests VSS4 User Guide 103 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Programming notes MPC106 104 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Address map Address map This chapter provides VSS4 address map information o Overall CHRP address map processor view and PCI master memory and I O view SS4 address map as viewed by the PowerPC processor s VSS4 address map as viewed by PCI devices Additional information on the board s memory spaces follows the board address map listing CHAP address map By default the VSS4 uses a Common Hardware Reference Platform CHRP compliant address map designated Address Map B Alternatively the board can use Address Map A PREP by programming the MPC106 we For detailed information about the Yi MPC106 refer to the Motorola MPC106 User s Manual MPC106UM AD This can be obtained by contacting Motorola Literature Distribution Center
79. s service goal is to return new or refurbished products within 14 days of the receipt of properly rejected boards that were returned in accordance with the requirements stated above and in next chapter Product returns under warranty Once products have been either accepted or the initial product accept reject period has passed products are warranted for the applicable warranty period as described below For information about returning products under warranty see the next chapter on Customer service Warranty periods Synergy Microsystems Inc offers the following warranty periods O 9 9 90 day guarantee and limited warranty All standard off the shelf and non standard custom products are automatically guaranteed for 90 days from the day of delivery 1 year standard limited warranty Customers who complete payment for the product to Synergy within 30 days of delivery receive a free warranty extension for a full year on all products covered by the payment 3 year extended limited warranty If desired Synergy offers an extended 3 year warranty for an additional charge The terms for the extended warranty are identical to those listed above VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 10 Warranties amp Service Customer service Customer service Please contact Synergy Microsystems Inc if you have any questions
80. shunts used are of the smaller 2 mm size and not the larger 100 size commonly found on older SBCs The jumpers are summarized below VSS4 Rev C or higher boards have zj additional jumpers for manual slot number geographical address select Verify that the board has a monitor EPROM and memory mod ule installed o Verify install shunt at JO2L 1 amp 2 to boot from DIP EPROM Install a shunt at JO2L 3 amp 4 to unterminate the SCSI bus Install a shunt at JO2L 5 amp 6 to force VME System Controller Install shunt at JO2L 7 amp 8 to disable Auto System Controller function Rev B or lower boards Install a shunt at JO2L 9 amp 10 for global Flash write protection o Rev C or higher boards Install a shunt at JO2L 9 20 for manual slot number configuration o Rev C or higher boards Install a shunt at JO2L 21 amp 22 for global Flash write protection Some boards have an ECO zj modification to provide extra write protection of Boot Flash See page 150 for more information The drawing below shows the location and pinout of jumper block JO2L VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Setting up the VSS4 hardware Boot ROM Enable Boot Source SCSI Termination Disable System Controller Manual System Controller Auto Flash Write Protect Configuration Jumpers J02L 99 0047a Rev B
81. side of board to remove see PMC card securing screws location drawing above Install PMC card onto SBC refer to drawing below for assembly details a b Place VSS4 assembly face up on a flat surface of an ESD protected workstation If not already on install PMC card s front panel O ring gasket included with PMC card by slipping gasket into groove around front panel Grasp PMC at sides with card front panel towards SBC front panel from rear tilt PMC front panel into SBC front panel cutout and engage front panel O ring gasket with chamfer in SBC panel cutout With PMC front panel in place place card over SBC connectors Ensure both PMC and SBC connectors are aligned then press down over PMC connector area to fully engage SBC connectors Turn VSS4 assembly over Install four 6 mm M2 5 slot head screws item 6 or whatever screw fasteners are supplied with PMC card from rear solder side of VSS4 motherboard Two screws engage the standoffs on the PMC card The other two screws engage the threaded holes in the PMC card front panel See Location PMC card securing screws drawing earlier in this chapter Removal is reverse of installation VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing PMC cards Single PMC installation Required hardware I
82. the PO PCI interrupt signals If it is not desired for the board to see any or all of these interrupts coming elsewhere from the bus use the PO PCI interrupt mask register to VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 123 Section 4 Programming the PowerPC Onboard registers prevent any of these interrupts from being passed on to the board See next PO PCI interrupt mask register OxFFEF_FEGO RW Bit7 6 5 4 3 2 1 0 x x 7 7 7 1 1 1 Reset value Bit assignments Bit s Function Values b7 b6 Reserved b5 P0 PCI System Error Mask 0 interrupt enabled 1 interrupt disabled masked b4 PO PCI Parity Error Mask 0 interrupt enabled 1 interrupt disabled masked b3 PO PCI Interrupt D Mask 0 interrupt enabled 1 interrupt disabled masked b2 PO PCI Interrupt C Mask 0 interrupt enabled 1 interrupt disabled masked b1 PQ PCI Interrupt B Mask 0 interrupt enabled 1 interrupt disabled masked b0 PQ PCI Interrupt A Mask 0 interrupt enabled 1 interrupt disabled masked The PO PCI interrupt mask register enables disables the board s processing of PO PCI interrupts This is necessary since the board is sharing interrupts when other boards are connected to the PO PCI interface Setting a bit masks the corresponding interrupt which prevents it
83. to the secondary bus of the bridge the access is passed through unchanged If the bus number matches the secondary bus number the bridge converts the access to a Type O PCI configuration access The device number is then decoded and the proper IDSel asserted to configure the device on the secondary bus For more information on PCI configuration refer to the PCI implementation details discussion in the PCI bus chapter in Section 3 page 62 and the Setting PCI device base address discussion in Section 4 page 101 Also refer to the Type 0 configuration table on page 108 PO PCI configuration The implementation of configuring the PO PCI bus for each board connected to the bus the address ranges and any address translation are application specific It is recommended that each board be allocated at least one 256KB window into the onboard memory VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 9 PCI PCI Bridge Interface Software support PO PC Software support PO PCI Synergy Microsystems provides optional software to support board to board communications using the VSS4 s PO PCI interface o Global Buffer Manager GBM Software Package The GBM software package allows sharing of data among processors on Synergy PPC CPU boards connected via the PO PCI bus backplane GBM is available for Linux and VxWorks contact factory for av
84. transfers those values into the actual Timekeeper counters and allows normal operation to resume The FT bit as well as the bits marked with zeros in the above table must be written with zeros to allow normal Timekeeper and RAM operation Stopping and starting the oscillator The oscillator may be stopped at any time If the CPU board is going to spend a significant amount of time on the shelf the oscillator can be turned off to minimize current drain from the battery The STOP bit is the MSB b7 of the Seconds register Set this bit to 1 to stop the oscillator VSS4 User Guide 139 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 140 Section 4 Programming the PowerPC Clock calendar To start the oscillator Set the Write bit to 1 Reset the Stop bit to 0 Reset the Write bit to 0 Wait two seconds Set the Write bit to 1 Set the correct time and date Reset the Write bit to 0 eogeoeddo Calibrating the clock speed The low order 5 bits of the control regis ter Calibration in the table above represent any value between 0 and 31 in binary form The sixth bit is a sign bit the s bit in the table above where S 1 indicates a positive calibration and speeds up the oscillator S 0 indicates a negative calibration and slows down the oscilla tor Calibration corrections are applied within a 64 minute cycle The first 62 minut
85. 0 600 0x04 0xE2 0x04E2 1250 300 1200 0x02 0x71 0x0271 625 600 2400 0x01 0x39 0x0139 313 1200 4800 0x00 0x9C 0x009C 156 2400 9600 0x00 0x4E 0x004E 78 4800 19 2K 0x00 0x27 0x0027 39 9600 38 4K 0x00 0x1A 0x001A 26 14 4K 57 6K 0x00 0x14 0x0014 20 19 2K 76 8K 0x00 0x0D 0x000D 13 28 8K 115 2K Note that the table above is not exhaustive it only contains the most commonly used baud rates The user can program a divisor value DLM DLL registers for any desired baud rate using the formulas o For divide by one mode 1 500 000 baudrate divisor For divide by two mode 375 000 baudrate divisor VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Asynchronous serial interface Serial interface interrupts The ST16C654 provides six levels of prioritized interrupts The status of these interrupts is shown in the Interrupt Status Register ISR A read of the ISR provides an indication of the highest pending interrupt to be serviced No other interrupts are acknowledged until the pending interrupt is serviced Reading the ISR clears the interrupt status of the current pending interrupt only Note that after an interrupt is cleared the ISR should be reread as another lower level interrupt may be pending The table below shows the interrupt sources the priority level and associated status bits Interrupt s
86. 0 8 minus front panel Board Thickness 0 062 0 005 inches or 15 24 0 51 mm Weight VSS4 19 ounces 539g Weight approx for board with 512 MB RGS3 memory module and no PMC card Power requirements VSS4 typical power consumption with no PMC card installed VSS4 User Guide 263 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix B Specifications Typical power consumption G4 7400 466 MHz 5 0V 5 15 7 A typical 5 00V 78 5 W 12V 5 50 mA for 12V 150 mA for 12V G4 7400 433 MHz 5 0V 5 11 0 A typical 5 00V 55 W 12V 5 50 mA for 12V 150 mA for 12V G4 7400 366 MHz 5 0V 5 9 5 A typical 5 00V 47 5 W 12V 5 50 mA for 12V 150 mA for 12V G4 7410 500 MHz 5 0V 5 8 37 A typical 5 00V 41 9 W 12V 5 50 mA for 12V 150 mA for 12V Notes 1 Measured with board running SMon memory test memory module 256 MB CPU core voltage 2 05V and L2 cache ratio 2 1 2 Measured with board running powertest under Synergy Linux BSP 2 14 12 B memory module 512 MB CPU core voltage 1 8V and L2 cache ratio 2 1 Voltages must be kept within these tol erances to ensure proper operation Operating environment Temperature Operating sea level O to 55 C ambient with forced air cooling minimum 400 LFM recommended 600 LFM Non operating Storage 20 to 70 C Board configura
87. 00_7800 17 0x10E3 0x0000 Tundra Semiconductor Universe II PCI VME64 bridge 0x8000_8800 18 0x1011 0x0046 DEC 21554 PCI PCI bridge Note 3 0x8000_9000 Notes 1 PMC Slot2 present on select model Synergy SBCs 2 This PCI PCI bridge 21154 on PEX3 only 3 This PCI PCI bridge 21554 on SBC models VGM5 and VSS4 only 4 Vendor and Device IDs set by PMC manufacturer VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC VSS4 address map The VSS4 address map as viewed by the PowerPC processor s and PCI devices is shown in the tables below Address map PowerPC Address Map Address Device address space description Access 0000_0000 01FF_FFFF RAM 32 MB D8 D64 RW 0000_0000 03FF_FFFF RAM 64 MB D8 D64 RW 0000_0000 O7FF_FFFF RAM 128 MB D8 D64 RW 0000_0000 OFFF_FFFF RAM 256 MB D8 D64 RW 0000_0000 1FFF_FFFF RAM 512 MB D8 D64 RW 0000_0000 3FFF_FFFF RAM 1 GB D8 D64 RW 0000_0080 Mailbox A Write D8 WO Note 2 0000_00A0 Mailbox B Write D8 WO Note 2 0000_00C0 Mailbox C Write D8 WO Note 2 0000_00E0 Mailbox D Write D8 WO Note 2 4000_0000 7FFF_FFFF Reserved 1 GB 8000_0000 FCFF_FFFF PCI Memory Space 2 GB 48 MB D8 D16 D32 RW FD00_0000 FDFF_FFFF Reserved FE00_0000 FE7F_FFFF PCI I O S
88. 06 PCI interface is compliant with PCI Local Bus Specification Revision 2 1 The PCI bus is 32 bits wide and runs at 33 MHz Refer to the PCI bus description in Section 3 for more information As a PCI interface the MPC106 functions as both a master and target device As a PCI bus master the MPC106 configures all PCI devices using PCI configuration cycles in addition to supporting read write operations to PCI memory space and PCI I O space As a PCI target the MPC106 supports read write operations to system memory VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC MPC106 PCI bridge memory controller Power management functions The table below lists the power management functions supported by the MPC106 MPC106 power management functions Mode Description Full On This is the normal operating mode Doze All functions disabled except PCI address decoding RAM refresh CPU bus requests and NMI monitoring The CPUs can continue to operate normally Nap All functions disabled except PCI address decoding RAM refresh CPU bus equests and NMI monitoring The CPUs are also in Nap mode 603s will not snoop but 604s will Flush 603 L1 caches before entering this mode Sleep All functions disabled except RAM refresh CPU bus requests and NMI monitoring CPUs are also in sleep or nap mode Suspend All
89. 080_0000 0x00BF_FFFF PCI I O space OxFECO_0000 OxFEDF_FFFF 4G 20M 4G 18M 1 CONFIG_ADDR PCI configuration address register OxFEEO_0000 OxFEEF_FFFF 4G 18M 4G 17M 1 CONFIG_DATA PCI configuration data register OxFEFO_0000 OxFEFF_FFFF 4G 17M 4G 16M 1 OxFEFF_0000 OxFEFF_FFFF PCI interrupt acknowledge OxFFO0_0000 OxFF7F_FFFF 4G 16M 4G 8M 1 OxFFO0_0000 0xFF7F_FFFF 64 bit system ROM space OxFF80_0000 OxFFFF_FFFF 4G 8M 4G 1 OxFF80_0000 OxFFFF_FFFF 8 or 64 bit system ROM space Address map B PCI memory master view PCI Memory Transaction Address Range PowerPC Processor Hex Decimal Address Range Definition 0x0000_0000 0x0009_FFFF 0 640K 1 0x0000_0000 0x0009_FFFF System memory space 0x000A_0000 Ox000F_FFFF 640K 1M 1 0x000A_0000 0x000F_FFFF Compatibility hole 0x0010_0000 Ox3FFF_FFFF 1M 1G 1 0x0010_0000 0x3FFF_FFFF System memory space 0x4000_0000 0x7FFF_FFFF 1G 2G 1 0x4000_0000 0x7FFF_FFFF Reserved 0x8000_0000 OxFCFF_FFFF 2G 4G 48M 1 No system memory cycle PCI memory space OxFD00_0000 OxFDFF_FFFF 4G 48M 4G 32M 1 0x0000_0000 0x00FF_FFFF System memory space OxFE00_0000 OxFEFF_FFFF 4G 32M 4G 16M 1 No system memory cycle Reserved OxFFO0_0000 OxFF7F_FFFF 4G 16M 4G 8M 1 OxFF00_0000 0xFF7F_FFFF 64 bit system ROM space OxFF80_0000 OxFFFF_FFFF 4G 8M 4G 1 OxFF80_0000 OxFFFF_FFFF 8 or 64 bit system ROM space Notes 1 Used for PCI configuration cycles 2 Maps to unused
90. 0x2_0050 IPI 1 dispatch register processor 0 R W 0x2_0060 IPI 2 dispatch register processor 0 R W 0x2_0070 IPI 3 dispatch register processor 0 R W 0x2_1040 IPI 0 dispatch register processor 1 R W 0x2_1050 IPI 1 dispatch register processor 1 R W 0x2_1060 IPI 2 dispatch register processor 1 R W 0x2_1070 IPI 3 dispatch register processor 1 R W 0x2_2040 IPI 0 dispatch register processor 2 R W 0x2_2050 IPI 1 dispatch register processor 2 R W 0x2_2060 IPI 2 dispatch register processor 2 R W 0x2_2070 IPI 3 dispatch register processor 2 R W 0x2_3040 IPI 0 dispatch register processor 3 R W 0x2_3050 IPI 1 dispatch register processor 3 R W 0x2_3060 IPI 2 dispatch register processor 3 R W 0x2_3070 IPI 3 dispatch register processor 3 R W Note Add to base address set during PCI configuration VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 6 MPIC Interrupt Controller MPIC registers Current Task Priority register Each processor has a Current Task Priority register 31 4 3 0 Reserved Priority 31 Priority Task Priority Set from O lowest to 15 highest Setting the Task Priority register to 15 masks all interrupts to this processor At reset hardware sets the Task Priority registers to OxF Do not use the Task Priority register to temporarily disable interrupts to a processor Doing so may result in a spurious interrupt being generat
91. 128K bytes of battery backed SRAM Note SRAM can be read with D8 D16 or D32 accesses For write accesses however only byte wise writes are allowed A D32 write to non volatile SRAM results in a bus error VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 143 144 Section 4 Programming the PowerPC Non volatile 728K x 8 SRAM NVRAM space allocation The table below is a guide to the VSS4 s NVRAM space allocation for various operating systems and factory test functions Observe these space allocations as required by your application Note that you have the option to use any unassigned or unused OS spaces in the listed NVRAM allocations Non volatile SRAM space allocations Address Size Description OxFFE8 0000 O0xFFE9_CFFF 116KB Free User Space OxFFE9_D000 OxFFE9_D4FF 1 25KB_ Reserved factory testing OxFFE9_D500 OxFFE9_D5FF 256B Reserved Boot up write verify Scratch Space OxFFE9_D600 OxFFE9_ DAFF 1 25KB OS9 OxFFE9_DBO00 0xFFE9_DBFF 256B unassigned OxFFE9_DC00 OxFFE9 EOFF 1 25KB LynxOS OxFFE9_E100 O0xFFE9_E2FF 512B unassigned OxFFE9_E300 OxFFE9_E6FF 1 0KB VxWorks OxFFE9_E700 0xFFE9_E8FF 512B OS common Boot config Bd Serial No OxFFE9_E900 0xFFE9_EDFF 1 25KB Linux OxFFE9_EE00 0xFFE9_EFFF 512B unassigned OxFFE9_F000 OxFFE9_F4FF 1 25KB
92. 2 i i O Standard PCI r Bridge a P13 Req Gnt Clk P13r l 1 AN l for PEX3 T VME P2 o a paa P15r SBC Slot Expansion i aT Pass through PCI bus i mclO 65 110 i Ag ois PMC C 1 0 2 l Signals not passed if D DZI P15 Synergy PMC 1 uses Oo i 7 T extra VO pins orif 5 i T PSTR adapter is used P34 VME P2 PEX3 Slot i i UserlO 65 110 D amp Z e P24 UserlO 1 64 A amp C ke a P14 Note Third party or Synergy PMC r Synergy PSTK 3 p 7 4 Synergy PSTR A Pass through Pit ped Gn Ck Pir Pt Piir for PEX3 a P12 P12r P12 P12r 7 i Pass through __ gt P13 J P13r P13 J Standard PCI i Piar 7 1 7 Req Gnt Clk i P15r for PEX3 pt o K mc i P15 UserlO 65 110 PMC C 1 0 i 99 0132 PMC P2 I O routing stacking VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 279 280 Appendix D PEX3 PMC expansion option Operation Address map The table below lists the PEX3 onboard memory and register addresses PEX3 memory address map PCI 9080 Space Local Address Device Access Space 0 0x0000_0000 0x3FFF_FFFF Flash D8 D16 D32 R D32 W Space 1 0x4000_0000 0x43FF_FFFF SDRAM D8 D16 D32 RW Space 0 0xC000_0000 Board Type register D8 RO Space 0 0xC000_0004 Revision and ECO Level register D8 RO Sp
93. 28 60 PpcDH29 61 Gnd 62 PpcDH30 63 PpcDH31 64 Vec3V 65 RamClk6 66 RamClk2 67 Gnd 68 PpcDLO 69 PpcDL1 70 Vec3V 71 PpcDL2 72 PpcDL3 73 Gnd 74 PpcDL4 75 PpcDL5 76 Vec3V 77 PpcDL6 78 PpcDL7 79 Gnd 80 PpcDL8 81 PpcDL9 82 Vec3V 83 PpcDL10 84 PpcDL11 85 Gnd 86 PpcDL12 87 PpcDL13 88 Vec3V 89 PpcDL14 90 PpcDL15 91 Gnd 92 PpcDL16 93 PpcDL17 94 Vec3V 95 PpcDL18 96 PpcDL19 97 Gnd 98 PpcDL20 99 PpcDL21 100 Vec3V VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 257 Appendix A Cables amp Connectors Memory module connectors PM1 amp PM2 Memory module connector PM2 pinouts 252 Odd Row Function Even Row Function Pin No Pin No 1 PpcDL22 2 PpcDL23 3 Gnd 4 PpcDL24 5 PpcDL25 6 Vec3V 7 PpcDL26 8 PpcDL27 9 Gnd 10 PpcDL28 11 PpcDL29 12 Vec3V 13 PpcDL30 14 PpcDL31 15 Gnd 16 MemRamWE 17 RamWrClk 18 Vec3V 19 MemRamRE 20 RamRdClk 21 Gnd 22 MemWE 23 MemSDCAS 24 Vec3V 25 MemSDRAS 26 MemCKE 27 Gnd 28 MemCS7 29 MemCS3 30 Vec3V 31 RamClk5 32 RamClk1 33 Gnd 34 MemCS6 35 MemCS2 36 Vec3V 37 MemCS5 38 MemCS1 39 Gnd 40 MemCS4 41 MemCS0 42 Vec3V 43 MemDQM7 44 MemDQM3 45 Gnd 46 MemDQM6 47 MemDQM2 48 Vec3V 49 MemDQM5 50 MemDQM1 51 Gnd 52 MemDQM4 53 MemDQM0 54 Vec3V 55 MemSDBAO 56 MemSDBA1 57 Gnd 58 MemSDMA1 5
94. 3 operating environment 264 operating notes about 9 P cable defined 300 PO overlay See PO PCI interface PO PCI interface 45 217 overlay board 45 217 PO overlay board models 46 PO overlay typical component assembly 49 software support 223 P1 P2 etc see connectors page defined 300 PCI bus overview 61 defined 300 device base address setting the 101 PCI configuration and address VSS4 108 PCI Discovery Also PCI Enumeration PCI Auto Configuration reset 160 PCI configuration and address PEX3 281 PCI interface PEX3 configuration 281 PCI 9080 basic setup 282 PCI interrupts PEX3 PMC 280 PEX3 about 4 269 address map 280 block diagram 270 board layout 271 features 269 VSS4 User Guide Artisan Technology Group Quality Instrumentation Flash write protect jumper JGO2 273 front panel layout 272 installing PMCs 274 onboard capability registers 283 PCI configuration 281 PCI Type 0 configuration 281 PEX3 expansion board 40 PMC PCI interrupts 280 registers overview 283 using memory 286 physical address Ethernet 80 physical configuration 5 PMC card installation 41 connectors pinout 237 defined 300 overview 62 PMC stacking details 278 power consumption 15 power supply 15 power monitor 161 PowerPC architecture 85 architecture overview 85 defined 300 G4 processor 90 instruction set overview 89
95. 37 DevSel 38 5V 39 Gnd 40 Lock 41 SDONE 42 SBO 43 Par 44 Gnd 45 VI O 5V 46 AD15 47 AD12 48 AD11 49 AD9 50 5V 51 Gnd 52 CBEO 53 AD6 54 AD5 55 AD4 56 Gnd 57 VI O 5V 58 AD3 59 AD2 60 AD1 61 ADO 62 5V 63 Gnd 64 Req64B VSS4 User Guide 239 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PMC connectors P11 P15 PMC connector P72 pinouts Pin Function Pin Function 1 12V 2 Gnd TRst 3 PEX3_Req TMS 4 TDO 5 PEX3_Clk TDI 6 Gnd 7 Gnd 8 Reserved 9 Reserved 10 Reserved 11 12 3 3V 13 Rst 14 15 3 3V 16 17 Reserved 18 Gnd 19 AD30 20 AD29 21 Gnd 22 AD26 23 AD24 24 3 3V 25 AD13 IDSel 26 AD23 27 3 3V 28 AD20 29 AD18 30 Gnd 31 AD16 32 CBE2 33 Gnd 34 Reserved 35 TRdy 36 3 3V 37 Gnd 38 Stop 39 PErr 40 Gnd 41 3 3V 42 SErr 43 CBE1 44 Gnd 45 AD14 46 AD13 47 Gnd 48 AD10 49 AD8 50 3 3V 51 AD7 52 Reserved 53 3 3V 54 Reserved 55 Reserved 56 Gnd 57 Reserved 58 Reserved 59 Gnd 60 Reserved 61 Ack64B 62 3 3V 63 Gnd 64 Reserved 240 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PMC connectors P11 P15 PMC connector P13 pinouts
96. 4 Bridge Improving VME performance Improving VME performance Universe Il specific U2SPEC register The Universe II chip Revision ID 01 or 02 comes with a register called Specific Register U2SPEC offset Ox4FC which is used to improve the performance of the Universe II by reducing the latency of key VMEbus timing elements The timing adjustment provided by the U2SPEC register is intended to compensate for VME master and slave latencies introduced by buffers transceivers and the backplane itself Using the U2SPEC register may result in violation of the VME specification The U2SPEC register is an unsupported feature of Universe Il Its design may not be as robust as other areas of the Universe Il design and may not be included in future revisions of the device Improper use of the U2SPEC register may result in undesirable system behavior Tundra Semiconductor Corp and Synergy Microsystems Inc do not recommend the manipulation of this register by users who are unfamiliar with the timing characteristics of their VME systems VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 195 196 Section 7 PCI VME64 Bridge Improving VME performance U2SPEC adjustable VME timing parameters VME DTAck Inactive Filter DTKFLTR bit 12 In order to overcome the DTAck noise typical of most VME systems the Universe l quadruple samples this signal
97. 4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC PowerPC architecture Separate L1 instruction and data caches e Instructions for controlling L1 data cache coherency at the user level Support for both big and little endian addressing Further information For further PowerPC processor information refer to the following Motorola IBM documentation e The appropriate processor model User s Manual PowerPC Microprocessor Family The Programmer s Reference Guide Document No MPCPRG D For these and other literature contact Motorola Literature Distribution Center P O Box 20912 Phoenix AZ 85036 PowerPC information and documentation in PDF format is also available at Motorola s Semiconductor Products Sector website http e www motorola com Architecture models There are three models within the PowerPC architecture 1 User model containing the user instruction set architecture UISA registers This model contains the GPR FPR condition floating point status and control XER link and count registers These registers are accessible by all software all the time 2 User model containing the virtual environment architecture VEA registers This model includes the UISA model and time base facility registers The time base facility registers are read only in this model 3 Supervisor model containing the oper
98. 4 bridge PCI configuration The PEX3 s 9080 PCI bus mastering interface chip is automatically configured via PCI configuration accesses during system startup The board s 9080 driver and the onboard serial EEPROM work in tandem to set up the chip The table below shows the PCI 9080 configuration space PEX3 PCI 9080 PCI configuration registers 31 16 15 0 PCI Access Device ID 0x9080 Vendor ID 0x10B5 0x00 Status Command 0x04 Class Code 0x068000 Rev ID 0x05 0x08 BIST Header Type PCI Bus Latency Cache Line Size 0x0C Timer PCI Base Addr 0 Memory Mapped Config Registers PCIBARO 0x10 PCI Base Addr 1 I O Mapped Config Registers PCIBAR1 0x14 PCI Base Addr 2 Local Address Space 0 PCIBAR2 PEX3 Flash 0x18 PCI Base Addr 3 Local Address Space 1 PCIBAR3 PEX3 SDRAM 0x10 Unused Base Address PCIBAR4 0x20 Unused Base Address PCIBAR5 0x24 Cardbus CIS Pointer not supported 0x28 Subsystem ID 0x2321 Subsystem Vendor ID 0x80F6 0x2C PCI Base Address for Local Expansion ROM 0x30 Reserved 0x34 Reserved 0x38 Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x3C Notes Shaded Register NOT USED for PEX3 1 EEPROM Writeable 2 PCI Writeable VSS4 User Guide 281 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 282 Appendix D PEX3 PMC expansion option PCI 9080 basi
99. 8 88 SOURCE www artisantg com 111 Section 4 Programming the PowerPC Address map Address Map Table Notes Note 1 The Boot Flash ROM and EPROM devices have specific locations and accesses depending on whether the board is configured to boot from Flash FlashBoot or DIP EPROM ROMBoot This is summarized below FlashBoot mode Boot ROM Enable jumper not installed The system boots from Boot Flash ROM at location FFFO_0100 The entire device is addressed at FFFO_0000 FFFF_FFFF and is D8 read write if Flash Write Protect jumper JO2L pins 9 amp 10 for Rev B or lower boards JO2L pins 21 amp 22 for Rev C or higher boards not installed and if FlashWP bit is not on otherwise device is read only EPROM is addressed at FFEO_0000 FFE7_FFFF The EPROM Flash ROM address map for FlashBoot is shown below Address Map FlashBoot Address Device address space description Access FFEO_0000 FFE7_FFFF EPROM 512 KB D8 RW D64 RO FFFO_0000 FFFF_FFFF Boot Flash ROM D8 RW D64 RO ROMBoot mode Boot ROM Enable jumper installed The system boots from EPROM at location FFF0_0100 EPROM is addressed at FFF0_0000 FFF7_FFFF Boot Flash ROM is read write and is split addressed at FFE0_0000 FFE7_FFFF and FFF8_0000 FFFF_FFFF Flash ROM reading programming code must deal with the address discontinuity to properly access the device The ERROM Flash ROM address map for ROMBoot is shown below A
100. 8 88 SOURCE www artisantg com Section 2 Getting Started Setting up the VSS4 hardware JO2L jumper settings for slot number selection SlotNo Pins11 amp 12 Pins13 amp 14 Pins15 amp 16 Pins17 amp 18 Pins 19 amp 20 GA4 GA3 GA2 GA1 GAO 1 oz Z 2 e 3 4 e 5 e e 6 e 7 e 8 e 9 e 10 11 12 e 13 e e e 14 i 15 e 8 e e 16 17 z e 18 Bn e 19 e 20 e 21 e e VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 28 Section 2 Getting Started Setting up the VSS4 hardware VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing a monitor PROM Installing a monitor PROM The VSS4 comes with one 32 pin 8 bit monitor DIP EPROM socket that accepts any of the following devicest 27C010 1 Mbit 128 KB DIP EPROM 27C020 2 Mbit 256 KB DIP EPROM 27C040 4 Mbit 512 KB DIP EPROM 28F020 2 Mbit 256 KB Flash DIP EPROM 29C040 4 Mbit 512 KB Flash DIP EPROM Some boards ship from the factory with the appropriate monitor PROM already install
101. 9 MemSDMA2 60 Vec3V 61 MemSDMA3 62 MemSDMA4 63 Gnd 64 MemSDMA5 65 MemSDMA6 66 Vec3V 67 RamClk4 68 RamClk0 69 Gnd 70 MemSDMA7 71 MemSDMA8 72 Vec3V 73 MemSDMAQ9 74 MemSDMA10 75 Gnd 76 MemSDMA11 77 MemSDMA12 78 Vec3V 79 80 81 Gnd 82 MemID7 83 MemID3 84 Vec3V 85 MemID6 86 MemID2 87 Gnd 88 MemlD5 89 MemID1 90 Vec3V 91 MemID4 92 MemID0 93 Gnd 94 MbxWrD 95 MbxWrC 96 Vec5V 97 MbxWrB 98 MbxWrA 99 Gnd 100 MbxLE VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Wide Ultra SCSI connector P264 Wide Ultra SCSI connector P264 A front panel 68 pin high density D connector provides the connection to the optional onboard Wide Ultra SCSI port The drawing below shows this connector P264 and its pin 1 orientation The table that follows lists the P264 pinouts Q D 2 SBC Front Panel ISOS G Wide Ultra SCSI Front Panel Connector Pin 1 Wide Ultra SCSI front panel connector P264 VSS4 User Guide 253 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Wide Ultra SCSI connector P264 Wide Ultra SCSI connector P264 pinouts
102. 90S OINd s 8490S OINd imille O O i O M I vLLO LO L OINd LOWdX s 8490S OINd apo Se aS ee k zed dk ted J l Zld d saueyns pieog D O z O O 7 O C o o o O O O O zor o o fe a auno ysep ul umoys x OWd A L Jaueg U014 jaued 4014 Jaued U014 OWd OWdX NYVYG 2 OWd ZINdX yse 4 L Nd LOWdX pueoquo do pueoquo do Jaduing 199 01q M Yse 4 PEX3 board layout 271 VSS4 User Guide Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation Appendix D PEX3 PMC expansion option Front panel layout The drawing below shows the VSS4 PEX3 front panel layout Eject Lever upper Status LEDs User LEDs 0 7 r 8 bit User Switch Wide Ultra SCSI Front Panel Connector Serial I O A amp B RJ 50 RJ 69 Jack Fast Ethernet RJ 45 Jack PMC Module Front Panel Cutout Filler Panel Eject Lever lower CPU Halt Run LEDs CPU SMI Reset Switch Expansion PMC 3 Front Panel Cutout Filler Panel Expansion PMC 2 Front Panel Cutout Filler Panel Expansion PMC 2 Front Panel Cutout Filler Panel 03 0255 VSS4 PEX3 option front panel 272 VSS4 User G
103. AD13 Gnd 13 AD14 SErr AD15 AD28 Lock Gnd 14 Req Stop SysCon CBE2 IRdy Gnd 15 CBE1 PErr TRay AD23 AD20 Gnd 16 DevSel AD19 AD17 AD24 AD29 Gnd 17 Frame CBE3 AD22 AD27 AD26 Gnd 18 AD16 AD21 IDSel AD30 AD31 Gnd 19 Gnt AD18 AD25 Rst Clk Gnd VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 247 Section A Cables amp Connectors PO PCI bus connector PO 248 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Memory module connectors PM1 amp PM2 Memory module connectors PM1 amp PM2 The field replaceable RGS3 memory module plugs into the VSS4 board via connectors PM1 and PM2 The drawing below shows the locations of these connectors The table that follows lists the PM1 and PM2 pin assignments This connector accepts the following j memory module board s RGS3 32 64 128 256 or 512MB of SDRAM VSS4 User Guide 249 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Memory module connectors PM1 amp PM2 PM1 PM2
104. Arbiter Board UP connector connector 95 pin socket connector 4 places BPL4 Left gt BPR4 Right PO Overlay PO Overlay c BPL4 BPR4 4 slot Left or Right PO overlay bridgeable Bridge Board connector left right only or both Bridge Board connectors left right only or both 95 pin socket 95 pin socket Arbiter Board connector Arbiter Board connector connector 5 places connector 6 places UP d BPM5 5 slot Center PO overlay bridgeable e BPM6 6 slot Center PO overlay bridgeable Note View is from FRONT of card cage looking towards back Farside components shown with dashed line 99 0245 PO overlay board models VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing the PO overlay Bridge Board connectors left or right only not both 95 pin socket Zs Arbiter Board connector connector 7 places UP f BPM7 7 slot Center PO overlay bridgeable i 95 pin socket Arbiter Board connector connector 8 places UP g BP08 8 slot Center PO overlay non bridgeable Note View is from FRONT of card cage looking towards back Farside components shown with dashed line 99 0246 PO overlay board models continued VSS4 Use
105. Boot Flash The result of this limit is that code stored in the User Flash must be read into RAM and executed from RAM instead of being directly executed from Flash ROM VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC User Flash memory User Flash bank selection Flash device Address within device Register User Flash Amount Value Boot 0x0008_0000 Ox000F_FFFF 0x00 User 0x0000_0000 0x0007_FFFF 0x80 User 0x0008_0000 Ox000F_FFFF 0x81 User 0x0010_0000 0x0017_FFFF 0x82 2MB User 0x0018_0000 0x001F_FFFF 0x83 User 0x0020_0000 0x0027_FFFF 0x84 4 MB User 0x0028_0000 0x002F_FFFF 0x85 User 0x0030_0000 0x0037_FFFF 0x86 User 0x0038_0000 0x003F_FFFF 0x87 User 0x0040_0000 0x0047_FFFF 0x88 8 MB User 0x0048_0000 0x004F_FFFF 0x89 User 0x0050_0000 0x0057_FFFF 0x8A User 0x0058_0000 0x005F_FFFF 0x8B User 0x0060_0000 0x0067_FFFF 0x8C User 0x0068_0000 0x006F_FFFF 0x8D User 0x0070_0000 0x0077_FFFF 0x8E User 0x0078_0000 0x007F_FFFF 0x8F User 0x0080_0000 0x0087_FFFF 0x90 16 MB User 0x0088_0000 0x008F_FFFF 0x91 User 0x0090_0000 0x0097_FFFF 0x92 User 0x0098_0000 0x009F_FF
106. CI card carry interrupts from the card to the PCI bus The standard labels these as A B C and D The Interrupt Pin field describes which of these pins this PCI device uses Generally it is hardwired for a particular device That is every time the system boots the device uses the same interrupt pin This information allows the interrupt handling subsystem to manage interrupts from this device Interrupt Line The Interrupt Line field of the device s PCI Configuration header is used to pass an interrupt handle between the PCI initialization code the device s driver and OS s interrupt handling subsystem The number written there is meaningless to the device driver but it allows the interrupt handler to correctly route an interrupt from the PCI device to the correct device driver s interrupt handling code within the operating system During system boot time PCI devices are detected and configured automatically via a software process called PCI Discovery Other names for this process include PCI Enumeration and PCI Auto Configuration The exact mechanism for PCI Discovery is system specific For Synergy PowerPC SBCs all PCI devices or slots in the system are hardwired with an address line that functions as the device s IDSEL number IDSEL is essentially a chip select for a device during PCI configuration VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com
107. D17 AD18 IDSel 26 AD23 27 3 3V 28 AD20 29 AD18 30 Gnd 31 AD16 32 CBE2 33 Gnd 34 35 TRdy 36 3 3V 37 Gnd 38 Stop 39 PErr 40 Gnd 41 3 3V 42 SErr 43 CBE1 44 Gnd 45 AD14 46 AD13 47 Gnd 48 AD10 49 AD8 50 3 3V 51 AD7 52 53 3 3V 54 55 56 Gnd 57 58 59 Gnd 60 61 Ack64 62 3 3V 63 Gnd 64 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 291 292 Appendix D PEX3 PMC expansion option PMC connector P13 P23 amp P33 pinouts Pin Function P13 P23 P33 Pin Function P13 P23 P33 1 2 Gnd 3 Gnd 4 CBE7 5 CBE6 6 CBE5 7 CBE4 8 Gnd 9 VI O 10 Par64 11 AD63 12 AD62 13 AD61 14 Gnd 15 Gnd 16 AD60 17 AD59 18 AD58 19 AD57 20 Gnd 21 VI O 22 AD56 23 AD55 24 AD54 25 AD53 26 Gnd 27 Gnd 28 AD52 29 AD51 30 AD50 31 AD49 32 Gnd 33 Gnd 34 AD48 35 AD47 36 AD46 37 AD45 38 Gnd 39 VI O 40 AD44 41 AD43 42 AD42 43 AD41 44 Gnd 45 Gnd 46 AD40 47 AD39 48 AD38 49 AD37 50 Gnd 51 Gnd 52 AD36 53 AD35 54 AD34 55 AD33 56 Gnd 57 VI O 58 AD32 59 60 61 62 Gnd 63 Gnd 64 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option PMC connector P14 pinouts PMC 1
108. E access to PCI and PCI access to VME The VME functions provided by this chip include System controller Block transfers master and slave Single data transfers master and slave Interrupt generation and handling For general information about the VSS4 VMEbus interface refer to the VME64 bus chapter in Section 3 The PCI interface side of the Universe Il provides the following functions PCI Target PCI masters address the Universe II Read transactions are coupled Write transactions are either coupled or posted depending on the PCI bus target image PCI masters can also perform RMW and ADOH cycles via the Universe I s Special Cycle generator For details on the mechanisms of these transfers refer to the Universe I User Manual o PCI Master An internal request of the Universe II s PCI Master interface by the VMEbus Slave channel or DMA channel causes the Universe Il to operate as a PCI master The user can set the relative priority of the VMEbus Slave channel and the DMA channel For details on how this is set up refer to the Universe II User Manual VSS4 User Guide 185 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 186 Section 7 PCI VME64 Bridge Introduction to Universe Il As an Interrupter and Interrupt Handler the Universe II provides flexible mapping of interrupts to the PCI bus or VMEbus interface PCI interrupts can be routed and proc
109. E9_FFF5 RPT4 RPT5 Al 10 Date Alarm Date Al Date 01 31 FFE9 FFF4 RPT3 0 Al 10 Hrs Alarm Hours Al Hours 00 23 FFEQ_FFF3 RPT2 Alarm 10 Minutes Alarm Minutes Al Minutes 00 59 FFEQ_FFF2 RPT1 Alarm 10 Seconds Alarm Seconds Al Seconds 00 59 FFE9_FFF1 1000 Years 100 Years Century 00 99 FFE9_FFFO WDF AF 0 BL RS3 RS2 RS1 RSO Flags Key S Sign bit WDS Watchdog Steering Bit FT Frequency Test Bit AF Alarm Flag R Read Bit BL Battery Low Flag W Write Bit SQWE Square Wave Enable Bit ST Stop Bit BMB0 BMB4 Watchdog Multiplier Bits 0 Must be set to 0 Z 0 and are read only RBO RB1 Watchdog Resolution Bits AFE Alarm Flag Enable ABE Alarm in Battery Back up Mode Enable RPT1 RPT5 Alarm Repeat Mode Bits WDF Watchdog Flag RS0 RS3 SQW Frequency Accessing clock data Access to the clock is as simple as conventional byte wide RAM access because the RAM and the clock are combined on the same die The Timekeeper registers are located in the upper 16 locations of the RAM as listed in the table above 138 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Clock calendar These registers contain beginning from the top year month day of month day of week Sunday 1 hour minutes and seconds data in 24 hour BCD format Corrections for leap year and the number of days
110. FB18 OxFFEF_FB10 O O wl gt VSS4 User Guide 133 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 134 Section 4 Programming the PowerPC Asynchronous serial interface Programmable baud rate generator A 24 0000 MHz clock oscillator provides input to the T16C654 baud rate generator The ST16C654 divides the clock input by 16 The resultant clock is divided down by a divisor which is programmed as a Hex value into the DLM MSB and DLL LSB registers Further division of this clock provides two table rates to support low clock divided by 4 and high clock divided by 1 data rate applications in the same system The default baud rate is set in hardware to the baud table that is derived from the clock divided by 1 After the board is initialized one of the two available baud tables must be selected via Modem Control Register MCR bit 7 MCR register b7 0 clock divided by 1 MCR register b7 1 clock divided by 4 The table below shows the DLM and DLL register program values and the associated output baud rate Baud rate generator programming table DLM value DLL value Divisor Output Baud bps Output Baud bps Hex Decimal clock 4 clock 1 0x4E 0x20 0x4E20 20000 75 0x27 0x10 0x2710 10000 150 0x13 0x88 0x1388 5000 75 300 0x09 0xC4 0x09C4 2500 15
111. FF 0x93 User 0x00A0_0000 0x00A7_FFFF 0x94 User 0x00A8_0000 0x00AF_FFFF 0x95 User 0x00B0_0000 0x00B7_FFFF 0x96 User 0x00B8_0000 0x00BF_FFFF 0x97 User 0x00C0_0000 0x00C7_FFFF 0x98 User 0x00C8_0000 0x00CF_FFFF 0x99 User 0x00D0_0000 0x00D7_FFFF 0x9A User 0x00D8_0000 0x00DF_FFFF 0x9B User 0x00E0_0000 0x00E7_FFFF 0x9C User 0x00E8_0000 0x00EF_FFFF 0x9D User 0x00F0_0000 0x00F7_FFFF 0x9E User Ox00F8_0000 OxO0FF_FFFF Ox9F 31 additional 512 KB windows User 0x01F8_0000 0x01FF_FFFF OxBF End of 32 MB User Flash 63 additional 512 KB windows User 0x07F8_0000 0x07FF_FFFF OxEF End of 64 MB User Flash VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 155 156 Section 4 Programming the PowerPC User Flash memory Writing and erasing Write protection of all Flash Boot Flash User Flash and DIP Flash EPROM if installed is set in either or both of two ways Jumper Flash Write Protect J02L pins 9 amp 10 Rev B or lower or pins 21 amp 22 Rev C or higher write protect if jumper ON no write protect if jumper OFF Refer to the Setting up the VSS4 hardware chapter in Section 2 page 23 for more information on the configuration jumpers Software Flash Write Protect Flash ROM register at OxFFEF_FE40 bit O controls protect 1 default and no protect 0 status Refer to the Refer to the Flash ROM
112. H E MNdI Z NdI LCi T Li LF i 1 azor sseduinr i OS E N oein O amol 10 g A8Y WZOF ZNdd M Ndd a g saueyns peog e ul pasapjos 5 O C Maneg lt WVYAN 2D 49019 Add X Ndd Nouda A o J pun 4 Y208 ul WOHd o yse 4 100g 9 i 5 e O00000 00O000000000 104205 o aie tae a i WOud3 did CLT SSS SSS SOOO OS i z oer es suedwine JeyBly 10 18M0 10 es uoljeunbyuog 9 ay g4 O a INOYdS O0PL 0SZ Odd O O ff zogr YouIMS azo a y yoer s10 99uU09 ynoyng jaueg suid pup 1 S Y INS SHOqd Bag u1 43 ainpow Aowa u014 8 NPOW DINd Aas 10 99UU09 SOS EMIN PPIM 265 VSS4 board layout Guaranteed 888 88 SOURCE www artisantg com VSS4 User Guide Artisan Technology Group Quality Instrumentation Appendix B Specifications Memory module RGS3 board layout 266 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix C Board revision summary This appendix summarizes some of the major changes made to the VSS4 boards affecting form fit and or function The paragraphs below list the changes pertaining to the revision shown oe The revision levels for each feature yj represents the revision level when the listed feature was added to the standard design
113. IC Interrupt Controller MPIC registers 1 every cycle until the device driver s interrupt service routine has cleared the interrupt at the source In some implementations Interrupt Acknowlege also flushes data buffers between the device and system memory Address map interrupt acknowlege registers Address Offset Register Access 0x2_00A0 Int Acknowledge register processor 0 RO 0x2_10A0 Int Acknowledge register processor 1 RO 0x2_20A0 Int Acknowledge register processor 2 RO 0x2_30A0 Int Acknowledge register processor 3 RO Note Add to base address set during PCI configuration End of interrupt registers There is one End of interrupt EOI register per processor Writing a zero to this register signals the end of processing for the highest priority interrupt currently in service by the associated processor EO Code values other than O are currently undefined and should not be used Reading this register returns the last value written MPIC Implementation Note When the EOI register is written the highest priority interrupt in the In Service Priority register is reset along with the corresponding bit in the Interrupt Source In Service register MPIC 2A requires the EOI code be written as zero to signal the end of processing for the highest priority interrupt currently in service by the associated processor EOI code values other than zero are ignored The MPIC 2A ret
114. Init bit in the MPIC is changed from O to 1 the CPU will be reset The Init bit must be reset to 0 before another soft reset may be performed VSS4 User Guide 163 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 5 Reset Reset information The Processor Init register is a 32 bit read write register of which the least 4 significant bits are defined Bit O on right is CPU X Init bit 1 is CPU Y etc Select Processors 3 0 31 3 2 1 0 c c c c P P P P Reserved ulululu wjiz yYy x To soft reset a particular CPU the appropriate bit s in the Processor Init register is are cleared to O then set to 1 This is done by masking the desired bit s off and writing the data word back to the register bit s cleared then ORing the bit s with the data word and writing that back to the register bit s set This initiates a soft reset of the corresponding processor s while the register bits of unselected processors remain unchanged A simplified form of this procedure in C is shown below bit Clear bit bit Set bit reg amp reg Where reg is the MPIC Processor Init register and bit is the value selecting one or more CPUs 1 2 4 8 corresponds to CPU X CPU Y CPU Z amp CPU W For Linux boot up code must start at zi 0x100 RAM space For this to happen the processor MSR register must have its MSR_IP bit cleared pr
115. Is 0 16M ee 0 16M E 4G 32M E TPM amp BIO M 4G 32M B TPM amp BO im PCI ISA bus port __ 2 L Ec 64KB or 8MB space I 4G 24M DIOE PCIVO l as ERON 4G 20M M TO M10 c 2o 10 CONFIG_ADDR 4G 18M 4G 17m _CONFIG_DATA aa pei POl MtAck 4G 16M System ROM space System ROM space 4G ROM or Flash 4G ROM or Flash 4G Note This view can be disabled Reserved Address map B Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VSS4 User Guide 107 108 Section 4 Programming the PowerPC Address map PCI configuration and address To help in programming VSS4 s PCI devices the table below lists each PCI device with its Type 0 PCI configuration data and address Type O configuration for devices on VSS4 ID Sel Vendor Device ID Manufacturer Part No Description PCI Config Address 0 0x1057 0x0002 Motorola MPC106 PCI bridge mem ctrlr 0x8000_0000 11 0x1014 0x0046 IBM MPIC multiproc int controller 0x8000_5800 12 0x1000 0x000D Symbios SYM53C885 SCSI controller 0x8000_6000 12 1 0x1000 0x0701 Symbios SYM53C885 Ethernet controller 0x8000_6100 13 Note 4 Note 4 Note 4 PMC Slot1 0x8000_6800 14 Note 4 Note 4 Note 4 PMC Slot2 Note 1 0x8000_7000 15 0x1011 0x0026 DEC 21154 PCI PCI bridge Note 2 0x80
116. LINT_MAP1 310 VMEbus Interrupt Enable register VINT_EN 314 VMEbus Interrupt Status register VINT_STAT 318 VMEbus Interrupt Map 0 register VINT_MAPO 31C VMEbus Interrupt Map 1 register VINT_MAP1 320 Interrupt Status ID Out register STATID 324 VIRQ1 Status ID register V1_STATID 328 VIRQ2 Status ID register V2_STATID 32C VIRQ3 Status ID register V3_STATID 330 VIRQ4 Status ID register V4_STATID 334 VIRQ5 Status ID register V5_STATID 338 VIRQ6 Status ID register V6_STATID 33C VIRQ7 Status ID register V7_STATID 340 PCI Interrupt Map 2 register LINT_MAP2 344 VME Interrupt Map 1 register VINT_MAP2 348 Mailbox 0 register MBOXO0 34C Mailbox 1 register MBOX1 350 Mailbox 2 register MBOX2 354 Mailbox 3 register MBOX3 358 Semaphore 0 register SEMAO 35C Semaphore 1 register SEMA1 360 3FC Reserved 400 Master Control register MAST_CTL 404 Misc Control register MISC_CTL 408 Misc Status register MISC_STAT 40C User AM Codes register USER_AM 410 EFC Reserved F00 VMEbus Slave Image 0 Control register VSIO_CTL F04 VMEbus Slave Image 0 Base Address register VSIO_BS F08 VMEbus Slave Image 0 Bound Address reg VSIO_BD FOC VMEbus Slave Image 0 Translation Offset reg VSIO_TO F10 Reserved F14 VMEbus Slave Image 1 Control register VSIH1_CTL F18 VMEbus Slave Image 1 Base Address register VSI1_BS FIC VMEbus Slave Image 1 Bound Address reg VSI1_BD F20 VMEbus Slave Image 1 Translation Offset reg VSI1_TO F24 Reserved F28 VMEbus Slave Image 2 Contro
117. Local Configuration Registers Runtime Registers typically not used for PEX3 DMA Registers X Messaging Queue Registers typically not used for PEX3 Refer to the PLX PCI 9080 documentation for detailed 9080 register information The PEX3 is also provided with the following onboard capability registers o o S Board Type Register Revision and ECO Level Register Flash Configuration Register SDRAM Configuration Register The following describes PEX3 s onboard read only registers These registers are intended to be read during driver initialization time using Space 0 This information configures the driver accordingly The register bit description uses the notation listed below in each bit position to show the register s value after a board reset i e power cycling or system reset Register bit description notations for reset value Notation What it means x Unused bit set to 0 for future compatibility Read only bit 1 Set to 1 upon reset 0 Set to 0 upon reset VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 283 Appendix D PEX3 PMC expansion option Board type register OxCOOO_OOOO RO Bit 7 6 5 4 3 2 1 0 0 0 0 0 O O 0 0 Reset value Bit assignments Bit s Function Values b7 b4 Board Type 0x0 PEX3 b3 b0 Reserved
118. P O Box 20912 Phoenix AZ 85036 Document descriptions and ordering information can be found on Motorola s website http www mot com SPS VSS4 User Guide 105 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 106 Section 4 Programming the PowerPC Address map The tables below list Address Map B as viewed by the processor and as viewed by PCI memory and I O Masters The figure following the tables shows a graphical view of Address Map B These tables are listed in Motorola s MPC106 User s Manual with additional notes Refer to the MPC106 user s manual for more information about Address Map B and Address Map A PREP Address map B Processor view PowerPC Processor Address Range PCI Hex Decimal Address Range Definition 0x0000_0000 0x0009_FFFF 0 640K 1 No PCI cycle System memory space 0x000A_0000 0x000B_FFFF 640K 768K 1 0x000A_0000 0x000B_FFFF Compatibility hole 0x000C_0000 Ox3FFF_FFFF 768K 1G No PCI cycle System memory space 0x4000_0000 0x7FFF_FFFF 1G 2G 1 No PCI cycle Reserved 0x8000_0000 OxFCFF_FFFF 2G 4G 48M 1 0x8000_000 OxFCFF_FFFF PCI memory space OxFD00_0000 0xFDFF_FFFF 4G 48M 4G 32M 1 0x0000_0000 0x00FF_FFFF PCI ISA memory space OxFE00_0000 OxFE7F_FFFF 4G 32M 4G 24M 1 0x0000_0000 0x0000_FFFF PCI ISA I O space 64Kbytes or 8 Mbytes OxFE80_0000 OxFEBF_FFFF 4G 24M 4G 20M 1 0x0
119. PC CPU s PowerPC Bus gt PowerPC to PCI Bridge Mem Ctrlr Local Bus _ PCI Sec Side to PCI Bridge Pri Side PO PCI P0 PO PCI Overlay External to SBC Arbiter Board Block diagram VSS4 PCI PCI bridge 218 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 9 PCI PCI Bridge Interface Registers Registers The 21554 contains the following register groups Primary and Secondary interface PCI configuration header registers Device specific configuration registers Memory and I O mapped control and status registers For detailed information on the 21554 PCl to PCI bridge refer to the 21554 PCl to PCI Bridge for Embedded Applications Hardware Reference Manual available from Intel This document is available as a PDF file from Intel s developer website http developer intel com design bridge Application notes datasheets and manuals for Intel s PCI bridges can be found at this site The table below lists recommended related documents available as PDF files from the Intel developer website online availability subject to change without notice Related 21554 documents available for download Document Date Size Specificati
120. PIC Interrupt Controller MPIC registers ACT Activity bit read only The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to 1 when its associated bit in the Interrupt Pending or In Service register is set Note that this bit is READ ONLY The vector and priority values should not be changed while the ACT bit is 1 MSK Mask bit Setting this bit disables any further interrupts from this source Reset sets this bit to one Unless otherwise specified reset sets all bits in all program accessible registers to zero Interrupt Source Destination register The destination register bit assignments are described below Select Processors 3 0 2 Reserved lt u NCUO C P U X Scud w This register indicates the destination processors s for this interrupt source CPU_ Setting the appropriate bit s b3 b0 directs the interrupt source to the corresponding processor s If a single destination processor is selected directed delivery mode then interrupts from this source are directed to that processor If multiple destination processors are selected distributed delivery mode then interrupts from this source are distributed among the selected destination processors using a fair implementation specific algorithm Per processor registers For each processor supported MPIC provides the following registers I nterprocessor interrupt
121. PMC expansion option Block diagram A functional block diagram of the optional PEX3 expansion board is shown below Front Panel T T T m Fnt Pnl Fnt Pnl Fnt Pnl i Cutout i Cutout Cutout I l i ESD Local Internal Bus 32 bit 33 MHz i Protect l i I l I I l l I I I l l l l l l 32 bit FI ash Potsoeo memory SDRAM ue i i Interface Controller Up to 256 I l I I l I I I l I l I I l I I l I Expansion PCI Bus 64 bit 33 MHz I I I I l I I l I I l ij PMC PMC PMC Expansion Expansion Expansion Slot 1 Slot 2 Slot 3 XPMC 1 XPMC 2 XPMC 3 64 46 46 1 0 Signals I O Signals 1 0 Signals SBC PMC Interface Connectors VME via PMC stacking or PSTK PSTR adapter o O 3 D FD aD wn wa wa Se aa Transition or PIM Transition or PIM SBC PCI Local Bus Carrier Module Carrier Module 00 0079 PEX3 functional block diagram 270 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option Board layout The drawing below shows the PEX3 components and PMC modules 10 D8UUO0D SNQAWA OWd OINdX 2 OWd Z0WdX S 4
122. R3 longword OxF8 MCCR4 longword OxFC VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC MPC106 PCI bridge memory controller Processor interface configuration registers The processor interface configuration registers PICRs control programmable parameters of the PowerPC bus and L2 cache interface Register Name Size Address Offset PICR1 longword OxA8 PICR2 longword OxAC Alternate OS Visible parameters registers Operating systems have an alternate means to access some of the bits of the PICR1 using the alternate OS visible parameters registers Register Name Size Address Offset Alternate OS visible parameters reg 1 byte OxBA Alternate OS visible parameters reg 2 byte 0xBB Emulation support configuration registers The emulation support configuration registers controls MPC106 operation in emulation mode Not used for VSS4 boards External configuration registers The external configuration registers allow access to certain configuration bits when using Address map A PREP Register Name Size Address Offset External configuration register 1 byte Port 0x092 External configuration register 2 byte Port 0x81C External configuration register 3 byte Port 0x850 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaran
123. S EES ASNE EEA EEO SESSIE ENEE Programming notes SYM53C885 ssssssseerssessreree SCSI prematurely surrendering PCI bus Section 9 PCI PCI Bridge Interface cccccccccceccceceeeceeeeeeeceeeceeeeeeeeeeeeeeeceeeeeeeeeeeeeeens 215 General ESCH ELON Serera ana ENE CEE N OAE ETA E aes ane eas N RER 217 TEE E EE E EE Configuration Introduction PC 1 COnmti SUnath OM ss isssscssssizsssesasasaccavectdsshesneessaceusanccedacoutstoetauasndescassgousessataacenbascdesstcavbsesarantuanavestehtuinrtoaaauiaiaainnsale PO PCI configuration SOMWare SUpPOnt POPC lM serer TERE NEE AREI EE ER T ERAEN Section 10 Warranties amp Service sssssssesssssseessssesessseesssssesessseessssseesssseesssssesessseesssse 225 Warranty terms amp OPtlons ssssessssssssssssssessssessascssssenssssessssnssasssssssssasssssceessssossssessstossssessssssnseondsoovesnsssosssesesbsdssssistesassseevansasvaseest 227 Customer SEICE ene e a e E AEA E T A E E 229 VI VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table of contents Appendix A Connectors amp Cables ccccccccsssscsssssssscccccccccccccccccccccsccccccccsccscccsecescceeseeees 231 VMEbus CONNECTORS PI BPD ciessesschcccsasaciadecats aciseasste N E A NEE E R 233 PMG COMMECHOFS P TSP 15 x ssi cussaseenssssssaegetsasiadosnsssssseasdnscnapasoensdivessossasoningssbnutescesetcasebonds rotasi SEE COEP Taea a
124. S4 s onboard PCI bus This connection scheme allows the PCI PCI bridge to be used for peer to peer communication between multiple VSS4 boards Up to 8 boards can be connected together using the PO PCI bus The PO PCI interface uses the VME64x PO connector which is in between the VME P1 and P2 connectors Note that the VSS4 s PO connector may interfere with board insertion in non VME64x compatible backplanes The VSS4 PO PCI interface works in conjunction with a PO PCI overlay board See the Installing the PO overlay chapter in Section 2 page 45 for model descriptions and installation information For ordering information of these components contact Synergy Microsystems Customer Service The external PO PCI overlay board connects PO PCI slots together from the back side of the VME64x backplane The overlay board with the exception of passive models includes a plug in arbiter board which provides clock generation and round robin PCI bus arbitration for all interconnected boards on the PO PCI bus The arbiter board also VSS4 User Guide 217 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 9 PCI PCI Bridge Interface General description provides power on reset to all devices on the primary side of PO PCI interface The diagram below shows the VSS4 PCI PCI bridge interface in relation to the other major busses in the system Power
125. SBDL SCSI Bus Data Lines 0x5A 0x5B Reserved 0x5C 0x5F R W SCRATCHB General Purpose Scratch Pad B 0x60 0x7F R W ScratchC J General Purpose Scratch Pad C J VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller SYM53C885 registers Ethernet registers PCI configuration The PCI configuration registers for the Ethernet interface are shown below Addresses 0x40 through OxFF are unused 31 16 15 0 Device ID Vendor ID 0x00 0x0701 0x1000 Status Command 0x0000 0x04 Class Code 0x020000 Revision ID 0x00 0x08 BIST Header Type Latency Timer Cache Line Size 0x0C Base Address Zero I O Ethernet Operating Registers 0x10 Base Address One Memory Ethernet Operating Registers 0x14 Not Supported 0x18 Not Supported 0x1C Not Supported 0x20 Not Supported 0x24 Reserved 0x28 Subsystem ID Subsystem Vendor ID 0x2C Expansion ROM Base Address 0x30 Reserved 0x34 Reserved 0x38 Max Lat Max_Gnt Interrupt Pin Interrupt Line 0x3C Note Setting bitO or bit 1 of the PCI command register enables the Ethernet interface to respond to accesses to the PCI Memory or I O Address space respectively VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 209 Section 8 SCSI Ethernet controller SYM53C885 registe
126. SOURCE www artisantg com Section 2 Getting Started Installing PMC cards Installing PMC cards VSS4 s I O expansion is provided by PMC PCI Mezzanine Card cards This chapter describes PMC card installation VSS4 User Guide 39 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 40 Section 2 Getting Started Installing PMC cards VSS4 PMC connectors The VSS4 comes with PMC connectors for direct installation of one PMC card The drawing below shows the location of a PMC card on the VSS4 board PMC card front panel PMC card component side PMC card Hex standoffs component side J lo 4 1 OU CJS CN OONA O O 99 0030 PMC location top view Adding additional PMC cards with the PEX3 expansion board The PEX3 PMC expansion option provides VSS4 with up to three additional PMC slots plus additional SDRAM and Flash memory Refer to Appendix D page 269 for complete PEX3 infor
127. Slave System Controller Sub busses Data Transfer Bus Data Transfer Arbitration Bus Priority Interrupt Bus Utility Bus Notes 1 For VSS4 P1 is 3 row for Rev B or lower boards only 2 Supported in select PowerPC Series models VSS4 VMEbus implementation The VSS4 VMEbus functionality is provided by the Universe II PCI to VME64 bridge interface The Universe II chip provides the VME interface It can do most all VME functions including system controller master and slave single and block transfers and interrupt generation and handling It cannot do read modify write RMW cycles The VSS4 has two functional modules involved with bus ownership the system controller and the Universe requester The system controller resides in the Universe II chip It is enabled when the VSS4 is installed in Slot 1 The system controller performs bus arbitration and system reset tasks It is not directly related to the VSS4 s VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions VME64 bus bus requesters All bus requesters in the system use the arbiter in this system controller The Universe requester is used when the Universe VME master function is used i e when the CPU accesses the VMEbus through a Universe VME master window The Universe VME requester has selectable bus request level release mode fair mode etc
128. Some boards with older revision levels may have had some of these features added during previous rework upgrades Contact Synergy customer service for upgrade information These paragraphs describe changes made to the VSS4 main board Revision F Revision E Revision D Revision C Revision B Revision A VSS4 User Guide Added power sequencing logic CPU ICE support NVRAM powerdown ramp protection and more ground planes Changed VME bus drivers to use pre buffered 5V power power busses Added tweaks for Universe IIB Upgraded DC DC power converter modules from DCDX to DCMxX type Added full JTAG boundary scan capability support for 21555 PCI PCI bridge and circuitry to synchronize the application of the 5V 3 3V 2V power busses Added support for G4 PowerPC 7400 capacitor backup option for RTC NVRAM watchdog timer 5 row VME64x P1 VME geographical addressing and support for not responding to own VME SysReset Improved CPU heatsink assembly Added system controller config jumpers pull up and pull downs for various signals Ethernet LEDs to lamp test and PO PCI interrupt masking capabilitly Changed Ethernet PHYceiver to LXT970 and Flash registers to new standard Changed interrupts to be more compatible with VGM Series Initial board release 267 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix C Board revision summary RGS3 memory
129. Usrl037 Usrl092 20 Gnd Usrl040 Usrl039 Usrl094 21 Usrl096 Usrl042 Usrl041 Usrl095 22 Gnd Usrl044 Gnd Usrl043 Usrl097 23 Usrl099 Usrl046 Usrl045 Usrl098 4 Gnd Usrl048 z Usrl047 UsrlO100 25 Usrl0102 Usrl050 Usrl049 Usrl0101 6 Gnd Usrl052 Usrl051 UsrlO103 27 UsrlO105 UsrlO54 Usrl053 UsrlO104 28 Gnd UsrlO56 Usrl055 UsrlO106 29 UsrlO108 Usrl058 Usrl057 Usrl0107 30 Gnd UsrlO60 E Usrl059 Usrl0109 31 UsrlO110 UsrlO62 Gnd UsrlO61 Gnd 32 Gnd Usrl064 5V Usrl063 Notes 1 Pins in this row connect to Expansion PMC 2 s P24 connector pin indicated in parentheses Space is provided in these columns to write in the assigned signals if desired Refer to the applicable PMC module documentation for P2 pin assignments 2 Pins in this row connect to Expansion PMC 1 s P14 connector pin indicated in parentheses Space is provided in these columns to write in the assigned signals if desired Refer to the applicable PMC module documentation for P2 pin assignments 3 This row present only with optional wide 160 pin VMEbus P1 amp P2 connectors VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 289 Appendix D PEX3 PMC expansion option PMC connectors PMC connector P11 P21 amp P31 pinouts
130. _01E0 Interrupt Source 15 Vector Priority register R W 0x1_01F0 Interrupt Source 15 Destination register R W Note Add to base address set during PCI configuration Each interrupt source has an associated vector priority register and a destination register There are 16 sets of these The vector priority register sets up how an interrupt source is detected its priority and its vector address The destination register routes or steers the interrupt source to one or more onboard processors The table below lists the VSS4 interrupt sources active low trigger mode used for all VSS4 interrupt sources Source Owner Notes 0 PCI Int D Note 1 PCI VME Bridge Universe Il Int 4 2 PCI Int B Note 3 PCI Int A Note 4 PCI PErr SErr 5 Mailbox D 6 PO PCI Bridge Interrupts T Mailbox C 8 PCI VME Bridge Universe Il Int 5 9 PCI Int C Note 10 Ethernet 11 SCSI 12 Mailbox B 13 Mailbox A 14 Serial Port B 15 Serial Port A VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 177 Section 6 MPIC Interrupt Controller MPIC registers Notes 1 PCI Int D can be driven by any of the following a Universe Int 3 b PMC Int D c PEX3 Int D d Serial Port D 2 PCI Int B can be driven by any of the following a Uni
131. absesscestusssbstecustatstssussbausistudusssestsssucestbutessuesotbebsd dese botishs E Serial VO address Map rosserae shan ds coscd nck ges yasunqas E E E RNE E Programmable baud rate generator Serial itera iter pts sneinen irinin ARE ERN ERRE CN NAN RNOR Serial interface CONnector ceccecssessscsesssessecsescsecsecssecsecsnccsecsscssessucssecsscesecsucesecsucesecssceuecsecssecasecseecsecsuecseceneeeneeseete Clock Calendat ecssesecseeseecneesneen Non volatile 128K x 8 SRAM NVRAM space allocation Boot Flash ROM DIP EPROM Boot options ae DIPEPROM USE nerenin e a TEA VE a AA nears AANA TE AE E VEA EPROM type COMM BUrati OM as sczssicesccdedssbosscicestbvseseplsdbsanaenccounsassascenessaebscuasansqdedassaenaesdesearcavotemansieel Boot Flash use Block organization WITLI BGM CLAS IG ascii sassvsessecesasasciseczatessebessss uasdsseopleisesseduscnasevasnesoascenschgenasedusisnse ssnsdsapesteastgeasapsisiaecl Additional write protection of Boot Flash 150 Additional Flash memory information e151 User Flash memory uu sessssssecsesecseesseessesseeseecseensecseesecseenseness 153 Introduction 153 Block organization 154 Baii2S leCti OM sysscssdesecsscececssvcantzessas vines de desravesedecd vaesacsdnvaasaasccas EN OER EE 154 WHYriting a NGHORASING vsecsczssaxsasreacorssvessstetstneescersarstasnstsinaicceanisnraumiaarnnaeatimanasn i aeaLTa mn MnRRIEY 156 Additional Flash memory information cssessees
132. ace 0 0xC000_0008 Flash Configuration register D8 RO Space 0 0xC000_000C DRAM Configuration register D8 RO Note Flash write width depends on device type mode and address PMC PCI interrupts A PEX3 PMC responds to and generates certain PCI interrupts depending on the PMC slot in which it is installed The table below lists the PEX3 PMC slots associated PCI interrupt lines PEX3 PCI interrupts Slot 1 A Slot 2 B Slot 3 C SBC PCI Bus IntD IntC IntB IntA IntA IntD IntC Int B IntB IntA IntD IntC IntC IntB IntA IntD VSS4 User Guide For example if a board in PEX3 s Slot 1 drives its IntA line it will be mapped to the SBC s PCI IntB input This is an interrupt rotation of 1 Slot 2 rotates 2 IntA assertion gets mapped to SBC s PCI IntC input and Slot 3 rotates 3 IntA assertion gets mapped to SBC s PCI IntD input Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option PCI Type O configuration and address The table below lists the PEX3 s PCI configuration PEX3 PCI Type O configuration Device Number ID Select Bus Master no Owner PCI Config Address 0 16 0 PMC Slot 1 A 0x800n_0000 1 17 1 PMC Slot 2 B 0x800n_0800 2 18 2 PMC Slot 3 C 0x800n_1000 3 19 3 Flash 0x800n_1800 Notes 1 n PCI Secondary Bus number for PEX3 2115
133. ache is a two way set associative tag memory with 8K tags per way The tags are sectored depending on L2 cache size A 1 MB L2 cache supports 2 cache line blocks per tag entry 2 sectors 64 bytes A 2 MB L2 cache supports 4 cache lines blocks per tag entry 4 sectors 128 bytes Because the cache runs at or near the CPU core frequency and has its own bus to the cache SRAMs the 750 7400 7410 s performance is noticeably improved over similar processors running at the same speed When a CPU read memory access is detected 1 It looks in its L1 cache to service the CPU request If not in L1 it looks in L2 2 If what the CPU wants is in either L1 or L2 it s a hit and the CPU fetches the data without using a memory access cycle 3 Ifthe requested data is not in either L1 or L2 cache it s a miss and the CPU accesses the main memory for the data using the Grackle VSS4 User Guide 127 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Backside L2 cache controller For a memory write the backside L2 cache will copy back the write 1 The CPU due to an L1 cache castout writes data to memory so it thinks 2 The backside L2 cache captures the write and stores the data 3 If the L2 cache write caused an L2 castout because that cache line was already used then the L2 cache writes copies back the previous data to
134. ailability Board Support Package BSP Linux and VxWorks Synergy Microsystems Linux and VxWorks BSP distribution includes sample software for PO PCI o Contact Synergy Customer Service for more information about these software options VSS4 User Guide 223 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 9 PCI PCI Bridge Interface Software support PO PCI 224 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 10 Warranties amp Service This section provides information on product warranty and support Warranty terms and options Customer service VSS4 User Guide 225 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 226 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 10 Warranties amp Service Warranty terms amp options Warranty terms amp options This chapter describes the warranty terms and options provided for the VSS4 SBC Warranty terms Synergy Microsystems Inc warrants all standard off the shelf and non standard custom products to be free of defects in materials and workmanship under normal use for the applicable warranty period as described below This limited warranty is void if the failure has result
135. als and documentation RENTALS ITAR CERTIFIED D a gaa tia Contact us 888 88 SOURCE sales artisantg com www artisantg com
136. alue Bit assignments Bit s Function Values b7 b2 Reserved a bi System Error SErr 0 not asserted 1 asserted b0 Parity Error PErr 0 not asserted 1 asserted To maximize the use of available MPIC interrupts the local PCI parity and system error signals are combined into one interrupt source Int 4 When this interrupt source is asserted the PCI error register tells the CPU the type of error parity or system originally generated by the local PCI PO PCI interrupt assert pending register OxFFEF_FE68 RV Bit 7 6 5 4 3 2 1 0 x Reset value Bit assignments Bit s Function Values b7 PO PCI Bridge Interrupt read only 0 not asserted 1 asserted b6 Reserved b5 PO PCI System Error read only 0 not asserted 1 asserted b4 PO PC Parity Error read only 0 not asserted 1 asserted b3 PO PCI Interrupt D 0 not asserted 1 asserted b2 PO PCI Interrupt C 0 not asserted 1 asserted bi PQ PCI Interrupt B 0 not asserted 1 asserted bd PO PCI Interrupt A 0 not asserted 1 asserted Setting b3 b0 of the PO PCI interrupt assert pending register asserts a PCI interrupt Int A D on the PO side of the PCI PCI bridge Clearing b3 b0 deasserts the corresponding interrupt A read of this register returns the current state of
137. and makes this information available to programs running on the computer system the simultaneous transmission of Ethernet packets by two or more Ethernet nodes resulting in a garbled transmission A collision occurs when two Ethernet nodes attempt to send a packet at the same time Collisions are handled with the CSMA CD protocol Central Processing Unit central controlling device in a computer system Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CRT data broadcasting DB 9 DB 25 DCE differential DMA DRAM DTE DUART dual ported dynamic RAM ECO VSS4 User Guide Glossary Cathode Ray Tube normally refers to a viewing screen also used as a synonym for terminal a bus communications technique in which a single CPU board can send data to multiple CPU boards at the same time a D shaped serial interface connector for I O cabling that provides access to up to 9 separate lines or pins on a matching connector a D shaped serial interface connector for I O cabling that provides access to up to 25 separate lines or pins on a matching connector Data Communications Equipment the end of a serial communications link that is or mimics a modem opposite of DTE a method of signaling in which two wires are used each carrying opposite versions of the signal information This is done to increase maximum cable drive and to incre
138. antg com Appendix D PEX3 PMC expansion option Note that if the DRAM needs to be accessed by multiple threads use a wrapper routine and a window ownership semaphore to manage it PEX3 connector pinouts Because the VME P2 connectors have user defined pins make sure that your backplane s P2 connectors are compatible with the PEX3 s P2 wiring before powering up the board Failure to observe this warning can cause the complete destruction of many on board components and also voids the product warranty VSS4 User Guide 287 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 288 Appendix D PEX3 PMC expansion option VMEbus connectors P71 amp P2 VMEbus P1 connector pinouts Pin Row Z Row A Row B Row C Row D 1 5V 2 Gnd Gnd 3 4 Gnd BGO 5 BGO 6 Gnd BG1 7 BG1 8 Gnd BG2 9 Gnd BG2 Gnd 10 Gnd BG3 11 Gnd BG3 12 Gnd 3 3V 13 14 Gnd 3 3V 15 Gnd 16 Gnd 3 3V 17 Gnd 18 Gnd 3 3V 19 Gnd 20 Gnd Gnd 3 3V 21 IAck 22 Gnd IAck 3 3V 23 Gnd
139. aphical Address 0 invalid 1 valid b4 b0 Binary Encoded Slot Number 1 slot 1 2 slot2 l i 21 slot 21 A byte read of this register returns information on the board s VME64x slot number assignment The five lower order bits make up the binary encoded slot number Additional bits show whether or not the VME64x geographical address is valid and the source of the slot number assignment board s jumper field JO2L or board s geographical address pins This register present on Rev C or higher boards only VSS4 User Guide 117 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers Status registers VSS4 status registers include Eight bit user switch register Board status register CPU status register Eight bit user switch register OxFFEF_FDOO RO Bit 7 6 5 4 3 2 1 0 Reset value Bit assignments Bit s Function Values b7 Switch 7 0 Off 1 On b6 Switch 6 0 Off 1 On b5 Switch 5 0 Off 1 On b4 Switch 4 0 Off 1 On b3 Switch 3 0 Off 1 On b2 Switch 2 0 Off 1 On b1 Switch 1 0 Off 1 On b0 Switch 0 0 Off 1 On A read of this register shows the setting of the 8 position front panel switch 118 VSS4 User Guide Artisan Technology Group Quality Instr
140. apsiso Velar SEE 237 PO PCI bus connector PO 245 Memory module connectors PM1 amp PM2 1249 Wide Ultra SCSI connector P264 cseeen 1253 Fast Ethernet connector P240 00 wi2oD Asynchronous serial connector P346 1257 senal VO GADIME airain iar cds SEAE O T E A OE VRT OEE ENEE 259 Appendix B Specifications ssiscccccse ecceues ecscei os vesccieacesecesdsesceuussdseeessszsectedeseceetsesteuesecseetes 263 Ber CNY O Utes sasc cache ana a a a a aa 264 Appendix C Board revision SUMMALY scccessssccccnsssecccnsssccccasssccceasssccceasssccceaseseeeeees 267 Appendix D PEX3 PMC expansion option sscccssssscccsssssccccssscccessscccesssecceassseeeeees 269 FOAtUICS sescsssssssssssssessssssssesssssasesseassssesbssestessosoeise 1 269 Block diagram 270 Board layout 271 Front panel layout unaa Configura Nera E ER I E EREE IE T A E TRGE 273 Flash Write prote Ct sss sscesesssscessusscesecuseseznvsteseveatassvavetsssvsscustvesssetavessecvsgcusavosscecyaaoapestsaansaasnesadatereuenasaties 273 Installation 274 installing PMC Cardis ASAR 274 PSTK PSTRiaGapters csitccsssessssussasssssssesstecssesncesvbccessncovthessssussndusd nsuesnecoodcnceivsatsvestasdebaielbestacisaaanstantesaste 274 PMC stacking and P2 I O routing 278 PMC P2 I O restriction sesse 1 278 Operation 1 280 Address map 280 PMC PCI interrupts ceeeeeeeeeeeeeee 280 PCI Type O configuration and address ecssecsesse
141. apter Address map for more information on the address map structure Configuration registers Using CHRP address map B the base address of the Grackle chip is OxFECO_0000 Address Register OxFEEO_O000 Data Register The OS initialization software sets up the MPC106 in the PCI configuration space header The PCI configuration space header format is shown below Note that Grackle operates in PCI memory space only write 2 0x0010 to command register to enable PCI memory access Access Grackle s configuration registers OxOO OxFC by writing Ox8000_00XX to OxFECO_0000 then reading or writing 32 bits only to from address OxFEEO_0000 In both cases the data must be byte reversed as the PCI bus uses little endian bit format whereas the PowerPC bus uses big endian bit format VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC MPC106 PCI bridge memory controller 31 16 15 0 Device ID Vendor ID 0x00 0x0002 0x1057 Status Command 0x0000 0x04 Class Code Subclass Code Standard Revision ID 0x08 Programming BIST Control Header Type Latency Timer Cache Line Size 0x0C MAX GNT MIN GNT Interrupt Pin Interrupt Line 0x3C Disconnect Cntr Subordinate Bus No Bus Number 0x40 Special Cycle Address 0x44
142. architecture in which the RAM can be accessed from several busses Most Significant Bit a unit of data four bits in length Sometimes spelled nybble nanosecond one billionth 10 9 of a second Non Volatile RAM RAM that retains its data even without external power output from a compiler or assembler that is in machine language but still must be linked to other object code to form an executable program the mandatory 96 pin VMEbus connector It carries all the signals to allow transfers up to A24 and D16 On a 3U board it is the only connector the secondary 96 pin VMEbus connector on 6U of 9U boards Thirty two of its pins carry the signals necessary to allow A32 and D32 transfers The other 64 pins are user definable the smallest unit of memory which is mapped by the MMU a 68 pin high density connector SCSI cable with 50 mil 1 27mm pin spacing The P cable which is defined in the SCSI 3 specification comes in two varieties external MiniD68M connector and internal high density ribbon cable Peripheral Connect Interface an electrical specification describing a 32 bit wide multiplexed data address bus which is commonly used to connect peripheral chips to a processor through a bridge chip PCI Mezzanine Card a type add on mezzanine I O card that plugs into a VMEbus Single Board Computer s PCI bus a microprocessor or architecture based on Motorola IBM s 32 bit RISC design CPU core
143. ard cage for your SBC PEX3 combo A N PEX3 does not support the VITA 32 extension Processor PCI Mezzanine Cards including Second Agent support to IEEE 1386 1 Therefore PMCs that use IDSelB e g PMCs with two PCI devices onboard are not supported by PEX3 PMC PEX3 installation Required hardware item Quantity Synergy part Item locator in assy number description 4 Fas HSM25F3S1HA Hex standoff M2 5 thread female 3 16 OD 1 2 inch long 6 8 Fas SwM25PS12S Screw M2 5 thread pan head slotted 12 mm long steel 6 2 Fas SwM25PS14S Screw M2 5 thread pan head slotted 14 mm long steel O 16 Fas SwM25PS6S Screw M2 5 thread pan head slotted 6 mm long steel Qty is 4 ea per PMC card Allow 2 ea to secure the PSTK or PSTR adapter PSTK PSTR adapters The PEX3 expansion carrier board can stack on top of an installed Synergy PMC for additional PMC expansion The Synergy PSTK or PSTR adapter lets the PEX3 connect to the SBC without the need for a Synergy PMC Refer to PMC stacking and P2 I O routing page 278 for details on stacking and the use of the PSTK PSTR adapter VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option PMC card front panel see Detail below Filler panel remove Front Panel Detail Slot 1 Position front panel cs see Detail
144. ary Power down the system and remove the VSS4 CPU board from the card cage Synergy SBCs contain static sensitive devices Make sure you are properly grounded by putting on a ground strap touching a system ground such as a metallic chassis or case etc before removing and handling the board Use an ESD protected workstation for module removal and installation work Remove existing RGS3 memory module from CPU motherboard if you are replacing refer to RGS3 module installation drawing below for assembly details a Place VSS4 RGS3 assembly face down that is with large circuit board motherboard on top on a flat surface of an ESD protected workstation b Remove four M2 5 slot head screws from rear solder side of VSS4 motherboard See Location memory module securing screws drawing below c Turn VSS4 RGS3 assembly over d Grasp RGS3 sides at connector end toward SBC front panel and gently pull up until the connector comes loose rocking back and forth may help Install RGS3 module on motherboard Installation of RGS3 memory module is reverse of removal Refer to RGS3 module installation drawing below for assembly details VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 35 36 Section 2 Getting Started Installing the RGS3 memory module The SBC memory module connector is fragile To avoid connector damage make sure that
145. ase noise immunity For example a pair of signals are called SD0 and SDO A 1 data bit may be represented by 5V on SDO and OV on SDO and a O bit by OV on SDO and 5V on SDO See single ended Direct Memory Access a data transfer method in which data can pass between peripheral devices and memory without intervention by the CPU Dynamic Random Access Memory high density fast access memory storage media that must be refreshed at continuous intervals Also simply referred to as RAM Data Terminal Equipment the end of a serial communications link that is or mimics a terminal or printer opposite of DCE Dual Universal Asynchronous Receiver Transmitter see UART a memory architecture which allows more than one access path to memory see DRAM Engineering Change Order an engineering document that describes and orders a change to a released product Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 297 Glossary Endian EPROM Ethernet Fast Ethernet FIFO Flash memory floating point FPU GPS receiver IAck IBM 298 VSS4 User Guide refers to the addressing of individual bytes within a 16 32 or 64 bit number Byte ordering that begins with the highest order byte as Byte 0 is referred to as Big Endian Byte ordering that begins with the lowest order byte as Byte 0 is referred to as Little Endian The programming community borrowe
146. ating environment architecture registers This model includes all the registers In this model the time base facility registers are read write VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC PowerPC architecture SUPERVISOR MODEL OEA USER MODEL VEA Configuration Registers N m Hardware Processor Version Machine State Registe Time Base Facility For Reading Implementation Register es TBL TBR 268 TBU TBR 269 Registers PyR sprog7 Ld HIDO SPR 1008 Processor ID Register USER MODEL UISA HID1 SPR 1009 Count Register General Purpose 2 o SPRS Registers Memory Management Registers GPRO Instruction BAT Data BAT Segment XER Registers Registers Registers XER SPR 1 ail IBATOU R 528 DBATOU SPR 536 SRO Link Register IBATOL R 529 DBATOL SPR 537 SR1 LR SPR 8 IBAT1U R 530 DBATIU SPR 538 GPR31 i Performance IBATIL R531 DBATIL SPR 539 Monitor Registers Floating Point IBAT2U R 532 DBAT2U SPR 540 1 Registers Performance Counters IBAT2L R 533 DBAT2L SPR 541 FPRO UPMC1 SPR 937 IBAT3U R 534 DBAT3U SPR 542 UPMC2 SPR 938 FER IBAT3L R 535 DBAT3L SPR 543 MSR PIR SPR 1023
147. ation headers contain the 64 byte Type O configuration header corresponding to that interface The device specific configuration registers are specific to the 21554 some of which apply to the primary interface others to the secondary interface and some to other 21554 functions Access to the 21554 configuration registers is supported from both the primary PO PCI and secondary onboard PCI interfaces Normally however access to the 21554 configuration space is allowed from the secondary interface only In this case the 21554 returns target retry to all accesses initiated on the primary bus with the exception of accesses to the Reset Control register at Dword OxD8 Clearing the Primary Lockout Bit in the Chip Control O register allows access to 21554 configuration space from the primary side VSS4 User Guide 221 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 222 Section 9 PCI PCI Bridge Interface Configuration PCI configuration The operating system PCI discovery routines dynamically set up the 21554 base address by writing to the appropriate registers in PCI configuration address space The host accesses devices behind the bridge i e devices outside the local PCI bus with Type 1 PCI configuration accesses which contain extra data for bus number and device number Type 1 accesses are intended for PCI PCI bridges only If a bridge detects that the bus number is not
148. ay to ensure that no overlap occurs with other stations that may also be retransmitting their data A packet less than the minimum size 512 bits is considered a collision remnant and is ignored by the receiving station Interchange signals Ethernet uses differential driver circuits for its interchange signals For the onboard 10 100Base T interface the transmit data and receive data signals are transformer coupled internally on the SBC and routed to the VSS4 front panel RJ 45 jack The table below lists the interchange signals and their pin assignments on the RJ 45 jack Ethernet interchange signals RJ 45 pin assignments P240 RJ 45 Pin IEEE 802 3 Name Function Signal from 1 DO Data Out 2 DO Data Out Transmit Pair VSS4 3 Dl Data In 6 DI Data In Receive Pair External Device i 2 3 4 5 6 7 8 Ethernet 10Base T 100Base TX connector pin numbering VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 82 Section 3 Basic Bus Descriptions Fast Ethernet interface LED indicators The VSS4 Ethernet interface is provided with three onboard LED indicators for quick port status indication Link OK lights up green when cable is connected to a functioning 10Base T 100Base TX network Link Activity flickers yellow whenever data is being received or transmitted If the VSS4 is connected to a re
149. c set up The PCI 9080 set up for PEX3 is summarized below Since PCI 9080 setup is done by Synergy s SMon software and or BSP OS Linux VxWorks the following is provided for information only The PEX3 PCI 9080 operates in C bus mode separate nonmultiplexed 32 bit address amp data busses with no local masters i e no Req used on the local bus Refer to the PLX PCI 9080 datasheet for Yi detailed device information The PCI 9080 datasheet is available as a PDF file from the PLX Technology website www plxtech com The PCI 9080 has three local address spaces of which two are used by the PEX3 Space O and Space 1 Space O is used for Flash memory in operation mode and capability register space at driver initialization time o BTerm and Burst disabled and READY Input enabled hardware wait states Read ahead disabled during programming enabled during operation if so configured Local base address 0x0000_0000 for Flash OxCOO0_0000 for registers Space 1 is used for SDRAM memory BTerm and Burst enabled and READY Input enabled hardware wait states Read ahead enabled if so configured Local base address 0x4000_0000 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Registers Appendix D PEX3 PMC expansion option In addition to the PCI configuration registers the 9080 chip has these groups of registers
150. ce they all speak the same high level language when communicating with the host History The SCSI interface started life as SASI Shugart Associates Systems Interface a joint development between Shugart Associates and NCR In late 1981 SASI was submitted to the ANSI X3T9 standards committee as a proposed interface standard The standards committee renamed the interface SCSI and in June 1986 SCSI was finally made an ANSI standard with the publication of specification X3 131 1986 This particular 8 bit SCSI was later referred to as SCSI 1 A fast wide SCSI interface referred to as SCSI 2 was then designed with increased throughput of up to 20 MB S The SCSI 2 interface was finally approved by ANSI on January 31 1994 and designated as specification X3 131 1994 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 68 Section 3 Basic Bus Descriptions SCSI bus Even before the release of the SCSI 2 standard work on SCSI 3 began in 1993 It became apparent to the standards committee that a variety of technology i e new serial interfaces for desktop and high performance environments was vying for inclusion in the SCSI spec As a result the SCSI 3 standard was turned into layers similar to a networking standard so that parts which were fast changing could be isolated and standardized on different schedules Since the creation of SCSI 3 the confusion surroun
151. coded in bit serial form and encapsulated in a basic unit called a frame packet The frame packet is made up of seven fields in which the data field is bracketed by several bytes of information The figure below shows the format of an Ethernet frame iu Bits within byte transmitted LSB first except FCS Preamble SFD Destination Source Length Data FCS 62 bits 2 bits 6 Bytes 6 Bytes 2 Bytes 46 1500 Bytes 4 Bytes Ethernet Frame Packet Format The packet fields are summarized below Preamble is a series of alternating 1 s and O s that serve to synchronize the clock and other circuitry on all the receivers and repeaters on the network Start of Frame Delimiter SFD consists of two consecutive 1 s to signal the start of a frame Destination six bytes to indicate the destination of the packet on the network Source six bytes to indicate the node that sent the packet Length two bytes to indicate the number of bytes contained in the data field Data 46 1500 data bytes Stations that need to send less than 46 bytes of data must pad the data to reach the minimum requirement Stations that need to send in excess of 1500 bytes of data must send multiple frame packets Frame Check Sequence CRC value of packet not including preamble and SFD fields for error detection Receiver rejects the frame if the calculated CRC value of the received data does not match the transmitted CRC value
152. ctors VMEbus connectors P71 amp P2 VMEbus P1 connector pinouts Pin Row Z Row A Row B Row C Row D 1 DO BBsy D8 5VPrecharge 2 Gnd D1 BCIr D9 Gnd 3 D2 ACFail D10 4 Gnd D3 BGOIn D11 5 D4 BG0Out D12 6 Gnd D5 BG11n D13 7 D6 BG10ut D14 8 Gnd D7 BG2in D15 9 Gnd BG2Out Gnd GAP 10 Gnd SysClk BG3In SysFail GA0 11 Gnd BG3Out BErr GA1 12 Gnd DS1 BRO SysReset 3 3V 13 DS0 BR1 LWord GA2 14 Gnd Write BRa2 AM5 3 3V 15 Gnd BR3 A23 GA3 16 Gnd DTAck AMO A22 3 3V 17 Gnd AM1 A21 GA4 18 Gnd AS AM2 A20 3 3V 19 Gnd AM3 A19 20 Gnd IAck Gnd A18 3 3V 21 lAckln A17 22 Gnd IAckOut A16 3 3V 23 AM4 Gnd A15 24 Gnd A7 IRg7 A14 3 3V 25 A6 IRqg6 A13 26 Gnd A5 IRg5 A12 3 3V 27 A4 IRg4 A11 LIN 28 Gnd A3 IRq3 A10 3 3V 29 A2 IRq2 A9 LIO 30 Gnd A1 IRqg1 A8 3 3V 31 12V 12V Gnd 32 Gnd 5V 5V 5V 5VPrecharge Notes 1 This row present only with optional wide 160 pin VMEbus P1 amp P2 connectors not available for VSS4 assembly Revision B or lower 234 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors VMEbus connectors P71 amp P2 VMEbus P2 connector pinou
153. d 5V Vcc supply from backplane threshold is 4 75V o 3 3V DC DC converter output threshold is 3 15V o 2 0V CPU core DC DC converter output threshold value is dependent on core voltage used set at factory For VSS4 Rev C or higher the 5V Vcc line has an additional power monitor provided by the DS1232 micromonitor chip whose main purpose in the VSS4 is to provide the watchdog timer function see below The power monitor threshold for this chip is 4 5V which provides a backup monitor for the primary Vcc power monitor with the 4 75V threshold The power monitor ensures that all bus voltages are at a valid level for reliable operation When powering up the power monitor holds all devices at reset until all voltages rise past the threshold If during the course of normal operation a voltage level should dip below the threshold the power monitor triggers a reset This action avoids the unpredictable nature of operating in a twilight zone Front panel reset switch The front panel reset switch see Front panel in Section 2 page 17 provides the user with a means to manually reset the board or system if board is system controller Push the front panel reset switch handle to the right to reset the board system External VME SysReset Assertion of the VMEbus SysReset signal P1 pin C12 causes a board system reset Note that there is a bit called SysReset Enable that allows the board to prevent itself from being reset by
154. d the Endian terms from the story Gulliver s Travels by Jonathan Swift In Swift s novel there were two ways of breaking eggs before eating them People who broke their eggs from the large end were called Big Endians people who broke their eggs from the small end were called Little Endians Erasable Programmable Read Only Memory a special type of PROM whose programming can be erased by exposure to ultraviolet light and then reprogrammed a high speed 10Mb sec communications protocol and cable standard for computer networks see 100BASE T First In First Out a data storage technique in which the first item stored in memory is also the first item on the stack of items for retrieval Also a piece of hardware that stores data in such a manner a nonvolatile random access and rewritable solid state storage technology that is ideal for field upgradeable code storage Flash memory is electrically erased and programmed in circuit method to represent numbers using the significant digits mantissa multiplied by the base of the number raised to the appropriate power exponent Values expressed in floating point form are similar in structure to number expressed in scientific notation Floating Point Unit a floating point co processor a radio receiver that locks onto the GPS Global Positioning System satellites in orbit around the earth Using a GPS receiver you can pinpoint your exact location anywhere on ear
155. data width and clock speed doubled to 64 bits and 66 MHz respectively for a maximum data transfer rate of 528 MB sec in the real world actual rate will be lower due to bus latency times Various clarifications and enhancements to PCI 2 1 were subsequently included in the PCI 2 2 specification The PCI 2 3 specification migrated the PCI bus from the original 5V signaling to a 3 3V signaling bus and included some changes in the system board keyed connector support PCI performance received yet another boost with the PCI X specification which provided a path for ever increasing bus speeds starting at 133 MHz or 1 GB s The PCI bus processor independence has caused the interface to gain in popularity as a solution to providing cost effective high performance peripheral interconnections regardless of the processor or platform used Key features of PCI Multiple busmasters on the same bus with bus mastering a device can take control of the bus and provide main memory 1 O without CPU intervention VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 62 Section 3 Basic Bus Descriptions PCI bus Auto configuring all components plugged into the PCI bus can be automatically detected and configured for use during the system startup routine Interrupt IRQ sharing the PCI bus is able to share a single interrupt between cards PCI devices High
156. ddress Map ROMBoot Address Device address space description Access FFE0_0000 FFE7_FFFF Boot Flash ROM lower half D8 RW D64 RO FFFO_0000 FFF7_FFFF EPROM 512 KB D8 RW D64 RO FFF8_0000 FFFF_FFFF Boot Flash ROM upper half D8 RW D64 RO Note 2 Mailbox writes are done by writing an 8 bit value to memory To ensure proper operation disable cache for page 0 of memory Note 3 User Flash is selected by setting bit 7 of the Flash Window Register OxFFEF_FE50 This register also addresses a particular 512 KB bank of User Flash The number of available User Flash banks depends on the amount of User Flash installed in the system User Flash and the upper 512 KB of Boot Flash cannot be accessed at the same time Access routines in application programs must be mutually exclusive when both Boot Flash and User Flash are used 112 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers Onboard registers This chapter describes the contents and use of the onboard registers that monitor and control the operation of various features and functions on VSS4 boards All registers described in this chapter are 8 bits wide and limited to PowerPC bus accesses only The onboard registers fall into one of three categories o Board information registers are read only registers that provide the system with
157. de bits defined 295 base address defined 296 battery NVRAM clock calendar 144 BCD defined 296 bit numbering conventions 10 block diagram 21554 microarchitecture 220 PCI PCI bridge interface 218 PEX3 optional expansion board 270 PowerPC with AltiVec G4 91 reset sources 160 Universe Il PCI VME bridge 186 VMEbus interface 59 VSS4 6 VSS4 User Guide Artisan Technology Group Quality Instrumentation Index BLT defined 296 improving performance 195 board information registers 114 board layout PEX3 271 RGS3 266 VSS4 265 Boot Flash 145 148 additional write protection 150 write protect 149 boot ROM enable jumper 25 147 boot selection 146 147 bridge defined 296 byte swapping 65 cache line defined 296 cache memory defined 296 capacitor backup option specifications 264 category 3 defined 296 category 5 defined 296 CHRP address map 105 clock calendar calibrating 140 defined 296 collision defined 296 configuration default hardware configuration 23 connectors CRJ4 serial adapter pinout 261 305 Guaranteed 888 88 SOURCE www artisantg com Index PO pinout 247 P1 13 motherboard defined 300 P1 VME PEX3 pinout 288 P11 P21 P31 PEX3 pinout 290 P11 P15 pinout 237 P12 P22 P32 PEX3 pinout 291 P13 P23 P33 PEX3 pinout 292 P14 PEX3 pinout 293 P2 14 P2 motherboard defined
158. ding SCSI standards has increased SCSI 3 is defined in a collection of about 30 different standards woe VSS4 s Wide Ultra Fast 20 SCSI yj interface is defined in ANSI standard X3 277 1996 which is an addendum to the SCSI 3 Parallel Interface SPI standard Two organizations exist to maintain and promote the SCSI standard o SCSI Trade Association STA This industry trade organization communicates the benefits of SCSI For more information on this organization refer to the STA website http www scsita org T10 National Committee on Information Technology Standards NCITS Technical Committee This is a standards committee that promulgates low level interface standards This group works with industry members to gain consensus on the low level interface rules These rules start out as draft standards that eventually become ANSI standards For more information on the T10 committee refer to the T10 home page on the web http www t10 org To keep pace with improvements in computer technology SCSI continues to evolve with wider data paths and increased transfer speeds The table below lists the current varieties of the SCSI interface as given by the SCSI Trade Association VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions SCSI bus List of SCSI types SCSI Trade Organization
159. dispatch register Current task priority register Interrupt request register implementation specific non program accessible Interrupt acknowledge register VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 179 180 Section 6 MPIC Interrupt Controller MPIC registers In service registers implementation specific non program accessible o End of interrupt register The following describes the bit assignments of the Per Processor registers Not included are the implementation specific non program accessible registers interrupt request and in service registers For these registers refer to the MPIC data manual for more information Interprocessor Interrupt Dispatch registers There are 4 interprocessor interrupt IPI dispatch registers 0 3 per processor Writing to an IPI dispatch register causes an interprocessor interrupt request to be sent to one or more processors A processor is interrupted if the bit in the IPI dispatch register corresponding to that processor is set during the write Reading these registers returns zeros 31 2 0 Reserved Scud w NCUO lt cvd lt cCVO Address map interprocessor interrupt dispatch registers Select Processors 3 0 Address Offset Register Access 0x2_0040 IPI 0 dispatch register processor 0 R W
160. dix A Connectors amp Cables This appendix contains descriptions and diagrams of the VSS4 connectors and specialized cabling o VMEbus connectors P1 amp P2 o PMC connectors P11 P15 PO PCI bus connector PO Memory module connectors PM1 amp PM2 Wide Ultra SCSI connector P264 Fast Ethernet connector P240 Asynchronous serial connector P346 o Serial I O cabling VSS4 User Guide 231 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 232 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors VMEbus connectors P71 amp P2 VMEbus connectors P7 amp P2 The VSS4 s P1 and P2 connectors provide the standard I O interface to the VMEbus as listed in the tables below ge The P1 connector is the standard 3 row Yi type for board revision B or lower For board revision C or higher the VME64x 5 row connector is optionally available for P1 The P2 connector shows the signals Synergy has assigned to the user de fined pins for rows A and C and Z and D for 5 row option on the standard VMEbus These rows are connected to the PMC I O P14 amp P15 connectors listed later in this chapter VSS4 User Guide 233 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Conne
161. dor ID 0x2C Expansion ROM Base Address 0x30 Reserved 0x34 Reserved 0x38 Max Lat Max_Gnt Interrupt Pin Interrupt Line 0x3C Shown above is a typical layout of a PCI configuration header Symbios Logic s Ethernet interface It contains the following fields VSS4 User Guide 63 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 64 Section 3 Basic Bus Descriptions PCI bus S 9 S S S S Vendor Identification A unique number describing the originator of the PCI device Symbios Logic s PCI Vendor Identification is 0x1000 Device Identification A unique number describing the device itself In the example above Symbios Logic s Fast Ethernet device has a device identification of 0x0701 Status This field gives the status of the device with the meaning of the bits of this field set by the PCI Local Bus Specification Command By writing to this field the system controls the device for example allowing the device to access PCI I O memory Class Code This identifies the device category There are standard classes for every sort of device video SCSI and so on The class code for SCSI is 0x0100 Base Address Registers These registers are used to determine and allocate the type amount and location of PCI I O and PCI memory space that the device can use Interrupt Pin Four of the physical pins on the P
162. e allows PCI bus mastering for fast memory accesses Typical uses include any combination of Expansion RAM Expansion Flash Buffer for a PMC I O board with DMA Buffer for a passive target only PMC I O board If a given PCI window is at least as large as the memory behind it no windowing control is needed all of the memory is directly accessible For smaller windows the 9080 s Local Base Address register must be adjusted Reading the Flash is similar to reading PEX3 SDRAM i e both are accessed through a window Writing to Flash however requires special code The PowerPC Series SMon monitor includes a full set of Flash commands The Flash driver is also available from Synergy Contact Customer Service for more information VxWorks BSP PEX3 driver Synergy s VxWorks BSP includes a PEX3 driver named exmem The header file for it is exmem h To include the driver in the kernel define INCLUDE_EXMEM The driver is initialized on startup The PEX3 Flash and DRAM are accessed through a PCI window The window size is stored in the PEX3 s PCl configuration EEPROM Use the wrEEPEX3 SMon routine to change the size of this window as required Access the DRAM window by first calling exmemDRamAdr with a DRAM offset This points the window to that section of DRAM and returns the actual access address VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artis
163. e current count decrements to zero Global Timer Base Count register Base Count Base Count This field contains the 31 bit base count for this timer The current count is loaded with the base count and the toggle bit in the Current Count register is cleared whenever the Base Count register is VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 175 176 Section 6 MPIC Interrupt Controller MPIC registers wo a wo oO written and the Count Inhibit bit transitions from 1 to a 0 The timer decrements while the Count Inhibit bit is zero When the timer counts down to zero an interrupt is generated the toggle bit in the Current Count register is inverted and the current count is reloaded from the base count C Count Inhibit bit 1 inhibit counting for this timer O0 proceed with counting Reset sets this bit to one inhibit counting Global Timer Vector Priority register 20 19 16 15 8 7 0 Kanz Reserved for Vector Expansion Vector Reserved Priority 31 Vector Interrupt Vector The vector value in this field is returned when the Interrupt Acknowledge register is examined and the interrupt associated with this vector is requested Priority Interrupt Priority This field sets the interrupt priority The lowest priority is O and the highest is 15 Setting the priority level to O disables
164. e filler panel will be one of two types The first type simply snaps in place remove by pushing from the inside The second type is an actual blank PMC front panel remove 2 ea 6 mm M2 5 slot head securing screws from solder side of board to remove see PMC card securing screws location drawing above Ensure that stackable Synergy PMC card or PSTK PSTR adapter is installed on SBC The PEX3 board connects to the SBC via a stackable Synergy PMC card or a Synergy PSTK PSTR adapter Both of these items have connectors on the opposite side of the SBC connectors for mating with the PEX3 board s plug connectors To install a PMC card onto the SBC refer to the PMC card installation instructions in Section 2 page 41 To install the PSTK PSTR adapter plug the adapter onto the SBC PMC connectors then secure with 2 ea screws item 6 as if securing the connector portion of a PMC card See PMC card PEX3 board installation drawing Remove rear stiffener bar if so equipped If the SBC is being fitted with the PEX3 for the first time a stiffener bar will be installed over the VSS4 VME P1 and P2 connectors Remove 4 VSS4 User Guide 277 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 278 Appendix D PEX3 PMC expansion option ea 16 mm securing screws from the VME P1 and P2 connectors Set aside this hardware plus the 4 ea 5 mm standoffs and stiffener bar f
165. e versus that for asynchronous mode The asynchronous data transfer mode is the default normal mode since this mode does not need to be selected All commands messages and status are always transferred asynchronously A synchronous target however can ask the initiator for synchronous transfer of data The initiator responds to this request by either maintaining asynchronous data transfers or establishing synchronous data transfers by an exchange of messages containing the minimum transfer period and maximum REQ ACK offset for each device When synchronous data transfer is established it is done using the greater of the two minimum transfer periods and the lesser of the two maximum REQ ACK offsets The VSS4 SCSI interface supports 8 bit Ultra SCSI synchronous transfers of up to 20 MB s and 16 bit Wide Ultra SCSI synchronous transfers of up to 40 MB s VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 75 76 Section 3 Basic Bus Descriptions SCSI bus VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions Fast Ethernet interface Fast Ethernet interface Ethernet is a LAN local area network architecture that provides the means for computers and other peripherals located in a moderately sized geographical area to communicate with each other at high
166. ection 2 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 1 Overview This section introduces the VSS4 single board computer VSS4 features Manual conventions VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 1 Overview VSS4 features VSS4 features Synergy Microsystems VSS4 is a 6U VMEbus Single Board Computer SBC designed for digital signal processing DSP applications The VSS4 comes bundled with Synergy s library of 450 scientific subroutines SSSL Synergy Scientific Subroutine Library that are hand coded for optimum performance specifically for running on the VSS4 The SSSL library is compatible with MATLAB and provided in VxWorks and PowerPC Linux with realtime extensions versions The VSS4 SBC is based on quad G3 G4 750 7400 7410 PowerPC microprocessors running at up to 533 MHz 7410 A dual CPU version of the board is also available Each processor is provided with a performance boosting 2 MB or 1 MB for G3 backside L2 cache as standard An upgradeable DRAM module provides 32 512 MB of high performance SDRAM memory SCSI Ethernet a PMC slot up to 64 MB of 8 bit User Flash and 128 KB NVRAM give the VSS4 the flex
167. ed However a new or updated PROM is easily added or changed in the field The paragraphs below describe a field installation of a new DIP EPROM and all of the potential configuration changes you may need to make to the VSS4 CPU board as a result If the desired monitor PROM is already YI present on the VSS4 board or if the monitor ROM is programmed into Boot Flash e g VxWorks proceed to the next chapter in this section TT brand EPROMs cannot be used Their requirement for Vcc on unused pins prevents a TI PROM from being used in a general purpose socket EPROMs from other manufacturers such as Intel AMD etc work without problem VSS4 User Guide 29 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 30 Section 2 Getting Started Installing a monitor PROM Materials To complete this procedure you will need the following materials o The desired monitor firmware PROM A 32 pin 0 6 wide DIP extractor tool to remove the current PROM if necessary The manual for the software product on the new EPROM Procedural steps To install a monitor EPROM complete the following procedure Verify proper operation of the motherboard if replacing an ex isting monitor PROM Before attempting to install a new EPROM on an existing board ensure that the motherboard and any attached mezzanine cards are operating properly
168. ed from accident abuse alteration or misapplication by the customer Product returns The following guidelines describe warranty terms for product returns D Initial product acceptance Synergy presumes that customers will inspect products within 14 days of receipt for conformance to the specifications stated in this manual for standard off the shelf units and or purchasing documentation for custom units Products not rejected within this period are considered by Synergy to be accepted by the customer Delivery rejection Products that do not conform to the speci fications and standards in this manual or purchase documents can be returned to Synergy for replacement repair Before returning products notify Synergy of the problem and get a Return Material Authorization RMA number Board rejection will not be valid unless boards are returned in the original ship ping cartons within 10 days of the receipt of the RMA number VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 227 228 Section 10 Warranties amp Service Warranty terms amp options S 9 For more information about returning products see the next chapter on Customer service If the customer adheres to these requirements Synergy agrees to pay shipping charges otherwise shipment costs must be paid by the customer Delivery turnaround after rejection Synergy
169. ed if an interrupt is requested just as the Task Priority register is set to disable interrupts Address map current task priority registers Address Offset Register Access 0x2_0080 Task Priority register processor 0 R W 0x2_1080 Task Priority register processor 1 R W 0x2_2080 Task Priority register processor 2 R W 0x2_3080 Task Priority register processor 3 R W Note Add to base address set during PCI configuration Interrupt Acknowlege registers 16115 8 7 0 Reserved for Reserved Vector Expansion Vector On PowerPC based systems Interrupt Acknowledge is implemented as a read request to a memory mapped Interrupt Acknowledge register There is one Interrupt Acknowledge register per processor Interrupt Acknowledge Returns the interrupt vector corresponding to the highest priority pending interrupt in that processor s Interrupt Request Register Transfers the highest priority pending interrupt from that processor s IRR to that processor s In Service register Clears the bit in the Interrupt Pending Register corresponding to the highest priority pending interrupt in that processor s IRR Note This is effective only for edge triggered interrupts Level triggered interrupts normally cause the bit in the IPR to be set to VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 181 Section 6 MP
170. eed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC User Flash memory User Flash memory Introduction VSS4 boards provide onboard User Flash memory as an option For Rev B or lower boards the size of User Flash is 2 or 4 MB For Rev C the size of User Flash is 4 or 16 MB For Rev D or higher User Flash options are 4 8 16 32 or 64 MB The memory chips have a byte write and block erase architecture with data storage similar to that of a sectored hard disk A typical use of User Flash includes operation as a RAM disk for loading an operating system kernel or accessing other files as needed by the system User Flash memory address location Address Data width Description OxFFF8_0000 OxFFFF_FFFF D8 User Flash 512 KB bank User Flash memory is made up of 1 2 or 4 ea Flash memory chip s used in byte wide mode The table below lists the devices used for the VSS4 s User Flash memory User Flash device Onboard Flash size Manufacturer Part Number Organization no of chips 4 8 MB 1 2 ea Intel 28F320J5 4MBx8 16 32 64 MB 1 2 4 ea Intel 28F128J3A 16 MB x8 VSS4 User Guide 153 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 154 Section 4 Programming the PowerPC User Flash memory Block organization For convenience in programming or erasing the block information for the onboard Flas
171. eiecececcietceseasavcceeusavecdesdacedeessadeedeadavensessaveedsess 1 WSS EEEO N EE EE E A A E E O A E gua Optional PEX3 expansion module 7 VSS4 phiysical Conti GUtatio tives vensscisscscvaceaveccescceussivecsiansaaeteisonerscacesnuarsaiestviin saraaavea SS ENE EEROR Functional ILO CK Ci at AI sessin E asena NSIR Feature summary 5 Manual CONVENTIONS siszccsaxeeasdecersysersqescracteencesvianschicserseesastetonsdettcarusier NTA AEA EE Typographical CONVENtIONS ssssssesssssessessessecsessessecsesneenccucssecsessesscsecsecsecsessesaesnesussucsucesecsesscsscssesaeeaeeaeeneeneenteneensess Notes Chapter s es Bit numbering conventions Web address URL s Mantal COMMONS davai acccsastagesaresdecranisrerniecsiaravisiioenasua EE EE R EA E ISR t Section 2 Getting Started cccccccccccccscccccccccccccccccccccccccccccccceccccccceccceccescceecececeeeeees 11 Minim m system FEQUITEMENES ssssssssssicssssssssssssasssesssssasesesssseasssesnsnsasssesssusessassvensnsscacssusndsnssbsusadsasossnsaseasbstsetbescsesebsesenstesesy 13 Front panel aereoa e A A N A E A E 17 B DIEIUSENSWHECIiscassssansszaseassrssecsiedsesdceseunasessebasehdanasessendeuvesescaacensdctsetussnviesssuobantagatanseayhasscasusdag A 18 Toggle switch 19 LEDS Saen N 20 Lamp test feature s22 Setting up the VSS4 hardware 23 Default configuration 23 Installing jj UA WES vaced sevsezedes aE A OTN TEITE 24 Setting the slot
172. elease 1 0c 11 10 99 Pre GA Release 1 0 3 28 00 GA Release 2 0 2 27 01 All Cleaned up various items as required Section 1 VSS4 features Updated User Flash capacity Section 4 User Flash Memory Updated User Flash capacity Section 7 Added Slave image programming caveat Appendix C Added VSS4 Rev D and E to revision summary Appendix D Deleted PO PCI references 3 0 6 18 01 All Cleaned up various items as required Section 2 App B Updated 12V specification Section 2 Installation notes Added slot installation recommendations Section 3 PCI bus Revised PCI bus discussion configuration SCSI bus Added SCSI 3 info expanded SCSI types table Section 4 Address Map Revised address map information 4 0 4 29 03 All Cleaned up various items as required Added typical power consumption data for 7410 500 MHz board Installing PMC cards All PEX3 info moved to Appendix D Installing a monitor PROM Revised J902 configuration jumper diagram to include Boot Flash Write Protect jumper function see next item below Boot Flash ROM DIP EPROM Added info describing J902 jumper settings for Boot Flash Write Enable Disable applicable only to boards that incorporate ECO specifying this change User Flash Memory Corrected bank address ranges in User Flash bank selection table Added VSS4 Rev F to revision summary Revised PCI 9080 basic setup info Added info on VxWorks BSP PEX3 driver Revised PMC connector pin assignments Added info previously in S
173. ength of up to 25 meters 82 feet For older SCSI interfaces device connections to a particular SCSI bus must be all single ended or differential they cannot be combined on the same bus To protect the differential driver circuits the DIFFSENS signal is provided This signal is a single ended signal that is used as an active high enable for the differential drivers If a single ended device or terminator is inadvertently connected DIFFSENS is grounded which disables the differential drivers by placing them in high impedance state tristate Newer SCSI interfaces that use low voltage differential LVD signaling can operate in multimode to allow a mix of low voltage differential and single ended devices on the bus In multimode the DIFFSENS line is used to differentiate between SE DIFFSENS lt 0 5 V and LVD DIFFSENS 0 7 V 1 9 V When a single ended device is connected to the bus the DIFFSENS line senses the voltage which causes all other attached devices to automatically configure themselves for single ended operation all signal pins grounded Since only SE or LVD buses can accommodate multimode operation HVD devices are not allowed to be connected to an SE or LVD bus The VSS4 SCSI interface is fixed at single ended For connector information refer to Appendix A Wide Ultra SCSI connector page 253 The SCSI signal lines are divided into two basic groups data lines DBO DB15 DBPO and DBP1 and control sig
174. ernal VME SysReset in Section 5 page 161 for details on the use of this register Watchdog enable register OxFFEF_FF40 W O Bit 7 6 5 4 3 2 1 0 xixix xi x x x 0O Reset value Bit assignments Bit s Function Values b7 b1 Reserved b0 Watchdog Enable 0 Watchdog disabled No need to service watchdog 1 Watchdog enabled Periodic writes to Watchdog Pet register see next register description is required to prevent board reset Setting bO of this write only register to 1 enables the watchdog timer function Once watchdog is enabled the application code must periodically write to the watchdog pet register see next to avoid reset An enabled watchdog can only be disabled by a board reset after which bO is automatically set to 0 Refer to Section 5 Reset page 157 for detailed reset information This register present on Rev C or higher boards only VSS4 User Guide 125 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers Watchdog pet register OxFFEF_FF48 WO Bit 7 6 5 4 3 2 1 0 xixix x x x x 0 Reset value Bit assignments Bit s Function Values b7 b1 Reserved b0 Watchdog Service Write alternating 0 and 1 to this bit within 250 ms to prevent board reset This register has no effect if wa
175. es in each 64 minute cycle may once per minute have one second either shortened or lengthened by 128 32768 seconds 3 906 ms If a binary 1 is loaded into the ccccc bits only the first 2 minutes in the 64 minute cycle will be modified if a binary 6 is loaded the first 12 minutes of the 64 minute cycle will be affected and so on If the oscilla tor is running precisely at its nominal frequency 32768 Hz each of the 31 increments in the calibration bits represents 5 35 seconds per average month or more precisely 175 78 ms per day This affords a total calibration range of about 5 4 seconds per day VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Clock calendar The simplest and most accurate method to calibrate the clock is as follows Synchronize the clock to an accurate timing source such as a GPS receiver or WWV radio transmissions from the National Bureau of Standards in Fort Collins Colorado available at 5 000 kHz 10 000 kHz and 15 000 kHz on the AM band Accumulate an error for a few weeks or months if necessary Compare the clock to the original source This procedure yields an accurate correction Even a manual compari son which has an error of a second or more is sufficient to adjust the clock to within a single count of the calibration register VSS4 User Guide 141 Artisan Technology
176. espond to accesses to the PCI Memory or I O Address space respectively 206G VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller SYM53C885 registers Operating registers The table below lists the SYM53C885 SCSI registers which are accessed through PCI memory or I O cycles depending on operation SYM53C885 SCSI registers address and descriptions Addr Offset R W Label Description 0x00 R W SCNTLO SCSI Control 0 0x01 R W SCNTL1 SCSI Control 1 0x02 R W SCNTL2 SCSI Control 2 0x03 R W SCNTL3 SCSI Control 3 0x04 R W SCID SCSI Chip ID 0x05 R W SXFER SCSI Transfer 0x06 R W SDID SCSI Destination ID 0x07 R W GPREG General Purpose Bits 0x08 R W SFBR SCSI First Byte Received 0x09 R W SOCL SCSI Output Control Latch Ox0A R SSID SCSI Selector ID 0x0B R W SBCL SCSI Bus Control Lines 0x0C R DSTAT DMA Status 0x0D R SSTATO SCSI Status 0 Ox0E R SSTAT1 SCSI Status 1 Ox0F R SSTAT2 SCSI Status 2 0x10 0x13 R W DSA Data Structure Address 0x14 R W ISTAT Interrupt Status 0x18 R W CTESTO Reserved 0x19 R W CTEST1 Chip Test 1 0x1A R CTEST2 Chip Test 2 0x1B R CTEST3 Chip Test 3 0x1C 1F R W TEMP Temporary Register 0x20 R W DFIFO DMA FIFO 0x21 R W CTEST4 Chip Test 4 0x22 R W CTEST5 Chip Test 5 0x23 R W CTEST6 Chip Test 6 0x24 0x26 R W DBC
177. essed and VMEbus interrupts can be input to generate a VMEbus lAck cycle and to generate the specified interrupt signal Software interrupts are ROAK while hardware and internal interrupts are RORA Universe II s DMA controller provides high performance data transfer between the PCI and VMEbus Universe II is provided with a set of DMA registers to set up DMA transfer parameters The diagram below shows the general architecture of the Universe Il PCI bus chip DMA Channel Interface Interface i VME l Slave VME i Pea Master PCI Interrupts EE EE I E E A TAE A VMEbus Slave Channel posted writes FIFO prefetch read FIFO m coupled read Interrupt Channel Interrupt Handler Interrupter Register Channel Mailbox Registers ra Master VME i Interrupts VMEbus VSS4 User Guide Universe Il architecture Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Introduction to Universe Il A register overview is given in the next chapter of this section Universe II register reference For detailed information on the Universe II chip refer to the Universe II User Manual and other supporting documentation available on Tundra Semiconductor Corporation s website on the WWW xe wy http www tundra com VSS4 User Guide 187 Artisan Technology Group
178. et o General description PCI reset o Hard reset sources Soft reset VSS4 User Guide 157 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 158 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 5 Reset Reset information Reset information General description A reset of the VSS4 causes the board to reset all processors registers and onboard peripheral devices such as I O controllers and bridges If the board is the system controller the VME SysReset is also asserted to force a system wide reset Once reset the three CPUs Y Z and W are disabled since the MP_ENABLE bit in the MPC106 is cleared by hardware reset CPU X enters the boot state in which it will execute the code at address OxFFFO_0100 in either DIP EPROM 512KB or Boot Flash 1MB depending on the Boot ROM Enable jumper configuration see Section 2 Setting up the VSS4 hardware page 23 The code at this address is typically a jump to the cold start routine which performs the initialization tasks that ready the board facilities for use For Linux boot code must direct the YI processor to go to 0x100 RAM space from address OxFFFO_0100 The MSR_IP bit in the processor s MSR register must also be cleared so that any subsequent soft resets would result in the processor executing boot at 0x100 The above
179. et controller Writing a one to this bit forces the controller logic to be reset This bit is cleared automatically when the reset sequence is complete While this bit is set the values of all other registers are undefined VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 171 172 Section 6 MPIC Interrupt Controller MPIC registers 31 Vendor identification register 24 23 16 15 8 7 0 Reserved Stepping Device ID Vendor ID Vendor ID Specifies the manufacturer of this part For this part the value is 0x14 Device ID Vendor specified identifier for this device Value for MPIC 2A part is 0x46 Stepping Stepping silicon revision for this device Initially 0 Processor init register Select Processors 3 0 31 3 1 0 JAHE Reserved ulululu wjiz Y x Writing to this register b3 b0 causes the INIT lines s to one or more processors to be activated Writing a one to a bit activates the corresponding INIT line Writing a zero to a bit deactivates the corresponding INIT line The INIT lines s are connected to the Soft Reset pin s on PowerPC processors The Soft Reset input on a PowerPC processor is normally edge triggered The Processor Init register is used to perform a soft reset of any or all CPUs on the VSS4 To issue a soft reset to a CPU write a O to the bit corresponding to the CPU to be
180. etc before removing and handling the board Use an ESD protected workstation for module removal and installation work Remove PEX3 board from SBC If not already removed remove the PEX3 from the SBC by removing 4 ea screws item 4 from PEX3 s VME connectors and 2 ea screws item 5 from underneath the SBC at the front eject lever VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option Mount PMC card s to PEX3 board refer to installation drawings above for assembly details a Place PEX3 face up on a flat surface of an ESD protected workstation b If not already on install PMC card s front panel O ring gasket included with PMC card by slipping gasket into groove around front panel c Grasp PMC at sides and place card over PEX3 board s PMC connectors at slot position A B or C Ensure both PMC and PEX3 connectors are aligned then press down over PMC connector area to fully engage PEX3 board connectors d Turn PEX3 board assembly over e Install four 6 mm M2 5 slot head screws item 6 from rear solder side of PEX3 board Two screws engage standoffs on the PMC card The other two screws engage threaded holes in PMC card front panel f Repeat steps b through e for each PMC card to be installed on PEX3 board Remove appropriate PMC filler panel s from SBC PEX3 front panel Th
181. evision Reg D8 RO FFEF_FE08 Special Mod and ECO Level Reg D8 RO FFEF_FE10 Board Family and Feature Register D8 RO FFEF_FE18 Board Status Register D8 RO FFEF_FE20 CPU Status Register D8 RO FFEF_FE28 CPU Timebase Register D8 RW FFEF_FE30 L2 Cache Register D8 RO FFEF_FE38 Memory Register D8 RO FFEF_FE40 Flash ROM Register D8 RW FFEF_FE48 PO PCI Register D8 RO FFEF_FE50 Flash Window Register D8 WO FFEF_FE60 PO PCl Interrupt Mask Register D8 RW FFEF_FE68 PO PCI Interrupt Assert Pending Register D8 RW FFEF_FE70 PCI Error Register D8 RO FFEF_FE80 User LED 0 Register D8 RW FFEF_FE88 User LED 1 Register D8 RW FFEF_FE90 User LED 2 Register D8 RW FFEF_FE98 User LED 3 Register D8 RW FFEF_FEAO User LED 4 Register D8 RW FFEF_FEA8 User LED 5 Register D8 RW FFEF_FEBO User LED 6 Register D8 RW FFEF_FEB8 User LED 7 Register D8 RW FFEF_FF30 VME64 Slot Register D8 RO FFEF_FF38 VME64 SysReset Register D8 RW FFEF_FF40 Watchdog Enable Register D8 WO FFEF_FF48 Watchdog Pet Register D8 WO FFFO_0000 FFF7_FFFF EPROM 512 KB ROMBoot D8 RW D64 RO Note 1 FFFO_0000 FFFF_FFFF Boot Flash ROM 1 MB FlashBoot D8 RW D64 RO Note 1 FFF8_0000 FFFF_FFFF Boot Flash ROM upper 512 KB ROMBoot D8 RW D64 RO Note 1 FFF8_0000 FFFF_FFFF User Flash Bank 512 KB D8 RW D64 RO Note 3 110 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com
182. evision level solder side of board ECO level solder side of board Operating system and Revision level of the Monitor PROM or other PROM EPROM if used on your board The revision level is normally printed on the label of the DIP EPROM if so equipped Purchase order number and billing address if the board is out of warranty Customer contact name address and telephone number Complete description of the problem Carefully package the board to protect it during shipment be sure that it is enclosed in an anti static bag Mark the RMA number on the shipping container Send the board and the requested information prepaid to Synergy at the following address Synergy Microsystems Inc 9605 Scranton Rd Suite 700 San Diego CA 92121 1773 An inspection and test charge will be applicable to all units returned for repair unless the unit is found to be defective and under warranty If the repair charge exceeds the inspection and test charge we will notify you of the repair charge The test and inspection charge will be applied to your repair charge No repair other than test and inspection will be performed on products that are out of warranty until we have received your approval for the charges We appreciate your cooperation with these procedures They help us give you the best possible service VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appen
183. executing posted writes VME Slave Parameter t28 Control PREt28 bit 0 VMEbus slaves must wait at least 30ns after the assertion of DS before driving DTAck low The PREt28 parameter in the U2SPEC register however allows DTAck to be asserted in less than 30ns when executing prefetched reads VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Improving VME performance U2SPEC register bit assignments The U2SPEC bit assignments and descriptions are listed below U2SPEC register offset Ox4FC bit assignments Bits Function 31 24 Universe Reserved 23 16 Universe Reserved 15 08 Universe Reserved DTKFLTR Reserved MASt11 READt27 07 00 Universe Reserved POSt28 Reserved PREt28 U2SPEC bit descriptions Name Type Reset By Reset State Function DTKFLTR R W All 0 VME DTAck Inactive Filter 0 Slower but better filter 1 Faster but poorer filter MASt11 R W All 0 VME Master Parameter t11 Control DS high time during BLT s and MBLT s 0 Default 1 Faster READt27 R W All 00 VME Master Parameter t27 Control Delay of DS negation after read 00 Default 01 Faster 10 No Delay POSt28 R W All 0 VME Slave Parameter t28 Control Time of DS to DTAck for posted write 0 Default 1 Faster PREt28 R W All 0 VME Slave Parameter t28 Control Time
184. for the interrupt under service This will occur if the interrupt request is negated by the source before the vector read cycle is performed by that CPU Only one spurious interrupt register exists so it will be used only for interrupts directed to the CPU to which it is steered Reset sets this register to 0x0000_00FF Global Timer registers MPIC contains four global timers 0 3 suitable for system timing and periodic interrupt generation The four timers share a Timer Frequency Reporting register Each timer has a set of 4 registers for configuration and control and each is readable on the fly Address map global timer registers Address Offset Register Access 0x010F0 Timer Frequency Reporting register R W 0x01100 Global Timer 0 Current Count RO 0x01110 Global Timer 0 Base Count R W 0x01120 Global Timer 0 Vector Priority register R W 0x01130 Global Timer 0 Destination register R W 0x01140 Global Timer 1 Current Count RO 0x01150 Global Timer 1 Base Count R W 0x01160 Global Timer 1 Vector Priority register R W 0x01170 Global Timer 1 Destination register R W 0x01180 Global Timer 2 Current Count RO 0x01190 Global Timer 2 Base Count R W 0x011A0 Global Timer 2 Vector Priority register R W 0x011B0 Global Timer 2 Destination register R W 0x011C0 Global Timer 3 Current Count RO 0x011D0 Global Timer 3 Base Count R W 0x011E0 Global Timer 3 Vector Priority register R W 0x011F0 Global Timer 3 Destination register R W Note Add to base addres
185. from being seen by the board Clearing a bit passes the corresponding interrupt to the board which enables it to act on the interrupt User LED registers OxFFEF_FE amp 8O OxFFEF_FE8 amp 8 OxFFEF_FE90 OxFFEF_FE98 OxFFEF_FEAO OxFFEF_FEA8 OxFFEF_FEBO OxFFEF_FEB8 RW Bt7 6 5 4 3 2 1 0 xixix x x x x 1 Reset value Bit assignments Bit s Function Values b7 b1 Reserved b0 User LED n 0 OFF n 0 1 2 3 4 5 6 7 1 ON There are eight User LED registers one for each user LED A write to one of these registers turns ON or OFF the appropriate user LED A 124 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers read of one of these registers returns the ON OFF status of the appropriate user LED VME64 SysReset register OxFFEF_FF38 RW Bt7 6 5 4 3 2 1 0 x x xi x x x x 7 Reset value Bit assignments Bit s Function Values b7 b1 Reserved _ b0 VME64 SysReset 0 Board does not respond to its own SysReset 1 Board does respond to its own SysReset A write to this register sets whether or not the board responds to its own SysReset A read of this register returns the value of the bits setting this register This register present on Rev C or higher boards only Refer to Ext
186. g that slave s window 200 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 8 SCS Ethernet Controller This section provides information about the SYM53C885 SCSI Ethernet controller interface o General description SYM53C885 registers Programming notes SYM53C885 ye The bit numbering of registers in this z section follows the zero on the right convention as opposed to the zero on the left bit numbering convention used by Motorola and IBM in their PowerPC documentation VSS4 User Guide 201 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 202 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller General description General description The VSS4 SCSI and Fast Ethernet interface is provided by a single multifunction device the Symbios Logic SYM53C885 PCI SCSI Fast Ethernet Multifunction Controller On the SCSI side the SYM53C885 provides a Wide Ultra SCSI interface using a PCI bus master DMA core and Symbios Logic SCSI SCRIPTS processor On the Ethernet side the SYM53C885 provides a 10 100Base T Ethernet interface with independent DMA engines for the transmit and receive channels for access to the motherboard bus and memory with little or no CPU intervention The Ethernet connect
187. gy Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table of contents IPE VECTOR PHOFILY TEBISTCRS esns pascestansgeeecsdansvigivsnrasehccrabspecaervay asbasrsancsteencouarsiaes 173 Spurious VECLOF RESIST Ns acscsstecscvessexzsissyasesusbcedcossuccsstecace cnsseseseasesusesagessicnyedze snuatseasnsedeesloscasedseapvascet 174 Global Tim resister Serisi n E E EA A ERE 174 Interrupt source configuration FEGISTELS cesseccecseestesseeneessecseestesnecseeseesuecutessesseeneessecseeseesseeseesueeseeeanecstestees 177 Interrupt Source Vector Priority registers sssssssseiiirisssssssssrsrrrreessssssrsrtrrrseesssssrtrrreeesesenrernt 178 Interrupt Source Destination register P r PFOCESSOF FERISLENS csisssnssscasssssesesnssesssisesosessstsssesbessessunssoteeissaasez ansevsesqusesehensessnddsunseedansusdsossesbassazenscestonssbesssass Interprocessor Interrupt Dispatch registers ccsesecsesseceessessecneessesscssensessecseestesueeseeasensecerensess 180 Current Task Priority register sess Interrupt Acknowlege registers End ofinterrupt registers senerara yassi atie e ELESE EAEE ERSAN REAREA Section 7 PCI VME64 Bridge Universe II cccccccccecececeeeceeeceeececeeeeeceeeceeeeeeeeeeeeeeens 183 Introduction to Universe Ul ssssssssgesescaicsisstesasscdsovessssccusnesaccosessassnusncesesseasssorsesocustonnsesnecdanessstssandesntesasieascesuessauedadehioaossiaenteaas
188. h memory is listed in the table below User Flash memory block information Flash Memory Size Total Blocks Block Size Block Numbers 4MB 32 64KB 0 31 8 MB 64 64KB 0 63 16 MB 128 64KB 0 127 32 MB 256 64KB 0 255 64 MB 512 64KB 0 511 Note that full Flash support is supplied in Synergy s SMon Application Developer and Debugger package Example Flash driver code is also available from Synergy Contact Customer Service for details and ordering information Bank selection The MPC106 provides only 2 Megabytes of address space for all 8 bit ROM devices Because of this limitation and the need to incorporate three different ROM devices plus onboard control status registers into this space the User Flash ROM must be accessed piecemeal User Flash is accessed in multiple 512 KB banks using the onboard Flash Window register at OxFFEF_FE50 see page 122 The total number of banks depends on the amount of User Flash installed on the board See table below With Boot Flash selected reg OxFFEF_FE50 bit 7 0 User Flash is inactive With User Flash selected reg OxFFEF_FE50 bit 7 1 User Flash is active and a 512 KB window of User Flash space can be selected Note that accesses to User Flash and the upper 512 KB of Boot Flash are not allowed to occur at the same time Only 512 KB of User Flash is visible at any time in the User Flash window and this 512 KB window is shared with the upper 512 KB of the
189. he P2 backplane is defined by VMEbus specifications and is bussed across the entire backplane Pin rows A and C are user configured and if connected at all are normally connected to adjacent slots via wirewrap or special cables Because the P2 and PO pinout may vary between backplanes or even slots in the same backplane DO NOT INSTALL the VSS4 into a system slot whose backplane is not compatible with the VSS4 s P2 and PO pinout Failure to observe this warning can cause the complete destruction of many on board components and also voids the product warranty The VSS4 pinout meets standard VME specifications for row B but rows A and C and for 5 row boards the majority of pins on row D and half the pins on row Z will vary according to the PMC card installed Synergy PMC card pinouts are shown in the associated manual If no PMC card is present P2 backplane rows A and C and D amp Z are defined as no connects For a complete list of the VSS4 P2 assignments see VMEbus connectors in Appendix A page 233 Section 2 Getting Started Minimum system requirements o Power supply VSS4 boards typically require the following power supply voltage levels with no PMC installed G4 7400 466 MHz 5 0V 5 15 7 A typical 5 00V 78 5 W 12V 5 50 mA for 12V 150 mA for 12V G4 7400 433 MHz 5 0V 5 11 0 A typical 5 00V 55 W 12V 5 50 mA for 12V 150 mA for 12V G4 7400 366 MHz 5 0V 5 9 5 A typ
190. he exception handling routine completes This is a 32 or 64 bit register depending on the processor VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC PowerPC architecture Segment Registers SRs SRs 16 ea for 32 bit processors are provided for memory management Special Purpose Registers SPRs Special purpose registers serve a variety of functions Some of these functions include control status indication processor configuration and other special operations The SPRs in PowerPC processors are 32 bits wide A program accesses SPRs according to its privilege level user or supervisor Instruction set overview All PowerPC instructions are encoded as single word 32 bit opcodes The PowerPC instructions are divided into the following categories Integer instructions These include computational and logical instructions Integer arithmetic instructions Integer compare instructions Integer logical instructions Integer rotate and shift instructions Floating point instructions Floating point arithmetic instructions Floating point multiply add instructions Floating point rounding and conversion instructions Floating point compare instructions Floating point status and control instructions Load store instructions Integer load and store instructions Integer load and store multiple instructions Floa
191. he read the total number of CPUs on the board and the halt run status for all onboard CPUs VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 119 120 Onboard registers Section 4 Programming the PowerPC Control Mode registers VSS4 control mode registers include o CPU timebase register Flash ROM register o Flash Window register PCI error register PO PCl interrupt assert pending register PO PCI interrupt mask register User LED registers VME64 SysReset register Watchdog enable register o Watchdog pet register Using Control Mode register functions Activating a Control Mode register function involves writing the appropriate hexadecimal data value to the appropriate register For example turning on LED 0 would require writing 0x01 to the User LED register at OxFFEF_FE80 using the following PowerPC instructions lis 3 OxFFEF ori 3 3 OxFE80 li 4 1 stb 4 0 3 CPU Timebase register OxFFEF_FE28 RW Bit7 6 5 4 3 2 1 0 xixix x 1 1 1 1 Reset value Bit assignments Bit s Function Values b7 b4 Reserved E b3 CPU W Timebase Enable 0 Disabled 1 Enabled b2 CPU Z Timebase Enable 0 Disabled 1 Enabled b1 CPU Y Timebase Enable 0 Disabled 1 Enabled b0 CPU X Timebase Enable 0 Disabled 1 Enabled VSS4 User Guide Arti
192. hen installing the VSS4 or similar quad board To ensure the suitability of a particular slot its airflow can be quickly checked with adjacent boards installed as they would be in the actual installation by using a hand held anemometer such as the Kestrel 1000 Pocket Wind Meter by Nielsen Kellerman www nkelectronics com Note that a system controller board needs to be the leftmost slot Any slot to the left of the system controller board must be empty Empty slots Empty slots in a cardcage tend to rob airflow away from populated slots It is recommended that empty slots be avoided If empty slots cannot be avoided it is recommended that empty slots be installed with Slot Bypass or Air Management boards www apw com or that empty slots be distributed in such a way that the VSS4 or any hot running board is adjacent to an empty slot By managing empty slot placement and avoiding slots with diminished airflow the cardcage should have no trouble cooling the VSS4 and other high power boards VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installation notes Bus grant signal problems with Hybricon VME64x backplanes Problem Installing a Universe Il equipped SBC in slot 1 of some early Hybricon VME64x backplanes prevents the bus grant daisy chain signals from being passed on to the next slot slot 2 Observation Some ear
193. hose addresses The above process repeats until all locations maximum of 21 PCI devices are read Endian issues byte swapping The PCI bus is inherently little endian where byte O is the LSB The PowerPC is big endian where byte O is the MSB This difference in endianness requires byte swapping code for accesses between PCI and PowerPC The PowerPC instruction set includes a class of load and store instructions that perform byte swapping based on the size of data being transferred The example in line routines below show how this is done for word and half word data define ASM volatile asm Read a longword from adr little endian extern inline int lwbrx void adr ASM lwbrx 0 0 1 r data r adr VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 65 Section 3 Basic Bus Descriptions PCI bus Store longword data to adr little endian extern inline void stwbrx int data void adr ASM stwbrx 0 0 1 r data r adr Read a 16 bit word from adr little endian extern inline int lhbrx void adr int data ASM lhbrx 0 0 1 r data r adr return data Store 16 bit word data to adr little endian extern inline void sthbrx int data void adr ASM sthbrx 0 0 1 r data r adr PCI standards organization PCI architecture specifications are maintained
194. ibility to meet almost any requirement Multiprocessing support includes quad CPUs with shared high bandwidth DRAM memory a private mailbox for each CPU and the OpenPIC interrupt controller Onboard peripherals include a Wide Ultra SCSI 8 16 bit wide interface Fast Ethernet 10Base T 100Base TX RJ 45 interface four RS 232D serial ports and a real time clock calendar with four digits for the year VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 1 Overview VSS4 features Quad PowerPC CPU Status amp 3 G4 LEDs Status LEDs User LEDs 8 bit Readable CPU Switch SMI Reset Rear stiffener Connectors Switch Wide Ultra ary SCSI Serial stiffener Connector DIP EPROM Interface Ethernet ke Connector Connector PMC Module Cutout VSS4 single board computer for DSP An industry standard PMC slot provides optional daughterboard I O connection to the PCI bus The VSS4 also provides Synergy Microsystems PO PCI interface which is a secondary PCI bus accessed through the PO connector PO PCI M provides support for additional PCI I O expansion and board to board communications A full line of system monitor kernel and operating system software firmware is also available from Synergy and leading developers Optional PEXS expansion module The expansion module option provides the VSS4 with additio
195. ical 5 00V 47 5 W 12V 5 50 mA for 12V 150 mA for 12V G4 7410 500 MHz 5 0V 5 8 37 A typical 5 00V 41 9 W 12V 5 50 mA for 12V 150 mA for 12V Ensure that the power supply is capable of meeting the above requirements plus the requirements of any additional boards in the system An extra 20 margin of current capacity should be factored in for safety o One modular quad serial I O port adapter cable assembly The VSS4 serial ports share a 10 pin modular RJ 50 RJ 69 front panel connector The CRJ4 serial interface adapter available from Synergy allows access to all four serial ports Refer to Serial I O cabling in Appendix A page 259 for more information o RS 232 compatible video display terminal or a PC with a COM port and terminal emulator software VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 16 Section 2 Getting Started Minimum system requirements VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Front panel The drawing below shows the layout of the connectors controls and Section 2 Getting Started indicators on the VSS4 front panel Front panel Status LEDs User LEDs 0 7 8 bit User CPU Halt Run LEDs Switch CPU SMI Reset Switch Wide Ultra SCSI Front Panel Connector Serial I O
196. ie 185 Universe II register reference COWVEMVIGW E E A A E A ET 189 Register ACCESS ania RE E RR ASD 189 Universe Il base aA ARS Senon E AR TER 189 Register Mapon nrnna A E AE E NR RENAN 190 Improving VME peifonmanNCE srira an EEN E E E EE NS AOE AEE EN 195 Universe II specific U2SPEC register sssssssssssssereessssssssesseeeeeesessssnssnereeeesesssssseserceretsessssnsssssssnsssnesseeeeeeeee 195 U2SPEC adjustable VME timing parameters ccccsessessessessssessessessesscsscsesecseesesuecuesseceseesessessessececseceseeneenss 196 U2SPEC register bit assignMents sscsecssecseesseecsseeseeesneecseecneeesscessecsucesuessuteseeesasenseecaeeseetsneessesees 197 Programming notes Universe Mvision a E R ra Writing to non existent VME locations Slave UmaGePrOSrarviMine sss ssssscessasssssscsssiecsoassessaansasceacacacccosaceanssstesesivans eatcusetstebsesnssbdeseesvsnadededtayansecestcoassseesiseey Section 8 SCSI Ethernmet Controller cccccccccccecececeeccecececeeececeeeceeeceeeeeeeeeeeeeeeeeeeeens 201 General description SYM53C885 registers SCSI registers PCI GOmtigubatio Meroena Sa a a eet a A SEE Ea N a A p aa 206 Operating reGiSters s essceccisssssssacsacessisacssssscaasesodsesscesusssossbannsosoastcosisssososesusbareszobeucedstandaetsastssobsbeatonsviesen 207 Ethernet registers PErconie Urai Me menaran E cst darttssenasvousststeusensetehedseustesss EA E Operating register Shristi ieni sisi iser eeni nii T
197. ineering Council a body that sets standards for chip packages and pinouts a type of cache memory that is most closely coupled to the CPU core It is built into the processor chip and is typically smaller and faster than L2 cache a type of cache memory that is external to the processor chip inbetween the CPU core and main memory It is typically larger and slower than L1 cache Light Emitting Diode a diode that emits light when forward biased commonly used for displays and indicators see Endian a unit of data 32 bits in length mechanism to allow any CPU or other Master to interrupt any other CPU of its choice a device that initiates and controls the transfer of addresses and data across a bus The opposite of Slave Memory protect a bit that can be set or cleared in the Mode register It usually is set to disable write accesses to the board and cleared to enable them but its meaning can be changed via PALs or ISPs Memory Management Unit a circuit that provides address translation and access control services for a CPU microsecond one millionth 10 of a second millisecond one thousandth 10 3 of a second Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 299 300 Glossary multi ported MSB nibble ns NVRAM object code P1 p2 page P cable PCI PMC PowerPC PROM RAM requester VSS4 User Guide a memory
198. ing such a function do so at their own risk and agree to fully indemnify Synergy Microsystems Inc for any and all damages arising from improper use This product and associated manuals are sold AS IS without implied warranty as to their merchantability or fitness for any particular use In no event shall Synergy Microsystems Inc or anyone involved in the creation production or delivery of this product be liable for any direct incidental or consequential damages such as but not limited to loss of anticipated profits benefits use or to data resulting from the use of this product or associated manuals or arising out of any breach of warranty In states that do not allow the exclusion or limitation of direct incidental or consequential damages this limitation may not apply Synergy VSS4 VSS Series V4xx Series V30 Series V20 Series EZ bus and PO PCI are trademarks of Synergy Microsystems Inc VMEbus Technology logo is a trademark of VITA Synergy wishes to acknowledge that the names of products and companies mentioned in this manual are trademarks of their respective manufacturers PRINTED IN THE USA Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table of contents Manual revision summary sssccccesssccccesesccccnsssecccasssecccensseecconsseeccaessecseasseeseasseesoes viii Section T OVOrVIEW lt 05cicccceisiccdeciececs cevstccsc
199. interrupts ACT Activity bit read only The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to 1 when its associated bit in the Interrupt Pending or In Service register is set Note that this bit is READ ONLY The vector and priority values should not be changed while the ACT bit is 1 MSK Mask bit Setting this bit disables any further interrupts from this source Reset sets this bit to one Global Timer Destination register Select Processors 3 0 210 Reserved Scvudsl co lt c lt cVvd C P U Z This register indicates the destination s for this timer s interrupts Timer interrupts operate only in Directed Delivery mode This register may specify multiple destinations multicast delivery CPU_ Setting the appropriate bit s b3 b0 directs the timer interrupt to the corresponding processor s VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 6 MPIC Interrupt Controller MPIC registers Interrupt source configuration registers The table below lists the address map locations of the interrupt source configuration registers Address map interrupt source configuration registers Address Offset Register Access 0x1_ 0000 Interrupt Source 0 Vector Priority register R W 0x1_0010 Interrupt Source 0 Destination register R W 0x1
200. ion The Slot C or XPMC 3 PMC card on the optional PEX3 expansion module cannot use the host SBC s P2 I O if the onboard Synergy PMC card uses extended P2 I O pins i e uses SBC P2 D amp Z rows or if the PSTR adapter is used The Slot C PMC card can use the SBC s P2 I O if the onboard Synergy PMC uses standard P2 I O e g uses only rows A and C or if the PSTK not PSTR adapter is used Note that all PMC cards in the system are free to use front panel I O without restriction VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com PEX3 PMC expansion option Appendix D In lieu of a Synergy PMC a PSTR PSTK adapter diagram below can be used to install PEX3 onto the SBC PMC 1 PSTR PSTK Expansion Connectors Connectors r SBC pl renee eee enn ne nF Synergy PMC 1 PEX3 ila vty f l oe SBC PMC dorreray Bch 3 PMC PEX3 i P P11 eq Gnt Ck PCI Circuitry Pitr a or PEX3 PCI PCl i a P12 P1
201. ion is available at the VSS4 front panel The SCSI option is provided with a front panel connector Refer to Appendix A for connector information Listed below are some of the features of the SYM53C885 o Fully PCI 2 1 compliant o Full 32 bit PCI DMA bus master High performance SCSI and Ethernet cores both highly programmable Upto 40MB s synchronous Wide Ultra SCSI transfers 10 100 Mb s Ethernet operation VSS4 User Guide 203 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller General description wo For detailed SYM53C885 programming zj information refer to the Symbios Logic Data Manual no T89962 1296 15MH This document and other supporting documents can be obtained by contacting LSI Logic Corporation 1551 McCarthy Blvd Milpitas CA 95035 United States Tel 408 433 8000 FAX 408 433 8989 Web http www lsilogic com A datasheet in PDF format is available from the LSI Logic website in their Tech Library Document P019641 SYM53C885 Data Sheet 3 98 204 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller SYM53C885 registers SYMS53C885 registers The operating system PCI discovery routines dynamically set up the SYM53C885 base address by writing to the appropriate registers in PCI configuration address space Note tha
202. ion mode in which the CPU enjoys all its privileges System Clock a signal driven by the system controller to all boards of a Multibus or VMEbus system System Failure a signal that can be driven by any board of a VMEbus system Traditionally used to indicate a failure to one or more boards or devices on a bus System Reset a signal driven by the system controller to reset all the cards on the system bus on VMEbus a group of circuits on the 1 slot VMEbus board that prioritize the bus requests provide a system clock and provide system timeouts a keyboard and display monitor CRT attached to a computer to allow communications between the user and a computer triple access DRAM see multi ported Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com UART VMEbus watchdog window size word VSS4 User Guide Glossary Universal Asynchronous Receiver Transmitter a device able to translate between parallel and asynchronous serial Communications signals for transmission and reception between a parallel processor bus and a serial communications port Versa Module Eurocard bus a microcomputer architecture whose physical and electrical characteristics are defined in the IEC 821 and IEEE 1014 1987 specifications The VMEbus supports separate address and data lines of up to 32 bits each This bus uses a backplane in which VMEbus modules are interconnected using
203. ior to initiating a soft reset This bit defaults to ON which directs the processor to begin executing code at OxFFFO_0100 Setting the MSR_IP bit OFF allows the processor to execute code at 0x100 Refer to Section 6 MPIC Interrupt Controller page 165 for more on the MPIC 164 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 6 MPIC Interrupt Controller This section provides information about the PowerPC multiprocessor interrupt controller MPIC General description MPIC registers The bit numbering of registers in this Yi section follows the zero on the right convention as opposed to the zero on the left bit numbering convention used by Motorola and IBM in their PowerPC documentation VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 165 166 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 6 MPIC Interrupt Controller General description General description Interrupt control on the VSS4 board is provided by IBM s MPIC multiprocessor interrupt controller chip which is specifically designed for PowerPC systems The chip provides interrupt management for board devices and the processors themselves The MPIC chip supports X 16 I O device interrupts X Up to 4 process
204. it 12 bit 11 bit 10 bit 9 bit 8 Enhanced Register Set 0x2 EFR RW Auto Auto Special Enable Cont 3 Cont 2 Cont 1 Cont 0 0x00 CTS RTS Char ERBits Ty Rx Tx Rx Tx Rx TxRx select 7 1AR Control Control Control Control FCR Bits 4 5 MCR Bits 5 7 0x4 Xon 1 RW bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 0x5 Xon 2 RW bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0x00 0x6 Xoff 1 RW bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 0x7 Xoff 2 RW bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0x00 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com VSS4 User Guide Section 4 Programming the PowerPC Asynchronous serial interface Notes 1 The value between the square brackets represents the register s initialized HEX value 2 The Baud Rate register set is accessible only when LCR bit 7 is set to 1 3 Enhanced Feature Register Xon 1 2 and Xoff 1 2 are accessible only when LCR is set to OxBF For detailed register descriptions refer to the ST16C654 datasheet Serial O address map Listed below are the base addresses of the four serial ports To calculate a serial port register address add the serial port s base address given below to the Address Offset listed in the left hand column of the table on the previous page Serial port base addresses Address Port OxFFEF_FB08 OxFFEF_FB00 OxFFEF_
205. l register VSI2_CTL F2C VMEbus Slave Image 2 Base Address register VSI2_BS F30 VMEbus Slave Image 2 Bound Address reg VSl2_BD F34 VMEbus Slave Image 2 Translation Offset reg VSI2_TO Note 1 Avoid updating slave image registers while VME traffic is using the slave window Doing so results in VME data errors See Programming notes Universe Ilon page 199 for more information VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 193 Section 7 PCI VME64 Bridge Universe I register reference Universe Il register map continued Offset Hex Register Name F38 Reserved F3C VMEbus Slave Image 3 Control register VSI3_CTL F40 VMEbus Slave Image 3 Base Address register VSI3_BS F44 VMEbus Slave Image 3 Bound Address reg VSI3_BD F48 VMEbus Slave Image 3 Translation Offset reg VSI3_TO F4C F60 Reserved F64 Location Monitor Control register LM_CTL F68 Location Monitor Base Address register LM_BS F6C Reserved F70 VMEbus Register Access Image Control reg VRAI_CTL F74 VMEbus Register Access Image Base Addr reg VRAI_BS F78 Reserved F7C Reserved F80 VMEbus CSR Control register VCSR_CTL F84 VMEbus CSR Translation Offset register VCSR_TO F88 VMEbus AM Code Error Log register V_AMERR F8C VMEbus Address Error Log regi
206. ly Hybricon VME64x backplanes use active logic to drive the bus grant daisy chain signals to the next slot The logic requires that the signal be low active coming out of the slot AND low active going into the slot in order to be driven to the next slot This logic is also included on the backplane for slot 1 even though there is no slot to the left of slot 1 The backplane includes pull down resistors 82K ohms for the BGnIn s and BGnOut s for slot 1 The Universe II VME interface chip however has an internal pull up 10kQ on its BGnIn s that is stronger than those on the backplane A board using the Universe II chip in slot 1 causes the active logic on the backplane to not pass the BGnOut s to the next slot because the active logic sees a high inactive signal going into slot 1 BG3Out from slot 1 works because of the pull down on BG3In for VME auto system controller Solution If the VSS4 board or any SBC using the Universe II is to be used in slot 1 of an early Hybricon VME64x backplane connect the backplane s slot 1 BGnIn s to ground This can be accomplished by adding four 4 short wires as listed in the table below Slot 1 wiring fix for some early Hybricon VME64x backplanes From To P1 Z4 GND P1 B4 BGOIn P1 Z6 GND P1 B6 BG1In P1 Z8 GND P1 B8 BG2In P1 Z10 GND P1 B10 BG3In VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed
207. ly connected to ground connect to Signal Ground Ground Gnd internally connected to ground connect to Signal Ground Receive Data Serial Port A Receive Data Serial Port B Receive Data Serial Port C Receive Data Serial Port D O WOWINI DI Oa HR worm K A serial connection option is available o CRJ4 VSS4 serial port adapter The CRJ4 serial port adapter is a PCB assembly that connects to the VSS4 front panel serial connector via an RJ 69 cable Four RJ 45 connectors on the CRJ4 provide the connection to from the individual serial channels Refer to the serial port connector discussion in Appendix A Cables amp Connectors page 257 for more information on VSS4 serial port connectivity 136 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Clock calendar Clock calendar The VSS4 provides clock calendar data including the year month date day hour minutes and seconds data in 24 hour BCD format from a SGS Thomson M48T201Y Timekeeper SRAM controller chip The Y2K compliant clock calendar is backed up by a lithium battery that should last for 5 10 years For high altitude applications gt 10 000 ft a capacitor backup option is available to back up the clock calendar in lieu of the regular lithium battery which can leak in a high altitude environment
208. mation VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing PMC cards PMC card securing screws To aid in installation the location of the PMC card securing screws on the VSS4 is shown in the drawing below SBC solder side PMC card securing screws 99 0034 Location PMC card securing screws Installing a PMC card Perform the following steps to install a PMC card The VSS4 PMC slot accepts 5V VI O or YA 5V tolerant PMCs only Power down and remove SBC from card cage Power down the system and remove the VSS4 from the card cage VSS4 User Guide 41 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 42 Section 2 Getting Started Installing PMC cards Synergy SBCs contain static sensitive devices Make sure you are properly grounded by putting on a ground strap touching a system ground such as a metallic chassis or case etc before removing and handling the board Use an ESD protected workstation for module removal and installation work Remove PMC filler panel from SBC front panel The filler panel will be one of two types The first type simply snaps in place remove by pushing from the inside The second type is an actual blank PMC front panel remove 2 ea 6 mm M2 5 slot head securing screws from solder
209. memory How to use the backside L2 cache The configuration of the backside L2 cache including the enable disable status is set by the processor s L2 cache control register L2CR The VSS4 is provided with an onboard register at OxFFEF_FE30 to discover the proper L2 clock ratio Information on this register is found in this section on page 116 Refer to the Motorola 750 7400 7410 User s Manual for more information about the backside L2 cache interface operation 128 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Mailboxes Mailboxes The VSS4 provides four 8 bit wide mailboxes for interprocessor communication Each mailbox generates an interrupt while it contains any data The mailbox write addresses are in RAM space which is accessible by all memory owners including either CPU all PCI masters including PMC cards and the Universe VME slave The mailbox read registers are located in ROM space and are readable only by the CPUs Mailboxes A D are typically used to interrupt CPU X CPU Y CPU Z and CPU W respectively This interrupt steering is programmed by the user into the MPIC interrupt controller and may be changed if needed Refer to Section 6 MPIC Interrupt Controller page 165 for more information on the MPIC Each mailbox contains a FIFO containing 256 storage locations which allows up to 256 pending messages
210. ment descriptions and ordering information can be found on Motorola s website on the WWW http www mot com SPS VSS4 User Guide 93 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC MPC106 PCI bridge memory controller PowerPC processor interface The MPC106 provides an interface to a variety of PowerPC processors up to 4 using a 32 bit address bus and a 64 bit data bus The address and data bus are decoupled for pipelining of 60x accesses The MPC106 processor interface supports full memory coherency and an optional local bus slave Secondary L2 cache interface The MPC106 supports various combinations of L2 cache 60x processors For the VSS4 however individual L2 backside cache is provided for each processor so the MPC106 s cache controller is not used This frees the MPC106 to support full arbitration and interface functions for multiprocessor operation Memory interface The MPC106 memory interface controls processor accesses to from main memory using a 64 bit data path The memory configuration size and error checking scheme normal parity RMW parity ECC is programmable ROM Flash interfacing is also provided by the MPC106 PCI access to from main memory is provided by the PCI bus interface see next PCI bus interface The MPC106 provides the PCI interface that connects to the processor and memory buses The MPC1
211. module These paragraphs describe changes made to recent versions of the RGS3 memory module Revision B PCB notched to clear DC DC converter module Revision A Initial board release 268 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option The Synergy Microsystems PEX3 is an optional 6U board that provides PMC and memory expansion to certain model Synergy SBCs using the Grackle or Chaparral PCI bridge PEX3 provides three single width PMC slots and up to 256 MB of SDRAM and up to 128 MB of Flash The PEX3 has PCI bus master capability for fast direct communication between the PMCs onboard memory and devices on the host SBC The PEX3 option replaces the regular SBC front panel with a double wide front panel to form a double wide module assembly The PEX3 connects to the host SBC through a stackable Synergy PMC card or adapter The stacking design lets the SBC use a PMC memory expansion solution without giving up the use of a PMC Features Supports three single width PMCs one single width and one double width PMC or one triple width PMC SDRAM capable of streaming data up to 256 MB Flash up to 128 MB PCI bus mastering capability with 2 DMA channels ESD protection VSS4 User Guide 269 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3
212. mory 1 1 bank 2 2 banks 3 4 banks 4 8 banks Function Type of Memory b5 b3 Memory per Bank b2 b0 Number of Banks A byte read of this register provides information on the board s installed memory Information provided in this register includes number of banks capacity per bank and type of memory used SDRAM type etc VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers Secondary PCI Slot register OxFFEF_FE48 RO Bit 7 6 5 4 3 2 1 0 xixix xi x x x Reset value Bit assignments Bit s Function Values b7 b1 Reserved b0 Sec PCI Bus Slot controller Indicator 0 Not System Controller 1 System Controller A byte read of this register informs which CPU board is responsible for configuring the PO PCI bus map If bO 0 the SBC configures the PO PCI bus map If bO 1 a CPU board on the secondary external PCI bus configures the PO PCI bus map VME64 Slot register OxFFEF_FF30 RO Bt7 6 5 4 3 2 1 0 x Reset value Bit assignments Bit s Function Values b7 Reserved b6 Slot Number Source 0 Manual Slot Jumper Field JO2L 1 Auto VME64x Geographical Address b5 Valid Invalid Geogr
213. n Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions PCI bus Memory address spaces are used by the device drivers The PCI Configuration space is used by the PCI initialization code being run at bootup All of these spaces are for PCI chips or devices Exactly what registers are used and their location depend on the assigned IDSel number and or its slot location if PMC and specific programming as set during PCI configuration The PCI I O space is a relic of the IBM j PC s ISA bus and is typically not used by modern PCI configuration routines for most PowerPC operating systems PCI configuration Every PCI device in the system including PCI PCI bridges has a data structure located in PCI configuration address space called the PCI Configuration header This structure which has a maximum length of 256 bytes allows the system to identify and control the device during configuration 31 16 15 0 Device ID 0x0701 Vendor ID 0x1000 0x00 Status Command 0x0000 0x04 Class Code 0x020000 Revision ID 0x00 0x08 BIST Header Type Latency Timer Cache Line Size 0x0C Base Address Zero I O Ethernet Operating Registers 0x10 Base Address One Memory Ethernet Operating Registers 0x14 Not Supported 0x18 Not Supported 0x1C Not Supported 0x20 Not Supported 0x24 Reserved 0x28 Subsystem ID Subsystem Ven
214. n the 28F020 DIP Flash is write protected However future ECOs may be issued to retrofit other VSS4 board revisions for this jumper function Contact Customer Service for assistance in determining whether or not your board has this added jumper function VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM Additional Flash memory information The Flash memory chips have embedded byte write and block sector erase algorithms For more information on the chip itself and on the software aspects of writing erasing Flash memory refer to the Intel Flash memory databook o Intel Flash Memory Databook Order no 210830 For ordering information contact Intel Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 In U S and Canada call toll free 800 548 4725 For general technical information via the Web Intel s Developer site http developer intel com Datasheets for the Flash parts are available in PDF Adobe Acrobat from the Intel s Developer site http developer intel com design flash datashts index htm VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 151 Section 4 Programming the PowerPC Boot Flash ROM DIP EPROM 152 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guarant
215. n the VSS4 board Use a chip extraction tool to remove the DIP EPROM from the socket to avoid damaging parts underneath Install the DIP EPROM Install the DIP EPROM in the socket The VSS4 EPROM socket accepts 32 pin DIP EPROM devices The figure above shows the orientation of the DIP EPROM after proper installation note orientation of notch end Install DIP EPROM configuration jumpers J902 Place a pair of jumpers at J902 to configure the board for the device used in the DIP EPROM socket as shown in the drawing below we Some VSS4 boards include an ECO that zi adds a Boot Flash write protect function to the J902 jumper block pins 1 and 2 Refer to the Additional write protection of Boot Flash discussion in Section 4 page 150 for more information on this jumper VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 32 Section 2 Getting Started Installing a monitor PROM DIP EPROM Boot Flash Configuration Jumpers J902 99 0047b Device Jumpers Installed on Pins 140 o2 3 amp 5 a 4 27Cxxx EPROM 486 4 7 a ofa N 1 oj2 i 28F020 Flash write enable 183 3 Ma 6 amp 8 5 a Bs 7 2 8 T 140 0 2 ui 28F020 Flash write prot 6 amp 8 En a 7 ois 290040 Flash 384 3 6 amp 8 5 9 Bic 7 Ms 100 c Boot Flash 182 3 o of4 g write enabled 5 E
216. n this position and wait 2 seconds for LED illumination 22 V554 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Setting up the VSS4 hardware Setting up the VSS4 hardware This chapter describes the general hardware configuration of VSS4 boards This configuration is done via jumper block JO2L Additional jumpers are provided on jumper block J902 for EPROM configuration Refer to the next chapter on Installing a monitor PROM for details on EPROM configuration Default configuration The table shown below lists VSS4 s default hardware configuration before the installation of any jumpers on JO2L Default hardware conditions Jumpers presumes no jumper installed Default JO2L Boot ROM Enable Disabled SCSI Termination Enabled Force VME System Controller Disabled VME64 Auto System Controller Enabled User Defined Slot Number None Flash Write Protect Disabled For Rev C or higher boards only VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 24 Section 2 Getting Started Setting up the VSS4 hardware Installing jumpers No jumpers need to be set for most applications However the JO2L user configuration jumpers let you change the default conditions listed in the table above if necessary Note that the jumper
217. nal single width PMC slots and additional Flash and SDRAM memory Refer to Appendix D page 269 for details on the PEX3 PMC expansion option VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 1 Overview VSS4 features VSS4 physical configuration VSS4 has onboard connectors for Modular memory card o PMC I O card and or PMC carrier board expansion Secondary PCI PO PCI interface via PO connector VSS4 s front panel includes Modular RJ 45 jack for Fast Ethernet Modular RJ 50 RJ 69 jack for quad serial ports A B C and D Processor SMI amp reset switch 8 user LEDs 8 status LEDs Software readable 8 bit DIP switch For SCSI option 68 pin Wide Ultra SCSI connector single ended VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com view Over Section 7 VSS4 features Functional block diagram Zd 8 bd SNGSWA SJ M ISULIL JWA pare go pug a 0d a92u ul 19d 0d ji i i 1 I i Ddod oy y n REE
218. nals SEL BSY C D I O MSG REQ ACK ATN and RST Altogether the SCSI 2 interface uses 68 lines The following table summarizes the ANSI standard SCSI 2 SCSI 3 bus signals supported by VSS4 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions SCSI bus SCSI 2 SCSI 3 bus signals Pin No Mnemonic see Note Signal Driven By 40 DBO Data Bus Line 0 Initiator Target 41 DB1 Data Bus Line 1 Initiator Target 42 DB2 Data Bus Line 2 Initiator Target 43 DB3 Data Bus Line 3 Initiator Target 44 DB4 Data Bus Line 4 Initiator Target 45 DB5 Data Bus Line 5 Initiator Target 46 DB6 Data Bus Line 6 Initiator Target 47 DB7 Data Bus Line 7 Initiator Target 65 DB8 Data Bus Line 8 Initiator Target 66 DB9 Data Bus Line 9 Initiator Target 67 DB10 Data Bus Line 10 Initiator Target 68 DB11 Data Bus Line 11 Initiator Target 35 DB12 Data Bus Line 12 Initiator Target 36 DB13 Data Bus Line 13 Initiator Target 37 DB14 Data Bus Line 14 Initiator Target 38 DB15 Data Bus Line 15 Initiator Target 48 DBPO Data Bus Parity1 Initiator Target 39 DBP1 Data Bus Parity2 Initiator Target DIFFSENS Differential Sense Any device 17 18 TERMPWR Terminator Power Any device 51 52 55 ATN Attention Initiator 57 BSY Busy Initiator Target 58 ACK Acknowledge Initia
219. niverse I register reference For more information on PCI configuration refer to the PCI implementation details discussion in the PCI bus chapter in Section 3 page 62 and the Setting PCI device base address discussion in Section 4 page 101 Also refer to the Type 0 configuration table on page 108 Register access from PCI There are two PCI access mechanisms for the Universe II registers PCI Configuration space only the lower 256 bytes of the UCSR can be accessed as Configuration space These bytes make up the Universe II s PCI configuration header PCI Memory or I O space As specified in the Space bit of the PCI_BSx registers the Universe II registers are accessed in either the PCI Memory or I O space Register access from VMEbus There are two VMEbus access mechanisms for the Universe II registers This mode is typically not used on the VSS4 since the VSS4 has onboard intelligence However it may be useful in certain applications o VMEbus Register Access Image VRAI this mechanism allows the user to map the Universe Il registers in A16 A24 or A32 address space CS CSR Space this mechanism uses the VME64 scheme in which each slot in the VMEbus system is assigned 512KBytes of CS CSR space X Register map The table below lists the Universe Il registers by offset address ye For CS CSR access add 508 KBytes zi Ox7_FOOO to offsets listed below VSS4 User Guide Artisan Technology Gr
220. nology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 9 PCI PCI Bridge Interface This section provides information about the PCI PCI bridge chip that provides the PO PCI bridge interface General description Registers Configuration Software support PO PCI VSS4 User Guide 215 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 216 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 9 PCI PCI Bridge Interface General description General description Synergy s PO PCI bus interface provides the VSS4 with a sub bus for board to board data transfers that are speedier than the VMEbus The PO PCI bus is 64 bits wide and operates at 33 MHz for a theoretical maximum aggregate bandwidth of 266 MB sec Up to 4 pair of SBCs 8 slots are allowed on the PO PCI bus A single VSS4 can write data to another VSS4 at about 72 MB sec over the PO PCI bus However the rest of the PO PCI bandwidth is not consumed so other transfers can occur concurrently up to the maximum bandwidth The PO PCI bus interface is based on Intel s formerly Digital Semiconductor s 21554 64 bit PCI to PCI bridge chip The 21554 chip has two PCI ports primary and secondary The primary port is connected to PO and the secondary port is connected to the VS
221. nslation Offset register LSI2_TO 138 Reserved 13C PCI Target Image 3 Control register LSI3_CTL 140 PCI Target Image 3 Base Address register LSI3_BS 144 PCI Target Image 3 Bound Address register LSI3_BD 148 PCI Target Image 3 Translation Offset register LSI3_TO 14C 16C Reserved 170 Special Cycle Control register SCYC_CTL 174 Special Cycle PCI Bus Address register SCYC_ADDR VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 191 Section 7 PCI VME64 Bridge Universe I register reference Universe Il register map continued Offset Hex Register Name 178 Special Cycle Swap Compare Enable register SCYC_EN 17C Special Cycle Compare Data register SCYC_CMP 180 Special Cycle Swap Data register SCYC_SWP 184 PCI Misc register LMISC 188 Special PCI Target Image register SLSI 18C PCI Command Error Log register L_CMDERR 190 PCI Address Error Log register LAERR 194 19C Reserved 1A0 PCI Target Image 4 Control register LSI4_CTL 1A4 PCI Target Image 4 Base Address register LSI4_BS 1A8 PCI Target Image 4 Bound Address register LSI4_BD 1AC PCI Target Image 4 Translation Offset register LSI4_TO 1B0 Reserved 1B4 PCI Target Image 5 Control register LSI5_CTL 1B8 PCI Target Image 5 Base Address register LSI5_BS 1BC PCI Target Image 5 Bound Address
222. ntrol registers a bus sharing method that engages each device or process in a group at its turn in a fixed cycle an industry standard for serial communications using 12V signals at up to 19 2 kb sec for distances up to 50 ft Release When Done a requester strategy that once granted the bus asserts Mastership only as long as actually needed Opposite of ROR Single Board Computer a printed circuit board containing microprocessor and support devices that provide CPU ROM RAM and peripheral interfaces Small Computer Systems Interface an industry standard parallel interface bus that provides host computers with device independence of add on peripherals such as disk drives tape drives CD ROM drives etc The standard began as an 8 bit parallel data interface with a max transfer rate of 5 MB S SCSI 1 The next SCSI standard SCSI 2 1994 doubled the 8 bit bus transfer rate to 10 MB S The SCSI Trade Organization STA has since categorized higher performing 16 bit SCSI types such as Wide Ultra SCSI and Wide Ultra2 SCSI The T10 standards committee expanded the scope of the SCSI interface with SCSI 3 which is not a standard but a collection of spec documents describing additional connector and cabling options protocol extensions and transmission schemes high performance serial and fiber data channel Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 307 302
223. number manually Rev C or higher 26 Installing a monitor PROM a Installing the RGS3 memory MOU es aca casssssascecsveconscierspsasarseruesoucccarsaseiacesanspsagcvinsistaccvansaatedovayecasssticcopuasecasqestt AT aaki 33 Installing upgrading the RGS3 memory MOAUIE essssecseessesecseeneecseeseessessccueessenseeseeneceueensessecseenteeseeenee 35 Memory module securing SCrEWS eseeseceenees 337 Installing PMC Cards sssr og VSSA PMG COMMOCEONS sessisccsssssssasscessessietsatusisnrenteriancteeistianbarsrtsibesctasrsctncssiereerieiobee 40 Adding additional PMC cards with the PEX3 expansion board 40 PMC card securing SCFOWS sesssecstesseessetecneeestessueesseesetecntecnsessueeseeesees 41 Installing a PME caid snan n RER REEERE V aan TEE 41 Installing the PO OVEr AY osanaan e R nae E iE 45 Installation notes Slot installation recommendations Bus grant signal problems with Hybricon VME64x backplanes essesseesseesseeceeeceeeneecseeeseecseesateceeenseenees 52 Section 3 Basic Bus Descriptions cccccccccccccccccccccccccccccccccccccccccccecccccceccceeceeeeeeeeees 53 PowerPC DUS rrin sceae es Sasctakesstusescescens bevcccer tances A A AR R AA AE 55 VME64 bus y OVENI OW e o a Ar A T NE E TA ETTE OO O RARE 57 VSS4 VMEbus implementation ssssccsssssssccesssssecstecseesseccesecnsecstesssecsseesusecuecssessuecsseesseecasecnseessseesneessseesueesseees 58 Introduction PMC CaSe a a A E A 62 PCI implemen
224. ol6 hrai 7 E ojs 5 dog 3 Boot Flash None E g write protected 1 amp 2 5 E oje 7 E ofa O lo a o oj g aw AACA aii o DIP EPROM Boot Flash configuration jumpers J902 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing the RGS3 memory module Installing the RGS3 memory module VSS4 boards provide on board SDRAM with the RGS3 memory module RGS3 is available in the following sizes 32 MB 64MB 128 MB 250MB 512MB Normally all VSS4 boards ship from the factory with a memory module installed The modular design of the VSS4 DRAM interface however allows for easy DRAM upgrades in the field The drawing below shows the location of the RGS3 memory module on the motherboard 33 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Get
225. ology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Front panel The eight User LEDs indicate application events 0 7 Software programmable LEDs are controlled by the User LED registers They indicate the current operating mode of the board as defined by the software currently running For more information on the registers that control these LEDs refer to the Onboard registers chapter in Section 4 The Status LEDs indicate various status items LED Label Indication FAIL Red When on indicates a condition that caused the CPU to reset VMEbus SysRst line or the front panel RESET toggle During normal operation the system boot software clears this condition shortly after RESET sc Green When on indicates System Controller function assumed by board VME Dual color LED VMEbus Activity Green VME Master Red VME Slave Flickers green in response to VME Master activity When the VMEbus interface is idle the VME LED lights up green on the last release on request ROR VMEbus master to have used the bus Flickers red in response to VME Slave activity PCI Dual color LED PCI Bus Activity Green PCI Bus Yellow PCI Expansion Flickers green in response to PCI bus activity Flickers yellow in response to PCI expansion PMC activity VSS4 User Guide A
226. on Update Aug 1998 88 Kbytes Product Preview Datasheet 797 Kbytes Bridge Performance Optimization AppNote Sep 1998 72 Kbytes Getting Started AppNote Sep 1998 94 Kbytes Issues w Host Processor Card AppNote Oct 1998 68 Kbytes Embedded Applications Hardware Reference Manual Sep 1998 1075 Kbytes VSS4 User Guide 219 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 9 PCI PCI Bridge Interface Registers The block diagram below shows the microarchitecture of the 21554 PCI PCI bridge i 7 a B Secondary Primary PCI PCI Bus Bus Primary Secondary Target i Target Control Primary sala Secondary Control Config pe Regist Config Registers ong egisiers Registers Registers Primary Secondary Master Master Control Control ROM Secondary Interface Bus Control Arbiter JTAG Signals ROM Interface Interrupt Secondary Arbiter Signals Signals Signals FM 06188 Al4 Microarchitecture 21554 PCI PCI bridge chip 220 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 9 PCI PCI Bridge Interface Configuration Configuration Introduction The 21554 configuration space is divided into three parts Primary interface configuration registers Secondary interface configuration registers Device specific configuration registers Both the primary and secondary interface configur
227. onfigured at assembly time by soldered in jumpers on the board Access to the PowerPC bus interface is granted through an external arbitration mechanism that allows devices to compete for bus mastership For the VSS4 these devices include the PowerPC to PCI Bridge Memory Controller Grackle chip and the PowerPC processors The Grackle chip handles PCl PowerPC bus accesses For more details on PowerPC bus arbitration refer to the Motorola IBM User s Manual for the appropriate processor resident on your VSS4 board VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 56 Section 3 Basic Bus Descriptions PowerPC Bus VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions VME64 bus VMIE64 bus Overview The VMEbus Versa Module Eurocard bus is a microcomputer architecture whose physical and electrical characteristics are defined in the IEC 821 and IEEE 1014 1987 specifications Standard VMEbus supports separate address and data lines of up to 32 bits each This bus uses a backplane in which VMEbus modules are interconnected using DIN 41612 connectors designated as P1 J1 and P2 J2 module backplane designations respectively Standard VMEbus modules come in two form factor types Single height 3U for single backplane using P1 J1 connectors Do
228. or lower ojojofofo o o o o o a Oonn t ONW a ei ae ies Eo H H gi a ee i E o C gee Onn Ono of no dle U li I ee Ua mE Sweet A z mt OONAN LIMA i r Boot ROM Enable Boot Source SCSI Termination Disable Rev C or higher System Controller Manual System Controller Auto Slot ID Jumper Enable 9 GA4 GA3 13 Geographical Addressing S42 Jumper Fields gai 47 GAO 19 Byoyoyeyejajayojayaya ofofofofefojofofolfolo Flash Write Protect 21 Him Configuration jumpers JO2L Jumper JO2L functions Jumper Pins Function For more info see Section Chapter 182 Boot ROM Enable When installed the board will boot from the DIP EPROM instead of Boot Flash ROM Section 4 Boot Flash ROM DIP EPROM 3 amp 4 SCSI Termination Disable When installed the on board SCSI termination is disabled Section 3 SCSI bus VME System Controller When installed the on board VME system controller function is active regardless of the VME64 auto system controller function or the actual VME slot in which the board is installed
229. or possible future use In place of the removed hardware install four ea standoffs item 3 on SBC s VME P1 and P2 connectors using 4 ea screws item 4 Mount PEX3 board assembly to SBC Tilt PEX3 board assembly to engage PMC front panel s to SBC front panel cutout s Each O ring gasket on PMC must engage chamfer in front panel cutout Once all front panels are in place align PEX3 board connector at bottom of Expansion PMC Slot 1 with SBC s PMC or PSTK PSTR stacking adapter if no PMC is used then press down to seat connector Pre existing installation secure PEX3 board by using two ea screws item 5 in front underneath SBC to engage PEX3 standoffs and four ea screws item 4 in back to engage standoffs on SBC See PMC card PEX3 expansion board installation drawing for details New installation Remove screw and nut securing each SBC eject handle to board Replace removed hardware with two ea screws item 5 Secure PEX3 in front by screwing in these screws to PEX3 standoffs Finish installation by securing rear of PEX3 with four ea screws item 4 which engage standoffs on SBC VME connectors See PMC card PEX3 expansion board installation drawing for details PMC stacking and P2 I O routing The schematic below shows the onboard PMC and PMC expansion PCI bus connections and the I O routing through the VME P2 user I O pins Use this diagram to plan your PMC installation and P2 I O wiring PMC P2 1 0 restrict
230. ors 0 3 4 interprocessor interrupts 4 global timers VSS4 User Guide 167 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 6 MPIC Interrupt Controller General description 168 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 6 MPIC Interrupt Controller MPIC registers MPIC registers MPIC base address The operating system PCI discovery routines dynamically set up the MPIC base address by writing to the appropriate registers in PCI configuration address space MPIC s PCI configuration header is shown below 31 16 15 0 Device ID Vendor ID 0x00 0x0046 0x1014 Status 0x0200 Command 0x0000 0x04 Reserved 0x08 Reserved 0x0C Base Address Register 0x0000_0000 0x10 Note Set PCI command register bit 1 to 1 to enable PCI Memory Address space access MPIC does not support I O space access The MPIC chip operates only in PCI Memory Space operation in PCI 1 O Space not supported For more information on PCI configuration refer to the PCI implementation details discussion in the PCI bus chapter in Section 3 page 62 and the Setting PCI device base address discussion in Section 4 page 101 Also refer to the Type 0 configuration table on page 108 The table below shows the overall address map of the MPIC registers which are accessed through PCI
231. otes SYM53C885 SCSI prematurely surrendering PCI bus Problem Slow SCSI transfers to SCSI drive when VME BLT s were occurring Observation The SYM53C885 SCSI chip was surrendering the PCI bus in the middle of a burst read transfer when the Universe II PCI VME bridge needed to write data This was slowing down the SCSI transfers in the face of VME traffic Solution The solution is to write a value of 20 decimal or greater to the SCSI chip s PCI Latency register OxOD or OxOE if big endian The C code to do this in pSOS or VxWorks is below VSS4 User Guide 213 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller Programming notes SYM53C885 SetLatency int value int temp value value amp OxFF Mask value to range of 0 255 temp readMPC 0x8000600C temp temp amp Oxff00 writeMPC 0x8000600C temp value lt lt 8 numbering bytes from right to left byte 0 is the Cache Line length byte at offset OxC and byte 1 is the Latency timer byte at offset 0xD which is defined as number of PCI clocks of latency Note that this register should always be set with this value There is no downside to setting the PCI Latency register to 20 since that s the length of one burst transfer This means that it s the optimal setting for use with the Grackle 214 VSS4 User Guide Artisan Tech
232. oup Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Universe I register reference Universe Il register map Offset Hex Register Name 000 PCI Configuration Space ID register PCI_ID 004 PCI Configuration Space Ctl amp Status reg PCI_CSR 008 PCI Configuration Class register PCI_Class 00C PCI Configuration Misc 0 register PCI_MISCO 010 PCI Configuration Base Address register PCI_BSO 014 PCI Configuration Base Address 1 register PCI_BS1 018 024 PCI Unimplemented 028 PCI Reserved 02C PCI Reserved 030 PCI Unimplemented 034 PCI Reserved 038 PCI Reserved 03C PCI Configuration Misc 1 register PCI_MISC1 040 0FF PCI Unimplemented 100 PCI Target Image 0 Control register LSIO_CTL 104 PCI Target Image 0 Base Address register LSIO_BS 108 PCI Target Image 0 Bound Address register LSIO_BD 10C PCI Target Image 0 Translation Offset register LSIO_TO 110 Reserved 114 PCI Target Image 1 Control register LSI1_CTL 118 PCI Target Image 1 Base Address register LSI1_BS 11C PCI Target Image 1 Bound Address register LSI1_BD 120 PCI Target Image 1 Translation Offset register LSI1_TO 124 Reserved 128 PCI Target Image 2 Control register LSI2_CTL 12C PCI Target Image 2 Base Address register LSI2_BS 130 PCI Target Image 2 Bound Address register LSI2_BD 134 PCI Target Image 2 Tra
233. ource ST16C654 Priority ISR Bits Interrupt Level b5 b4 b3 b2 bt bO Source 1 0 0 0 1 1 0 LSR Receiver Line Status Reg 2 0 0 0 1 0 0 RXRDY Rx Data Ready 2 0 0 1 1 0 0 RXRDY Rx Data timeout 3 0 0 0 0 1 0 TXRDY Tx Holding Reg Empty 4 0 0 0 0 0 0 MSR Modem Status Register 5 0 1 0 0 0 0 RXRDY Rec d Xoff signal Special character 6 1 0 0 0 0 0 CTS RTS change of state Enabling disabling the serial ports as interrupt sources The Interrupt Enable Register IER masks the interrupts from receiver read transmitter empty line status and modem status registers These interrupts are normally seen on the INT A D output pins Refer to the ST16C654 datasheet for programming details VSS4 User Guide 135 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Asynchronous serial interface Serial interface connector The figure and table identify the pinout numbers and signals for the VSS4 front panel serial port RJ 50 RJ 69 connector 2 4_6_8 10 1 3 5 7 9 PON Asynchronous serial connector pin numbering Serial Ports A B C amp D P346 pin assignments y 5 Function Transmit Data Serial Port D Transmit Data Serial Port C Transmit Data Serial Port B Transmit Data Serial Port A Ground Gnd internal
234. pace 8 MB 0 based D8 D16 D32 RW FE80_0000 FEBF_FFFF PCI I O Space 4 MB 0 based D8 D16 D32 RW FECO_0000 FEDF_FFFF PCI Configuration Address Reg 2 MB D8 D16 D32 RW FEE0_0000 FEEF_FFFF PCI Configuration Data Reg 1 MB D8 D16 D32 RW FEFO_0000 FEFF_FFFF PCI Interrupt Acknowledge 1 MB D8 D16 D32 RO FF00_0000 FFDF_FFFF Reserved 14 MB FFE0_0000 FFE7_FFFF Boot Flash ROM lower 512 KB ROMBoot D8 RW D64 RO Note 1 FFEQ_0000 FFE7_FFFF EPROM 512 KB FlashBoot D8 RO D64 RO Note 1 FFE8_ 0000 FFE9_FFEF NVRAM 128 KB 16 bytes D8 RW D64 RO FFEQ_FFFO FFE9_FFFF Real Time Clock Calendar D8 RW D64 RO FFEA_0000 FFEF_FAFF Reserved FFEF_FBOO FFEF_FBO7 Serial Port B 8B D8 RW FFEF_FBO8 FFEF_FBOF Serial Port A 8B D8 RW FFEF_FB10 FFEF_FB17 Serial Port D 8B D8 RW FFEF_FB18 FFEF_FB1F Serial Port C 8B D8 RW FFEF_FC00 Mailbox A Read D8 RO FFEF_FC08 Mailbox B Read D8 RO FFEF_FC10 Mailbox C Read D8 RO FFEF_FC18 Mailbox D Read D8 RO VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 109 Section 4 Programming the PowerPC Address map PowerPC Address Map continued Address Device address space description Access FFEF_FD0O0 8 bit User Switch Register D8 RO FFEF_FE00 Board Type and R
235. pace by the Grackle This poses a problem as the Grackle gives priority to write posts writes to ROM space at the expense of other processes waiting for Grackle s services Observation A program had a tight loop which was reading 8 bytes of data from a file and then writing a number to the LEDs which caused 8 write operations to ROM space At the same time that was going on there was lots of contention for the Grackle s services another CPU card tried to make many accesses to the CPUs RAM through the VME interface and onboard DMA transfers were occurring from the Ethernet interface The Grackle in effect gave priority to the writes to ROM space which it performed rather slowly too and serviced the DMA and VMEbus requests in whatever time was left over Occasionally the Grackle would make the Universe II chip wait longer than 16us for the memory access it requested Since the VME timeout is set to the standard value of 16us this longer than 16us wait caused the VMEbus system controller to generate a bus timeout a bus error VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Programming notes MPC106 Solution Altering the LED writing routine solved the problem After each write to an LED a read of that LED is performed The LED read data itself is ignored The act of reading the LED register is what causes the Grackle to
236. peater type hub instead of a switch type hub this LED may still flicker even when the VSS4 is not transferring data since packets sent over the network to other nodes will also be sent to the VSS4 Link Speed lights up orange if cable is connected to a 100Base TX hub LED is OFF if cable is connected to a 10Base T hub Refer to the LED discussion in Section 2 page 20 for more information VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A Programming the PowerPC This section provides programming and operation information for the PowerPC processor and for other devices under its direct control PowerPC architecture MPC106 PCI bridge memory controller Programming notes MPC106 Address map Onboard registers L2 backside cache controller Mailboxes Asynchronous serial interface Clock calendar Non volatile 128K x 8 SRAM Boot Flash ROM EPROM oe 8e e888 eeoeeg 8 8 User Flash memory The bit numbering of registers in this zj section follows the zero on the right convention as opposed to the zero on the left bit numbering convention used by Motorola and IBM in their PowerPC documentation VSS4 User Guide 83 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 84 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com
237. pecial features In diagrams and descriptions in this manual signal names fol lowed by a backslash are active low Notes chapter Within this manual a notes chapter is provided in select sections Some or all of the following notes chapters may be found in this manual Programming notes deals with programming issues o Installation notes deals with installation issues Operating notes deals with operating usage issues Refer to this special information for any notes or caveats for the device or topic under discussion VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 10 Section 1 Overview Manual conventions Bit numbering conventions To avoid confusion be aware that there are two bit numbering conventions The PowerPC architecture was invented by IBM who number their bits with O on the left most significant bit or MSB and 31 on the right least significant bit or LSB This zero on the left numbering convention is reflected in the IBM PowerPC documentation PCI bus and VMEbus both number the bits with O on the right LSB and 31 on the left MSB This zero on the right numbering convention is used in the bit descriptions contained in this manual Bit numbering conventions Binary bits ofdata 1 0 1 1 0 0 1 0 Zero on the right 7 6 5 4 3 2 1 0 Zero on the left 0 1 2 3 4 5 6 7 Web address URL
238. per present on Rev C or higher boards Setting the slot number manually Rev C or higher On a VME64x backplane 5 row connectors a board can automatically sense which slot it is plugged into by reading special pins on P1 These geographical address pins are encoded on the backplane Boards that can read these pins present the geographical address in the VME64 Slot register These boards also check the geographically addressing parity and signal its validity in the same register In some cases the VSS4 will not be able to read these pins because the board is configured with 3 row VME connectors or it may be plugged into an old VME64 backplane 3 row connectors For these situations jumpers on JO2L pins 9 20 are provided to set the board s slot number manually To set a slot number install jumpers over the appropriate pair of pins as shown with a bullet in the table below Pins with no jumper installed are shown with a dash This is a binary encoded scheme with pins 11 amp 12 MSB and pins 19 amp 20 LSB Install the User Defined Slot Number jumper pins 9 amp 10 to let hardware software read the user defined slot number from the VME64 Slot register The value in this register is set by the 5 slot number jumpers Note that user defined slot number jumpers must not be used if both the board and backplane have 5 row connectors VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 88
239. plug in arbiter board Some overlay models allow joining with another overlay section via a bridge board The table below lists the PO overlay components for use with the PO PCI interface PO overlay components Model Number Description BP08 8 slot PO overlay non bridgeable BPM7 7 slot PO overlay bridging to left or right BPM6 6 slot PO overlay bridging to left right both BPM5 5 slot PO overlay bridging to left right both BPR4 4 slot PO overlay bridging to left only BPL4 4 slot PO overlay bridging to right only BP03 3 slot PO overlay non bridgeable BP02 2 slot PO overlay non bridgeable BBPO Bridge board DPPA Arbiter board standup type DPPB Arbiter board flat type The drawing below shows the available PO overlay boards VSS4 User Guide 45 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing the PO overlay Arbiter Board connector BP02 only Arbiter Board connector BP03 only 95 pin socket 95 pin socket connector connector UP 2 places 3 places a BP02 2 slot PO overlay non bridgeable b BP03 3 slot PO overlay non bridgeable Bridge Board connector Bridge Board connector 95 pin socket 2 placas Arbiter Board
240. pt vector The vector value in this field is returned when the Interrupt Acknowledge register is examined and the interrupt associated with this vector is requested Priority Interrupt priority This field sets the interrupt priority The lowest priority is O and the highest is 15 Setting the priority level to O disables interrupts ACT Activity bit read only The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to 1 when its associated bit in the Interrupt Pending or In Service register is set Note that this bit is read only The Vector Priority and Sense values should not be changed while the ACT bitis 1 MSK Mask bit Setting this bit to 1 disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated This bit is always set to 1 following a reset VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 173 Section 6 MPIC Interrupt Controller MPIC registers Spurious vector register 31 16 15 B17 0 Reserved for Reserved Vector Expansion Vector The MPIC will respond to a spurious interrupt by presenting the CPU with the vector stored in this register when it is unable to determine the vector
241. r 512 KB ROMBoot OxFFF8_0000 OxFFFF_FFFF D8 D64 Boot Flash upper 512 KB ROMBoot OxFFFO_0000 OxFFFF_FFFF D8 D64 Boot Flash Flash Boot Block organization For convenience in programming or erasing the block information for the Boot Flash memory is listed in the table below Boot Flash memory block information Flash Memory Size Total Blocks Block Size Block Numbers 1 MB 16 64 KB 0 15 Note that full Flash support is supplied in Synergy s SMon Application Developer and Debugger package Example Flash driver code is also available from Synergy Contact Customer Service for details and ordering information Writing and erasing Write protection of all Flash Boot Flash User Flash and DIP Flash EPROM if installed is set in either or both of two ways Jumper Flash Write Protect J02L pins 9 amp 10 Rev B or lower or pins 21 amp 22 Rev C or higher write protect if jumper ON no write protect if jumper OFF Refer to the Setting up the VSS4 hardware chapter in Section 2 page 23 for more information on the configuration jumpers Software Flash Write Protect Flash ROM register at OxFFEF_FE40 bit O controls protect 1 default and no protect 0 status Refer to the Flash ROM register discussion in Section 4 page 121 for more information on the Flash ROM register To enable writing to Flash memory remove the Flash Write Protect jumper JO2L pins 9 amp 10 Rev B or lower or
242. r Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 47 48 Section 2 Getting Started Installing the PO overlay The drawing below is provided as a guide to assembly of PO overlay components The minimum installation is an overlay board with its arbiter plugged in plugged into the VME backplane Other installations may have one or more overlay sections joined together with a bridge board Observe the following precautions when installing the PO overlay boards First check to make sure that the PO backplane pins are straight With the pins verified or made straight carefully align the overlay board onto the PO backplane pins Ensure that all backplane PO pins properly engage the overlay board socket before fully seating the board If board doesn t begin to seat when pressed against the pins BACK OFF and try aligning the board again To avoid accidental damage to the arbiter board always remove it from its PO overlay socket before handling the PO overlay board This applies especially to the standup type arbiter DPPA used with the BPO2 2 slot PO overlay VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing the PO overlay Cardcage Front VME64x Backplane w PO BPR4 Overlay Board BPM7 Overlay Board DPPB A
243. r is a software Flash write protect bit Setting this bit protects Flash from writes even if the Flash write protect jumper JO2L is removed Clearing this bit allows Flash to be written provided that the JO2L Flash write protect jumper is also removed and that the MPC106 ROM write protect bit has not been set since the last board reset A read of bit 6 indicates the state of the Flash write protect jumper JO2L pins 9 amp 10 for Rev B or lower JO2L pins 21 amp 22 for Rev C or higher When 1 the Flash write protect jumper is ON for Flash write protection When 0O the Flash write protect jumper is OFF to enable Flash writes However this is true only if the write protect bit bO of this register is cleared and if the MPC106 ROM write protect bit has not been set since the last board reset Flash write protection indicated or set by this register applies to Boot Flash User Flash and Flash EPROM if installed in the DIP EPROM socket VSS4 User Guide 121 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 122 Section 4 Programming the PowerPC Onboard registers A read of bit 7 indicates the state of the Boot ROM enable jumper JO2L pins 1 amp 2 which selects between two possible boot sources When 0 the jumper is OFF and boot is from Boot Flash When 1 the jumper is ON and boot is from DIP EPROM Refer to the Setting up the VSS4 hardware chapter page 23 for more
244. rbiter Board SSS DPPB Arbiter Board BPPO Bridge Board Assembly Side View Looking From Above Cardcage Bridge Board Model BBPO Orient board with label Top at DPPB Arbiter upper left DPPB Arbiter Board Flat Board Flat L AN J yY yY BPR4 4 slot PO overlay right BPM7 7 slot PO overlay bridging to right configuration Notes View is from BACK of card cage looking towards front Farside components shown with dashed line A standup arbiter board DPPA is used with BP02 2 slot overlay only 99 0247 PO overlay boards typical component assembly VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 50 Section 2 Getting Started Installing the PO overlay VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installation notes Installation notes Slot installation recommendations The VSS4 and other quad processor boards place extra demands on the chassis for cooling and ventilation Two chassis issues affect this slot location and empty slots Slot location Some slots in a VME or CompactPCl cardcage have little or no airflow End slots in wide e g 21 slot cardcages are often prone to poor airflow as well as slots located between fans It is recommended that these slots be avoided w
245. register discussion in Section 4 page 121 for more information on the Flash ROM register To enable writing to Flash memory remove the Flash Write Protect jumper JO2L pins 9 amp 10 Rev B or lower or pins 21 amp 22 Rev C or higher and clear bit O of the Flash ROM register at OxFFEF_FE40 To protect Flash from writes install the Flash Write Protect jumper JO2L pins 9 amp 10 Rev B or lower or pins 21 amp 22 Rev C or higher or set bit O of the Flash ROM register at OxFFEF_FE40 or take both actions if desired Additional Flash memory information The Flash memory chips have embedded byte write and block sector erase algorithms For more information on the chip itself and on the software aspects of writing erasing Flash memory refer to the Intel Flash memory databook o Intel Flash Memory Databook Order no 210830 For ordering information contact Intel Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 In U S and Canada call toll free 800 548 4725 For general technical information via the Web Intel s Developer site http developer intel com Datasheets for the Flash parts are available in PDF Adobe Acrobat from the Intel s Developer site http developer intel com design flash datashts index htm VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Reset This section provides information about VSS4 res
246. reset then write a 1 to that bit An eieio instruction between the two writes is recommended to enforce proper sequencing of the hardware write cycles Beware that a soft reset performed inside an interrupt service routine will leave the MPIC s internal interrupt under service bit set for that interrupt which will prevent future interrupts from that source from being serviced This interrupt under service bit may be cleared by writing a zero to the End Of Interrupt register for the processor servicing the interrupt For more information on VSS4 reset refer to Section 5 Reset page 157 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ov a ow Section 6 MPIC Interrupt Controller MPIC registers IPI vector priority registers There are 4 IPI vector priority registers one for each IPI dispatch register The IPI vector priority register bit assignments are described below Address map IPI vector priority registers Address Offset Register Access 0x010A0 IPI 0 Vector Priority register R W 0x010B0 IPI 1 Vector Priority register R W 0x010C0 IPI 2 Vector Priority register R W 0x010D0 IPI 3 Vector Priority register R W Note Add to base address set during PCI configuration 20 19 16115 B17 0 ANE HOr Reserved for Vector Expansion Vector Reserved Priority Vector Interru
247. rs Operating registers The table below lists the SYM53C885 Ethernet registers which are accessed through PCI memory or I O cycles depending on operation SYM53C885 Ethernet registers address and descriptions Addr Offset R W Description 0x00 0x03 R W Transmit Channel Control 0x04 0x05 R W Transmit Channel Status 0x06 0x07 Reserved 0x08 0x0B Reserved 0x0C 0x0F R W Transmit CommandPtrLo 0x10 0x13 R W Transmit InterruptSelect 0x14 0x17 R W Transmit BranchSelect 0x18 0x1B R W Transmit WaitSelect 0x1C 3F Reserved 0x40 0x43 R W Receive ChannelControl 0x44 0x45 R Receive ChannelStatus 0x46 0x47 Reserved 0x48 0x4B Reserved 0x4C 0x4F R Receive CommandPtrLo 0x50 0x53 R Receive InterruptSelect 0x54 0x57 R Receive BranchSelect 0x58 0x5B R W Receive WaitSelect 0x5C 0x7F Reserved 0x80 0x81 R W EventStatus 0x82 0x83 R W InterruptEnable 0x84 0x85 R InterruptClear 0x86 0x87 InterruptStatus 0x88 0x8B Reserved 0x8C 0x8F Chip Revision 0x90 0x93 DBDMA Control 0x0x94 TxThreshold 0x95 0x97 Reserved 0x98 0x9B Reserved 0x9C 0x9D Reserved 0x9E General Purpose 0x9F General Purpose Control 0xA0 0xA1 R Configuration 0xA2 0xA3 R W Back to Back Interpacket Gap 0xA4 0xA5 R W Non Back to Back Interpacket Gap 0xA6 0xA7 R W MIIM Command 210 VSS4 User Guide Artisan Technology Group
248. rsessseesseesueesssecseesneecntecatecseesseeeseeeneessneesneeseeese 281 PCs GOmnth SUT ett Ob izssezstexccssscsesteescznssssscyconstessesasepasateacarsuseastepzatesscencasaieststcasaseassseaseuseteaatensstereetecsiaszesst e PCI 9080 basic set up n REGISEEMS scscsssasissnosscsssssiessoessesssenssusteadsesscesscesasenssessssusanseusns ostossetasn oben sesuasttsnaceussotsssecdsbsnndtostossessensaseassese Board type register OXC000_0000 RO sssssesesssessecsessesnesssessecusessessecaseneecnecneeanecneeneensecneesneees 284 Revision and ECO level register OxCO00_0004 RO 1 284 Flash configuration register OxCOO00_0008 RO 1285 DRAM configuration register 0OxC000_000C RO 1285 Using PEX3 MCMOSY wu sees 1 286 PEX3 connector pinouts uu eee 1 287 VME s connectors PI Se P2 vinione nei NE 288 PMG GOMMOCIONS sigscsisccasedatescaslacecsssezsstasiesneccodtescarsussosessdaadsovsessardsssaiuscintiesyasisesniestandoseyscunbascoseaateviosdern 290 GIOSSANY A O E E E E E tase deccens A E tenets ee eee 295 INGOX A E E E E E E 305 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com vii Manual revision summary Manual revision summary Section 2 App B Section 4 Appendix C Appendix D Revision level Revision date Section Affected chapter description 1 0a 3 16 99 1st Preliminary Release 1 0b 5 28 99 2nd Preliminary R
249. rtisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 21 Section 2 Getting Started Front panel The CPU LEDs indicate the run status of the CPUs LED Label Indication CPU X Dual color LED CPU X Y Z W Run Status CPU Y Green Run Red Halt CPUZ Flickers green in response to Lights red when CPU has halted CPU W PowerPC bus activity by CPU X Y ZM lf not on indicates CPU is not executing bus cycles as it executes instructions in cache or waits for an interrupt The three LEDs on the VSS4 motherboard indicate Ethernet port status as follows Green Link OK lit when 10Base T 100Base TX cable is properly plugged into a functioning Ethernet network and onboard software has initialized the Ethernet interface Yellow Link Activity flickers whenever data is being received or transmitted If the VSS4 is connected to a repeater type hub instead of a switch type hub this LED may still flicker even when the VSS4 is not transferring data since packets sent over the network to other nodes will also be sent to the VSSA Orange Link Speed lit when operating as 100Base TX LED is OFF when operating as 10Base T Lamp test feature During board level reset all LEDs are illuminated to provide a lamp test You can confirm proper operation of the LED indicators as you do a board level reset by observing the LEDs and pushing the CPU reset switch to the right Hold switch i
250. s set during PCI configuration 174 V554 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 31 Section 6 MPIC Interrupt Controller MPIC registers Timer frequency reporting register Timer Frequency 31 30 Timer Frequency This register is used to report the frequency in Hz of the clock source for the global timers The global timers clock source is the MPIC input clock frequency divided by 8 This register contains zero after a Reset System initialization code should initialize this register to one eighth the MPIC clock frequency once the MPIC clock frequency VSS4 s 33MHz PCI clock has been determined A typical value for this register would be 0x003F_940B indicating each timer is updated once every 240nS Global Timer Current Count register Current Count 31 30 Current Count The current count is loaded with the base count and the toggle bit is cleared whenever the Base Count register is written and the Count Inhibit bit in the Base Count register transitions from 1 to 0 The timer decrements while the Count Inhibit bit in the Base Count register is zero When the time counts down to zero an interrupt is generated the toggle bit is inverted and the current count is reloaded from the base count Following Reset counting is disabled and the current count register contains zero T Toggle This bit toggles whenever th
251. san Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers A write to this register enables 1 or disables 0 the CPU s X Y Z or W internal timebase generator This internal timebase generator is a free running counter that runs at the CPU s core frequency Software can use this free running counter to determine the speed at which the processor is running or other timing functions as required A read of this register returns the status of the timebase enables disables Flash ROM register OxFFEF_FE40 RW Bt7 6 5 4 3 2 1 0 x x x x x 1 Reset value Bit assignments Bit s Function Values b7 Boot ROM Enable jumper JO2L 1 amp 2 RO 0 Jumper OFF Boot Source is Boot Flash 1 Jumper ON Boot Source is DIP EPROM b6 Flash ROM Write Protect Jumper 0 Jumper OFF no write protect J02L 9 amp 10 or 21 amp 22 RO see text 1 Jumper ON write protect b5 b1 Reserved b0 Software Flash ROM Write Protect RW 0 Flash ROM not write protected jumper ON overrides this 1 Flash ROM write protected set bit overrides jumper OFF NOTE When Flash ROM is not write protected only CPU X has access to it Jumper refers to J02L Flash Write Protect jumper This register addresses the board s Flash ROM operation Bit O of this registe
252. santg com Section 2 Getting Started Front panel Toggle switch The VSS4 is provided with a toggle switch for RESET and SMI interrupt RESET Pushing the switch to the right asserts a board level RESET that o Resets the CPUs o Resets all on board components that have such a function and clears all on board control registers Asserts a VME RESET if the board is serv ing as the System Controller SMI Pushing the toggle switch to the left asserts an SMI interrupt to all CPUs on the board Close up of RESET and SMI switch VSS4 User Guide 19 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Front panel LEDs Shown below are the VSS4 front panel and onboard LEDs that provide a quick indication of board activity The following describes the function of these LEDs Status LEDs Fail Red Fail User LEDs 0 7 SC Green System Controller mode Yellow VME Green Master Red Slave PCI Green PCI Yellow PCI Expansion CPU Run Halt LEDs Red Halt Green Run Front panel lower o Fast Ethernet Jack Ethernet Link Status LED Green Link OK Ethernet Link Activity LED Yellow Activity Ethernet Speed LED Orange 100Base TX Not Lit 10Base T 99 0026 VSS4 LEDs VSS4 User Guide Artisan Techn
253. seesreneecsecseestenseeneenerseeasets External configuration registers ccseecseecsessessesecneecseecseecseecscssucesucesucecucecurecseesseceseecsecsseessueessetersees Programming notes MPC106 ssssssssssssssersssesrrrisereeen Setting PCI device base address Write posting to ROM Space Address MAP sesssssssssscsessnssessessnssenseeensssosees CHRP address map PClcomfiguitation and address nnii nE E E OVE S AT VSS4 address MaDi ssri eeri aa SEE r E A EEr da EEAS ANATEL TEREN ATSE EEE RS Onboard registers Board information registers Board type and revision register OXFFEF_FEOO RO s ssssessssssssssssssssssssssssssssssssssrnssssrreesssreees 114 Special mod and ECO level register OXFFEF_FEO8 RO ccssscsssssessesssessssesesseesssseesesseeseesees 115 Board family and feature register OXFFEF_FE10 RO c ssssesssssssssscsessesseesssssecsecseessesnecneeseenes L2 cache register OXFFEF_FE30 RO Memory register OXFFEF_FE38 RO Secondary PCI Slot register OxFFEF_FE48 RO VME64 Slot register OXFFEF_FF30 RO c ssssssscssssssessessesesessessesseeseeseeseeeseesesseesesseeeseeseeaeeneeses SATUS TE SISESIS sscecesvsescedscszuscactss canstecescssnss E AN a A A T E I R E E TEE Eight bit user switch register OxFFEF_FDOO RO Board status register OXFFEF_FE18 RO c ssssssesssesssesseessccseecseessuessueessecsucesucenusenueesneesneenseeseeeees CPU status register OXFFEF_FE20 RO csssssssssssssesce
254. ser Guide Copyright 1999 2003 Synergy Microsystems Inc This manual is copyrighted under Title 17 US Code of the United States Copyright Law All rights are reserved by Synergy Microsystems Inc This document may not in whole or in part be copied photocopied reproduced translated scanned or reduced to any electronic medium or readable form without the express written consent of Synergy Microsystems Inc This document contains material of a proprietary nature to Synergy Microsystems Inc All manufacturing use and sales rights pertaining to this product are expressly reserved Distribution of this material does not convey any license or title under any patent or copyright It is submitted in strict confidence to provide technical information for purchasers of this product or for those considering the purchase of the product Each recipient by accepting this document agrees that its contents will not be disclosed in any manner or any person except to serve this purpose Synergy Microsystems Inc reserves the right to make changes to the specifications and contents in this document without prior notification If in doubt users are urged to consult Synergy to determine whether any such changes have been made Synergy products are not intended for use in life support systems or other applications where a failure of the product could result in injury or loss of life Customers using or selling this product in systems or applications serv
255. space in VSS4 3 Maps to VSS4 s onboard registers and all ROM NVRAM 4 Synergy does not use the compatibility hole which needs to be explicitly enabled to be present For the VSS4 this space is part of the 1GB system memory RAM space allocation permitted by the CHRP address map VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Address map Address map B PCI I O master view PCI I O Transaction Address Range PowerPC Processor Hex Decimal Address Range Definition 0x0000_0000 0x0000_FFFF 0 64K 1 No system memory cycle PCI ISA I O space 0x0001_0000 0x007F_FFFF 64K 8M 1 No system memory cycle Reserved 0x0080_0000 Ox00BF_FFFF 8M 12G 1 No system memory cycle PCI I O space 0x00C0_0000 OxFFFF_FFFF 12M 4G 1 No system memory cycle Reserved Processor View PCI Master Memory View PCI Master I O View 0 0 0 System memory q System memory r 4 ISA bus ports 640K 640K Compatibility hole Compatibility hole 768K iN i i pas ell i 1 8M System memory i System memory f ni p PCI I O space ni 42M 16M 1 16M 1 11 l I System memory i System memory i f E tt l 1G SPM mm 1G SPM M I k It US i i Di j l 2C TM M o C o A I i Li og vy l i i J i PCI memory i i PCI memory B I T in i tt i I 4G 48M 4G L 48M PCI ISA memory p 4 System memory
256. speed The Ethernet prototype was developed by Xerox Corporation in 1975 and grew to a standard LAN specification 10 years later IEEE 802 3 1985 with the collaborative efforts of Digital Equipment Corporation Intel Corporation and Xerox Corporation From the standard Ethernet specification came the 10Base T Ethernet standard that used inexpensive unshielded twisted pair cable terminated in modular plugs The popularity of 10Base T fueled the development of Fast Ethernet 100Base T which incorporated new signaling schemes to provide a 100 Mbps data rate over a range of twisted pair 100Base TX 100Base T4 and fiber cabling 100Base FX types 100Base TX provides an easy migration path to higher performance since it can use existing 10Base T cables and equipment for interim 10Base T operation Changing over to Category 5 cable and Fast Ethernet hubs automatically switches the network to Fast Ethernet operation Ethernet provides what is called a link level facility since it deals with the lowest two layers of network architecture as defined by the ISO Model for Open Systems Interconnection the Physical Level and the Data Link Layer With Ethernet the type of data it transmits is immaterial since it does not concern itself with data protocol and interpretation As such Ethernet LANs are used for various types of computing platforms such as mainframe computers Macintoshes IBM PC and compatibles SPARC workstations UNIX systems etc
257. srlO73 10 UsrlO74 11 UsrlO75 12 UsrlO76 13 UsrlO77 14 UsrlO78 15 UsrlO79 16 UsrlO80 17 UsrlO81 18 UsrlO82 19 Usrl083 20 Usrl084 21 UsrlO85 22 UsrlO86 23 UsrlO87 24 UsrlO88 25 Usrl089 26 Usrl090 27 UsrlO91 28 UsrlO92 29 Usrl093 30 Usrl094 31 Usrl095 32 UsrlO96 33 Usrl097 34 Usrl098 35 Usrl099 36 Usrl0100 37 UsrlO101 38 Usrl0102 39 Usrl0103 40 Usrl0104 41 Usrl0105 42 UsrlO106 43 Usrl0107 44 UsrlO108 45 Usrl0109 46 Usrl0110 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Note 1 The function of pins labeled UsrlOxxx depends on the add on card installed on the board Space is provided in these columns to write the assigned signals if desired 294 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Glossary The paragraphs below define and describe some of the terms used in this manual The definition entries observe the following conventions o Terms in definitions that appear in italics and in parentheses are related and or alternative terms or acronym translations for the term being defined Terms in definitions that appear in boldface in definitions are defined elsewhere in the glossary 9 10Base T a type of Ethernet that uses unshielded twisted pair UTP cable and modular RJ 45 connectors for LAN connections in a star configuration i e
258. ssessecsecsseeseeseeesscssusesseecseecsecsecsecsssccsuecsuecsueesusessueeeneessueeenees 156 Section S Resets iseenese nr aE EE Ta Aa a E SEE EEES 157 Reset information W159 General description PCI reset 160 Hard reset sources 160 POW IMOMNICON ornini AGRA A N 161 Eront panel treset Swit liisscaiss sarssccussedseastelarsscnassdoseoncasosuneaseqistayanaesavennctassgestavindentedascnassasseeseancersc etanstees 161 External VME SysReset a Watchdog CUTTS es sanececeazsnzcxsaccesavxsouzcsiansasesactovaaeaodas cous avg ctavanenteasonasian gave mneauencaar nn ouacmnnivaiatccrervanraens Universe Il software reS t ceccecsessssssssesessssssesesseesessessesucsucsscesecuesscsucsecseesecsesaesneenceuceuceucsuesuceseeaeeaeenses 163 SOIE SE Ter na NA T ER EIRE ainda aula EAGT 163 Section 6 MPIC Interrupt Controller ccccccccccccccccecccccccccccccccccccccccceccescecsceeeeeeees 165 General deschptiOiss meane e aR A E Eaa EAER N E EEA NEA TE ER 167 MaE N E E E E L E E E 169 MPIC base addre SSi A E E A a 169 Global registers Feature reporting TESISTED ssssssscsessssssssecssssssscssusssseossssssssnssnasssnseosssaosnsuosnsasanseensssessssossstesbssessssneesesszess Global configuration registers Vendor identification register Processor init FEBISTER ss cis 5 cnivastisdersnsstessscnes sede onsernctebocesesdeapuviasasdebasdvesnessbvendencdeluesesucestresesiceegstesosnoes VSS4 User Guide Artisan Technolo
259. ssesseesesseeseesescsesaesaessesnecuesecsesensaeeneeseeseesess VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table of contents Control MOde registers esssessecseessesecnsecneessueesseesneeesteenees CPU Timebase register OxFFEF_FE28 RW Flash ROM register OxFFEF_FE40 RW es Flash Window register OxFFEF_FE50 WO sssssessessseecssecneecneesseecseecneesseesseecatecnesentecseecseerseesses PCI error register OXFFEF_FE7O RO sssssssssssssscssssesescesenescsscsssseccnsessesecueeussssecuessnecnsessecseesesane PO PCI interrupt assert pending register OxFFEF_FE68 RW aise PO PCI interrupt mask register OXFFEF_FEGO RW sssssesssssesececneessesecnecneesnenseeneeneesnente User LED registers OxFFEF_FE80 OxFFEF_FE88 OxFFEF_FE90 OxFFEF_FE98 OxFFEF_FEAO OxFFEF_FEA8 OxFFEFFEBO OxFFER_ FEBS RW sscsssssssssessessssssssssusessssenseastssicacsesssanssssestesnsasstsenes 124 VME64 SysReset register OxFFEF_FF38 RW we 125 Watchdog enable register OxFFEF_FF40 WO wT 25 Watchdog pet register OxFFEF_FF48 WO 126 Backside L2 cache controller sesssssssssssesesssssssssssssssrceseesssssssssesereeeesee eel 27 How to use the backside L2 cache Mail DOXCS sic ctlsssstesecesessticacgctasrescdecetsatasecceaviedertes Asynchronous serial interface IQR ISLOUS veovcessecistalccisscscustyecs cos csuevesnsg
260. ster VAERR F90 VMEbus Slave Image 4 Control register VSI4_CTL F94 VMEbus Slave Image 4 Base Address register VSI4_BS F98 VMEbus Slave Image 4 Bound Address reg VSI4_BD F9C VMEbus Slave Image 4 Translation Offset reg VSI4_TO FAO Reserved FA4 VMEbus Slave Image 5 Control register VSI5_CTL FA8 VMEbus Slave Image 5 Base Address register VSI5_BS FAC VMEbus Slave Image 5 Bound Address reg VSI5_BD FBO VMEbus Slave Image 5 Translation Offset reg VSI5_TO FB4 Reserved FB8 VMEbus Slave Image 6 Control register VSI6_CTL FBC VMEbus Slave Image 6 Base Address register VSI6_BS FCO VMEbus Slave Image 6 Bound Address reg VSI6_BD FC4 VMEbus Slave Image 6 Translation Offset reg VSI6_TO FC8 Reserved FCC VMEbus Slave Image 7 Control register VSI7_CTL FDO VMEbus Slave Image 7 Base Address register VSI7_BS FD4 VMEbus Slave Image 7 Bound Address reg VSI7_BD FD8 VMEbus Slave Image 7 Translation Offset reg VSI7_TO FDC FEC Reserved FFO VME CR CSR Reserved FF4 VMEbus CSR Bit Clear register VCSR_CKR FF8 VMEbus CSR Bit Set register VCSR_SET FFC VMEbus CSR Base Address register VCSR_BS Note 1 Avoid updating slave image registers while VME traffic is using the slave window Doing so results in VME data errors See Programming notes Universe Ilon page 199 for more information 194 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME6
261. t the SYM53C885 is a multifunction PCI device Thus SCSI and Ethernet functions are programmed as separate entities by the PCI auto configuration For more information on PCI configuration refer to the PCI implementation details discussion in the PCI bus chapter in Section 3 page 62 and the Setting PCI device base address discussion in Section 4 page 101 Also refer to the Type 0 configuration table on page 108 The following is an overview of the registers in each interface VSS4 User Guide 205 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 8 SCSI Ethernet controller SYM53C885 registers SCSI registers PCI configuration The PCI configuration registers for the SCSI interface are shown below Addresses 0x40 through OxFF are unused 31 16 15 0 Device ID Vendor ID 0x00 0x000D 0x1000 Status Command 0x0000 0x04 Class Code 0x010000 Revision ID 0x00 0x08 BIST Header Type Latency Timer Cache Line Size 0x0C Base Address Register 1 0x10 Base Address Register 2 0x14 Base Address Register 3 0x18 Not Supported 0x1C Not Supported 0x20 Not Supported 0x24 Reserved 0x28 Subsystem ID Subsystem Vendor ID 0x2C Expansion ROM Base Address 0x30 Reserved 0x34 Reserved 0x38 Max Lat Max_Gnt Interrupt Pin Interrupt Line 0x3C Note Setting bit0 or bit 1 of the PCI command register enables the SCSI interface to r
262. tation details 62 PCI configuration 63 Endian issues byte swapping PCI standards organization SESI DUS te tates ccieer Aisi nian OVENI Winey ian r A A E EAEE OO O AEEA IEO p A E EEEE SCSI specifications and publications es DQVICE COMMECUIOINS sers eve eusadonteccasssusuncvar E EEEa VSS4 User Guide WM Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table of contents Electrical connections Physical topology Bus terminations ae BUS COMMUNICATION CONKIOL cesssssesesesseseseseessscsesesessescsescsesssscscsesescssescscsesssescacscsesssscssscsesseessesssacseseessacseseestecesees Datta transterOptiOmssssasesscssssesscssncosssesvsadeancssstanccoxssovendencasstousebasensaduousadsten corisesivedeatesieseasecssisseaietadshdesensasisontsaasienie Fast Ethernet interface ee Ethernet network CONNECTIONS ccccccccsesescesescsssesesecscscsescsssscsesesssssssscscsesesecscscsssessscscsescsesssscacsusscsesescscseseeseaeseses 78 DatantransmiS SiO ee E O RO ck ssssesdockac si A sata hTea E A 79 Ethernet ID or physical address 80 Avoiding bus contention CSMA CD Interchange signals 81 LED indicatore enn e A N sen ene nests npn 82 Section 4 Programming the PowerPC ccccccccecseeeecececeeeeeeececeeeeeeeeeeeseeeeeeeeseeseeeeeeens 83 PowerPC architecte ninni rains aA OREN ENAA 85 VPP OCU GTI e AAN EE EEE EE 85
263. tchdog is disabled The watchdog is held off from resetting the board by periodic writes alternating between O and 1 to the watchdog pet register bO A 0 to 1 transition at least once every 250 milliseconds is required The code may twiddle this bit as often as it likes as long as this maximum time is not exceeded This periodic writing to the watchdog pet register is typically done in the main polling loop of the application program Should the program fail to write to the watchdog pet register the watchdog times out and the board system is reset Refer to Section 5 Reset page 157 for detailed reset information This register present on Rev C or higher boards only 126 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Backside L2 cache controller Backside L2 cache controller The 750 7400 7410 processor has an onboard L2 cache controller with a dedicated port to the external synchronous SRAMs 1 MB for Rev D or lower boards 1 MB or 2 MB for Rev E or higher boards The L2 backside cache maintains cache coherency through snooping and is normally configured for copyback mode For the 750 G3 processor the L2 cache is a two way set associative tag memory with 4096 tags per way With 1 MB of SRAM the L2 tags are configured for four sectors 128 bytes per L2 cache block For the 7400 7410 G4 processor the L2 c
264. teed 888 88 SOURCE www artisantg com 99 Section 4 Programming the PowerPC MPC106 PCI bridge memory controller 100 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Programming notes MPC706 Programming notes MPC106 Setting PCI device base address Each PCI device has a standard set of configuration registers accessed with PCI configuration cycles using the Grackle s CFG_ADDR OxFECO_0000 and CFG_DATA OxFEEO_0000 registers Refer to the type 0 and type 1 configuration register tables from the PCI spec The standard Synergy Microsystems PowerPC SBC configuration addresses for PCI devices are listed in the VxWorks svgm1 h header file Most OS s contain PCI configuration access routines VxWorks for example has readMpc and writeMPCc readMPC 0x80006800 returns a 32 bit value which is the VendorlD and DevicelD registers of the first PMC daughterboard or OxFFFF_FFFF if none exists And writeMPC 0x80006810 0xe00000000 writes the address 0xE000_0000 to a type O device s configuration register 0x10 BARO Each device defines some of its Base Address Registers to be the address of a particular bank within it usually additional registers or dual ported memory Bit O of the register specifies the PCI space in which it is to be placed O for PCI Memory and 1 for PCI I O space B
265. tem Quantity Synergy part Item locator in assy number description O 4 Fas SwM25FP6S Screw M2 5 thread pan head phillips 6 mm long steel or use whatever screw fastener is supplied in PMC card kit O ring Groove Gasket T a PMC car oi p I A Se front panel Place o ring gasket in front panel groove S PMC CARD Filler panel Front panel PMC cutout Screw M2 5 6mm PMC Connectors panhd 4 places g0 o Rubber o ring gasket in place Tilt front VMEbus panel into connectors SBC cutout 9 Screw M2 5 thread 6mm a pan head slot 4 places B Eject Knob PMC Card SBC ra PMC connectors to E VIEW A A Side View PMC Card Installation 01 0059 PMC card installation VSS4 User Guide Artisan Technology G roup Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 43 44 Section 2 Getting Started Installing PMC cards VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing the PO overlay Installing the PO overlay The PO overlay is used to interconnect boards within the same cardcage via Synergy s PO PCI interface Refer to Section 9 page 215 for a description of the interface The PO overlay board comes in left right and center configurations of varying slot capacities Each overlay uses a small
266. th and use the GPS satellite s onboard atomic clock as a time reference Interrupt Acknowledge a VMEbus signal used by a Master to indicate that an interrupt was received manufacturer of the Selectric typewriter and inventor of the 80 column punched card Collaborated with Motorola and Apple Computer in 1991 to invent the PowerPC based on IBM s RISC design called POWER Performance Optimization With Enhanced RISC Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com interrupter interrupt handler YO ISP JEDEC L1 cache L2 cache LED Little Endian longword mailbox Master mem protect MMU us VSS4 User Guide Glossary a circuit that sources interrupts usually at the behest of peripherals An interrupter must drive an interrupt line and provide a vector number during an interrupt acknowledge cycle In VMEbus devices it may cease driving the interrupt line upon the interrupt being acknowledged ROAK or wait until a register access to the peripheral explicitly removes the request RORA a circuit usually in conjunction with a CPU that acknowledges and handles interrupts Input Output In System Programmable logic a high density programmable logic device that can be programmed while the device is in the circuit ISP logic can be upgraded easily in the field using a standard PC and a simple adapter cable Joint Electronic Device Eng
267. the byte of data at exactly the specified address i e the most significant byte will be written to the FIFO VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Asynchronous serial interface Asynchronous serial interface The VSS4 s asynchronous serial ports are provided by Exar Corporation s ST16C654 quad UART chip The four serial channels A D are brought out to a single RJ 69 jack on the front panel The ST16C654 features 64 bytes of transmit and 64 bytes of receive FIFO per channel This reduces overall UART interrupt servicing time which allows the CPU extra time to run other processes multitask For more information about Yi programming the ST16C654 refer to the Exar ST16C654 datasheet This can be obtained by contacting EXAR Corporation 48720 Kato Road Fremont CA 94538 510 668 7000 FAX 510 668 7017 The datasheet is also available on Exar s website http www exar com products st16c654 pdf Registers The ST16C654 provides 14 internal registers per channel for monitoring and control These registers are summarized in the table below VSS4 User Guide 131 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 132 Section 4 Programming the PowerPC Asynchronous serial interface Asynchronous serial interface registers ST16C654
268. ting Started Installing the RGS3 memory module RGS3 Memory Module _ S a S id CCEA A A CLAN a Q O Q O 99 0027 RGS3 memory module location top view This chapter describes field installation of an RGS3 memory module If the desired RGS3 module is already zi present on the VSS4 board proceed to the next chapter in this section 34 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 2 Getting Started Installing the RGS3 memory module Installing upgrading the RGS3 memory module Perform the following steps to install or upgrade an RGS3 memory module Verify proper operation of motherboard if replacing an existing RGS3 memory module Before attempting to install a new RGS3 memory module on a working CPU motherboard consider checking that the motherboard and any attached PMC cards are operating properly Power down and remove CPU motherboard from card cage if necess
269. ting point load and store Integer load and store with byte reversal instructions Flow control instructions Branch and trap instructions Condition register logical instructions Processor control instructions Move to from SPR instructions Move to from MSR Synchronize VSS4 User Guide 89 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC PowerPC architecture Instruction synchronize Order loads and saves e Memory control instructions Supervisor level cache management instructions User level cache instructions Segment register manipulation instructions Translation lookaside buffer management instructions Detailed information on the PowerPC architecture can be found in the PowerPC Microprocessor Family The Programming Environments manual available from IBM or Motorola PowerPC G4 processor The PowerPC G4 74xx is a 4th generation PowerPC processor This processor is similar to the PowerPC G3 750 with exception of the G4 s 128 bit vector unit that operates concurrently with the 32 bit integer and floating point units The addition of the vector execution unit is the basis for Motorola s AltiVec technology With its AltiVec technology the G4 provides for highly parallel operations with the ability to execute up to 16 operations in a single clock cycle The G4 performs a type of parallel processing called
270. tion Transmit Data Serial Port D Transmit Data Serial Port C Transmit Data Serial Port B Transmit Data Serial Port A Ground Gnd Ground Gnd Receive Data Serial Port A Receive Data Serial Port B O l OINID al A IN Receive Data Serial Port C oO Receive Data Serial Port D P2 P3 P4 P5 to from ext serial device pin assignments D 5 Function Transmit Data Ground Gnd Ground Gnd Receive Data olol NID AIIAJN oO VSS4 User Guide 261 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors Serial I O cabling 262 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix B Specifications The VSS4 SBC conforms to the following set of specifications and standards VMEbus compliance IEEE 1014 VMEbus Specification Rev C 1 amp D 1 Master A32 A24 A16 D32 D16 D08 EO RMW RWD ROR FAIR UAT BLT32 BLT64 Slave A32 A24 D32 D16 D08 EO RMW UAT BLT32 BLT64 Interrupter 1 7 D08 O ROAK Interrupt handler H 1 7 D08 O Physical dimensions The VSS4 printed circuit board conforms to VME 6U requirements for form factor board spacing and board thickness Board Size 6U 6 4 x 9 19 x
271. tion on the VSS4 non volatile SRAM refer to the Non volatile 128K x 8 SRAM chapter in Section 4 page 143 Avoiding bus contention CSMA CD To avoid contention from two or more stations trying to talk at the same time on the network Ethernet uses a media access method called CSMA CD Carrier Sense Multiple Access with Collision Detection With CSMA CD a station transmits a frame only when the network is not busy If a collision does occur after a transmission the station resolves it by retransmitting the frame 1 To avoid contention stations monitor a carrier signal an encoded clock signal integrated with the data that indicates whether or not another station is transmitting If a station has data of its own to transmit and the network is not busy it is sent immediately Otherwise if the network is busy the station waits until it senses no activity plus an extra delay time padding for channel recovery before transmitting its own data VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions Fast Ethernet interface 11 When a collision does occur all stations are notified of the occurrence by a signal applied to their Collision Detect input Any station that is currently transmitting must stop and wait a certain amount of time before retransmitting the frame The station s location on the network is factored into the time del
272. tions that provide a yj wider operating temperature range are available Contact Customer Service for a listing of Thermal Capability options Humidity 10 to 90 RH non condensing Altitude 10 000 ft max with battery backup 50 000 ft max with capacitor backup option Capacitor backup option Time to charge 2 hours minimum capacitor with residual charge 12 hours maximum capacitor fully discharged Backup duration 12 days 20 C typical Number of VME slots used 1 Board layout See drawings below for VSS4 and RGS3 board layout 264 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix B Specifications 10 98UU0D SNQIWA n6 d Bod dSI 890S OINd 0d 40 98UU0D Dd Od Od 5 Zd 5 uIs ea ao L OCC TEU CU ce pare CI JI 1 M
273. tor 59 RST Reset Any device 60 MSG Message Target 61 SEL Select Initiator Target 62 C D Control Data Target 63 REQ Request Target 64 VO Input Output Target 19 53 No Connection Note Signals in bold italic are provided as plus and minus signal pairs for differential SCSI For single ended SCSI each of these signals is provided as one negative polarity line and the DIFFSENSE signal is unused Physical topology SCSI devices are connected one after the other in daisy chain fashion Up to seven devices can make up this chain See Electrical connections above for the maximum cumulative length of the chain VSS4 User Guide 73 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 74 Section 3 Basic Bus Descriptions SCSI bus Bus terminations All SCSI signals must be terminated at each end of the SCSI chain to ensure clean signals and proper timing of bus operations This is achieved either by a voltage divider resistor network powered by the TERMPWR pin on one of the SCSI device connectors or by active circuitry that provides the same function The VSS4 SCSI interface has active termination circuitry that is enabled disabled with configuration jumper JO2L pins 3 amp 4 See Section 2 Setting up the VSS4 hardware for more information on the SCSI termination jumper Bus communication control The SCSI interface uses the following eight phases or bus states to con
274. trol communication over the bus 1 Bus Free indicates that no SCSI device is actively using the bus and that it is free Arbitration an optional phase in which SCSI devices arbitrate for use of the bus Selection lets an initiator select a target to perform a function such as a Read or Write command Reselection an optional phase in which a target reconnects to an initiator to continue an operation that was previously started but was suspended by the target Command lets a target request command information from the initiator Data allows data transfer from target to initiator or from initiator to target O Status allows status information to be sent from target to initiator Q Message allows sending of single or multi byte messages from target to initiator or from initiator to target The last four phases listed above are called information phases since they transfer command data status or message information VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 3 Basic Bus Descriptions SCSI bus Data transfer options Asynchronous and synchronous protocols are used in the SCSI bus The asynchronous protocol requires a handshake for every byte transferred The synchronous protocol transfers a series of bytes before the handshake occurs This means a higher data transfer rate for synchronous mod
275. ts Pin Row Z Row A Row B Row C Row D 1 UsrlO66 UsrlO2 5V UsrlO1 UsrlO65 2 Gnd Usrl04 Gnd UsrlO3 Usrl067 3 UsrlO69 UsrlO6 Retry UsrlO5 UsrlO68 4 Gnd UsrlO8 A24 Usrl07 Usrl070 5 Usrl072 UsrlO10 A25 UsrlO9 Usrl071 6 Gnd UsrlO12 A26 UsrlO11 Usrl073 7 Usrl075 UsrlO14 A27 UsrlO13 Usrl074 8 Gnd UsrlO16 A28 UsrlO15 Usrl076 9 UsrlO78 Usrl018 A29 Usrl017 Usrl077 10 Gnd Usrl020 A30 Usrl019 Usrl079 11 Usrl081 Usrl022 A31 Usrl021 Usrl080 12 Gnd Usrl024 Gnd Usrl023 Usrl082 13 Usrl084 Usrl026 5V Usrl025 Usrl083 14 Gnd Usrl028 D16 Usrl027 Usrl085 15 Usrl087 Usrl030 D17 Usrl029 UsrlO86 16 Gnd Usrl032 D18 Usrl031 Usrl088 17 Usrl090 Usrl034 D19 Usrl033 Usrl089 18 Gnd UsrlO36 D20 UsrlO35 Usrl091 19 Usrl093 Usrl038 D21 Usrl037 Usrl092 20 Gnd Usrl040 D22 Usrl039 Usrl094 21 Usrl096 Usrl042 D23 Usrl041 Usrl095 22 Gnd Usrl044 Gnd Usrl043 Usrl097 23 Usrl099 Usrl046 D24 Usrl045 Usrl098 4 Gnd Usrl048 D25 Usrl047 UsrlO100 25 UsrlO102 UsrlO50 D26 UsrlO49 UsrlO101 6 Gnd Usrl052 D27 Usrl051 Usrl0103 27 Usrl0105 Usrl054 D28 Usrl053 UsrlO104 28 Gnd UsrlO56 D29 Usrl055 Usrl0106 29 Usrl0108 Usrl058 D30 Usrl057 Usrl0107 30 Gnd Usrl060 D31 Usrl059
276. uality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC MPC106 PCI bridge memory controller Error handling registers The error handling registers control the MPC106 s error handling and reporting Register Name Size Address Offset ECC single bit error counter register byte 0xB8 ECC single bit error trigger register byte 0xB9 ErrEnR1 byte 0xC0 ErrDR1 byte 0xC1 60x Bus error status register byte 0xC3 ErrEnR2 byte OxC4 ErrDR2 byte OxC5 PCI bus error status register byte OxC7 60x PCI error address register byte OxC8 Memory interface registers Memory boundaries starting and ending addresses memory bank enables memory timing and external memory buffers are all controlled by the memory interface configuration registers MICRs Register Name Size Address Offset Memory starting address register 1 longword 0x80 Memory starting address register 2 longword 0x84 Ext memory starting address register 1 longword 0x88 Ext memory starting address register 2 longword 0x8C Memory ending address register 1 longword 0x90 Memory ending address register 2 longword 0x94 Ext memory ending address register 1 longword 0x98 Ext memory ending address register 2 longword 0x9C Memory bank enable register byte 0xA0 Memory page mode register byte 0xA3 MCCR1 longword 0xF0 MCCR2 longword OxF4 MCC
277. ually the lowest address of a memory window or of a set of peripheral registers Binary Coded Decimal a coding system in which four binary 1s and Os digits represent each digit in a decimal 0 through 9 value see Endian the smallest unit of data represented as either a 1 ON or true or O OFF or false Block Transfer a data transfer method for moving large amounts blocks of data A BLT cycle is faster and more efficient than a regular R W cycle because the address to start the transfer of multiple bytes is presented only once a chip that connects two different busses together A bridge may be either transparent meaning that it does not translate the addresses passing through it or it may be non transparent meaning that it translates addresses a unit of data eight bits in length the amount of memory read into or out of cache in a single operation This is 32 bytes in 60x and 7xx PowerPC processors special RAM memory that provides the processor with quicker more direct access to data The use of cache memory increases performance as time is saved by not having to access the relatively slower main memory circuits for data See also L1 cache and L2 cache unshielded twisted pair cable specification that functions at 10 Megabits per second on each pair unshielded twisted pair cable specification that functions at 100 Megabits per second on each pair a device that records the progress of the time and date
278. uble height 6U for two backplanes or combined backplane using P1 J1 and P2 J2 connectors The original VMEbus specification has been refined through several revisions A B C C 1 IEC 821 and IEEE 1014 1987 On April 10 1995 a new VME64 standard was approved for publication as ANSI VITA 1 1994 The VME64 standard was based on the VME Revision C 1 specification and adds several features including 64 bit address and data transfers However 64 bit addressing is not supported by the VSS4 board since the PowerPC processor has only a 32 bit address bus VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 58 Section 3 Basic Bus Descriptions VME64 bus The table below summarizes the VMEbus architecture and features supported by the VSS4 VSS4 VMEbus feature support Standard VMEbus VME64 add VME64 Extensions add 32 bit address bus 64 bit data transfer 160 pin P1 P2 wide P1 P2 address range Locked cycles User defined PO conn 16 bit Rescinding DTAck Slot geographical addressing 24 bit Autoslot ID Mate first break last 32 bit Auto Sys Controller detection precharge pins on P1 P2 for 64 bit hot swapping applications ETL bus transceivers 32 bit data bus EMI front panel data path width 8 bit 16 bit 24 bit 32 bit 64 bit 7 interrupt levels Master Slave architecture Functional modules Master
279. uide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix D PEX3 PMC expansion option Configuration Flash write protect Flash Write protect is the only configuration option for PEX3 After programming the Flash it can be protected from writes by installing a 100 jumper shunt on JGO2 Install this jumper as required for your application See drawing below Flash Write Ea Protect Jumper ON write protect E L 8 JE J 3 02 0141 PEX3 Flash write protect jumper JGO2 VSS4 User Guide 273 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 274 Appendix D PEX3 PMC expansion option Installation Installing PMC cards The PEX3 expansion option lets the VSS4 use up to 3 additional single width PMC cards Perform the following steps to install a PMC card onto a PEX3 expansion board Refer to the PMC Card PEX3 Expansion Board Installation drawing below for details we The PEX3 expansion board and its PMC yj cards are assembled as a sub unit prior to mating to the SBC This allows the PMC cards to be secured to the expansion board The PEX3 option converts the SBC into a double wide module Ensure that space is available in the c
280. umentation Guaranteed 888 88 SOURCE www artisantg com Section 4 Programming the PowerPC Onboard registers Board status register OxFFEF_FE18 RO Bit7 6 5 4 3 2 1 0 xixi x x Reset value Bit assignments Bit s Function Values b7 b4 Reserved b3 b2 PowerPC Bus Speed 0 66MHz 1 83MHz 2 100MHz 3 undefined b1 Board Ejector Handle Switches 0 Both eject handle switches are closed 1 one both eject handles switch es open b0 Fail LED 0 OFF 1 0N NOTE This bit valid only for boards with locking ejector handle option A read of this register shows the status of the board s FAIL LED ON or OFF and the PowerPC bus speed CPU status register OxFFEF_FE2O RO Bt7 6 5 4 3 2 1 0 Reset value Bit assignments Bit s Function Values b7 CPU W status 0 Halted 1 Running b6 CPU Z status 0 Halted 1 Running b5 CPU Y status 0 Halted 1 Running b4 CPU X status 0 Halted Running b3 b2 Number of CPUs 0 4 1 2 2 3 3 b1 b0 CPU ID 0 W Y 2 Z 3 W NOTE This is a processor dependent register All CPUs access the same address but the information in b1 b0 identifies which CPU is performing the read A read of this register returns the status of the CPU s on the board Information in this register includes the CPU ID of the processor doing t
281. urns zero on reads 31 0 EOI Code Address map end of interrupt registers Address Offset Register Access 0x2_00B0 End of interrupt register processor 0 RO 0x2_10B0 End of interrupt register processor 1 RO 0x2_20B0 End of interrupt register processor 2 RO 0x2_30B0 End of interrupt register processor 3 RO Note Add to base address set during PCI configuration 182 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 7 PCI VME64 Bridge Universe II This section provides general information about the Universe II PCI VME64 bridge interface Introduction to Universe Il Universe Il register reference mproving BLT performance Programming notes Universe II ge The bit numbering of registers in this zj section follows the zero on the right convention as opposed to the zero on the left bit numbering convention used by Motorola and IBM in their PowerPC documentation VSS4 User Guide 183 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 184 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 7 PCI VME64 Bridge Introduction to Universe Il Introduction to Universe I The Universe II PCI VME64 bridge chip from Tundra Semiconductor provides the VSS4 VMEbus interface Universe II s address translation provides VM
282. verse Int 1 b PMC Int B c PEX3 Int B 3 PCI Int A can be driven by any of the following a Universe Int 0 b PMC Int A c PEX3 Int A 4 PCI Int C can be driven by any of the following a Universe Int 2 b PMC Int C c PEX3 Int C d Serial Port C Interrupt Source Vector Priority registers The vector priority register bit assignments are described below 31 30 29 24 23 22 21 20 19 16115 8 7 0 MIA P S R R aA Reserved f gt Reserved 7 Priority Vector Expansion Vector Vector Interrupt Vector The vector value in this field is returned when the Interrupt Acknowledge register is examined and the interrupt associated with this vector is requested Priority Interrupt Priority This field sets the interrupt priority The lowest priority is O and the highest is 15 Setting the priority level to O disables interrupts S Sense This bit sets the sense for external interrupts Setting this bit to O enables edge sensitive interrupts Setting this bit to 1 enables level sensitive interrupts POL Polarity This bit sets the polarity for external interrupts Setting this bit to O enables active low or negative edge Setting this bit to 1 enables active high or positive edge For Synergy PowerPC series boards all A I O interrupt sources 0 15 are set up for Active Low polarity and Level Triggered sense 178 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 6 M
283. vice Write alternating 0 and 1 to this bit within 250 ms to prevent board reset This register has no effect if watchdog is disabled The watchdog is held off from resetting the board by periodic writes alternating between O and 1 to the watchdog pet register bO A 0 to 1 transition at least once every 250 milliseconds is required The code may twiddle this bit as often as it likes as long as this maximum time is not exceeded This periodic writing to the watchdog pet register is typically done in the main polling loop of the application program Should the program fail to write to the watchdog pet register the watchdog times out and the board system is reset Universe I software reset Sotware can initiate a board reset by setting bit 22 of the Universe II PCI VME64 bridge Miscellaneous Control register MISC_CTL If the board is the system controller the software reset will also reset the system Some OS board support packages from Synergy include a facility for software reset via the Universe II The VxWorks BSP for example includes the sysReset function Soft reset Each of the four CPUs may be independently reset by means of the Soft Reset feature The MPIC interrupt controller generates a signal called Init to each of the four CPUs The four signals InitO Init3 are wired to the SReset inputs of CPUs X Y Z and W respectively The SReset function in the CPU is edge triggered This means that when a CPU s
284. w shows the location and pin orientation of the VSS4 s PO PCI connector The table that follows lists the pin assignments of this connector P2 Component Side PO N ooOogoa ooo oOo Gd opoOoOoO oO oO oOo Gd ooo od oOo oo Gd NT Rear edge of SBC side view PO PCI bus connector PO 246 VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Appendix A Cables amp Connectors PO PCI bus connector PO PO PCI bus connector PO pinouts Pin Number A B C D E F 1 IntA AD44 IntB Gt IntC Rq IntD Ck Gnd 2 AD45 AD39 AD37 AD32 AD34 Gnd 3 AD47 AD46 AD42 AD33 AD36 Gnd 4 AD50 AD51 AD48 AD38 AD41 Gnd 5 AD52 AD54 AD53 AD35 AD40 Gnd 6 AD56 AD55 Vec5V AD43 Par64 Gnd 7 AD59 AD63 AD60 AD49 AD57 Gnd 8 AD61 CBE6 CBE4 AD58 AD62 Gnd 9 CBE5 AD1 ADO Req64 CBE7 Gnd 10 Ack64 AD2 AD6 AD5 AD4 Gnd 11 AD3 AD7 AD8 CBE0 AD9 Gnd 12 AD11 AD12 AD10 Par
285. watchdog timer is disabled by default at reset and must be enabled by software before it is usable Once the watchdog is enabled it cannot be disabled by software It can only be disabled by a board reset This protects the watchdog from being disabled by errant software Two write only registers are used to control the watchdog Watchdog enable register OxFFEF_FF40 W O Bit 7 6 5 4 3 2 1 0 xixix x x x x 0O Reset value Bit assignments Bit s Function Values b7 b1 Reserved b0 Watchdog Enable 0 Watchdog disabled No need to service watchdog 1 Watchdog enabled Periodic writes to Watchdog Pet register see next register description is required to prevent board reset The watchdog timer function is enabled by setting bO of this write only register to 1 Once watchdog is enabled the application code must VSS4 User Guide Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Section 5 Reset Reset information periodically write to the watchdog pet register see next to avoid reset An enabled watchdog can only be disabled by a board reset after which bO is automatically set to 0 Watchdog pet register OxFFEF_FF48 WO Bit 7 6 5 4 3 2 1 0 xixix x x x x 0O Reset value Bit assignments Bit s Function Values b7 b1 Reserved b0 Watchdog Ser
286. with the 64MHz clock While safer the extra sampling results in decreased performance User who believe their systems to have little noise on their DTAck lines can elect to filter this signal less and thus increase their Universe II response time VME Master Parameter t11 Control MASt11 bit 10 According to the VME64 Specification a VMEbus master must not drive DSO low until both it and DS1 have been simultaneously high for a minimum of 40ns The MASt11 parameter in the U2SPEC register however allows DSO to be driven low in less than 40ns VME Master Parameter t27 Control READt27 bits 8 amp 9 During read cycles the VMEbus master must guarantee that the data lines will be valid within 25ns after DTAck is asserted That is to say the master must not latch the data and terminate the cycle for a minimum of 25ns after the falling edge of DTAck The READt27 parameter in the U2SPEC register allows for faster cycle termination in one of two ways One setting allows for the data to be latched and the cycle terminated with an associated delay that is less than 25ns The other setting results in no delay whatsoever in latching and termination VME Slave Parameter t28 Control POSt28 bit 2 According to the VME64 Specification VMEbus slaves must wait at least 30ns after the assertion of DS before driving DTAck low The POSt28 parameter in the U2SPEC register however allows DTAck to be asserted in less than 30ns when
287. y Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 31 Section 6 MPIC Interrupt Controller MPIC registers Feature reporting register 27 26 16 15 13 12 8 7 0 Reserved Num IRQ Sources Reserved Num CPU Version ID 31 30 29 28 Version ID Version ID for this interrupt controller This value reports what level of the OpenPIC specification is supported by this implementation 1 Spec Revision 1 0 2 Spec Revision 1 2 Num CPU The number of the highest physical CPU supported For a 4 processor MPIC chip this value is 3 for a 2 processor MPIC chip this value is 1 for a 1 processor EPIC chip this value is 0 Num IRQ The number of the highest IRQ source supported For example in a system with 16 I O interrupt sources this value is 15 Global configuration registers 20 19 0 R M Reserved Base not used in PowerPC based systems Base Base Address Relocation field This field is not used in Power PC based systems M Cascade mode Set this bit to 1 to enable the MPIC This bit is provided to support an 8259 interrupt controller which is not used on the VSS4 When set to 0 reset default the MPIC passes interrupt input O directly through to CPU X which disables all other interrupt encoding and steering operations This effectively disables the MPIC When set to 1 the MPIC processes all interrupt inputs normally R Res
288. y first writing OxFFFF_FFFF to the register and reading it back it is possible to tell which bits are writable those that aren t won t change This tells the size of the bank and whether it is fixed in a particular space On the PowerPC Series SBC the allowed ranges for the PCI spaces are VSS4 User Guide 101 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 102 Section 4 Programming the PowerPC Programming notes MPC106 Memory base OxDFFF_O000 OxEFFF_FFFF I O base OxFEBO_0000 OxFEBF_FFFF You also need to enable the PCI device s response to PCI Memory space and or PCI I O space by setting the corresponding bits in the device s Command register typically bits 1 and O respectively The MPIC interrupt vector assigned to PCI Interrupt A is 13 and for B it is 12 Write posting to ROM Space Problem If you have a program that writes very frequently to that address region which the Grackle considers to be ROM space the Grackle services those writes at the expense of other requests for memory access that might happen at the same time The ROM space includes everything at high address range any address that is OxFFxx_xxxx This includes the ROMs that are meaningless to write to but it also includes all the CPU control registers the LEDs being among them So it is normal for the CPU to make writes to this region even though it s considered ROM s
289. y not be supported by other PowerPC processors The following paragraphs give a brief description of the PowerPC register set For more detailed register set information on a particular processor refer to that processor s user s manual General Purpose Registers GPRs 32 user level general purpose registers are defined in the PowerPC architecture These registers are either 32 or 64 bits wide in 32 and 64 bit wide PowerPC processors GPRs serve as the data source or destination for all integer instructions Floating Point Registers FPRs 32 user level 64 bit wide floating point registers are defined in the PowerPC architecture These registers serve as the data source or destination for floating point instructions FPRs can contain either single or double precision floating point data Condition Register CR The CR is a 32 bit user level register that is used to show the results of certain operations such as move integer and floating point compare and provide a mechanism for testing and branching Floating point Status and Control Register FPSCR The FPSCR provides compliance to the IEEE 754 standard by containing all exception signal bits exception summary bits exception enable bits and rounding control bits Machine State Register MSR The MSR is a supervisor level register that reflects the state of the processor The contents of this register are saved when an exception is taken and restored when t

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