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netX 50 to netX 51/52

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1. n Lu T 2 REESE m ple z Figure 7 Design Example netX 51 Core Memory netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 47 56 Lu LL VERE b 3 5 A ewes N 5 5 55 REN Se oo wa T Pe RR REE a nn IGUIIGODIDIITIIITI Lu Di Di Di Li Lu Lu Lu Lu Du t t t L i 3 food o 5 N ad L Zk 0 YY 17k I m bor i Ze Ge Zi E sz 2 E a o ze m Prze u Fa 24 E 5422 i 5008 52 1 PENE 4 4 ENE m y 36 3 TE
2. enne enne 47 Figure 9 Design Example netX 51 2 Port 00 48 Figure 10 Design Example netX 51 Power 7 49 Figure 11 Design Example netX 52 50 Figure 12 Design Example netX 52 51 Figure 13 Design Example netX 52 52 Figure 14 Design Example netX 52 Ethernet 53 Figure 15 Design Example netX 52 Power nennen nennen nnne neret nnne nennen 54 netX 50 to netX 51 52 Migration Guide DOC120 109MGOSEN Revision 5 English 2013 08 Released Public 2012 2013 Appendix 7 3 Contacts Headquarters Germany Hilscher Gesellschaft f r Systemautomation mbH Rheinstrasse 15 65795 Hattersheim Phone 49 0 6190 9907 0 Fax 49 0 6190 9907 50 E Mail info hilscher com Support Phone 49 0 6190 9907 99 E Mail de support hilscher com Subsidiaries China Hilscher Systemautomation Shanghai Co Ltd 200010 Shanghai Phone 86 0 21 6355 5161 E Mail info hilscher cn Support Phone 86 0 21 6355 5161 E Mail cn support hilscher com France Hilscher France S a r l 69500 Bron Phone 33 0 4 72 37 98 40 E Mail info hilscher fr Support Phone 33 0 4 72 37 98 40 E Mail fr su
3. TaN 1 x x x x Dec uc o a a coc gt 5 22 5 t i i cea ecco 2 1 SS E 2 2223 aceon SG GB I gt 000 6 Bee uno pee eee M la ul Figure 9 Design Example netX 51 2 Ethernet netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 49 56 Le 4 1 1 1 gt 8 1 4 11 t ef wH a H T 220012 Hil Hat I 1 EN H J Hilsch 4 G 1 Figure 10 Design Example 51 Power Supply netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 50 56 6 2 Design Example netX 52 NT AN Il I
4. sc Ser od B B FA s 5 T T 5 E 29 4 e 4 E I 4 i ad ZI N HE Li r 11 14 x Jx ES 5 d 2 ta ree 2 E EG q x 2 i i 90 gt So s 300 SR E i I rr a gt X Soe gt ES az ISS Ir EE x io en aad at 2 z ul Figure 14 Design Example netX 52 Ethernet Interface netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 54 56 4 4 5 5 No m 3 e 28 me E I 5 B 2 2 m 5 d B Gee p 4 E E Figure 15 Design Example netX 52 Power Supply netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Appendix 55 56 7 Ap
5. E 42 5 1 Fixed Erratas Of elX a Ren e ca eta a 42 5 2 New Errata for netX 51 43 5 2 1 SYS LED lights doesn t light correctly during active Boot 43 5 2 2 Simultaneous Operation of SDRAM and parallel Flash Memory at the Memory Interface 44 6 Design Examples Eee 45 6 1 Design Example netX 51 45 6 2 Design Example nelX 52 o iae tere Eug iode evn 50 7 l 22 2 4 4 55 Wali 4 ione eet tad bete 55 7223 UEISUODEIQUEOS n bac d ecc esau 55 Z o 56 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 3 56 1 Introduction 1 4 Migration from netX 50 to netX 51 52 This manual describes the differences between the netX 50 and netX 51 52 with the aim to support and lead you during the migration from netX 50 to netX 51 52
6. Note CLKOUT pin Note signals The MMIO can not be changed Symbol Description Input O Output Z Output is tristateable or open drain 5 Input provides Schmitt trigger U Internal pull up 50 I2C pins pull up 5k D Internal pull down 50 k 6 Output buffer can source sink 6 mA 9 Output buffer can source sink 9 mA XTAL Crystal input or output USB USB pad PHY PHY pad ANA Analog pin PWR 1 5 V Core or 3 3 V I O GND Digital Ground 0 V APWR Analog power 1 5V 3 3V AGND Analog ground 0 V Table 16 Pad Type Explanation netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 32 56 3 4 MMIO Signals Function Signal Type Functional Group nx50 nx51 52 XMO 100 5 In out FieldbusO X X XMO RX Input FieldbusO X XMO TX OE Non tristatable output FieldbusO X 5 XMO TX OUT Tristatable output FieldbusO X X XM1 1OO 5 In out Fieldbus1 X X XM1 RX Input Fieldbus1 X X XM1 TX OE Non tristatable output Fieldbus1 X XM1 TX OUT Tristatable output Fieldbus1 X X GPIOO 31 In out GPIO IO Link x X PHYO LEDO Always driven output INT PHYO X X PHYO LED1 Always driven output INT PHYO X X PHYO LED2 Always driven output INT PHYO X X LED3 Always driven output INT PH
7. hilschher COMPETENCE IN COMMUNICATION Migration Guide netX 50 to netX 51 52 Hilscher Gesellschaft f r Systemautomation mbH www hilscher com DOC 120109MGOSEN Revision 5 English 2013 08 Released Public Introduction 2 56 Table of Contents 1 ilo ect PESO 3 11 Migration from netX 50 to netX 51 52 U n n nene 3 1 22 LiStOf Revisions n 2 EE 5 1 3 Terms Abbreviations and 5 1 31 Signal Description oe moa i raodo BU nenne 6 1 4 Legal Note8 aurai ie etu er dedi diri tut nds 10 1 Gopytights oie DER REOR UNTRA UB rte UD Mte HERI 10 1 4 2 Important NOotes nnde E sa np e Dee Ee QUT ones 10 1 4 3 Exclusion of i iiec erige Ret De te events 11 1 4 4 M 11 2 Comparison netX 50 with netX 51 52 J J J J 12 21 Ew EIE 12 2 1 1 Block Diagrarmis iceberg er 12 2 1 2 ag EE 13 2 1 3 Enhancements of netX 51 52 against netX 50 14 3 Package Pinning Pad Cells u 15 SPEED CI uU ER E 15 3 1 1 52 I uu
8. 15 312 net 52 PINNING eter epe co ce Be nae tees 16 3 2 Alternative Function at Host 22 9 3 Memes 24 3 3 1 Differences in Pinning and Pad Cells a 24 34 MMIQ SignalS i eiit err er 32 4 General Cha AgNO s 2 eM Rr Ben 34 4 1 CPUS iets kasu Sh EEE s bears A 34 AAA C m B meis aL eU enis MUN MUN ie un oe 34 4 1 2 Additional GPW u nern Ran kreis 34 4 2 EIE 35 4 2 WAY o 0 PETE TE TE E E E A E 35 4 3 Peripheralgs tee e Het t ai irida iaa ai aaa 36 4 4 Improved Memory Access Performancoe L L nan 38 4 5 Activating 256 KByte as Dual Port Memory and Detection of netX 51 or netX 52 Mode 39 46 HostIntertace MOGes UL Lr reae teo enne Pee 40 4 7 Miscellaneous ee rette dte Saar i a er Te tret e Fee utu Tua anat buy 41 47 1 Operating Gonditions tette nba gee anal Q E Par e lame queda 41 4 7 2 Effects to existing Software omine ec goi dee een 41 4 7 3 Effects to existing Development Tools 1 41 5
9. i l 4 4 i M es j z 2 a 2 m m a oo mn a im N 8 a gt LL Figure 8 Design Example netX 51 Ethernet Diagport netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 48 56 ul I xag H 1 anro Hn 8 2 2 DR AX x 2 Sco EEE BUE 55 x X c Ic La ala Oo m m gg m m PROG poop POOH gggg gugggmguggr N 4 4 5 I 2 3 E ES 2 gt i m Edu i aa m 5 4 14 28 H 34 5 V B fl zum 0 EE
10. Price netX 50 netX 51 Mass Production ei IE Enhanced Functionality BGA 324 Pins 19x19mm M Pin compatible to net 50 Real Time Ethernet Fieldbus 10 netX 52 eae Without external Memory in high quantities BGA 244 Pins 15x15 mm external VPN netX 51 52 netX 52 None external Memory Bus netX 6 Without ARM CPU MI orks with any Host CPU Pin compatible to netx 52 Host Interface Functionality Performance Figure 1 Functionality and Price of netX 6 50 51 52 Within the netX network controller family the netX 50 support all Real Time Ethernet systems After a few years in the market it was necessary to upgrade the communication functionality to support PROFINET in the version 2 3 Together with some other enhancement we are offering the pin compatible controller netX 51 This can be placed on already existing netX 50 PCBs without modifications It also supports IO Link version 1 1 and includes much more RAM and an additional 32 Bit Risc Controller CAN controller and a MAC The same functionality is available as netX 52 without an external memory bus in a smaller package for a lower price The netX 6 with the same housing as the netX 52 is designed as network access controller This means it needs additional a host CPU to run the protocol stack It includes only the 32 Bit Risc controller and less memory to realize only the Real Tim
11. 12 0 501 In out 12 0 12C0_SDA In out 12C0 X X 12 1 SCL In out 12 1 12 1 SDA In out 12 1 x XC_SAMPLEO Input Trigger Latch Unit X X XC SAMPLE1 Input Trigger Latch Unit X X TRIGGERO Tristate able output Trigger Latch Unit X X TRIGGER1 Tristate able output Trigger Latch Unit X X UARTO 2 CTSN Input UART 0 2 X X UARTO 2 RTSN Tristate able output UART 0 2 X X UARTO 2 RXD Input UART 0 2 X X UARTO 2 TXD Tristate able output UART 0 2 X X USB ID DIG Input USB X USB ID PULLUP CTRL Non tristate able output USB X USB RPD ENA Non tristate able output USB X USB RPU ENA Non tristate able output USB X CCD DATAQ 7 Input CCD Sensor X CCD PIXCLK Input CCD Sensor X CCD LINE VALID Input CCD Sensor X CCD FRAME VALID Input CCD Sensor X CAN RX Input CAN 5 X CAN TX Always driven output CAN X MEM RDY Input MEM IF ready busy input X Table 17 Multiplex Matrix Signals The internal functions which can be mapped at the MMIO signals change as following The internal CCD Controller is not implemented anymore The internal MII signals for the internal PHYs can not be mapped anymore A second l2C controller is implemented special for accessing the fiber optic transceiver in PROFINET communication The additional USB signals are no more necessary because netX 50 has only s USB device and the USB pin becomes a function to pull the USB line high The signals of the dedicated CAN controller are also avai
12. contractual obligations are limited to damages that are foreseeable and typical for this type of contract It is strictly prohibited to use the software in the following areas for military purposes or in weapon systems for the design construction maintenance or operation of nuclear facilities in air traffic control systems air traffic or air traffic communication systems in life support systems in systems in which failures in the software could lead to personal injury or injuries leading to death We inform you that the software was not developed for use in dangerous environments requiring fail proof control mechanisms Use of the software in such an environment occurs at your own risk No liability is assumed for damages or losses due to unauthorized use 1 4 4 Export The delivered product including the technical data is subject to export or import laws as well as the associated regulations of different counters in particular those of Germany and the USA The software may not be exported to countries where this is prohibited by the United States Export Administration Act and its additional provisions You are obligated to comply with the regulations at your personal responsibility We wish to inform you that you may require permission from state authorities to export re export or import the product netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Comparison
13. 1 5V 3 3V IO Power VDDIO POWER Power Supply IO 3 3V C04 3 3V IO Power VDDIO POWER Power Supply IO 3 3V C14 3 3V IO Power VDDIO POWER Power Supply IO 3 3V D17 3 3V IO Power VDDIO POWER Power Supply IO 3 3V E01 3 3V IO Power VDDIO POWER Power Supply IO 3 3V E02 3 3V IO Power VDDIO POWER Power Supply IO 3 3V E16 3 3V IO Power VDDIO POWER Power Supply IO 3 3V K01 3 3V IO Power VDDIO POWER Power Supply IO 3 3V 102 3 3V IO Power VDDIO POWER Power Supply IO 3 3V 3 3V IO Power VDDIO POWER Power Supply IO 3 3V 3 3V IO Power VDDIO POWER Power Supply IO 3 3V netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 20 56 Pin Pad In Signal Group Description Out 9 3 3V IO Power VDDIO POWER Power Supply IO 3 3V U17 3 3V IO Power VDDIO POWER Power Supply IO 3 3V V04 3 3V IO Power VDDIO POWER Power Supply IO 3 3V 01 Ground VSS POWER Power Supply Ground 05 Ground VSS POWER Power Supply Ground C16 Ground VSS POWER Power Supply Ground 16 Ground VSS POWER Power Supply Ground G01 Ground VSS POWER Power Supply Ground 907 Ground VSS POWER Power Supply Ground 008 Ground VSS POWER Power Supply Ground G09 Ground VSS POWER Power Supply Ground G10 Grou
14. Analog Central Power Supply 3 3 V PHY_VSSAT PHY Analog Test Ground Supply PHY_VDDIOAT PHY Analog Test Power Supply 3 3 V Power VSS Ground Supply except PHY and Oscillator VDDC Power Supply Core 1 5 V except PHY and Oscillator VDDIO Power Supply IO Buffer 3 3 V except PHY and USB ETM ETM_TCLK ETM Trace clock ETM_TSYNC ETM Trace synchronization ETM_DRQ ETM Debug request ETM_DACK ETM Debug acknowledge ETM_PSTATO ETM Pipe status 0 ETM_PSTAT1 ETM Pipe status 1 ETM_PSTAT2 ETM Pipe status 2 0 1 ETM Trace packet 1 2 ETM Trace packet 2 ETM Trace packet 3 ETM_TPKT04 ETM Trace packet 4 5 ETM Trace packet 5 ETM Trace packet 6 ETM TPKTO7 ETM Trace packet 7 ETM 8 ETM Trace packet 8 9 ETM Trace packet 9 ETM_TPKT10 ETM Trace packet 10 ETM_TPKT11 ETM Trace packet 11 ETM_TPKT12 ETM Trace packet 12 ETM_TPKT13 ETM Trace packet 13 ETM_TPKT14 ETM Trace packet 14 ETM_TPKT15 ETM Trace packet 15 Table 4 Signal Description netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 10 56 14 Legal Notes 1 4 1 Copyright 2012 2013 Hilscher Gesellschaft fur Systemautomation mbH All rights reserved The images photographs and texts in the accompanying material user manual accompanying texts d
15. D18 DPM D11 IOU9 SPM CLK MMIO43 G18 C18 DPM D12 009 SPM_DIRQn MMIO44 G15 B18 DPM_D13 IOU9 SPM SIRQn MMIO45 D18 C17 DPM D14 IOU9 SPM SIO2 MMIO46 C18 B17 DPM D15 IOU9 SPM SIO3 MMIO47 J18 G17 DPM D16 IOU9 H17 F18 DPM D17 IOU9 netX 50 to netX 51 52 Migration Guide DOC120109MGOSEN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 29 56 Ball Pos Signal Pad Type MUX Func1 MUX Func2 netX netX netX netX netX 50 51 52 50 51 52 50 51 52 50 51 52 50 51 52 H18 E18 DPM D18 IOU9 G17 E17 DPM D19 WDGACT 009 B13 C12 DPM_D20 IOU9 A14 C11 DPM D21 IOU9 A13 A11 DPM D22 IOU9 C12 C10 DPM D23 IOU9 B10 A9 DPM D24 IOU9 A11 A8 DPM D25 IOU9 A9 A6 DPM D26 IOU9 C9 B7 DPM D27 IOU9 B6 A2 DPM D28 IOU9 4 DPM_D29 IOU9 A2 D3 DPM_D30 IOU9 J17 H17 DPM D31 IOU9 C17 D16 DPM INT DIRQn IOU9 B17 B15 DPM RDn IOU9 B18 C15 DPM RDY DPM BUSYn IOU9 MII_RXCLK C16 B14 DPM_WRn WRLn IOU9 B11 C8 TCLK DPM_SIRQn 009 Table 14 Differences Pinning Pad Cells Host Interface Note Only the name of these signals changed to be consistent with the configuration as active low signals on Hilscher boards The Host Interface becomes two additional functions for serial data transfer between netX and Host system These are a very fast SPI slave interface and a MII interface Both options are activated by
16. Port Memory Data 2 1009 IO DPM_D3 DPM Dual Port Memory Data 3 B04 1009 IO DPM_D4 DPM Dual Port Memory Data 4 B02 1009 IO DPM_D5 DPM Dual Port Memory Data 5 A05 1009 IO DPM_D6 DPM Dual Port Memory Data 6 B05 1009 IO DPM_D7 DPM Dual Port Memory Data 7 G18 1009 IO DPM_D8 DPM Dual Port Memory Data 8 G16 1009 IO DPM_D9 DPM Dual Port Memory Data 9 F17 1009 IO DPM_D10 DPM Dual Port Memory Data 10 018 1009 IO DPM_D11 DPM Dual Port Memory Data 11 C18 1009 IO DPM_D12 DPM Dual Port Memory Data 12 B18 1009 IO DPM_D13 DPM Dual Port Memory Data 13 C17 1009 IO DPM_D14 DPM Dual Port Memory Data 14 B17 1009 IO DPM_D15 DPM Dual Port Memory Data 15 917 1009 IO DPM_D16 DPM Dual Port Memory Data 16 F18 IOU9 IO DPM_D17 DPM Dual Port Memory Data 17 E18 1009 IO DPM_D18 DPM Dual Port Memory Data 18 E17 1009 IO DPM_D19 DPM Dual Port Memory Data 19 C12 1009 IO DPM_D20 DPM Dual Port Memory Data 20 C11 1009 IO DPM_D21 DPM Dual Port Memory Data 21 A11 1009 IO DPM_D22 DPM Dual Port Memory Data 22 C10 1009 IO DPM_D23 DPM Dual Port Memory Data 23 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 17 56 Pin Pad In Signal Group Description Out 09 1009 IO DPM_D24 DPM Dual Port Memory D
17. a ANA NLS UND 2 2 Nov Ne No NP CKD 275 J S Na 2 WN OO eO T VA INA 27 VN P Z 2 N 2 Figure 11 Design Example netX 52 Top View netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 51 56 ul 2 mmm 5 5 E 2 m A I I x 2 E od I m x x pc px px px x x x x x x px x px px px px x x x x r MH UL E GE A ul lt 5 i t DTE Sn z 24222220 0 u i 2 Hener 5 1 2 c 2c e nr T 5 2 E x d Ty e rea 5 i d ul Figure 12 Design Example netX 52 Host Interface netX 50 to net
18. because internal pull down resistors This allows reading in at start time a configuration value which is defined by external pull up resistors at the other memory signals Two additional lines are needed to run the SPI controller in Quad SPI mode Normally the memory signals MEM A18 and MEM A19 are not used by SDRAM An internal multiplex can be activated to change these address lines into the SIO2 and SIO3 signals for the Quad SPI mode and the MEM A18 and MEM 19 functionality moves to the highest address lines netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 3 3 1 4 SPI and QSPI Ball Pos Signal Pad Type MUX Func1 netX netX netX netX 50 51 52 50 51 52 50 51 52 50 51 52 V15 V16 SPIO CLK IOD6 QSPI CLK U14 U15 SPIO 50 IOD6 IOU6 QSPI_CSn 14 SPIO CS1n IOD6 IOU6 V16 U16 SPI0_MOSI IOD6 QSPI_SIOO U15 15 SPIO_MISO 1006 QSPI_SIO1 Pi2 14 MEM_A18 IOD6 QSPI SIO2 R13 V15 MEM A19 IOD6 5 5103 Table 12 Differences in Pinning and Pad Cells SPI 26 56 If a Quad SPI flash is used for fast start up at netX 50 the already published workaround via the communication controller is working also with netX 51 In addition the netx 51 includes a very fast Quad SPI controller which also support execution in place to run program code directly out of the Quad
19. few MMIO signals must be unconnected or tied at defined logic level Now the TEST pin becomes the BSCAN_TRST signal and Boundary Scan can activate with this signal only To be backward compatible the original TEST signal is moved to the former MEM_IF_OM pin which was a reserved signal for an optional System in Package design and was never used The BSCAN_TRST signal has the same level and function to switch on and off as the former TEST signal The netX 50 Technical Reference Manual said about MEM_IF_OM Connect to GND for normal operation This means for netX 51 52 the TEST signal is disabled If the former MEM_IF_OM is not connected to GND this works as well because this Pad is now changed from a internal pull up to an pull down Resistor netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 3 3 1 3 Memory Interface Ball Pos Signal Pad Type MUX Func1 netX netX netX netX 50 51 52 50 51 52 50 51 52 50 51 52 P12 T14 18 O6 IOD6 QSPI SIO2 R13 V15 MEM A19 O6 IOD6 QSPI 5103 J14 MEM A22 O6 IOD6 MEM A18 J15 MEM A23 O6 1006 MEM 19 All Memory Signals without MEMDR_CLK and O6 IOD6 MEM 0 32 Table 11 Differences in Pinning and Pad Cells Memory Interface 25 56 All Memory Signals without the SDRAM Clock and the Data lines can be used as inputs with a default value of zero
20. host interface mode only allow a certain Host Interface Configuration The usage depends on the selected boot source devices and the destination device from the bootable image An example is shown in section SP and QSPI on 26 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 General Changing 41 56 4 7 Miscellaneous 4 7 1 Operating Conditions netX 50 netX 51 netX 52 Operating temperature 40 70 C 40 70 C tod without heat sink Operating temperature 40 85 C 40 85 C tbd with heat sink 10 W Storage temperature 65 150 C 65 150 C 65 150 C Power consumption with 0 8 W PHYs disabled Power consumption with 1 3 W PHYs enabled Table 23 Operating Conditions 4 7 2 Effects to existing Software Due the netX 51 52 is not software compatible to the netX 50 different memory and register outlet please note new Security Memory content required new Software is required like Loadable Firmware Protocol Stacks Linkable Objects Operating Systems compilations 4 7 3 Effects to existing Development Tools Due the netX 51 52 has another netX version and is not software compatible to the netX 50 different memory and register outlet please note New Hitop PlugIn required New Lauterbach PlugIn required netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 En
21. netX 50 with netX 51 52 12 56 2 Comparison netX 50 with netX 51 52 2 1 Overview 2 1 1 Block Diagrams Block Diagram netX 50 10 Link RS232 485 Sensors 105 2x Fieldbus 2x Ethernet 40 Lines IO Matrix s xPEC xPEC 0 TCM D ARM 966 k a TCN I PHY 21 Bild Y Y Y 8x 32x GPIO Buffer IO Link 8x PIO E 4 96 SRAM 64 KR ROM EN E mI NI Controller 1 Y Ve cere Interface Multiplexer USB ser EPROM Memory Host Peripheral SRAM DPM xi Bit Figure 3 Block Diagram of netX 50 Block Diagram netX 51 52 IO Link RS232 485 Sensors IOs 2x Fieldbus or 2x Ethernet 40 Lines netX 51 24 Lines netX 52 IO Matrix t PHY EX PHY _ E ame 8x 2x xPEC 2x xPEC IO Link he A 2 672 KB SRAM DMA SDRAM Extension DPM SPM light Bus 8 16 32 Bit serial SPI Host Interface Multiplexer USB ser EPROM Memory Host Peripheral SRAM SDRAM Figure 4 Block Diagram of netX 51 52 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Comparison netX 50 with netX 51 52 13 56 2 1 2 Key Features The netX 51 and netX 52 is an enhancement of the existing netX 50 to fulfil the increasing demands of performance and functionality of industrial networks These controllers are supporting the PROFINET Specification 2 3 with the
22. new option of Dynamic Frame Packaging and the IO Link Version 1 1 with long telegrams We followed the successful strategy of the netX 10 controllers and implemented a second RISC CPU This can be programmed by the user to work parallel with the ARM CPU handling very fast IO signals without interfering the communication tasks Further more we increased the application interface with a dedicated CAN Controller and an Ethernet MAC Very often these communication lines were the reason to use the more expensive three channel controller netX 100 To increase the over all performance of the netX 51 52 and to allow real single chip solutions the internal memory is dramatically enlarged from 96 KByte to 672 KByte netX 50 51 52 CPU ARM 966 200 MHz ARM 966 100 MHz Secondary CPU xPIC 100 MHz SRAM ROM ITCM DTCM kByte 96 64 8 8 672 64 Separate External Memory Bus X X DPM parallel Data Width 8 16 32 DPM serial Host Interface PlOs 54 58 Host Interface usable as ExtMemBus SDRAM MAC sp Communication Channels Internal PHYs CAN Controller Ethernet MAC Eu X X IO Link Channels Version 8 V1 0 8 V1 0 V1 1 USB Host Device X X 1 UARTs 12C SPI QSPI 3 1 2 3 2 1 1 IEEE 1588 System Time lOs without Host Interface 32 40 24 Pins Packag
23. 09MGOSEN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 46 56 von Em 5 iaa aa eee Ep F b dade WS El 7 alt th om m m m gggg ppop gugg lt x HT E 8 5 m9 DG et Y bent 5 3 LO Uon d 2 1 1 1 1 5k 1 5 gt nn cnc 9 EE i fe D 1 u Y 11 6 Set e 2 t z 5 E 2 EXE A c 5 x E S 2 i c c 7 As S 5 3 E FEE pi 5 11121406 n m 5 5 ia HERE 2 TW n tn n 7 I EE HERR 2 1 2 2 Tes c I o er 2 E eL a ace 48 11 j 3 Le c a gt 2 th fw iren 4 4 3 I Lu E 1 x L z 1 Ss aa
24. 125 MBaud Integrated SDRAM Controller Table 20 Peripheral Comparison netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 General Changing 38 56 4 4 Improved Memory Access Performance Improvement The netX 50 has following disadvantages 966 has no Level 1 Cache included Tightly Coupled Memories 8K 8K Instruction Data are often too small for applications Only 96 KByte internal SRAM 64 KByte internal SRAM used for data exchange between xPEC and ARM966 32 KByte internal SRAM used as Dual Port Memory to exchange data between ARM966 and external Host One combined channel for data and instruction of ARM966 on SDRAM So the user application has to run non cached out of external memory which leads to a weak access performance see benchmark table below The netX 51 52 has following changes regarding to netX 50 Internal SRAM enlarged from 96 KByte to 672 KByte Tightly Coupled Memories removed and remaining two TCM Instruction Data channels connected to internal SRAM Two separated channels for data and instruction of ARM966 on SDRAM Advantage of the new ARM integration in netX 51 52 is that full internal SRAM can be reached by TCM channels Furthermore ARM can run accesses in parallel now Access can be performed on both TCM channels e g instruction fetch and data store and even ARM AHB channel e g peripheral access simultaneously Additionally so
25. CSn SDRAM Chip Select MEMDR WEn SDRAM Write Enable MEMDR RASn SDRAM RAS MEMDR CASn SDRAM CAS MEMDR CKE SDRAM Clock Enable MEMDR CLK SDRAM Clock MEM DQMO Memory Data Qualifier Mask DO 7 MEM 1 Memory Data Qualifier Mask D8 15 MEM DQM2 Memory Data Qualifier Mask D16 23 MEM DQMS Memory Data Qualifier Mask D24 31 MEM 0 31 Memory Data 0 31 MEM 0 23 Memory Address 0 23 Host Interface DPM_A00 15 Dual Port Memory Address 0 15 DPM BE1n Dual Port Memory Byte High Enable netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 8 56 DPM_BE3n Dual Port Memory Byte Enable 3 DPM_CSn Dual Port Memory Chip Select DPM 31 Dual Port Memory Data 0 31 DPM_DIRQn Dual Port Memory Data Interrupt DPM_SIRQn Dual Port Memory Sync Interrupt DPM_RDn Dual Port Memory Read DPM_WAITn Dual Port Memory Wait DPM_WRn Dual Port Memory Write SPM_MISO Serial Port Memory SPI Master Input Slave Output Data SPM_MOSI Serial Port Memory SPI Master Output Slave Input Data SPM_CSN Serial Port Memory SPI Chip Select SPM_CLK Serial Port Memory SPI Clock SPM_DIRQ Serial Port Memory Interrupt Source 1 SPM_SIRQ Serial Port Memory Interrupt Source 2 PHYO PHY1 PHYO_RXN PHY 0 Receive Input negative PHYO_RXP PHY 0 Receive Input positive PHYO_TXN PHY 0 Trans
26. ED are inverted This happens only if there is no firmware on the netX 51 board or during the boot phase till the firmware is started In new designs this can be compensated by connecting the Cathode of the SYS LED instead the Anode according the schematic below This LED interface is exactly the same as for the netX 10 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Erratas 44 56 5 2 2 Simultaneous Operation of SDRAM and parallel Flash Memory at the Memory Interface For the netX 51 the following maximum load capacity applies for operation of SDRAM at the Memory Interface Signal Maximum Load Capacity MEM_DO D31 15 pF All other signals 10 pF Important This means never connect parallel Flash memory to the Memory Interface when using SDRAM memory Operating one or more parallel flash memories given that at the same time no SDRAM memory is connected is possible at the Memory Interface even if the maximum load capacity is thereby exceeded The SDRAM controller in the netX must be deactivated when operating flash memory to avoid wrong address mapping causing data errors Note The limitations described above do not apply for the Host Interface It is possible to operate SDRAM memory and parallel Flash Memory at the Host Interface at the same time Maximum load capacity for SDRAM at th
27. IO 5 02 10056 IO MMIO6 MMIO Multiplex Matrix IO 6 01 10056 IO MMIO7 MMIO Multiplex Matrix IO 7 02 10056 IO MMIO8 MMIO Multiplex Matrix 10 8 P02 10056 IO MMIO9 MMIO Multiplex Matrix IO 9 R01 10056 IO MMIO10 MMIO Multiplex Matrix IO 10 1 10056 IO MMIO11 MMIO Multiplex Matrix IO 11 R02 10056 IO MMIO12 MMIO Multiplex Matrix IO 12 002 10056 IO MMIO13 MMIO Multiplex Matrix IO 13 02 10056 IO MMIO14 MMIO Multiplex Matrix IO 14 10056 IO MMIO15 MMIO Multiplex Matrix IO 15 T04 10056 IO MMIO16 MMIO Multiplex Matrix IO 16 01 10056 IO MMIO17 MMIO Multiplex Matrix IO 17 004 10056 IO MMIO18 MMIO Multiplex Matrix IO 18 003 10056 IO MMIO19 MMIO Multiplex Matrix IO 19 T05 IODS6 IO MMIO20 MMIO Multiplex Matrix IO 20 V03 10056 IO MMIO21 MMIO Multiplex Matrix IO 21 06 10056 IO MMIO22 MMIO Multiplex Matrix IO 22 005 10056 IO MMIO23 MMIO Multiplex Matrix IO 23 N16 ANA PHY_ATP PHY PHY Analog Test Point leave open N17 ANA PHY_EXTRES PHY PHY Reference Resistor 12 4K 1 16 APWR PHY_VDDCAP PHY PHY Power Supply Core 1 5V N18 APWR PHY_VDDIOAC PHY PHY Power Supply IO 3 3V T17 APWR PHY_VDDIOAT PHY PHY Power Supply IO 3 3V L16 AGND PHY_VSSACP PHY PHY Power Supply Ground M12 AGND PHY_VSSAT PHY PHY Power Supply Ground R17 PHY Receiver PHYO_RXN PHY PHY 0 Receive Input negative R18 PHY Receiver PHYO_RXP PHY PHY 0 Receive Input positive P17 PHY Transceiver PHYO TXN PHY PHY 0 Transmit Output negative P18 PHY T
28. IODS6 TXDO V2 V1 MMIO17 IODS6 ETM TCLK TXD1 V3 U4 MMIO18 IODS6 ETM_TSYNC TXD2 T6 U3 MMIO19 IODS6 ETM_DRQ MII TXD3 V6 T5 MMIO20 IODS6 ETM DACK MII TXEN U6 V3 MMIO21 IODS6 ETM_PSTATO MII TXER T7 T6 MMIO22 IODS6 PSTAT1 MII COL V7 U5 MMIO23 IODS6 ETM PSTAT2 U7 MMIO24 IODS6 ETM TPKTOO R8 MMIO25 IODS6 ETM_TPKT01 V9 MMIO26 IODS6 ETM 2 U9 z MMIO27 IODS6 ETM_TPKT03 T9 2 MMIO28 IODS6 ETM_TPKT04 U10 MMIO29 IODS6 ETM_TPKT05 T10 5 MMIO30 IODS6 ETM_TPKTO6 U11 MMIO31 IODS6 7 V12 MMIO32 IODS6 ETM TPKTO8 EN T11 gt MMIO33 IODS6 ETM_TPKT09 FO0_RD U12 MMIO34 IODS6 ETM_TPKT10 FO0_SD T12 MMIO35 IODS6 ETM_TPKT11 FO0_TD V13 5 MMIO36 IODS6 ETM_TPKT12 FO1_EN U13 MMIO37 IODS6 ETM_TPKT13 FO1_RD T13 5 MMIO38 IODS6 ETM_TPKT14 FO1_SD netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 31 56 Ball Pos Signal Pad Type MUX Func1 MUX Func2 MUX Func3 netX Netx netX netX netX netX 50 51 52 50 51 52 50 51 52 50 51 52 50 51 52 50 51 52 V14 MMIO39 IODS6 ETM_TPKT15 FO1_TD Table 15 Differences in Pinning and Pad Cells MMIO The MMIOs 40 47 are shared with Host interface pins The MMIO 48 is shared with In addition the MII interface of the third MAC controller can be multiplexed with the MII
29. Peripheral IO Table 8 Alternative Function at Host Interface netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 24 56 3 3 netX 51 3 3 1 Differences in Pinning and Pad Cells For some of the new features there are some additional external signals necessary This is done by sharing the pins with existing functions This new functions are disabled after power up or reset that the netX 51 has the same behaviour as the netX 50 To use these features these have to be enabled by software For some reason we had to change some few pad cells with small details which should not create any problems These enhancements and differences are documented in the following chapters 3 3 1 1 General Ball Pos Signal Pad Type MUX Func1 netX netX netX netX 50 51 52 50 51 52 50 51 52 50 51 52 D1 CLKOUT OZ6 IOD6 MMIO48 Table 9 Differences in Pinning and Pad Cells General The Clock Signal CLKOUT can now also be configured as additional MMIO Input 3 3 1 2 Test Ball Pos Signal Pad Type netX netX netX 50 51 52 50 51 52 50 51 52 G5 E3 TEST BSCAN_TRST ID IDS 12 B10 MEM_IF_OM TEST IUS ID Table 10 Differences in Pinning and Pad Cells Test For the netX 50 it was quite difficult to activate the Boundary Scan Test Function The TEST signal had to be activated and a
30. SPI flash This option can be used only if a new PCB is designed because the signal MEM_A18 is used as SPI_SIO2 and 19 as SPI_SIO3 E13 RI 2 RIB8 SPL SIO2 RS RIB SPI S 3102 3 5 5109 5103 14 nae SA MEMSA_WE F 0 T 2 x12 HE men Dana 0141081 CLK DD IO The schematic shows an example how to set up the configuration of the Host Interface by the strapping options and how to connect a Quad SPI flash netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 3 3 1 5 USB Ball Pos Signal Pad Type netX netX netX 50 51 52 50 51 52 50 51 52 V8 U6 USB_DNEG USB USB BPOS U8 6 USB_DPOS or USB ullu 3 3V pull up pu up resistor Table 13 Differences in Pinning and Pad Cells USB In USB device mode the netX 50 requires an external resistor to connect USB hosts 27 56 This resistor is activated either using a MMIO in software or via jumper during bootstrap situation With netX 51 52 this external resistor is not required anymore because it is included within the pad cell and switched automatically by the USB core Note Existing designs may work together with the external resistor if activation of the internal r
31. ST Reset Boundary Scan Controller TEST Activate Test Mode left open TMC1 Test Mode 1 left open TMC2 Test Mode 2 left open netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 7 56 TACT_TRST Reset Test Controller Memory Interface Output Mode Connect to GND for normal operating mode MMIO MMIOO 48 Multiplex Matrix IO 0 48 Fieldbus Interface XMO TX XMACO Transmit Data XMO External Clock input for XMO TX output from XMACO XMO TX ECLK XMACO Transmit Data clocked with external clock FBO CLK Clock output of fbO XM1 TX XMAC1 Transmit Data XM1_ECLK External Clock input for XM1 TX output from XMAC1 XM1_TX_ECLK XMAC1 Transmit Data clocked with external clock FB1_CLK Clock output of fo1_clk Ethernet MAC MII Interface MII_RXCLK Ethernet MAC Rx Clock MII_RXDO 3 Ethernet MAC Rx Data 0 3 MII_RXDV Ethernet MAC Rx Data Valid MII_RXER Ethernet MAC Rx Error MII_TXCLK Ethernet MAC Tx Clock TXDO 3 Ethernet MAC Tx Data O 3 MII TXEN Ethernet MAC Tx Enable MII TXER Ethernet MAC Tx Error MII COL Ethernet MAC Oollision CRS Ethernet MAC Carrier Sense Memory Interface MEMSR 50 2 SRAM Chip Select 0 2 MEMSR OEn SRAM Output Enable MEMSR WEn SRAM Write Enable MEMDR
32. Sensor X removed CORDIC 2 New module for fast coordinate transformation Memory Controller No differences New SRAM based device features Asynchronous Page Mode APM Optional ready wait signal for external wait state generation providing signal filtering an timeout logic Host Interface Following DPM Modes supported NTEL 8BIT SRAM NTEL 8BIT MULTIPLEXED NTEL 16BIT SRAM NTEL 16BIT BYTE WRITE NTEL 16BIT MUL NO BES NTEL 32BIT SRAM MOTOROLA 8BIT MULTIPLEXED MOTOROLA 16BIT MOTOROLA 16BIT 68000 Following netX 50 compatible DPM Modes NTEL 8BIT SRAM INTEL_8BIT_MULTIPLEXED NTEL 16BIT SRAM INTEL 16BIT BYTE WRITE INTEL 16BIT MUL BES INTEL 32BIT SRAM MOTOROLA 8BIT MULTIPLEXED MOTOROLA 16BIT MOTOROLA 16BIT 68000 Additionally supported DPM Modes INTEL 16BIT MUL BYTE WRITE NTEL 16BIT MUL 2BE INTEL 16BIT MUL BYTE ADDR INTEL 32BIT BYTE WRITE INTEL 2 MUL BYTE ADDR INTEL 2 MUL DWORD ADDR INTEL 2 MUL 4BE INTEL 32BIT MUL 4BE BYTE ADDR MOTOROLA 8BIT 6800 MOTOROLA 16BIT MUL BYTE ADDR MOTOROLA 16BIT MUL WORD ADDR MOTOROLA 32BIT MOTOROLA 32BIT MUL BYTE ADDR MOTOROLA 32BIT MUL DWORD ADD R TIOMAP 16BIT NON MULTIPLEXED TIOMAP 16BIT MULTIPLEXED SA 8BIT SA 16BIT Additionally supported serial DPM via SPI QSPI SPI modes 0 3 up to
33. X 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 52 56 5 u af e I s S Sc m gt Net EREE 4 i n un HHIH N c 1 gt 2 N ale a 8 A 0 x zs r 5 21 lo neo l m 8 1 ig 2l 5 E E E i Y 4 2 2 E i a E a D a oF 8 9 2 5 1 visio ASAS a 1 te 2 5 gt 3188 549 OHR e sec IST 4 Lu 5 In UIS m res E 4 f N RSA E ee zx S x 5 21 2 oe a a r ME fint H 4495949 f 2 2333 3 z 2343 25 a ad i od E Lo EE EME ETE 2 X XXX x nm Gere u EG E z aari 1 2240 aD i Y gt gt YE 2 Bere 55555 2222 2333 E H 222 O
34. YO X X PHY1 LEDO Always driven output INT PHY1 X X PHY1 LED1 Always driven output INT PHY1 X X PHY1 LED2 Always driven output INT PHY1 X X PHY1 LED3 Always driven output INT PHY1 X X MII MDC Always driven output MDIO X X MDIO In out MDIO X X MIIO COL Input MIIO X MIIO CRS Input MIIO X MIIO LEDO 3 Input MIIO X 5 MIIO_RXCLK Input MIIO X 1 MIIO_RXDO 3 Input MIIO X MIIO RXDV Input MIIO X RXER Input MIIO X MIIO_TXCLK Input MIIO X MII0_TXD0 3 Tristate able output MII0 X 1 MIIO_TXEN Tristate able output MIIO MIIO_TXER Tristate able output MIIO X MII1 COL Input X 1 MIl1_CRS Input X LEDO 3 Input X MIl1_RXCLK Input X E RXDO 3 Input X 5 Mil1_RXDV Input X Mil1_RXER Input X MII1 TXCLK Input X MII1_TXD0 3 Tristate able output X MIl1_TXEN Tristate able output x MIl1_TXER Tristate able output X netX 50 to netX 51 52 Migration Guide DOC120109MGOSEN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 33 56 Function Signal Type Functional Group nx50 nx51 52 PIOO 7 In out PIO SPIO_CS2N In out SPIO SPH In out SPI X X SPI1_CSON In out SPH X X SPI1_CS1N In out SPI1 X X SPI1_CS2N In out SPI X X SPI1_MISO In out SPI X X SPI1_MOSI In out SPI X X
35. a g HH J Ba ll X 2 Le M E 2 T 5 1 1 2 1 1 5 11 i 5 2 5 2 1 BE LS 22 E 2 22 2 1 1 5 hd Dodo 6 E vow S 1 B YE rc EHEER Figure 13 Design Example netX 52 CPU Core netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Design Examples 53 56 5 2 2 zZ x 5 5 x Jor ers i fa 1 B i Z g rb OE a E ale u u 3 d 4 1 4 FTT Fo Fo Fon i 1 1 S s 105 Se 1 or z gt N nm fx i zZ gt B e ek S Ale E NT V u 11 1 N er 51 at ul rc 5 4
36. and Pad Cells MMIO L 31 Pad Type Explanation emm eei ores ik eub etri gu rete Rl ede eden ena 31 z Multiplex Matrie Signals 5 1 2 tt oue De be tede tee tuit o tee urguet dire aes 33 v Gore GRU Comparison DEREN DM REDDAM mE 34 Memory LayoUtz Qu a u n un lr ted eene eroe tia A d ee depre er ce 35 s Peripheral te ee edocet Ce TU 37 Memory Access Performance Results 000 38 zHost Interface Modes me aa aa T ae 40 Operating Conditions 2 EE 41 RiXxed Erratas of nelX 50 nee Lee eee 42 List of Figures Figure 1 Functionality and Price of netX 6 50 51 52 3 Figure 2 Design Example with netX 51 00444 4 Figure 3 BlockeDIAQram Of NetX 502 engel 12 Figure 4 Block Diagram Of netX 5 1 52 4 7 a pe me TE a a N 12 Figure 5 Mechanical Dimensions of the netX 52 15 Figure 6 Design Example netX 51 COM Interfaces enne nennen nennen nnne 45 Figure 7 Design Example netX 51 Core Memory U 46 Figure 8 Design Example netX 51 Ethernet
37. ata 24 A08 IOU9 IO DPM_D25 DPM Dual Port Memory Data 25 A06 1009 IO DPM_D26 DPM Dual Port Memory Data 26 B07 1009 IO DPM_D27 DPM Dual Port Memory Data 27 A02 1009 IO DPM_D28 DPM Dual Port Memory Data 28 A04 1009 IO DPM_D29 DPM Dual Port Memory Data 29 D03 1009 IO DPM_D30 DPM Dual Port Memory Data 30 H17 1 009 IO DPM_D31 DPM Dual Port Memory Data 31 016 1009 IO DPM_DIRQn DPM Dual Port Memory Data Interrupt B15 1009 IO DPM_RDn DPM Dual Port Memory Read C15 1009 IO DPM_WAITn DPM Dual Port Memory Wait C08 1009 IO DPM_SIRQn DPM Dual Port Memory Sync Interrupt B16 1009 IO DPM_WRHn BE3n DPM Dual Port Memory Byte Enable 3 B14 1009 IO DPM_WRn WRLn DPM Dual Port Memory Write E03 IDS BSCAN_TRST GENERAL Reset Boundary Scan Controller 07 PLL power supply OSC_VDDC GENERAL Oscillator Power Supply Core 1 5V 007 PLL power supply OSC_VSS GENERAL Oscillator Power Supply Ground 008 Ocsillator pad OSC_XTI GENERAL 25 MHz Crystal Input V08 Ocsillator pad OSC_XTO GENERAL 25 MHz Crystal Output 01 108 PORn GENERAL Power on Reset F01 1006 IO RDYn GENERAL RDY LED Boot start option D01 OZ6 RSTOUTn GENERAL Reset Output 2 1006 IO RUNn GENERAL RUN LED Boot start option 902 IDS TACT_TRST GENERAL Reset Test Controller B10 ID TEST GENERAL Activate Test Mode left open Internal Test pin tmc1 TMC1 GENERAL Test Mode 1 left open Internal Test pin tmc2 2 GENERAL Test Mode 2
38. d Public 2012 2013 Package Pinning Pad Cells 16 56 3 1 2 netX 52 Pinning Pin Pad In Signal Group Description Out A03 1009 IO _ Dual Port Memory Address 0 1009 IO DPM_A1 BE2n DPM Dual Port Memory Address 1 12 1009 IO DPM_A10 DPM Dual Port Memory Address 10 A14 11009 IO DPM_A11 DPM Dual Port Memory Address 11 B13 1009 IO DPM_A12 DPM Dual Port Memory Address 12 A13 1009 IO DPM_A13 DPM Dual Port Memory Address 13 A12 1009 IO DPM_A14 DPM Dual Port Memory Address 14 1009 IO DPM_A15 DPM Dual Port Memory Address 15 A17 1009 IO DPM_A16 DPM Dual Port Memory Address 16 A18 1009 IO DPM_A17 DPM Dual Port Memory Address 17 C06 1009 IO DPM_A2 DPM Dual Port Memory Address 2 C07 1009 IO DPM_A3 DPM Dual Port Memory Address 3 Bos 1009 IO DPM_A4 DPM Dual Port Memory Address 4 A07 1009 IO DPM_A5 DPM Dual Port Memory Address 5 Bog 1009 IO DPM_A6 DPM Dual Port Memory Address 6 C09 1009 IO DPM_A7 DPM Dual Port Memory Address 7 C13 1009 IO DPM_A8 DPM Dual Port Memory Address 8 A10 1009 IO DPM_A9 DPM Dual Port Memory Address 9 A16 1009 IO DPM_BHEn BE1n DPM Dual Port Memory Byte Enable 1 A15 1009 IO DPM_CSn DPM Dual Port Memory Chip Select A01 1009 IO DPM_DO DPM Dual Port Memory Data 0 02 1009 IO DPM_D1 DPM Dual Port Memory Data 1 002 1009 IO DPM_D2 DPM Dual
39. ddress 0 B11 1009 IO SD_BA1 SD SDRAM Bank Address 1 A13 1009 IO SD_DQMOn SD SDRAM Data Qualifier 0 16 1009 IO SD_DQM1n SD SDRAM Data Qualifier 1 15 1009 IO SD_CSn SD SDRAM Chip Select A17 1009 IO SD_RASn SD SDRAM Row Address Select A18 1009 IO SD_CASn SD SDRAM Colum Address Select B14 1009 IO SD_WEn SD SDRAM Write 08 IOD9 IO SD_CLK SD SDRAM Clock C15 1009 IO SD_CKE SD SDRAM Clock Enable 016 1009 IO MII_RXDO MII MII Data Interrupt B18 1009 IO MII_RXD1 MII MII Data 13 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 23 56 Pin Pad In Signal Group Description Out C17 1009 IO MII_RXD2 MII MII Data 14 B17 1009 IO MII_RXD3 MII MII Data 15 B16 1009 IO MII_RXDV Mil MII Byte Enable 3 A02 1009 IO MII_RXCLK MII MII Receive Clock A04 1009 IO MII_RXER Mil MII Receive Error C11 1009 IO MII_TXDO MII MII Transmit Data 0 A11 IOU9 IO MII_TXD1 MII MII Transmit Data 1 C10 1009 IO MII_TXD2 MII MII Transmit Data 2 A09 1009 IO MII_TXD3 MII MII Transmit Data 3 A08 1009 IO MII_TXEN MII MII Transmit Enable F17 1009 IO MII_TXER MII MII Transmit Error C12 1009 IO MII_TXCLK MII MII Transmit Clock G18 009 IO MII_COL MII MII Transmit G16 1009 IO MII_CRS MII MII 018 1009 IO MII_MDIO MII MII Data 11 C18 1009 IO MII MDC MII MII Data 12 B15 1009 IO PIO52 PIO
40. e 324 PBGA 244 PBGA Grid size mm 1 0 mm 19x19 0 8 mm 15x15 Fieldbus RTE w o PN IRT with DFP and FTS X X Support PROFINET IRT with DFP Support Fast Track Switching FTS Table 5 Key Features netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Comparison netX 50 with netX 51 52 14 56 2 1 3 Enhancements of netX 51 52 against netX 50 Significant more internal memory available to accelerate tasks High performance access to INTRAM blocks via TCM channels of ARM CPU Reduced Power Consumption with higher Performance based on lower System Clock with ARM CPU high speed Memory Access via two TCM channels Improved ARM performance on SDRAM Performance of communication channel doubled to support high performance RTE systems as PROFINET IRT with Dynamic Frame Packing or Fast Track Switching xPIC as additional 100 MHz RISC CPU for time critical tasks Separate CAN Controller in addition to two communication channels Separate Ethernet MAC in addition to two communication channels Datalink layer done by xPIC New generation of Renesas internal PHYs for shortening cut through delays Dual Port Memory minimized access times can run without Wait Busy line Serial access to internal DPM via SPI QSPI Slave interface without interfering of ARM CPU Support IO Link V1 1 specification Dedicated Quad SPI Contro
41. e Host Interface is 30 pF netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 6 6 1 Design Examples 45 56 Design Examples Design Example netX 51 re i3 EN 1 5 6 iom L z RY p od ads IN Fad n c REI EE Xu it E 5 gape Bb EB or sx UE T emn 2 m m E gt ji EA 2 22 1 MM 4 rnb 3 25 B Figure 6 Design Example netX 51 COM Interfaces netX 50 to netX 51 52 Migration Guide DOC1201
42. e Switch functionality netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 4 56 With the netX 52 you can build up a very compact 30 x 30 mm 2 Port Real Time Ethernet Interfaces for a very low price With the loadable firmware the whole interface works a black box with a configurable 8 16 32 Bit Dual Port Memory or a SPI slave interface The following block diagram gives you an overview The detailed schematic you will find in the annex of this Migration Guide Host DPM mM gt Host SPI jodbus UART or I fm POWERLINK Synchronization 4 _ 20180 USB sercos the automation bus ED LINK ei Ethernet Channel 0 DI 25 MHz Zl LINK A go AGT Ethernet Channel 1 E gt GND 1 4 LT Figure 2 Design Example with netX 51 Component Description Manufacturer Price netX 52 Network Controller Hilscher 10 00 W25Q32VSSIG QSPI Flash Windbond 0 70 MAX811SEUS T Reset Generator Maxim 0 20 EN5312Q DC DC Converter 3 3 V 1 5 V Enpirion 1 20 25 MHz Crystal div 0 30 3x LED Dual Color div 0 30 Dual RJ45 with Magnetics LEDs div 2 80 Rs Cs Ls div 0 50 Material Cost per Int
43. erface in quantities of 10 000 pcs without PCB 16 00 Table 1 Material Costs netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 12 List of Revisions 5 56 Rev Date Name Chapter Revision 0 2012 02 01 AO All Created 1 2012 02 08 HJH All Reviewed 2 2012 04 25 HJH Added some additional explanation 3 2012 11 28 HH 1 3 1 Signal name for MIl interface starts with MII instead of ETH in Table 4 2 1 1 Figure 4 MAC to PHY mappable into Host Interface 3 1 2 Corrections 3 2 Section Alternative Function at Host Interface added 5 2 2 Section Simultaneous Operation of SDRAM and parallel Flash Memory at the Memory Interface added 4 2013 03 26 HH 2 1 1 Correction 1x 12 for netX 50 2 1 2 4 6 Section Host Interface Modes updated Table 22 revised 5 2013 08 26 HH 4 5 Correction 10 Kbyte to 10 Table 2 List of Revisions 1 3 Terms Abbreviations and Definitions Term Description DPM Dual Port Memory DFP Dynamic Frame Packing FTS Fast Track Switching HIF Host InterFace INTRAM INTernal SRAM PBGA Plastic Ball Grid Array XiP EXecution in Place xMAC Flexible Media Access Controller xPEC Flexible Protocol Execution Controller xPIC Flexible Peripheral Interface Controller Table 3 Terms Abbreviations and Definitions All variables pa
44. ernatively the Host Interface can be configured as a 16 Bit SDRAM Controller working in parallel with a MII Interface for a third Ethernet channel Pin Pad In Signal Group Description Out A01 1009 IO SD_D0 SD SDRAM Data 0 C02 09 IO SD D1 SD SDRAM Data 1 02 1009 IO SD_D2 SD SDRAM Data 2 1009 IO SD_D3 SD SDRAM Data 3 4 1009 IO SD_D4 SD SDRAM Data 4 B02 1009 IO SD_D5 SD SDRAM Data 5 A05 1009 IO SD_D6 SD SDRAM Data 6 B05 1009 IO SD_D7 SD SDRAM Data 7 G17 1009 IO SD_D8 SD SDRAM Data 8 F18 1009 IO SD_D9 SD SDRAM Data 9 E18 1009 IO SD_D10 SD SDRAM Data 10 17 1009 IO SD_D11 SD SDRAM Data 11 A06 1009 IO SD_D12 SD SDRAM Data 12 BO7 1009 IO SD_D13 SD SDRAM Data 13 1009 IO SD_D14 SD SDRAM Data 14 H17 1009 IO SD_D15 SD SDRAM Data 15 A03 1009 IO SD_A0 SD SDRAM Address 0 1009 IO SD A1 SD SDRAM Address 1 C06 09 IO 50 2 50 SDRAM Address 2 C07 09 IO SD_A3 SD SDRAM Address 3 08 1009 IO 50 4 50 SDRAM Address 4 A07 1009 IO SD_A5 SD SDRAM Address 5 9 1009 IO SD_A6 SD SDRAM Address 6 C09 09 IO SD_A7 SD SDRAM Address 7 C13 1009 IO SD_A8 SD SDRAM Address 8 A10 1009 IO SD_A9 SD SDRAM Address 9 B12 1009 IO SD_A10 SD SDRAM Address 10 14 1009 IO SD_A11 SD SDRAM Address 11 B13 1009 IO SD_A12 SD SDRAM Address 12 12 1009 IO SD_BA0 SD SDRAM Bank A
45. esistor by software is avoided New designs should omit external resistors netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 28 56 3 3 1 6 Host Interface Ball Pos Signal Pad Type MUX Func1 MUX Func2 netX netX netX netX netX 50 51 52 50 51 52 50 51 52 50 51 52 50 51 52 7 AO00 BEOn IOU9 MII TXER B8 B6 AO01 BE2n IOU9 MII COL C8 C6 DPM A02 1009 MII_CRS C10 C7 A03 IOU9 RXDO A10 B8 A04 IOU9 RXD1 B9 A7 A05 IOU9 RXD2 C11 B9 A06 IOU9 MII_RXD3 D11 C9 DPM A07 IOU9 RXDV C13 C13 A08 IOU9 TXDO B12 A10 A09 IOU9 TXD1 C14 B12 DPM A10 IOU9 TXD2 A17 A14 DPM A11 IOU9 TXD3 B15 B13 DPM A12 IOU9 MII TXEN A16 A13 DPM A13 IOU9 TXCLK B14 A12 DPM A14 IOU9 A15 B11 DPM A15 IOU9 E14 A17 VDDC DPM A16 PWR IOU9 D14 A18 VSS DPM A17 PWR IOU9 A18 A16 DPM BHEn BE1n IOU9 RXER C15 B16 DPM WRHn BES3n IOU9 B16 A15 DPM CSn IOU9 A1 A1 DPM DO IOU9 B2 C2 DPM D1 IOU9 C2 D2 DPM D2 IOU9 C6 B3 DPM D3 1009 A6 B4 DPM D4 IOU9 A3 B2 DPM D5 IOU9 A8 A5 DPM D6 IOU9 B7 B5 DPM D7 IOU9 J16 G18 DPM_D8 1009 SPM_MISO SIO1 MMIO40 H15 G16 DPM_D9 IOU9 SPM_MOSI SIOO MMIO41 H16 F17 DPM_D10 IOU9 SPM CSn MMIO42 G16
46. glish 2013 08 Released Public 2012 2013 Erratas 42 56 5 Erratas 5 1 Fixed Erratas of netX 50 netX 50 Errata Desciption Fixed in Number netX 51 52 1 DMA Controller Controller can not write to SDRAM Yes 2 SDRAM Access to offset OXDEADO DEADF fails after Power On Reset Yes 3 SPI Setting the clock divider to O and starting a transfer causes SPI core to hang Yes 4 SPI Legacy Register NCPHA Bit appears inverted when read Yes 5 I2C Signal timing can cause problems with some components Yes 6 Reset Control Register Register not protected by netX locking mechanism Yes 8 SPI Master Transmit FIFO may loose data in 16 bit mode Yes 9 UARTS Using Transmit FIFO may result in wrong transmit data Yes 10 Host interface Watchdog Output DPM D19 signal is driven low after Reset Yes 11 Host interface Error in configuration register regarding DPM ISA mode Yes 12 GPIO module Interrupts may be lost Yes 13 Internal PHYs Error in 10 Mbit half duplex mode Yes 14 Host Interface DPM access time with Hilscher standard DPM layout is unpredictable Yes Table 24 Fixed Erratas of netX 50 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Erratas 43 56 5 2 New Errata for netX 51 52 5 2 1 SYS LED lights doesn t light correctly during active Boot Loader Due a bug in the Boot Loader the signals for controlling the SYS L
47. ion 5 English 2013 08 Released Public 2012 2013 General Changing 40 56 4 6 Host Interface Modes The selection of the Host Interface Mode is a new feature of netX 51 52 compared to netX 50 These options are a simple way to configure the host interface if the Security Memory is not used The strapping options are selected with one two or three 1 5 KOhm pull up resistors on the pins SPIO_CLK SPIO_MOSI and SPIO_MISO The ROM code reads these signals and uses them to initialize the Host Interface during the boot process Description SPIO_MOSI SPIO_CLK SPIO_MISO netX boots from the connected Memory None Host Interface configuration 0 open 0 open 0 open SDRAM on Host Interface with 16 bit data bus and up to 4MByte 0 open 0 open 1 pull up address range SRAM on Host Interface with 16 bit data bus and 22 address lines 0 open 1 pull up 0 open on chip select 0 1 2 and3 SDRAM on Host Interface with 32 bit data bus and up to 4 MByte 1 pull up 0 open 1 pull up address range Host CPU supported Host CPU boots netX via Dual Port Memory Dual Port Memory with 8 bit data bus and 11 address lines 1 pull up 0 open 0 open Serial access over SPM lines 0 open 1 pull up 1 pull up Dual Port Memory with 8 bit data bus and 16 address lines 1 pull up 1 pull up 1 pull up Reserved Reserved 1 pull up 1 pull up 0 open Table 22 Host Interface Modes The
48. lable at the MMIO pins netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 General Changing 34 56 4 General Changing 4 1 CPUs 4 1 1 Core CPU Feature netX 50 netX 51 52 Core ARM 966 ARM 966 Speed 200MHz 100 MHz I TCM 8 kB Internal SRAMs via TCM interface accessible without wait states D TCM 8 kB Internal SRAMs via TCM interface accessible without wait states Code execution Internal SRAM if not used by XC Internal SRAM channels or external host External memories via extension External memories via extension bus SDRAM interface bus SDRAM interface Serial flash via QSPI Execution in Place Table 18 Core CPU Comparison 4 1 2 Additional CPU xPIC The netX 51 has an additional CPU called xPIC This CPU runs with a frequency of 100 MHz and is designed to process fast IO signals in parallel to the ARM CPU with a latency time of down till five clock cycles The xPIC is also used for the IO Link controller and the additional third Ethernet MAC channel In this cases the xPIC not available user applications netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 General Changing 35 56 4 2 Memory 4 2 1 Layout Memory netX 50 Start Address netX 51 52 Start Address Assig
49. left open H18 104059 5K pull up IO 120 5601 12 2 Serial Clock Line H16 IOZUS9 5K pull up IO 12C_SDA 12 2 Serial Data Line 01 1105 JT_TCLK JTAG JTAG Test Clock 403 IUS JT_TDI JTAG JTAG Test Data Input OZ6 JT_TDO JTAG JTAG Test Data Output 105 JT_TMS JTAG JTAG Test Mode Select HOS IDS JT_TRSTn JTAG JTAG Test Reset T13 1 n C Reserved T10 1 5V Core Power VDDC POWER Power Supply Core 1 5V T12 1 5V Core Power VDDC POWER Power Supply Core 1 5V T11 3 3V IO Power VDDIO POWER Power Supply IO 3 3V U14 3 3V IO Power VDDIO POWER Power Supply IO 3 3V U10 n C Reserved V10 n C 2 Reserved U12 n C Reserved 12 n C Reserved U11 n C Reserved V11 n C i Reserved U13 l n C Reserved netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 18 56 Pin Pad In Signal Group Description Out V13 l n c Reserved 02 10056 IO MMIOO MMIO Multiplex Matrix IO 0 K02 10056 IO MMIO1 MMIO Multiplex Matrix IO 1 402 10056 IO MMIO2 MMIO Multiplex Matrix IO 2 103 10056 IO MMIO3 MMIO Multiplex Matrix IO 3 LO1 10056 IO MMIO4 MMIO Multiplex Matrix 10 4 M01 10056 IO MMIO5 MMIO Multiplex Matrix
50. ller instead using internal communication controller for fast loading of program code Support of XiP Execution in Place Execution of program code directly out of serial flash netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 3 Package Pinning Pad Cells 15 56 The netX 51 comes in a 324 pin PBGA package and has the same pinning and size as the netX 50 has It is designed to replace the netX 50 without changing the PCB drop in replacement The netX 52 comes in a smaller 244 pin PBGA package with 0 8mm grid 31 netX 52 3 1 1 netX 52 Package Index Mark Al RE Se A s o Le 00 s D H eee i eee F eee F eee eee E ipa 1 H 1 L eee L eee eee m N LE E E eee N eee i eee T u 1 u x eee i D A2 Figure 5 Mechanical Dimensions of the netX 52 Symbol Min Type Max Al 0 29 mm 0 35 mm 0 41 mm A2 1 11 mm b 0 40 mm 0 50 mm 0 55 mm E 14 90 mm 15 00 mm 15 10 mm 0 80 mm 14 90 mm 15 00 mm 15 10 mm Table 6 Mechanical Dimensions of the netX 52 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Release
51. me ARM TCM features e g data buffering lead to better performance than using standard AHB interface That leads to an increased total ARM performance even when operating frequency is decreased to 100MHz Decreased operating frequency leads to less power consumption On SDRAM the ARM performance benefits from separated channels for data and instructions Benchmark CoreMark an open source benchmark program for embedded processors was used to visualize the improvements Instruction code and data are located in different memory regions The call stack is located within internal RAM The data area is static no heap is used The following table shows the CoreMark Processing times smaller values are better in clock cycles of 10ns under ARM Compiler Optimization 2 Instruction Data Memory netX 50 200 MHz ARM966 netX 51 52 100 MHz ARM 966 INTRAM INTRAM 152 233 96 590 ITCM DTCM 61 541 SDRAM 32 bit 454 253 392 966 XiP Execution in Place QSPI Clock 1 240 979 80 MHz Table 21 Memory Access Performance Results netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 General Changing 39 56 4 5 Activating 256 KByte as Dual Port Memory and Detection of netX 51 or netX 52 Mode A chip can be roughly divided into 2 components the integrated circuit die this is the little silicon piece and the surrounding package The package incl
52. mirror start addresses For example to access INTRAM via I TCM interface the start address is 0x00020000 and via D TCM interface is 0x04020000 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 General Changing 4 3 Peripherals 36 56 Peripheral netX 50 netX 51 52 VIC Interrupt table changed DMAC 4 channels no SDRAM access channels SDRAM access supported GPIO O Link function moved to separate module systime compare function doubled and moved to new ARM Timer xPIC Timer modules PIO No differences MMIO 40 MMIOs MMIOO 39 netX 51 40 MMIOs MMIOO 39 148 functional signals mappable netX 52 24 MMIOs MMIOO 23 No PIO functionality Additional MMIO40 47 multiplexed with DPM pins Additional MMIO48 multiplexed with CLKOUT 98 functional signals mappable s chapter 2 6 Each unused usable as PIO Pointer FIFO 32 FIFOs 32 FIFOs 1024 Entries overall 3200 Entries overall Default depth per FIFO 32 Default depth per FIFO 100 ARM Timer New module with 2 ARM dedicated 32 bit timers systime read and compare IRQ support Systime IEEE1588 No differences New netX 51 includes 2nd independent systime unit systime_uc FMMU SyncManager BufferManager No differences 8 FMMUs 8 SyncMan 8 BufMan Trigger Sample Unit No differences Ne
53. mit Output negative PHY 0 Transmit Output positive FOO_RD Fiberoptic Ethernet channel 0 Receive Data FOO_TD Fiberoptic Ethernet channel 0 Transmit Data FOO_EN Fiberoptic Ethernet channel 0 Enable FOO_SD Fiberoptic Ethernet channel 0 Signal Detect PHYO 55 1 PHYO_VSSAT2 PHY 0 Analog Ground Supply PHY 0 Analog Ground Supply PHYO_VSSAR PHY 0 Analog Ground Supply PHYO_VDDCART PHY 0 Analog TX RX Power Supply 1 5 V PHY1 RXN PHY 1 Receive Input negative PHY1 RXP PHY 1 Receive Input positive PHY1 TXN PHY 1 Transmit Output negative PHY1 TXP PHY 1 Transmit Output positive FO1 RD Fiberoptic Ethernet channel 1 Receive Data FO1 TD Fiberoptic Ethernet channel 1 Transmit Data FO1 EN Fiberoptic Ethernet channel 1 Enable FO1 SD Fiberoptic Ethernet channel 1 Signal Detect PHY1_VSSAT1 PHY 1 Analog Ground Supply PHY1_VSSAT2 PHY 1 Analog Ground Supply PHY1_VSSAR PHY 1 Analog Ground Supply PHY1_VDDCART PHY 1 Analog TX RX Power Supply 1 5 V PHY_EXTRES Reference Resistor 12 4 k 1 Leave open PHY_VSSACP PHY Analog Central Ground Supply PHY_VDDCAP PHY Analog Central Power Supply 1 5 V netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 9 56 PHY_VDDIOAC PHY
54. nd VSS POWER Power Supply Ground G11 Ground VSS POWER Power Supply Ground G12 Ground VSS POWER Power Supply Ground H07 Ground VSS POWER Power Supply Ground 8 Ground VSS POWER Power Supply Ground 09 Ground VSS POWER Power Supply Ground H10 Ground VSS POWER Power Supply Ground H11 Ground VSS POWER Power Supply Ground H12 Ground VSS POWER Power Supply Ground J01 Ground VSS POWER Power Supply Ground J07 Ground VSS POWER Power Supply Ground J08 Ground VSS POWER Power Supply Ground 409 Ground VSS POWER Power Supply Ground J10 Ground VSS POWER Power Supply Ground J11 Ground VSS POWER Power Supply Ground J12 Ground VSS POWER Power Supply Ground J16 Ground VSS POWER Power Supply Ground K07 Ground VSS POWER Power Supply Ground K08 Ground VSS POWER Power Supply Ground K09 Ground VSS POWER Power Supply Ground K10 Ground VSS POWER Power Supply Ground K11 Ground VSS POWER Power Supply Ground K12 Ground VSS POWER Power Supply Ground LO7 Ground VSS POWER Power Supply Ground 108 Ground VSS POWER Power Supply Ground 109 Ground VSS POWER Power Supply Ground 07 Ground VSS POWER Power Supply Ground 08 Ground VSS POWER Power Supply Ground 09 Ground VSS POWER Power Supply Ground M10 Ground VSS POWER Power Supply Ground M11 Ground VSS POWER Power Supply Ground NO3 Ground VSS POWER Power Supply Ground 01 Ground VSS POWER Power Supply Ground T18 Ground VSS POWER Power Supply Ground 001 G
55. ned to Assigned to INTRAMO 32 KByte XCO 0x08000000 128 KByte ARM 0x08000000 INTRAM1 32 KByte XC1 0x08008000 128 KByte ARM 0x08020000 INTRAM2 32 KByte DPM 0x08010000 64 KByte ARM 0x08040000 INTRAM3 64 KByte ARM 0x08050000 INTRAM4 64 KByte ARM 0x08060000 INTRAM5 32 KByte xPIC Instr 0x08070000 INTRAM6 32 KByte xPIC Data 0x08078000 INTRAM7 64 KByte XCO 0x08080000 INTRAM8 64 KByte XC1 0x08090000 INTRAMHS 32 KByte DPM 0x080a0000 HIF_SDRAM 256 MByte ARM xPIC 0x40000000 HIF_EXTSRAMO 64 MByte ARM xPIC 0x60000000 HIF_EXTSRAM1 64 MByte ARM xPIC 0x64000000 HIF_EXTSRAM2 64 MByte ARM xPIC 0x68000000 HIF_EXTSRAM3 64 MByte ARM xPIC 0x6c000000 SDRAM 256 MByte ARM 0x80000000 256 MByte ARM xPIC 0x80000000 EXTSRAMO 64 MByte ARM 0xc0000000 64 MByte ARM xPIC 0xc0000000 EXTSRAM1 64 MByte ARM 0 8000000 64 MByte ARM xPIC 0xc4000000 EXTSRAM2 64 MByte ARM 0xd0000000 64 MByte ARM xPIC 0xc8000000 BOOT ROM 64 KByte Bootloader 0 08200000 64 KByte Bootloader 0x080f0000 QSPI ROM XiP 16 MByte ARM xPIC 0x0c000000 Table 19 Memory Layout netX 51 All INTRAM block start addresses shown are addresses via standard ARM966 system interface segment address 0x08000000 All INTRAM blocks are also accessible via TCM segment address 0x00000000 and D TCM segment address 0x04000000 interface of ARM966 core To realize that all INTRAM blocks have
56. ocumentation etc are protected by German and international copyright law as well as international trade and protection provisions You are not authorized to duplicate these in whole or in part using technical or mechanical methods printing photocopying or other methods to manipulate or transfer using electronic systems without prior written consent You are not permitted to make changes to copyright notices markings trademarks or ownership declarations The included diagrams do not take the patent situation into account The company names and product descriptions included in this document may be trademarks or brands of the respective owners and may be trademarked or patented Any form of further use requires the explicit consent of the respective rights owner 1 4 2 Important Notes The user manual accompanying texts and the documentation were created for the use of the products by qualified experts however errors cannot be ruled out For this reason no guarantee can be made and neither juristic responsibility for erroneous information nor any liability can be assumed Descriptions accompanying texts and documentation included in the user manual do not present a guarantee nor any information about proper use as stipulated in the contract or a warranted feature It cannot be ruled out that the user manual the accompanying texts and the documentation do not correspond exactly to the described features standards or other data of the delivered
57. ower Supply Core 1 5V F12 1 5V Core Power VDDC POWER Power Supply Core 1 5V F13 1 5V Core Power VDDC POWER Power Supply Core 1 5V 906 1 5V Core Power VDDC POWER Power Supply Core 1 5V G13 1 5 Core Power VDDC POWER Power Supply Core 1 5V H06 1 5V Core Power VDDC POWER Power Supply Core 1 5V H13 1 5V Core Power VDDC POWER Power Supply Core 1 5V 406 1 5 Core Power VDDC POWER Power Supply Core 1 5V 413 1 5V Core Power VDDC POWER Power Supply Core 1 5V J17 1 5V Core Power VDDC POWER Power Supply Core 1 5V 418 1 5V Core Power VDDC POWER Power Supply Core 1 5V K06 1 5V Core Power VDDC POWER Power Supply Core 1 5V K13 1 5V Core Power VDDC POWER Power Supply Core 1 5V LO6 1 5V Core Power VDDC POWER Power Supply Core 1 5V L13 1 5V Core Power VDDC POWER Power Supply Core 1 5V 06 1 5V Core Power VDDC POWER Power Supply Core 1 5V M13 1 5V Core Power VDDC POWER Power Supply Core 1 5V No6 1 5V Core Power VDDC POWER Power Supply Core 1 5V NO7 1 5V Core Power VDDC POWER Power Supply Core 1 5V No8 1 5V Core Power VDDC POWER Power Supply Core 1 5V 9 1 5V Core Power VDDC POWER Power Supply Core 1 5V N10 1 5V Core Power VDDC POWER Power Supply Core 1 5V N11 1 5V Core Power VDDC POWER Power Supply Core 1 5V N12 1 5V Core Power VDDC POWER Power Supply Core 1 5V N13 1 5V Core Power VDDC POWER Power Supply Core 1 5V R16 1 5V Core Power VDDC POWER Power Supply Core 1 5V T16 1 5V Core Power VDDC POWER Power Supply Core
58. pendix 7 1 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 7 2 List of Tables Material 515 5 ates an en ed en eed 4 List Of REVISIONS D ERN 5 Terms Abbreviations and Definitions cccccccccccsssssecececeeeeseececeeeceeenseceeceeeeaeasseceecessaaaeaseeeeeeeeeeeaaseceeeeseasaasaeees 5 Signal Description ORI ERREUR UR a RU 9 ed ss De eee 13 Mechanical Dimensions of the netX 52 15 netX 52 PInniINg E MM 21 Alternative Function at Host lnterface ck eaves re en Bann Damme nn 23 Differences in Pinning and Pad Cells General u 24 Differences in Pinning and Pad Cells Test u 24 Differences in Pinning and Pad Cells Memory 25 Differences in Pinning and Pad Cells SPI enne enne nnne nmn nnne nnns nnns 26 Differences in Pinning and Pad Cells 06 2 0 27 Differences in Pinning and Pad Cells Host 29 Differences in Pinning
59. pport hilscher com India Hilscher India Pvt Ltd New Delhi 110 065 Phone 91 11 26915430 E Mail info hilscher in Italy Hilscher Italia S r l 20090 Vimodrone MI Phone 39 02 25007068 E Mail info hilscher it Support Phone 39 02 25007068 E Mail it support hilscher com netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 56 56 Japan Hilscher Japan KK Tokyo 160 0022 Phone 81 0 3 5362 0521 E Mail info hilscher jp Support Phone 81 0 3 5362 0521 E Mail jp support hilscher com Korea Hilscher Korea Inc Seongnam Gyeonggi 463 400 Phone 82 0 31 789 3715 E Mail info hilscher kr Switzerland Hilscher Swiss GmbH 4500 Solothurn Phone 41 0 32 623 6633 E Mail info hilscher ch Support Phone 49 0 6190 9907 99 E Mail ch support hilscher com USA Hilscher North America Inc Lisle IL 60532 Phone 1 630 505 5301 E Mail info hilscher us Support Phone 1 630 505 5301 E Mail us support hilscher com 2012 2013
60. product No warranty or guarantee regarding the correctness or accuracy of the information is assumed We reserve the right to change our products and their specification as well as related user manuals accompanying texts and documentation at all times and without advance notice without obligation to report the change Changes will be included in future manuals and do not constitute any obligations There is no entitlement to revisions of delivered documents The manual delivered with the product applies Hilscher Gesellschaft fur Systemautomation mbH is not liable under any circumstances for direct indirect incidental or follow on damage or loss of earnings resulting from the use of the information contained in this publication netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 11 56 1 4 3 Exclusion of Liability The software was produced and tested with utmost care by Hilscher Gesellschaft fur Systemautomation mbH and is made available as is No warranty can be assumed for the performance and flawlessness of the software for all usage conditions and cases and for the results produced when utilized by the user Liability for any damages that may result from the use of the hardware or software or related documents is limited to cases of intent or grossly negligent violation of significant contractual obligations Indemnity claims for the violation of significant
61. rameters and data used in this manual have the LSB MSB Intel data format This corresponds to the convention of the Microsoft C Compiler All IP addresses in this document have host byte order netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Introduction 6 56 1 3 1 netX Signal Description General PORn Power on Reset RSTINn Reset Input RSTOUTn Reset Output RDYn RDY LED Boot option RUNn RUN LED Boot option CLKOUT Clock out WDGACT Watchdog active Oscillator OSC_XTI 25 MHz Crystal Input OSC_XTO 25 MHz Crystal Output OSC_VSS Oscillator Power Supply Ground OSC_VDDC Oscillator Power Supply Core 1 5V JTAG JT_TRSTn JTAG Test Reset JT_TMS JTAG Test Mode Select JT_TCLK JTAG Test Clock JT_TDI JTAG Test Data Input JT_TDO JTAG Test Data Output SPI SPIO_CLK SPI 0 Clock SPIO CSOn SPI 0 Chip Select 0 SPIO CS1n SPI 0 Chip Select 1 5 10 MISO SPI 0 Master Input Slave Output Data SPIO MOSI SPI 0 Master Output Slave Input Data QSPI CLK XiP QSPI Clock QSPI CSn XiP QSPI Chip Select QSPI SIOO 3 XiP QSPI Serial IO Data 0 3 12 12 501 12 Serial Clock Line 2 SDA 12 Serial Data Line USB USB DNEG USB D Line USB DPOS USB D Line USB VDDC USB Power Supply Core 1 5 V USB VDDIO USB Power Supply IO 3 3 V Test BSCAN TR
62. ransceiver _ PHY 0 Transmit Output positive U18 APWR PHYO_VDDCART PHY PHY 0 Power Supply Core 1 5V P16 AGND PHYO_VSSAR PHY PHY 0 Power Supply Ground L10 AGND 0 55 1 PHY PHY 0 Power Supply Ground 111 AGND PHYO_VSSAT2 PHY PHY 0 Power Supply Ground K17 PHY Receiver PHY1_RXN PHY PHY 0 Receive Input positive K18 PHY Receiver PHY1_RXP PHY PHY 0 Receive Input negative L17 PHY Transceiver PHY1_TXN PHY PHY 1 Transmit Output positive L18 PHY Transceiver 1_ PHY 1 Transmit Output negative K16 APWR PHY1_VDDCART PHY PHY 1 Power Supply Core 1 5V netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 19 56 Pad In Signal Group Description Out L12 AGND PHY1_VSSAR PHY PHY 1 Power Supply Ground M18 AGND PHY1_VSSAT1 PHY PHY 1 Power Supply Ground M17 AGND PHY1_VSSAT2 PHY PHY 1 Power Supply Ground FO6 1 5V Core Power VDDC POWER Power Supply Core 1 5V FO7 1 5V Core Power VDDC POWER Power Supply Core 1 5V FO8 1 5V Core Power VDDC POWER Power Supply Core 1 5V F09 1 5V Core Power VDDC POWER Power Supply Core 1 5V F10 1 5V Core Power VDDC POWER Power Supply Core 1 5V F11 1 5V Core Power VDDC POWER P
63. round VSS POWER Power Supply Ground netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 21 56 Pin Pad In Signal Group Description Out 009 Ground VSS POWER Power Supply Ground 02 Ground VSS POWER Power Supply Ground V05 Ground VSS POWER Power Supply Ground V09 Ground VSS POWER Power Supply Ground V14 Ground VSS POWER Power Supply Ground V17 Ground VSS POWER Power Supply Ground V18 Ground VSS POWER Power Supply Ground V16 IOD6 IO SPIO_CLK SPI SPI Clock QSPI_CLK QSPI Clock U15 1006 IO SPIO_CSOn SPI SPI Chip Select 0 QSPI_CSn QSPI Chip Select T15 IOD6 IO SPIO_MISO SPI SPI Master Input Slave Output Data QSPI SIO1 QSPI Serial IO Data 1 U16 1006 IO SPIO_MOSI SPI SPI Master Output Slave Input Data QSPI_SIOO QSPI Serial IO Data 0 T14 1006 QSPI SIO2 SPI QSPI Serial IO Data 2 V15 1006 QSPI_SIO3 SPI QSPI Serial IO Data 3 006 USB IO USB_DNEG USB USB D Line 06 USB IO USB_DPOS USB USB D Line 08 PWR USB_VDDC USB USB Power Supply Core 1 5 V T07 PWR USB_VDDIO USB USB Power Supply IO 3 3 V Table 7 netX 52 Pinning netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 3 2 Alternative Function at Host Interface 22 56 Alt
64. software and use an internal multiplexer to change the Host Interface signals There fore the signals are fixed and can not move to other pins The SPI slave works as Serial Port Memory means it can be read and write the internal Dual Port Memory without interfering the internal ARM CPU The Ethernet signals emulate a PHY with a MII Interface in the way that every CPU with an integrated MAC can be used for data transfer netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 Package Pinning Pad Cells 30 56 3 3 1 7 MMIO Ball Pos Signal Pad Type MUX Func1 MUX Func2 MUX Func3 netX Netx netX netX netX netX 50 51 52 50 51 52 50 51 52 50 51 52 50 51 52 50 51 52 H1 H2 MMIOO IODS6 FO0 RD J1 K2 MMIO1 IODS6 XMO TX XMO TX ECLK TD J2 J2 MMIO2 IODS6 XMO ECLK FBO CLK 0 EN L2 L3 MMIO3 IODS6 FO1_RD K2 11 MMIO4 IODS6 XM1_TX XM1_TX_ECLK FO1_TD Ki M1 MMIO5 IODS6 XM1_ECLK FB1_CLK FO1_EN 11 M2 MMIO6 IODS6 FBO_CLK FOO_SD M2 N1 MMIO7 IODS6 FB1_CLK FO1_SD M1 N2 MMIO8 IODS6 MII_RXCLK N1 P2 9 IODS6 RXDO N2 R1 MMIO10 IODS6 MII_RXD1 P1 T1 MMIO 1 1 IODS6 MII RXD2 R1 R2 MMIO12 IODS6 MII_RXD3 U1 U2 MMIO13 IODS6 MII_RXDV T1 T2 MMIO14 IODS6 RXER V1 R3 MMIO15 IODS6 TXCLK U2 MMIO16
65. udes the plastic housing and the connection from the die to the outer pins This is the pinning It determines which signals from the die are routed to a pin on the surface of the package Note that not all signals from the die must be connected to a pin A pinning can leave some of the signals unconnected The netX 51 and netX 52 share the same die but the netX 52 have less bond wires and less pins to the pins to fit in a smaller housing and reduce the component costs For netX 51 and netX 52 the firmware must be updated in any case The netX 51 provides all signals from the die The pinning is identical to the netX 50 and the chip can be placed instead of a netX 50 on the PCB For some special application it is necessary to enlarge the size of the Dual Port Memory up to 256 KByte One Power pad and one Ground pad of the netX 50 is used as additional address lines A16 and 17 For safety reason this has to be activated by a pull up resistor of 10 kOhm at MEM A18 or MEM 19 according the following table MEM 18 10 kOhm to activate 16 and 17 in netX 51 designs MEM 19 10 kOhm to activate 16 and 17 in netX 52 designs These two bits can be read out of Bit 10 and Bit 11 of the netX Version register to determine if the netX is running as netX 51 or netX 52 designs In case of netX 52 mode the USB Device ID changes from 0x18 to 0x19 netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revis
66. w netX 51 includes improvement for Sercos 3 DIVCLK generation IO Link Channels 8 Version 1 0 only Channels 8 Version V1 0 1 1 Datalink Layer realized via xPIC SPI SPIO SPIO Master and Slave Master only SPI or QSPI no Quad support Quad Support used for XiP SPI1 SPI1 Master and Slave Master and Slave no Quad support no Quad support 2 One 2 module only Two 2 modules Multiplexable to different MMIO pins mode for I2C pins UART O 2 No differences USB Host and Device Device only USB2JTAG integrated Note Completely new core not register compatible CAN Controller SJA1000 compatible Pelican Mode only no Basic CAN mode Ethernet MAC MII Interface Supports 10 100 Mbit FD HD MAC Mode connect to ext PHY PHY Mode direct connection to Host via MII w o ext PHY Datalink Layer realized via xPIC Multiplexed to MMIO and HIF pins netX 50 to netX 51 52 Migration Guide DOC120109MGO5EN Revision 5 English 2013 08 Released Public 2012 2013 General Changing 37 56 Peripheral netX 50 netX 51 52 Internal Dual PHY No differences New netX 51 PHY with optimized latency round trip latency 230ns MIIMU MDIO 1 MDIO interface for both internal PHYs Separate MDIO interfaces for internal and external PHYs CRC unit No differences Watchdog No differences CCD

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